drivers/net/e1000/base/e1000_ich8lan.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 /* 82562G 10/100 Network Connection
   6  * 82562G-2 10/100 Network Connection
   7  * 82562GT 10/100 Network Connection
   8  * 82562GT-2 10/100 Network Connection
   9  * 82562V 10/100 Network Connection
  10  * 82562V-2 10/100 Network Connection
  11  * 82566DC-2 Gigabit Network Connection
  12  * 82566DC Gigabit Network Connection
  13  * 82566DM-2 Gigabit Network Connection
  14  * 82566DM Gigabit Network Connection
  15  * 82566MC Gigabit Network Connection
  16  * 82566MM Gigabit Network Connection
  17  * 82567LM Gigabit Network Connection
  18  * 82567LF Gigabit Network Connection
  19  * 82567V Gigabit Network Connection
  20  * 82567LM-2 Gigabit Network Connection
  21  * 82567LF-2 Gigabit Network Connection
  22  * 82567V-2 Gigabit Network Connection
  23  * 82567LF-3 Gigabit Network Connection
  24  * 82567LM-3 Gigabit Network Connection
  25  * 82567LM-4 Gigabit Network Connection
  26  * 82577LM Gigabit Network Connection
  27  * 82577LC Gigabit Network Connection
  28  * 82578DM Gigabit Network Connection
  29  * 82578DC Gigabit Network Connection
  30  * 82579LM Gigabit Network Connection
  31  * 82579V Gigabit Network Connection
  32  * Ethernet Connection I217-LM
  33  * Ethernet Connection I217-V
  34  * Ethernet Connection I218-V
  35  * Ethernet Connection I218-LM
  36  * Ethernet Connection (2) I218-LM
  37  * Ethernet Connection (2) I218-V
  38  * Ethernet Connection (3) I218-LM
  39  * Ethernet Connection (3) I218-V
  40  */
  41
  42 #include "e1000_api.h"
  43
  44 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
  45 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  46 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  47 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  48 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  49 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  50 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  51 STATIC int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  52 STATIC int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  53 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  54 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
  55 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  56                                               u8 *mc_addr_list,
  57                                               u32 mc_addr_count);
  58 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
  59 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  60 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  61 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  62 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  63                                             bool active);
  64 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  65                                             bool active);
  66 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  67                                    u16 words, u16 *data);
  68 STATIC s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
  69                                u16 *data);
  70 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  71                                     u16 words, u16 *data);
  72 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  73 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  74 STATIC s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
  75 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
  76                                             u16 *data);
  77 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
  78 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
  79 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
  80 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
  81 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
  82 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
  83 STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
  84 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
  85                                            u16 *speed, u16 *duplex);
  86 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
  87 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
  88 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
  89 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
  90 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
  91 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
  92 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
  93 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
  94 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  95 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
  96 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
  97 STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
  98 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
  99                                           u32 offset, u8 *data);
 100 STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 101                                           u8 size, u16 *data);
 102 STATIC s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 103                                             u32 *data);
 104 STATIC s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 105                                            u32 offset, u32 *data);
 106 STATIC s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 107                                              u32 offset, u32 data);
 108 STATIC s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 109                                                   u32 offset, u32 dword);
 110 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 111                                           u32 offset, u16 *data);
 112 STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 113                                                  u32 offset, u8 byte);
 114 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 115 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 116 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 117 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 118 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 119 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 120
 121 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 122 /* Offset 04h HSFSTS */
 123 union ich8_hws_flash_status {
 124         struct ich8_hsfsts {
 125                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 126                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 127                 u16 dael:1; /* bit 2 Direct Access error Log */
 128                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 129                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 130                 u16 reserved1:2; /* bit 13:6 Reserved */
 131                 u16 reserved2:6; /* bit 13:6 Reserved */
 132                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 133                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 134         } hsf_status;
 135         u16 regval;
 136 };
 137
 138 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 139 /* Offset 06h FLCTL */
 140 union ich8_hws_flash_ctrl {
 141         struct ich8_hsflctl {
 142                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 143                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 144                 u16 reserved:5;   /* 7:3 Reserved  */
 145                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 146                 u16 flockdn:6;   /* 15:10 Reserved */
 147         } hsf_ctrl;
 148         u16 regval;
 149 };
 150
 151 /* ICH Flash Region Access Permissions */
 152 union ich8_hws_flash_regacc {
 153         struct ich8_flracc {
 154                 u32 grra:8; /* 0:7 GbE region Read Access */
 155                 u32 grwa:8; /* 8:15 GbE region Write Access */
 156                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 157                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 158         } hsf_flregacc;
 159         u16 regval;
 160 };
 161
 162 /**
 163  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 164  *  @hw: pointer to the HW structure
 165  *
 166  *  Test access to the PHY registers by reading the PHY ID registers.  If
 167  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 168  *  otherwise assume the read PHY ID is correct if it is valid.
 169  *
 170  *  Assumes the sw/fw/hw semaphore is already acquired.
 171  **/
 172 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 173 {
 174         u16 phy_reg = 0;
 175         u32 phy_id = 0;
 176         s32 ret_val = 0;
 177         u16 retry_count;
 178         u32 mac_reg = 0;
 179
 180         for (retry_count = 0; retry_count < 2; retry_count++) {
 181                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 182                 if (ret_val || (phy_reg == 0xFFFF))
 183                         continue;
 184                 phy_id = (u32)(phy_reg << 16);
 185
 186                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 187                 if (ret_val || (phy_reg == 0xFFFF)) {
 188                         phy_id = 0;
 189                         continue;
 190                 }
 191                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 192                 break;
 193         }
 194
 195         if (hw->phy.id) {
 196                 if  (hw->phy.id == phy_id)
 197                         goto out;
 198         } else if (phy_id) {
 199                 hw->phy.id = phy_id;
 200                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 201                 goto out;
 202         }
 203
 204         /* In case the PHY needs to be in mdio slow mode,
 205          * set slow mode and try to get the PHY id again.
 206          */
 207         if (hw->mac.type < e1000_pch_lpt) {
 208                 hw->phy.ops.release(hw);
 209                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 210                 if (!ret_val)
 211                         ret_val = e1000_get_phy_id(hw);
 212                 hw->phy.ops.acquire(hw);
 213         }
 214
 215         if (ret_val)
 216                 return false;
 217 out:
 218         if (hw->mac.type >= e1000_pch_lpt) {
 219                 /* Only unforce SMBus if ME is not active */
 220                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
 221                     E1000_ICH_FWSM_FW_VALID)) {
 222                         /* Unforce SMBus mode in PHY */
 223                         hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 224                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 225                         hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 226
 227                         /* Unforce SMBus mode in MAC */
 228                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 229                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 230                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 231                 }
 232         }
 233
 234         return true;
 235 }
 236
 237 /**
 238  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 239  *  @hw: pointer to the HW structure
 240  *
 241  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 242  *  used to reset the PHY to a quiescent state when necessary.
 243  **/
 244 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 245 {
 246         u32 mac_reg;
 247
 248         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 249
 250         /* Set Phy Config Counter to 50msec */
 251         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 252         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 253         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 254         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 255
 256         /* Toggle LANPHYPC Value bit */
 257         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 258         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 259         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 260         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 261         E1000_WRITE_FLUSH(hw);
 262         msec_delay(1);
 263         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 264         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 265         E1000_WRITE_FLUSH(hw);
 266
 267         if (hw->mac.type < e1000_pch_lpt) {
 268                 msec_delay(50);
 269         } else {
 270                 u16 count = 20;
 271
 272                 do {
 273                         msec_delay(5);
 274                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 275                            E1000_CTRL_EXT_LPCD) && count--);
 276
 277                 msec_delay(30);
 278         }
 279 }
 280
 281 /**
 282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  Workarounds/flow necessary for PHY initialization during driver load
 286  *  and resume paths.
 287  **/
 288 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 289 {
 290         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 291         s32 ret_val;
 292
 293         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 294
 295         /* Gate automatic PHY configuration by hardware on managed and
 296          * non-managed 82579 and newer adapters.
 297          */
 298         e1000_gate_hw_phy_config_ich8lan(hw, true);
 299
 300 #ifdef ULP_SUPPORT
 301         /* It is not possible to be certain of the current state of ULP
 302          * so forcibly disable it.
 303          */
 304         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 305
 306 #endif /* ULP_SUPPORT */
 307         ret_val = hw->phy.ops.acquire(hw);
 308         if (ret_val) {
 309                 DEBUGOUT("Failed to initialize PHY flow\n");
 310                 goto out;
 311         }
 312
 313         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 314          * inaccessible and resetting the PHY is not blocked, toggle the
 315          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 316          */
 317         switch (hw->mac.type) {
 318         case e1000_pch_lpt:
 319         case e1000_pch_spt:
 320         case e1000_pch_cnp:
 321                 if (e1000_phy_is_accessible_pchlan(hw))
 322                         break;
 323
 324                 /* Before toggling LANPHYPC, see if PHY is accessible by
 325                  * forcing MAC to SMBus mode first.
 326                  */
 327                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 328                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 329                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 330
 331                 /* Wait 50 milliseconds for MAC to finish any retries
 332                  * that it might be trying to perform from previous
 333                  * attempts to acknowledge any phy read requests.
 334                  */
 335                  msec_delay(50);
 336
 337                 /* fall-through */
 338         case e1000_pch2lan:
 339                 if (e1000_phy_is_accessible_pchlan(hw))
 340                         break;
 341
 342                 /* fall-through */
 343         case e1000_pchlan:
 344                 if ((hw->mac.type == e1000_pchlan) &&
 345                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 346                         break;
 347
 348                 if (hw->phy.ops.check_reset_block(hw)) {
 349                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 350                         ret_val = -E1000_ERR_PHY;
 351                         break;
 352                 }
 353
 354                 /* Toggle LANPHYPC Value bit */
 355                 e1000_toggle_lanphypc_pch_lpt(hw);
 356                 if (hw->mac.type >= e1000_pch_lpt) {
 357                         if (e1000_phy_is_accessible_pchlan(hw))
 358                                 break;
 359
 360                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 361                          * so ensure that the MAC is also out of SMBus mode
 362                          */
 363                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 364                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 365                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 366
 367                         if (e1000_phy_is_accessible_pchlan(hw))
 368                                 break;
 369
 370                         ret_val = -E1000_ERR_PHY;
 371                 }
 372                 break;
 373         default:
 374                 break;
 375         }
 376
 377         hw->phy.ops.release(hw);
 378         if (!ret_val) {
 379
 380                 /* Check to see if able to reset PHY.  Print error if not */
 381                 if (hw->phy.ops.check_reset_block(hw)) {
 382                         ERROR_REPORT("Reset blocked by ME\n");
 383                         goto out;
 384                 }
 385
 386                 /* Reset the PHY before any access to it.  Doing so, ensures
 387                  * that the PHY is in a known good state before we read/write
 388                  * PHY registers.  The generic reset is sufficient here,
 389                  * because we haven't determined the PHY type yet.
 390                  */
 391                 ret_val = e1000_phy_hw_reset_generic(hw);
 392                 if (ret_val)
 393                         goto out;
 394
 395                 /* On a successful reset, possibly need to wait for the PHY
 396                  * to quiesce to an accessible state before returning control
 397                  * to the calling function.  If the PHY does not quiesce, then
 398                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 399                  *  the PHY is in.
 400                  */
 401                 ret_val = hw->phy.ops.check_reset_block(hw);
 402                 if (ret_val)
 403                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 404         }
 405
 406 out:
 407         /* Ungate automatic PHY configuration on non-managed 82579 */
 408         if ((hw->mac.type == e1000_pch2lan) &&
 409             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 410                 msec_delay(10);
 411                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 412         }
 413
 414         return ret_val;
 415 }
 416
 417 /**
 418  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 419  *  @hw: pointer to the HW structure
 420  *
 421  *  Initialize family-specific PHY parameters and function pointers.
 422  **/
 423 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 424 {
 425         struct e1000_phy_info *phy = &hw->phy;
 426         s32 ret_val;
 427
 428         DEBUGFUNC("e1000_init_phy_params_pchlan");
 429
 430         phy->addr               = 1;
 431         phy->reset_delay_us     = 100;
 432
 433         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 434         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 435         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 436         phy->ops.set_page       = e1000_set_page_igp;
 437         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 438         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 439         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 440         phy->ops.release        = e1000_release_swflag_ich8lan;
 441         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 442         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 443         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 444         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 445         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 446         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 447         phy->ops.power_up       = e1000_power_up_phy_copper;
 448         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 449         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 450
 451         phy->id = e1000_phy_unknown;
 452
 453         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 454         if (ret_val)
 455                 return ret_val;
 456
 457         if (phy->id == e1000_phy_unknown)
 458                 switch (hw->mac.type) {
 459                 default:
 460                         ret_val = e1000_get_phy_id(hw);
 461                         if (ret_val)
 462                                 return ret_val;
 463                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 464                                 break;
 465                         /* fall-through */
 466                 case e1000_pch2lan:
 467                 case e1000_pch_lpt:
 468                 case e1000_pch_spt:
 469                 case e1000_pch_cnp:
 470                         /* In case the PHY needs to be in mdio slow mode,
 471                          * set slow mode and try to get the PHY id again.
 472                          */
 473                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 474                         if (ret_val)
 475                                 return ret_val;
 476                         ret_val = e1000_get_phy_id(hw);
 477                         if (ret_val)
 478                                 return ret_val;
 479                         break;
 480                 }
 481         phy->type = e1000_get_phy_type_from_id(phy->id);
 482
 483         switch (phy->type) {
 484         case e1000_phy_82577:
 485         case e1000_phy_82579:
 486         case e1000_phy_i217:
 487                 phy->ops.check_polarity = e1000_check_polarity_82577;
 488                 phy->ops.force_speed_duplex =
 489                         e1000_phy_force_speed_duplex_82577;
 490                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 491                 phy->ops.get_info = e1000_get_phy_info_82577;
 492                 phy->ops.commit = e1000_phy_sw_reset_generic;
 493                 break;
 494         case e1000_phy_82578:
 495                 phy->ops.check_polarity = e1000_check_polarity_m88;
 496                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 497                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 498                 phy->ops.get_info = e1000_get_phy_info_m88;
 499                 break;
 500         default:
 501                 ret_val = -E1000_ERR_PHY;
 502                 break;
 503         }
 504
 505         return ret_val;
 506 }
 507
 508 /**
 509  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 510  *  @hw: pointer to the HW structure
 511  *
 512  *  Initialize family-specific PHY parameters and function pointers.
 513  **/
 514 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 515 {
 516         struct e1000_phy_info *phy = &hw->phy;
 517         s32 ret_val;
 518         u16 i = 0;
 519
 520         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 521
 522         phy->addr               = 1;
 523         phy->reset_delay_us     = 100;
 524
 525         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 526         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 527         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 528         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 529         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 530         phy->ops.release        = e1000_release_swflag_ich8lan;
 531         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 532         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 533         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 534         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 535         phy->ops.power_up       = e1000_power_up_phy_copper;
 536         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 537
 538         /* We may need to do this twice - once for IGP and if that fails,
 539          * we'll set BM func pointers and try again
 540          */
 541         ret_val = e1000_determine_phy_address(hw);
 542         if (ret_val) {
 543                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 544                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 545                 ret_val = e1000_determine_phy_address(hw);
 546                 if (ret_val) {
 547                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 548                         return ret_val;
 549                 }
 550         }
 551
 552         phy->id = 0;
 553         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 554                (i++ < 100)) {
 555                 msec_delay(1);
 556                 ret_val = e1000_get_phy_id(hw);
 557                 if (ret_val)
 558                         return ret_val;
 559         }
 560
 561         /* Verify phy id */
 562         switch (phy->id) {
 563         case IGP03E1000_E_PHY_ID:
 564                 phy->type = e1000_phy_igp_3;
 565                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 566                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 567                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 568                 phy->ops.get_info = e1000_get_phy_info_igp;
 569                 phy->ops.check_polarity = e1000_check_polarity_igp;
 570                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 571                 break;
 572         case IFE_E_PHY_ID:
 573         case IFE_PLUS_E_PHY_ID:
 574         case IFE_C_E_PHY_ID:
 575                 phy->type = e1000_phy_ife;
 576                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 577                 phy->ops.get_info = e1000_get_phy_info_ife;
 578                 phy->ops.check_polarity = e1000_check_polarity_ife;
 579                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 580                 break;
 581         case BME1000_E_PHY_ID:
 582                 phy->type = e1000_phy_bm;
 583                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 584                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 585                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 586                 phy->ops.commit = e1000_phy_sw_reset_generic;
 587                 phy->ops.get_info = e1000_get_phy_info_m88;
 588                 phy->ops.check_polarity = e1000_check_polarity_m88;
 589                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 590                 break;
 591         default:
 592                 return -E1000_ERR_PHY;
 593                 break;
 594         }
 595
 596         return E1000_SUCCESS;
 597 }
 598
 599 /**
 600  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 601  *  @hw: pointer to the HW structure
 602  *
 603  *  Initialize family-specific NVM parameters and function
 604  *  pointers.
 605  **/
 606 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 607 {
 608         struct e1000_nvm_info *nvm = &hw->nvm;
 609         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 610         u32 gfpreg, sector_base_addr, sector_end_addr;
 611         u16 i;
 612         u32 nvm_size;
 613
 614         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 615
 616         nvm->type = e1000_nvm_flash_sw;
 617
 618         if (hw->mac.type >= e1000_pch_spt) {
 619                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 620                  * STRAP register. This is because in SPT the GbE Flash region
 621                  * is no longer accessed through the flash registers. Instead,
 622                  * the mechanism has changed, and the Flash region access
 623                  * registers are now implemented in GbE memory space.
 624                  */
 625                 nvm->flash_base_addr = 0;
 626                 nvm_size =
 627                     (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
 628                     * NVM_SIZE_MULTIPLIER;
 629                 nvm->flash_bank_size = nvm_size / 2;
 630                 /* Adjust to word count */
 631                 nvm->flash_bank_size /= sizeof(u16);
 632                 /* Set the base address for flash register access */
 633                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 634         } else {
 635                 /* Can't read flash registers if register set isn't mapped. */
 636                 if (!hw->flash_address) {
 637                         DEBUGOUT("ERROR: Flash registers not mapped\n");
 638                         return -E1000_ERR_CONFIG;
 639                 }
 640
 641                 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 642
 643                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 644                  * Add 1 to sector_end_addr since this sector is included in
 645                  * the overall size.
 646                  */
 647                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 648                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 649
 650                 /* flash_base_addr is byte-aligned */
 651                 nvm->flash_base_addr = sector_base_addr
 652                                        << FLASH_SECTOR_ADDR_SHIFT;
 653
 654                 /* find total size of the NVM, then cut in half since the total
 655                  * size represents two separate NVM banks.
 656                  */
 657                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 658                                         << FLASH_SECTOR_ADDR_SHIFT);
 659                 nvm->flash_bank_size /= 2;
 660                 /* Adjust to word count */
 661                 nvm->flash_bank_size /= sizeof(u16);
 662         }
 663
 664         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 665
 666         /* Clear shadow ram */
 667         for (i = 0; i < nvm->word_size; i++) {
 668                 dev_spec->shadow_ram[i].modified = false;
 669                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 670         }
 671
 672         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 673         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 674
 675         /* Function Pointers */
 676         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 677         nvm->ops.release        = e1000_release_nvm_ich8lan;
 678         if (hw->mac.type >= e1000_pch_spt) {
 679                 nvm->ops.read   = e1000_read_nvm_spt;
 680                 nvm->ops.update = e1000_update_nvm_checksum_spt;
 681         } else {
 682                 nvm->ops.read   = e1000_read_nvm_ich8lan;
 683                 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
 684         }
 685         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 686         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 687         nvm->ops.write          = e1000_write_nvm_ich8lan;
 688
 689         return E1000_SUCCESS;
 690 }
 691
 692 /**
 693  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 694  *  @hw: pointer to the HW structure
 695  *
 696  *  Initialize family-specific MAC parameters and function
 697  *  pointers.
 698  **/
 699 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 700 {
 701         struct e1000_mac_info *mac = &hw->mac;
 702 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 703         u16 pci_cfg;
 704 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 705
 706         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 707
 708         /* Set media type function pointer */
 709         hw->phy.media_type = e1000_media_type_copper;
 710
 711         /* Set mta register count */
 712         mac->mta_reg_count = 32;
 713         /* Set rar entry count */
 714         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 715         if (mac->type == e1000_ich8lan)
 716                 mac->rar_entry_count--;
 717         /* Set if part includes ASF firmware */
 718         mac->asf_firmware_present = true;
 719         /* FWSM register */
 720         mac->has_fwsm = true;
 721         /* ARC subsystem not supported */
 722         mac->arc_subsystem_valid = false;
 723         /* Adaptive IFS supported */
 724         mac->adaptive_ifs = true;
 725
 726         /* Function pointers */
 727
 728         /* bus type/speed/width */
 729         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 730         /* function id */
 731         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 732         /* reset */
 733         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 734         /* hw initialization */
 735         mac->ops.init_hw = e1000_init_hw_ich8lan;
 736         /* link setup */
 737         mac->ops.setup_link = e1000_setup_link_ich8lan;
 738         /* physical interface setup */
 739         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 740         /* check for link */
 741         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 742         /* link info */
 743         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 744         /* multicast address update */
 745         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 746         /* clear hardware counters */
 747         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 748
 749         /* LED and other operations */
 750         switch (mac->type) {
 751         case e1000_ich8lan:
 752         case e1000_ich9lan:
 753         case e1000_ich10lan:
 754                 /* check management mode */
 755                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 756                 /* ID LED init */
 757                 mac->ops.id_led_init = e1000_id_led_init_generic;
 758                 /* blink LED */
 759                 mac->ops.blink_led = e1000_blink_led_generic;
 760                 /* setup LED */
 761                 mac->ops.setup_led = e1000_setup_led_generic;
 762                 /* cleanup LED */
 763                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 764                 /* turn on/off LED */
 765                 mac->ops.led_on = e1000_led_on_ich8lan;
 766                 mac->ops.led_off = e1000_led_off_ich8lan;
 767                 break;
 768         case e1000_pch2lan:
 769                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 770                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 771                 /* fall-through */
 772         case e1000_pch_lpt:
 773         case e1000_pch_spt:
 774         case e1000_pch_cnp:
 775 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 776                 /* multicast address update for pch2 */
 777                 mac->ops.update_mc_addr_list =
 778                         e1000_update_mc_addr_list_pch2lan;
 779                 /* fall-through */
 780 #endif
 781         case e1000_pchlan:
 782 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 783                 /* save PCH revision_id */
 784                 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
 785                 /* SPT uses full byte for revision ID,
 786                  * as opposed to previous generations
 787                  */
 788                 if (hw->mac.type >= e1000_pch_spt)
 789                         hw->revision_id = (u8)(pci_cfg &= 0x00FF);
 790                 else
 791                         hw->revision_id = (u8)(pci_cfg &= 0x000F);
 792 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 793                 /* check management mode */
 794                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 795                 /* ID LED init */
 796                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 797                 /* setup LED */
 798                 mac->ops.setup_led = e1000_setup_led_pchlan;
 799                 /* cleanup LED */
 800                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 801                 /* turn on/off LED */
 802                 mac->ops.led_on = e1000_led_on_pchlan;
 803                 mac->ops.led_off = e1000_led_off_pchlan;
 804                 break;
 805         default:
 806                 break;
 807         }
 808
 809         if (mac->type >= e1000_pch_lpt) {
 810                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 811                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 812                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 813         }
 814
 815         /* Enable PCS Lock-loss workaround for ICH8 */
 816         if (mac->type == e1000_ich8lan)
 817                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 818
 819         return E1000_SUCCESS;
 820 }
 821
 822 /**
 823  *  __e1000_access_emi_reg_locked - Read/write EMI register
 824  *  @hw: pointer to the HW structure
 825  *  @address: EMI address to program
 826  *  @data: pointer to value to read/write from/to the EMI address
 827  *  @read: boolean flag to indicate read or write
 828  *
 829  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 830  **/
 831 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 832                                          u16 *data, bool read)
 833 {
 834         s32 ret_val;
 835
 836         DEBUGFUNC("__e1000_access_emi_reg_locked");
 837
 838         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 839         if (ret_val)
 840                 return ret_val;
 841
 842         if (read)
 843                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 844                                                       data);
 845         else
 846                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 847                                                        *data);
 848
 849         return ret_val;
 850 }
 851
 852 /**
 853  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 854  *  @hw: pointer to the HW structure
 855  *  @addr: EMI address to program
 856  *  @data: value to be read from the EMI address
 857  *
 858  *  Assumes the SW/FW/HW Semaphore is already acquired.
 859  **/
 860 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 861 {
 862         DEBUGFUNC("e1000_read_emi_reg_locked");
 863
 864         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 865 }
 866
 867 /**
 868  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 869  *  @hw: pointer to the HW structure
 870  *  @addr: EMI address to program
 871  *  @data: value to be written to the EMI address
 872  *
 873  *  Assumes the SW/FW/HW Semaphore is already acquired.
 874  **/
 875 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 876 {
 877         DEBUGFUNC("e1000_read_emi_reg_locked");
 878
 879         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 880 }
 881
 882 /**
 883  *  e1000_set_eee_pchlan - Enable/disable EEE support
 884  *  @hw: pointer to the HW structure
 885  *
 886  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 887  *  the link and the EEE capabilities of the link partner.  The LPI Control
 888  *  register bits will remain set only if/when link is up.
 889  *
 890  *  EEE LPI must not be asserted earlier than one second after link is up.
 891  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 892  *  can be link issues with some switches.  Other devices can have EEE LPI
 893  *  enabled immediately upon link up since they have a timer in hardware which
 894  *  prevents LPI from being asserted too early.
 895  **/
 896 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 897 {
 898         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 899         s32 ret_val;
 900         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 901
 902         DEBUGFUNC("e1000_set_eee_pchlan");
 903
 904         switch (hw->phy.type) {
 905         case e1000_phy_82579:
 906                 lpa = I82579_EEE_LP_ABILITY;
 907                 pcs_status = I82579_EEE_PCS_STATUS;
 908                 adv_addr = I82579_EEE_ADVERTISEMENT;
 909                 break;
 910         case e1000_phy_i217:
 911                 lpa = I217_EEE_LP_ABILITY;
 912                 pcs_status = I217_EEE_PCS_STATUS;
 913                 adv_addr = I217_EEE_ADVERTISEMENT;
 914                 break;
 915         default:
 916                 return E1000_SUCCESS;
 917         }
 918
 919         ret_val = hw->phy.ops.acquire(hw);
 920         if (ret_val)
 921                 return ret_val;
 922
 923         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 924         if (ret_val)
 925                 goto release;
 926
 927         /* Clear bits that enable EEE in various speeds */
 928         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 929
 930         /* Enable EEE if not disabled by user */
 931         if (!dev_spec->eee_disable) {
 932                 /* Save off link partner's EEE ability */
 933                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 934                                                     &dev_spec->eee_lp_ability);
 935                 if (ret_val)
 936                         goto release;
 937
 938                 /* Read EEE advertisement */
 939                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 940                 if (ret_val)
 941                         goto release;
 942
 943                 /* Enable EEE only for speeds in which the link partner is
 944                  * EEE capable and for which we advertise EEE.
 945                  */
 946                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 947                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 948
 949                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 950                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 951                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 952                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 953                         else
 954                                 /* EEE is not supported in 100Half, so ignore
 955                                  * partner's EEE in 100 ability if full-duplex
 956                                  * is not advertised.
 957                                  */
 958                                 dev_spec->eee_lp_ability &=
 959                                     ~I82579_EEE_100_SUPPORTED;
 960                 }
 961         }
 962
 963         if (hw->phy.type == e1000_phy_82579) {
 964                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 965                                                     &data);
 966                 if (ret_val)
 967                         goto release;
 968
 969                 data &= ~I82579_LPI_100_PLL_SHUT;
 970                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 971                                                      data);
 972         }
 973
 974         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 975         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 976         if (ret_val)
 977                 goto release;
 978
 979         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 980 release:
 981         hw->phy.ops.release(hw);
 982
 983         return ret_val;
 984 }
 985
 986 /**
 987  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 988  *  @hw:   pointer to the HW structure
 989  *  @link: link up bool flag
 990  *
 991  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 992  *  preventing further DMA write requests.  Workaround the issue by disabling
 993  *  the de-assertion of the clock request when in 1Gpbs mode.
 994  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 995  *  speeds in order to avoid Tx hangs.
 996  **/
 997 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 998 {
 999         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1000         u32 status = E1000_READ_REG(hw, E1000_STATUS);
1001         s32 ret_val = E1000_SUCCESS;
1002         u16 reg;
1003
1004         if (link && (status & E1000_STATUS_SPEED_1000)) {
1005                 ret_val = hw->phy.ops.acquire(hw);
1006                 if (ret_val)
1007                         return ret_val;
1008
1009                 ret_val =
1010                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1011                                                &reg);
1012                 if (ret_val)
1013                         goto release;
1014
1015                 ret_val =
1016                     e1000_write_kmrn_reg_locked(hw,
1017                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1018                                                 reg &
1019                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1020                 if (ret_val)
1021                         goto release;
1022
1023                 usec_delay(10);
1024
1025                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1026                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1027
1028                 ret_val =
1029                     e1000_write_kmrn_reg_locked(hw,
1030                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1031                                                 reg);
1032 release:
1033                 hw->phy.ops.release(hw);
1034         } else {
1035                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1036                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1037
1038                 if ((hw->phy.revision > 5) || !link ||
1039                     ((status & E1000_STATUS_SPEED_100) &&
1040                      (status & E1000_STATUS_FD)))
1041                         goto update_fextnvm6;
1042
1043                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1044                 if (ret_val)
1045                         return ret_val;
1046
1047                 /* Clear link status transmit timeout */
1048                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1049
1050                 if (status & E1000_STATUS_SPEED_100) {
1051                         /* Set inband Tx timeout to 5x10us for 100Half */
1052                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1053
1054                         /* Do not extend the K1 entry latency for 100Half */
1055                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1056                 } else {
1057                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1058                         reg |= 50 <<
1059                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1060
1061                         /* Extend the K1 entry latency for 10 Mbps */
1062                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1063                 }
1064
1065                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1066                 if (ret_val)
1067                         return ret_val;
1068
1069 update_fextnvm6:
1070                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1071         }
1072
1073         return ret_val;
1074 }
1075
1076 #ifdef ULP_SUPPORT
1077 /**
1078  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1079  *  @hw: pointer to the HW structure
1080  *  @to_sx: boolean indicating a system power state transition to Sx
1081  *
1082  *  When link is down, configure ULP mode to significantly reduce the power
1083  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1084  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1085  *  system, configure the ULP mode by software.
1086  */
1087 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1088 {
1089         u32 mac_reg;
1090         s32 ret_val = E1000_SUCCESS;
1091         u16 phy_reg;
1092         u16 oem_reg = 0;
1093
1094         if ((hw->mac.type < e1000_pch_lpt) ||
1095             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1096             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1097             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1098             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1099             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1100                 return 0;
1101
1102         if (!to_sx) {
1103                 int i = 0;
1104                 /* Poll up to 5 seconds for Cable Disconnected indication */
1105                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1106                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1107                         /* Bail if link is re-acquired */
1108                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1109                                 return -E1000_ERR_PHY;
1110                         if (i++ == 100)
1111                                 break;
1112
1113                         msec_delay(50);
1114                 }
1115                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1116                           (E1000_READ_REG(hw, E1000_FEXT) &
1117                            E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1118                           i * 50);
1119                 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1120                     E1000_FEXT_PHY_CABLE_DISCONNECTED))
1121                         return 0;
1122         }
1123
1124         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1125                 /* Request ME configure ULP mode in the PHY */
1126                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1127                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1128                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1129
1130                 goto out;
1131         }
1132
1133         ret_val = hw->phy.ops.acquire(hw);
1134         if (ret_val)
1135                 goto out;
1136
1137         /* During S0 Idle keep the phy in PCI-E mode */
1138         if (hw->dev_spec.ich8lan.smbus_disable)
1139                 goto skip_smbus;
1140
1141         /* Force SMBus mode in PHY */
1142         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1143         if (ret_val)
1144                 goto release;
1145         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1146         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1147
1148         /* Force SMBus mode in MAC */
1149         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1150         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1151         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1152
1153         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1154          * LPLU and disable Gig speed when entering ULP
1155          */
1156         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1157                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1158                                                        &oem_reg);
1159                 if (ret_val)
1160                         goto release;
1161
1162                 phy_reg = oem_reg;
1163                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1164
1165                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1166                                                         phy_reg);
1167
1168                 if (ret_val)
1169                         goto release;
1170         }
1171
1172 skip_smbus:
1173         if (!to_sx) {
1174                 /* Change the 'Link Status Change' interrupt to trigger
1175                  * on 'Cable Status Change'
1176                  */
1177                 ret_val = e1000_read_kmrn_reg_locked(hw,
1178                                                      E1000_KMRNCTRLSTA_OP_MODES,
1179                                                      &phy_reg);
1180                 if (ret_val)
1181                         goto release;
1182                 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1183                 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1184                                             phy_reg);
1185         }
1186
1187         /* Set Inband ULP Exit, Reset to SMBus mode and
1188          * Disable SMBus Release on PERST# in PHY
1189          */
1190         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1191         if (ret_val)
1192                 goto release;
1193         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1194                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1195         if (to_sx) {
1196                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1197                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1198                 else
1199                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1200
1201                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1202                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1203         } else {
1204                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1205                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1206                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1207         }
1208         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1209
1210         /* Set Disable SMBus Release on PERST# in MAC */
1211         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1212         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1213         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1214
1215         /* Commit ULP changes in PHY by starting auto ULP configuration */
1216         phy_reg |= I218_ULP_CONFIG1_START;
1217         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1218
1219         if (!to_sx) {
1220                 /* Disable Tx so that the MAC doesn't send any (buffered)
1221                  * packets to the PHY.
1222                  */
1223                 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1224                 mac_reg &= ~E1000_TCTL_EN;
1225                 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1226         }
1227
1228         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1229             to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1230                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1231                                                         oem_reg);
1232                 if (ret_val)
1233                         goto release;
1234         }
1235
1236 release:
1237         hw->phy.ops.release(hw);
1238 out:
1239         if (ret_val)
1240                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1241         else
1242                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1243
1244         return ret_val;
1245 }
1246
1247 /**
1248  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1249  *  @hw: pointer to the HW structure
1250  *  @force: boolean indicating whether or not to force disabling ULP
1251  *
1252  *  Un-configure ULP mode when link is up, the system is transitioned from
1253  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1254  *  system, poll for an indication from ME that ULP has been un-configured.
1255  *  If not on an ME enabled system, un-configure the ULP mode by software.
1256  *
1257  *  During nominal operation, this function is called when link is acquired
1258  *  to disable ULP mode (force=false); otherwise, for example when unloading
1259  *  the driver or during Sx->S0 transitions, this is called with force=true
1260  *  to forcibly disable ULP.
1261
1262  *  When the cable is plugged in while the device is in D0, a Cable Status
1263  *  Change interrupt is generated which causes this function to be called
1264  *  to partially disable ULP mode and restart autonegotiation.  This function
1265  *  is then called again due to the resulting Link Status Change interrupt
1266  *  to finish cleaning up after the ULP flow.
1267  */
1268 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1269 {
1270         s32 ret_val = E1000_SUCCESS;
1271         u32 mac_reg;
1272         u16 phy_reg;
1273         int i = 0;
1274
1275         if ((hw->mac.type < e1000_pch_lpt) ||
1276             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1277             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1278             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1279             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1280             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1281                 return 0;
1282
1283         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1284                 if (force) {
1285                         /* Request ME un-configure ULP mode in the PHY */
1286                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1287                         mac_reg &= ~E1000_H2ME_ULP;
1288                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1289                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1290                 }
1291
1292                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1293                 while (E1000_READ_REG(hw, E1000_FWSM) &
1294                        E1000_FWSM_ULP_CFG_DONE) {
1295                         if (i++ == 30) {
1296                                 ret_val = -E1000_ERR_PHY;
1297                                 goto out;
1298                         }
1299
1300                         msec_delay(10);
1301                 }
1302                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1303
1304                 if (force) {
1305                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1306                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1307                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1308                 } else {
1309                         /* Clear H2ME.ULP after ME ULP configuration */
1310                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1311                         mac_reg &= ~E1000_H2ME_ULP;
1312                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1313
1314                         /* Restore link speed advertisements and restart
1315                          * Auto-negotiation
1316                          */
1317                         if (hw->mac.autoneg) {
1318                                 ret_val = e1000_phy_setup_autoneg(hw);
1319                                 if (ret_val)
1320                                         goto out;
1321                         } else {
1322                                 ret_val = e1000_setup_copper_link_generic(hw);
1323                                 if (ret_val)
1324                                         goto out;
1325                         }
1326                         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1327                 }
1328
1329                 goto out;
1330         }
1331
1332         ret_val = hw->phy.ops.acquire(hw);
1333         if (ret_val)
1334                 goto out;
1335
1336         /* Revert the change to the 'Link Status Change'
1337          * interrupt to trigger on 'Cable Status Change'
1338          */
1339         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1340                                              &phy_reg);
1341         if (ret_val)
1342                 goto release;
1343         phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1344         e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1345
1346         if (force)
1347                 /* Toggle LANPHYPC Value bit */
1348                 e1000_toggle_lanphypc_pch_lpt(hw);
1349
1350         /* Unforce SMBus mode in PHY */
1351         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1352         if (ret_val) {
1353                 /* The MAC might be in PCIe mode, so temporarily force to
1354                  * SMBus mode in order to access the PHY.
1355                  */
1356                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1357                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1358                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1359
1360                 msec_delay(50);
1361
1362                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1363                                                        &phy_reg);
1364                 if (ret_val)
1365                         goto release;
1366         }
1367         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1368         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1369
1370         /* Unforce SMBus mode in MAC */
1371         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1372         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1373         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1374
1375         /* When ULP mode was previously entered, K1 was disabled by the
1376          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1377          */
1378         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1379         if (ret_val)
1380                 goto release;
1381         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1382         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1383
1384         /* Clear ULP enabled configuration */
1385         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1386         if (ret_val)
1387                 goto release;
1388         /* CSC interrupt received due to ULP Indication */
1389         if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1390                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1391                              I218_ULP_CONFIG1_STICKY_ULP |
1392                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1393                              I218_ULP_CONFIG1_WOL_HOST |
1394                              I218_ULP_CONFIG1_INBAND_EXIT |
1395                              I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1396                              I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1397                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1398                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1399
1400                 /* Commit ULP changes by starting auto ULP configuration */
1401                 phy_reg |= I218_ULP_CONFIG1_START;
1402                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1403
1404                 /* Clear Disable SMBus Release on PERST# in MAC */
1405                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1406                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1407                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1408
1409                 if (!force) {
1410                         hw->phy.ops.release(hw);
1411
1412                         if (hw->mac.autoneg)
1413                                 e1000_phy_setup_autoneg(hw);
1414                         else
1415                                 e1000_setup_copper_link_generic(hw);
1416
1417                         e1000_sw_lcd_config_ich8lan(hw);
1418
1419                         e1000_oem_bits_config_ich8lan(hw, true);
1420
1421                         /* Set ULP state to unknown and return non-zero to
1422                          * indicate no link (yet) and re-enter on the next LSC
1423                          * to finish disabling ULP flow.
1424                          */
1425                         hw->dev_spec.ich8lan.ulp_state =
1426                             e1000_ulp_state_unknown;
1427
1428                         return 1;
1429                 }
1430         }
1431
1432         /* Re-enable Tx */
1433         mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1434         mac_reg |= E1000_TCTL_EN;
1435         E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1436
1437 release:
1438         hw->phy.ops.release(hw);
1439         if (force) {
1440                 hw->phy.ops.reset(hw);
1441                 msec_delay(50);
1442         }
1443 out:
1444         if (ret_val)
1445                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1446         else
1447                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1448
1449         return ret_val;
1450 }
1451
1452 #endif /* ULP_SUPPORT */
1453
1454
1455 /**
1456  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1457  *  @hw: pointer to the HW structure
1458  *
1459  *  Checks to see of the link status of the hardware has changed.  If a
1460  *  change in link status has been detected, then we read the PHY registers
1461  *  to get the current speed/duplex if link exists.
1462  **/
1463 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1464 {
1465         struct e1000_mac_info *mac = &hw->mac;
1466         s32 ret_val, tipg_reg = 0;
1467         u16 emi_addr, emi_val = 0;
1468         bool link = false;
1469         u16 phy_reg;
1470
1471         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1472
1473         /* We only want to go out to the PHY registers to see if Auto-Neg
1474          * has completed and/or if our link status has changed.  The
1475          * get_link_status flag is set upon receiving a Link Status
1476          * Change or Rx Sequence Error interrupt.
1477          */
1478         if (!mac->get_link_status)
1479                 return E1000_SUCCESS;
1480
1481         if ((hw->mac.type < e1000_pch_lpt) ||
1482             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1483             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1484                 /* First we want to see if the MII Status Register reports
1485                  * link.  If so, then we want to get the current speed/duplex
1486                  * of the PHY.
1487                  */
1488                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1489                 if (ret_val)
1490                         return ret_val;
1491         } else {
1492                 /* Check the MAC's STATUS register to determine link state
1493                  * since the PHY could be inaccessible while in ULP mode.
1494                  */
1495                 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1496                 if (link)
1497                         ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1498                 else
1499                         ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1500                 if (ret_val)
1501                         return ret_val;
1502         }
1503
1504         if (hw->mac.type == e1000_pchlan) {
1505                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1506                 if (ret_val)
1507                         return ret_val;
1508         }
1509
1510         /* When connected at 10Mbps half-duplex, some parts are excessively
1511          * aggressive resulting in many collisions. To avoid this, increase
1512          * the IPG and reduce Rx latency in the PHY.
1513          */
1514         if ((hw->mac.type >= e1000_pch2lan) && link) {
1515                 u16 speed, duplex;
1516
1517                 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1518                 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1519                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1520
1521                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1522                         tipg_reg |= 0xFF;
1523                         /* Reduce Rx latency in analog PHY */
1524                         emi_val = 0;
1525                 } else if (hw->mac.type >= e1000_pch_spt &&
1526                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1527                         tipg_reg |= 0xC;
1528                         emi_val = 1;
1529                 } else {
1530                         /* Roll back the default values */
1531                         tipg_reg |= 0x08;
1532                         emi_val = 1;
1533                 }
1534
1535                 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1536
1537                 ret_val = hw->phy.ops.acquire(hw);
1538                 if (ret_val)
1539                         return ret_val;
1540
1541                 if (hw->mac.type == e1000_pch2lan)
1542                         emi_addr = I82579_RX_CONFIG;
1543                 else
1544                         emi_addr = I217_RX_CONFIG;
1545                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1546
1547
1548                 if (hw->mac.type >= e1000_pch_lpt) {
1549                         hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1550                                                     &phy_reg);
1551                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1552                         if (speed == SPEED_100 || speed == SPEED_10)
1553                                 phy_reg |= 0x3E8;
1554                         else
1555                                 phy_reg |= 0xFA;
1556                         hw->phy.ops.write_reg_locked(hw,
1557                                                      I217_PLL_CLOCK_GATE_REG,
1558                                                      phy_reg);
1559
1560                         if (speed == SPEED_1000) {
1561                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1562                                                             &phy_reg);
1563
1564                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1565
1566                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1567                                                              phy_reg);
1568                                 }
1569                  }
1570                 hw->phy.ops.release(hw);
1571
1572                 if (ret_val)
1573                         return ret_val;
1574
1575                 if (hw->mac.type >= e1000_pch_spt) {
1576                         u16 data;
1577                         u16 ptr_gap;
1578
1579                         if (speed == SPEED_1000) {
1580                                 ret_val = hw->phy.ops.acquire(hw);
1581                                 if (ret_val)
1582                                         return ret_val;
1583
1584                                 ret_val = hw->phy.ops.read_reg_locked(hw,
1585                                                               PHY_REG(776, 20),
1586                                                               &data);
1587                                 if (ret_val) {
1588                                         hw->phy.ops.release(hw);
1589                                         return ret_val;
1590                                 }
1591
1592                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1593                                 if (ptr_gap < 0x18) {
1594                                         data &= ~(0x3FF << 2);
1595                                         data |= (0x18 << 2);
1596                                         ret_val =
1597                                                 hw->phy.ops.write_reg_locked(hw,
1598                                                         PHY_REG(776, 20), data);
1599                                 }
1600                                 hw->phy.ops.release(hw);
1601                                 if (ret_val)
1602                                         return ret_val;
1603                         } else {
1604                                 ret_val = hw->phy.ops.acquire(hw);
1605                                 if (ret_val)
1606                                         return ret_val;
1607
1608                                 ret_val = hw->phy.ops.write_reg_locked(hw,
1609                                                              PHY_REG(776, 20),
1610                                                              0xC023);
1611                                 hw->phy.ops.release(hw);
1612                                 if (ret_val)
1613                                         return ret_val;
1614
1615                         }
1616                 }
1617         }
1618
1619         /* I217 Packet Loss issue:
1620          * ensure that FEXTNVM4 Beacon Duration is set correctly
1621          * on power up.
1622          * Set the Beacon Duration for I217 to 8 usec
1623          */
1624         if (hw->mac.type >= e1000_pch_lpt) {
1625                 u32 mac_reg;
1626
1627                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1628                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1629                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1630                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1631         }
1632
1633         /* Work-around I218 hang issue */
1634         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1635             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1636             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1637             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1638                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1639                 if (ret_val)
1640                         return ret_val;
1641         }
1642         /* Clear link partner's EEE ability */
1643         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1644
1645         /* Configure K0s minimum time */
1646         if (hw->mac.type >= e1000_pch_lpt) {
1647                 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1648         }
1649
1650         if (hw->mac.type >= e1000_pch_lpt) {
1651                 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1652
1653                 if (hw->mac.type == e1000_pch_spt) {
1654                         /* FEXTNVM6 K1-off workaround - for SPT only */
1655                         u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1656
1657                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1658                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1659                         else
1660                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1661                 }
1662
1663                 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1664                         fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1665
1666                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1667         }
1668
1669         if (!link)
1670                 return E1000_SUCCESS; /* No link detected */
1671
1672         mac->get_link_status = false;
1673
1674         switch (hw->mac.type) {
1675         case e1000_pch2lan:
1676                 ret_val = e1000_k1_workaround_lv(hw);
1677                 if (ret_val)
1678                         return ret_val;
1679                 /* fall-thru */
1680         case e1000_pchlan:
1681                 if (hw->phy.type == e1000_phy_82578) {
1682                         ret_val = e1000_link_stall_workaround_hv(hw);
1683                         if (ret_val)
1684                                 return ret_val;
1685                 }
1686
1687                 /* Workaround for PCHx parts in half-duplex:
1688                  * Set the number of preambles removed from the packet
1689                  * when it is passed from the PHY to the MAC to prevent
1690                  * the MAC from misinterpreting the packet type.
1691                  */
1692                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1693                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1694
1695                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1696                     E1000_STATUS_FD)
1697                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1698
1699                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1700                 break;
1701         default:
1702                 break;
1703         }
1704
1705         /* Check if there was DownShift, must be checked
1706          * immediately after link-up
1707          */
1708         e1000_check_downshift_generic(hw);
1709
1710         /* Enable/Disable EEE after link up */
1711         if (hw->phy.type > e1000_phy_82579) {
1712                 ret_val = e1000_set_eee_pchlan(hw);
1713                 if (ret_val)
1714                         return ret_val;
1715         }
1716
1717         /* If we are forcing speed/duplex, then we simply return since
1718          * we have already determined whether we have link or not.
1719          */
1720         if (!mac->autoneg)
1721                 return -E1000_ERR_CONFIG;
1722
1723         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1724          * of MAC speed/duplex configuration.  So we only need to
1725          * configure Collision Distance in the MAC.
1726          */
1727         mac->ops.config_collision_dist(hw);
1728
1729         /* Configure Flow Control now that Auto-Neg has completed.
1730          * First, we need to restore the desired flow control
1731          * settings because we may have had to re-autoneg with a
1732          * different link partner.
1733          */
1734         ret_val = e1000_config_fc_after_link_up_generic(hw);
1735         if (ret_val)
1736                 DEBUGOUT("Error configuring flow control\n");
1737
1738         return ret_val;
1739 }
1740
1741 /**
1742  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1743  *  @hw: pointer to the HW structure
1744  *
1745  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1746  **/
1747 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1748 {
1749         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1750
1751         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1752         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1753         switch (hw->mac.type) {
1754         case e1000_ich8lan:
1755         case e1000_ich9lan:
1756         case e1000_ich10lan:
1757                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1758                 break;
1759         case e1000_pchlan:
1760         case e1000_pch2lan:
1761         case e1000_pch_lpt:
1762         case e1000_pch_spt:
1763         case e1000_pch_cnp:
1764                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1765                 break;
1766         default:
1767                 break;
1768         }
1769 }
1770
1771 /**
1772  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1773  *  @hw: pointer to the HW structure
1774  *
1775  *  Acquires the mutex for performing NVM operations.
1776  **/
1777 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1778 {
1779         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1780
1781         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1782
1783         return E1000_SUCCESS;
1784 }
1785
1786 /**
1787  *  e1000_release_nvm_ich8lan - Release NVM mutex
1788  *  @hw: pointer to the HW structure
1789  *
1790  *  Releases the mutex used while performing NVM operations.
1791  **/
1792 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1793 {
1794         DEBUGFUNC("e1000_release_nvm_ich8lan");
1795
1796         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1797
1798         return;
1799 }
1800
1801 /**
1802  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1803  *  @hw: pointer to the HW structure
1804  *
1805  *  Acquires the software control flag for performing PHY and select
1806  *  MAC CSR accesses.
1807  **/
1808 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1809 {
1810         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1811         s32 ret_val = E1000_SUCCESS;
1812
1813         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1814
1815         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1816
1817         while (timeout) {
1818                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1819                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1820                         break;
1821
1822                 msec_delay_irq(1);
1823                 timeout--;
1824         }
1825
1826         if (!timeout) {
1827                 DEBUGOUT("SW has already locked the resource.\n");
1828                 ret_val = -E1000_ERR_CONFIG;
1829                 goto out;
1830         }
1831
1832         timeout = SW_FLAG_TIMEOUT;
1833
1834         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1835         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1836
1837         while (timeout) {
1838                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1839                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1840                         break;
1841
1842                 msec_delay_irq(1);
1843                 timeout--;
1844         }
1845
1846         if (!timeout) {
1847                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1848                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1849                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1850                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1851                 ret_val = -E1000_ERR_CONFIG;
1852                 goto out;
1853         }
1854
1855 out:
1856         if (ret_val)
1857                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1858
1859         return ret_val;
1860 }
1861
1862 /**
1863  *  e1000_release_swflag_ich8lan - Release software control flag
1864  *  @hw: pointer to the HW structure
1865  *
1866  *  Releases the software control flag for performing PHY and select
1867  *  MAC CSR accesses.
1868  **/
1869 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1870 {
1871         u32 extcnf_ctrl;
1872
1873         DEBUGFUNC("e1000_release_swflag_ich8lan");
1874
1875         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1876
1877         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1878                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1879                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1880         } else {
1881                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1882         }
1883
1884         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1885
1886         return;
1887 }
1888
1889 /**
1890  *  e1000_check_mng_mode_ich8lan - Checks management mode
1891  *  @hw: pointer to the HW structure
1892  *
1893  *  This checks if the adapter has any manageability enabled.
1894  *  This is a function pointer entry point only called by read/write
1895  *  routines for the PHY and NVM parts.
1896  **/
1897 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1898 {
1899         u32 fwsm;
1900
1901         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1902
1903         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1904
1905         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1906                ((fwsm & E1000_FWSM_MODE_MASK) ==
1907                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1908 }
1909
1910 /**
1911  *  e1000_check_mng_mode_pchlan - Checks management mode
1912  *  @hw: pointer to the HW structure
1913  *
1914  *  This checks if the adapter has iAMT enabled.
1915  *  This is a function pointer entry point only called by read/write
1916  *  routines for the PHY and NVM parts.
1917  **/
1918 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1919 {
1920         u32 fwsm;
1921
1922         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1923
1924         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1925
1926         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1927                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1928 }
1929
1930 /**
1931  *  e1000_rar_set_pch2lan - Set receive address register
1932  *  @hw: pointer to the HW structure
1933  *  @addr: pointer to the receive address
1934  *  @index: receive address array register
1935  *
1936  *  Sets the receive address array register at index to the address passed
1937  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1938  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1939  *  Use SHRA[0-3] in place of those reserved for ME.
1940  **/
1941 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1942 {
1943         u32 rar_low, rar_high;
1944
1945         DEBUGFUNC("e1000_rar_set_pch2lan");
1946
1947         /* HW expects these in little endian so we reverse the byte order
1948          * from network order (big endian) to little endian
1949          */
1950         rar_low = ((u32) addr[0] |
1951                    ((u32) addr[1] << 8) |
1952                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1953
1954         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1955
1956         /* If MAC address zero, no need to set the AV bit */
1957         if (rar_low || rar_high)
1958                 rar_high |= E1000_RAH_AV;
1959
1960         if (index == 0) {
1961                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1962                 E1000_WRITE_FLUSH(hw);
1963                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1964                 E1000_WRITE_FLUSH(hw);
1965                 return E1000_SUCCESS;
1966         }
1967
1968         /* RAR[1-6] are owned by manageability.  Skip those and program the
1969          * next address into the SHRA register array.
1970          */
1971         if (index < (u32) (hw->mac.rar_entry_count)) {
1972                 s32 ret_val;
1973
1974                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1975                 if (ret_val)
1976                         goto out;
1977
1978                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1979                 E1000_WRITE_FLUSH(hw);
1980                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1981                 E1000_WRITE_FLUSH(hw);
1982
1983                 e1000_release_swflag_ich8lan(hw);
1984
1985                 /* verify the register updates */
1986                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1987                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1988                         return E1000_SUCCESS;
1989
1990                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1991                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1992         }
1993
1994 out:
1995         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1996         return -E1000_ERR_CONFIG;
1997 }
1998
1999 /**
2000  *  e1000_rar_set_pch_lpt - Set receive address registers
2001  *  @hw: pointer to the HW structure
2002  *  @addr: pointer to the receive address
2003  *  @index: receive address array register
2004  *
2005  *  Sets the receive address register array at index to the address passed
2006  *  in by addr. For LPT, RAR[0] is the base address register that is to
2007  *  contain the MAC address. SHRA[0-10] are the shared receive address
2008  *  registers that are shared between the Host and manageability engine (ME).
2009  **/
2010 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2011 {
2012         u32 rar_low, rar_high;
2013         u32 wlock_mac;
2014
2015         DEBUGFUNC("e1000_rar_set_pch_lpt");
2016
2017         /* HW expects these in little endian so we reverse the byte order
2018          * from network order (big endian) to little endian
2019          */
2020         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2021                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2022
2023         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2024
2025         /* If MAC address zero, no need to set the AV bit */
2026         if (rar_low || rar_high)
2027                 rar_high |= E1000_RAH_AV;
2028
2029         if (index == 0) {
2030                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2031                 E1000_WRITE_FLUSH(hw);
2032                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2033                 E1000_WRITE_FLUSH(hw);
2034                 return E1000_SUCCESS;
2035         }
2036
2037         /* The manageability engine (ME) can lock certain SHRAR registers that
2038          * it is using - those registers are unavailable for use.
2039          */
2040         if (index < hw->mac.rar_entry_count) {
2041                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2042                             E1000_FWSM_WLOCK_MAC_MASK;
2043                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2044
2045                 /* Check if all SHRAR registers are locked */
2046                 if (wlock_mac == 1)
2047                         goto out;
2048
2049                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2050                         s32 ret_val;
2051
2052                         ret_val = e1000_acquire_swflag_ich8lan(hw);
2053
2054                         if (ret_val)
2055                                 goto out;
2056
2057                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2058                                         rar_low);
2059                         E1000_WRITE_FLUSH(hw);
2060                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2061                                         rar_high);
2062                         E1000_WRITE_FLUSH(hw);
2063
2064                         e1000_release_swflag_ich8lan(hw);
2065
2066                         /* verify the register updates */
2067                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2068                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2069                                 return E1000_SUCCESS;
2070                 }
2071         }
2072
2073 out:
2074         DEBUGOUT1("Failed to write receive address at index %d\n", index);
2075         return -E1000_ERR_CONFIG;
2076 }
2077
2078 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
2079 /**
2080  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2081  *  @hw: pointer to the HW structure
2082  *  @mc_addr_list: array of multicast addresses to program
2083  *  @mc_addr_count: number of multicast addresses to program
2084  *
2085  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2086  *  The caller must have a packed mc_addr_list of multicast addresses.
2087  **/
2088 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2089                                               u8 *mc_addr_list,
2090                                               u32 mc_addr_count)
2091 {
2092         u16 phy_reg = 0;
2093         int i;
2094         s32 ret_val;
2095
2096         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2097
2098         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2099
2100         ret_val = hw->phy.ops.acquire(hw);
2101         if (ret_val)
2102                 return;
2103
2104         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2105         if (ret_val)
2106                 goto release;
2107
2108         for (i = 0; i < hw->mac.mta_reg_count; i++) {
2109                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2110                                            (u16)(hw->mac.mta_shadow[i] &
2111                                                  0xFFFF));
2112                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2113                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
2114                                                  0xFFFF));
2115         }
2116
2117         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2118
2119 release:
2120         hw->phy.ops.release(hw);
2121 }
2122
2123 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
2124 /**
2125  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2126  *  @hw: pointer to the HW structure
2127  *
2128  *  Checks if firmware is blocking the reset of the PHY.
2129  *  This is a function pointer entry point only called by
2130  *  reset routines.
2131  **/
2132 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2133 {
2134         u32 fwsm;
2135         bool blocked = false;
2136         int i = 0;
2137
2138         DEBUGFUNC("e1000_check_reset_block_ich8lan");
2139
2140         do {
2141                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2142                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2143                         blocked = true;
2144                         msec_delay(10);
2145                         continue;
2146                 }
2147                 blocked = false;
2148         } while (blocked && (i++ < 30));
2149         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2150 }
2151
2152 /**
2153  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2154  *  @hw: pointer to the HW structure
2155  *
2156  *  Assumes semaphore already acquired.
2157  *
2158  **/
2159 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2160 {
2161         u16 phy_data;
2162         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2163         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2164                 E1000_STRAP_SMT_FREQ_SHIFT;
2165         s32 ret_val;
2166
2167         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2168
2169         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2170         if (ret_val)
2171                 return ret_val;
2172
2173         phy_data &= ~HV_SMB_ADDR_MASK;
2174         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2175         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2176
2177         if (hw->phy.type == e1000_phy_i217) {
2178                 /* Restore SMBus frequency */
2179                 if (freq--) {
2180                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2181                         phy_data |= (freq & (1 << 0)) <<
2182                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2183                         phy_data |= (freq & (1 << 1)) <<
2184                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2185                 } else {
2186                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
2187                 }
2188         }
2189
2190         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2191 }
2192
2193 /**
2194  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2195  *  @hw:   pointer to the HW structure
2196  *
2197  *  SW should configure the LCD from the NVM extended configuration region
2198  *  as a workaround for certain parts.
2199  **/
2200 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2201 {
2202         struct e1000_phy_info *phy = &hw->phy;
2203         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2204         s32 ret_val = E1000_SUCCESS;
2205         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2206
2207         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2208
2209         /* Initialize the PHY from the NVM on ICH platforms.  This
2210          * is needed due to an issue where the NVM configuration is
2211          * not properly autoloaded after power transitions.
2212          * Therefore, after each PHY reset, we will load the
2213          * configuration data out of the NVM manually.
2214          */
2215         switch (hw->mac.type) {
2216         case e1000_ich8lan:
2217                 if (phy->type != e1000_phy_igp_3)
2218                         return ret_val;
2219
2220                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2221                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2222                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2223                         break;
2224                 }
2225                 /* Fall-thru */
2226         case e1000_pchlan:
2227         case e1000_pch2lan:
2228         case e1000_pch_lpt:
2229         case e1000_pch_spt:
2230         case e1000_pch_cnp:
2231                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2232                 break;
2233         default:
2234                 return ret_val;
2235         }
2236
2237         ret_val = hw->phy.ops.acquire(hw);
2238         if (ret_val)
2239                 return ret_val;
2240
2241         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2242         if (!(data & sw_cfg_mask))
2243                 goto release;
2244
2245         /* Make sure HW does not configure LCD from PHY
2246          * extended configuration before SW configuration
2247          */
2248         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2249         if ((hw->mac.type < e1000_pch2lan) &&
2250             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2251                         goto release;
2252
2253         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2254         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2255         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2256         if (!cnf_size)
2257                 goto release;
2258
2259         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2260         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2261
2262         if (((hw->mac.type == e1000_pchlan) &&
2263              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2264             (hw->mac.type > e1000_pchlan)) {
2265                 /* HW configures the SMBus address and LEDs when the
2266                  * OEM and LCD Write Enable bits are set in the NVM.
2267                  * When both NVM bits are cleared, SW will configure
2268                  * them instead.
2269                  */
2270                 ret_val = e1000_write_smbus_addr(hw);
2271                 if (ret_val)
2272                         goto release;
2273
2274                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2275                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2276                                                         (u16)data);
2277                 if (ret_val)
2278                         goto release;
2279         }
2280
2281         /* Configure LCD from extended configuration region. */
2282
2283         /* cnf_base_addr is in DWORD */
2284         word_addr = (u16)(cnf_base_addr << 1);
2285
2286         for (i = 0; i < cnf_size; i++) {
2287                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2288                                            &reg_data);
2289                 if (ret_val)
2290                         goto release;
2291
2292                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2293                                            1, &reg_addr);
2294                 if (ret_val)
2295                         goto release;
2296
2297                 /* Save off the PHY page for future writes. */
2298                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2299                         phy_page = reg_data;
2300                         continue;
2301                 }
2302
2303                 reg_addr &= PHY_REG_MASK;
2304                 reg_addr |= phy_page;
2305
2306                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2307                                                     reg_data);
2308                 if (ret_val)
2309                         goto release;
2310         }
2311
2312 release:
2313         hw->phy.ops.release(hw);
2314         return ret_val;
2315 }
2316
2317 /**
2318  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2319  *  @hw:   pointer to the HW structure
2320  *  @link: link up bool flag
2321  *
2322  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2323  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2324  *  If link is down, the function will restore the default K1 setting located
2325  *  in the NVM.
2326  **/
2327 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2328 {
2329         s32 ret_val = E1000_SUCCESS;
2330         u16 status_reg = 0;
2331         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2332
2333         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2334
2335         if (hw->mac.type != e1000_pchlan)
2336                 return E1000_SUCCESS;
2337
2338         /* Wrap the whole flow with the sw flag */
2339         ret_val = hw->phy.ops.acquire(hw);
2340         if (ret_val)
2341                 return ret_val;
2342
2343         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2344         if (link) {
2345                 if (hw->phy.type == e1000_phy_82578) {
2346                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2347                                                               &status_reg);
2348                         if (ret_val)
2349                                 goto release;
2350
2351                         status_reg &= (BM_CS_STATUS_LINK_UP |
2352                                        BM_CS_STATUS_RESOLVED |
2353                                        BM_CS_STATUS_SPEED_MASK);
2354
2355                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2356                                            BM_CS_STATUS_RESOLVED |
2357                                            BM_CS_STATUS_SPEED_1000))
2358                                 k1_enable = false;
2359                 }
2360
2361                 if (hw->phy.type == e1000_phy_82577) {
2362                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2363                                                               &status_reg);
2364                         if (ret_val)
2365                                 goto release;
2366
2367                         status_reg &= (HV_M_STATUS_LINK_UP |
2368                                        HV_M_STATUS_AUTONEG_COMPLETE |
2369                                        HV_M_STATUS_SPEED_MASK);
2370
2371                         if (status_reg == (HV_M_STATUS_LINK_UP |
2372                                            HV_M_STATUS_AUTONEG_COMPLETE |
2373                                            HV_M_STATUS_SPEED_1000))
2374                                 k1_enable = false;
2375                 }
2376
2377                 /* Link stall fix for link up */
2378                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2379                                                        0x0100);
2380                 if (ret_val)
2381                         goto release;
2382
2383         } else {
2384                 /* Link stall fix for link down */
2385                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2386                                                        0x4100);
2387                 if (ret_val)
2388                         goto release;
2389         }
2390
2391         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2392
2393 release:
2394         hw->phy.ops.release(hw);
2395
2396         return ret_val;
2397 }
2398
2399 /**
2400  *  e1000_configure_k1_ich8lan - Configure K1 power state
2401  *  @hw: pointer to the HW structure
2402  *  @k1_enable: K1 state to configure
2403  *
2404  *  Configure the K1 power state based on the provided parameter.
2405  *  Assumes semaphore already acquired.
2406  *
2407  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2408  **/
2409 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2410 {
2411         s32 ret_val;
2412         u32 ctrl_reg = 0;
2413         u32 ctrl_ext = 0;
2414         u32 reg = 0;
2415         u16 kmrn_reg = 0;
2416
2417         DEBUGFUNC("e1000_configure_k1_ich8lan");
2418
2419         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2420                                              &kmrn_reg);
2421         if (ret_val)
2422                 return ret_val;
2423
2424         if (k1_enable)
2425                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2426         else
2427                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2428
2429         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2430                                               kmrn_reg);
2431         if (ret_val)
2432                 return ret_val;
2433
2434         usec_delay(20);
2435         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2436         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2437
2438         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2439         reg |= E1000_CTRL_FRCSPD;
2440         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2441
2442         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2443         E1000_WRITE_FLUSH(hw);
2444         usec_delay(20);
2445         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2446         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2447         E1000_WRITE_FLUSH(hw);
2448         usec_delay(20);
2449
2450         return E1000_SUCCESS;
2451 }
2452
2453 /**
2454  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2455  *  @hw:       pointer to the HW structure
2456  *  @d0_state: boolean if entering d0 or d3 device state
2457  *
2458  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2459  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2460  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2461  **/
2462 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2463 {
2464         s32 ret_val = 0;
2465         u32 mac_reg;
2466         u16 oem_reg;
2467
2468         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2469
2470         if (hw->mac.type < e1000_pchlan)
2471                 return ret_val;
2472
2473         ret_val = hw->phy.ops.acquire(hw);
2474         if (ret_val)
2475                 return ret_val;
2476
2477         if (hw->mac.type == e1000_pchlan) {
2478                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2479                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2480                         goto release;
2481         }
2482
2483         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2484         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2485                 goto release;
2486
2487         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2488
2489         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2490         if (ret_val)
2491                 goto release;
2492
2493         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2494
2495         if (d0_state) {
2496                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2497                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2498
2499                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2500                         oem_reg |= HV_OEM_BITS_LPLU;
2501         } else {
2502                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2503                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2504                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2505
2506                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2507                     E1000_PHY_CTRL_NOND0A_LPLU))
2508                         oem_reg |= HV_OEM_BITS_LPLU;
2509         }
2510
2511         /* Set Restart auto-neg to activate the bits */
2512         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2513             !hw->phy.ops.check_reset_block(hw))
2514                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2515
2516         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2517
2518 release:
2519         hw->phy.ops.release(hw);
2520
2521         return ret_val;
2522 }
2523
2524
2525 /**
2526  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2527  *  @hw:   pointer to the HW structure
2528  **/
2529 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2530 {
2531         s32 ret_val;
2532         u16 data;
2533
2534         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2535
2536         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2537         if (ret_val)
2538                 return ret_val;
2539
2540         data |= HV_KMRN_MDIO_SLOW;
2541
2542         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2543
2544         return ret_val;
2545 }
2546
2547 /**
2548  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2549  *  done after every PHY reset.
2550  *  @hw: pointer to the HW structure
2551  **/
2552 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2553 {
2554         s32 ret_val = E1000_SUCCESS;
2555         u16 phy_data;
2556
2557         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2558
2559         if (hw->mac.type != e1000_pchlan)
2560                 return E1000_SUCCESS;
2561
2562         /* Set MDIO slow mode before any other MDIO access */
2563         if (hw->phy.type == e1000_phy_82577) {
2564                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2565                 if (ret_val)
2566                         return ret_val;
2567         }
2568
2569         if (((hw->phy.type == e1000_phy_82577) &&
2570              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2571             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2572                 /* Disable generation of early preamble */
2573                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2574                 if (ret_val)
2575                         return ret_val;
2576
2577                 /* Preamble tuning for SSC */
2578                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2579                                                 0xA204);
2580                 if (ret_val)
2581                         return ret_val;
2582         }
2583
2584         if (hw->phy.type == e1000_phy_82578) {
2585                 /* Return registers to default by doing a soft reset then
2586                  * writing 0x3140 to the control register.
2587                  */
2588                 if (hw->phy.revision < 2) {
2589                         e1000_phy_sw_reset_generic(hw);
2590                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2591                                                         0x3140);
2592                 }
2593         }
2594
2595         /* Select page 0 */
2596         ret_val = hw->phy.ops.acquire(hw);
2597         if (ret_val)
2598                 return ret_val;
2599
2600         hw->phy.addr = 1;
2601         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2602         hw->phy.ops.release(hw);
2603         if (ret_val)
2604                 return ret_val;
2605
2606         /* Configure the K1 Si workaround during phy reset assuming there is
2607          * link so that it disables K1 if link is in 1Gbps.
2608          */
2609         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2610         if (ret_val)
2611                 return ret_val;
2612
2613         /* Workaround for link disconnects on a busy hub in half duplex */
2614         ret_val = hw->phy.ops.acquire(hw);
2615         if (ret_val)
2616                 return ret_val;
2617         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2618         if (ret_val)
2619                 goto release;
2620         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2621                                                phy_data & 0x00FF);
2622         if (ret_val)
2623                 goto release;
2624
2625         /* set MSE higher to enable link to stay up when noise is high */
2626         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2627 release:
2628         hw->phy.ops.release(hw);
2629
2630         return ret_val;
2631 }
2632
2633 /**
2634  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2635  *  @hw:   pointer to the HW structure
2636  **/
2637 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2638 {
2639         u32 mac_reg;
2640         u16 i, phy_reg = 0;
2641         s32 ret_val;
2642
2643         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2644
2645         ret_val = hw->phy.ops.acquire(hw);
2646         if (ret_val)
2647                 return;
2648         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2649         if (ret_val)
2650                 goto release;
2651
2652         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2653         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2654                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2655                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2656                                            (u16)(mac_reg & 0xFFFF));
2657                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2658                                            (u16)((mac_reg >> 16) & 0xFFFF));
2659
2660                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2661                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2662                                            (u16)(mac_reg & 0xFFFF));
2663                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2664                                            (u16)((mac_reg & E1000_RAH_AV)
2665                                                  >> 16));
2666         }
2667
2668         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2669
2670 release:
2671         hw->phy.ops.release(hw);
2672 }
2673
2674 #ifndef CRC32_OS_SUPPORT
2675 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2676 {
2677         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2678         u32 i, j, mask, crc;
2679
2680         DEBUGFUNC("e1000_calc_rx_da_crc");
2681
2682         crc = 0xffffffff;
2683         for (i = 0; i < 6; i++) {
2684                 crc = crc ^ mac[i];
2685                 for (j = 8; j > 0; j--) {
2686                         mask = (crc & 1) * (-1);
2687                         crc = (crc >> 1) ^ (poly & mask);
2688                 }
2689         }
2690         return ~crc;
2691 }
2692
2693 #endif /* CRC32_OS_SUPPORT */
2694 /**
2695  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2696  *  with 82579 PHY
2697  *  @hw: pointer to the HW structure
2698  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2699  **/
2700 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2701 {
2702         s32 ret_val = E1000_SUCCESS;
2703         u16 phy_reg, data;
2704         u32 mac_reg;
2705         u16 i;
2706
2707         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2708
2709         if (hw->mac.type < e1000_pch2lan)
2710                 return E1000_SUCCESS;
2711
2712         /* disable Rx path while enabling/disabling workaround */
2713         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2714         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2715                                         phy_reg | (1 << 14));
2716         if (ret_val)
2717                 return ret_val;
2718
2719         if (enable) {
2720                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2721                  * SHRAL/H) and initial CRC values to the MAC
2722                  */
2723                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2724                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2725                         u32 addr_high, addr_low;
2726
2727                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2728                         if (!(addr_high & E1000_RAH_AV))
2729                                 continue;
2730                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2731                         mac_addr[0] = (addr_low & 0xFF);
2732                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2733                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2734                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2735                         mac_addr[4] = (addr_high & 0xFF);
2736                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2737
2738 #ifndef CRC32_OS_SUPPORT
2739                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2740                                         e1000_calc_rx_da_crc(mac_addr));
2741 #else /* CRC32_OS_SUPPORT */
2742                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2743                                         E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2744 #endif /* CRC32_OS_SUPPORT */
2745                 }
2746
2747                 /* Write Rx addresses to the PHY */
2748                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2749
2750                 /* Enable jumbo frame workaround in the MAC */
2751                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2752                 mac_reg &= ~(1 << 14);
2753                 mac_reg |= (7 << 15);
2754                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2755
2756                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2757                 mac_reg |= E1000_RCTL_SECRC;
2758                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2759
2760                 ret_val = e1000_read_kmrn_reg_generic(hw,
2761                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2762                                                 &data);
2763                 if (ret_val)
2764                         return ret_val;
2765                 ret_val = e1000_write_kmrn_reg_generic(hw,
2766                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2767                                                 data | (1 << 0));
2768                 if (ret_val)
2769                         return ret_val;
2770                 ret_val = e1000_read_kmrn_reg_generic(hw,
2771                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2772                                                 &data);
2773                 if (ret_val)
2774                         return ret_val;
2775                 data &= ~(0xF << 8);
2776                 data |= (0xB << 8);
2777                 ret_val = e1000_write_kmrn_reg_generic(hw,
2778                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2779                                                 data);
2780                 if (ret_val)
2781                         return ret_val;
2782
2783                 /* Enable jumbo frame workaround in the PHY */
2784                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2785                 data &= ~(0x7F << 5);
2786                 data |= (0x37 << 5);
2787                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2788                 if (ret_val)
2789                         return ret_val;
2790                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2791                 data &= ~(1 << 13);
2792                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2793                 if (ret_val)
2794                         return ret_val;
2795                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2796                 data &= ~(0x3FF << 2);
2797                 data |= (E1000_TX_PTR_GAP << 2);
2798                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2799                 if (ret_val)
2800                         return ret_val;
2801                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2802                 if (ret_val)
2803                         return ret_val;
2804                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2805                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2806                                                 (1 << 10));
2807                 if (ret_val)
2808                         return ret_val;
2809         } else {
2810                 /* Write MAC register values back to h/w defaults */
2811                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2812                 mac_reg &= ~(0xF << 14);
2813                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2814
2815                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2816                 mac_reg &= ~E1000_RCTL_SECRC;
2817                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2818
2819                 ret_val = e1000_read_kmrn_reg_generic(hw,
2820                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2821                                                 &data);
2822                 if (ret_val)
2823                         return ret_val;
2824                 ret_val = e1000_write_kmrn_reg_generic(hw,
2825                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2826                                                 data & ~(1 << 0));
2827                 if (ret_val)
2828                         return ret_val;
2829                 ret_val = e1000_read_kmrn_reg_generic(hw,
2830                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2831                                                 &data);
2832                 if (ret_val)
2833                         return ret_val;
2834                 data &= ~(0xF << 8);
2835                 data |= (0xB << 8);
2836                 ret_val = e1000_write_kmrn_reg_generic(hw,
2837                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2838                                                 data);
2839                 if (ret_val)
2840                         return ret_val;
2841
2842                 /* Write PHY register values back to h/w defaults */
2843                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2844                 data &= ~(0x7F << 5);
2845                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2846                 if (ret_val)
2847                         return ret_val;
2848                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2849                 data |= (1 << 13);
2850                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2851                 if (ret_val)
2852                         return ret_val;
2853                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2854                 data &= ~(0x3FF << 2);
2855                 data |= (0x8 << 2);
2856                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2857                 if (ret_val)
2858                         return ret_val;
2859                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2860                 if (ret_val)
2861                         return ret_val;
2862                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2863                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2864                                                 ~(1 << 10));
2865                 if (ret_val)
2866                         return ret_val;
2867         }
2868
2869         /* re-enable Rx path after enabling/disabling workaround */
2870         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2871                                      ~(1 << 14));
2872 }
2873
2874 /**
2875  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2876  *  done after every PHY reset.
2877  *  @hw: pointer to the HW structure
2878  **/
2879 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2880 {
2881         s32 ret_val = E1000_SUCCESS;
2882
2883         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2884
2885         if (hw->mac.type != e1000_pch2lan)
2886                 return E1000_SUCCESS;
2887
2888         /* Set MDIO slow mode before any other MDIO access */
2889         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2890         if (ret_val)
2891                 return ret_val;
2892
2893         ret_val = hw->phy.ops.acquire(hw);
2894         if (ret_val)
2895                 return ret_val;
2896         /* set MSE higher to enable link to stay up when noise is high */
2897         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2898         if (ret_val)
2899                 goto release;
2900         /* drop link after 5 times MSE threshold was reached */
2901         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2902 release:
2903         hw->phy.ops.release(hw);
2904
2905         return ret_val;
2906 }
2907
2908 /**
2909  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2910  *  @hw:   pointer to the HW structure
2911  *
2912  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2913  *  Disable K1 for 1000 and 100 speeds
2914  **/
2915 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2916 {
2917         s32 ret_val = E1000_SUCCESS;
2918         u16 status_reg = 0;
2919
2920         DEBUGFUNC("e1000_k1_workaround_lv");
2921
2922         if (hw->mac.type != e1000_pch2lan)
2923                 return E1000_SUCCESS;
2924
2925         /* Set K1 beacon duration based on 10Mbs speed */
2926         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2927         if (ret_val)
2928                 return ret_val;
2929
2930         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2931             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2932                 if (status_reg &
2933                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2934                         u16 pm_phy_reg;
2935
2936                         /* LV 1G/100 Packet drop issue wa  */
2937                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2938                                                        &pm_phy_reg);
2939                         if (ret_val)
2940                                 return ret_val;
2941                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2942                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2943                                                         pm_phy_reg);
2944                         if (ret_val)
2945                                 return ret_val;
2946                 } else {
2947                         u32 mac_reg;
2948                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2949                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2950                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2951                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2952                 }
2953         }
2954
2955         return ret_val;
2956 }
2957
2958 /**
2959  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2960  *  @hw:   pointer to the HW structure
2961  *  @gate: boolean set to true to gate, false to ungate
2962  *
2963  *  Gate/ungate the automatic PHY configuration via hardware; perform
2964  *  the configuration via software instead.
2965  **/
2966 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2967 {
2968         u32 extcnf_ctrl;
2969
2970         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2971
2972         if (hw->mac.type < e1000_pch2lan)
2973                 return;
2974
2975         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2976
2977         if (gate)
2978                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2979         else
2980                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2981
2982         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2983 }
2984
2985 /**
2986  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2987  *  @hw: pointer to the HW structure
2988  *
2989  *  Check the appropriate indication the MAC has finished configuring the
2990  *  PHY after a software reset.
2991  **/
2992 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2993 {
2994         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2995
2996         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2997
2998         /* Wait for basic configuration completes before proceeding */
2999         do {
3000                 data = E1000_READ_REG(hw, E1000_STATUS);
3001                 data &= E1000_STATUS_LAN_INIT_DONE;
3002                 usec_delay(100);
3003         } while ((!data) && --loop);
3004
3005         /* If basic configuration is incomplete before the above loop
3006          * count reaches 0, loading the configuration from NVM will
3007          * leave the PHY in a bad state possibly resulting in no link.
3008          */
3009         if (loop == 0)
3010                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3011
3012         /* Clear the Init Done bit for the next init event */
3013         data = E1000_READ_REG(hw, E1000_STATUS);
3014         data &= ~E1000_STATUS_LAN_INIT_DONE;
3015         E1000_WRITE_REG(hw, E1000_STATUS, data);
3016 }
3017
3018 /**
3019  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3020  *  @hw: pointer to the HW structure
3021  **/
3022 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3023 {
3024         s32 ret_val = E1000_SUCCESS;
3025         u16 reg;
3026
3027         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3028
3029         if (hw->phy.ops.check_reset_block(hw))
3030                 return E1000_SUCCESS;
3031
3032         /* Allow time for h/w to get to quiescent state after reset */
3033         msec_delay(10);
3034
3035         /* Perform any necessary post-reset workarounds */
3036         switch (hw->mac.type) {
3037         case e1000_pchlan:
3038                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3039                 if (ret_val)
3040                         return ret_val;
3041                 break;
3042         case e1000_pch2lan:
3043                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3044                 if (ret_val)
3045                         return ret_val;
3046                 break;
3047         default:
3048                 break;
3049         }
3050
3051         /* Clear the host wakeup bit after lcd reset */
3052         if (hw->mac.type >= e1000_pchlan) {
3053                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
3054                 reg &= ~BM_WUC_HOST_WU_BIT;
3055                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3056         }
3057
3058         /* Configure the LCD with the extended configuration region in NVM */
3059         ret_val = e1000_sw_lcd_config_ich8lan(hw);
3060         if (ret_val)
3061                 return ret_val;
3062
3063         /* Configure the LCD with the OEM bits in NVM */
3064         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3065
3066         if (hw->mac.type == e1000_pch2lan) {
3067                 /* Ungate automatic PHY configuration on non-managed 82579 */
3068                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3069                     E1000_ICH_FWSM_FW_VALID)) {
3070                         msec_delay(10);
3071                         e1000_gate_hw_phy_config_ich8lan(hw, false);
3072                 }
3073
3074                 /* Set EEE LPI Update Timer to 200usec */
3075                 ret_val = hw->phy.ops.acquire(hw);
3076                 if (ret_val)
3077                         return ret_val;
3078                 ret_val = e1000_write_emi_reg_locked(hw,
3079                                                      I82579_LPI_UPDATE_TIMER,
3080                                                      0x1387);
3081                 hw->phy.ops.release(hw);
3082         }
3083
3084         return ret_val;
3085 }
3086
3087 /**
3088  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3089  *  @hw: pointer to the HW structure
3090  *
3091  *  Resets the PHY
3092  *  This is a function pointer entry point called by drivers
3093  *  or other shared routines.
3094  **/
3095 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3096 {
3097         s32 ret_val = E1000_SUCCESS;
3098
3099         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3100
3101         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3102         if ((hw->mac.type == e1000_pch2lan) &&
3103             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3104                 e1000_gate_hw_phy_config_ich8lan(hw, true);
3105
3106         ret_val = e1000_phy_hw_reset_generic(hw);
3107         if (ret_val)
3108                 return ret_val;
3109
3110         return e1000_post_phy_reset_ich8lan(hw);
3111 }
3112
3113 /**
3114  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3115  *  @hw: pointer to the HW structure
3116  *  @active: true to enable LPLU, false to disable
3117  *
3118  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
3119  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3120  *  the phy speed. This function will manually set the LPLU bit and restart
3121  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
3122  *  since it configures the same bit.
3123  **/
3124 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3125 {
3126         s32 ret_val;
3127         u16 oem_reg;
3128
3129         DEBUGFUNC("e1000_set_lplu_state_pchlan");
3130         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3131         if (ret_val)
3132                 return ret_val;
3133
3134         if (active)
3135                 oem_reg |= HV_OEM_BITS_LPLU;
3136         else
3137                 oem_reg &= ~HV_OEM_BITS_LPLU;
3138
3139         if (!hw->phy.ops.check_reset_block(hw))
3140                 oem_reg |= HV_OEM_BITS_RESTART_AN;
3141
3142         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3143 }
3144
3145 /**
3146  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3147  *  @hw: pointer to the HW structure
3148  *  @active: true to enable LPLU, false to disable
3149  *
3150  *  Sets the LPLU D0 state according to the active flag.  When
3151  *  activating LPLU this function also disables smart speed
3152  *  and vice versa.  LPLU will not be activated unless the
3153  *  device autonegotiation advertisement meets standards of
3154  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3155  *  This is a function pointer entry point only called by
3156  *  PHY setup routines.
3157  **/
3158 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3159 {
3160         struct e1000_phy_info *phy = &hw->phy;
3161         u32 phy_ctrl;
3162         s32 ret_val = E1000_SUCCESS;
3163         u16 data;
3164
3165         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3166
3167         if (phy->type == e1000_phy_ife)
3168                 return E1000_SUCCESS;
3169
3170         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3171
3172         if (active) {
3173                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3174                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3175
3176                 if (phy->type != e1000_phy_igp_3)
3177                         return E1000_SUCCESS;
3178
3179                 /* Call gig speed drop workaround on LPLU before accessing
3180                  * any PHY registers
3181                  */
3182                 if (hw->mac.type == e1000_ich8lan)
3183                         e1000_gig_downshift_workaround_ich8lan(hw);
3184
3185                 /* When LPLU is enabled, we should disable SmartSpeed */
3186                 ret_val = phy->ops.read_reg(hw,
3187                                             IGP01E1000_PHY_PORT_CONFIG,
3188                                             &data);
3189                 if (ret_val)
3190                         return ret_val;
3191                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3192                 ret_val = phy->ops.write_reg(hw,
3193                                              IGP01E1000_PHY_PORT_CONFIG,
3194                                              data);
3195                 if (ret_val)
3196                         return ret_val;
3197         } else {
3198                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3199                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3200
3201                 if (phy->type != e1000_phy_igp_3)
3202                         return E1000_SUCCESS;
3203
3204                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3205                  * during Dx states where the power conservation is most
3206                  * important.  During driver activity we should enable
3207                  * SmartSpeed, so performance is maintained.
3208                  */
3209                 if (phy->smart_speed == e1000_smart_speed_on) {
3210                         ret_val = phy->ops.read_reg(hw,
3211                                                     IGP01E1000_PHY_PORT_CONFIG,
3212                                                     &data);
3213                         if (ret_val)
3214                                 return ret_val;
3215
3216                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3217                         ret_val = phy->ops.write_reg(hw,
3218                                                      IGP01E1000_PHY_PORT_CONFIG,
3219                                                      data);
3220                         if (ret_val)
3221                                 return ret_val;
3222                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3223                         ret_val = phy->ops.read_reg(hw,
3224                                                     IGP01E1000_PHY_PORT_CONFIG,
3225                                                     &data);
3226                         if (ret_val)
3227                                 return ret_val;
3228
3229                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3230                         ret_val = phy->ops.write_reg(hw,
3231                                                      IGP01E1000_PHY_PORT_CONFIG,
3232                                                      data);
3233                         if (ret_val)
3234                                 return ret_val;
3235                 }
3236         }
3237
3238         return E1000_SUCCESS;
3239 }
3240
3241 /**
3242  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3243  *  @hw: pointer to the HW structure
3244  *  @active: true to enable LPLU, false to disable
3245  *
3246  *  Sets the LPLU D3 state according to the active flag.  When
3247  *  activating LPLU this function also disables smart speed
3248  *  and vice versa.  LPLU will not be activated unless the
3249  *  device autonegotiation advertisement meets standards of
3250  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3251  *  This is a function pointer entry point only called by
3252  *  PHY setup routines.
3253  **/
3254 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3255 {
3256         struct e1000_phy_info *phy = &hw->phy;
3257         u32 phy_ctrl;
3258         s32 ret_val = E1000_SUCCESS;
3259         u16 data;
3260
3261         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3262
3263         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3264
3265         if (!active) {
3266                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3267                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3268
3269                 if (phy->type != e1000_phy_igp_3)
3270                         return E1000_SUCCESS;
3271
3272                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3273                  * during Dx states where the power conservation is most
3274                  * important.  During driver activity we should enable
3275                  * SmartSpeed, so performance is maintained.
3276                  */
3277                 if (phy->smart_speed == e1000_smart_speed_on) {
3278                         ret_val = phy->ops.read_reg(hw,
3279                                                     IGP01E1000_PHY_PORT_CONFIG,
3280                                                     &data);
3281                         if (ret_val)
3282                                 return ret_val;
3283
3284                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3285                         ret_val = phy->ops.write_reg(hw,
3286                                                      IGP01E1000_PHY_PORT_CONFIG,
3287                                                      data);
3288                         if (ret_val)
3289                                 return ret_val;
3290                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3291                         ret_val = phy->ops.read_reg(hw,
3292                                                     IGP01E1000_PHY_PORT_CONFIG,
3293                                                     &data);
3294                         if (ret_val)
3295                                 return ret_val;
3296
3297                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3298                         ret_val = phy->ops.write_reg(hw,
3299                                                      IGP01E1000_PHY_PORT_CONFIG,
3300                                                      data);
3301                         if (ret_val)
3302                                 return ret_val;
3303                 }
3304         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3305                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3306                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3307                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3308                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3309
3310                 if (phy->type != e1000_phy_igp_3)
3311                         return E1000_SUCCESS;
3312
3313                 /* Call gig speed drop workaround on LPLU before accessing
3314                  * any PHY registers
3315                  */
3316                 if (hw->mac.type == e1000_ich8lan)
3317                         e1000_gig_downshift_workaround_ich8lan(hw);
3318
3319                 /* When LPLU is enabled, we should disable SmartSpeed */
3320                 ret_val = phy->ops.read_reg(hw,
3321                                             IGP01E1000_PHY_PORT_CONFIG,
3322                                             &data);
3323                 if (ret_val)
3324                         return ret_val;
3325
3326                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3327                 ret_val = phy->ops.write_reg(hw,
3328                                              IGP01E1000_PHY_PORT_CONFIG,
3329                                              data);
3330         }
3331
3332         return ret_val;
3333 }
3334
3335 /**
3336  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3337  *  @hw: pointer to the HW structure
3338  *  @bank:  pointer to the variable that returns the active bank
3339  *
3340  *  Reads signature byte from the NVM using the flash access registers.
3341  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3342  **/
3343 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3344 {
3345         u32 eecd;
3346         struct e1000_nvm_info *nvm = &hw->nvm;
3347         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3348         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3349         u32 nvm_dword = 0;
3350         u8 sig_byte = 0;
3351         s32 ret_val;
3352
3353         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3354
3355         switch (hw->mac.type) {
3356         case e1000_pch_spt:
3357         case e1000_pch_cnp:
3358                 bank1_offset = nvm->flash_bank_size;
3359                 act_offset = E1000_ICH_NVM_SIG_WORD;
3360
3361                 /* set bank to 0 in case flash read fails */
3362                 *bank = 0;
3363
3364                 /* Check bank 0 */
3365                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3366                                                          &nvm_dword);
3367                 if (ret_val)
3368                         return ret_val;
3369                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3370                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3371                     E1000_ICH_NVM_SIG_VALUE) {
3372                         *bank = 0;
3373                         return E1000_SUCCESS;
3374                 }
3375
3376                 /* Check bank 1 */
3377                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3378                                                          bank1_offset,
3379                                                          &nvm_dword);
3380                 if (ret_val)
3381                         return ret_val;
3382                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3383                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3384                     E1000_ICH_NVM_SIG_VALUE) {
3385                         *bank = 1;
3386                         return E1000_SUCCESS;
3387                 }
3388
3389                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3390                 return -E1000_ERR_NVM;
3391         case e1000_ich8lan:
3392         case e1000_ich9lan:
3393                 eecd = E1000_READ_REG(hw, E1000_EECD);
3394                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3395                     E1000_EECD_SEC1VAL_VALID_MASK) {
3396                         if (eecd & E1000_EECD_SEC1VAL)
3397                                 *bank = 1;
3398                         else
3399                                 *bank = 0;
3400
3401                         return E1000_SUCCESS;
3402                 }
3403                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3404                 /* fall-thru */
3405         default:
3406                 /* set bank to 0 in case flash read fails */
3407                 *bank = 0;
3408
3409                 /* Check bank 0 */
3410                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3411                                                         &sig_byte);
3412                 if (ret_val)
3413                         return ret_val;
3414                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3415                     E1000_ICH_NVM_SIG_VALUE) {
3416                         *bank = 0;
3417                         return E1000_SUCCESS;
3418                 }
3419
3420                 /* Check bank 1 */
3421                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3422                                                         bank1_offset,
3423                                                         &sig_byte);
3424                 if (ret_val)
3425                         return ret_val;
3426                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3427                     E1000_ICH_NVM_SIG_VALUE) {
3428                         *bank = 1;
3429                         return E1000_SUCCESS;
3430                 }
3431
3432                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3433                 return -E1000_ERR_NVM;
3434         }
3435 }
3436
3437 /**
3438  *  e1000_read_nvm_spt - NVM access for SPT
3439  *  @hw: pointer to the HW structure
3440  *  @offset: The offset (in bytes) of the word(s) to read.
3441  *  @words: Size of data to read in words.
3442  *  @data: pointer to the word(s) to read at offset.
3443  *
3444  *  Reads a word(s) from the NVM
3445  **/
3446 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3447                               u16 *data)
3448 {
3449         struct e1000_nvm_info *nvm = &hw->nvm;
3450         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3451         u32 act_offset;
3452         s32 ret_val = E1000_SUCCESS;
3453         u32 bank = 0;
3454         u32 dword = 0;
3455         u16 offset_to_read;
3456         u16 i;
3457
3458         DEBUGFUNC("e1000_read_nvm_spt");
3459
3460         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3461             (words == 0)) {
3462                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3463                 ret_val = -E1000_ERR_NVM;
3464                 goto out;
3465         }
3466
3467         nvm->ops.acquire(hw);
3468
3469         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3470         if (ret_val != E1000_SUCCESS) {
3471                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3472                 bank = 0;
3473         }
3474
3475         act_offset = (bank) ? nvm->flash_bank_size : 0;
3476         act_offset += offset;
3477
3478         ret_val = E1000_SUCCESS;
3479
3480         for (i = 0; i < words; i += 2) {
3481                 if (words - i == 1) {
3482                         if (dev_spec->shadow_ram[offset + i].modified) {
3483                                 data[i] =
3484                                     dev_spec->shadow_ram[offset + i].value;
3485                         } else {
3486                                 offset_to_read = act_offset + i -
3487                                                  ((act_offset + i) % 2);
3488                                 ret_val =
3489                                    e1000_read_flash_dword_ich8lan(hw,
3490                                                                  offset_to_read,
3491                                                                  &dword);
3492                                 if (ret_val)
3493                                         break;
3494                                 if ((act_offset + i) % 2 == 0)
3495                                         data[i] = (u16)(dword & 0xFFFF);
3496                                 else
3497                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3498                         }
3499                 } else {
3500                         offset_to_read = act_offset + i;
3501                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3502                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3503                                 ret_val =
3504                                    e1000_read_flash_dword_ich8lan(hw,
3505                                                                  offset_to_read,
3506                                                                  &dword);
3507                                 if (ret_val)
3508                                         break;
3509                         }
3510                         if (dev_spec->shadow_ram[offset + i].modified)
3511                                 data[i] =
3512                                     dev_spec->shadow_ram[offset + i].value;
3513                         else
3514                                 data[i] = (u16)(dword & 0xFFFF);
3515                         if (dev_spec->shadow_ram[offset + i + 1].modified)
3516                                 data[i + 1] =
3517                                    dev_spec->shadow_ram[offset + i + 1].value;
3518                         else
3519                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3520                 }
3521         }
3522
3523         nvm->ops.release(hw);
3524
3525 out:
3526         if (ret_val)
3527                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3528
3529         return ret_val;
3530 }
3531
3532 /**
3533  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3534  *  @hw: pointer to the HW structure
3535  *  @offset: The offset (in bytes) of the word(s) to read.
3536  *  @words: Size of data to read in words
3537  *  @data: Pointer to the word(s) to read at offset.
3538  *
3539  *  Reads a word(s) from the NVM using the flash access registers.
3540  **/
3541 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3542                                   u16 *data)
3543 {
3544         struct e1000_nvm_info *nvm = &hw->nvm;
3545         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3546         u32 act_offset;
3547         s32 ret_val = E1000_SUCCESS;
3548         u32 bank = 0;
3549         u16 i, word;
3550
3551         DEBUGFUNC("e1000_read_nvm_ich8lan");
3552
3553         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3554             (words == 0)) {
3555                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3556                 ret_val = -E1000_ERR_NVM;
3557                 goto out;
3558         }
3559
3560         nvm->ops.acquire(hw);
3561
3562         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3563         if (ret_val != E1000_SUCCESS) {
3564                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3565                 bank = 0;
3566         }
3567
3568         act_offset = (bank) ? nvm->flash_bank_size : 0;
3569         act_offset += offset;
3570
3571         ret_val = E1000_SUCCESS;
3572         for (i = 0; i < words; i++) {
3573                 if (dev_spec->shadow_ram[offset + i].modified) {
3574                         data[i] = dev_spec->shadow_ram[offset + i].value;
3575                 } else {
3576                         ret_val = e1000_read_flash_word_ich8lan(hw,
3577                                                                 act_offset + i,
3578                                                                 &word);
3579                         if (ret_val)
3580                                 break;
3581                         data[i] = word;
3582                 }
3583         }
3584
3585         nvm->ops.release(hw);
3586
3587 out:
3588         if (ret_val)
3589                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3590
3591         return ret_val;
3592 }
3593
3594 /**
3595  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3596  *  @hw: pointer to the HW structure
3597  *
3598  *  This function does initial flash setup so that a new read/write/erase cycle
3599  *  can be started.
3600  **/
3601 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3602 {
3603         union ich8_hws_flash_status hsfsts;
3604         s32 ret_val = -E1000_ERR_NVM;
3605
3606         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3607
3608         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3609
3610         /* Check if the flash descriptor is valid */
3611         if (!hsfsts.hsf_status.fldesvalid) {
3612                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3613                 return -E1000_ERR_NVM;
3614         }
3615
3616         /* Clear FCERR and DAEL in hw status by writing 1 */
3617         hsfsts.hsf_status.flcerr = 1;
3618         hsfsts.hsf_status.dael = 1;
3619         if (hw->mac.type >= e1000_pch_spt)
3620                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3621                                       hsfsts.regval & 0xFFFF);
3622         else
3623                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3624
3625         /* Either we should have a hardware SPI cycle in progress
3626          * bit to check against, in order to start a new cycle or
3627          * FDONE bit should be changed in the hardware so that it
3628          * is 1 after hardware reset, which can then be used as an
3629          * indication whether a cycle is in progress or has been
3630          * completed.
3631          */
3632
3633         if (!hsfsts.hsf_status.flcinprog) {
3634                 /* There is no cycle running at present,
3635                  * so we can start a cycle.
3636                  * Begin by setting Flash Cycle Done.
3637                  */
3638                 hsfsts.hsf_status.flcdone = 1;
3639                 if (hw->mac.type >= e1000_pch_spt)
3640                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3641                                               hsfsts.regval & 0xFFFF);
3642                 else
3643                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3644                                                 hsfsts.regval);
3645                 ret_val = E1000_SUCCESS;
3646         } else {
3647                 s32 i;
3648
3649                 /* Otherwise poll for sometime so the current
3650                  * cycle has a chance to end before giving up.
3651                  */
3652                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3653                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3654                                                               ICH_FLASH_HSFSTS);
3655                         if (!hsfsts.hsf_status.flcinprog) {
3656                                 ret_val = E1000_SUCCESS;
3657                                 break;
3658                         }
3659                         usec_delay(1);
3660                 }
3661                 if (ret_val == E1000_SUCCESS) {
3662                         /* Successful in waiting for previous cycle to timeout,
3663                          * now set the Flash Cycle Done.
3664                          */
3665                         hsfsts.hsf_status.flcdone = 1;
3666                         if (hw->mac.type >= e1000_pch_spt)
3667                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3668                                                       hsfsts.regval & 0xFFFF);
3669                         else
3670                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3671                                                         hsfsts.regval);
3672                 } else {
3673                         DEBUGOUT("Flash controller busy, cannot get access\n");
3674                 }
3675         }
3676
3677         return ret_val;
3678 }
3679
3680 /**
3681  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3682  *  @hw: pointer to the HW structure
3683  *  @timeout: maximum time to wait for completion
3684  *
3685  *  This function starts a flash cycle and waits for its completion.
3686  **/
3687 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3688 {
3689         union ich8_hws_flash_ctrl hsflctl;
3690         union ich8_hws_flash_status hsfsts;
3691         u32 i = 0;
3692
3693         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3694
3695         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3696         if (hw->mac.type >= e1000_pch_spt)
3697                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3698         else
3699                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3700         hsflctl.hsf_ctrl.flcgo = 1;
3701
3702         if (hw->mac.type >= e1000_pch_spt)
3703                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3704                                       hsflctl.regval << 16);
3705         else
3706                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3707
3708         /* wait till FDONE bit is set to 1 */
3709         do {
3710                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3711                 if (hsfsts.hsf_status.flcdone)
3712                         break;
3713                 usec_delay(1);
3714         } while (i++ < timeout);
3715
3716         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3717                 return E1000_SUCCESS;
3718
3719         return -E1000_ERR_NVM;
3720 }
3721
3722 /**
3723  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3724  *  @hw: pointer to the HW structure
3725  *  @offset: offset to data location
3726  *  @data: pointer to the location for storing the data
3727  *
3728  *  Reads the flash dword at offset into data.  Offset is converted
3729  *  to bytes before read.
3730  **/
3731 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3732                                           u32 *data)
3733 {
3734         DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3735
3736         if (!data)
3737                 return -E1000_ERR_NVM;
3738
3739         /* Must convert word offset into bytes. */
3740         offset <<= 1;
3741
3742         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3743 }
3744
3745 /**
3746  *  e1000_read_flash_word_ich8lan - Read word from flash
3747  *  @hw: pointer to the HW structure
3748  *  @offset: offset to data location
3749  *  @data: pointer to the location for storing the data
3750  *
3751  *  Reads the flash word at offset into data.  Offset is converted
3752  *  to bytes before read.
3753  **/
3754 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3755                                          u16 *data)
3756 {
3757         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3758
3759         if (!data)
3760                 return -E1000_ERR_NVM;
3761
3762         /* Must convert offset into bytes. */
3763         offset <<= 1;
3764
3765         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3766 }
3767
3768 /**
3769  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3770  *  @hw: pointer to the HW structure
3771  *  @offset: The offset of the byte to read.
3772  *  @data: Pointer to a byte to store the value read.
3773  *
3774  *  Reads a single byte from the NVM using the flash access registers.
3775  **/
3776 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3777                                          u8 *data)
3778 {
3779         s32 ret_val;
3780         u16 word = 0;
3781
3782         /* In SPT, only 32 bits access is supported,
3783          * so this function should not be called.
3784          */
3785         if (hw->mac.type >= e1000_pch_spt)
3786                 return -E1000_ERR_NVM;
3787         else
3788                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3789
3790         if (ret_val)
3791                 return ret_val;
3792
3793         *data = (u8)word;
3794
3795         return E1000_SUCCESS;
3796 }
3797
3798 /**
3799  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3800  *  @hw: pointer to the HW structure
3801  *  @offset: The offset (in bytes) of the byte or word to read.
3802  *  @size: Size of data to read, 1=byte 2=word
3803  *  @data: Pointer to the word to store the value read.
3804  *
3805  *  Reads a byte or word from the NVM using the flash access registers.
3806  **/
3807 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3808                                          u8 size, u16 *data)
3809 {
3810         union ich8_hws_flash_status hsfsts;
3811         union ich8_hws_flash_ctrl hsflctl;
3812         u32 flash_linear_addr;
3813         u32 flash_data = 0;
3814         s32 ret_val = -E1000_ERR_NVM;
3815         u8 count = 0;
3816
3817         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3818
3819         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3820                 return -E1000_ERR_NVM;
3821         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3822                              hw->nvm.flash_base_addr);
3823
3824         do {
3825                 usec_delay(1);
3826                 /* Steps */
3827                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3828                 if (ret_val != E1000_SUCCESS)
3829                         break;
3830                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3831
3832                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3833                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3834                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3835                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3836                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3837
3838                 ret_val = e1000_flash_cycle_ich8lan(hw,
3839                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3840
3841                 /* Check if FCERR is set to 1, if set to 1, clear it
3842                  * and try the whole sequence a few more times, else
3843                  * read in (shift in) the Flash Data0, the order is
3844                  * least significant byte first msb to lsb
3845                  */
3846                 if (ret_val == E1000_SUCCESS) {
3847                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3848                         if (size == 1)
3849                                 *data = (u8)(flash_data & 0x000000FF);
3850                         else if (size == 2)
3851                                 *data = (u16)(flash_data & 0x0000FFFF);
3852                         break;
3853                 } else {
3854                         /* If we've gotten here, then things are probably
3855                          * completely hosed, but if the error condition is
3856                          * detected, it won't hurt to give it another try...
3857                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3858                          */
3859                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3860                                                               ICH_FLASH_HSFSTS);
3861                         if (hsfsts.hsf_status.flcerr) {
3862                                 /* Repeat for some time before giving up. */
3863                                 continue;
3864                         } else if (!hsfsts.hsf_status.flcdone) {
3865                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3866                                 break;
3867                         }
3868                 }
3869         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3870
3871         return ret_val;
3872 }
3873
3874 /**
3875  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3876  *  @hw: pointer to the HW structure
3877  *  @offset: The offset (in bytes) of the dword to read.
3878  *  @data: Pointer to the dword to store the value read.
3879  *
3880  *  Reads a byte or word from the NVM using the flash access registers.
3881  **/
3882 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3883                                            u32 *data)
3884 {
3885         union ich8_hws_flash_status hsfsts;
3886         union ich8_hws_flash_ctrl hsflctl;
3887         u32 flash_linear_addr;
3888         s32 ret_val = -E1000_ERR_NVM;
3889         u8 count = 0;
3890
3891         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3892
3893                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3894                     hw->mac.type < e1000_pch_spt)
3895                         return -E1000_ERR_NVM;
3896         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3897                              hw->nvm.flash_base_addr);
3898
3899         do {
3900                 usec_delay(1);
3901                 /* Steps */
3902                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3903                 if (ret_val != E1000_SUCCESS)
3904                         break;
3905                 /* In SPT, This register is in Lan memory space, not flash.
3906                  * Therefore, only 32 bit access is supported
3907                  */
3908                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3909
3910                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3911                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3912                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3913                 /* In SPT, This register is in Lan memory space, not flash.
3914                  * Therefore, only 32 bit access is supported
3915                  */
3916                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3917                                       (u32)hsflctl.regval << 16);
3918                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3919
3920                 ret_val = e1000_flash_cycle_ich8lan(hw,
3921                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3922
3923                 /* Check if FCERR is set to 1, if set to 1, clear it
3924                  * and try the whole sequence a few more times, else
3925                  * read in (shift in) the Flash Data0, the order is
3926                  * least significant byte first msb to lsb
3927                  */
3928                 if (ret_val == E1000_SUCCESS) {
3929                         *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3930                         break;
3931                 } else {
3932                         /* If we've gotten here, then things are probably
3933                          * completely hosed, but if the error condition is
3934                          * detected, it won't hurt to give it another try...
3935                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3936                          */
3937                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3938                                                               ICH_FLASH_HSFSTS);
3939                         if (hsfsts.hsf_status.flcerr) {
3940                                 /* Repeat for some time before giving up. */
3941                                 continue;
3942                         } else if (!hsfsts.hsf_status.flcdone) {
3943                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3944                                 break;
3945                         }
3946                 }
3947         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3948
3949         return ret_val;
3950 }
3951
3952 /**
3953  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3954  *  @hw: pointer to the HW structure
3955  *  @offset: The offset (in bytes) of the word(s) to write.
3956  *  @words: Size of data to write in words
3957  *  @data: Pointer to the word(s) to write at offset.
3958  *
3959  *  Writes a byte or word to the NVM using the flash access registers.
3960  **/
3961 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3962                                    u16 *data)
3963 {
3964         struct e1000_nvm_info *nvm = &hw->nvm;
3965         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3966         u16 i;
3967
3968         DEBUGFUNC("e1000_write_nvm_ich8lan");
3969
3970         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3971             (words == 0)) {
3972                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3973                 return -E1000_ERR_NVM;
3974         }
3975
3976         nvm->ops.acquire(hw);
3977
3978         for (i = 0; i < words; i++) {
3979                 dev_spec->shadow_ram[offset + i].modified = true;
3980                 dev_spec->shadow_ram[offset + i].value = data[i];
3981         }
3982
3983         nvm->ops.release(hw);
3984
3985         return E1000_SUCCESS;
3986 }
3987
3988 /**
3989  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3990  *  @hw: pointer to the HW structure
3991  *
3992  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3993  *  which writes the checksum to the shadow ram.  The changes in the shadow
3994  *  ram are then committed to the EEPROM by processing each bank at a time
3995  *  checking for the modified bit and writing only the pending changes.
3996  *  After a successful commit, the shadow ram is cleared and is ready for
3997  *  future writes.
3998  **/
3999 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4000 {
4001         struct e1000_nvm_info *nvm = &hw->nvm;
4002         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4003         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4004         s32 ret_val;
4005         u32 dword = 0;
4006
4007         DEBUGFUNC("e1000_update_nvm_checksum_spt");
4008
4009         ret_val = e1000_update_nvm_checksum_generic(hw);
4010         if (ret_val)
4011                 goto out;
4012
4013         if (nvm->type != e1000_nvm_flash_sw)
4014                 goto out;
4015
4016         nvm->ops.acquire(hw);
4017
4018         /* We're writing to the opposite bank so if we're on bank 1,
4019          * write to bank 0 etc.  We also need to erase the segment that
4020          * is going to be written
4021          */
4022         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4023         if (ret_val != E1000_SUCCESS) {
4024                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4025                 bank = 0;
4026         }
4027
4028         if (bank == 0) {
4029                 new_bank_offset = nvm->flash_bank_size;
4030                 old_bank_offset = 0;
4031                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4032                 if (ret_val)
4033                         goto release;
4034         } else {
4035                 old_bank_offset = nvm->flash_bank_size;
4036                 new_bank_offset = 0;
4037                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4038                 if (ret_val)
4039                         goto release;
4040         }
4041         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4042                 /* Determine whether to write the value stored
4043                  * in the other NVM bank or a modified value stored
4044                  * in the shadow RAM
4045                  */
4046                 ret_val = e1000_read_flash_dword_ich8lan(hw,
4047                                                          i + old_bank_offset,
4048                                                          &dword);
4049
4050                 if (dev_spec->shadow_ram[i].modified) {
4051                         dword &= 0xffff0000;
4052                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4053                 }
4054                 if (dev_spec->shadow_ram[i + 1].modified) {
4055                         dword &= 0x0000ffff;
4056                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4057                                   << 16);
4058                 }
4059                 if (ret_val)
4060                         break;
4061
4062                 /* If the word is 0x13, then make sure the signature bits
4063                  * (15:14) are 11b until the commit has completed.
4064                  * This will allow us to write 10b which indicates the
4065                  * signature is valid.  We want to do this after the write
4066                  * has completed so that we don't mark the segment valid
4067                  * while the write is still in progress
4068                  */
4069                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4070                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
4071
4072                 /* Convert offset to bytes. */
4073                 act_offset = (i + new_bank_offset) << 1;
4074
4075                 usec_delay(100);
4076
4077                 /* Write the data to the new bank. Offset in words*/
4078                 act_offset = i + new_bank_offset;
4079                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4080                                                                 dword);
4081                 if (ret_val)
4082                         break;
4083          }
4084
4085         /* Don't bother writing the segment valid bits if sector
4086          * programming failed.
4087          */
4088         if (ret_val) {
4089                 DEBUGOUT("Flash commit failed.\n");
4090                 goto release;
4091         }
4092
4093         /* Finally validate the new segment by setting bit 15:14
4094          * to 10b in word 0x13 , this can be done without an
4095          * erase as well since these bits are 11 to start with
4096          * and we need to change bit 14 to 0b
4097          */
4098         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4099
4100         /*offset in words but we read dword*/
4101         --act_offset;
4102         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4103
4104         if (ret_val)
4105                 goto release;
4106
4107         dword &= 0xBFFFFFFF;
4108         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4109
4110         if (ret_val)
4111                 goto release;
4112
4113         /* And invalidate the previously valid segment by setting
4114          * its signature word (0x13) high_byte to 0b. This can be
4115          * done without an erase because flash erase sets all bits
4116          * to 1's. We can write 1's to 0's without an erase
4117          */
4118         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4119
4120         /* offset in words but we read dword*/
4121         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4122         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4123
4124         if (ret_val)
4125                 goto release;
4126
4127         dword &= 0x00FFFFFF;
4128         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4129
4130         if (ret_val)
4131                 goto release;
4132
4133         /* Great!  Everything worked, we can now clear the cached entries. */
4134         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4135                 dev_spec->shadow_ram[i].modified = false;
4136                 dev_spec->shadow_ram[i].value = 0xFFFF;
4137         }
4138
4139 release:
4140         nvm->ops.release(hw);
4141
4142         /* Reload the EEPROM, or else modifications will not appear
4143          * until after the next adapter reset.
4144          */
4145         if (!ret_val) {
4146                 nvm->ops.reload(hw);
4147                 msec_delay(10);
4148         }
4149
4150 out:
4151         if (ret_val)
4152                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4153
4154         return ret_val;
4155 }
4156
4157 /**
4158  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4159  *  @hw: pointer to the HW structure
4160  *
4161  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
4162  *  which writes the checksum to the shadow ram.  The changes in the shadow
4163  *  ram are then committed to the EEPROM by processing each bank at a time
4164  *  checking for the modified bit and writing only the pending changes.
4165  *  After a successful commit, the shadow ram is cleared and is ready for
4166  *  future writes.
4167  **/
4168 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4169 {
4170         struct e1000_nvm_info *nvm = &hw->nvm;
4171         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4172         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4173         s32 ret_val;
4174         u16 data = 0;
4175
4176         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4177
4178         ret_val = e1000_update_nvm_checksum_generic(hw);
4179         if (ret_val)
4180                 goto out;
4181
4182         if (nvm->type != e1000_nvm_flash_sw)
4183                 goto out;
4184
4185         nvm->ops.acquire(hw);
4186
4187         /* We're writing to the opposite bank so if we're on bank 1,
4188          * write to bank 0 etc.  We also need to erase the segment that
4189          * is going to be written
4190          */
4191         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4192         if (ret_val != E1000_SUCCESS) {
4193                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4194                 bank = 0;
4195         }
4196
4197         if (bank == 0) {
4198                 new_bank_offset = nvm->flash_bank_size;
4199                 old_bank_offset = 0;
4200                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4201                 if (ret_val)
4202                         goto release;
4203         } else {
4204                 old_bank_offset = nvm->flash_bank_size;
4205                 new_bank_offset = 0;
4206                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4207                 if (ret_val)
4208                         goto release;
4209         }
4210         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4211                 if (dev_spec->shadow_ram[i].modified) {
4212                         data = dev_spec->shadow_ram[i].value;
4213                 } else {
4214                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
4215                                                                 old_bank_offset,
4216                                                                 &data);
4217                         if (ret_val)
4218                                 break;
4219                 }
4220                 /* If the word is 0x13, then make sure the signature bits
4221                  * (15:14) are 11b until the commit has completed.
4222                  * This will allow us to write 10b which indicates the
4223                  * signature is valid.  We want to do this after the write
4224                  * has completed so that we don't mark the segment valid
4225                  * while the write is still in progress
4226                  */
4227                 if (i == E1000_ICH_NVM_SIG_WORD)
4228                         data |= E1000_ICH_NVM_SIG_MASK;
4229
4230                 /* Convert offset to bytes. */
4231                 act_offset = (i + new_bank_offset) << 1;
4232
4233                 usec_delay(100);
4234
4235                 /* Write the bytes to the new bank. */
4236                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4237                                                                act_offset,
4238                                                                (u8)data);
4239                 if (ret_val)
4240                         break;
4241
4242                 usec_delay(100);
4243                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4244                                                           act_offset + 1,
4245                                                           (u8)(data >> 8));
4246                 if (ret_val)
4247                         break;
4248         }
4249
4250         /* Don't bother writing the segment valid bits if sector
4251          * programming failed.
4252          */
4253         if (ret_val) {
4254                 DEBUGOUT("Flash commit failed.\n");
4255                 goto release;
4256         }
4257
4258         /* Finally validate the new segment by setting bit 15:14
4259          * to 10b in word 0x13 , this can be done without an
4260          * erase as well since these bits are 11 to start with
4261          * and we need to change bit 14 to 0b
4262          */
4263         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4264         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4265         if (ret_val)
4266                 goto release;
4267
4268         data &= 0xBFFF;
4269         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4270                                                        (u8)(data >> 8));
4271         if (ret_val)
4272                 goto release;
4273
4274         /* And invalidate the previously valid segment by setting
4275          * its signature word (0x13) high_byte to 0b. This can be
4276          * done without an erase because flash erase sets all bits
4277          * to 1's. We can write 1's to 0's without an erase
4278          */
4279         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4280
4281         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4282
4283         if (ret_val)
4284                 goto release;
4285
4286         /* Great!  Everything worked, we can now clear the cached entries. */
4287         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4288                 dev_spec->shadow_ram[i].modified = false;
4289                 dev_spec->shadow_ram[i].value = 0xFFFF;
4290         }
4291
4292 release:
4293         nvm->ops.release(hw);
4294
4295         /* Reload the EEPROM, or else modifications will not appear
4296          * until after the next adapter reset.
4297          */
4298         if (!ret_val) {
4299                 nvm->ops.reload(hw);
4300                 msec_delay(10);
4301         }
4302
4303 out:
4304         if (ret_val)
4305                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4306
4307         return ret_val;
4308 }
4309
4310 /**
4311  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4312  *  @hw: pointer to the HW structure
4313  *
4314  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4315  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4316  *  calculated, in which case we need to calculate the checksum and set bit 6.
4317  **/
4318 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4319 {
4320         s32 ret_val;
4321         u16 data;
4322         u16 word;
4323         u16 valid_csum_mask;
4324
4325         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4326
4327         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4328          * the checksum needs to be fixed.  This bit is an indication that
4329          * the NVM was prepared by OEM software and did not calculate
4330          * the checksum...a likely scenario.
4331          */
4332         switch (hw->mac.type) {
4333         case e1000_pch_lpt:
4334         case e1000_pch_spt:
4335         case e1000_pch_cnp:
4336                 word = NVM_COMPAT;
4337                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4338                 break;
4339         default:
4340                 word = NVM_FUTURE_INIT_WORD1;
4341                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4342                 break;
4343         }
4344
4345         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4346         if (ret_val)
4347                 return ret_val;
4348
4349         if (!(data & valid_csum_mask)) {
4350                 data |= valid_csum_mask;
4351                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4352                 if (ret_val)
4353                         return ret_val;
4354                 ret_val = hw->nvm.ops.update(hw);
4355                 if (ret_val)
4356                         return ret_val;
4357         }
4358
4359         return e1000_validate_nvm_checksum_generic(hw);
4360 }
4361
4362 /**
4363  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4364  *  @hw: pointer to the HW structure
4365  *  @offset: The offset (in bytes) of the byte/word to read.
4366  *  @size: Size of data to read, 1=byte 2=word
4367  *  @data: The byte(s) to write to the NVM.
4368  *
4369  *  Writes one/two bytes to the NVM using the flash access registers.
4370  **/
4371 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4372                                           u8 size, u16 data)
4373 {
4374         union ich8_hws_flash_status hsfsts;
4375         union ich8_hws_flash_ctrl hsflctl;
4376         u32 flash_linear_addr;
4377         u32 flash_data = 0;
4378         s32 ret_val;
4379         u8 count = 0;
4380
4381         DEBUGFUNC("e1000_write_ich8_data");
4382
4383         if (hw->mac.type >= e1000_pch_spt) {
4384                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4385                         return -E1000_ERR_NVM;
4386         } else {
4387                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4388                         return -E1000_ERR_NVM;
4389         }
4390
4391         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4392                              hw->nvm.flash_base_addr);
4393
4394         do {
4395                 usec_delay(1);
4396                 /* Steps */
4397                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4398                 if (ret_val != E1000_SUCCESS)
4399                         break;
4400                 /* In SPT, This register is in Lan memory space, not
4401                  * flash.  Therefore, only 32 bit access is supported
4402                  */
4403                 if (hw->mac.type >= e1000_pch_spt)
4404                         hsflctl.regval =
4405                             E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4406                 else
4407                         hsflctl.regval =
4408                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4409
4410                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4411                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4412                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4413                 /* In SPT, This register is in Lan memory space,
4414                  * not flash.  Therefore, only 32 bit access is
4415                  * supported
4416                  */
4417                 if (hw->mac.type >= e1000_pch_spt)
4418                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4419                                               hsflctl.regval << 16);
4420                 else
4421                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4422                                                 hsflctl.regval);
4423
4424                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4425
4426                 if (size == 1)
4427                         flash_data = (u32)data & 0x00FF;
4428                 else
4429                         flash_data = (u32)data;
4430
4431                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4432
4433                 /* check if FCERR is set to 1 , if set to 1, clear it
4434                  * and try the whole sequence a few more times else done
4435                  */
4436                 ret_val =
4437                     e1000_flash_cycle_ich8lan(hw,
4438                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4439                 if (ret_val == E1000_SUCCESS)
4440                         break;
4441
4442                 /* If we're here, then things are most likely
4443                  * completely hosed, but if the error condition
4444                  * is detected, it won't hurt to give it another
4445                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4446                  */
4447                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4448                 if (hsfsts.hsf_status.flcerr)
4449                         /* Repeat for some time before giving up. */
4450                         continue;
4451                 if (!hsfsts.hsf_status.flcdone) {
4452                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4453                         break;
4454                 }
4455         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4456
4457         return ret_val;
4458 }
4459
4460 /**
4461 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4462 *  @hw: pointer to the HW structure
4463 *  @offset: The offset (in bytes) of the dwords to read.
4464 *  @data: The 4 bytes to write to the NVM.
4465 *
4466 *  Writes one/two/four bytes to the NVM using the flash access registers.
4467 **/
4468 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4469                                             u32 data)
4470 {
4471         union ich8_hws_flash_status hsfsts;
4472         union ich8_hws_flash_ctrl hsflctl;
4473         u32 flash_linear_addr;
4474         s32 ret_val;
4475         u8 count = 0;
4476
4477         DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4478
4479         if (hw->mac.type >= e1000_pch_spt) {
4480                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4481                         return -E1000_ERR_NVM;
4482         }
4483         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4484                              hw->nvm.flash_base_addr);
4485         do {
4486                 usec_delay(1);
4487                 /* Steps */
4488                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4489                 if (ret_val != E1000_SUCCESS)
4490                         break;
4491
4492                 /* In SPT, This register is in Lan memory space, not
4493                  * flash.  Therefore, only 32 bit access is supported
4494                  */
4495                 if (hw->mac.type >= e1000_pch_spt)
4496                         hsflctl.regval = E1000_READ_FLASH_REG(hw,
4497                                                               ICH_FLASH_HSFSTS)
4498                                          >> 16;
4499                 else
4500                         hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4501                                                               ICH_FLASH_HSFCTL);
4502
4503                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4504                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4505
4506                 /* In SPT, This register is in Lan memory space,
4507                  * not flash.  Therefore, only 32 bit access is
4508                  * supported
4509                  */
4510                 if (hw->mac.type >= e1000_pch_spt)
4511                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4512                                               hsflctl.regval << 16);
4513                 else
4514                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4515                                                 hsflctl.regval);
4516
4517                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4518
4519                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4520
4521                 /* check if FCERR is set to 1 , if set to 1, clear it
4522                  * and try the whole sequence a few more times else done
4523                  */
4524                 ret_val = e1000_flash_cycle_ich8lan(hw,
4525                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4526
4527                 if (ret_val == E1000_SUCCESS)
4528                         break;
4529
4530                 /* If we're here, then things are most likely
4531                  * completely hosed, but if the error condition
4532                  * is detected, it won't hurt to give it another
4533                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4534                  */
4535                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4536
4537                 if (hsfsts.hsf_status.flcerr)
4538                         /* Repeat for some time before giving up. */
4539                         continue;
4540                 if (!hsfsts.hsf_status.flcdone) {
4541                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4542                         break;
4543                 }
4544         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4545
4546         return ret_val;
4547 }
4548
4549 /**
4550  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4551  *  @hw: pointer to the HW structure
4552  *  @offset: The index of the byte to read.
4553  *  @data: The byte to write to the NVM.
4554  *
4555  *  Writes a single byte to the NVM using the flash access registers.
4556  **/
4557 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4558                                           u8 data)
4559 {
4560         u16 word = (u16)data;
4561
4562         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4563
4564         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4565 }
4566
4567 /**
4568 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4569 *  @hw: pointer to the HW structure
4570 *  @offset: The offset of the word to write.
4571 *  @dword: The dword to write to the NVM.
4572 *
4573 *  Writes a single dword to the NVM using the flash access registers.
4574 *  Goes through a retry algorithm before giving up.
4575 **/
4576 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4577                                                  u32 offset, u32 dword)
4578 {
4579         s32 ret_val;
4580         u16 program_retries;
4581
4582         DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4583
4584         /* Must convert word offset into bytes. */
4585         offset <<= 1;
4586
4587         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4588
4589         if (!ret_val)
4590                 return ret_val;
4591         for (program_retries = 0; program_retries < 100; program_retries++) {
4592                 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4593                 usec_delay(100);
4594                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4595                 if (ret_val == E1000_SUCCESS)
4596                         break;
4597         }
4598         if (program_retries == 100)
4599                 return -E1000_ERR_NVM;
4600
4601         return E1000_SUCCESS;
4602 }
4603
4604 /**
4605  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4606  *  @hw: pointer to the HW structure
4607  *  @offset: The offset of the byte to write.
4608  *  @byte: The byte to write to the NVM.
4609  *
4610  *  Writes a single byte to the NVM using the flash access registers.
4611  *  Goes through a retry algorithm before giving up.
4612  **/
4613 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4614                                                 u32 offset, u8 byte)
4615 {
4616         s32 ret_val;
4617         u16 program_retries;
4618
4619         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4620
4621         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4622         if (!ret_val)
4623                 return ret_val;
4624
4625         for (program_retries = 0; program_retries < 100; program_retries++) {
4626                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4627                 usec_delay(100);
4628                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4629                 if (ret_val == E1000_SUCCESS)
4630                         break;
4631         }
4632         if (program_retries == 100)
4633                 return -E1000_ERR_NVM;
4634
4635         return E1000_SUCCESS;
4636 }
4637
4638 /**
4639  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4640  *  @hw: pointer to the HW structure
4641  *  @bank: 0 for first bank, 1 for second bank, etc.
4642  *
4643  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4644  *  bank N is 4096 * N + flash_reg_addr.
4645  **/
4646 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4647 {
4648         struct e1000_nvm_info *nvm = &hw->nvm;
4649         union ich8_hws_flash_status hsfsts;
4650         union ich8_hws_flash_ctrl hsflctl;
4651         u32 flash_linear_addr;
4652         /* bank size is in 16bit words - adjust to bytes */
4653         u32 flash_bank_size = nvm->flash_bank_size * 2;
4654         s32 ret_val;
4655         s32 count = 0;
4656         s32 j, iteration, sector_size;
4657
4658         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4659
4660         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4661
4662         /* Determine HW Sector size: Read BERASE bits of hw flash status
4663          * register
4664          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4665          *     consecutive sectors.  The start index for the nth Hw sector
4666          *     can be calculated as = bank * 4096 + n * 256
4667          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4668          *     The start index for the nth Hw sector can be calculated
4669          *     as = bank * 4096
4670          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4671          *     (ich9 only, otherwise error condition)
4672          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4673          */
4674         switch (hsfsts.hsf_status.berasesz) {
4675         case 0:
4676                 /* Hw sector size 256 */
4677                 sector_size = ICH_FLASH_SEG_SIZE_256;
4678                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4679                 break;
4680         case 1:
4681                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4682                 iteration = 1;
4683                 break;
4684         case 2:
4685                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4686                 iteration = 1;
4687                 break;
4688         case 3:
4689                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4690                 iteration = 1;
4691                 break;
4692         default:
4693                 return -E1000_ERR_NVM;
4694         }
4695
4696         /* Start with the base address, then add the sector offset. */
4697         flash_linear_addr = hw->nvm.flash_base_addr;
4698         flash_linear_addr += (bank) ? flash_bank_size : 0;
4699
4700         for (j = 0; j < iteration; j++) {
4701                 do {
4702                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4703
4704                         /* Steps */
4705                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4706                         if (ret_val)
4707                                 return ret_val;
4708
4709                         /* Write a value 11 (block Erase) in Flash
4710                          * Cycle field in hw flash control
4711                          */
4712                         if (hw->mac.type >= e1000_pch_spt)
4713                                 hsflctl.regval =
4714                                     E1000_READ_FLASH_REG(hw,
4715                                                          ICH_FLASH_HSFSTS)>>16;
4716                         else
4717                                 hsflctl.regval =
4718                                     E1000_READ_FLASH_REG16(hw,
4719                                                            ICH_FLASH_HSFCTL);
4720
4721                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4722                         if (hw->mac.type >= e1000_pch_spt)
4723                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4724                                                       hsflctl.regval << 16);
4725                         else
4726                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4727                                                         hsflctl.regval);
4728
4729                         /* Write the last 24 bits of an index within the
4730                          * block into Flash Linear address field in Flash
4731                          * Address.
4732                          */
4733                         flash_linear_addr += (j * sector_size);
4734                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4735                                               flash_linear_addr);
4736
4737                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4738                         if (ret_val == E1000_SUCCESS)
4739                                 break;
4740
4741                         /* Check if FCERR is set to 1.  If 1,
4742                          * clear it and try the whole sequence
4743                          * a few more times else Done
4744                          */
4745                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4746                                                       ICH_FLASH_HSFSTS);
4747                         if (hsfsts.hsf_status.flcerr)
4748                                 /* repeat for some time before giving up */
4749                                 continue;
4750                         else if (!hsfsts.hsf_status.flcdone)
4751                                 return ret_val;
4752                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4753         }
4754
4755         return E1000_SUCCESS;
4756 }
4757
4758 /**
4759  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4760  *  @hw: pointer to the HW structure
4761  *  @data: Pointer to the LED settings
4762  *
4763  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4764  *  settings is all 0's or F's, set the LED default to a valid LED default
4765  *  setting.
4766  **/
4767 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4768 {
4769         s32 ret_val;
4770
4771         DEBUGFUNC("e1000_valid_led_default_ich8lan");
4772
4773         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4774         if (ret_val) {
4775                 DEBUGOUT("NVM Read Error\n");
4776                 return ret_val;
4777         }
4778
4779         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4780                 *data = ID_LED_DEFAULT_ICH8LAN;
4781
4782         return E1000_SUCCESS;
4783 }
4784
4785 /**
4786  *  e1000_id_led_init_pchlan - store LED configurations
4787  *  @hw: pointer to the HW structure
4788  *
4789  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4790  *  the PHY LED configuration register.
4791  *
4792  *  PCH also does not have an "always on" or "always off" mode which
4793  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4794  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4795  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4796  *  link based on logic in e1000_led_[on|off]_pchlan().
4797  **/
4798 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4799 {
4800         struct e1000_mac_info *mac = &hw->mac;
4801         s32 ret_val;
4802         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4803         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4804         u16 data, i, temp, shift;
4805
4806         DEBUGFUNC("e1000_id_led_init_pchlan");
4807
4808         /* Get default ID LED modes */
4809         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4810         if (ret_val)
4811                 return ret_val;
4812
4813         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4814         mac->ledctl_mode1 = mac->ledctl_default;
4815         mac->ledctl_mode2 = mac->ledctl_default;
4816
4817         for (i = 0; i < 4; i++) {
4818                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4819                 shift = (i * 5);
4820                 switch (temp) {
4821                 case ID_LED_ON1_DEF2:
4822                 case ID_LED_ON1_ON2:
4823                 case ID_LED_ON1_OFF2:
4824                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4825                         mac->ledctl_mode1 |= (ledctl_on << shift);
4826                         break;
4827                 case ID_LED_OFF1_DEF2:
4828                 case ID_LED_OFF1_ON2:
4829                 case ID_LED_OFF1_OFF2:
4830                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4831                         mac->ledctl_mode1 |= (ledctl_off << shift);
4832                         break;
4833                 default:
4834                         /* Do nothing */
4835                         break;
4836                 }
4837                 switch (temp) {
4838                 case ID_LED_DEF1_ON2:
4839                 case ID_LED_ON1_ON2:
4840                 case ID_LED_OFF1_ON2:
4841                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4842                         mac->ledctl_mode2 |= (ledctl_on << shift);
4843                         break;
4844                 case ID_LED_DEF1_OFF2:
4845                 case ID_LED_ON1_OFF2:
4846                 case ID_LED_OFF1_OFF2:
4847                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4848                         mac->ledctl_mode2 |= (ledctl_off << shift);
4849                         break;
4850                 default:
4851                         /* Do nothing */
4852                         break;
4853                 }
4854         }
4855
4856         return E1000_SUCCESS;
4857 }
4858
4859 /**
4860  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4861  *  @hw: pointer to the HW structure
4862  *
4863  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4864  *  register, so the bus width is hard coded.
4865  **/
4866 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4867 {
4868         struct e1000_bus_info *bus = &hw->bus;
4869         s32 ret_val;
4870
4871         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4872
4873         ret_val = e1000_get_bus_info_pcie_generic(hw);
4874
4875         /* ICH devices are "PCI Express"-ish.  They have
4876          * a configuration space, but do not contain
4877          * PCI Express Capability registers, so bus width
4878          * must be hardcoded.
4879          */
4880         if (bus->width == e1000_bus_width_unknown)
4881                 bus->width = e1000_bus_width_pcie_x1;
4882
4883         return ret_val;
4884 }
4885
4886 /**
4887  *  e1000_reset_hw_ich8lan - Reset the hardware
4888  *  @hw: pointer to the HW structure
4889  *
4890  *  Does a full reset of the hardware which includes a reset of the PHY and
4891  *  MAC.
4892  **/
4893 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4894 {
4895         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4896         u16 kum_cfg;
4897         u32 ctrl, reg;
4898         s32 ret_val;
4899
4900         DEBUGFUNC("e1000_reset_hw_ich8lan");
4901
4902         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4903          * on the last TLP read/write transaction when MAC is reset.
4904          */
4905         ret_val = e1000_disable_pcie_master_generic(hw);
4906         if (ret_val)
4907                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4908
4909         DEBUGOUT("Masking off all interrupts\n");
4910         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4911
4912         /* Disable the Transmit and Receive units.  Then delay to allow
4913          * any pending transactions to complete before we hit the MAC
4914          * with the global reset.
4915          */
4916         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4917         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4918         E1000_WRITE_FLUSH(hw);
4919
4920         msec_delay(10);
4921
4922         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4923         if (hw->mac.type == e1000_ich8lan) {
4924                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4925                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4926                 /* Set Packet Buffer Size to 16k. */
4927                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4928         }
4929
4930         if (hw->mac.type == e1000_pchlan) {
4931                 /* Save the NVM K1 bit setting*/
4932                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4933                 if (ret_val)
4934                         return ret_val;
4935
4936                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4937                         dev_spec->nvm_k1_enabled = true;
4938                 else
4939                         dev_spec->nvm_k1_enabled = false;
4940         }
4941
4942         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4943
4944         if (!hw->phy.ops.check_reset_block(hw)) {
4945                 /* Full-chip reset requires MAC and PHY reset at the same
4946                  * time to make sure the interface between MAC and the
4947                  * external PHY is reset.
4948                  */
4949                 ctrl |= E1000_CTRL_PHY_RST;
4950
4951                 /* Gate automatic PHY configuration by hardware on
4952                  * non-managed 82579
4953                  */
4954                 if ((hw->mac.type == e1000_pch2lan) &&
4955                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4956                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4957         }
4958         ret_val = e1000_acquire_swflag_ich8lan(hw);
4959         DEBUGOUT("Issuing a global reset to ich8lan\n");
4960         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4961         /* cannot issue a flush here because it hangs the hardware */
4962         msec_delay(20);
4963
4964         /* Set Phy Config Counter to 50msec */
4965         if (hw->mac.type == e1000_pch2lan) {
4966                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4967                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4968                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4969                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4970         }
4971
4972         if (!ret_val)
4973                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4974
4975         if (ctrl & E1000_CTRL_PHY_RST) {
4976                 ret_val = hw->phy.ops.get_cfg_done(hw);
4977                 if (ret_val)
4978                         return ret_val;
4979
4980                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4981                 if (ret_val)
4982                         return ret_val;
4983         }
4984
4985         /* For PCH, this write will make sure that any noise
4986          * will be detected as a CRC error and be dropped rather than show up
4987          * as a bad packet to the DMA engine.
4988          */
4989         if (hw->mac.type == e1000_pchlan)
4990                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4991
4992         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4993         E1000_READ_REG(hw, E1000_ICR);
4994
4995         reg = E1000_READ_REG(hw, E1000_KABGTXD);
4996         reg |= E1000_KABGTXD_BGSQLBIAS;
4997         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4998
4999         return E1000_SUCCESS;
5000 }
5001
5002 /**
5003  *  e1000_init_hw_ich8lan - Initialize the hardware
5004  *  @hw: pointer to the HW structure
5005  *
5006  *  Prepares the hardware for transmit and receive by doing the following:
5007  *   - initialize hardware bits
5008  *   - initialize LED identification
5009  *   - setup receive address registers
5010  *   - setup flow control
5011  *   - setup transmit descriptors
5012  *   - clear statistics
5013  **/
5014 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5015 {
5016         struct e1000_mac_info *mac = &hw->mac;
5017         u32 ctrl_ext, txdctl, snoop;
5018         s32 ret_val;
5019         u16 i;
5020
5021         DEBUGFUNC("e1000_init_hw_ich8lan");
5022
5023         e1000_initialize_hw_bits_ich8lan(hw);
5024
5025         /* Initialize identification LED */
5026         ret_val = mac->ops.id_led_init(hw);
5027         /* An error is not fatal and we should not stop init due to this */
5028         if (ret_val)
5029                 DEBUGOUT("Error initializing identification LED\n");
5030
5031         /* Setup the receive address. */
5032         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5033
5034         /* Zero out the Multicast HASH table */
5035         DEBUGOUT("Zeroing the MTA\n");
5036         for (i = 0; i < mac->mta_reg_count; i++)
5037                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5038
5039         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5040          * the ME.  Disable wakeup by clearing the host wakeup bit.
5041          * Reset the phy after disabling host wakeup to reset the Rx buffer.
5042          */
5043         if (hw->phy.type == e1000_phy_82578) {
5044                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5045                 i &= ~BM_WUC_HOST_WU_BIT;
5046                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5047                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5048                 if (ret_val)
5049                         return ret_val;
5050         }
5051
5052         /* Setup link and flow control */
5053         ret_val = mac->ops.setup_link(hw);
5054
5055         /* Set the transmit descriptor write-back policy for both queues */
5056         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5057         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5058                   E1000_TXDCTL_FULL_TX_DESC_WB);
5059         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5060                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5061         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5062         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5063         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5064                   E1000_TXDCTL_FULL_TX_DESC_WB);
5065         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5066                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5067         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5068
5069         /* ICH8 has opposite polarity of no_snoop bits.
5070          * By default, we should use snoop behavior.
5071          */
5072         if (mac->type == e1000_ich8lan)
5073                 snoop = PCIE_ICH8_SNOOP_ALL;
5074         else
5075                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5076         e1000_set_pcie_no_snoop_generic(hw, snoop);
5077
5078         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5079         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5080         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5081
5082         /* Clear all of the statistics registers (clear on read).  It is
5083          * important that we do this after we have tried to establish link
5084          * because the symbol error count will increment wildly if there
5085          * is no link.
5086          */
5087         e1000_clear_hw_cntrs_ich8lan(hw);
5088
5089         return ret_val;
5090 }
5091
5092 /**
5093  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5094  *  @hw: pointer to the HW structure
5095  *
5096  *  Sets/Clears required hardware bits necessary for correctly setting up the
5097  *  hardware for transmit and receive.
5098  **/
5099 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5100 {
5101         u32 reg;
5102
5103         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5104
5105         /* Extended Device Control */
5106         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5107         reg |= (1 << 22);
5108         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5109         if (hw->mac.type >= e1000_pchlan)
5110                 reg |= E1000_CTRL_EXT_PHYPDEN;
5111         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5112
5113         /* Transmit Descriptor Control 0 */
5114         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5115         reg |= (1 << 22);
5116         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5117
5118         /* Transmit Descriptor Control 1 */
5119         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5120         reg |= (1 << 22);
5121         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5122
5123         /* Transmit Arbitration Control 0 */
5124         reg = E1000_READ_REG(hw, E1000_TARC(0));
5125         if (hw->mac.type == e1000_ich8lan)
5126                 reg |= (1 << 28) | (1 << 29);
5127         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5128         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5129
5130         /* Transmit Arbitration Control 1 */
5131         reg = E1000_READ_REG(hw, E1000_TARC(1));
5132         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5133                 reg &= ~(1 << 28);
5134         else
5135                 reg |= (1 << 28);
5136         reg |= (1 << 24) | (1 << 26) | (1 << 30);
5137         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5138
5139         /* Device Status */
5140         if (hw->mac.type == e1000_ich8lan) {
5141                 reg = E1000_READ_REG(hw, E1000_STATUS);
5142                 reg &= ~(1U << 31);
5143                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5144         }
5145
5146         /* work-around descriptor data corruption issue during nfs v2 udp
5147          * traffic, just disable the nfs filtering capability
5148          */
5149         reg = E1000_READ_REG(hw, E1000_RFCTL);
5150         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5151
5152         /* Disable IPv6 extension header parsing because some malformed
5153          * IPv6 headers can hang the Rx.
5154          */
5155         if (hw->mac.type == e1000_ich8lan)
5156                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5157         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5158
5159         /* Enable ECC on Lynxpoint */
5160         if (hw->mac.type >= e1000_pch_lpt) {
5161                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5162                 reg |= E1000_PBECCSTS_ECC_ENABLE;
5163                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5164
5165                 reg = E1000_READ_REG(hw, E1000_CTRL);
5166                 reg |= E1000_CTRL_MEHE;
5167                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5168         }
5169
5170         return;
5171 }
5172
5173 /**
5174  *  e1000_setup_link_ich8lan - Setup flow control and link settings
5175  *  @hw: pointer to the HW structure
5176  *
5177  *  Determines which flow control settings to use, then configures flow
5178  *  control.  Calls the appropriate media-specific link configuration
5179  *  function.  Assuming the adapter has a valid link partner, a valid link
5180  *  should be established.  Assumes the hardware has previously been reset
5181  *  and the transmitter and receiver are not enabled.
5182  **/
5183 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5184 {
5185         s32 ret_val;
5186
5187         DEBUGFUNC("e1000_setup_link_ich8lan");
5188
5189         if (hw->phy.ops.check_reset_block(hw))
5190                 return E1000_SUCCESS;
5191
5192         /* ICH parts do not have a word in the NVM to determine
5193          * the default flow control setting, so we explicitly
5194          * set it to full.
5195          */
5196         if (hw->fc.requested_mode == e1000_fc_default)
5197                 hw->fc.requested_mode = e1000_fc_full;
5198
5199         /* Save off the requested flow control mode for use later.  Depending
5200          * on the link partner's capabilities, we may or may not use this mode.
5201          */
5202         hw->fc.current_mode = hw->fc.requested_mode;
5203
5204         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5205                 hw->fc.current_mode);
5206
5207         /* Continue to configure the copper link. */
5208         ret_val = hw->mac.ops.setup_physical_interface(hw);
5209         if (ret_val)
5210                 return ret_val;
5211
5212         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5213         if ((hw->phy.type == e1000_phy_82578) ||
5214             (hw->phy.type == e1000_phy_82579) ||
5215             (hw->phy.type == e1000_phy_i217) ||
5216             (hw->phy.type == e1000_phy_82577)) {
5217                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5218
5219                 ret_val = hw->phy.ops.write_reg(hw,
5220                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
5221                                              hw->fc.pause_time);
5222                 if (ret_val)
5223                         return ret_val;
5224         }
5225
5226         return e1000_set_fc_watermarks_generic(hw);
5227 }
5228
5229 /**
5230  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5231  *  @hw: pointer to the HW structure
5232  *
5233  *  Configures the kumeran interface to the PHY to wait the appropriate time
5234  *  when polling the PHY, then call the generic setup_copper_link to finish
5235  *  configuring the copper link.
5236  **/
5237 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5238 {
5239         u32 ctrl;
5240         s32 ret_val;
5241         u16 reg_data;
5242
5243         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5244
5245         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5246         ctrl |= E1000_CTRL_SLU;
5247         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5248         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5249
5250         /* Set the mac to wait the maximum time between each iteration
5251          * and increase the max iterations when polling the phy;
5252          * this fixes erroneous timeouts at 10Mbps.
5253          */
5254         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5255                                                0xFFFF);
5256         if (ret_val)
5257                 return ret_val;
5258         ret_val = e1000_read_kmrn_reg_generic(hw,
5259                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
5260                                               &reg_data);
5261         if (ret_val)
5262                 return ret_val;
5263         reg_data |= 0x3F;
5264         ret_val = e1000_write_kmrn_reg_generic(hw,
5265                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
5266                                                reg_data);
5267         if (ret_val)
5268                 return ret_val;
5269
5270         switch (hw->phy.type) {
5271         case e1000_phy_igp_3:
5272                 ret_val = e1000_copper_link_setup_igp(hw);
5273                 if (ret_val)
5274                         return ret_val;
5275                 break;
5276         case e1000_phy_bm:
5277         case e1000_phy_82578:
5278                 ret_val = e1000_copper_link_setup_m88(hw);
5279                 if (ret_val)
5280                         return ret_val;
5281                 break;
5282         case e1000_phy_82577:
5283         case e1000_phy_82579:
5284                 ret_val = e1000_copper_link_setup_82577(hw);
5285                 if (ret_val)
5286                         return ret_val;
5287                 break;
5288         case e1000_phy_ife:
5289                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5290                                                &reg_data);
5291                 if (ret_val)
5292                         return ret_val;
5293
5294                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5295
5296                 switch (hw->phy.mdix) {
5297                 case 1:
5298                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5299                         break;
5300                 case 2:
5301                         reg_data |= IFE_PMC_FORCE_MDIX;
5302                         break;
5303                 case 0:
5304                 default:
5305                         reg_data |= IFE_PMC_AUTO_MDIX;
5306                         break;
5307                 }
5308                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5309                                                 reg_data);
5310                 if (ret_val)
5311                         return ret_val;
5312                 break;
5313         default:
5314                 break;
5315         }
5316
5317         return e1000_setup_copper_link_generic(hw);
5318 }
5319
5320 /**
5321  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5322  *  @hw: pointer to the HW structure
5323  *
5324  *  Calls the PHY specific link setup function and then calls the
5325  *  generic setup_copper_link to finish configuring the link for
5326  *  Lynxpoint PCH devices
5327  **/
5328 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5329 {
5330         u32 ctrl;
5331         s32 ret_val;
5332
5333         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5334
5335         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5336         ctrl |= E1000_CTRL_SLU;
5337         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5338         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5339
5340         ret_val = e1000_copper_link_setup_82577(hw);
5341         if (ret_val)
5342                 return ret_val;
5343
5344         return e1000_setup_copper_link_generic(hw);
5345 }
5346
5347 /**
5348  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5349  *  @hw: pointer to the HW structure
5350  *  @speed: pointer to store current link speed
5351  *  @duplex: pointer to store the current link duplex
5352  *
5353  *  Calls the generic get_speed_and_duplex to retrieve the current link
5354  *  information and then calls the Kumeran lock loss workaround for links at
5355  *  gigabit speeds.
5356  **/
5357 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5358                                           u16 *duplex)
5359 {
5360         s32 ret_val;
5361
5362         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5363
5364         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5365         if (ret_val)
5366                 return ret_val;
5367
5368         if ((hw->mac.type == e1000_ich8lan) &&
5369             (hw->phy.type == e1000_phy_igp_3) &&
5370             (*speed == SPEED_1000)) {
5371                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5372         }
5373
5374         return ret_val;
5375 }
5376
5377 /**
5378  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5379  *  @hw: pointer to the HW structure
5380  *
5381  *  Work-around for 82566 Kumeran PCS lock loss:
5382  *  On link status change (i.e. PCI reset, speed change) and link is up and
5383  *  speed is gigabit-
5384  *    0) if workaround is optionally disabled do nothing
5385  *    1) wait 1ms for Kumeran link to come up
5386  *    2) check Kumeran Diagnostic register PCS lock loss bit
5387  *    3) if not set the link is locked (all is good), otherwise...
5388  *    4) reset the PHY
5389  *    5) repeat up to 10 times
5390  *  Note: this is only called for IGP3 copper when speed is 1gb.
5391  **/
5392 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5393 {
5394         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5395         u32 phy_ctrl;
5396         s32 ret_val;
5397         u16 i, data;
5398         bool link;
5399
5400         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5401
5402         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5403                 return E1000_SUCCESS;
5404
5405         /* Make sure link is up before proceeding.  If not just return.
5406          * Attempting this while link is negotiating fouled up link
5407          * stability
5408          */
5409         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5410         if (!link)
5411                 return E1000_SUCCESS;
5412
5413         for (i = 0; i < 10; i++) {
5414                 /* read once to clear */
5415                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5416                 if (ret_val)
5417                         return ret_val;
5418                 /* and again to get new status */
5419                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5420                 if (ret_val)
5421                         return ret_val;
5422
5423                 /* check for PCS lock */
5424                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5425                         return E1000_SUCCESS;
5426
5427                 /* Issue PHY reset */
5428                 hw->phy.ops.reset(hw);
5429                 msec_delay_irq(5);
5430         }
5431         /* Disable GigE link negotiation */
5432         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5433         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5434                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5435         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5436
5437         /* Call gig speed drop workaround on Gig disable before accessing
5438          * any PHY registers
5439          */
5440         e1000_gig_downshift_workaround_ich8lan(hw);
5441
5442         /* unable to acquire PCS lock */
5443         return -E1000_ERR_PHY;
5444 }
5445
5446 /**
5447  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5448  *  @hw: pointer to the HW structure
5449  *  @state: boolean value used to set the current Kumeran workaround state
5450  *
5451  *  If ICH8, set the current Kumeran workaround state (enabled - true
5452  *  /disabled - false).
5453  **/
5454 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5455                                                  bool state)
5456 {
5457         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5458
5459         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5460
5461         if (hw->mac.type != e1000_ich8lan) {
5462                 DEBUGOUT("Workaround applies to ICH8 only.\n");
5463                 return;
5464         }
5465
5466         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5467
5468         return;
5469 }
5470
5471 /**
5472  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5473  *  @hw: pointer to the HW structure
5474  *
5475  *  Workaround for 82566 power-down on D3 entry:
5476  *    1) disable gigabit link
5477  *    2) write VR power-down enable
5478  *    3) read it back
5479  *  Continue if successful, else issue LCD reset and repeat
5480  **/
5481 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5482 {
5483         u32 reg;
5484         u16 data;
5485         u8  retry = 0;
5486
5487         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5488
5489         if (hw->phy.type != e1000_phy_igp_3)
5490                 return;
5491
5492         /* Try the workaround twice (if needed) */
5493         do {
5494                 /* Disable link */
5495                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5496                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5497                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5498                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5499
5500                 /* Call gig speed drop workaround on Gig disable before
5501                  * accessing any PHY registers
5502                  */
5503                 if (hw->mac.type == e1000_ich8lan)
5504                         e1000_gig_downshift_workaround_ich8lan(hw);
5505
5506                 /* Write VR power-down enable */
5507                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5508                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5509                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5510                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5511
5512                 /* Read it back and test */
5513                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5514                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5515                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5516                         break;
5517
5518                 /* Issue PHY reset and repeat at most one more time */
5519                 reg = E1000_READ_REG(hw, E1000_CTRL);
5520                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5521                 retry++;
5522         } while (retry);
5523 }
5524
5525 /**
5526  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5527  *  @hw: pointer to the HW structure
5528  *
5529  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5530  *  LPLU, Gig disable, MDIC PHY reset):
5531  *    1) Set Kumeran Near-end loopback
5532  *    2) Clear Kumeran Near-end loopback
5533  *  Should only be called for ICH8[m] devices with any 1G Phy.
5534  **/
5535 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5536 {
5537         s32 ret_val;
5538         u16 reg_data = 0;
5539
5540         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5541
5542         if ((hw->mac.type != e1000_ich8lan) ||
5543             (hw->phy.type == e1000_phy_ife))
5544                 return;
5545
5546         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5547                                               &reg_data);
5548         if (ret_val)
5549                 return;
5550         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5551         ret_val = e1000_write_kmrn_reg_generic(hw,
5552                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
5553                                                reg_data);
5554         if (ret_val)
5555                 return;
5556         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5557         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5558                                      reg_data);
5559 }
5560
5561 /**
5562  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5563  *  @hw: pointer to the HW structure
5564  *
5565  *  During S0 to Sx transition, it is possible the link remains at gig
5566  *  instead of negotiating to a lower speed.  Before going to Sx, set
5567  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5568  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5569  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5570  *  needs to be written.
5571  *  Parts that support (and are linked to a partner which support) EEE in
5572  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5573  *  than 10Mbps w/o EEE.
5574  **/
5575 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5576 {
5577         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5578         u32 phy_ctrl;
5579         s32 ret_val;
5580
5581         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5582
5583         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5584         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5585
5586         if (hw->phy.type == e1000_phy_i217) {
5587                 u16 phy_reg, device_id = hw->device_id;
5588
5589                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5590                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5591                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5592                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5593                     (hw->mac.type >= e1000_pch_spt)) {
5594                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5595
5596                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5597                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5598                 }
5599
5600                 ret_val = hw->phy.ops.acquire(hw);
5601                 if (ret_val)
5602                         goto out;
5603
5604                 if (!dev_spec->eee_disable) {
5605                         u16 eee_advert;
5606
5607                         ret_val =
5608                             e1000_read_emi_reg_locked(hw,
5609                                                       I217_EEE_ADVERTISEMENT,
5610                                                       &eee_advert);
5611                         if (ret_val)
5612                                 goto release;
5613
5614                         /* Disable LPLU if both link partners support 100BaseT
5615                          * EEE and 100Full is advertised on both ends of the
5616                          * link, and enable Auto Enable LPI since there will
5617                          * be no driver to enable LPI while in Sx.
5618                          */
5619                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5620                             (dev_spec->eee_lp_ability &
5621                              I82579_EEE_100_SUPPORTED) &&
5622                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5623                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5624                                               E1000_PHY_CTRL_NOND0A_LPLU);
5625
5626                                 /* Set Auto Enable LPI after link up */
5627                                 hw->phy.ops.read_reg_locked(hw,
5628                                                             I217_LPI_GPIO_CTRL,
5629                                                             &phy_reg);
5630                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5631                                 hw->phy.ops.write_reg_locked(hw,
5632                                                              I217_LPI_GPIO_CTRL,
5633                                                              phy_reg);
5634                         }
5635                 }
5636
5637                 /* For i217 Intel Rapid Start Technology support,
5638                  * when the system is going into Sx and no manageability engine
5639                  * is present, the driver must configure proxy to reset only on
5640                  * power good.  LPI (Low Power Idle) state must also reset only
5641                  * on power good, as well as the MTA (Multicast table array).
5642                  * The SMBus release must also be disabled on LCD reset.
5643                  */
5644                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5645                       E1000_ICH_FWSM_FW_VALID)) {
5646                         /* Enable proxy to reset only on power good. */
5647                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5648                                                     &phy_reg);
5649                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5650                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5651                                                      phy_reg);
5652
5653                         /* Set bit enable LPI (EEE) to reset only on
5654                          * power good.
5655                         */
5656                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5657                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5658                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5659
5660                         /* Disable the SMB release on LCD reset. */
5661                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5662                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5663                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5664                 }
5665
5666                 /* Enable MTA to reset for Intel Rapid Start Technology
5667                  * Support
5668                  */
5669                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5670                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5671                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5672
5673 release:
5674                 hw->phy.ops.release(hw);
5675         }
5676 out:
5677         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5678
5679         if (hw->mac.type == e1000_ich8lan)
5680                 e1000_gig_downshift_workaround_ich8lan(hw);
5681
5682         if (hw->mac.type >= e1000_pchlan) {
5683                 e1000_oem_bits_config_ich8lan(hw, false);
5684
5685                 /* Reset PHY to activate OEM bits on 82577/8 */
5686                 if (hw->mac.type == e1000_pchlan)
5687                         e1000_phy_hw_reset_generic(hw);
5688
5689                 ret_val = hw->phy.ops.acquire(hw);
5690                 if (ret_val)
5691                         return;
5692                 e1000_write_smbus_addr(hw);
5693                 hw->phy.ops.release(hw);
5694         }
5695
5696         return;
5697 }
5698
5699 /**
5700  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5701  *  @hw: pointer to the HW structure
5702  *
5703  *  During Sx to S0 transitions on non-managed devices or managed devices
5704  *  on which PHY resets are not blocked, if the PHY registers cannot be
5705  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5706  *  the PHY.
5707  *  On i217, setup Intel Rapid Start Technology.
5708  **/
5709 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5710 {
5711         s32 ret_val;
5712
5713         DEBUGFUNC("e1000_resume_workarounds_pchlan");
5714         if (hw->mac.type < e1000_pch2lan)
5715                 return E1000_SUCCESS;
5716
5717         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5718         if (ret_val) {
5719                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5720                 return ret_val;
5721         }
5722
5723         /* For i217 Intel Rapid Start Technology support when the system
5724          * is transitioning from Sx and no manageability engine is present
5725          * configure SMBus to restore on reset, disable proxy, and enable
5726          * the reset on MTA (Multicast table array).
5727          */
5728         if (hw->phy.type == e1000_phy_i217) {
5729                 u16 phy_reg;
5730
5731                 ret_val = hw->phy.ops.acquire(hw);
5732                 if (ret_val) {
5733                         DEBUGOUT("Failed to setup iRST\n");
5734                         return ret_val;
5735                 }
5736
5737                 /* Clear Auto Enable LPI after link up */
5738                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5739                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5740                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5741
5742                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5743                     E1000_ICH_FWSM_FW_VALID)) {
5744                         /* Restore clear on SMB if no manageability engine
5745                          * is present
5746                          */
5747                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5748                                                               &phy_reg);
5749                         if (ret_val)
5750                                 goto release;
5751                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5752                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5753
5754                         /* Disable Proxy */
5755                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5756                 }
5757                 /* Enable reset on MTA */
5758                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5759                                                       &phy_reg);
5760                 if (ret_val)
5761                         goto release;
5762                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5763                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5764 release:
5765                 if (ret_val)
5766                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5767                 hw->phy.ops.release(hw);
5768                 return ret_val;
5769         }
5770         return E1000_SUCCESS;
5771 }
5772
5773 /**
5774  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5775  *  @hw: pointer to the HW structure
5776  *
5777  *  Return the LED back to the default configuration.
5778  **/
5779 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5780 {
5781         DEBUGFUNC("e1000_cleanup_led_ich8lan");
5782
5783         if (hw->phy.type == e1000_phy_ife)
5784                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5785                                              0);
5786
5787         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5788         return E1000_SUCCESS;
5789 }
5790
5791 /**
5792  *  e1000_led_on_ich8lan - Turn LEDs on
5793  *  @hw: pointer to the HW structure
5794  *
5795  *  Turn on the LEDs.
5796  **/
5797 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5798 {
5799         DEBUGFUNC("e1000_led_on_ich8lan");
5800
5801         if (hw->phy.type == e1000_phy_ife)
5802                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5803                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5804
5805         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5806         return E1000_SUCCESS;
5807 }
5808
5809 /**
5810  *  e1000_led_off_ich8lan - Turn LEDs off
5811  *  @hw: pointer to the HW structure
5812  *
5813  *  Turn off the LEDs.
5814  **/
5815 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5816 {
5817         DEBUGFUNC("e1000_led_off_ich8lan");
5818
5819         if (hw->phy.type == e1000_phy_ife)
5820                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5821                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5822
5823         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5824         return E1000_SUCCESS;
5825 }
5826
5827 /**
5828  *  e1000_setup_led_pchlan - Configures SW controllable LED
5829  *  @hw: pointer to the HW structure
5830  *
5831  *  This prepares the SW controllable LED for use.
5832  **/
5833 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5834 {
5835         DEBUGFUNC("e1000_setup_led_pchlan");
5836
5837         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5838                                      (u16)hw->mac.ledctl_mode1);
5839 }
5840
5841 /**
5842  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5843  *  @hw: pointer to the HW structure
5844  *
5845  *  Return the LED back to the default configuration.
5846  **/
5847 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5848 {
5849         DEBUGFUNC("e1000_cleanup_led_pchlan");
5850
5851         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5852                                      (u16)hw->mac.ledctl_default);
5853 }
5854
5855 /**
5856  *  e1000_led_on_pchlan - Turn LEDs on
5857  *  @hw: pointer to the HW structure
5858  *
5859  *  Turn on the LEDs.
5860  **/
5861 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5862 {
5863         u16 data = (u16)hw->mac.ledctl_mode2;
5864         u32 i, led;
5865
5866         DEBUGFUNC("e1000_led_on_pchlan");
5867
5868         /* If no link, then turn LED on by setting the invert bit
5869          * for each LED that's mode is "link_up" in ledctl_mode2.
5870          */
5871         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5872                 for (i = 0; i < 3; i++) {
5873                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5874                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5875                             E1000_LEDCTL_MODE_LINK_UP)
5876                                 continue;
5877                         if (led & E1000_PHY_LED0_IVRT)
5878                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5879                         else
5880                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5881                 }
5882         }
5883
5884         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5885 }
5886
5887 /**
5888  *  e1000_led_off_pchlan - Turn LEDs off
5889  *  @hw: pointer to the HW structure
5890  *
5891  *  Turn off the LEDs.
5892  **/
5893 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5894 {
5895         u16 data = (u16)hw->mac.ledctl_mode1;
5896         u32 i, led;
5897
5898         DEBUGFUNC("e1000_led_off_pchlan");
5899
5900         /* If no link, then turn LED off by clearing the invert bit
5901          * for each LED that's mode is "link_up" in ledctl_mode1.
5902          */
5903         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5904                 for (i = 0; i < 3; i++) {
5905                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5906                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5907                             E1000_LEDCTL_MODE_LINK_UP)
5908                                 continue;
5909                         if (led & E1000_PHY_LED0_IVRT)
5910                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5911                         else
5912                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5913                 }
5914         }
5915
5916         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5917 }
5918
5919 /**
5920  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5921  *  @hw: pointer to the HW structure
5922  *
5923  *  Read appropriate register for the config done bit for completion status
5924  *  and configure the PHY through s/w for EEPROM-less parts.
5925  *
5926  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5927  *  config done bit, so only an error is logged and continues.  If we were
5928  *  to return with error, EEPROM-less silicon would not be able to be reset
5929  *  or change link.
5930  **/
5931 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5932 {
5933         s32 ret_val = E1000_SUCCESS;
5934         u32 bank = 0;
5935         u32 status;
5936
5937         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5938
5939         e1000_get_cfg_done_generic(hw);
5940
5941         /* Wait for indication from h/w that it has completed basic config */
5942         if (hw->mac.type >= e1000_ich10lan) {
5943                 e1000_lan_init_done_ich8lan(hw);
5944         } else {
5945                 ret_val = e1000_get_auto_rd_done_generic(hw);
5946                 if (ret_val) {
5947                         /* When auto config read does not complete, do not
5948                          * return with an error. This can happen in situations
5949                          * where there is no eeprom and prevents getting link.
5950                          */
5951                         DEBUGOUT("Auto Read Done did not complete\n");
5952                         ret_val = E1000_SUCCESS;
5953                 }
5954         }
5955
5956         /* Clear PHY Reset Asserted bit */
5957         status = E1000_READ_REG(hw, E1000_STATUS);
5958         if (status & E1000_STATUS_PHYRA)
5959                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5960         else
5961                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5962
5963         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5964         if (hw->mac.type <= e1000_ich9lan) {
5965                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5966                     (hw->phy.type == e1000_phy_igp_3)) {
5967                         e1000_phy_init_script_igp3(hw);
5968                 }
5969         } else {
5970                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5971                         /* Maybe we should do a basic PHY config */
5972                         DEBUGOUT("EEPROM not present\n");
5973                         ret_val = -E1000_ERR_CONFIG;
5974                 }
5975         }
5976
5977         return ret_val;
5978 }
5979
5980 /**
5981  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5982  * @hw: pointer to the HW structure
5983  *
5984  * In the case of a PHY power down to save power, or to turn off link during a
5985  * driver unload, or wake on lan is not enabled, remove the link.
5986  **/
5987 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5988 {
5989         /* If the management interface is not enabled, then power down */
5990         if (!(hw->mac.ops.check_mng_mode(hw) ||
5991               hw->phy.ops.check_reset_block(hw)))
5992                 e1000_power_down_phy_copper(hw);
5993
5994         return;
5995 }
5996
5997 /**
5998  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5999  *  @hw: pointer to the HW structure
6000  *
6001  *  Clears hardware counters specific to the silicon family and calls
6002  *  clear_hw_cntrs_generic to clear all general purpose counters.
6003  **/
6004 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6005 {
6006         u16 phy_data;
6007         s32 ret_val;
6008
6009         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6010
6011         e1000_clear_hw_cntrs_base_generic(hw);
6012
6013         E1000_READ_REG(hw, E1000_ALGNERRC);
6014         E1000_READ_REG(hw, E1000_RXERRC);
6015         E1000_READ_REG(hw, E1000_TNCRS);
6016         E1000_READ_REG(hw, E1000_CEXTERR);
6017         E1000_READ_REG(hw, E1000_TSCTC);
6018         E1000_READ_REG(hw, E1000_TSCTFC);
6019
6020         E1000_READ_REG(hw, E1000_MGTPRC);
6021         E1000_READ_REG(hw, E1000_MGTPDC);
6022         E1000_READ_REG(hw, E1000_MGTPTC);
6023
6024         E1000_READ_REG(hw, E1000_IAC);
6025         E1000_READ_REG(hw, E1000_ICRXOC);
6026
6027         /* Clear PHY statistics registers */
6028         if ((hw->phy.type == e1000_phy_82578) ||
6029             (hw->phy.type == e1000_phy_82579) ||
6030             (hw->phy.type == e1000_phy_i217) ||
6031             (hw->phy.type == e1000_phy_82577)) {
6032                 ret_val = hw->phy.ops.acquire(hw);
6033                 if (ret_val)
6034                         return;
6035                 ret_val = hw->phy.ops.set_page(hw,
6036                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
6037                 if (ret_val)
6038                         goto release;
6039                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6040                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6041                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6042                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6043                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6044                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6045                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6046                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6047                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6048                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6049                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6050                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6051                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6052                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6053 release:
6054                 hw->phy.ops.release(hw);
6055         }
6056 }
6057
6058 /**
6059  *  e1000_configure_k0s_lpt - Configure K0s power state
6060  *  @hw: pointer to the HW structure
6061  *  @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6062  *      0 corresponds to 128ns, each value over 0 doubles the duration.
6063  *  @min_time: Minimum Tx idle period allowed  - valid values are 0 to 4.
6064  *      0 corresponds to 128ns, each value over 0 doubles the duration.
6065  *
6066  *  Configure the K1 power state based on the provided parameter.
6067  *  Assumes semaphore already acquired.
6068  *
6069  *  Success returns 0, Failure returns:
6070  *      -E1000_ERR_PHY (-2) in case of access error
6071  *      -E1000_ERR_PARAM (-4) in case of parameters error
6072  **/
6073 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6074 {
6075         s32 ret_val;
6076         u16 kmrn_reg = 0;
6077
6078         DEBUGFUNC("e1000_configure_k0s_lpt");
6079
6080         if (entry_latency > 3 || min_time > 4)
6081                 return -E1000_ERR_PARAM;
6082
6083         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6084                                              &kmrn_reg);
6085         if (ret_val)
6086                 return ret_val;
6087
6088         /* for now don't touch the latency */
6089         kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6090         kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6091
6092         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6093                                               kmrn_reg);
6094         if (ret_val)
6095                 return ret_val;
6096
6097         return E1000_SUCCESS;
6098 }