1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
5 /* 82562G 10/100 Network Connection
6 * 82562G-2 10/100 Network Connection
7 * 82562GT 10/100 Network Connection
8 * 82562GT-2 10/100 Network Connection
9 * 82562V 10/100 Network Connection
10 * 82562V-2 10/100 Network Connection
11 * 82566DC-2 Gigabit Network Connection
12 * 82566DC Gigabit Network Connection
13 * 82566DM-2 Gigabit Network Connection
14 * 82566DM Gigabit Network Connection
15 * 82566MC Gigabit Network Connection
16 * 82566MM Gigabit Network Connection
17 * 82567LM Gigabit Network Connection
18 * 82567LF Gigabit Network Connection
19 * 82567V Gigabit Network Connection
20 * 82567LM-2 Gigabit Network Connection
21 * 82567LF-2 Gigabit Network Connection
22 * 82567V-2 Gigabit Network Connection
23 * 82567LF-3 Gigabit Network Connection
24 * 82567LM-3 Gigabit Network Connection
25 * 82567LM-4 Gigabit Network Connection
26 * 82577LM Gigabit Network Connection
27 * 82577LC Gigabit Network Connection
28 * 82578DM Gigabit Network Connection
29 * 82578DC Gigabit Network Connection
30 * 82579LM Gigabit Network Connection
31 * 82579V Gigabit Network Connection
32 * Ethernet Connection I217-LM
33 * Ethernet Connection I217-V
34 * Ethernet Connection I218-V
35 * Ethernet Connection I218-LM
36 * Ethernet Connection (2) I218-LM
37 * Ethernet Connection (2) I218-V
38 * Ethernet Connection (3) I218-LM
39 * Ethernet Connection (3) I218-V
42 #include "e1000_api.h"
44 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
45 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
46 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
47 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
48 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
49 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
50 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
51 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
52 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
53 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
54 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
55 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
58 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
59 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
60 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
61 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
62 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
64 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
66 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
67 u16 words, u16 *data);
68 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
70 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
71 u16 words, u16 *data);
72 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
73 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
74 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
75 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
77 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
78 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
79 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
80 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
81 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
82 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
83 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
84 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
85 u16 *speed, u16 *duplex);
86 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
87 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
88 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
89 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
90 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
91 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
92 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);
93 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
94 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
95 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
96 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
97 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
98 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
99 u32 offset, u8 *data);
100 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
102 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
104 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
105 u32 offset, u32 *data);
106 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
107 u32 offset, u32 data);
108 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
109 u32 offset, u32 dword);
110 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
111 u32 offset, u16 *data);
112 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
113 u32 offset, u8 byte);
114 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
115 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
116 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
117 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
118 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
119 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
121 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
122 /* Offset 04h HSFSTS */
123 union ich8_hws_flash_status {
125 u16 flcdone:1; /* bit 0 Flash Cycle Done */
126 u16 flcerr:1; /* bit 1 Flash Cycle Error */
127 u16 dael:1; /* bit 2 Direct Access error Log */
128 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
129 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
130 u16 reserved1:2; /* bit 13:6 Reserved */
131 u16 reserved2:6; /* bit 13:6 Reserved */
132 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
133 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
138 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
139 /* Offset 06h FLCTL */
140 union ich8_hws_flash_ctrl {
141 struct ich8_hsflctl {
142 u16 flcgo:1; /* 0 Flash Cycle Go */
143 u16 flcycle:2; /* 2:1 Flash Cycle */
144 u16 reserved:5; /* 7:3 Reserved */
145 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
146 u16 flockdn:6; /* 15:10 Reserved */
151 /* ICH Flash Region Access Permissions */
152 union ich8_hws_flash_regacc {
154 u32 grra:8; /* 0:7 GbE region Read Access */
155 u32 grwa:8; /* 8:15 GbE region Write Access */
156 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
157 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
163 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
164 * @hw: pointer to the HW structure
166 * Test access to the PHY registers by reading the PHY ID registers. If
167 * the PHY ID is already known (e.g. resume path) compare it with known ID,
168 * otherwise assume the read PHY ID is correct if it is valid.
170 * Assumes the sw/fw/hw semaphore is already acquired.
172 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
180 for (retry_count = 0; retry_count < 2; retry_count++) {
181 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
182 if (ret_val || (phy_reg == 0xFFFF))
184 phy_id = (u32)(phy_reg << 16);
186 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
187 if (ret_val || (phy_reg == 0xFFFF)) {
191 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 if (hw->phy.id == phy_id)
200 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
204 /* In case the PHY needs to be in mdio slow mode,
205 * set slow mode and try to get the PHY id again.
207 if (hw->mac.type < e1000_pch_lpt) {
208 hw->phy.ops.release(hw);
209 ret_val = e1000_set_mdio_slow_mode_hv(hw);
211 ret_val = e1000_get_phy_id(hw);
212 hw->phy.ops.acquire(hw);
218 if (hw->mac.type >= e1000_pch_lpt) {
219 /* Only unforce SMBus if ME is not active */
220 if (!(E1000_READ_REG(hw, E1000_FWSM) &
221 E1000_ICH_FWSM_FW_VALID)) {
222 /* Unforce SMBus mode in PHY */
223 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
224 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
225 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
227 /* Unforce SMBus mode in MAC */
228 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
229 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
230 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
238 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
239 * @hw: pointer to the HW structure
241 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
242 * used to reset the PHY to a quiescent state when necessary.
244 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
250 /* Set Phy Config Counter to 50msec */
251 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
252 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
253 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
254 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
256 /* Toggle LANPHYPC Value bit */
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
258 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
259 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
260 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
261 E1000_WRITE_FLUSH(hw);
263 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
264 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
265 E1000_WRITE_FLUSH(hw);
267 if (hw->mac.type < e1000_pch_lpt) {
274 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
275 E1000_CTRL_EXT_LPCD) && count--);
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
285 * Workarounds/flow necessary for PHY initialization during driver load
288 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
290 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
293 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
295 /* Gate automatic PHY configuration by hardware on managed and
296 * non-managed 82579 and newer adapters.
298 e1000_gate_hw_phy_config_ich8lan(hw, true);
301 /* It is not possible to be certain of the current state of ULP
302 * so forcibly disable it.
304 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
306 #endif /* ULP_SUPPORT */
307 ret_val = hw->phy.ops.acquire(hw);
309 DEBUGOUT("Failed to initialize PHY flow\n");
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
317 switch (hw->mac.type) {
321 if (e1000_phy_is_accessible_pchlan(hw))
324 /* Before toggling LANPHYPC, see if PHY is accessible by
325 * forcing MAC to SMBus mode first.
327 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
328 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
329 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
331 /* Wait 50 milliseconds for MAC to finish any retries
332 * that it might be trying to perform from previous
333 * attempts to acknowledge any phy read requests.
339 if (e1000_phy_is_accessible_pchlan(hw))
344 if ((hw->mac.type == e1000_pchlan) &&
345 (fwsm & E1000_ICH_FWSM_FW_VALID))
348 if (hw->phy.ops.check_reset_block(hw)) {
349 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
350 ret_val = -E1000_ERR_PHY;
354 /* Toggle LANPHYPC Value bit */
355 e1000_toggle_lanphypc_pch_lpt(hw);
356 if (hw->mac.type >= e1000_pch_lpt) {
357 if (e1000_phy_is_accessible_pchlan(hw))
360 /* Toggling LANPHYPC brings the PHY out of SMBus mode
361 * so ensure that the MAC is also out of SMBus mode
363 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
364 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
365 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
367 if (e1000_phy_is_accessible_pchlan(hw))
370 ret_val = -E1000_ERR_PHY;
377 hw->phy.ops.release(hw);
380 /* Check to see if able to reset PHY. Print error if not */
381 if (hw->phy.ops.check_reset_block(hw)) {
382 ERROR_REPORT("Reset blocked by ME\n");
386 /* Reset the PHY before any access to it. Doing so, ensures
387 * that the PHY is in a known good state before we read/write
388 * PHY registers. The generic reset is sufficient here,
389 * because we haven't determined the PHY type yet.
391 ret_val = e1000_phy_hw_reset_generic(hw);
395 /* On a successful reset, possibly need to wait for the PHY
396 * to quiesce to an accessible state before returning control
397 * to the calling function. If the PHY does not quiesce, then
398 * return E1000E_BLK_PHY_RESET, as this is the condition that
401 ret_val = hw->phy.ops.check_reset_block(hw);
403 ERROR_REPORT("ME blocked access to PHY after reset\n");
407 /* Ungate automatic PHY configuration on non-managed 82579 */
408 if ((hw->mac.type == e1000_pch2lan) &&
409 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
411 e1000_gate_hw_phy_config_ich8lan(hw, false);
418 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
419 * @hw: pointer to the HW structure
421 * Initialize family-specific PHY parameters and function pointers.
423 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
425 struct e1000_phy_info *phy = &hw->phy;
428 DEBUGFUNC("e1000_init_phy_params_pchlan");
431 phy->reset_delay_us = 100;
433 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
434 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
435 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
436 phy->ops.set_page = e1000_set_page_igp;
437 phy->ops.read_reg = e1000_read_phy_reg_hv;
438 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
439 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
440 phy->ops.release = e1000_release_swflag_ich8lan;
441 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
442 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
443 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
444 phy->ops.write_reg = e1000_write_phy_reg_hv;
445 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
446 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
447 phy->ops.power_up = e1000_power_up_phy_copper;
448 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
449 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
451 phy->id = e1000_phy_unknown;
453 ret_val = e1000_init_phy_workarounds_pchlan(hw);
457 if (phy->id == e1000_phy_unknown)
458 switch (hw->mac.type) {
460 ret_val = e1000_get_phy_id(hw);
463 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
470 /* In case the PHY needs to be in mdio slow mode,
471 * set slow mode and try to get the PHY id again.
473 ret_val = e1000_set_mdio_slow_mode_hv(hw);
476 ret_val = e1000_get_phy_id(hw);
481 phy->type = e1000_get_phy_type_from_id(phy->id);
484 case e1000_phy_82577:
485 case e1000_phy_82579:
487 phy->ops.check_polarity = e1000_check_polarity_82577;
488 phy->ops.force_speed_duplex =
489 e1000_phy_force_speed_duplex_82577;
490 phy->ops.get_cable_length = e1000_get_cable_length_82577;
491 phy->ops.get_info = e1000_get_phy_info_82577;
492 phy->ops.commit = e1000_phy_sw_reset_generic;
494 case e1000_phy_82578:
495 phy->ops.check_polarity = e1000_check_polarity_m88;
496 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
497 phy->ops.get_cable_length = e1000_get_cable_length_m88;
498 phy->ops.get_info = e1000_get_phy_info_m88;
501 ret_val = -E1000_ERR_PHY;
509 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
510 * @hw: pointer to the HW structure
512 * Initialize family-specific PHY parameters and function pointers.
514 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
516 struct e1000_phy_info *phy = &hw->phy;
520 DEBUGFUNC("e1000_init_phy_params_ich8lan");
523 phy->reset_delay_us = 100;
525 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
526 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
527 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
528 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
529 phy->ops.read_reg = e1000_read_phy_reg_igp;
530 phy->ops.release = e1000_release_swflag_ich8lan;
531 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
532 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
533 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
534 phy->ops.write_reg = e1000_write_phy_reg_igp;
535 phy->ops.power_up = e1000_power_up_phy_copper;
536 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
538 /* We may need to do this twice - once for IGP and if that fails,
539 * we'll set BM func pointers and try again
541 ret_val = e1000_determine_phy_address(hw);
543 phy->ops.write_reg = e1000_write_phy_reg_bm;
544 phy->ops.read_reg = e1000_read_phy_reg_bm;
545 ret_val = e1000_determine_phy_address(hw);
547 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
553 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
556 ret_val = e1000_get_phy_id(hw);
563 case IGP03E1000_E_PHY_ID:
564 phy->type = e1000_phy_igp_3;
565 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
566 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
567 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
568 phy->ops.get_info = e1000_get_phy_info_igp;
569 phy->ops.check_polarity = e1000_check_polarity_igp;
570 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
573 case IFE_PLUS_E_PHY_ID:
575 phy->type = e1000_phy_ife;
576 phy->autoneg_mask = E1000_ALL_NOT_GIG;
577 phy->ops.get_info = e1000_get_phy_info_ife;
578 phy->ops.check_polarity = e1000_check_polarity_ife;
579 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
581 case BME1000_E_PHY_ID:
582 phy->type = e1000_phy_bm;
583 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
584 phy->ops.read_reg = e1000_read_phy_reg_bm;
585 phy->ops.write_reg = e1000_write_phy_reg_bm;
586 phy->ops.commit = e1000_phy_sw_reset_generic;
587 phy->ops.get_info = e1000_get_phy_info_m88;
588 phy->ops.check_polarity = e1000_check_polarity_m88;
589 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
592 return -E1000_ERR_PHY;
596 return E1000_SUCCESS;
600 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
601 * @hw: pointer to the HW structure
603 * Initialize family-specific NVM parameters and function
606 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
608 struct e1000_nvm_info *nvm = &hw->nvm;
609 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
610 u32 gfpreg, sector_base_addr, sector_end_addr;
614 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
616 nvm->type = e1000_nvm_flash_sw;
618 if (hw->mac.type >= e1000_pch_spt) {
619 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
620 * STRAP register. This is because in SPT the GbE Flash region
621 * is no longer accessed through the flash registers. Instead,
622 * the mechanism has changed, and the Flash region access
623 * registers are now implemented in GbE memory space.
625 nvm->flash_base_addr = 0;
627 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
628 * NVM_SIZE_MULTIPLIER;
629 nvm->flash_bank_size = nvm_size / 2;
630 /* Adjust to word count */
631 nvm->flash_bank_size /= sizeof(u16);
632 /* Set the base address for flash register access */
633 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
635 /* Can't read flash registers if register set isn't mapped. */
636 if (!hw->flash_address) {
637 DEBUGOUT("ERROR: Flash registers not mapped\n");
638 return -E1000_ERR_CONFIG;
641 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
643 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
644 * Add 1 to sector_end_addr since this sector is included in
647 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
648 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
650 /* flash_base_addr is byte-aligned */
651 nvm->flash_base_addr = sector_base_addr
652 << FLASH_SECTOR_ADDR_SHIFT;
654 /* find total size of the NVM, then cut in half since the total
655 * size represents two separate NVM banks.
657 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
658 << FLASH_SECTOR_ADDR_SHIFT);
659 nvm->flash_bank_size /= 2;
660 /* Adjust to word count */
661 nvm->flash_bank_size /= sizeof(u16);
664 nvm->word_size = E1000_SHADOW_RAM_WORDS;
666 /* Clear shadow ram */
667 for (i = 0; i < nvm->word_size; i++) {
668 dev_spec->shadow_ram[i].modified = false;
669 dev_spec->shadow_ram[i].value = 0xFFFF;
672 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
673 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
675 /* Function Pointers */
676 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
677 nvm->ops.release = e1000_release_nvm_ich8lan;
678 if (hw->mac.type >= e1000_pch_spt) {
679 nvm->ops.read = e1000_read_nvm_spt;
680 nvm->ops.update = e1000_update_nvm_checksum_spt;
682 nvm->ops.read = e1000_read_nvm_ich8lan;
683 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
685 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
686 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
687 nvm->ops.write = e1000_write_nvm_ich8lan;
689 return E1000_SUCCESS;
693 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
694 * @hw: pointer to the HW structure
696 * Initialize family-specific MAC parameters and function
699 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
701 struct e1000_mac_info *mac = &hw->mac;
702 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
704 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
706 DEBUGFUNC("e1000_init_mac_params_ich8lan");
708 /* Set media type function pointer */
709 hw->phy.media_type = e1000_media_type_copper;
711 /* Set mta register count */
712 mac->mta_reg_count = 32;
713 /* Set rar entry count */
714 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
715 if (mac->type == e1000_ich8lan)
716 mac->rar_entry_count--;
717 /* Set if part includes ASF firmware */
718 mac->asf_firmware_present = true;
720 mac->has_fwsm = true;
721 /* ARC subsystem not supported */
722 mac->arc_subsystem_valid = false;
723 /* Adaptive IFS supported */
724 mac->adaptive_ifs = true;
726 /* Function pointers */
728 /* bus type/speed/width */
729 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
731 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
733 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
734 /* hw initialization */
735 mac->ops.init_hw = e1000_init_hw_ich8lan;
737 mac->ops.setup_link = e1000_setup_link_ich8lan;
738 /* physical interface setup */
739 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
741 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
743 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
744 /* multicast address update */
745 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
746 /* clear hardware counters */
747 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
749 /* LED and other operations */
754 /* check management mode */
755 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
757 mac->ops.id_led_init = e1000_id_led_init_generic;
759 mac->ops.blink_led = e1000_blink_led_generic;
761 mac->ops.setup_led = e1000_setup_led_generic;
763 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
764 /* turn on/off LED */
765 mac->ops.led_on = e1000_led_on_ich8lan;
766 mac->ops.led_off = e1000_led_off_ich8lan;
769 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
770 mac->ops.rar_set = e1000_rar_set_pch2lan;
775 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
776 /* multicast address update for pch2 */
777 mac->ops.update_mc_addr_list =
778 e1000_update_mc_addr_list_pch2lan;
782 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
783 /* save PCH revision_id */
784 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
785 /* SPT uses full byte for revision ID,
786 * as opposed to previous generations
788 if (hw->mac.type >= e1000_pch_spt)
789 hw->revision_id = (u8)(pci_cfg &= 0x00FF);
791 hw->revision_id = (u8)(pci_cfg &= 0x000F);
792 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
793 /* check management mode */
794 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
796 mac->ops.id_led_init = e1000_id_led_init_pchlan;
798 mac->ops.setup_led = e1000_setup_led_pchlan;
800 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
801 /* turn on/off LED */
802 mac->ops.led_on = e1000_led_on_pchlan;
803 mac->ops.led_off = e1000_led_off_pchlan;
809 if (mac->type >= e1000_pch_lpt) {
810 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
811 mac->ops.rar_set = e1000_rar_set_pch_lpt;
812 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
815 /* Enable PCS Lock-loss workaround for ICH8 */
816 if (mac->type == e1000_ich8lan)
817 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
819 return E1000_SUCCESS;
823 * __e1000_access_emi_reg_locked - Read/write EMI register
824 * @hw: pointer to the HW structure
825 * @address: EMI address to program
826 * @data: pointer to value to read/write from/to the EMI address
827 * @read: boolean flag to indicate read or write
829 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
831 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
832 u16 *data, bool read)
836 DEBUGFUNC("__e1000_access_emi_reg_locked");
838 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
843 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
846 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
853 * e1000_read_emi_reg_locked - Read Extended Management Interface register
854 * @hw: pointer to the HW structure
855 * @addr: EMI address to program
856 * @data: value to be read from the EMI address
858 * Assumes the SW/FW/HW Semaphore is already acquired.
860 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
862 DEBUGFUNC("e1000_read_emi_reg_locked");
864 return __e1000_access_emi_reg_locked(hw, addr, data, true);
868 * e1000_write_emi_reg_locked - Write Extended Management Interface register
869 * @hw: pointer to the HW structure
870 * @addr: EMI address to program
871 * @data: value to be written to the EMI address
873 * Assumes the SW/FW/HW Semaphore is already acquired.
875 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
877 DEBUGFUNC("e1000_read_emi_reg_locked");
879 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
883 * e1000_set_eee_pchlan - Enable/disable EEE support
884 * @hw: pointer to the HW structure
886 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
887 * the link and the EEE capabilities of the link partner. The LPI Control
888 * register bits will remain set only if/when link is up.
890 * EEE LPI must not be asserted earlier than one second after link is up.
891 * On 82579, EEE LPI should not be enabled until such time otherwise there
892 * can be link issues with some switches. Other devices can have EEE LPI
893 * enabled immediately upon link up since they have a timer in hardware which
894 * prevents LPI from being asserted too early.
896 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
898 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
900 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
902 DEBUGFUNC("e1000_set_eee_pchlan");
904 switch (hw->phy.type) {
905 case e1000_phy_82579:
906 lpa = I82579_EEE_LP_ABILITY;
907 pcs_status = I82579_EEE_PCS_STATUS;
908 adv_addr = I82579_EEE_ADVERTISEMENT;
911 lpa = I217_EEE_LP_ABILITY;
912 pcs_status = I217_EEE_PCS_STATUS;
913 adv_addr = I217_EEE_ADVERTISEMENT;
916 return E1000_SUCCESS;
919 ret_val = hw->phy.ops.acquire(hw);
923 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
927 /* Clear bits that enable EEE in various speeds */
928 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
930 /* Enable EEE if not disabled by user */
931 if (!dev_spec->eee_disable) {
932 /* Save off link partner's EEE ability */
933 ret_val = e1000_read_emi_reg_locked(hw, lpa,
934 &dev_spec->eee_lp_ability);
938 /* Read EEE advertisement */
939 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
943 /* Enable EEE only for speeds in which the link partner is
944 * EEE capable and for which we advertise EEE.
946 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
947 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
949 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
950 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
951 if (data & NWAY_LPAR_100TX_FD_CAPS)
952 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
954 /* EEE is not supported in 100Half, so ignore
955 * partner's EEE in 100 ability if full-duplex
958 dev_spec->eee_lp_ability &=
959 ~I82579_EEE_100_SUPPORTED;
963 if (hw->phy.type == e1000_phy_82579) {
964 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
969 data &= ~I82579_LPI_100_PLL_SHUT;
970 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
974 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
975 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
979 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
981 hw->phy.ops.release(hw);
987 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
988 * @hw: pointer to the HW structure
989 * @link: link up bool flag
991 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
992 * preventing further DMA write requests. Workaround the issue by disabling
993 * the de-assertion of the clock request when in 1Gpbs mode.
994 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
995 * speeds in order to avoid Tx hangs.
997 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
999 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1000 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1001 s32 ret_val = E1000_SUCCESS;
1004 if (link && (status & E1000_STATUS_SPEED_1000)) {
1005 ret_val = hw->phy.ops.acquire(hw);
1010 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1016 e1000_write_kmrn_reg_locked(hw,
1017 E1000_KMRNCTRLSTA_K1_CONFIG,
1019 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1025 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1026 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1029 e1000_write_kmrn_reg_locked(hw,
1030 E1000_KMRNCTRLSTA_K1_CONFIG,
1033 hw->phy.ops.release(hw);
1035 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1036 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1038 if ((hw->phy.revision > 5) || !link ||
1039 ((status & E1000_STATUS_SPEED_100) &&
1040 (status & E1000_STATUS_FD)))
1041 goto update_fextnvm6;
1043 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1047 /* Clear link status transmit timeout */
1048 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1050 if (status & E1000_STATUS_SPEED_100) {
1051 /* Set inband Tx timeout to 5x10us for 100Half */
1052 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1054 /* Do not extend the K1 entry latency for 100Half */
1055 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1057 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1059 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1061 /* Extend the K1 entry latency for 10 Mbps */
1062 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1065 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1070 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1078 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1079 * @hw: pointer to the HW structure
1080 * @to_sx: boolean indicating a system power state transition to Sx
1082 * When link is down, configure ULP mode to significantly reduce the power
1083 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1084 * ME firmware to start the ULP configuration. If not on an ME enabled
1085 * system, configure the ULP mode by software.
1087 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1090 s32 ret_val = E1000_SUCCESS;
1094 if ((hw->mac.type < e1000_pch_lpt) ||
1095 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1096 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1097 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1098 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1099 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1104 /* Poll up to 5 seconds for Cable Disconnected indication */
1105 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1106 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1107 /* Bail if link is re-acquired */
1108 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1109 return -E1000_ERR_PHY;
1115 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1116 (E1000_READ_REG(hw, E1000_FEXT) &
1117 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1119 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1120 E1000_FEXT_PHY_CABLE_DISCONNECTED))
1124 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1125 /* Request ME configure ULP mode in the PHY */
1126 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1127 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1128 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1133 ret_val = hw->phy.ops.acquire(hw);
1137 /* During S0 Idle keep the phy in PCI-E mode */
1138 if (hw->dev_spec.ich8lan.smbus_disable)
1141 /* Force SMBus mode in PHY */
1142 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1145 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1146 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1148 /* Force SMBus mode in MAC */
1149 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1150 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1151 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1153 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1154 * LPLU and disable Gig speed when entering ULP
1156 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1157 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1163 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1165 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1174 /* Change the 'Link Status Change' interrupt to trigger
1175 * on 'Cable Status Change'
1177 ret_val = e1000_read_kmrn_reg_locked(hw,
1178 E1000_KMRNCTRLSTA_OP_MODES,
1182 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1183 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1187 /* Set Inband ULP Exit, Reset to SMBus mode and
1188 * Disable SMBus Release on PERST# in PHY
1190 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1193 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1194 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1196 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1197 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1199 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1201 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1202 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1204 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1205 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1206 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1208 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1210 /* Set Disable SMBus Release on PERST# in MAC */
1211 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1212 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1213 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1215 /* Commit ULP changes in PHY by starting auto ULP configuration */
1216 phy_reg |= I218_ULP_CONFIG1_START;
1217 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1220 /* Disable Tx so that the MAC doesn't send any (buffered)
1221 * packets to the PHY.
1223 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1224 mac_reg &= ~E1000_TCTL_EN;
1225 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1228 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1229 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1230 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1237 hw->phy.ops.release(hw);
1240 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1242 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1248 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1249 * @hw: pointer to the HW structure
1250 * @force: boolean indicating whether or not to force disabling ULP
1252 * Un-configure ULP mode when link is up, the system is transitioned from
1253 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1254 * system, poll for an indication from ME that ULP has been un-configured.
1255 * If not on an ME enabled system, un-configure the ULP mode by software.
1257 * During nominal operation, this function is called when link is acquired
1258 * to disable ULP mode (force=false); otherwise, for example when unloading
1259 * the driver or during Sx->S0 transitions, this is called with force=true
1260 * to forcibly disable ULP.
1262 * When the cable is plugged in while the device is in D0, a Cable Status
1263 * Change interrupt is generated which causes this function to be called
1264 * to partially disable ULP mode and restart autonegotiation. This function
1265 * is then called again due to the resulting Link Status Change interrupt
1266 * to finish cleaning up after the ULP flow.
1268 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1270 s32 ret_val = E1000_SUCCESS;
1275 if ((hw->mac.type < e1000_pch_lpt) ||
1276 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1277 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1278 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1279 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1280 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1283 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1285 /* Request ME un-configure ULP mode in the PHY */
1286 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1287 mac_reg &= ~E1000_H2ME_ULP;
1288 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1289 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1292 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1293 while (E1000_READ_REG(hw, E1000_FWSM) &
1294 E1000_FWSM_ULP_CFG_DONE) {
1296 ret_val = -E1000_ERR_PHY;
1302 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1305 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1306 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1307 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1309 /* Clear H2ME.ULP after ME ULP configuration */
1310 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1311 mac_reg &= ~E1000_H2ME_ULP;
1312 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1314 /* Restore link speed advertisements and restart
1317 if (hw->mac.autoneg) {
1318 ret_val = e1000_phy_setup_autoneg(hw);
1322 ret_val = e1000_setup_copper_link_generic(hw);
1326 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1332 ret_val = hw->phy.ops.acquire(hw);
1336 /* Revert the change to the 'Link Status Change'
1337 * interrupt to trigger on 'Cable Status Change'
1339 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1343 phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1344 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1347 /* Toggle LANPHYPC Value bit */
1348 e1000_toggle_lanphypc_pch_lpt(hw);
1350 /* Unforce SMBus mode in PHY */
1351 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1353 /* The MAC might be in PCIe mode, so temporarily force to
1354 * SMBus mode in order to access the PHY.
1356 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1357 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1358 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1362 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1367 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1368 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1370 /* Unforce SMBus mode in MAC */
1371 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1372 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1373 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1375 /* When ULP mode was previously entered, K1 was disabled by the
1376 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1378 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1381 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1382 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1384 /* Clear ULP enabled configuration */
1385 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1388 /* CSC interrupt received due to ULP Indication */
1389 if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1390 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1391 I218_ULP_CONFIG1_STICKY_ULP |
1392 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1393 I218_ULP_CONFIG1_WOL_HOST |
1394 I218_ULP_CONFIG1_INBAND_EXIT |
1395 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1396 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1397 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1398 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1400 /* Commit ULP changes by starting auto ULP configuration */
1401 phy_reg |= I218_ULP_CONFIG1_START;
1402 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1404 /* Clear Disable SMBus Release on PERST# in MAC */
1405 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1406 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1407 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1410 hw->phy.ops.release(hw);
1412 if (hw->mac.autoneg)
1413 e1000_phy_setup_autoneg(hw);
1415 e1000_setup_copper_link_generic(hw);
1417 e1000_sw_lcd_config_ich8lan(hw);
1419 e1000_oem_bits_config_ich8lan(hw, true);
1421 /* Set ULP state to unknown and return non-zero to
1422 * indicate no link (yet) and re-enter on the next LSC
1423 * to finish disabling ULP flow.
1425 hw->dev_spec.ich8lan.ulp_state =
1426 e1000_ulp_state_unknown;
1433 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1434 mac_reg |= E1000_TCTL_EN;
1435 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1438 hw->phy.ops.release(hw);
1440 hw->phy.ops.reset(hw);
1445 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1447 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1452 #endif /* ULP_SUPPORT */
1456 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1457 * @hw: pointer to the HW structure
1459 * Checks to see of the link status of the hardware has changed. If a
1460 * change in link status has been detected, then we read the PHY registers
1461 * to get the current speed/duplex if link exists.
1463 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1465 struct e1000_mac_info *mac = &hw->mac;
1466 s32 ret_val, tipg_reg = 0;
1467 u16 emi_addr, emi_val = 0;
1471 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1473 /* We only want to go out to the PHY registers to see if Auto-Neg
1474 * has completed and/or if our link status has changed. The
1475 * get_link_status flag is set upon receiving a Link Status
1476 * Change or Rx Sequence Error interrupt.
1478 if (!mac->get_link_status)
1479 return E1000_SUCCESS;
1481 if ((hw->mac.type < e1000_pch_lpt) ||
1482 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1483 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1484 /* First we want to see if the MII Status Register reports
1485 * link. If so, then we want to get the current speed/duplex
1488 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1492 /* Check the MAC's STATUS register to determine link state
1493 * since the PHY could be inaccessible while in ULP mode.
1495 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1497 ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1499 ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1504 if (hw->mac.type == e1000_pchlan) {
1505 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1510 /* When connected at 10Mbps half-duplex, some parts are excessively
1511 * aggressive resulting in many collisions. To avoid this, increase
1512 * the IPG and reduce Rx latency in the PHY.
1514 if ((hw->mac.type >= e1000_pch2lan) && link) {
1517 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1518 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1519 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1521 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1523 /* Reduce Rx latency in analog PHY */
1525 } else if (hw->mac.type >= e1000_pch_spt &&
1526 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1530 /* Roll back the default values */
1535 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1537 ret_val = hw->phy.ops.acquire(hw);
1541 if (hw->mac.type == e1000_pch2lan)
1542 emi_addr = I82579_RX_CONFIG;
1544 emi_addr = I217_RX_CONFIG;
1545 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1548 if (hw->mac.type >= e1000_pch_lpt) {
1549 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1551 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1552 if (speed == SPEED_100 || speed == SPEED_10)
1556 hw->phy.ops.write_reg_locked(hw,
1557 I217_PLL_CLOCK_GATE_REG,
1560 if (speed == SPEED_1000) {
1561 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1564 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1566 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1570 hw->phy.ops.release(hw);
1575 if (hw->mac.type >= e1000_pch_spt) {
1579 if (speed == SPEED_1000) {
1580 ret_val = hw->phy.ops.acquire(hw);
1584 ret_val = hw->phy.ops.read_reg_locked(hw,
1588 hw->phy.ops.release(hw);
1592 ptr_gap = (data & (0x3FF << 2)) >> 2;
1593 if (ptr_gap < 0x18) {
1594 data &= ~(0x3FF << 2);
1595 data |= (0x18 << 2);
1597 hw->phy.ops.write_reg_locked(hw,
1598 PHY_REG(776, 20), data);
1600 hw->phy.ops.release(hw);
1604 ret_val = hw->phy.ops.acquire(hw);
1608 ret_val = hw->phy.ops.write_reg_locked(hw,
1611 hw->phy.ops.release(hw);
1619 /* I217 Packet Loss issue:
1620 * ensure that FEXTNVM4 Beacon Duration is set correctly
1622 * Set the Beacon Duration for I217 to 8 usec
1624 if (hw->mac.type >= e1000_pch_lpt) {
1627 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1628 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1629 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1630 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1633 /* Work-around I218 hang issue */
1634 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1635 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1636 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1637 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1638 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1642 /* Clear link partner's EEE ability */
1643 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1645 /* Configure K0s minimum time */
1646 if (hw->mac.type >= e1000_pch_lpt) {
1647 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1650 if (hw->mac.type >= e1000_pch_lpt) {
1651 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1653 if (hw->mac.type == e1000_pch_spt) {
1654 /* FEXTNVM6 K1-off workaround - for SPT only */
1655 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1657 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1658 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1660 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1663 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1664 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1666 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1670 return E1000_SUCCESS; /* No link detected */
1672 mac->get_link_status = false;
1674 switch (hw->mac.type) {
1676 ret_val = e1000_k1_workaround_lv(hw);
1681 if (hw->phy.type == e1000_phy_82578) {
1682 ret_val = e1000_link_stall_workaround_hv(hw);
1687 /* Workaround for PCHx parts in half-duplex:
1688 * Set the number of preambles removed from the packet
1689 * when it is passed from the PHY to the MAC to prevent
1690 * the MAC from misinterpreting the packet type.
1692 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1693 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1695 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1697 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1699 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1705 /* Check if there was DownShift, must be checked
1706 * immediately after link-up
1708 e1000_check_downshift_generic(hw);
1710 /* Enable/Disable EEE after link up */
1711 if (hw->phy.type > e1000_phy_82579) {
1712 ret_val = e1000_set_eee_pchlan(hw);
1717 /* If we are forcing speed/duplex, then we simply return since
1718 * we have already determined whether we have link or not.
1721 return -E1000_ERR_CONFIG;
1723 /* Auto-Neg is enabled. Auto Speed Detection takes care
1724 * of MAC speed/duplex configuration. So we only need to
1725 * configure Collision Distance in the MAC.
1727 mac->ops.config_collision_dist(hw);
1729 /* Configure Flow Control now that Auto-Neg has completed.
1730 * First, we need to restore the desired flow control
1731 * settings because we may have had to re-autoneg with a
1732 * different link partner.
1734 ret_val = e1000_config_fc_after_link_up_generic(hw);
1736 DEBUGOUT("Error configuring flow control\n");
1742 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1743 * @hw: pointer to the HW structure
1745 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1747 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1749 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1751 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1752 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1753 switch (hw->mac.type) {
1756 case e1000_ich10lan:
1757 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1764 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1772 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1773 * @hw: pointer to the HW structure
1775 * Acquires the mutex for performing NVM operations.
1777 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1779 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1781 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1783 return E1000_SUCCESS;
1787 * e1000_release_nvm_ich8lan - Release NVM mutex
1788 * @hw: pointer to the HW structure
1790 * Releases the mutex used while performing NVM operations.
1792 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1794 DEBUGFUNC("e1000_release_nvm_ich8lan");
1796 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1802 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1803 * @hw: pointer to the HW structure
1805 * Acquires the software control flag for performing PHY and select
1808 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1810 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1811 s32 ret_val = E1000_SUCCESS;
1813 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1815 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1818 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1819 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1827 DEBUGOUT("SW has already locked the resource.\n");
1828 ret_val = -E1000_ERR_CONFIG;
1832 timeout = SW_FLAG_TIMEOUT;
1834 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1835 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1838 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1839 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1847 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1848 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1849 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1850 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1851 ret_val = -E1000_ERR_CONFIG;
1857 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1863 * e1000_release_swflag_ich8lan - Release software control flag
1864 * @hw: pointer to the HW structure
1866 * Releases the software control flag for performing PHY and select
1869 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1873 DEBUGFUNC("e1000_release_swflag_ich8lan");
1875 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1877 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1878 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1879 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1881 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1884 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1890 * e1000_check_mng_mode_ich8lan - Checks management mode
1891 * @hw: pointer to the HW structure
1893 * This checks if the adapter has any manageability enabled.
1894 * This is a function pointer entry point only called by read/write
1895 * routines for the PHY and NVM parts.
1897 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1901 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1903 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1905 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1906 ((fwsm & E1000_FWSM_MODE_MASK) ==
1907 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1911 * e1000_check_mng_mode_pchlan - Checks management mode
1912 * @hw: pointer to the HW structure
1914 * This checks if the adapter has iAMT enabled.
1915 * This is a function pointer entry point only called by read/write
1916 * routines for the PHY and NVM parts.
1918 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1922 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1924 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1926 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1927 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1931 * e1000_rar_set_pch2lan - Set receive address register
1932 * @hw: pointer to the HW structure
1933 * @addr: pointer to the receive address
1934 * @index: receive address array register
1936 * Sets the receive address array register at index to the address passed
1937 * in by addr. For 82579, RAR[0] is the base address register that is to
1938 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1939 * Use SHRA[0-3] in place of those reserved for ME.
1941 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1943 u32 rar_low, rar_high;
1945 DEBUGFUNC("e1000_rar_set_pch2lan");
1947 /* HW expects these in little endian so we reverse the byte order
1948 * from network order (big endian) to little endian
1950 rar_low = ((u32) addr[0] |
1951 ((u32) addr[1] << 8) |
1952 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1954 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1956 /* If MAC address zero, no need to set the AV bit */
1957 if (rar_low || rar_high)
1958 rar_high |= E1000_RAH_AV;
1961 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1962 E1000_WRITE_FLUSH(hw);
1963 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1964 E1000_WRITE_FLUSH(hw);
1965 return E1000_SUCCESS;
1968 /* RAR[1-6] are owned by manageability. Skip those and program the
1969 * next address into the SHRA register array.
1971 if (index < (u32) (hw->mac.rar_entry_count)) {
1974 ret_val = e1000_acquire_swflag_ich8lan(hw);
1978 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1979 E1000_WRITE_FLUSH(hw);
1980 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1981 E1000_WRITE_FLUSH(hw);
1983 e1000_release_swflag_ich8lan(hw);
1985 /* verify the register updates */
1986 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1987 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1988 return E1000_SUCCESS;
1990 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1991 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1995 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1996 return -E1000_ERR_CONFIG;
2000 * e1000_rar_set_pch_lpt - Set receive address registers
2001 * @hw: pointer to the HW structure
2002 * @addr: pointer to the receive address
2003 * @index: receive address array register
2005 * Sets the receive address register array at index to the address passed
2006 * in by addr. For LPT, RAR[0] is the base address register that is to
2007 * contain the MAC address. SHRA[0-10] are the shared receive address
2008 * registers that are shared between the Host and manageability engine (ME).
2010 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2012 u32 rar_low, rar_high;
2015 DEBUGFUNC("e1000_rar_set_pch_lpt");
2017 /* HW expects these in little endian so we reverse the byte order
2018 * from network order (big endian) to little endian
2020 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2021 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2023 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2025 /* If MAC address zero, no need to set the AV bit */
2026 if (rar_low || rar_high)
2027 rar_high |= E1000_RAH_AV;
2030 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2031 E1000_WRITE_FLUSH(hw);
2032 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2033 E1000_WRITE_FLUSH(hw);
2034 return E1000_SUCCESS;
2037 /* The manageability engine (ME) can lock certain SHRAR registers that
2038 * it is using - those registers are unavailable for use.
2040 if (index < hw->mac.rar_entry_count) {
2041 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2042 E1000_FWSM_WLOCK_MAC_MASK;
2043 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2045 /* Check if all SHRAR registers are locked */
2049 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2052 ret_val = e1000_acquire_swflag_ich8lan(hw);
2057 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2059 E1000_WRITE_FLUSH(hw);
2060 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2062 E1000_WRITE_FLUSH(hw);
2064 e1000_release_swflag_ich8lan(hw);
2066 /* verify the register updates */
2067 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2068 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2069 return E1000_SUCCESS;
2074 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2075 return -E1000_ERR_CONFIG;
2078 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
2080 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2081 * @hw: pointer to the HW structure
2082 * @mc_addr_list: array of multicast addresses to program
2083 * @mc_addr_count: number of multicast addresses to program
2085 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2086 * The caller must have a packed mc_addr_list of multicast addresses.
2088 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2096 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2098 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2100 ret_val = hw->phy.ops.acquire(hw);
2104 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2108 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2109 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2110 (u16)(hw->mac.mta_shadow[i] &
2112 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2113 (u16)((hw->mac.mta_shadow[i] >> 16) &
2117 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2120 hw->phy.ops.release(hw);
2123 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
2125 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2126 * @hw: pointer to the HW structure
2128 * Checks if firmware is blocking the reset of the PHY.
2129 * This is a function pointer entry point only called by
2132 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2135 bool blocked = false;
2138 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2141 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2142 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2148 } while (blocked && (i++ < 30));
2149 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2153 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2154 * @hw: pointer to the HW structure
2156 * Assumes semaphore already acquired.
2159 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2162 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2163 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2164 E1000_STRAP_SMT_FREQ_SHIFT;
2167 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2169 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2173 phy_data &= ~HV_SMB_ADDR_MASK;
2174 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2175 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2177 if (hw->phy.type == e1000_phy_i217) {
2178 /* Restore SMBus frequency */
2180 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2181 phy_data |= (freq & (1 << 0)) <<
2182 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2183 phy_data |= (freq & (1 << 1)) <<
2184 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2186 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2190 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2194 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2195 * @hw: pointer to the HW structure
2197 * SW should configure the LCD from the NVM extended configuration region
2198 * as a workaround for certain parts.
2200 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2202 struct e1000_phy_info *phy = &hw->phy;
2203 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2204 s32 ret_val = E1000_SUCCESS;
2205 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2207 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2209 /* Initialize the PHY from the NVM on ICH platforms. This
2210 * is needed due to an issue where the NVM configuration is
2211 * not properly autoloaded after power transitions.
2212 * Therefore, after each PHY reset, we will load the
2213 * configuration data out of the NVM manually.
2215 switch (hw->mac.type) {
2217 if (phy->type != e1000_phy_igp_3)
2220 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2221 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2222 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2231 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2237 ret_val = hw->phy.ops.acquire(hw);
2241 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2242 if (!(data & sw_cfg_mask))
2245 /* Make sure HW does not configure LCD from PHY
2246 * extended configuration before SW configuration
2248 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2249 if ((hw->mac.type < e1000_pch2lan) &&
2250 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2253 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2254 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2255 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2259 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2260 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2262 if (((hw->mac.type == e1000_pchlan) &&
2263 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2264 (hw->mac.type > e1000_pchlan)) {
2265 /* HW configures the SMBus address and LEDs when the
2266 * OEM and LCD Write Enable bits are set in the NVM.
2267 * When both NVM bits are cleared, SW will configure
2270 ret_val = e1000_write_smbus_addr(hw);
2274 data = E1000_READ_REG(hw, E1000_LEDCTL);
2275 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2281 /* Configure LCD from extended configuration region. */
2283 /* cnf_base_addr is in DWORD */
2284 word_addr = (u16)(cnf_base_addr << 1);
2286 for (i = 0; i < cnf_size; i++) {
2287 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2292 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2297 /* Save off the PHY page for future writes. */
2298 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2299 phy_page = reg_data;
2303 reg_addr &= PHY_REG_MASK;
2304 reg_addr |= phy_page;
2306 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2313 hw->phy.ops.release(hw);
2318 * e1000_k1_gig_workaround_hv - K1 Si workaround
2319 * @hw: pointer to the HW structure
2320 * @link: link up bool flag
2322 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2323 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2324 * If link is down, the function will restore the default K1 setting located
2327 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2329 s32 ret_val = E1000_SUCCESS;
2331 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2333 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2335 if (hw->mac.type != e1000_pchlan)
2336 return E1000_SUCCESS;
2338 /* Wrap the whole flow with the sw flag */
2339 ret_val = hw->phy.ops.acquire(hw);
2343 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2345 if (hw->phy.type == e1000_phy_82578) {
2346 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2351 status_reg &= (BM_CS_STATUS_LINK_UP |
2352 BM_CS_STATUS_RESOLVED |
2353 BM_CS_STATUS_SPEED_MASK);
2355 if (status_reg == (BM_CS_STATUS_LINK_UP |
2356 BM_CS_STATUS_RESOLVED |
2357 BM_CS_STATUS_SPEED_1000))
2361 if (hw->phy.type == e1000_phy_82577) {
2362 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2367 status_reg &= (HV_M_STATUS_LINK_UP |
2368 HV_M_STATUS_AUTONEG_COMPLETE |
2369 HV_M_STATUS_SPEED_MASK);
2371 if (status_reg == (HV_M_STATUS_LINK_UP |
2372 HV_M_STATUS_AUTONEG_COMPLETE |
2373 HV_M_STATUS_SPEED_1000))
2377 /* Link stall fix for link up */
2378 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2384 /* Link stall fix for link down */
2385 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2391 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2394 hw->phy.ops.release(hw);
2400 * e1000_configure_k1_ich8lan - Configure K1 power state
2401 * @hw: pointer to the HW structure
2402 * @k1_enable: K1 state to configure
2404 * Configure the K1 power state based on the provided parameter.
2405 * Assumes semaphore already acquired.
2407 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2409 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2417 DEBUGFUNC("e1000_configure_k1_ich8lan");
2419 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2425 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2427 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2429 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2435 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2436 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2438 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2439 reg |= E1000_CTRL_FRCSPD;
2440 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2442 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2443 E1000_WRITE_FLUSH(hw);
2445 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2446 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2447 E1000_WRITE_FLUSH(hw);
2450 return E1000_SUCCESS;
2454 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2455 * @hw: pointer to the HW structure
2456 * @d0_state: boolean if entering d0 or d3 device state
2458 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2459 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2460 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2462 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2468 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2470 if (hw->mac.type < e1000_pchlan)
2473 ret_val = hw->phy.ops.acquire(hw);
2477 if (hw->mac.type == e1000_pchlan) {
2478 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2479 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2483 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2484 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2487 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2489 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2493 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2496 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2497 oem_reg |= HV_OEM_BITS_GBE_DIS;
2499 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2500 oem_reg |= HV_OEM_BITS_LPLU;
2502 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2503 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2504 oem_reg |= HV_OEM_BITS_GBE_DIS;
2506 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2507 E1000_PHY_CTRL_NOND0A_LPLU))
2508 oem_reg |= HV_OEM_BITS_LPLU;
2511 /* Set Restart auto-neg to activate the bits */
2512 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2513 !hw->phy.ops.check_reset_block(hw))
2514 oem_reg |= HV_OEM_BITS_RESTART_AN;
2516 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2519 hw->phy.ops.release(hw);
2526 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2527 * @hw: pointer to the HW structure
2529 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2534 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2536 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2540 data |= HV_KMRN_MDIO_SLOW;
2542 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2548 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2549 * done after every PHY reset.
2550 * @hw: pointer to the HW structure
2552 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2554 s32 ret_val = E1000_SUCCESS;
2557 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2559 if (hw->mac.type != e1000_pchlan)
2560 return E1000_SUCCESS;
2562 /* Set MDIO slow mode before any other MDIO access */
2563 if (hw->phy.type == e1000_phy_82577) {
2564 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2569 if (((hw->phy.type == e1000_phy_82577) &&
2570 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2571 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2572 /* Disable generation of early preamble */
2573 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2577 /* Preamble tuning for SSC */
2578 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2584 if (hw->phy.type == e1000_phy_82578) {
2585 /* Return registers to default by doing a soft reset then
2586 * writing 0x3140 to the control register.
2588 if (hw->phy.revision < 2) {
2589 e1000_phy_sw_reset_generic(hw);
2590 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2596 ret_val = hw->phy.ops.acquire(hw);
2601 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2602 hw->phy.ops.release(hw);
2606 /* Configure the K1 Si workaround during phy reset assuming there is
2607 * link so that it disables K1 if link is in 1Gbps.
2609 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2613 /* Workaround for link disconnects on a busy hub in half duplex */
2614 ret_val = hw->phy.ops.acquire(hw);
2617 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2620 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2625 /* set MSE higher to enable link to stay up when noise is high */
2626 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2628 hw->phy.ops.release(hw);
2634 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2635 * @hw: pointer to the HW structure
2637 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2643 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2645 ret_val = hw->phy.ops.acquire(hw);
2648 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2652 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2653 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2654 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2655 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2656 (u16)(mac_reg & 0xFFFF));
2657 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2658 (u16)((mac_reg >> 16) & 0xFFFF));
2660 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2661 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2662 (u16)(mac_reg & 0xFFFF));
2663 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2664 (u16)((mac_reg & E1000_RAH_AV)
2668 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2671 hw->phy.ops.release(hw);
2674 #ifndef CRC32_OS_SUPPORT
2675 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2677 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2678 u32 i, j, mask, crc;
2680 DEBUGFUNC("e1000_calc_rx_da_crc");
2683 for (i = 0; i < 6; i++) {
2685 for (j = 8; j > 0; j--) {
2686 mask = (crc & 1) * (-1);
2687 crc = (crc >> 1) ^ (poly & mask);
2693 #endif /* CRC32_OS_SUPPORT */
2695 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2697 * @hw: pointer to the HW structure
2698 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2700 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2702 s32 ret_val = E1000_SUCCESS;
2707 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2709 if (hw->mac.type < e1000_pch2lan)
2710 return E1000_SUCCESS;
2712 /* disable Rx path while enabling/disabling workaround */
2713 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2714 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2715 phy_reg | (1 << 14));
2720 /* Write Rx addresses (rar_entry_count for RAL/H, and
2721 * SHRAL/H) and initial CRC values to the MAC
2723 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2724 u8 mac_addr[ETH_ADDR_LEN] = {0};
2725 u32 addr_high, addr_low;
2727 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2728 if (!(addr_high & E1000_RAH_AV))
2730 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2731 mac_addr[0] = (addr_low & 0xFF);
2732 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2733 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2734 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2735 mac_addr[4] = (addr_high & 0xFF);
2736 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2738 #ifndef CRC32_OS_SUPPORT
2739 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2740 e1000_calc_rx_da_crc(mac_addr));
2741 #else /* CRC32_OS_SUPPORT */
2742 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2743 E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2744 #endif /* CRC32_OS_SUPPORT */
2747 /* Write Rx addresses to the PHY */
2748 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2750 /* Enable jumbo frame workaround in the MAC */
2751 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2752 mac_reg &= ~(1 << 14);
2753 mac_reg |= (7 << 15);
2754 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2756 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2757 mac_reg |= E1000_RCTL_SECRC;
2758 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2760 ret_val = e1000_read_kmrn_reg_generic(hw,
2761 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2765 ret_val = e1000_write_kmrn_reg_generic(hw,
2766 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2770 ret_val = e1000_read_kmrn_reg_generic(hw,
2771 E1000_KMRNCTRLSTA_HD_CTRL,
2775 data &= ~(0xF << 8);
2777 ret_val = e1000_write_kmrn_reg_generic(hw,
2778 E1000_KMRNCTRLSTA_HD_CTRL,
2783 /* Enable jumbo frame workaround in the PHY */
2784 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2785 data &= ~(0x7F << 5);
2786 data |= (0x37 << 5);
2787 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2790 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2792 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2795 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2796 data &= ~(0x3FF << 2);
2797 data |= (E1000_TX_PTR_GAP << 2);
2798 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2801 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2804 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2805 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2810 /* Write MAC register values back to h/w defaults */
2811 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2812 mac_reg &= ~(0xF << 14);
2813 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2815 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2816 mac_reg &= ~E1000_RCTL_SECRC;
2817 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2819 ret_val = e1000_read_kmrn_reg_generic(hw,
2820 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2824 ret_val = e1000_write_kmrn_reg_generic(hw,
2825 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2829 ret_val = e1000_read_kmrn_reg_generic(hw,
2830 E1000_KMRNCTRLSTA_HD_CTRL,
2834 data &= ~(0xF << 8);
2836 ret_val = e1000_write_kmrn_reg_generic(hw,
2837 E1000_KMRNCTRLSTA_HD_CTRL,
2842 /* Write PHY register values back to h/w defaults */
2843 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2844 data &= ~(0x7F << 5);
2845 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2848 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2850 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2853 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2854 data &= ~(0x3FF << 2);
2856 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2859 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2862 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2863 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2869 /* re-enable Rx path after enabling/disabling workaround */
2870 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2875 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2876 * done after every PHY reset.
2877 * @hw: pointer to the HW structure
2879 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2881 s32 ret_val = E1000_SUCCESS;
2883 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2885 if (hw->mac.type != e1000_pch2lan)
2886 return E1000_SUCCESS;
2888 /* Set MDIO slow mode before any other MDIO access */
2889 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2893 ret_val = hw->phy.ops.acquire(hw);
2896 /* set MSE higher to enable link to stay up when noise is high */
2897 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2900 /* drop link after 5 times MSE threshold was reached */
2901 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2903 hw->phy.ops.release(hw);
2909 * e1000_k1_gig_workaround_lv - K1 Si workaround
2910 * @hw: pointer to the HW structure
2912 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2913 * Disable K1 for 1000 and 100 speeds
2915 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2917 s32 ret_val = E1000_SUCCESS;
2920 DEBUGFUNC("e1000_k1_workaround_lv");
2922 if (hw->mac.type != e1000_pch2lan)
2923 return E1000_SUCCESS;
2925 /* Set K1 beacon duration based on 10Mbs speed */
2926 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2930 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2931 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2933 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2936 /* LV 1G/100 Packet drop issue wa */
2937 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2941 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2942 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2948 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2949 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2950 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2951 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2959 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2960 * @hw: pointer to the HW structure
2961 * @gate: boolean set to true to gate, false to ungate
2963 * Gate/ungate the automatic PHY configuration via hardware; perform
2964 * the configuration via software instead.
2966 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2970 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2972 if (hw->mac.type < e1000_pch2lan)
2975 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2978 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2980 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2982 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2986 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2987 * @hw: pointer to the HW structure
2989 * Check the appropriate indication the MAC has finished configuring the
2990 * PHY after a software reset.
2992 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2994 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2996 DEBUGFUNC("e1000_lan_init_done_ich8lan");
2998 /* Wait for basic configuration completes before proceeding */
3000 data = E1000_READ_REG(hw, E1000_STATUS);
3001 data &= E1000_STATUS_LAN_INIT_DONE;
3003 } while ((!data) && --loop);
3005 /* If basic configuration is incomplete before the above loop
3006 * count reaches 0, loading the configuration from NVM will
3007 * leave the PHY in a bad state possibly resulting in no link.
3010 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3012 /* Clear the Init Done bit for the next init event */
3013 data = E1000_READ_REG(hw, E1000_STATUS);
3014 data &= ~E1000_STATUS_LAN_INIT_DONE;
3015 E1000_WRITE_REG(hw, E1000_STATUS, data);
3019 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3020 * @hw: pointer to the HW structure
3022 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3024 s32 ret_val = E1000_SUCCESS;
3027 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3029 if (hw->phy.ops.check_reset_block(hw))
3030 return E1000_SUCCESS;
3032 /* Allow time for h/w to get to quiescent state after reset */
3035 /* Perform any necessary post-reset workarounds */
3036 switch (hw->mac.type) {
3038 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3043 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3051 /* Clear the host wakeup bit after lcd reset */
3052 if (hw->mac.type >= e1000_pchlan) {
3053 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3054 reg &= ~BM_WUC_HOST_WU_BIT;
3055 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3058 /* Configure the LCD with the extended configuration region in NVM */
3059 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3063 /* Configure the LCD with the OEM bits in NVM */
3064 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3066 if (hw->mac.type == e1000_pch2lan) {
3067 /* Ungate automatic PHY configuration on non-managed 82579 */
3068 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3069 E1000_ICH_FWSM_FW_VALID)) {
3071 e1000_gate_hw_phy_config_ich8lan(hw, false);
3074 /* Set EEE LPI Update Timer to 200usec */
3075 ret_val = hw->phy.ops.acquire(hw);
3078 ret_val = e1000_write_emi_reg_locked(hw,
3079 I82579_LPI_UPDATE_TIMER,
3081 hw->phy.ops.release(hw);
3088 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3089 * @hw: pointer to the HW structure
3092 * This is a function pointer entry point called by drivers
3093 * or other shared routines.
3095 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3097 s32 ret_val = E1000_SUCCESS;
3099 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3101 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3102 if ((hw->mac.type == e1000_pch2lan) &&
3103 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3104 e1000_gate_hw_phy_config_ich8lan(hw, true);
3106 ret_val = e1000_phy_hw_reset_generic(hw);
3110 return e1000_post_phy_reset_ich8lan(hw);
3114 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3115 * @hw: pointer to the HW structure
3116 * @active: true to enable LPLU, false to disable
3118 * Sets the LPLU state according to the active flag. For PCH, if OEM write
3119 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3120 * the phy speed. This function will manually set the LPLU bit and restart
3121 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3122 * since it configures the same bit.
3124 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3129 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3130 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3135 oem_reg |= HV_OEM_BITS_LPLU;
3137 oem_reg &= ~HV_OEM_BITS_LPLU;
3139 if (!hw->phy.ops.check_reset_block(hw))
3140 oem_reg |= HV_OEM_BITS_RESTART_AN;
3142 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3146 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3147 * @hw: pointer to the HW structure
3148 * @active: true to enable LPLU, false to disable
3150 * Sets the LPLU D0 state according to the active flag. When
3151 * activating LPLU this function also disables smart speed
3152 * and vice versa. LPLU will not be activated unless the
3153 * device autonegotiation advertisement meets standards of
3154 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3155 * This is a function pointer entry point only called by
3156 * PHY setup routines.
3158 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3160 struct e1000_phy_info *phy = &hw->phy;
3162 s32 ret_val = E1000_SUCCESS;
3165 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3167 if (phy->type == e1000_phy_ife)
3168 return E1000_SUCCESS;
3170 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3173 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3174 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3176 if (phy->type != e1000_phy_igp_3)
3177 return E1000_SUCCESS;
3179 /* Call gig speed drop workaround on LPLU before accessing
3182 if (hw->mac.type == e1000_ich8lan)
3183 e1000_gig_downshift_workaround_ich8lan(hw);
3185 /* When LPLU is enabled, we should disable SmartSpeed */
3186 ret_val = phy->ops.read_reg(hw,
3187 IGP01E1000_PHY_PORT_CONFIG,
3191 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3192 ret_val = phy->ops.write_reg(hw,
3193 IGP01E1000_PHY_PORT_CONFIG,
3198 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3199 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3201 if (phy->type != e1000_phy_igp_3)
3202 return E1000_SUCCESS;
3204 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3205 * during Dx states where the power conservation is most
3206 * important. During driver activity we should enable
3207 * SmartSpeed, so performance is maintained.
3209 if (phy->smart_speed == e1000_smart_speed_on) {
3210 ret_val = phy->ops.read_reg(hw,
3211 IGP01E1000_PHY_PORT_CONFIG,
3216 data |= IGP01E1000_PSCFR_SMART_SPEED;
3217 ret_val = phy->ops.write_reg(hw,
3218 IGP01E1000_PHY_PORT_CONFIG,
3222 } else if (phy->smart_speed == e1000_smart_speed_off) {
3223 ret_val = phy->ops.read_reg(hw,
3224 IGP01E1000_PHY_PORT_CONFIG,
3229 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3230 ret_val = phy->ops.write_reg(hw,
3231 IGP01E1000_PHY_PORT_CONFIG,
3238 return E1000_SUCCESS;
3242 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3243 * @hw: pointer to the HW structure
3244 * @active: true to enable LPLU, false to disable
3246 * Sets the LPLU D3 state according to the active flag. When
3247 * activating LPLU this function also disables smart speed
3248 * and vice versa. LPLU will not be activated unless the
3249 * device autonegotiation advertisement meets standards of
3250 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3251 * This is a function pointer entry point only called by
3252 * PHY setup routines.
3254 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3256 struct e1000_phy_info *phy = &hw->phy;
3258 s32 ret_val = E1000_SUCCESS;
3261 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3263 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3266 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3267 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3269 if (phy->type != e1000_phy_igp_3)
3270 return E1000_SUCCESS;
3272 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3273 * during Dx states where the power conservation is most
3274 * important. During driver activity we should enable
3275 * SmartSpeed, so performance is maintained.
3277 if (phy->smart_speed == e1000_smart_speed_on) {
3278 ret_val = phy->ops.read_reg(hw,
3279 IGP01E1000_PHY_PORT_CONFIG,
3284 data |= IGP01E1000_PSCFR_SMART_SPEED;
3285 ret_val = phy->ops.write_reg(hw,
3286 IGP01E1000_PHY_PORT_CONFIG,
3290 } else if (phy->smart_speed == e1000_smart_speed_off) {
3291 ret_val = phy->ops.read_reg(hw,
3292 IGP01E1000_PHY_PORT_CONFIG,
3297 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3298 ret_val = phy->ops.write_reg(hw,
3299 IGP01E1000_PHY_PORT_CONFIG,
3304 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3305 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3306 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3307 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3308 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3310 if (phy->type != e1000_phy_igp_3)
3311 return E1000_SUCCESS;
3313 /* Call gig speed drop workaround on LPLU before accessing
3316 if (hw->mac.type == e1000_ich8lan)
3317 e1000_gig_downshift_workaround_ich8lan(hw);
3319 /* When LPLU is enabled, we should disable SmartSpeed */
3320 ret_val = phy->ops.read_reg(hw,
3321 IGP01E1000_PHY_PORT_CONFIG,
3326 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3327 ret_val = phy->ops.write_reg(hw,
3328 IGP01E1000_PHY_PORT_CONFIG,
3336 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3337 * @hw: pointer to the HW structure
3338 * @bank: pointer to the variable that returns the active bank
3340 * Reads signature byte from the NVM using the flash access registers.
3341 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3343 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3346 struct e1000_nvm_info *nvm = &hw->nvm;
3347 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3348 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3353 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3355 switch (hw->mac.type) {
3358 bank1_offset = nvm->flash_bank_size;
3359 act_offset = E1000_ICH_NVM_SIG_WORD;
3361 /* set bank to 0 in case flash read fails */
3365 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3369 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3370 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3371 E1000_ICH_NVM_SIG_VALUE) {
3373 return E1000_SUCCESS;
3377 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3382 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3383 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3384 E1000_ICH_NVM_SIG_VALUE) {
3386 return E1000_SUCCESS;
3389 DEBUGOUT("ERROR: No valid NVM bank present\n");
3390 return -E1000_ERR_NVM;
3393 eecd = E1000_READ_REG(hw, E1000_EECD);
3394 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3395 E1000_EECD_SEC1VAL_VALID_MASK) {
3396 if (eecd & E1000_EECD_SEC1VAL)
3401 return E1000_SUCCESS;
3403 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3406 /* set bank to 0 in case flash read fails */
3410 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3414 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3415 E1000_ICH_NVM_SIG_VALUE) {
3417 return E1000_SUCCESS;
3421 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3426 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3427 E1000_ICH_NVM_SIG_VALUE) {
3429 return E1000_SUCCESS;
3432 DEBUGOUT("ERROR: No valid NVM bank present\n");
3433 return -E1000_ERR_NVM;
3438 * e1000_read_nvm_spt - NVM access for SPT
3439 * @hw: pointer to the HW structure
3440 * @offset: The offset (in bytes) of the word(s) to read.
3441 * @words: Size of data to read in words.
3442 * @data: pointer to the word(s) to read at offset.
3444 * Reads a word(s) from the NVM
3446 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3449 struct e1000_nvm_info *nvm = &hw->nvm;
3450 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3452 s32 ret_val = E1000_SUCCESS;
3458 DEBUGFUNC("e1000_read_nvm_spt");
3460 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3462 DEBUGOUT("nvm parameter(s) out of bounds\n");
3463 ret_val = -E1000_ERR_NVM;
3467 nvm->ops.acquire(hw);
3469 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3470 if (ret_val != E1000_SUCCESS) {
3471 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3475 act_offset = (bank) ? nvm->flash_bank_size : 0;
3476 act_offset += offset;
3478 ret_val = E1000_SUCCESS;
3480 for (i = 0; i < words; i += 2) {
3481 if (words - i == 1) {
3482 if (dev_spec->shadow_ram[offset + i].modified) {
3484 dev_spec->shadow_ram[offset + i].value;
3486 offset_to_read = act_offset + i -
3487 ((act_offset + i) % 2);
3489 e1000_read_flash_dword_ich8lan(hw,
3494 if ((act_offset + i) % 2 == 0)
3495 data[i] = (u16)(dword & 0xFFFF);
3497 data[i] = (u16)((dword >> 16) & 0xFFFF);
3500 offset_to_read = act_offset + i;
3501 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3502 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3504 e1000_read_flash_dword_ich8lan(hw,
3510 if (dev_spec->shadow_ram[offset + i].modified)
3512 dev_spec->shadow_ram[offset + i].value;
3514 data[i] = (u16)(dword & 0xFFFF);
3515 if (dev_spec->shadow_ram[offset + i + 1].modified)
3517 dev_spec->shadow_ram[offset + i + 1].value;
3519 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3523 nvm->ops.release(hw);
3527 DEBUGOUT1("NVM read error: %d\n", ret_val);
3533 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3534 * @hw: pointer to the HW structure
3535 * @offset: The offset (in bytes) of the word(s) to read.
3536 * @words: Size of data to read in words
3537 * @data: Pointer to the word(s) to read at offset.
3539 * Reads a word(s) from the NVM using the flash access registers.
3541 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3544 struct e1000_nvm_info *nvm = &hw->nvm;
3545 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3547 s32 ret_val = E1000_SUCCESS;
3551 DEBUGFUNC("e1000_read_nvm_ich8lan");
3553 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3555 DEBUGOUT("nvm parameter(s) out of bounds\n");
3556 ret_val = -E1000_ERR_NVM;
3560 nvm->ops.acquire(hw);
3562 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3563 if (ret_val != E1000_SUCCESS) {
3564 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3568 act_offset = (bank) ? nvm->flash_bank_size : 0;
3569 act_offset += offset;
3571 ret_val = E1000_SUCCESS;
3572 for (i = 0; i < words; i++) {
3573 if (dev_spec->shadow_ram[offset + i].modified) {
3574 data[i] = dev_spec->shadow_ram[offset + i].value;
3576 ret_val = e1000_read_flash_word_ich8lan(hw,
3585 nvm->ops.release(hw);
3589 DEBUGOUT1("NVM read error: %d\n", ret_val);
3595 * e1000_flash_cycle_init_ich8lan - Initialize flash
3596 * @hw: pointer to the HW structure
3598 * This function does initial flash setup so that a new read/write/erase cycle
3601 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3603 union ich8_hws_flash_status hsfsts;
3604 s32 ret_val = -E1000_ERR_NVM;
3606 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3608 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3610 /* Check if the flash descriptor is valid */
3611 if (!hsfsts.hsf_status.fldesvalid) {
3612 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3613 return -E1000_ERR_NVM;
3616 /* Clear FCERR and DAEL in hw status by writing 1 */
3617 hsfsts.hsf_status.flcerr = 1;
3618 hsfsts.hsf_status.dael = 1;
3619 if (hw->mac.type >= e1000_pch_spt)
3620 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3621 hsfsts.regval & 0xFFFF);
3623 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3625 /* Either we should have a hardware SPI cycle in progress
3626 * bit to check against, in order to start a new cycle or
3627 * FDONE bit should be changed in the hardware so that it
3628 * is 1 after hardware reset, which can then be used as an
3629 * indication whether a cycle is in progress or has been
3633 if (!hsfsts.hsf_status.flcinprog) {
3634 /* There is no cycle running at present,
3635 * so we can start a cycle.
3636 * Begin by setting Flash Cycle Done.
3638 hsfsts.hsf_status.flcdone = 1;
3639 if (hw->mac.type >= e1000_pch_spt)
3640 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3641 hsfsts.regval & 0xFFFF);
3643 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3645 ret_val = E1000_SUCCESS;
3649 /* Otherwise poll for sometime so the current
3650 * cycle has a chance to end before giving up.
3652 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3653 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3655 if (!hsfsts.hsf_status.flcinprog) {
3656 ret_val = E1000_SUCCESS;
3661 if (ret_val == E1000_SUCCESS) {
3662 /* Successful in waiting for previous cycle to timeout,
3663 * now set the Flash Cycle Done.
3665 hsfsts.hsf_status.flcdone = 1;
3666 if (hw->mac.type >= e1000_pch_spt)
3667 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3668 hsfsts.regval & 0xFFFF);
3670 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3673 DEBUGOUT("Flash controller busy, cannot get access\n");
3681 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3682 * @hw: pointer to the HW structure
3683 * @timeout: maximum time to wait for completion
3685 * This function starts a flash cycle and waits for its completion.
3687 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3689 union ich8_hws_flash_ctrl hsflctl;
3690 union ich8_hws_flash_status hsfsts;
3693 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3695 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3696 if (hw->mac.type >= e1000_pch_spt)
3697 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3699 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3700 hsflctl.hsf_ctrl.flcgo = 1;
3702 if (hw->mac.type >= e1000_pch_spt)
3703 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3704 hsflctl.regval << 16);
3706 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3708 /* wait till FDONE bit is set to 1 */
3710 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3711 if (hsfsts.hsf_status.flcdone)
3714 } while (i++ < timeout);
3716 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3717 return E1000_SUCCESS;
3719 return -E1000_ERR_NVM;
3723 * e1000_read_flash_dword_ich8lan - Read dword from flash
3724 * @hw: pointer to the HW structure
3725 * @offset: offset to data location
3726 * @data: pointer to the location for storing the data
3728 * Reads the flash dword at offset into data. Offset is converted
3729 * to bytes before read.
3731 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3734 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3737 return -E1000_ERR_NVM;
3739 /* Must convert word offset into bytes. */
3742 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3746 * e1000_read_flash_word_ich8lan - Read word from flash
3747 * @hw: pointer to the HW structure
3748 * @offset: offset to data location
3749 * @data: pointer to the location for storing the data
3751 * Reads the flash word at offset into data. Offset is converted
3752 * to bytes before read.
3754 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3757 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3760 return -E1000_ERR_NVM;
3762 /* Must convert offset into bytes. */
3765 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3769 * e1000_read_flash_byte_ich8lan - Read byte from flash
3770 * @hw: pointer to the HW structure
3771 * @offset: The offset of the byte to read.
3772 * @data: Pointer to a byte to store the value read.
3774 * Reads a single byte from the NVM using the flash access registers.
3776 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3782 /* In SPT, only 32 bits access is supported,
3783 * so this function should not be called.
3785 if (hw->mac.type >= e1000_pch_spt)
3786 return -E1000_ERR_NVM;
3788 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3795 return E1000_SUCCESS;
3799 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3800 * @hw: pointer to the HW structure
3801 * @offset: The offset (in bytes) of the byte or word to read.
3802 * @size: Size of data to read, 1=byte 2=word
3803 * @data: Pointer to the word to store the value read.
3805 * Reads a byte or word from the NVM using the flash access registers.
3807 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3810 union ich8_hws_flash_status hsfsts;
3811 union ich8_hws_flash_ctrl hsflctl;
3812 u32 flash_linear_addr;
3814 s32 ret_val = -E1000_ERR_NVM;
3817 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3819 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3820 return -E1000_ERR_NVM;
3821 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3822 hw->nvm.flash_base_addr);
3827 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3828 if (ret_val != E1000_SUCCESS)
3830 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3832 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3833 hsflctl.hsf_ctrl.fldbcount = size - 1;
3834 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3835 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3836 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3838 ret_val = e1000_flash_cycle_ich8lan(hw,
3839 ICH_FLASH_READ_COMMAND_TIMEOUT);
3841 /* Check if FCERR is set to 1, if set to 1, clear it
3842 * and try the whole sequence a few more times, else
3843 * read in (shift in) the Flash Data0, the order is
3844 * least significant byte first msb to lsb
3846 if (ret_val == E1000_SUCCESS) {
3847 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3849 *data = (u8)(flash_data & 0x000000FF);
3851 *data = (u16)(flash_data & 0x0000FFFF);
3854 /* If we've gotten here, then things are probably
3855 * completely hosed, but if the error condition is
3856 * detected, it won't hurt to give it another try...
3857 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3859 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3861 if (hsfsts.hsf_status.flcerr) {
3862 /* Repeat for some time before giving up. */
3864 } else if (!hsfsts.hsf_status.flcdone) {
3865 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3869 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3875 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3876 * @hw: pointer to the HW structure
3877 * @offset: The offset (in bytes) of the dword to read.
3878 * @data: Pointer to the dword to store the value read.
3880 * Reads a byte or word from the NVM using the flash access registers.
3882 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3885 union ich8_hws_flash_status hsfsts;
3886 union ich8_hws_flash_ctrl hsflctl;
3887 u32 flash_linear_addr;
3888 s32 ret_val = -E1000_ERR_NVM;
3891 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3893 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3894 hw->mac.type < e1000_pch_spt)
3895 return -E1000_ERR_NVM;
3896 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3897 hw->nvm.flash_base_addr);
3902 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3903 if (ret_val != E1000_SUCCESS)
3905 /* In SPT, This register is in Lan memory space, not flash.
3906 * Therefore, only 32 bit access is supported
3908 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3910 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3911 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3912 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3913 /* In SPT, This register is in Lan memory space, not flash.
3914 * Therefore, only 32 bit access is supported
3916 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3917 (u32)hsflctl.regval << 16);
3918 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3920 ret_val = e1000_flash_cycle_ich8lan(hw,
3921 ICH_FLASH_READ_COMMAND_TIMEOUT);
3923 /* Check if FCERR is set to 1, if set to 1, clear it
3924 * and try the whole sequence a few more times, else
3925 * read in (shift in) the Flash Data0, the order is
3926 * least significant byte first msb to lsb
3928 if (ret_val == E1000_SUCCESS) {
3929 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3932 /* If we've gotten here, then things are probably
3933 * completely hosed, but if the error condition is
3934 * detected, it won't hurt to give it another try...
3935 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3937 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3939 if (hsfsts.hsf_status.flcerr) {
3940 /* Repeat for some time before giving up. */
3942 } else if (!hsfsts.hsf_status.flcdone) {
3943 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3947 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3953 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3954 * @hw: pointer to the HW structure
3955 * @offset: The offset (in bytes) of the word(s) to write.
3956 * @words: Size of data to write in words
3957 * @data: Pointer to the word(s) to write at offset.
3959 * Writes a byte or word to the NVM using the flash access registers.
3961 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3964 struct e1000_nvm_info *nvm = &hw->nvm;
3965 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3968 DEBUGFUNC("e1000_write_nvm_ich8lan");
3970 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3972 DEBUGOUT("nvm parameter(s) out of bounds\n");
3973 return -E1000_ERR_NVM;
3976 nvm->ops.acquire(hw);
3978 for (i = 0; i < words; i++) {
3979 dev_spec->shadow_ram[offset + i].modified = true;
3980 dev_spec->shadow_ram[offset + i].value = data[i];
3983 nvm->ops.release(hw);
3985 return E1000_SUCCESS;
3989 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3990 * @hw: pointer to the HW structure
3992 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3993 * which writes the checksum to the shadow ram. The changes in the shadow
3994 * ram are then committed to the EEPROM by processing each bank at a time
3995 * checking for the modified bit and writing only the pending changes.
3996 * After a successful commit, the shadow ram is cleared and is ready for
3999 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4001 struct e1000_nvm_info *nvm = &hw->nvm;
4002 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4003 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4007 DEBUGFUNC("e1000_update_nvm_checksum_spt");
4009 ret_val = e1000_update_nvm_checksum_generic(hw);
4013 if (nvm->type != e1000_nvm_flash_sw)
4016 nvm->ops.acquire(hw);
4018 /* We're writing to the opposite bank so if we're on bank 1,
4019 * write to bank 0 etc. We also need to erase the segment that
4020 * is going to be written
4022 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4023 if (ret_val != E1000_SUCCESS) {
4024 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4029 new_bank_offset = nvm->flash_bank_size;
4030 old_bank_offset = 0;
4031 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4035 old_bank_offset = nvm->flash_bank_size;
4036 new_bank_offset = 0;
4037 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4041 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4042 /* Determine whether to write the value stored
4043 * in the other NVM bank or a modified value stored
4046 ret_val = e1000_read_flash_dword_ich8lan(hw,
4047 i + old_bank_offset,
4050 if (dev_spec->shadow_ram[i].modified) {
4051 dword &= 0xffff0000;
4052 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4054 if (dev_spec->shadow_ram[i + 1].modified) {
4055 dword &= 0x0000ffff;
4056 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4062 /* If the word is 0x13, then make sure the signature bits
4063 * (15:14) are 11b until the commit has completed.
4064 * This will allow us to write 10b which indicates the
4065 * signature is valid. We want to do this after the write
4066 * has completed so that we don't mark the segment valid
4067 * while the write is still in progress
4069 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4070 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4072 /* Convert offset to bytes. */
4073 act_offset = (i + new_bank_offset) << 1;
4077 /* Write the data to the new bank. Offset in words*/
4078 act_offset = i + new_bank_offset;
4079 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4085 /* Don't bother writing the segment valid bits if sector
4086 * programming failed.
4089 DEBUGOUT("Flash commit failed.\n");
4093 /* Finally validate the new segment by setting bit 15:14
4094 * to 10b in word 0x13 , this can be done without an
4095 * erase as well since these bits are 11 to start with
4096 * and we need to change bit 14 to 0b
4098 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4100 /*offset in words but we read dword*/
4102 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4107 dword &= 0xBFFFFFFF;
4108 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4113 /* And invalidate the previously valid segment by setting
4114 * its signature word (0x13) high_byte to 0b. This can be
4115 * done without an erase because flash erase sets all bits
4116 * to 1's. We can write 1's to 0's without an erase
4118 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4120 /* offset in words but we read dword*/
4121 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4122 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4127 dword &= 0x00FFFFFF;
4128 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4133 /* Great! Everything worked, we can now clear the cached entries. */
4134 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4135 dev_spec->shadow_ram[i].modified = false;
4136 dev_spec->shadow_ram[i].value = 0xFFFF;
4140 nvm->ops.release(hw);
4142 /* Reload the EEPROM, or else modifications will not appear
4143 * until after the next adapter reset.
4146 nvm->ops.reload(hw);
4152 DEBUGOUT1("NVM update error: %d\n", ret_val);
4158 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4159 * @hw: pointer to the HW structure
4161 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4162 * which writes the checksum to the shadow ram. The changes in the shadow
4163 * ram are then committed to the EEPROM by processing each bank at a time
4164 * checking for the modified bit and writing only the pending changes.
4165 * After a successful commit, the shadow ram is cleared and is ready for
4168 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4170 struct e1000_nvm_info *nvm = &hw->nvm;
4171 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4172 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4176 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4178 ret_val = e1000_update_nvm_checksum_generic(hw);
4182 if (nvm->type != e1000_nvm_flash_sw)
4185 nvm->ops.acquire(hw);
4187 /* We're writing to the opposite bank so if we're on bank 1,
4188 * write to bank 0 etc. We also need to erase the segment that
4189 * is going to be written
4191 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4192 if (ret_val != E1000_SUCCESS) {
4193 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4198 new_bank_offset = nvm->flash_bank_size;
4199 old_bank_offset = 0;
4200 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4204 old_bank_offset = nvm->flash_bank_size;
4205 new_bank_offset = 0;
4206 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4210 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4211 if (dev_spec->shadow_ram[i].modified) {
4212 data = dev_spec->shadow_ram[i].value;
4214 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4220 /* If the word is 0x13, then make sure the signature bits
4221 * (15:14) are 11b until the commit has completed.
4222 * This will allow us to write 10b which indicates the
4223 * signature is valid. We want to do this after the write
4224 * has completed so that we don't mark the segment valid
4225 * while the write is still in progress
4227 if (i == E1000_ICH_NVM_SIG_WORD)
4228 data |= E1000_ICH_NVM_SIG_MASK;
4230 /* Convert offset to bytes. */
4231 act_offset = (i + new_bank_offset) << 1;
4235 /* Write the bytes to the new bank. */
4236 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4243 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4250 /* Don't bother writing the segment valid bits if sector
4251 * programming failed.
4254 DEBUGOUT("Flash commit failed.\n");
4258 /* Finally validate the new segment by setting bit 15:14
4259 * to 10b in word 0x13 , this can be done without an
4260 * erase as well since these bits are 11 to start with
4261 * and we need to change bit 14 to 0b
4263 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4264 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4269 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4274 /* And invalidate the previously valid segment by setting
4275 * its signature word (0x13) high_byte to 0b. This can be
4276 * done without an erase because flash erase sets all bits
4277 * to 1's. We can write 1's to 0's without an erase
4279 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4281 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4286 /* Great! Everything worked, we can now clear the cached entries. */
4287 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4288 dev_spec->shadow_ram[i].modified = false;
4289 dev_spec->shadow_ram[i].value = 0xFFFF;
4293 nvm->ops.release(hw);
4295 /* Reload the EEPROM, or else modifications will not appear
4296 * until after the next adapter reset.
4299 nvm->ops.reload(hw);
4305 DEBUGOUT1("NVM update error: %d\n", ret_val);
4311 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4312 * @hw: pointer to the HW structure
4314 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4315 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4316 * calculated, in which case we need to calculate the checksum and set bit 6.
4318 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4323 u16 valid_csum_mask;
4325 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4327 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4328 * the checksum needs to be fixed. This bit is an indication that
4329 * the NVM was prepared by OEM software and did not calculate
4330 * the checksum...a likely scenario.
4332 switch (hw->mac.type) {
4337 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4340 word = NVM_FUTURE_INIT_WORD1;
4341 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4345 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4349 if (!(data & valid_csum_mask)) {
4350 data |= valid_csum_mask;
4351 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4354 ret_val = hw->nvm.ops.update(hw);
4359 return e1000_validate_nvm_checksum_generic(hw);
4363 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4364 * @hw: pointer to the HW structure
4365 * @offset: The offset (in bytes) of the byte/word to read.
4366 * @size: Size of data to read, 1=byte 2=word
4367 * @data: The byte(s) to write to the NVM.
4369 * Writes one/two bytes to the NVM using the flash access registers.
4371 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4374 union ich8_hws_flash_status hsfsts;
4375 union ich8_hws_flash_ctrl hsflctl;
4376 u32 flash_linear_addr;
4381 DEBUGFUNC("e1000_write_ich8_data");
4383 if (hw->mac.type >= e1000_pch_spt) {
4384 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4385 return -E1000_ERR_NVM;
4387 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4388 return -E1000_ERR_NVM;
4391 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4392 hw->nvm.flash_base_addr);
4397 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4398 if (ret_val != E1000_SUCCESS)
4400 /* In SPT, This register is in Lan memory space, not
4401 * flash. Therefore, only 32 bit access is supported
4403 if (hw->mac.type >= e1000_pch_spt)
4405 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4408 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4410 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4411 hsflctl.hsf_ctrl.fldbcount = size - 1;
4412 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4413 /* In SPT, This register is in Lan memory space,
4414 * not flash. Therefore, only 32 bit access is
4417 if (hw->mac.type >= e1000_pch_spt)
4418 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4419 hsflctl.regval << 16);
4421 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4424 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4427 flash_data = (u32)data & 0x00FF;
4429 flash_data = (u32)data;
4431 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4433 /* check if FCERR is set to 1 , if set to 1, clear it
4434 * and try the whole sequence a few more times else done
4437 e1000_flash_cycle_ich8lan(hw,
4438 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4439 if (ret_val == E1000_SUCCESS)
4442 /* If we're here, then things are most likely
4443 * completely hosed, but if the error condition
4444 * is detected, it won't hurt to give it another
4445 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4447 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4448 if (hsfsts.hsf_status.flcerr)
4449 /* Repeat for some time before giving up. */
4451 if (!hsfsts.hsf_status.flcdone) {
4452 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4455 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4461 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4462 * @hw: pointer to the HW structure
4463 * @offset: The offset (in bytes) of the dwords to read.
4464 * @data: The 4 bytes to write to the NVM.
4466 * Writes one/two/four bytes to the NVM using the flash access registers.
4468 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4471 union ich8_hws_flash_status hsfsts;
4472 union ich8_hws_flash_ctrl hsflctl;
4473 u32 flash_linear_addr;
4477 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4479 if (hw->mac.type >= e1000_pch_spt) {
4480 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4481 return -E1000_ERR_NVM;
4483 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4484 hw->nvm.flash_base_addr);
4488 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4489 if (ret_val != E1000_SUCCESS)
4492 /* In SPT, This register is in Lan memory space, not
4493 * flash. Therefore, only 32 bit access is supported
4495 if (hw->mac.type >= e1000_pch_spt)
4496 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4500 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4503 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4504 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4506 /* In SPT, This register is in Lan memory space,
4507 * not flash. Therefore, only 32 bit access is
4510 if (hw->mac.type >= e1000_pch_spt)
4511 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4512 hsflctl.regval << 16);
4514 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4517 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4519 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4521 /* check if FCERR is set to 1 , if set to 1, clear it
4522 * and try the whole sequence a few more times else done
4524 ret_val = e1000_flash_cycle_ich8lan(hw,
4525 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4527 if (ret_val == E1000_SUCCESS)
4530 /* If we're here, then things are most likely
4531 * completely hosed, but if the error condition
4532 * is detected, it won't hurt to give it another
4533 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4535 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4537 if (hsfsts.hsf_status.flcerr)
4538 /* Repeat for some time before giving up. */
4540 if (!hsfsts.hsf_status.flcdone) {
4541 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4544 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4550 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4551 * @hw: pointer to the HW structure
4552 * @offset: The index of the byte to read.
4553 * @data: The byte to write to the NVM.
4555 * Writes a single byte to the NVM using the flash access registers.
4557 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4560 u16 word = (u16)data;
4562 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4564 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4568 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4569 * @hw: pointer to the HW structure
4570 * @offset: The offset of the word to write.
4571 * @dword: The dword to write to the NVM.
4573 * Writes a single dword to the NVM using the flash access registers.
4574 * Goes through a retry algorithm before giving up.
4576 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4577 u32 offset, u32 dword)
4580 u16 program_retries;
4582 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4584 /* Must convert word offset into bytes. */
4587 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4591 for (program_retries = 0; program_retries < 100; program_retries++) {
4592 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4594 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4595 if (ret_val == E1000_SUCCESS)
4598 if (program_retries == 100)
4599 return -E1000_ERR_NVM;
4601 return E1000_SUCCESS;
4605 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4606 * @hw: pointer to the HW structure
4607 * @offset: The offset of the byte to write.
4608 * @byte: The byte to write to the NVM.
4610 * Writes a single byte to the NVM using the flash access registers.
4611 * Goes through a retry algorithm before giving up.
4613 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4614 u32 offset, u8 byte)
4617 u16 program_retries;
4619 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4621 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4625 for (program_retries = 0; program_retries < 100; program_retries++) {
4626 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4628 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4629 if (ret_val == E1000_SUCCESS)
4632 if (program_retries == 100)
4633 return -E1000_ERR_NVM;
4635 return E1000_SUCCESS;
4639 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4640 * @hw: pointer to the HW structure
4641 * @bank: 0 for first bank, 1 for second bank, etc.
4643 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4644 * bank N is 4096 * N + flash_reg_addr.
4646 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4648 struct e1000_nvm_info *nvm = &hw->nvm;
4649 union ich8_hws_flash_status hsfsts;
4650 union ich8_hws_flash_ctrl hsflctl;
4651 u32 flash_linear_addr;
4652 /* bank size is in 16bit words - adjust to bytes */
4653 u32 flash_bank_size = nvm->flash_bank_size * 2;
4656 s32 j, iteration, sector_size;
4658 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4660 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4662 /* Determine HW Sector size: Read BERASE bits of hw flash status
4664 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4665 * consecutive sectors. The start index for the nth Hw sector
4666 * can be calculated as = bank * 4096 + n * 256
4667 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4668 * The start index for the nth Hw sector can be calculated
4670 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4671 * (ich9 only, otherwise error condition)
4672 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4674 switch (hsfsts.hsf_status.berasesz) {
4676 /* Hw sector size 256 */
4677 sector_size = ICH_FLASH_SEG_SIZE_256;
4678 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4681 sector_size = ICH_FLASH_SEG_SIZE_4K;
4685 sector_size = ICH_FLASH_SEG_SIZE_8K;
4689 sector_size = ICH_FLASH_SEG_SIZE_64K;
4693 return -E1000_ERR_NVM;
4696 /* Start with the base address, then add the sector offset. */
4697 flash_linear_addr = hw->nvm.flash_base_addr;
4698 flash_linear_addr += (bank) ? flash_bank_size : 0;
4700 for (j = 0; j < iteration; j++) {
4702 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4705 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4709 /* Write a value 11 (block Erase) in Flash
4710 * Cycle field in hw flash control
4712 if (hw->mac.type >= e1000_pch_spt)
4714 E1000_READ_FLASH_REG(hw,
4715 ICH_FLASH_HSFSTS)>>16;
4718 E1000_READ_FLASH_REG16(hw,
4721 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4722 if (hw->mac.type >= e1000_pch_spt)
4723 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4724 hsflctl.regval << 16);
4726 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4729 /* Write the last 24 bits of an index within the
4730 * block into Flash Linear address field in Flash
4733 flash_linear_addr += (j * sector_size);
4734 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4737 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4738 if (ret_val == E1000_SUCCESS)
4741 /* Check if FCERR is set to 1. If 1,
4742 * clear it and try the whole sequence
4743 * a few more times else Done
4745 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4747 if (hsfsts.hsf_status.flcerr)
4748 /* repeat for some time before giving up */
4750 else if (!hsfsts.hsf_status.flcdone)
4752 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4755 return E1000_SUCCESS;
4759 * e1000_valid_led_default_ich8lan - Set the default LED settings
4760 * @hw: pointer to the HW structure
4761 * @data: Pointer to the LED settings
4763 * Reads the LED default settings from the NVM to data. If the NVM LED
4764 * settings is all 0's or F's, set the LED default to a valid LED default
4767 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4771 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4773 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4775 DEBUGOUT("NVM Read Error\n");
4779 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4780 *data = ID_LED_DEFAULT_ICH8LAN;
4782 return E1000_SUCCESS;
4786 * e1000_id_led_init_pchlan - store LED configurations
4787 * @hw: pointer to the HW structure
4789 * PCH does not control LEDs via the LEDCTL register, rather it uses
4790 * the PHY LED configuration register.
4792 * PCH also does not have an "always on" or "always off" mode which
4793 * complicates the ID feature. Instead of using the "on" mode to indicate
4794 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4795 * use "link_up" mode. The LEDs will still ID on request if there is no
4796 * link based on logic in e1000_led_[on|off]_pchlan().
4798 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4800 struct e1000_mac_info *mac = &hw->mac;
4802 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4803 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4804 u16 data, i, temp, shift;
4806 DEBUGFUNC("e1000_id_led_init_pchlan");
4808 /* Get default ID LED modes */
4809 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4813 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4814 mac->ledctl_mode1 = mac->ledctl_default;
4815 mac->ledctl_mode2 = mac->ledctl_default;
4817 for (i = 0; i < 4; i++) {
4818 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4821 case ID_LED_ON1_DEF2:
4822 case ID_LED_ON1_ON2:
4823 case ID_LED_ON1_OFF2:
4824 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4825 mac->ledctl_mode1 |= (ledctl_on << shift);
4827 case ID_LED_OFF1_DEF2:
4828 case ID_LED_OFF1_ON2:
4829 case ID_LED_OFF1_OFF2:
4830 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4831 mac->ledctl_mode1 |= (ledctl_off << shift);
4838 case ID_LED_DEF1_ON2:
4839 case ID_LED_ON1_ON2:
4840 case ID_LED_OFF1_ON2:
4841 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4842 mac->ledctl_mode2 |= (ledctl_on << shift);
4844 case ID_LED_DEF1_OFF2:
4845 case ID_LED_ON1_OFF2:
4846 case ID_LED_OFF1_OFF2:
4847 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4848 mac->ledctl_mode2 |= (ledctl_off << shift);
4856 return E1000_SUCCESS;
4860 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4861 * @hw: pointer to the HW structure
4863 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4864 * register, so the bus width is hard coded.
4866 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4868 struct e1000_bus_info *bus = &hw->bus;
4871 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4873 ret_val = e1000_get_bus_info_pcie_generic(hw);
4875 /* ICH devices are "PCI Express"-ish. They have
4876 * a configuration space, but do not contain
4877 * PCI Express Capability registers, so bus width
4878 * must be hardcoded.
4880 if (bus->width == e1000_bus_width_unknown)
4881 bus->width = e1000_bus_width_pcie_x1;
4887 * e1000_reset_hw_ich8lan - Reset the hardware
4888 * @hw: pointer to the HW structure
4890 * Does a full reset of the hardware which includes a reset of the PHY and
4893 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4895 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4901 DEBUGFUNC("e1000_reset_hw_ich8lan");
4903 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4904 * on the last TLP read/write transaction when MAC is reset.
4906 ret_val = e1000_disable_pcie_master_generic(hw);
4908 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4910 DEBUGOUT("Masking off all interrupts\n");
4911 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4913 /* Disable the Transmit and Receive units. Then delay to allow
4914 * any pending transactions to complete before we hit the MAC
4915 * with the global reset.
4917 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4918 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4919 E1000_WRITE_FLUSH(hw);
4923 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4924 if (hw->mac.type == e1000_ich8lan) {
4925 /* Set Tx and Rx buffer allocation to 8k apiece. */
4926 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4927 /* Set Packet Buffer Size to 16k. */
4928 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4931 if (hw->mac.type == e1000_pchlan) {
4932 /* Save the NVM K1 bit setting*/
4933 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4937 if (kum_cfg & E1000_NVM_K1_ENABLE)
4938 dev_spec->nvm_k1_enabled = true;
4940 dev_spec->nvm_k1_enabled = false;
4943 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4945 if (!hw->phy.ops.check_reset_block(hw)) {
4946 /* Full-chip reset requires MAC and PHY reset at the same
4947 * time to make sure the interface between MAC and the
4948 * external PHY is reset.
4950 ctrl |= E1000_CTRL_PHY_RST;
4952 /* Gate automatic PHY configuration by hardware on
4955 if ((hw->mac.type == e1000_pch2lan) &&
4956 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4957 e1000_gate_hw_phy_config_ich8lan(hw, true);
4959 ret_val = e1000_acquire_swflag_ich8lan(hw);
4961 /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
4962 * may occur during global reset and cause system hang.
4963 * Configuration space access creates the needed delay.
4964 * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
4965 * insures configuration space read is done before global reset.
4967 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
4968 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
4969 DEBUGOUT("Issuing a global reset to ich8lan\n");
4970 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4971 /* cannot issue a flush here because it hangs the hardware */
4974 /* Configuration space access improve HW level time sync mechanism.
4975 * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
4976 * value to insure configuration space read is done
4977 * before any access to mac register.
4979 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
4980 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
4982 /* Set Phy Config Counter to 50msec */
4983 if (hw->mac.type == e1000_pch2lan) {
4984 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4985 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4986 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4987 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4991 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4993 if (ctrl & E1000_CTRL_PHY_RST) {
4994 ret_val = hw->phy.ops.get_cfg_done(hw);
4998 ret_val = e1000_post_phy_reset_ich8lan(hw);
5003 /* For PCH, this write will make sure that any noise
5004 * will be detected as a CRC error and be dropped rather than show up
5005 * as a bad packet to the DMA engine.
5007 if (hw->mac.type == e1000_pchlan)
5008 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5010 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5011 E1000_READ_REG(hw, E1000_ICR);
5013 reg = E1000_READ_REG(hw, E1000_KABGTXD);
5014 reg |= E1000_KABGTXD_BGSQLBIAS;
5015 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5017 return E1000_SUCCESS;
5021 * e1000_init_hw_ich8lan - Initialize the hardware
5022 * @hw: pointer to the HW structure
5024 * Prepares the hardware for transmit and receive by doing the following:
5025 * - initialize hardware bits
5026 * - initialize LED identification
5027 * - setup receive address registers
5028 * - setup flow control
5029 * - setup transmit descriptors
5030 * - clear statistics
5032 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5034 struct e1000_mac_info *mac = &hw->mac;
5035 u32 ctrl_ext, txdctl, snoop;
5039 DEBUGFUNC("e1000_init_hw_ich8lan");
5041 e1000_initialize_hw_bits_ich8lan(hw);
5043 /* Initialize identification LED */
5044 ret_val = mac->ops.id_led_init(hw);
5045 /* An error is not fatal and we should not stop init due to this */
5047 DEBUGOUT("Error initializing identification LED\n");
5049 /* Setup the receive address. */
5050 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5052 /* Zero out the Multicast HASH table */
5053 DEBUGOUT("Zeroing the MTA\n");
5054 for (i = 0; i < mac->mta_reg_count; i++)
5055 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5057 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5058 * the ME. Disable wakeup by clearing the host wakeup bit.
5059 * Reset the phy after disabling host wakeup to reset the Rx buffer.
5061 if (hw->phy.type == e1000_phy_82578) {
5062 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5063 i &= ~BM_WUC_HOST_WU_BIT;
5064 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5065 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5070 /* Setup link and flow control */
5071 ret_val = mac->ops.setup_link(hw);
5073 /* Set the transmit descriptor write-back policy for both queues */
5074 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5075 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5076 E1000_TXDCTL_FULL_TX_DESC_WB);
5077 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5078 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5079 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5080 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5081 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5082 E1000_TXDCTL_FULL_TX_DESC_WB);
5083 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5084 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5085 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5087 /* ICH8 has opposite polarity of no_snoop bits.
5088 * By default, we should use snoop behavior.
5090 if (mac->type == e1000_ich8lan)
5091 snoop = PCIE_ICH8_SNOOP_ALL;
5093 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5094 e1000_set_pcie_no_snoop_generic(hw, snoop);
5096 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5097 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5098 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5100 /* Clear all of the statistics registers (clear on read). It is
5101 * important that we do this after we have tried to establish link
5102 * because the symbol error count will increment wildly if there
5105 e1000_clear_hw_cntrs_ich8lan(hw);
5111 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5112 * @hw: pointer to the HW structure
5114 * Sets/Clears required hardware bits necessary for correctly setting up the
5115 * hardware for transmit and receive.
5117 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5121 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5123 /* Extended Device Control */
5124 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5126 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5127 if (hw->mac.type >= e1000_pchlan)
5128 reg |= E1000_CTRL_EXT_PHYPDEN;
5129 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5131 /* Transmit Descriptor Control 0 */
5132 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5134 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5136 /* Transmit Descriptor Control 1 */
5137 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5139 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5141 /* Transmit Arbitration Control 0 */
5142 reg = E1000_READ_REG(hw, E1000_TARC(0));
5143 if (hw->mac.type == e1000_ich8lan)
5144 reg |= (1 << 28) | (1 << 29);
5145 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5146 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5148 /* Transmit Arbitration Control 1 */
5149 reg = E1000_READ_REG(hw, E1000_TARC(1));
5150 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5154 reg |= (1 << 24) | (1 << 26) | (1 << 30);
5155 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5158 if (hw->mac.type == e1000_ich8lan) {
5159 reg = E1000_READ_REG(hw, E1000_STATUS);
5161 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5164 /* work-around descriptor data corruption issue during nfs v2 udp
5165 * traffic, just disable the nfs filtering capability
5167 reg = E1000_READ_REG(hw, E1000_RFCTL);
5168 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5170 /* Disable IPv6 extension header parsing because some malformed
5171 * IPv6 headers can hang the Rx.
5173 if (hw->mac.type == e1000_ich8lan)
5174 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5175 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5177 /* Enable ECC on Lynxpoint */
5178 if (hw->mac.type >= e1000_pch_lpt) {
5179 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5180 reg |= E1000_PBECCSTS_ECC_ENABLE;
5181 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5183 reg = E1000_READ_REG(hw, E1000_CTRL);
5184 reg |= E1000_CTRL_MEHE;
5185 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5192 * e1000_setup_link_ich8lan - Setup flow control and link settings
5193 * @hw: pointer to the HW structure
5195 * Determines which flow control settings to use, then configures flow
5196 * control. Calls the appropriate media-specific link configuration
5197 * function. Assuming the adapter has a valid link partner, a valid link
5198 * should be established. Assumes the hardware has previously been reset
5199 * and the transmitter and receiver are not enabled.
5201 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5205 DEBUGFUNC("e1000_setup_link_ich8lan");
5207 if (hw->phy.ops.check_reset_block(hw))
5208 return E1000_SUCCESS;
5210 /* ICH parts do not have a word in the NVM to determine
5211 * the default flow control setting, so we explicitly
5214 if (hw->fc.requested_mode == e1000_fc_default)
5215 hw->fc.requested_mode = e1000_fc_full;
5217 /* Save off the requested flow control mode for use later. Depending
5218 * on the link partner's capabilities, we may or may not use this mode.
5220 hw->fc.current_mode = hw->fc.requested_mode;
5222 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5223 hw->fc.current_mode);
5225 /* Continue to configure the copper link. */
5226 ret_val = hw->mac.ops.setup_physical_interface(hw);
5230 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5231 if ((hw->phy.type == e1000_phy_82578) ||
5232 (hw->phy.type == e1000_phy_82579) ||
5233 (hw->phy.type == e1000_phy_i217) ||
5234 (hw->phy.type == e1000_phy_82577)) {
5235 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5237 ret_val = hw->phy.ops.write_reg(hw,
5238 PHY_REG(BM_PORT_CTRL_PAGE, 27),
5244 return e1000_set_fc_watermarks_generic(hw);
5248 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5249 * @hw: pointer to the HW structure
5251 * Configures the kumeran interface to the PHY to wait the appropriate time
5252 * when polling the PHY, then call the generic setup_copper_link to finish
5253 * configuring the copper link.
5255 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5261 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5263 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5264 ctrl |= E1000_CTRL_SLU;
5265 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5266 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5268 /* Set the mac to wait the maximum time between each iteration
5269 * and increase the max iterations when polling the phy;
5270 * this fixes erroneous timeouts at 10Mbps.
5272 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5276 ret_val = e1000_read_kmrn_reg_generic(hw,
5277 E1000_KMRNCTRLSTA_INBAND_PARAM,
5282 ret_val = e1000_write_kmrn_reg_generic(hw,
5283 E1000_KMRNCTRLSTA_INBAND_PARAM,
5288 switch (hw->phy.type) {
5289 case e1000_phy_igp_3:
5290 ret_val = e1000_copper_link_setup_igp(hw);
5295 case e1000_phy_82578:
5296 ret_val = e1000_copper_link_setup_m88(hw);
5300 case e1000_phy_82577:
5301 case e1000_phy_82579:
5302 ret_val = e1000_copper_link_setup_82577(hw);
5307 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5312 reg_data &= ~IFE_PMC_AUTO_MDIX;
5314 switch (hw->phy.mdix) {
5316 reg_data &= ~IFE_PMC_FORCE_MDIX;
5319 reg_data |= IFE_PMC_FORCE_MDIX;
5323 reg_data |= IFE_PMC_AUTO_MDIX;
5326 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5335 return e1000_setup_copper_link_generic(hw);
5339 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5340 * @hw: pointer to the HW structure
5342 * Calls the PHY specific link setup function and then calls the
5343 * generic setup_copper_link to finish configuring the link for
5344 * Lynxpoint PCH devices
5346 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5351 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5353 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5354 ctrl |= E1000_CTRL_SLU;
5355 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5356 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5358 ret_val = e1000_copper_link_setup_82577(hw);
5362 return e1000_setup_copper_link_generic(hw);
5366 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5367 * @hw: pointer to the HW structure
5368 * @speed: pointer to store current link speed
5369 * @duplex: pointer to store the current link duplex
5371 * Calls the generic get_speed_and_duplex to retrieve the current link
5372 * information and then calls the Kumeran lock loss workaround for links at
5375 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5380 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5382 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5386 if ((hw->mac.type == e1000_ich8lan) &&
5387 (hw->phy.type == e1000_phy_igp_3) &&
5388 (*speed == SPEED_1000)) {
5389 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5396 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5397 * @hw: pointer to the HW structure
5399 * Work-around for 82566 Kumeran PCS lock loss:
5400 * On link status change (i.e. PCI reset, speed change) and link is up and
5402 * 0) if workaround is optionally disabled do nothing
5403 * 1) wait 1ms for Kumeran link to come up
5404 * 2) check Kumeran Diagnostic register PCS lock loss bit
5405 * 3) if not set the link is locked (all is good), otherwise...
5407 * 5) repeat up to 10 times
5408 * Note: this is only called for IGP3 copper when speed is 1gb.
5410 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5412 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5418 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5420 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5421 return E1000_SUCCESS;
5423 /* Make sure link is up before proceeding. If not just return.
5424 * Attempting this while link is negotiating fouled up link
5427 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5429 return E1000_SUCCESS;
5431 for (i = 0; i < 10; i++) {
5432 /* read once to clear */
5433 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5436 /* and again to get new status */
5437 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5441 /* check for PCS lock */
5442 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5443 return E1000_SUCCESS;
5445 /* Issue PHY reset */
5446 hw->phy.ops.reset(hw);
5449 /* Disable GigE link negotiation */
5450 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5451 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5452 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5453 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5455 /* Call gig speed drop workaround on Gig disable before accessing
5458 e1000_gig_downshift_workaround_ich8lan(hw);
5460 /* unable to acquire PCS lock */
5461 return -E1000_ERR_PHY;
5465 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5466 * @hw: pointer to the HW structure
5467 * @state: boolean value used to set the current Kumeran workaround state
5469 * If ICH8, set the current Kumeran workaround state (enabled - true
5470 * /disabled - false).
5472 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5475 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5477 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5479 if (hw->mac.type != e1000_ich8lan) {
5480 DEBUGOUT("Workaround applies to ICH8 only.\n");
5484 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5490 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5491 * @hw: pointer to the HW structure
5493 * Workaround for 82566 power-down on D3 entry:
5494 * 1) disable gigabit link
5495 * 2) write VR power-down enable
5497 * Continue if successful, else issue LCD reset and repeat
5499 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5505 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5507 if (hw->phy.type != e1000_phy_igp_3)
5510 /* Try the workaround twice (if needed) */
5513 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5514 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5515 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5516 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5518 /* Call gig speed drop workaround on Gig disable before
5519 * accessing any PHY registers
5521 if (hw->mac.type == e1000_ich8lan)
5522 e1000_gig_downshift_workaround_ich8lan(hw);
5524 /* Write VR power-down enable */
5525 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5526 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5527 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5528 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5530 /* Read it back and test */
5531 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5532 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5533 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5536 /* Issue PHY reset and repeat at most one more time */
5537 reg = E1000_READ_REG(hw, E1000_CTRL);
5538 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5544 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5545 * @hw: pointer to the HW structure
5547 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5548 * LPLU, Gig disable, MDIC PHY reset):
5549 * 1) Set Kumeran Near-end loopback
5550 * 2) Clear Kumeran Near-end loopback
5551 * Should only be called for ICH8[m] devices with any 1G Phy.
5553 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5558 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5560 if ((hw->mac.type != e1000_ich8lan) ||
5561 (hw->phy.type == e1000_phy_ife))
5564 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5568 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5569 ret_val = e1000_write_kmrn_reg_generic(hw,
5570 E1000_KMRNCTRLSTA_DIAG_OFFSET,
5574 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5575 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5580 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5581 * @hw: pointer to the HW structure
5583 * During S0 to Sx transition, it is possible the link remains at gig
5584 * instead of negotiating to a lower speed. Before going to Sx, set
5585 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5586 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5587 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5588 * needs to be written.
5589 * Parts that support (and are linked to a partner which support) EEE in
5590 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5591 * than 10Mbps w/o EEE.
5593 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5595 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5599 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5601 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5602 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5604 if (hw->phy.type == e1000_phy_i217) {
5605 u16 phy_reg, device_id = hw->device_id;
5607 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5608 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5609 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5610 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5611 (hw->mac.type >= e1000_pch_spt)) {
5612 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5614 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5615 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5618 ret_val = hw->phy.ops.acquire(hw);
5622 if (!dev_spec->eee_disable) {
5626 e1000_read_emi_reg_locked(hw,
5627 I217_EEE_ADVERTISEMENT,
5632 /* Disable LPLU if both link partners support 100BaseT
5633 * EEE and 100Full is advertised on both ends of the
5634 * link, and enable Auto Enable LPI since there will
5635 * be no driver to enable LPI while in Sx.
5637 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5638 (dev_spec->eee_lp_ability &
5639 I82579_EEE_100_SUPPORTED) &&
5640 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5641 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5642 E1000_PHY_CTRL_NOND0A_LPLU);
5644 /* Set Auto Enable LPI after link up */
5645 hw->phy.ops.read_reg_locked(hw,
5648 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5649 hw->phy.ops.write_reg_locked(hw,
5655 /* For i217 Intel Rapid Start Technology support,
5656 * when the system is going into Sx and no manageability engine
5657 * is present, the driver must configure proxy to reset only on
5658 * power good. LPI (Low Power Idle) state must also reset only
5659 * on power good, as well as the MTA (Multicast table array).
5660 * The SMBus release must also be disabled on LCD reset.
5662 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5663 E1000_ICH_FWSM_FW_VALID)) {
5664 /* Enable proxy to reset only on power good. */
5665 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5667 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5668 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5671 /* Set bit enable LPI (EEE) to reset only on
5674 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5675 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5676 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5678 /* Disable the SMB release on LCD reset. */
5679 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5680 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5681 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5684 /* Enable MTA to reset for Intel Rapid Start Technology
5687 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5688 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5689 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5692 hw->phy.ops.release(hw);
5695 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5697 if (hw->mac.type == e1000_ich8lan)
5698 e1000_gig_downshift_workaround_ich8lan(hw);
5700 if (hw->mac.type >= e1000_pchlan) {
5701 e1000_oem_bits_config_ich8lan(hw, false);
5703 /* Reset PHY to activate OEM bits on 82577/8 */
5704 if (hw->mac.type == e1000_pchlan)
5705 e1000_phy_hw_reset_generic(hw);
5707 ret_val = hw->phy.ops.acquire(hw);
5710 e1000_write_smbus_addr(hw);
5711 hw->phy.ops.release(hw);
5718 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5719 * @hw: pointer to the HW structure
5721 * During Sx to S0 transitions on non-managed devices or managed devices
5722 * on which PHY resets are not blocked, if the PHY registers cannot be
5723 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5725 * On i217, setup Intel Rapid Start Technology.
5727 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5731 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5732 if (hw->mac.type < e1000_pch2lan)
5733 return E1000_SUCCESS;
5735 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5737 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5741 /* For i217 Intel Rapid Start Technology support when the system
5742 * is transitioning from Sx and no manageability engine is present
5743 * configure SMBus to restore on reset, disable proxy, and enable
5744 * the reset on MTA (Multicast table array).
5746 if (hw->phy.type == e1000_phy_i217) {
5749 ret_val = hw->phy.ops.acquire(hw);
5751 DEBUGOUT("Failed to setup iRST\n");
5755 /* Clear Auto Enable LPI after link up */
5756 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5757 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5758 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5760 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5761 E1000_ICH_FWSM_FW_VALID)) {
5762 /* Restore clear on SMB if no manageability engine
5765 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5769 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5770 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5773 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5775 /* Enable reset on MTA */
5776 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5780 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5781 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5784 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5785 hw->phy.ops.release(hw);
5788 return E1000_SUCCESS;
5792 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5793 * @hw: pointer to the HW structure
5795 * Return the LED back to the default configuration.
5797 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5799 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5801 if (hw->phy.type == e1000_phy_ife)
5802 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5805 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5806 return E1000_SUCCESS;
5810 * e1000_led_on_ich8lan - Turn LEDs on
5811 * @hw: pointer to the HW structure
5815 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5817 DEBUGFUNC("e1000_led_on_ich8lan");
5819 if (hw->phy.type == e1000_phy_ife)
5820 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5821 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5823 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5824 return E1000_SUCCESS;
5828 * e1000_led_off_ich8lan - Turn LEDs off
5829 * @hw: pointer to the HW structure
5831 * Turn off the LEDs.
5833 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5835 DEBUGFUNC("e1000_led_off_ich8lan");
5837 if (hw->phy.type == e1000_phy_ife)
5838 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5839 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5841 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5842 return E1000_SUCCESS;
5846 * e1000_setup_led_pchlan - Configures SW controllable LED
5847 * @hw: pointer to the HW structure
5849 * This prepares the SW controllable LED for use.
5851 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5853 DEBUGFUNC("e1000_setup_led_pchlan");
5855 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5856 (u16)hw->mac.ledctl_mode1);
5860 * e1000_cleanup_led_pchlan - Restore the default LED operation
5861 * @hw: pointer to the HW structure
5863 * Return the LED back to the default configuration.
5865 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5867 DEBUGFUNC("e1000_cleanup_led_pchlan");
5869 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5870 (u16)hw->mac.ledctl_default);
5874 * e1000_led_on_pchlan - Turn LEDs on
5875 * @hw: pointer to the HW structure
5879 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5881 u16 data = (u16)hw->mac.ledctl_mode2;
5884 DEBUGFUNC("e1000_led_on_pchlan");
5886 /* If no link, then turn LED on by setting the invert bit
5887 * for each LED that's mode is "link_up" in ledctl_mode2.
5889 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5890 for (i = 0; i < 3; i++) {
5891 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5892 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5893 E1000_LEDCTL_MODE_LINK_UP)
5895 if (led & E1000_PHY_LED0_IVRT)
5896 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5898 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5902 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5906 * e1000_led_off_pchlan - Turn LEDs off
5907 * @hw: pointer to the HW structure
5909 * Turn off the LEDs.
5911 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5913 u16 data = (u16)hw->mac.ledctl_mode1;
5916 DEBUGFUNC("e1000_led_off_pchlan");
5918 /* If no link, then turn LED off by clearing the invert bit
5919 * for each LED that's mode is "link_up" in ledctl_mode1.
5921 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5922 for (i = 0; i < 3; i++) {
5923 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5924 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5925 E1000_LEDCTL_MODE_LINK_UP)
5927 if (led & E1000_PHY_LED0_IVRT)
5928 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5930 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5934 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5938 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5939 * @hw: pointer to the HW structure
5941 * Read appropriate register for the config done bit for completion status
5942 * and configure the PHY through s/w for EEPROM-less parts.
5944 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5945 * config done bit, so only an error is logged and continues. If we were
5946 * to return with error, EEPROM-less silicon would not be able to be reset
5949 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5951 s32 ret_val = E1000_SUCCESS;
5955 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5957 e1000_get_cfg_done_generic(hw);
5959 /* Wait for indication from h/w that it has completed basic config */
5960 if (hw->mac.type >= e1000_ich10lan) {
5961 e1000_lan_init_done_ich8lan(hw);
5963 ret_val = e1000_get_auto_rd_done_generic(hw);
5965 /* When auto config read does not complete, do not
5966 * return with an error. This can happen in situations
5967 * where there is no eeprom and prevents getting link.
5969 DEBUGOUT("Auto Read Done did not complete\n");
5970 ret_val = E1000_SUCCESS;
5974 /* Clear PHY Reset Asserted bit */
5975 status = E1000_READ_REG(hw, E1000_STATUS);
5976 if (status & E1000_STATUS_PHYRA)
5977 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5979 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5981 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5982 if (hw->mac.type <= e1000_ich9lan) {
5983 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5984 (hw->phy.type == e1000_phy_igp_3)) {
5985 e1000_phy_init_script_igp3(hw);
5988 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5989 /* Maybe we should do a basic PHY config */
5990 DEBUGOUT("EEPROM not present\n");
5991 ret_val = -E1000_ERR_CONFIG;
5999 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
6000 * @hw: pointer to the HW structure
6002 * In the case of a PHY power down to save power, or to turn off link during a
6003 * driver unload, or wake on lan is not enabled, remove the link.
6005 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6007 /* If the management interface is not enabled, then power down */
6008 if (!(hw->mac.ops.check_mng_mode(hw) ||
6009 hw->phy.ops.check_reset_block(hw)))
6010 e1000_power_down_phy_copper(hw);
6016 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6017 * @hw: pointer to the HW structure
6019 * Clears hardware counters specific to the silicon family and calls
6020 * clear_hw_cntrs_generic to clear all general purpose counters.
6022 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6027 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6029 e1000_clear_hw_cntrs_base_generic(hw);
6031 E1000_READ_REG(hw, E1000_ALGNERRC);
6032 E1000_READ_REG(hw, E1000_RXERRC);
6033 E1000_READ_REG(hw, E1000_TNCRS);
6034 E1000_READ_REG(hw, E1000_CEXTERR);
6035 E1000_READ_REG(hw, E1000_TSCTC);
6036 E1000_READ_REG(hw, E1000_TSCTFC);
6038 E1000_READ_REG(hw, E1000_MGTPRC);
6039 E1000_READ_REG(hw, E1000_MGTPDC);
6040 E1000_READ_REG(hw, E1000_MGTPTC);
6042 E1000_READ_REG(hw, E1000_IAC);
6043 E1000_READ_REG(hw, E1000_ICRXOC);
6045 /* Clear PHY statistics registers */
6046 if ((hw->phy.type == e1000_phy_82578) ||
6047 (hw->phy.type == e1000_phy_82579) ||
6048 (hw->phy.type == e1000_phy_i217) ||
6049 (hw->phy.type == e1000_phy_82577)) {
6050 ret_val = hw->phy.ops.acquire(hw);
6053 ret_val = hw->phy.ops.set_page(hw,
6054 HV_STATS_PAGE << IGP_PAGE_SHIFT);
6057 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6058 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6059 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6060 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6061 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6062 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6063 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6064 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6065 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6066 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6067 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6068 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6069 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6070 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6072 hw->phy.ops.release(hw);
6077 * e1000_configure_k0s_lpt - Configure K0s power state
6078 * @hw: pointer to the HW structure
6079 * @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6080 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6081 * @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
6082 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6084 * Configure the K1 power state based on the provided parameter.
6085 * Assumes semaphore already acquired.
6087 * Success returns 0, Failure returns:
6088 * -E1000_ERR_PHY (-2) in case of access error
6089 * -E1000_ERR_PARAM (-4) in case of parameters error
6091 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6096 DEBUGFUNC("e1000_configure_k0s_lpt");
6098 if (entry_latency > 3 || min_time > 4)
6099 return -E1000_ERR_PARAM;
6101 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6106 /* for now don't touch the latency */
6107 kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6108 kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6110 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6115 return E1000_SUCCESS;