drivers/net/e1000/base/e1000_ich8lan.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 82562G 10/100 Network Connection
  35  * 82562G-2 10/100 Network Connection
  36  * 82562GT 10/100 Network Connection
  37  * 82562GT-2 10/100 Network Connection
  38  * 82562V 10/100 Network Connection
  39  * 82562V-2 10/100 Network Connection
  40  * 82566DC-2 Gigabit Network Connection
  41  * 82566DC Gigabit Network Connection
  42  * 82566DM-2 Gigabit Network Connection
  43  * 82566DM Gigabit Network Connection
  44  * 82566MC Gigabit Network Connection
  45  * 82566MM Gigabit Network Connection
  46  * 82567LM Gigabit Network Connection
  47  * 82567LF Gigabit Network Connection
  48  * 82567V Gigabit Network Connection
  49  * 82567LM-2 Gigabit Network Connection
  50  * 82567LF-2 Gigabit Network Connection
  51  * 82567V-2 Gigabit Network Connection
  52  * 82567LF-3 Gigabit Network Connection
  53  * 82567LM-3 Gigabit Network Connection
  54  * 82567LM-4 Gigabit Network Connection
  55  * 82577LM Gigabit Network Connection
  56  * 82577LC Gigabit Network Connection
  57  * 82578DM Gigabit Network Connection
  58  * 82578DC Gigabit Network Connection
  59  * 82579LM Gigabit Network Connection
  60  * 82579V Gigabit Network Connection
  61  * Ethernet Connection I217-LM
  62  * Ethernet Connection I217-V
  63  * Ethernet Connection I218-V
  64  * Ethernet Connection I218-LM
  65  * Ethernet Connection (2) I218-LM
  66  * Ethernet Connection (2) I218-V
  67  * Ethernet Connection (3) I218-LM
  68  * Ethernet Connection (3) I218-V
  69  */
  70
  71 #include "e1000_api.h"
  72
  73 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
  74 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  75 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  76 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  77 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  78 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  79 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  80 STATIC int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  81 STATIC int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  82 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  83 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
  84 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  85                                               u8 *mc_addr_list,
  86                                               u32 mc_addr_count);
  87 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
  88 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  89 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  90 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  91 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  92                                             bool active);
  93 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  94                                             bool active);
  95 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  96                                    u16 words, u16 *data);
  97 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  98                                     u16 words, u16 *data);
  99 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
 100 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
 101 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
 102                                             u16 *data);
 103 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 104 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 105 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
 106 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
 107 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 108 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 109 STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 110 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
 111                                            u16 *speed, u16 *duplex);
 112 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 113 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 114 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
 115 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 116 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 117 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 118 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 119 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 120 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 121 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 122 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 123 STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 124 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 125                                           u32 offset, u8 *data);
 126 STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 127                                           u8 size, u16 *data);
 128 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 129                                           u32 offset, u16 *data);
 130 STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 131                                                  u32 offset, u8 byte);
 132 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 133 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 134 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 135 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 136 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 137 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 138
 139 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 140 /* Offset 04h HSFSTS */
 141 union ich8_hws_flash_status {
 142         struct ich8_hsfsts {
 143                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 144                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 145                 u16 dael:1; /* bit 2 Direct Access error Log */
 146                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 147                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 148                 u16 reserved1:2; /* bit 13:6 Reserved */
 149                 u16 reserved2:6; /* bit 13:6 Reserved */
 150                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 151                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 152         } hsf_status;
 153         u16 regval;
 154 };
 155
 156 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 157 /* Offset 06h FLCTL */
 158 union ich8_hws_flash_ctrl {
 159         struct ich8_hsflctl {
 160                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 161                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 162                 u16 reserved:5;   /* 7:3 Reserved  */
 163                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 164                 u16 flockdn:6;   /* 15:10 Reserved */
 165         } hsf_ctrl;
 166         u16 regval;
 167 };
 168
 169 /* ICH Flash Region Access Permissions */
 170 union ich8_hws_flash_regacc {
 171         struct ich8_flracc {
 172                 u32 grra:8; /* 0:7 GbE region Read Access */
 173                 u32 grwa:8; /* 8:15 GbE region Write Access */
 174                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 175                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 176         } hsf_flregacc;
 177         u16 regval;
 178 };
 179
 180 /**
 181  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 182  *  @hw: pointer to the HW structure
 183  *
 184  *  Test access to the PHY registers by reading the PHY ID registers.  If
 185  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 186  *  otherwise assume the read PHY ID is correct if it is valid.
 187  *
 188  *  Assumes the sw/fw/hw semaphore is already acquired.
 189  **/
 190 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 191 {
 192         u16 phy_reg = 0;
 193         u32 phy_id = 0;
 194         s32 ret_val = 0;
 195         u16 retry_count;
 196         u32 mac_reg = 0;
 197
 198         for (retry_count = 0; retry_count < 2; retry_count++) {
 199                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 200                 if (ret_val || (phy_reg == 0xFFFF))
 201                         continue;
 202                 phy_id = (u32)(phy_reg << 16);
 203
 204                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 205                 if (ret_val || (phy_reg == 0xFFFF)) {
 206                         phy_id = 0;
 207                         continue;
 208                 }
 209                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 210                 break;
 211         }
 212
 213         if (hw->phy.id) {
 214                 if  (hw->phy.id == phy_id)
 215                         goto out;
 216         } else if (phy_id) {
 217                 hw->phy.id = phy_id;
 218                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 219                 goto out;
 220         }
 221
 222         /* In case the PHY needs to be in mdio slow mode,
 223          * set slow mode and try to get the PHY id again.
 224          */
 225         if (hw->mac.type < e1000_pch_lpt) {
 226                 hw->phy.ops.release(hw);
 227                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 228                 if (!ret_val)
 229                         ret_val = e1000_get_phy_id(hw);
 230                 hw->phy.ops.acquire(hw);
 231         }
 232
 233         if (ret_val)
 234                 return false;
 235 out:
 236         if (hw->mac.type == e1000_pch_lpt) {
 237                 /* Only unforce SMBus if ME is not active */
 238                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
 239                     E1000_ICH_FWSM_FW_VALID)) {
 240                         /* Unforce SMBus mode in PHY */
 241                         hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 242                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 243                         hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 244
 245                         /* Unforce SMBus mode in MAC */
 246                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 247                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 248                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 249                 }
 250         }
 251
 252         return true;
 253 }
 254
 255 /**
 256  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 257  *  @hw: pointer to the HW structure
 258  *
 259  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 260  *  used to reset the PHY to a quiescent state when necessary.
 261  **/
 262 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 263 {
 264         u32 mac_reg;
 265
 266         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 267
 268         /* Set Phy Config Counter to 50msec */
 269         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 270         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 271         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 272         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 273
 274         /* Toggle LANPHYPC Value bit */
 275         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 276         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 277         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 278         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 279         E1000_WRITE_FLUSH(hw);
 280         usec_delay(10);
 281         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 282         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 283         E1000_WRITE_FLUSH(hw);
 284
 285         if (hw->mac.type < e1000_pch_lpt) {
 286                 msec_delay(50);
 287         } else {
 288                 u16 count = 20;
 289
 290                 do {
 291                         msec_delay(5);
 292                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 293                            E1000_CTRL_EXT_LPCD) && count--);
 294
 295                 msec_delay(30);
 296         }
 297 }
 298
 299 /**
 300  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 301  *  @hw: pointer to the HW structure
 302  *
 303  *  Workarounds/flow necessary for PHY initialization during driver load
 304  *  and resume paths.
 305  **/
 306 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 307 {
 308         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 309         s32 ret_val;
 310
 311         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 312
 313         /* Gate automatic PHY configuration by hardware on managed and
 314          * non-managed 82579 and newer adapters.
 315          */
 316         e1000_gate_hw_phy_config_ich8lan(hw, true);
 317
 318 #ifdef ULP_SUPPORT
 319         /* It is not possible to be certain of the current state of ULP
 320          * so forcibly disable it.
 321          */
 322         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 323
 324 #endif /* ULP_SUPPORT */
 325         ret_val = hw->phy.ops.acquire(hw);
 326         if (ret_val) {
 327                 DEBUGOUT("Failed to initialize PHY flow\n");
 328                 goto out;
 329         }
 330
 331         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 332          * inaccessible and resetting the PHY is not blocked, toggle the
 333          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 334          */
 335         switch (hw->mac.type) {
 336         case e1000_pch_lpt:
 337                 if (e1000_phy_is_accessible_pchlan(hw))
 338                         break;
 339
 340                 /* Before toggling LANPHYPC, see if PHY is accessible by
 341                  * forcing MAC to SMBus mode first.
 342                  */
 343                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 344                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 345                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 346
 347                 /* Wait 50 milliseconds for MAC to finish any retries
 348                  * that it might be trying to perform from previous
 349                  * attempts to acknowledge any phy read requests.
 350                  */
 351                  msec_delay(50);
 352
 353                 /* fall-through */
 354         case e1000_pch2lan:
 355                 if (e1000_phy_is_accessible_pchlan(hw))
 356                         break;
 357
 358                 /* fall-through */
 359         case e1000_pchlan:
 360                 if ((hw->mac.type == e1000_pchlan) &&
 361                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 362                         break;
 363
 364                 if (hw->phy.ops.check_reset_block(hw)) {
 365                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 366                         ret_val = -E1000_ERR_PHY;
 367                         break;
 368                 }
 369
 370                 /* Toggle LANPHYPC Value bit */
 371                 e1000_toggle_lanphypc_pch_lpt(hw);
 372                 if (hw->mac.type >= e1000_pch_lpt) {
 373                         if (e1000_phy_is_accessible_pchlan(hw))
 374                                 break;
 375
 376                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 377                          * so ensure that the MAC is also out of SMBus mode
 378                          */
 379                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 380                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 381                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 382
 383                         if (e1000_phy_is_accessible_pchlan(hw))
 384                                 break;
 385
 386                         ret_val = -E1000_ERR_PHY;
 387                 }
 388                 break;
 389         default:
 390                 break;
 391         }
 392
 393         hw->phy.ops.release(hw);
 394         if (!ret_val) {
 395
 396                 /* Check to see if able to reset PHY.  Print error if not */
 397                 if (hw->phy.ops.check_reset_block(hw)) {
 398                         ERROR_REPORT("Reset blocked by ME\n");
 399                         goto out;
 400                 }
 401
 402                 /* Reset the PHY before any access to it.  Doing so, ensures
 403                  * that the PHY is in a known good state before we read/write
 404                  * PHY registers.  The generic reset is sufficient here,
 405                  * because we haven't determined the PHY type yet.
 406                  */
 407                 ret_val = e1000_phy_hw_reset_generic(hw);
 408                 if (ret_val)
 409                         goto out;
 410
 411                 /* On a successful reset, possibly need to wait for the PHY
 412                  * to quiesce to an accessible state before returning control
 413                  * to the calling function.  If the PHY does not quiesce, then
 414                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 415                  *  the PHY is in.
 416                  */
 417                 ret_val = hw->phy.ops.check_reset_block(hw);
 418                 if (ret_val)
 419                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 420         }
 421
 422 out:
 423         /* Ungate automatic PHY configuration on non-managed 82579 */
 424         if ((hw->mac.type == e1000_pch2lan) &&
 425             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 426                 msec_delay(10);
 427                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 428         }
 429
 430         return ret_val;
 431 }
 432
 433 /**
 434  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 435  *  @hw: pointer to the HW structure
 436  *
 437  *  Initialize family-specific PHY parameters and function pointers.
 438  **/
 439 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 440 {
 441         struct e1000_phy_info *phy = &hw->phy;
 442         s32 ret_val;
 443
 444         DEBUGFUNC("e1000_init_phy_params_pchlan");
 445
 446         phy->addr               = 1;
 447         phy->reset_delay_us     = 100;
 448
 449         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 450         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 451         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 452         phy->ops.set_page       = e1000_set_page_igp;
 453         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 454         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 455         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 456         phy->ops.release        = e1000_release_swflag_ich8lan;
 457         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 458         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 459         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 460         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 461         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 462         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 463         phy->ops.power_up       = e1000_power_up_phy_copper;
 464         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 465         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 466
 467         phy->id = e1000_phy_unknown;
 468
 469         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 470         if (ret_val)
 471                 return ret_val;
 472
 473         if (phy->id == e1000_phy_unknown)
 474                 switch (hw->mac.type) {
 475                 default:
 476                         ret_val = e1000_get_phy_id(hw);
 477                         if (ret_val)
 478                                 return ret_val;
 479                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 480                                 break;
 481                         /* fall-through */
 482                 case e1000_pch2lan:
 483                 case e1000_pch_lpt:
 484                         /* In case the PHY needs to be in mdio slow mode,
 485                          * set slow mode and try to get the PHY id again.
 486                          */
 487                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 488                         if (ret_val)
 489                                 return ret_val;
 490                         ret_val = e1000_get_phy_id(hw);
 491                         if (ret_val)
 492                                 return ret_val;
 493                         break;
 494                 }
 495         phy->type = e1000_get_phy_type_from_id(phy->id);
 496
 497         switch (phy->type) {
 498         case e1000_phy_82577:
 499         case e1000_phy_82579:
 500         case e1000_phy_i217:
 501                 phy->ops.check_polarity = e1000_check_polarity_82577;
 502                 phy->ops.force_speed_duplex =
 503                         e1000_phy_force_speed_duplex_82577;
 504                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 505                 phy->ops.get_info = e1000_get_phy_info_82577;
 506                 phy->ops.commit = e1000_phy_sw_reset_generic;
 507                 break;
 508         case e1000_phy_82578:
 509                 phy->ops.check_polarity = e1000_check_polarity_m88;
 510                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 511                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 512                 phy->ops.get_info = e1000_get_phy_info_m88;
 513                 break;
 514         default:
 515                 ret_val = -E1000_ERR_PHY;
 516                 break;
 517         }
 518
 519         return ret_val;
 520 }
 521
 522 /**
 523  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 524  *  @hw: pointer to the HW structure
 525  *
 526  *  Initialize family-specific PHY parameters and function pointers.
 527  **/
 528 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 529 {
 530         struct e1000_phy_info *phy = &hw->phy;
 531         s32 ret_val;
 532         u16 i = 0;
 533
 534         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 535
 536         phy->addr               = 1;
 537         phy->reset_delay_us     = 100;
 538
 539         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 540         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 541         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 542         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 543         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 544         phy->ops.release        = e1000_release_swflag_ich8lan;
 545         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 546         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 547         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 548         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 549         phy->ops.power_up       = e1000_power_up_phy_copper;
 550         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 551
 552         /* We may need to do this twice - once for IGP and if that fails,
 553          * we'll set BM func pointers and try again
 554          */
 555         ret_val = e1000_determine_phy_address(hw);
 556         if (ret_val) {
 557                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 558                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 559                 ret_val = e1000_determine_phy_address(hw);
 560                 if (ret_val) {
 561                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 562                         return ret_val;
 563                 }
 564         }
 565
 566         phy->id = 0;
 567         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 568                (i++ < 100)) {
 569                 msec_delay(1);
 570                 ret_val = e1000_get_phy_id(hw);
 571                 if (ret_val)
 572                         return ret_val;
 573         }
 574
 575         /* Verify phy id */
 576         switch (phy->id) {
 577         case IGP03E1000_E_PHY_ID:
 578                 phy->type = e1000_phy_igp_3;
 579                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 580                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 581                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 582                 phy->ops.get_info = e1000_get_phy_info_igp;
 583                 phy->ops.check_polarity = e1000_check_polarity_igp;
 584                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 585                 break;
 586         case IFE_E_PHY_ID:
 587         case IFE_PLUS_E_PHY_ID:
 588         case IFE_C_E_PHY_ID:
 589                 phy->type = e1000_phy_ife;
 590                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 591                 phy->ops.get_info = e1000_get_phy_info_ife;
 592                 phy->ops.check_polarity = e1000_check_polarity_ife;
 593                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 594                 break;
 595         case BME1000_E_PHY_ID:
 596                 phy->type = e1000_phy_bm;
 597                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 598                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 599                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 600                 phy->ops.commit = e1000_phy_sw_reset_generic;
 601                 phy->ops.get_info = e1000_get_phy_info_m88;
 602                 phy->ops.check_polarity = e1000_check_polarity_m88;
 603                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 604                 break;
 605         default:
 606                 return -E1000_ERR_PHY;
 607                 break;
 608         }
 609
 610         return E1000_SUCCESS;
 611 }
 612
 613 /**
 614  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 615  *  @hw: pointer to the HW structure
 616  *
 617  *  Initialize family-specific NVM parameters and function
 618  *  pointers.
 619  **/
 620 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 621 {
 622         struct e1000_nvm_info *nvm = &hw->nvm;
 623         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 624         u32 gfpreg, sector_base_addr, sector_end_addr;
 625         u16 i;
 626
 627         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 628
 629         /* Can't read flash registers if the register set isn't mapped. */
 630         nvm->type = e1000_nvm_flash_sw;
 631         if (!hw->flash_address) {
 632                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 633                 return -E1000_ERR_CONFIG;
 634         }
 635
 636         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 637
 638         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 639          * Add 1 to sector_end_addr since this sector is included in
 640          * the overall size.
 641          */
 642         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 643         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 644
 645         /* flash_base_addr is byte-aligned */
 646         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 647
 648         /* find total size of the NVM, then cut in half since the total
 649          * size represents two separate NVM banks.
 650          */
 651         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 652                                 << FLASH_SECTOR_ADDR_SHIFT);
 653         nvm->flash_bank_size /= 2;
 654         /* Adjust to word count */
 655         nvm->flash_bank_size /= sizeof(u16);
 656
 657         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 658
 659         /* Clear shadow ram */
 660         for (i = 0; i < nvm->word_size; i++) {
 661                 dev_spec->shadow_ram[i].modified = false;
 662                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 663         }
 664
 665         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 666         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 667
 668         /* Function Pointers */
 669         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 670         nvm->ops.release        = e1000_release_nvm_ich8lan;
 671         nvm->ops.read           = e1000_read_nvm_ich8lan;
 672         nvm->ops.update         = e1000_update_nvm_checksum_ich8lan;
 673         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 674         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 675         nvm->ops.write          = e1000_write_nvm_ich8lan;
 676
 677         return E1000_SUCCESS;
 678 }
 679
 680 /**
 681  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 682  *  @hw: pointer to the HW structure
 683  *
 684  *  Initialize family-specific MAC parameters and function
 685  *  pointers.
 686  **/
 687 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 688 {
 689         struct e1000_mac_info *mac = &hw->mac;
 690 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 691         u16 pci_cfg;
 692 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 693
 694         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 695
 696         /* Set media type function pointer */
 697         hw->phy.media_type = e1000_media_type_copper;
 698
 699         /* Set mta register count */
 700         mac->mta_reg_count = 32;
 701         /* Set rar entry count */
 702         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 703         if (mac->type == e1000_ich8lan)
 704                 mac->rar_entry_count--;
 705         /* Set if part includes ASF firmware */
 706         mac->asf_firmware_present = true;
 707         /* FWSM register */
 708         mac->has_fwsm = true;
 709         /* ARC subsystem not supported */
 710         mac->arc_subsystem_valid = false;
 711         /* Adaptive IFS supported */
 712         mac->adaptive_ifs = true;
 713
 714         /* Function pointers */
 715
 716         /* bus type/speed/width */
 717         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 718         /* function id */
 719         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 720         /* reset */
 721         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 722         /* hw initialization */
 723         mac->ops.init_hw = e1000_init_hw_ich8lan;
 724         /* link setup */
 725         mac->ops.setup_link = e1000_setup_link_ich8lan;
 726         /* physical interface setup */
 727         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 728         /* check for link */
 729         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 730         /* link info */
 731         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 732         /* multicast address update */
 733         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 734         /* clear hardware counters */
 735         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 736
 737         /* LED and other operations */
 738         switch (mac->type) {
 739         case e1000_ich8lan:
 740         case e1000_ich9lan:
 741         case e1000_ich10lan:
 742                 /* check management mode */
 743                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 744                 /* ID LED init */
 745                 mac->ops.id_led_init = e1000_id_led_init_generic;
 746                 /* blink LED */
 747                 mac->ops.blink_led = e1000_blink_led_generic;
 748                 /* setup LED */
 749                 mac->ops.setup_led = e1000_setup_led_generic;
 750                 /* cleanup LED */
 751                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 752                 /* turn on/off LED */
 753                 mac->ops.led_on = e1000_led_on_ich8lan;
 754                 mac->ops.led_off = e1000_led_off_ich8lan;
 755                 break;
 756         case e1000_pch2lan:
 757                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 758                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 759                 /* fall-through */
 760         case e1000_pch_lpt:
 761 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 762                 /* multicast address update for pch2 */
 763                 mac->ops.update_mc_addr_list =
 764                         e1000_update_mc_addr_list_pch2lan;
 765                 /* fall-through */
 766 #endif
 767         case e1000_pchlan:
 768 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 769                 /* save PCH revision_id */
 770                 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
 771                 hw->revision_id = (u8)(pci_cfg &= 0x000F);
 772 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 773                 /* check management mode */
 774                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 775                 /* ID LED init */
 776                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 777                 /* setup LED */
 778                 mac->ops.setup_led = e1000_setup_led_pchlan;
 779                 /* cleanup LED */
 780                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 781                 /* turn on/off LED */
 782                 mac->ops.led_on = e1000_led_on_pchlan;
 783                 mac->ops.led_off = e1000_led_off_pchlan;
 784                 break;
 785         default:
 786                 break;
 787         }
 788
 789         if (mac->type == e1000_pch_lpt) {
 790                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 791                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 792                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 793         }
 794
 795         /* Enable PCS Lock-loss workaround for ICH8 */
 796         if (mac->type == e1000_ich8lan)
 797                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 798
 799         return E1000_SUCCESS;
 800 }
 801
 802 /**
 803  *  __e1000_access_emi_reg_locked - Read/write EMI register
 804  *  @hw: pointer to the HW structure
 805  *  @addr: EMI address to program
 806  *  @data: pointer to value to read/write from/to the EMI address
 807  *  @read: boolean flag to indicate read or write
 808  *
 809  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 810  **/
 811 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 812                                          u16 *data, bool read)
 813 {
 814         s32 ret_val;
 815
 816         DEBUGFUNC("__e1000_access_emi_reg_locked");
 817
 818         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 819         if (ret_val)
 820                 return ret_val;
 821
 822         if (read)
 823                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 824                                                       data);
 825         else
 826                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 827                                                        *data);
 828
 829         return ret_val;
 830 }
 831
 832 /**
 833  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 834  *  @hw: pointer to the HW structure
 835  *  @addr: EMI address to program
 836  *  @data: value to be read from the EMI address
 837  *
 838  *  Assumes the SW/FW/HW Semaphore is already acquired.
 839  **/
 840 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 841 {
 842         DEBUGFUNC("e1000_read_emi_reg_locked");
 843
 844         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 845 }
 846
 847 /**
 848  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 849  *  @hw: pointer to the HW structure
 850  *  @addr: EMI address to program
 851  *  @data: value to be written to the EMI address
 852  *
 853  *  Assumes the SW/FW/HW Semaphore is already acquired.
 854  **/
 855 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 856 {
 857         DEBUGFUNC("e1000_read_emi_reg_locked");
 858
 859         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 860 }
 861
 862 /**
 863  *  e1000_set_eee_pchlan - Enable/disable EEE support
 864  *  @hw: pointer to the HW structure
 865  *
 866  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 867  *  the link and the EEE capabilities of the link partner.  The LPI Control
 868  *  register bits will remain set only if/when link is up.
 869  *
 870  *  EEE LPI must not be asserted earlier than one second after link is up.
 871  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 872  *  can be link issues with some switches.  Other devices can have EEE LPI
 873  *  enabled immediately upon link up since they have a timer in hardware which
 874  *  prevents LPI from being asserted too early.
 875  **/
 876 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 877 {
 878         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 879         s32 ret_val;
 880         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 881
 882         DEBUGFUNC("e1000_set_eee_pchlan");
 883
 884         switch (hw->phy.type) {
 885         case e1000_phy_82579:
 886                 lpa = I82579_EEE_LP_ABILITY;
 887                 pcs_status = I82579_EEE_PCS_STATUS;
 888                 adv_addr = I82579_EEE_ADVERTISEMENT;
 889                 break;
 890         case e1000_phy_i217:
 891                 lpa = I217_EEE_LP_ABILITY;
 892                 pcs_status = I217_EEE_PCS_STATUS;
 893                 adv_addr = I217_EEE_ADVERTISEMENT;
 894                 break;
 895         default:
 896                 return E1000_SUCCESS;
 897         }
 898
 899         ret_val = hw->phy.ops.acquire(hw);
 900         if (ret_val)
 901                 return ret_val;
 902
 903         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 904         if (ret_val)
 905                 goto release;
 906
 907         /* Clear bits that enable EEE in various speeds */
 908         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 909
 910         /* Enable EEE if not disabled by user */
 911         if (!dev_spec->eee_disable) {
 912                 /* Save off link partner's EEE ability */
 913                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 914                                                     &dev_spec->eee_lp_ability);
 915                 if (ret_val)
 916                         goto release;
 917
 918                 /* Read EEE advertisement */
 919                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 920                 if (ret_val)
 921                         goto release;
 922
 923                 /* Enable EEE only for speeds in which the link partner is
 924                  * EEE capable and for which we advertise EEE.
 925                  */
 926                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 927                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 928
 929                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 930                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 931                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 932                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 933                         else
 934                                 /* EEE is not supported in 100Half, so ignore
 935                                  * partner's EEE in 100 ability if full-duplex
 936                                  * is not advertised.
 937                                  */
 938                                 dev_spec->eee_lp_ability &=
 939                                     ~I82579_EEE_100_SUPPORTED;
 940                 }
 941         }
 942
 943         if (hw->phy.type == e1000_phy_82579) {
 944                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 945                                                     &data);
 946                 if (ret_val)
 947                         goto release;
 948
 949                 data &= ~I82579_LPI_100_PLL_SHUT;
 950                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 951                                                      data);
 952         }
 953
 954         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 955         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 956         if (ret_val)
 957                 goto release;
 958
 959         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 960 release:
 961         hw->phy.ops.release(hw);
 962
 963         return ret_val;
 964 }
 965
 966 /**
 967  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 968  *  @hw:   pointer to the HW structure
 969  *  @link: link up bool flag
 970  *
 971  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 972  *  preventing further DMA write requests.  Workaround the issue by disabling
 973  *  the de-assertion of the clock request when in 1Gpbs mode.
 974  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 975  *  speeds in order to avoid Tx hangs.
 976  **/
 977 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 978 {
 979         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
 980         u32 status = E1000_READ_REG(hw, E1000_STATUS);
 981         s32 ret_val = E1000_SUCCESS;
 982         u16 reg;
 983
 984         if (link && (status & E1000_STATUS_SPEED_1000)) {
 985                 ret_val = hw->phy.ops.acquire(hw);
 986                 if (ret_val)
 987                         return ret_val;
 988
 989                 ret_val =
 990                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 991                                                &reg);
 992                 if (ret_val)
 993                         goto release;
 994
 995                 ret_val =
 996                     e1000_write_kmrn_reg_locked(hw,
 997                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 998                                                 reg &
 999                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1000                 if (ret_val)
1001                         goto release;
1002
1003                 usec_delay(10);
1004
1005                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1006                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1007
1008                 ret_val =
1009                     e1000_write_kmrn_reg_locked(hw,
1010                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1011                                                 reg);
1012 release:
1013                 hw->phy.ops.release(hw);
1014         } else {
1015                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1016                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1017
1018                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1019                               (status & E1000_STATUS_FD)))
1020                         goto update_fextnvm6;
1021
1022                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1023                 if (ret_val)
1024                         return ret_val;
1025
1026                 /* Clear link status transmit timeout */
1027                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1028
1029                 if (status & E1000_STATUS_SPEED_100) {
1030                         /* Set inband Tx timeout to 5x10us for 100Half */
1031                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1032
1033                         /* Do not extend the K1 entry latency for 100Half */
1034                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1035                 } else {
1036                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1037                         reg |= 50 <<
1038                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1039
1040                         /* Extend the K1 entry latency for 10 Mbps */
1041                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1042                 }
1043
1044                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1045                 if (ret_val)
1046                         return ret_val;
1047
1048 update_fextnvm6:
1049                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1050         }
1051
1052         return ret_val;
1053 }
1054
1055 #ifdef ULP_SUPPORT
1056 /**
1057  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1058  *  @hw: pointer to the HW structure
1059  *  @to_sx: boolean indicating a system power state transition to Sx
1060  *
1061  *  When link is down, configure ULP mode to significantly reduce the power
1062  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1063  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1064  *  system, configure the ULP mode by software.
1065  */
1066 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1067 {
1068         u32 mac_reg;
1069         s32 ret_val = E1000_SUCCESS;
1070         u16 phy_reg;
1071
1072         if ((hw->mac.type < e1000_pch_lpt) ||
1073             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1074             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1075             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1076             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1077             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1078                 return 0;
1079
1080         if (!to_sx) {
1081                 int i = 0;
1082                 /* Poll up to 5 seconds for Cable Disconnected indication */
1083                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1084                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1085                         /* Bail if link is re-acquired */
1086                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1087                                 return -E1000_ERR_PHY;
1088                         if (i++ == 100)
1089                                 break;
1090
1091                         msec_delay(50);
1092                 }
1093                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1094                           (E1000_READ_REG(hw, E1000_FEXT) &
1095                            E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1096                           i * 50);
1097                 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1098                     E1000_FEXT_PHY_CABLE_DISCONNECTED))
1099                         return 0;
1100         }
1101
1102         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1103                 /* Request ME configure ULP mode in the PHY */
1104                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1105                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1106                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1107
1108                 goto out;
1109         }
1110
1111         ret_val = hw->phy.ops.acquire(hw);
1112         if (ret_val)
1113                 goto out;
1114
1115         /* During S0 Idle keep the phy in PCI-E mode */
1116         if (hw->dev_spec.ich8lan.smbus_disable)
1117                 goto skip_smbus;
1118
1119         /* Force SMBus mode in PHY */
1120         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1121         if (ret_val)
1122                 goto release;
1123         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1124         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1125
1126         /* Force SMBus mode in MAC */
1127         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1128         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1129         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1130
1131 skip_smbus:
1132         if (!to_sx) {
1133                 /* Change the 'Link Status Change' interrupt to trigger
1134                  * on 'Cable Status Change'
1135                  */
1136                 ret_val = e1000_read_kmrn_reg_locked(hw,
1137                                                      E1000_KMRNCTRLSTA_OP_MODES,
1138                                                      &phy_reg);
1139                 if (ret_val)
1140                         goto release;
1141                 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1142                 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1143                                             phy_reg);
1144         }
1145
1146         /* Set Inband ULP Exit, Reset to SMBus mode and
1147          * Disable SMBus Release on PERST# in PHY
1148          */
1149         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1150         if (ret_val)
1151                 goto release;
1152         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1153                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1154         if (to_sx) {
1155                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1156                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1157
1158                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1159         } else {
1160                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1161         }
1162         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1163
1164         /* Set Disable SMBus Release on PERST# in MAC */
1165         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1166         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1167         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1168
1169         /* Commit ULP changes in PHY by starting auto ULP configuration */
1170         phy_reg |= I218_ULP_CONFIG1_START;
1171         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1172
1173         if (!to_sx) {
1174                 /* Disable Tx so that the MAC doesn't send any (buffered)
1175                  * packets to the PHY.
1176                  */
1177                 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1178                 mac_reg &= ~E1000_TCTL_EN;
1179                 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1180         }
1181 release:
1182         hw->phy.ops.release(hw);
1183 out:
1184         if (ret_val)
1185                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1186         else
1187                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1188
1189         return ret_val;
1190 }
1191
1192 /**
1193  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1194  *  @hw: pointer to the HW structure
1195  *  @force: boolean indicating whether or not to force disabling ULP
1196  *
1197  *  Un-configure ULP mode when link is up, the system is transitioned from
1198  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1199  *  system, poll for an indication from ME that ULP has been un-configured.
1200  *  If not on an ME enabled system, un-configure the ULP mode by software.
1201  *
1202  *  During nominal operation, this function is called when link is acquired
1203  *  to disable ULP mode (force=false); otherwise, for example when unloading
1204  *  the driver or during Sx->S0 transitions, this is called with force=true
1205  *  to forcibly disable ULP.
1206
1207  *  When the cable is plugged in while the device is in D0, a Cable Status
1208  *  Change interrupt is generated which causes this function to be called
1209  *  to partially disable ULP mode and restart autonegotiation.  This function
1210  *  is then called again due to the resulting Link Status Change interrupt
1211  *  to finish cleaning up after the ULP flow.
1212  */
1213 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1214 {
1215         s32 ret_val = E1000_SUCCESS;
1216         u32 mac_reg;
1217         u16 phy_reg;
1218         int i = 0;
1219
1220         if ((hw->mac.type < e1000_pch_lpt) ||
1221             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1222             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1223             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1224             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1225             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1226                 return 0;
1227
1228         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1229                 if (force) {
1230                         /* Request ME un-configure ULP mode in the PHY */
1231                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1232                         mac_reg &= ~E1000_H2ME_ULP;
1233                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1234                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1235                 }
1236
1237                 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1238                 while (E1000_READ_REG(hw, E1000_FWSM) &
1239                        E1000_FWSM_ULP_CFG_DONE) {
1240                         if (i++ == 10) {
1241                                 ret_val = -E1000_ERR_PHY;
1242                                 goto out;
1243                         }
1244
1245                         msec_delay(10);
1246                 }
1247                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1248
1249                 if (force) {
1250                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1251                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1252                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1253                 } else {
1254                         /* Clear H2ME.ULP after ME ULP configuration */
1255                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1256                         mac_reg &= ~E1000_H2ME_ULP;
1257                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1258
1259                         /* Restore link speed advertisements and restart
1260                          * Auto-negotiation
1261                          */
1262                         if (hw->mac.autoneg) {
1263                                 ret_val = e1000_phy_setup_autoneg(hw);
1264                                 if (ret_val)
1265                                         goto out;
1266                         } else {
1267                                 ret_val = e1000_setup_copper_link_generic(hw);
1268                                 if (ret_val)
1269                                         goto out;
1270                         }
1271                         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1272                 }
1273
1274                 goto out;
1275         }
1276
1277         ret_val = hw->phy.ops.acquire(hw);
1278         if (ret_val)
1279                 goto out;
1280
1281         /* Revert the change to the 'Link Status Change'
1282          * interrupt to trigger on 'Cable Status Change'
1283          */
1284         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1285                                              &phy_reg);
1286         if (ret_val)
1287                 goto release;
1288         phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1289         e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1290
1291         if (force)
1292                 /* Toggle LANPHYPC Value bit */
1293                 e1000_toggle_lanphypc_pch_lpt(hw);
1294
1295         /* Unforce SMBus mode in PHY */
1296         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1297         if (ret_val) {
1298                 /* The MAC might be in PCIe mode, so temporarily force to
1299                  * SMBus mode in order to access the PHY.
1300                  */
1301                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1302                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1303                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1304
1305                 msec_delay(50);
1306
1307                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1308                                                        &phy_reg);
1309                 if (ret_val)
1310                         goto release;
1311         }
1312         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1313         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1314
1315         /* Unforce SMBus mode in MAC */
1316         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1317         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1318         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1319
1320         /* When ULP mode was previously entered, K1 was disabled by the
1321          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1322          */
1323         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1324         if (ret_val)
1325                 goto release;
1326         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1327         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1328
1329         /* Clear ULP enabled configuration */
1330         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1331         if (ret_val)
1332                 goto release;
1333         /* CSC interrupt received due to ULP Indication */
1334         if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1335                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1336                              I218_ULP_CONFIG1_STICKY_ULP |
1337                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1338                              I218_ULP_CONFIG1_WOL_HOST |
1339                              I218_ULP_CONFIG1_INBAND_EXIT |
1340                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1341                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1342
1343                 /* Commit ULP changes by starting auto ULP configuration */
1344                 phy_reg |= I218_ULP_CONFIG1_START;
1345                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1346
1347                 /* Clear Disable SMBus Release on PERST# in MAC */
1348                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1349                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1350                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1351
1352                 if (!force) {
1353                         hw->phy.ops.release(hw);
1354
1355                         if (hw->mac.autoneg)
1356                                 e1000_phy_setup_autoneg(hw);
1357
1358                         e1000_sw_lcd_config_ich8lan(hw);
1359
1360                         e1000_oem_bits_config_ich8lan(hw, true);
1361
1362                         /* Set ULP state to unknown and return non-zero to
1363                          * indicate no link (yet) and re-enter on the next LSC
1364                          * to finish disabling ULP flow.
1365                          */
1366                         hw->dev_spec.ich8lan.ulp_state =
1367                             e1000_ulp_state_unknown;
1368
1369                         return 1;
1370                 }
1371         }
1372
1373         /* Re-enable Tx */
1374         mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1375         mac_reg |= E1000_TCTL_EN;
1376         E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1377
1378 release:
1379         hw->phy.ops.release(hw);
1380         if (force) {
1381                 hw->phy.ops.reset(hw);
1382                 msec_delay(50);
1383         }
1384 out:
1385         if (ret_val)
1386                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1387         else
1388                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1389
1390         return ret_val;
1391 }
1392
1393 #endif /* ULP_SUPPORT */
1394 /**
1395  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1396  *  @hw: pointer to the HW structure
1397  *
1398  *  Checks to see of the link status of the hardware has changed.  If a
1399  *  change in link status has been detected, then we read the PHY registers
1400  *  to get the current speed/duplex if link exists.
1401  **/
1402 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1403 {
1404         struct e1000_mac_info *mac = &hw->mac;
1405         s32 ret_val, tipg_reg = 0;
1406         u16 emi_addr, emi_val = 0;
1407         bool link = false;
1408         u16 phy_reg;
1409
1410         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1411
1412         /* We only want to go out to the PHY registers to see if Auto-Neg
1413          * has completed and/or if our link status has changed.  The
1414          * get_link_status flag is set upon receiving a Link Status
1415          * Change or Rx Sequence Error interrupt.
1416          */
1417         if (!mac->get_link_status)
1418                 return E1000_SUCCESS;
1419
1420         if ((hw->mac.type < e1000_pch_lpt) ||
1421             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1422             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1423                 /* First we want to see if the MII Status Register reports
1424                  * link.  If so, then we want to get the current speed/duplex
1425                  * of the PHY.
1426                  */
1427                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1428                 if (ret_val)
1429                         return ret_val;
1430         } else {
1431                 /* Check the MAC's STATUS register to determine link state
1432                  * since the PHY could be inaccessible while in ULP mode.
1433                  */
1434                 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1435                 if (link)
1436                         ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1437                 else
1438                         ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1439
1440                 if (ret_val)
1441                         return ret_val;
1442         }
1443
1444         if (hw->mac.type == e1000_pchlan) {
1445                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1446                 if (ret_val)
1447                         return ret_val;
1448         }
1449
1450         /* When connected at 10Mbps half-duplex, some parts are excessively
1451          * aggressive resulting in many collisions. To avoid this, increase
1452          * the IPG and reduce Rx latency in the PHY.
1453          */
1454         if (((hw->mac.type == e1000_pch2lan) ||
1455              (hw->mac.type == e1000_pch_lpt)) && link) {
1456                 u16 speed, duplex;
1457
1458                 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1459                 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1460                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1461
1462                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1463                         tipg_reg |= 0xFF;
1464                         /* Reduce Rx latency in analog PHY */
1465                         emi_val = 0;
1466                 } else {
1467                         /* Roll back the default values */
1468                         tipg_reg |= 0x08;
1469                         emi_val = 1;
1470                 }
1471
1472                 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1473
1474                 ret_val = hw->phy.ops.acquire(hw);
1475                 if (ret_val)
1476                         return ret_val;
1477
1478                 if (hw->mac.type == e1000_pch2lan)
1479                         emi_addr = I82579_RX_CONFIG;
1480                 else
1481                         emi_addr = I217_RX_CONFIG;
1482                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1483
1484                 hw->phy.ops.release(hw);
1485
1486                 if (ret_val)
1487                         return ret_val;
1488         }
1489
1490         /* I217 Packet Loss issue:
1491          * ensure that FEXTNVM4 Beacon Duration is set correctly
1492          * on power up.
1493          * Set the Beacon Duration for I217 to 8 usec
1494          */
1495         if (hw->mac.type == e1000_pch_lpt) {
1496                 u32 mac_reg;
1497
1498                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1499                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1500                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1501                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1502         }
1503
1504         /* Work-around I218 hang issue */
1505         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1506             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1507             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1508             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1509                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1510                 if (ret_val)
1511                         return ret_val;
1512         }
1513         /* Clear link partner's EEE ability */
1514         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1515
1516         /* Configure K0s minimum time */
1517         if (hw->mac.type == e1000_pch_lpt) {
1518                 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1519         }
1520
1521         if (!link)
1522                 return E1000_SUCCESS; /* No link detected */
1523
1524         mac->get_link_status = false;
1525
1526         switch (hw->mac.type) {
1527         case e1000_pch2lan:
1528                 ret_val = e1000_k1_workaround_lv(hw);
1529                 if (ret_val)
1530                         return ret_val;
1531                 /* fall-thru */
1532         case e1000_pchlan:
1533                 if (hw->phy.type == e1000_phy_82578) {
1534                         ret_val = e1000_link_stall_workaround_hv(hw);
1535                         if (ret_val)
1536                                 return ret_val;
1537                 }
1538
1539                 /* Workaround for PCHx parts in half-duplex:
1540                  * Set the number of preambles removed from the packet
1541                  * when it is passed from the PHY to the MAC to prevent
1542                  * the MAC from misinterpreting the packet type.
1543                  */
1544                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1545                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1546
1547                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1548                     E1000_STATUS_FD)
1549                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1550
1551                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1552                 break;
1553         default:
1554                 break;
1555         }
1556
1557         /* Check if there was DownShift, must be checked
1558          * immediately after link-up
1559          */
1560         e1000_check_downshift_generic(hw);
1561
1562         /* Enable/Disable EEE after link up */
1563         if (hw->phy.type > e1000_phy_82579) {
1564                 ret_val = e1000_set_eee_pchlan(hw);
1565                 if (ret_val)
1566                         return ret_val;
1567         }
1568
1569         /* If we are forcing speed/duplex, then we simply return since
1570          * we have already determined whether we have link or not.
1571          */
1572         if (!mac->autoneg)
1573                 return -E1000_ERR_CONFIG;
1574
1575         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1576          * of MAC speed/duplex configuration.  So we only need to
1577          * configure Collision Distance in the MAC.
1578          */
1579         mac->ops.config_collision_dist(hw);
1580
1581         /* Configure Flow Control now that Auto-Neg has completed.
1582          * First, we need to restore the desired flow control
1583          * settings because we may have had to re-autoneg with a
1584          * different link partner.
1585          */
1586         ret_val = e1000_config_fc_after_link_up_generic(hw);
1587         if (ret_val)
1588                 DEBUGOUT("Error configuring flow control\n");
1589
1590         return ret_val;
1591 }
1592
1593 /**
1594  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1595  *  @hw: pointer to the HW structure
1596  *
1597  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1598  **/
1599 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1600 {
1601         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1602
1603         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1604         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1605         switch (hw->mac.type) {
1606         case e1000_ich8lan:
1607         case e1000_ich9lan:
1608         case e1000_ich10lan:
1609                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1610                 break;
1611         case e1000_pchlan:
1612         case e1000_pch2lan:
1613         case e1000_pch_lpt:
1614                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1615                 break;
1616         default:
1617                 break;
1618         }
1619 }
1620
1621 /**
1622  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1623  *  @hw: pointer to the HW structure
1624  *
1625  *  Acquires the mutex for performing NVM operations.
1626  **/
1627 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1628 {
1629         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1630
1631         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1632
1633         return E1000_SUCCESS;
1634 }
1635
1636 /**
1637  *  e1000_release_nvm_ich8lan - Release NVM mutex
1638  *  @hw: pointer to the HW structure
1639  *
1640  *  Releases the mutex used while performing NVM operations.
1641  **/
1642 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1643 {
1644         DEBUGFUNC("e1000_release_nvm_ich8lan");
1645
1646         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1647
1648         return;
1649 }
1650
1651 /**
1652  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1653  *  @hw: pointer to the HW structure
1654  *
1655  *  Acquires the software control flag for performing PHY and select
1656  *  MAC CSR accesses.
1657  **/
1658 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1659 {
1660         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1661         s32 ret_val = E1000_SUCCESS;
1662
1663         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1664
1665         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1666
1667         while (timeout) {
1668                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1669                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1670                         break;
1671
1672                 msec_delay_irq(1);
1673                 timeout--;
1674         }
1675
1676         if (!timeout) {
1677                 DEBUGOUT("SW has already locked the resource.\n");
1678                 ret_val = -E1000_ERR_CONFIG;
1679                 goto out;
1680         }
1681
1682         timeout = SW_FLAG_TIMEOUT;
1683
1684         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1685         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1686
1687         while (timeout) {
1688                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1689                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1690                         break;
1691
1692                 msec_delay_irq(1);
1693                 timeout--;
1694         }
1695
1696         if (!timeout) {
1697                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1698                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1699                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1700                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1701                 ret_val = -E1000_ERR_CONFIG;
1702                 goto out;
1703         }
1704
1705 out:
1706         if (ret_val)
1707                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1708
1709         return ret_val;
1710 }
1711
1712 /**
1713  *  e1000_release_swflag_ich8lan - Release software control flag
1714  *  @hw: pointer to the HW structure
1715  *
1716  *  Releases the software control flag for performing PHY and select
1717  *  MAC CSR accesses.
1718  **/
1719 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1720 {
1721         u32 extcnf_ctrl;
1722
1723         DEBUGFUNC("e1000_release_swflag_ich8lan");
1724
1725         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1726
1727         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1728                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1729                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1730         } else {
1731                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1732         }
1733
1734         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1735
1736         return;
1737 }
1738
1739 /**
1740  *  e1000_check_mng_mode_ich8lan - Checks management mode
1741  *  @hw: pointer to the HW structure
1742  *
1743  *  This checks if the adapter has any manageability enabled.
1744  *  This is a function pointer entry point only called by read/write
1745  *  routines for the PHY and NVM parts.
1746  **/
1747 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1748 {
1749         u32 fwsm;
1750
1751         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1752
1753         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1754
1755         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1756                ((fwsm & E1000_FWSM_MODE_MASK) ==
1757                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1758 }
1759
1760 /**
1761  *  e1000_check_mng_mode_pchlan - Checks management mode
1762  *  @hw: pointer to the HW structure
1763  *
1764  *  This checks if the adapter has iAMT enabled.
1765  *  This is a function pointer entry point only called by read/write
1766  *  routines for the PHY and NVM parts.
1767  **/
1768 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1769 {
1770         u32 fwsm;
1771
1772         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1773
1774         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1775
1776         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1777                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1778 }
1779
1780 /**
1781  *  e1000_rar_set_pch2lan - Set receive address register
1782  *  @hw: pointer to the HW structure
1783  *  @addr: pointer to the receive address
1784  *  @index: receive address array register
1785  *
1786  *  Sets the receive address array register at index to the address passed
1787  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1788  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1789  *  Use SHRA[0-3] in place of those reserved for ME.
1790  **/
1791 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1792 {
1793         u32 rar_low, rar_high;
1794
1795         DEBUGFUNC("e1000_rar_set_pch2lan");
1796
1797         /* HW expects these in little endian so we reverse the byte order
1798          * from network order (big endian) to little endian
1799          */
1800         rar_low = ((u32) addr[0] |
1801                    ((u32) addr[1] << 8) |
1802                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1803
1804         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1805
1806         /* If MAC address zero, no need to set the AV bit */
1807         if (rar_low || rar_high)
1808                 rar_high |= E1000_RAH_AV;
1809
1810         if (index == 0) {
1811                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1812                 E1000_WRITE_FLUSH(hw);
1813                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1814                 E1000_WRITE_FLUSH(hw);
1815                 return E1000_SUCCESS;
1816         }
1817
1818         /* RAR[1-6] are owned by manageability.  Skip those and program the
1819          * next address into the SHRA register array.
1820          */
1821         if (index < (u32) (hw->mac.rar_entry_count)) {
1822                 s32 ret_val;
1823
1824                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1825                 if (ret_val)
1826                         goto out;
1827
1828                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1829                 E1000_WRITE_FLUSH(hw);
1830                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1831                 E1000_WRITE_FLUSH(hw);
1832
1833                 e1000_release_swflag_ich8lan(hw);
1834
1835                 /* verify the register updates */
1836                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1837                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1838                         return E1000_SUCCESS;
1839
1840                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1841                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1842         }
1843
1844 out:
1845         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1846         return -E1000_ERR_CONFIG;
1847 }
1848
1849 /**
1850  *  e1000_rar_set_pch_lpt - Set receive address registers
1851  *  @hw: pointer to the HW structure
1852  *  @addr: pointer to the receive address
1853  *  @index: receive address array register
1854  *
1855  *  Sets the receive address register array at index to the address passed
1856  *  in by addr. For LPT, RAR[0] is the base address register that is to
1857  *  contain the MAC address. SHRA[0-10] are the shared receive address
1858  *  registers that are shared between the Host and manageability engine (ME).
1859  **/
1860 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1861 {
1862         u32 rar_low, rar_high;
1863         u32 wlock_mac;
1864
1865         DEBUGFUNC("e1000_rar_set_pch_lpt");
1866
1867         /* HW expects these in little endian so we reverse the byte order
1868          * from network order (big endian) to little endian
1869          */
1870         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1871                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1872
1873         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1874
1875         /* If MAC address zero, no need to set the AV bit */
1876         if (rar_low || rar_high)
1877                 rar_high |= E1000_RAH_AV;
1878
1879         if (index == 0) {
1880                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1881                 E1000_WRITE_FLUSH(hw);
1882                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1883                 E1000_WRITE_FLUSH(hw);
1884                 return E1000_SUCCESS;
1885         }
1886
1887         /* The manageability engine (ME) can lock certain SHRAR registers that
1888          * it is using - those registers are unavailable for use.
1889          */
1890         if (index < hw->mac.rar_entry_count) {
1891                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1892                             E1000_FWSM_WLOCK_MAC_MASK;
1893                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1894
1895                 /* Check if all SHRAR registers are locked */
1896                 if (wlock_mac == 1)
1897                         goto out;
1898
1899                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1900                         s32 ret_val;
1901
1902                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1903
1904                         if (ret_val)
1905                                 goto out;
1906
1907                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1908                                         rar_low);
1909                         E1000_WRITE_FLUSH(hw);
1910                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1911                                         rar_high);
1912                         E1000_WRITE_FLUSH(hw);
1913
1914                         e1000_release_swflag_ich8lan(hw);
1915
1916                         /* verify the register updates */
1917                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1918                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1919                                 return E1000_SUCCESS;
1920                 }
1921         }
1922
1923 out:
1924         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1925         return -E1000_ERR_CONFIG;
1926 }
1927
1928 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
1929 /**
1930  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1931  *  @hw: pointer to the HW structure
1932  *  @mc_addr_list: array of multicast addresses to program
1933  *  @mc_addr_count: number of multicast addresses to program
1934  *
1935  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1936  *  The caller must have a packed mc_addr_list of multicast addresses.
1937  **/
1938 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1939                                               u8 *mc_addr_list,
1940                                               u32 mc_addr_count)
1941 {
1942         u16 phy_reg = 0;
1943         int i;
1944         s32 ret_val;
1945
1946         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1947
1948         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1949
1950         ret_val = hw->phy.ops.acquire(hw);
1951         if (ret_val)
1952                 return;
1953
1954         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1955         if (ret_val)
1956                 goto release;
1957
1958         for (i = 0; i < hw->mac.mta_reg_count; i++) {
1959                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1960                                            (u16)(hw->mac.mta_shadow[i] &
1961                                                  0xFFFF));
1962                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1963                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
1964                                                  0xFFFF));
1965         }
1966
1967         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1968
1969 release:
1970         hw->phy.ops.release(hw);
1971 }
1972
1973 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
1974 /**
1975  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1976  *  @hw: pointer to the HW structure
1977  *
1978  *  Checks if firmware is blocking the reset of the PHY.
1979  *  This is a function pointer entry point only called by
1980  *  reset routines.
1981  **/
1982 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1983 {
1984         u32 fwsm;
1985         bool blocked = false;
1986         int i = 0;
1987
1988         DEBUGFUNC("e1000_check_reset_block_ich8lan");
1989
1990         do {
1991                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1992                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
1993                         blocked = true;
1994                         msec_delay(10);
1995                         continue;
1996                 }
1997                 blocked = false;
1998         } while (blocked && (i++ < 30));
1999         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2000 }
2001
2002 /**
2003  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2004  *  @hw: pointer to the HW structure
2005  *
2006  *  Assumes semaphore already acquired.
2007  *
2008  **/
2009 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2010 {
2011         u16 phy_data;
2012         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2013         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2014                 E1000_STRAP_SMT_FREQ_SHIFT;
2015         s32 ret_val;
2016
2017         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2018
2019         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2020         if (ret_val)
2021                 return ret_val;
2022
2023         phy_data &= ~HV_SMB_ADDR_MASK;
2024         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2025         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2026
2027         if (hw->phy.type == e1000_phy_i217) {
2028                 /* Restore SMBus frequency */
2029                 if (freq--) {
2030                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2031                         phy_data |= (freq & (1 << 0)) <<
2032                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2033                         phy_data |= (freq & (1 << 1)) <<
2034                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2035                 } else {
2036                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
2037                 }
2038         }
2039
2040         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2041 }
2042
2043 /**
2044  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2045  *  @hw:   pointer to the HW structure
2046  *
2047  *  SW should configure the LCD from the NVM extended configuration region
2048  *  as a workaround for certain parts.
2049  **/
2050 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2051 {
2052         struct e1000_phy_info *phy = &hw->phy;
2053         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2054         s32 ret_val = E1000_SUCCESS;
2055         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2056
2057         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2058
2059         /* Initialize the PHY from the NVM on ICH platforms.  This
2060          * is needed due to an issue where the NVM configuration is
2061          * not properly autoloaded after power transitions.
2062          * Therefore, after each PHY reset, we will load the
2063          * configuration data out of the NVM manually.
2064          */
2065         switch (hw->mac.type) {
2066         case e1000_ich8lan:
2067                 if (phy->type != e1000_phy_igp_3)
2068                         return ret_val;
2069
2070                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2071                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2072                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2073                         break;
2074                 }
2075                 /* Fall-thru */
2076         case e1000_pchlan:
2077         case e1000_pch2lan:
2078         case e1000_pch_lpt:
2079                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2080                 break;
2081         default:
2082                 return ret_val;
2083         }
2084
2085         ret_val = hw->phy.ops.acquire(hw);
2086         if (ret_val)
2087                 return ret_val;
2088
2089         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2090         if (!(data & sw_cfg_mask))
2091                 goto release;
2092
2093         /* Make sure HW does not configure LCD from PHY
2094          * extended configuration before SW configuration
2095          */
2096         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2097         if ((hw->mac.type < e1000_pch2lan) &&
2098             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2099                         goto release;
2100
2101         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2102         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2103         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2104         if (!cnf_size)
2105                 goto release;
2106
2107         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2108         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2109
2110         if (((hw->mac.type == e1000_pchlan) &&
2111              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2112             (hw->mac.type > e1000_pchlan)) {
2113                 /* HW configures the SMBus address and LEDs when the
2114                  * OEM and LCD Write Enable bits are set in the NVM.
2115                  * When both NVM bits are cleared, SW will configure
2116                  * them instead.
2117                  */
2118                 ret_val = e1000_write_smbus_addr(hw);
2119                 if (ret_val)
2120                         goto release;
2121
2122                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2123                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2124                                                         (u16)data);
2125                 if (ret_val)
2126                         goto release;
2127         }
2128
2129         /* Configure LCD from extended configuration region. */
2130
2131         /* cnf_base_addr is in DWORD */
2132         word_addr = (u16)(cnf_base_addr << 1);
2133
2134         for (i = 0; i < cnf_size; i++) {
2135                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2136                                            &reg_data);
2137                 if (ret_val)
2138                         goto release;
2139
2140                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2141                                            1, &reg_addr);
2142                 if (ret_val)
2143                         goto release;
2144
2145                 /* Save off the PHY page for future writes. */
2146                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2147                         phy_page = reg_data;
2148                         continue;
2149                 }
2150
2151                 reg_addr &= PHY_REG_MASK;
2152                 reg_addr |= phy_page;
2153
2154                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2155                                                     reg_data);
2156                 if (ret_val)
2157                         goto release;
2158         }
2159
2160 release:
2161         hw->phy.ops.release(hw);
2162         return ret_val;
2163 }
2164
2165 /**
2166  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2167  *  @hw:   pointer to the HW structure
2168  *  @link: link up bool flag
2169  *
2170  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2171  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2172  *  If link is down, the function will restore the default K1 setting located
2173  *  in the NVM.
2174  **/
2175 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2176 {
2177         s32 ret_val = E1000_SUCCESS;
2178         u16 status_reg = 0;
2179         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2180
2181         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2182
2183         if (hw->mac.type != e1000_pchlan)
2184                 return E1000_SUCCESS;
2185
2186         /* Wrap the whole flow with the sw flag */
2187         ret_val = hw->phy.ops.acquire(hw);
2188         if (ret_val)
2189                 return ret_val;
2190
2191         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2192         if (link) {
2193                 if (hw->phy.type == e1000_phy_82578) {
2194                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2195                                                               &status_reg);
2196                         if (ret_val)
2197                                 goto release;
2198
2199                         status_reg &= (BM_CS_STATUS_LINK_UP |
2200                                        BM_CS_STATUS_RESOLVED |
2201                                        BM_CS_STATUS_SPEED_MASK);
2202
2203                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2204                                            BM_CS_STATUS_RESOLVED |
2205                                            BM_CS_STATUS_SPEED_1000))
2206                                 k1_enable = false;
2207                 }
2208
2209                 if (hw->phy.type == e1000_phy_82577) {
2210                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2211                                                               &status_reg);
2212                         if (ret_val)
2213                                 goto release;
2214
2215                         status_reg &= (HV_M_STATUS_LINK_UP |
2216                                        HV_M_STATUS_AUTONEG_COMPLETE |
2217                                        HV_M_STATUS_SPEED_MASK);
2218
2219                         if (status_reg == (HV_M_STATUS_LINK_UP |
2220                                            HV_M_STATUS_AUTONEG_COMPLETE |
2221                                            HV_M_STATUS_SPEED_1000))
2222                                 k1_enable = false;
2223                 }
2224
2225                 /* Link stall fix for link up */
2226                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2227                                                        0x0100);
2228                 if (ret_val)
2229                         goto release;
2230
2231         } else {
2232                 /* Link stall fix for link down */
2233                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2234                                                        0x4100);
2235                 if (ret_val)
2236                         goto release;
2237         }
2238
2239         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2240
2241 release:
2242         hw->phy.ops.release(hw);
2243
2244         return ret_val;
2245 }
2246
2247 /**
2248  *  e1000_configure_k1_ich8lan - Configure K1 power state
2249  *  @hw: pointer to the HW structure
2250  *  @enable: K1 state to configure
2251  *
2252  *  Configure the K1 power state based on the provided parameter.
2253  *  Assumes semaphore already acquired.
2254  *
2255  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2256  **/
2257 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2258 {
2259         s32 ret_val;
2260         u32 ctrl_reg = 0;
2261         u32 ctrl_ext = 0;
2262         u32 reg = 0;
2263         u16 kmrn_reg = 0;
2264
2265         DEBUGFUNC("e1000_configure_k1_ich8lan");
2266
2267         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2268                                              &kmrn_reg);
2269         if (ret_val)
2270                 return ret_val;
2271
2272         if (k1_enable)
2273                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2274         else
2275                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2276
2277         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2278                                               kmrn_reg);
2279         if (ret_val)
2280                 return ret_val;
2281
2282         usec_delay(20);
2283         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2284         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2285
2286         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2287         reg |= E1000_CTRL_FRCSPD;
2288         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2289
2290         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2291         E1000_WRITE_FLUSH(hw);
2292         usec_delay(20);
2293         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2294         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2295         E1000_WRITE_FLUSH(hw);
2296         usec_delay(20);
2297
2298         return E1000_SUCCESS;
2299 }
2300
2301 /**
2302  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2303  *  @hw:       pointer to the HW structure
2304  *  @d0_state: boolean if entering d0 or d3 device state
2305  *
2306  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2307  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2308  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2309  **/
2310 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2311 {
2312         s32 ret_val = 0;
2313         u32 mac_reg;
2314         u16 oem_reg;
2315
2316         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2317
2318         if (hw->mac.type < e1000_pchlan)
2319                 return ret_val;
2320
2321         ret_val = hw->phy.ops.acquire(hw);
2322         if (ret_val)
2323                 return ret_val;
2324
2325         if (hw->mac.type == e1000_pchlan) {
2326                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2327                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2328                         goto release;
2329         }
2330
2331         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2332         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2333                 goto release;
2334
2335         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2336
2337         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2338         if (ret_val)
2339                 goto release;
2340
2341         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2342
2343         if (d0_state) {
2344                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2345                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2346
2347                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2348                         oem_reg |= HV_OEM_BITS_LPLU;
2349         } else {
2350                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2351                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2352                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2353
2354                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2355                     E1000_PHY_CTRL_NOND0A_LPLU))
2356                         oem_reg |= HV_OEM_BITS_LPLU;
2357         }
2358
2359         /* Set Restart auto-neg to activate the bits */
2360         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2361             !hw->phy.ops.check_reset_block(hw))
2362                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2363
2364         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2365
2366 release:
2367         hw->phy.ops.release(hw);
2368
2369         return ret_val;
2370 }
2371
2372
2373 /**
2374  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2375  *  @hw:   pointer to the HW structure
2376  **/
2377 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2378 {
2379         s32 ret_val;
2380         u16 data;
2381
2382         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2383
2384         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2385         if (ret_val)
2386                 return ret_val;
2387
2388         data |= HV_KMRN_MDIO_SLOW;
2389
2390         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2391
2392         return ret_val;
2393 }
2394
2395 /**
2396  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2397  *  done after every PHY reset.
2398  **/
2399 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2400 {
2401         s32 ret_val = E1000_SUCCESS;
2402         u16 phy_data;
2403
2404         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2405
2406         if (hw->mac.type != e1000_pchlan)
2407                 return E1000_SUCCESS;
2408
2409         /* Set MDIO slow mode before any other MDIO access */
2410         if (hw->phy.type == e1000_phy_82577) {
2411                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2412                 if (ret_val)
2413                         return ret_val;
2414         }
2415
2416         if (((hw->phy.type == e1000_phy_82577) &&
2417              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2418             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2419                 /* Disable generation of early preamble */
2420                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2421                 if (ret_val)
2422                         return ret_val;
2423
2424                 /* Preamble tuning for SSC */
2425                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2426                                                 0xA204);
2427                 if (ret_val)
2428                         return ret_val;
2429         }
2430
2431         if (hw->phy.type == e1000_phy_82578) {
2432                 /* Return registers to default by doing a soft reset then
2433                  * writing 0x3140 to the control register.
2434                  */
2435                 if (hw->phy.revision < 2) {
2436                         e1000_phy_sw_reset_generic(hw);
2437                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2438                                                         0x3140);
2439                 }
2440         }
2441
2442         /* Select page 0 */
2443         ret_val = hw->phy.ops.acquire(hw);
2444         if (ret_val)
2445                 return ret_val;
2446
2447         hw->phy.addr = 1;
2448         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2449         hw->phy.ops.release(hw);
2450         if (ret_val)
2451                 return ret_val;
2452
2453         /* Configure the K1 Si workaround during phy reset assuming there is
2454          * link so that it disables K1 if link is in 1Gbps.
2455          */
2456         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2457         if (ret_val)
2458                 return ret_val;
2459
2460         /* Workaround for link disconnects on a busy hub in half duplex */
2461         ret_val = hw->phy.ops.acquire(hw);
2462         if (ret_val)
2463                 return ret_val;
2464         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2465         if (ret_val)
2466                 goto release;
2467         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2468                                                phy_data & 0x00FF);
2469         if (ret_val)
2470                 goto release;
2471
2472         /* set MSE higher to enable link to stay up when noise is high */
2473         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2474 release:
2475         hw->phy.ops.release(hw);
2476
2477         return ret_val;
2478 }
2479
2480 /**
2481  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2482  *  @hw:   pointer to the HW structure
2483  **/
2484 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2485 {
2486         u32 mac_reg;
2487         u16 i, phy_reg = 0;
2488         s32 ret_val;
2489
2490         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2491
2492         ret_val = hw->phy.ops.acquire(hw);
2493         if (ret_val)
2494                 return;
2495         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2496         if (ret_val)
2497                 goto release;
2498
2499         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2500         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2501                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2502                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2503                                            (u16)(mac_reg & 0xFFFF));
2504                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2505                                            (u16)((mac_reg >> 16) & 0xFFFF));
2506
2507                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2508                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2509                                            (u16)(mac_reg & 0xFFFF));
2510                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2511                                            (u16)((mac_reg & E1000_RAH_AV)
2512                                                  >> 16));
2513         }
2514
2515         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2516
2517 release:
2518         hw->phy.ops.release(hw);
2519 }
2520
2521 #ifndef CRC32_OS_SUPPORT
2522 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2523 {
2524         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2525         u32 i, j, mask, crc;
2526
2527         DEBUGFUNC("e1000_calc_rx_da_crc");
2528
2529         crc = 0xffffffff;
2530         for (i = 0; i < 6; i++) {
2531                 crc = crc ^ mac[i];
2532                 for (j = 8; j > 0; j--) {
2533                         mask = (crc & 1) * (-1);
2534                         crc = (crc >> 1) ^ (poly & mask);
2535                 }
2536         }
2537         return ~crc;
2538 }
2539
2540 #endif /* CRC32_OS_SUPPORT */
2541 /**
2542  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2543  *  with 82579 PHY
2544  *  @hw: pointer to the HW structure
2545  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2546  **/
2547 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2548 {
2549         s32 ret_val = E1000_SUCCESS;
2550         u16 phy_reg, data;
2551         u32 mac_reg;
2552         u16 i;
2553
2554         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2555
2556         if (hw->mac.type < e1000_pch2lan)
2557                 return E1000_SUCCESS;
2558
2559         /* disable Rx path while enabling/disabling workaround */
2560         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2561         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2562                                         phy_reg | (1 << 14));
2563         if (ret_val)
2564                 return ret_val;
2565
2566         if (enable) {
2567                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2568                  * SHRAL/H) and initial CRC values to the MAC
2569                  */
2570                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2571                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2572                         u32 addr_high, addr_low;
2573
2574                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2575                         if (!(addr_high & E1000_RAH_AV))
2576                                 continue;
2577                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2578                         mac_addr[0] = (addr_low & 0xFF);
2579                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2580                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2581                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2582                         mac_addr[4] = (addr_high & 0xFF);
2583                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2584
2585 #ifndef CRC32_OS_SUPPORT
2586                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2587                                         e1000_calc_rx_da_crc(mac_addr));
2588 #else /* CRC32_OS_SUPPORT */
2589                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2590                                         E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2591 #endif /* CRC32_OS_SUPPORT */
2592                 }
2593
2594                 /* Write Rx addresses to the PHY */
2595                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2596
2597                 /* Enable jumbo frame workaround in the MAC */
2598                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2599                 mac_reg &= ~(1 << 14);
2600                 mac_reg |= (7 << 15);
2601                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2602
2603                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2604                 mac_reg |= E1000_RCTL_SECRC;
2605                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2606
2607                 ret_val = e1000_read_kmrn_reg_generic(hw,
2608                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2609                                                 &data);
2610                 if (ret_val)
2611                         return ret_val;
2612                 ret_val = e1000_write_kmrn_reg_generic(hw,
2613                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2614                                                 data | (1 << 0));
2615                 if (ret_val)
2616                         return ret_val;
2617                 ret_val = e1000_read_kmrn_reg_generic(hw,
2618                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2619                                                 &data);
2620                 if (ret_val)
2621                         return ret_val;
2622                 data &= ~(0xF << 8);
2623                 data |= (0xB << 8);
2624                 ret_val = e1000_write_kmrn_reg_generic(hw,
2625                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2626                                                 data);
2627                 if (ret_val)
2628                         return ret_val;
2629
2630                 /* Enable jumbo frame workaround in the PHY */
2631                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2632                 data &= ~(0x7F << 5);
2633                 data |= (0x37 << 5);
2634                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2635                 if (ret_val)
2636                         return ret_val;
2637                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2638                 data &= ~(1 << 13);
2639                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2640                 if (ret_val)
2641                         return ret_val;
2642                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2643                 data &= ~(0x3FF << 2);
2644                 data |= (E1000_TX_PTR_GAP << 2);
2645                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2646                 if (ret_val)
2647                         return ret_val;
2648                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2649                 if (ret_val)
2650                         return ret_val;
2651                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2652                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2653                                                 (1 << 10));
2654                 if (ret_val)
2655                         return ret_val;
2656         } else {
2657                 /* Write MAC register values back to h/w defaults */
2658                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2659                 mac_reg &= ~(0xF << 14);
2660                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2661
2662                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2663                 mac_reg &= ~E1000_RCTL_SECRC;
2664                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2665
2666                 ret_val = e1000_read_kmrn_reg_generic(hw,
2667                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2668                                                 &data);
2669                 if (ret_val)
2670                         return ret_val;
2671                 ret_val = e1000_write_kmrn_reg_generic(hw,
2672                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2673                                                 data & ~(1 << 0));
2674                 if (ret_val)
2675                         return ret_val;
2676                 ret_val = e1000_read_kmrn_reg_generic(hw,
2677                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2678                                                 &data);
2679                 if (ret_val)
2680                         return ret_val;
2681                 data &= ~(0xF << 8);
2682                 data |= (0xB << 8);
2683                 ret_val = e1000_write_kmrn_reg_generic(hw,
2684                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2685                                                 data);
2686                 if (ret_val)
2687                         return ret_val;
2688
2689                 /* Write PHY register values back to h/w defaults */
2690                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2691                 data &= ~(0x7F << 5);
2692                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2693                 if (ret_val)
2694                         return ret_val;
2695                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2696                 data |= (1 << 13);
2697                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2698                 if (ret_val)
2699                         return ret_val;
2700                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2701                 data &= ~(0x3FF << 2);
2702                 data |= (0x8 << 2);
2703                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2704                 if (ret_val)
2705                         return ret_val;
2706                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2707                 if (ret_val)
2708                         return ret_val;
2709                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2710                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2711                                                 ~(1 << 10));
2712                 if (ret_val)
2713                         return ret_val;
2714         }
2715
2716         /* re-enable Rx path after enabling/disabling workaround */
2717         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2718                                      ~(1 << 14));
2719 }
2720
2721 /**
2722  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2723  *  done after every PHY reset.
2724  **/
2725 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2726 {
2727         s32 ret_val = E1000_SUCCESS;
2728
2729         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2730
2731         if (hw->mac.type != e1000_pch2lan)
2732                 return E1000_SUCCESS;
2733
2734         /* Set MDIO slow mode before any other MDIO access */
2735         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2736         if (ret_val)
2737                 return ret_val;
2738
2739         ret_val = hw->phy.ops.acquire(hw);
2740         if (ret_val)
2741                 return ret_val;
2742         /* set MSE higher to enable link to stay up when noise is high */
2743         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2744         if (ret_val)
2745                 goto release;
2746         /* drop link after 5 times MSE threshold was reached */
2747         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2748 release:
2749         hw->phy.ops.release(hw);
2750
2751         return ret_val;
2752 }
2753
2754 /**
2755  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2756  *  @hw:   pointer to the HW structure
2757  *
2758  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2759  *  Disable K1 for 1000 and 100 speeds
2760  **/
2761 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2762 {
2763         s32 ret_val = E1000_SUCCESS;
2764         u16 status_reg = 0;
2765
2766         DEBUGFUNC("e1000_k1_workaround_lv");
2767
2768         if (hw->mac.type != e1000_pch2lan)
2769                 return E1000_SUCCESS;
2770
2771         /* Set K1 beacon duration based on 10Mbs speed */
2772         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2773         if (ret_val)
2774                 return ret_val;
2775
2776         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2777             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2778                 if (status_reg &
2779                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2780                         u16 pm_phy_reg;
2781
2782                         /* LV 1G/100 Packet drop issue wa  */
2783                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2784                                                        &pm_phy_reg);
2785                         if (ret_val)
2786                                 return ret_val;
2787                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2788                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2789                                                         pm_phy_reg);
2790                         if (ret_val)
2791                                 return ret_val;
2792                 } else {
2793                         u32 mac_reg;
2794                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2795                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2796                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2797                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2798                 }
2799         }
2800
2801         return ret_val;
2802 }
2803
2804 /**
2805  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2806  *  @hw:   pointer to the HW structure
2807  *  @gate: boolean set to true to gate, false to ungate
2808  *
2809  *  Gate/ungate the automatic PHY configuration via hardware; perform
2810  *  the configuration via software instead.
2811  **/
2812 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2813 {
2814         u32 extcnf_ctrl;
2815
2816         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2817
2818         if (hw->mac.type < e1000_pch2lan)
2819                 return;
2820
2821         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2822
2823         if (gate)
2824                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2825         else
2826                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2827
2828         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2829 }
2830
2831 /**
2832  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2833  *  @hw: pointer to the HW structure
2834  *
2835  *  Check the appropriate indication the MAC has finished configuring the
2836  *  PHY after a software reset.
2837  **/
2838 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2839 {
2840         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2841
2842         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2843
2844         /* Wait for basic configuration completes before proceeding */
2845         do {
2846                 data = E1000_READ_REG(hw, E1000_STATUS);
2847                 data &= E1000_STATUS_LAN_INIT_DONE;
2848                 usec_delay(100);
2849         } while ((!data) && --loop);
2850
2851         /* If basic configuration is incomplete before the above loop
2852          * count reaches 0, loading the configuration from NVM will
2853          * leave the PHY in a bad state possibly resulting in no link.
2854          */
2855         if (loop == 0)
2856                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2857
2858         /* Clear the Init Done bit for the next init event */
2859         data = E1000_READ_REG(hw, E1000_STATUS);
2860         data &= ~E1000_STATUS_LAN_INIT_DONE;
2861         E1000_WRITE_REG(hw, E1000_STATUS, data);
2862 }
2863
2864 /**
2865  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2866  *  @hw: pointer to the HW structure
2867  **/
2868 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2869 {
2870         s32 ret_val = E1000_SUCCESS;
2871         u16 reg;
2872
2873         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2874
2875         if (hw->phy.ops.check_reset_block(hw))
2876                 return E1000_SUCCESS;
2877
2878         /* Allow time for h/w to get to quiescent state after reset */
2879         msec_delay(10);
2880
2881         /* Perform any necessary post-reset workarounds */
2882         switch (hw->mac.type) {
2883         case e1000_pchlan:
2884                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2885                 if (ret_val)
2886                         return ret_val;
2887                 break;
2888         case e1000_pch2lan:
2889                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2890                 if (ret_val)
2891                         return ret_val;
2892                 break;
2893         default:
2894                 break;
2895         }
2896
2897         /* Clear the host wakeup bit after lcd reset */
2898         if (hw->mac.type >= e1000_pchlan) {
2899                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
2900                 reg &= ~BM_WUC_HOST_WU_BIT;
2901                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2902         }
2903
2904         /* Configure the LCD with the extended configuration region in NVM */
2905         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2906         if (ret_val)
2907                 return ret_val;
2908
2909         /* Configure the LCD with the OEM bits in NVM */
2910         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2911
2912         if (hw->mac.type == e1000_pch2lan) {
2913                 /* Ungate automatic PHY configuration on non-managed 82579 */
2914                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2915                     E1000_ICH_FWSM_FW_VALID)) {
2916                         msec_delay(10);
2917                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2918                 }
2919
2920                 /* Set EEE LPI Update Timer to 200usec */
2921                 ret_val = hw->phy.ops.acquire(hw);
2922                 if (ret_val)
2923                         return ret_val;
2924                 ret_val = e1000_write_emi_reg_locked(hw,
2925                                                      I82579_LPI_UPDATE_TIMER,
2926                                                      0x1387);
2927                 hw->phy.ops.release(hw);
2928         }
2929
2930         return ret_val;
2931 }
2932
2933 /**
2934  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2935  *  @hw: pointer to the HW structure
2936  *
2937  *  Resets the PHY
2938  *  This is a function pointer entry point called by drivers
2939  *  or other shared routines.
2940  **/
2941 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2942 {
2943         s32 ret_val = E1000_SUCCESS;
2944
2945         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2946
2947         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2948         if ((hw->mac.type == e1000_pch2lan) &&
2949             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2950                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2951
2952         ret_val = e1000_phy_hw_reset_generic(hw);
2953         if (ret_val)
2954                 return ret_val;
2955
2956         return e1000_post_phy_reset_ich8lan(hw);
2957 }
2958
2959 /**
2960  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2961  *  @hw: pointer to the HW structure
2962  *  @active: true to enable LPLU, false to disable
2963  *
2964  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2965  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2966  *  the phy speed. This function will manually set the LPLU bit and restart
2967  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2968  *  since it configures the same bit.
2969  **/
2970 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2971 {
2972         s32 ret_val;
2973         u16 oem_reg;
2974
2975         DEBUGFUNC("e1000_set_lplu_state_pchlan");
2976
2977         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2978         if (ret_val)
2979                 return ret_val;
2980
2981         if (active)
2982                 oem_reg |= HV_OEM_BITS_LPLU;
2983         else
2984                 oem_reg &= ~HV_OEM_BITS_LPLU;
2985
2986         if (!hw->phy.ops.check_reset_block(hw))
2987                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2988
2989         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2990 }
2991
2992 /**
2993  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2994  *  @hw: pointer to the HW structure
2995  *  @active: true to enable LPLU, false to disable
2996  *
2997  *  Sets the LPLU D0 state according to the active flag.  When
2998  *  activating LPLU this function also disables smart speed
2999  *  and vice versa.  LPLU will not be activated unless the
3000  *  device autonegotiation advertisement meets standards of
3001  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3002  *  This is a function pointer entry point only called by
3003  *  PHY setup routines.
3004  **/
3005 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3006 {
3007         struct e1000_phy_info *phy = &hw->phy;
3008         u32 phy_ctrl;
3009         s32 ret_val = E1000_SUCCESS;
3010         u16 data;
3011
3012         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3013
3014         if (phy->type == e1000_phy_ife)
3015                 return E1000_SUCCESS;
3016
3017         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3018
3019         if (active) {
3020                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3021                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3022
3023                 if (phy->type != e1000_phy_igp_3)
3024                         return E1000_SUCCESS;
3025
3026                 /* Call gig speed drop workaround on LPLU before accessing
3027                  * any PHY registers
3028                  */
3029                 if (hw->mac.type == e1000_ich8lan)
3030                         e1000_gig_downshift_workaround_ich8lan(hw);
3031
3032                 /* When LPLU is enabled, we should disable SmartSpeed */
3033                 ret_val = phy->ops.read_reg(hw,
3034                                             IGP01E1000_PHY_PORT_CONFIG,
3035                                             &data);
3036                 if (ret_val)
3037                         return ret_val;
3038                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3039                 ret_val = phy->ops.write_reg(hw,
3040                                              IGP01E1000_PHY_PORT_CONFIG,
3041                                              data);
3042                 if (ret_val)
3043                         return ret_val;
3044         } else {
3045                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3046                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3047
3048                 if (phy->type != e1000_phy_igp_3)
3049                         return E1000_SUCCESS;
3050
3051                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3052                  * during Dx states where the power conservation is most
3053                  * important.  During driver activity we should enable
3054                  * SmartSpeed, so performance is maintained.
3055                  */
3056                 if (phy->smart_speed == e1000_smart_speed_on) {
3057                         ret_val = phy->ops.read_reg(hw,
3058                                                     IGP01E1000_PHY_PORT_CONFIG,
3059                                                     &data);
3060                         if (ret_val)
3061                                 return ret_val;
3062
3063                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3064                         ret_val = phy->ops.write_reg(hw,
3065                                                      IGP01E1000_PHY_PORT_CONFIG,
3066                                                      data);
3067                         if (ret_val)
3068                                 return ret_val;
3069                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3070                         ret_val = phy->ops.read_reg(hw,
3071                                                     IGP01E1000_PHY_PORT_CONFIG,
3072                                                     &data);
3073                         if (ret_val)
3074                                 return ret_val;
3075
3076                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3077                         ret_val = phy->ops.write_reg(hw,
3078                                                      IGP01E1000_PHY_PORT_CONFIG,
3079                                                      data);
3080                         if (ret_val)
3081                                 return ret_val;
3082                 }
3083         }
3084
3085         return E1000_SUCCESS;
3086 }
3087
3088 /**
3089  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3090  *  @hw: pointer to the HW structure
3091  *  @active: true to enable LPLU, false to disable
3092  *
3093  *  Sets the LPLU D3 state according to the active flag.  When
3094  *  activating LPLU this function also disables smart speed
3095  *  and vice versa.  LPLU will not be activated unless the
3096  *  device autonegotiation advertisement meets standards of
3097  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3098  *  This is a function pointer entry point only called by
3099  *  PHY setup routines.
3100  **/
3101 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3102 {
3103         struct e1000_phy_info *phy = &hw->phy;
3104         u32 phy_ctrl;
3105         s32 ret_val = E1000_SUCCESS;
3106         u16 data;
3107
3108         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3109
3110         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3111
3112         if (!active) {
3113                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3114                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3115
3116                 if (phy->type != e1000_phy_igp_3)
3117                         return E1000_SUCCESS;
3118
3119                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3120                  * during Dx states where the power conservation is most
3121                  * important.  During driver activity we should enable
3122                  * SmartSpeed, so performance is maintained.
3123                  */
3124                 if (phy->smart_speed == e1000_smart_speed_on) {
3125                         ret_val = phy->ops.read_reg(hw,
3126                                                     IGP01E1000_PHY_PORT_CONFIG,
3127                                                     &data);
3128                         if (ret_val)
3129                                 return ret_val;
3130
3131                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3132                         ret_val = phy->ops.write_reg(hw,
3133                                                      IGP01E1000_PHY_PORT_CONFIG,
3134                                                      data);
3135                         if (ret_val)
3136                                 return ret_val;
3137                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3138                         ret_val = phy->ops.read_reg(hw,
3139                                                     IGP01E1000_PHY_PORT_CONFIG,
3140                                                     &data);
3141                         if (ret_val)
3142                                 return ret_val;
3143
3144                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3145                         ret_val = phy->ops.write_reg(hw,
3146                                                      IGP01E1000_PHY_PORT_CONFIG,
3147                                                      data);
3148                         if (ret_val)
3149                                 return ret_val;
3150                 }
3151         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3152                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3153                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3154                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3155                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3156
3157                 if (phy->type != e1000_phy_igp_3)
3158                         return E1000_SUCCESS;
3159
3160                 /* Call gig speed drop workaround on LPLU before accessing
3161                  * any PHY registers
3162                  */
3163                 if (hw->mac.type == e1000_ich8lan)
3164                         e1000_gig_downshift_workaround_ich8lan(hw);
3165
3166                 /* When LPLU is enabled, we should disable SmartSpeed */
3167                 ret_val = phy->ops.read_reg(hw,
3168                                             IGP01E1000_PHY_PORT_CONFIG,
3169                                             &data);
3170                 if (ret_val)
3171                         return ret_val;
3172
3173                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3174                 ret_val = phy->ops.write_reg(hw,
3175                                              IGP01E1000_PHY_PORT_CONFIG,
3176                                              data);
3177         }
3178
3179         return ret_val;
3180 }
3181
3182 /**
3183  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3184  *  @hw: pointer to the HW structure
3185  *  @bank:  pointer to the variable that returns the active bank
3186  *
3187  *  Reads signature byte from the NVM using the flash access registers.
3188  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3189  **/
3190 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3191 {
3192         u32 eecd;
3193         struct e1000_nvm_info *nvm = &hw->nvm;
3194         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3195         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3196         u8 sig_byte = 0;
3197         s32 ret_val;
3198
3199         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3200
3201         switch (hw->mac.type) {
3202         case e1000_ich8lan:
3203         case e1000_ich9lan:
3204                 eecd = E1000_READ_REG(hw, E1000_EECD);
3205                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3206                     E1000_EECD_SEC1VAL_VALID_MASK) {
3207                         if (eecd & E1000_EECD_SEC1VAL)
3208                                 *bank = 1;
3209                         else
3210                                 *bank = 0;
3211
3212                         return E1000_SUCCESS;
3213                 }
3214                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3215                 /* fall-thru */
3216         default:
3217                 /* set bank to 0 in case flash read fails */
3218                 *bank = 0;
3219
3220                 /* Check bank 0 */
3221                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3222                                                         &sig_byte);
3223                 if (ret_val)
3224                         return ret_val;
3225                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3226                     E1000_ICH_NVM_SIG_VALUE) {
3227                         *bank = 0;
3228                         return E1000_SUCCESS;
3229                 }
3230
3231                 /* Check bank 1 */
3232                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3233                                                         bank1_offset,
3234                                                         &sig_byte);
3235                 if (ret_val)
3236                         return ret_val;
3237                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3238                     E1000_ICH_NVM_SIG_VALUE) {
3239                         *bank = 1;
3240                         return E1000_SUCCESS;
3241                 }
3242
3243                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3244                 return -E1000_ERR_NVM;
3245         }
3246 }
3247
3248 /**
3249  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3250  *  @hw: pointer to the HW structure
3251  *  @offset: The offset (in bytes) of the word(s) to read.
3252  *  @words: Size of data to read in words
3253  *  @data: Pointer to the word(s) to read at offset.
3254  *
3255  *  Reads a word(s) from the NVM using the flash access registers.
3256  **/
3257 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3258                                   u16 *data)
3259 {
3260         struct e1000_nvm_info *nvm = &hw->nvm;
3261         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3262         u32 act_offset;
3263         s32 ret_val = E1000_SUCCESS;
3264         u32 bank = 0;
3265         u16 i, word;
3266
3267         DEBUGFUNC("e1000_read_nvm_ich8lan");
3268
3269         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3270             (words == 0)) {
3271                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3272                 ret_val = -E1000_ERR_NVM;
3273                 goto out;
3274         }
3275
3276         nvm->ops.acquire(hw);
3277
3278         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3279         if (ret_val != E1000_SUCCESS) {
3280                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3281                 bank = 0;
3282         }
3283
3284         act_offset = (bank) ? nvm->flash_bank_size : 0;
3285         act_offset += offset;
3286
3287         ret_val = E1000_SUCCESS;
3288         for (i = 0; i < words; i++) {
3289                 if (dev_spec->shadow_ram[offset+i].modified) {
3290                         data[i] = dev_spec->shadow_ram[offset+i].value;
3291                 } else {
3292                         ret_val = e1000_read_flash_word_ich8lan(hw,
3293                                                                 act_offset + i,
3294                                                                 &word);
3295                         if (ret_val)
3296                                 break;
3297                         data[i] = word;
3298                 }
3299         }
3300
3301         nvm->ops.release(hw);
3302
3303 out:
3304         if (ret_val)
3305                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3306
3307         return ret_val;
3308 }
3309
3310 /**
3311  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3312  *  @hw: pointer to the HW structure
3313  *
3314  *  This function does initial flash setup so that a new read/write/erase cycle
3315  *  can be started.
3316  **/
3317 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3318 {
3319         union ich8_hws_flash_status hsfsts;
3320         s32 ret_val = -E1000_ERR_NVM;
3321
3322         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3323
3324         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3325
3326         /* Check if the flash descriptor is valid */
3327         if (!hsfsts.hsf_status.fldesvalid) {
3328                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3329                 return -E1000_ERR_NVM;
3330         }
3331
3332         /* Clear FCERR and DAEL in hw status by writing 1 */
3333         hsfsts.hsf_status.flcerr = 1;
3334         hsfsts.hsf_status.dael = 1;
3335         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3336
3337         /* Either we should have a hardware SPI cycle in progress
3338          * bit to check against, in order to start a new cycle or
3339          * FDONE bit should be changed in the hardware so that it
3340          * is 1 after hardware reset, which can then be used as an
3341          * indication whether a cycle is in progress or has been
3342          * completed.
3343          */
3344
3345         if (!hsfsts.hsf_status.flcinprog) {
3346                 /* There is no cycle running at present,
3347                  * so we can start a cycle.
3348                  * Begin by setting Flash Cycle Done.
3349                  */
3350                 hsfsts.hsf_status.flcdone = 1;
3351                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3352                 ret_val = E1000_SUCCESS;
3353         } else {
3354                 s32 i;
3355
3356                 /* Otherwise poll for sometime so the current
3357                  * cycle has a chance to end before giving up.
3358                  */
3359                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3360                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3361                                                               ICH_FLASH_HSFSTS);
3362                         if (!hsfsts.hsf_status.flcinprog) {
3363                                 ret_val = E1000_SUCCESS;
3364                                 break;
3365                         }
3366                         usec_delay(1);
3367                 }
3368                 if (ret_val == E1000_SUCCESS) {
3369                         /* Successful in waiting for previous cycle to timeout,
3370                          * now set the Flash Cycle Done.
3371                          */
3372                         hsfsts.hsf_status.flcdone = 1;
3373                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3374                                                 hsfsts.regval);
3375                 } else {
3376                         DEBUGOUT("Flash controller busy, cannot get access\n");
3377                 }
3378         }
3379
3380         return ret_val;
3381 }
3382
3383 /**
3384  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3385  *  @hw: pointer to the HW structure
3386  *  @timeout: maximum time to wait for completion
3387  *
3388  *  This function starts a flash cycle and waits for its completion.
3389  **/
3390 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3391 {
3392         union ich8_hws_flash_ctrl hsflctl;
3393         union ich8_hws_flash_status hsfsts;
3394         u32 i = 0;
3395
3396         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3397
3398         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3399         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3400         hsflctl.hsf_ctrl.flcgo = 1;
3401
3402         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3403
3404         /* wait till FDONE bit is set to 1 */
3405         do {
3406                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3407                 if (hsfsts.hsf_status.flcdone)
3408                         break;
3409                 usec_delay(1);
3410         } while (i++ < timeout);
3411
3412         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3413                 return E1000_SUCCESS;
3414
3415         return -E1000_ERR_NVM;
3416 }
3417
3418 /**
3419  *  e1000_read_flash_word_ich8lan - Read word from flash
3420  *  @hw: pointer to the HW structure
3421  *  @offset: offset to data location
3422  *  @data: pointer to the location for storing the data
3423  *
3424  *  Reads the flash word at offset into data.  Offset is converted
3425  *  to bytes before read.
3426  **/
3427 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3428                                          u16 *data)
3429 {
3430         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3431
3432         if (!data)
3433                 return -E1000_ERR_NVM;
3434
3435         /* Must convert offset into bytes. */
3436         offset <<= 1;
3437
3438         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3439 }
3440
3441 /**
3442  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3443  *  @hw: pointer to the HW structure
3444  *  @offset: The offset of the byte to read.
3445  *  @data: Pointer to a byte to store the value read.
3446  *
3447  *  Reads a single byte from the NVM using the flash access registers.
3448  **/
3449 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3450                                          u8 *data)
3451 {
3452         s32 ret_val;
3453         u16 word = 0;
3454
3455         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3456
3457         if (ret_val)
3458                 return ret_val;
3459
3460         *data = (u8)word;
3461
3462         return E1000_SUCCESS;
3463 }
3464
3465 /**
3466  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3467  *  @hw: pointer to the HW structure
3468  *  @offset: The offset (in bytes) of the byte or word to read.
3469  *  @size: Size of data to read, 1=byte 2=word
3470  *  @data: Pointer to the word to store the value read.
3471  *
3472  *  Reads a byte or word from the NVM using the flash access registers.
3473  **/
3474 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3475                                          u8 size, u16 *data)
3476 {
3477         union ich8_hws_flash_status hsfsts;
3478         union ich8_hws_flash_ctrl hsflctl;
3479         u32 flash_linear_addr;
3480         u32 flash_data = 0;
3481         s32 ret_val = -E1000_ERR_NVM;
3482         u8 count = 0;
3483
3484         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3485
3486         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3487                 return -E1000_ERR_NVM;
3488         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3489                              hw->nvm.flash_base_addr);
3490
3491         do {
3492                 usec_delay(1);
3493                 /* Steps */
3494                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3495                 if (ret_val != E1000_SUCCESS)
3496                         break;
3497                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3498
3499                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3500                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3501                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3502                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3503
3504                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3505
3506                 ret_val =
3507                     e1000_flash_cycle_ich8lan(hw,
3508                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3509
3510                 /* Check if FCERR is set to 1, if set to 1, clear it
3511                  * and try the whole sequence a few more times, else
3512                  * read in (shift in) the Flash Data0, the order is
3513                  * least significant byte first msb to lsb
3514                  */
3515                 if (ret_val == E1000_SUCCESS) {
3516                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3517                         if (size == 1)
3518                                 *data = (u8)(flash_data & 0x000000FF);
3519                         else if (size == 2)
3520                                 *data = (u16)(flash_data & 0x0000FFFF);
3521                         break;
3522                 } else {
3523                         /* If we've gotten here, then things are probably
3524                          * completely hosed, but if the error condition is
3525                          * detected, it won't hurt to give it another try...
3526                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3527                          */
3528                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3529                                                               ICH_FLASH_HSFSTS);
3530                         if (hsfsts.hsf_status.flcerr) {
3531                                 /* Repeat for some time before giving up. */
3532                                 continue;
3533                         } else if (!hsfsts.hsf_status.flcdone) {
3534                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3535                                 break;
3536                         }
3537                 }
3538         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3539
3540         return ret_val;
3541 }
3542
3543 /**
3544  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3545  *  @hw: pointer to the HW structure
3546  *  @offset: The offset (in bytes) of the word(s) to write.
3547  *  @words: Size of data to write in words
3548  *  @data: Pointer to the word(s) to write at offset.
3549  *
3550  *  Writes a byte or word to the NVM using the flash access registers.
3551  **/
3552 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3553                                    u16 *data)
3554 {
3555         struct e1000_nvm_info *nvm = &hw->nvm;
3556         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3557         u16 i;
3558
3559         DEBUGFUNC("e1000_write_nvm_ich8lan");
3560
3561         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3562             (words == 0)) {
3563                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3564                 return -E1000_ERR_NVM;
3565         }
3566
3567         nvm->ops.acquire(hw);
3568
3569         for (i = 0; i < words; i++) {
3570                 dev_spec->shadow_ram[offset+i].modified = true;
3571                 dev_spec->shadow_ram[offset+i].value = data[i];
3572         }
3573
3574         nvm->ops.release(hw);
3575
3576         return E1000_SUCCESS;
3577 }
3578
3579 /**
3580  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3581  *  @hw: pointer to the HW structure
3582  *
3583  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3584  *  which writes the checksum to the shadow ram.  The changes in the shadow
3585  *  ram are then committed to the EEPROM by processing each bank at a time
3586  *  checking for the modified bit and writing only the pending changes.
3587  *  After a successful commit, the shadow ram is cleared and is ready for
3588  *  future writes.
3589  **/
3590 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3591 {
3592         struct e1000_nvm_info *nvm = &hw->nvm;
3593         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3594         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3595         s32 ret_val;
3596         u16 data;
3597
3598         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3599
3600         ret_val = e1000_update_nvm_checksum_generic(hw);
3601         if (ret_val)
3602                 goto out;
3603
3604         if (nvm->type != e1000_nvm_flash_sw)
3605                 goto out;
3606
3607         nvm->ops.acquire(hw);
3608
3609         /* We're writing to the opposite bank so if we're on bank 1,
3610          * write to bank 0 etc.  We also need to erase the segment that
3611          * is going to be written
3612          */
3613         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3614         if (ret_val != E1000_SUCCESS) {
3615                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3616                 bank = 0;
3617         }
3618
3619         if (bank == 0) {
3620                 new_bank_offset = nvm->flash_bank_size;
3621                 old_bank_offset = 0;
3622                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3623                 if (ret_val)
3624                         goto release;
3625         } else {
3626                 old_bank_offset = nvm->flash_bank_size;
3627                 new_bank_offset = 0;
3628                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3629                 if (ret_val)
3630                         goto release;
3631         }
3632
3633         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3634                 /* Determine whether to write the value stored
3635                  * in the other NVM bank or a modified value stored
3636                  * in the shadow RAM
3637                  */
3638                 if (dev_spec->shadow_ram[i].modified) {
3639                         data = dev_spec->shadow_ram[i].value;
3640                 } else {
3641                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3642                                                                 old_bank_offset,
3643                                                                 &data);
3644                         if (ret_val)
3645                                 break;
3646                 }
3647
3648                 /* If the word is 0x13, then make sure the signature bits
3649                  * (15:14) are 11b until the commit has completed.
3650                  * This will allow us to write 10b which indicates the
3651                  * signature is valid.  We want to do this after the write
3652                  * has completed so that we don't mark the segment valid
3653                  * while the write is still in progress
3654                  */
3655                 if (i == E1000_ICH_NVM_SIG_WORD)
3656                         data |= E1000_ICH_NVM_SIG_MASK;
3657
3658                 /* Convert offset to bytes. */
3659                 act_offset = (i + new_bank_offset) << 1;
3660
3661                 usec_delay(100);
3662                 /* Write the bytes to the new bank. */
3663                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3664                                                                act_offset,
3665                                                                (u8)data);
3666                 if (ret_val)
3667                         break;
3668
3669                 usec_delay(100);
3670                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3671                                                           act_offset + 1,
3672                                                           (u8)(data >> 8));
3673                 if (ret_val)
3674                         break;
3675         }
3676
3677         /* Don't bother writing the segment valid bits if sector
3678          * programming failed.
3679          */
3680         if (ret_val) {
3681                 DEBUGOUT("Flash commit failed.\n");
3682                 goto release;
3683         }
3684
3685         /* Finally validate the new segment by setting bit 15:14
3686          * to 10b in word 0x13 , this can be done without an
3687          * erase as well since these bits are 11 to start with
3688          * and we need to change bit 14 to 0b
3689          */
3690         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3691         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3692         if (ret_val)
3693                 goto release;
3694
3695         data &= 0xBFFF;
3696         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3697                                                        act_offset * 2 + 1,
3698                                                        (u8)(data >> 8));
3699         if (ret_val)
3700                 goto release;
3701
3702         /* And invalidate the previously valid segment by setting
3703          * its signature word (0x13) high_byte to 0b. This can be
3704          * done without an erase because flash erase sets all bits
3705          * to 1's. We can write 1's to 0's without an erase
3706          */
3707         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3708         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3709         if (ret_val)
3710                 goto release;
3711
3712         /* Great!  Everything worked, we can now clear the cached entries. */
3713         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3714                 dev_spec->shadow_ram[i].modified = false;
3715                 dev_spec->shadow_ram[i].value = 0xFFFF;
3716         }
3717
3718 release:
3719         nvm->ops.release(hw);
3720
3721         /* Reload the EEPROM, or else modifications will not appear
3722          * until after the next adapter reset.
3723          */
3724         if (!ret_val) {
3725                 nvm->ops.reload(hw);
3726                 msec_delay(10);
3727         }
3728
3729 out:
3730         if (ret_val)
3731                 DEBUGOUT1("NVM update error: %d\n", ret_val);
3732
3733         return ret_val;
3734 }
3735
3736 /**
3737  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3738  *  @hw: pointer to the HW structure
3739  *
3740  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3741  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3742  *  calculated, in which case we need to calculate the checksum and set bit 6.
3743  **/
3744 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3745 {
3746         s32 ret_val;
3747         u16 data;
3748         u16 word;
3749         u16 valid_csum_mask;
3750
3751         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3752
3753         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3754          * the checksum needs to be fixed.  This bit is an indication that
3755          * the NVM was prepared by OEM software and did not calculate
3756          * the checksum...a likely scenario.
3757          */
3758         switch (hw->mac.type) {
3759         case e1000_pch_lpt:
3760                 word = NVM_COMPAT;
3761                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3762                 break;
3763         default:
3764                 word = NVM_FUTURE_INIT_WORD1;
3765                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3766                 break;
3767         }
3768
3769         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3770         if (ret_val)
3771                 return ret_val;
3772
3773         if (!(data & valid_csum_mask)) {
3774                 data |= valid_csum_mask;
3775                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3776                 if (ret_val)
3777                         return ret_val;
3778                 ret_val = hw->nvm.ops.update(hw);
3779                 if (ret_val)
3780                         return ret_val;
3781         }
3782
3783         return e1000_validate_nvm_checksum_generic(hw);
3784 }
3785
3786 /**
3787  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3788  *  @hw: pointer to the HW structure
3789  *  @offset: The offset (in bytes) of the byte/word to read.
3790  *  @size: Size of data to read, 1=byte 2=word
3791  *  @data: The byte(s) to write to the NVM.
3792  *
3793  *  Writes one/two bytes to the NVM using the flash access registers.
3794  **/
3795 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3796                                           u8 size, u16 data)
3797 {
3798         union ich8_hws_flash_status hsfsts;
3799         union ich8_hws_flash_ctrl hsflctl;
3800         u32 flash_linear_addr;
3801         u32 flash_data = 0;
3802         s32 ret_val;
3803         u8 count = 0;
3804
3805         DEBUGFUNC("e1000_write_ich8_data");
3806
3807         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3808                 return -E1000_ERR_NVM;
3809
3810         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3811                              hw->nvm.flash_base_addr);
3812
3813         do {
3814                 usec_delay(1);
3815                 /* Steps */
3816                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3817                 if (ret_val != E1000_SUCCESS)
3818                         break;
3819                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3820
3821                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3822                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3823                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3824                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3825
3826                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3827
3828                 if (size == 1)
3829                         flash_data = (u32)data & 0x00FF;
3830                 else
3831                         flash_data = (u32)data;
3832
3833                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3834
3835                 /* check if FCERR is set to 1 , if set to 1, clear it
3836                  * and try the whole sequence a few more times else done
3837                  */
3838                 ret_val =
3839                     e1000_flash_cycle_ich8lan(hw,
3840                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3841                 if (ret_val == E1000_SUCCESS)
3842                         break;
3843
3844                 /* If we're here, then things are most likely
3845                  * completely hosed, but if the error condition
3846                  * is detected, it won't hurt to give it another
3847                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3848                  */
3849                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3850                 if (hsfsts.hsf_status.flcerr)
3851                         /* Repeat for some time before giving up. */
3852                         continue;
3853                 if (!hsfsts.hsf_status.flcdone) {
3854                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3855                         break;
3856                 }
3857         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3858
3859         return ret_val;
3860 }
3861
3862 /**
3863  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3864  *  @hw: pointer to the HW structure
3865  *  @offset: The index of the byte to read.
3866  *  @data: The byte to write to the NVM.
3867  *
3868  *  Writes a single byte to the NVM using the flash access registers.
3869  **/
3870 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3871                                           u8 data)
3872 {
3873         u16 word = (u16)data;
3874
3875         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3876
3877         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3878 }
3879
3880 /**
3881  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3882  *  @hw: pointer to the HW structure
3883  *  @offset: The offset of the byte to write.
3884  *  @byte: The byte to write to the NVM.
3885  *
3886  *  Writes a single byte to the NVM using the flash access registers.
3887  *  Goes through a retry algorithm before giving up.
3888  **/
3889 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3890                                                 u32 offset, u8 byte)
3891 {
3892         s32 ret_val;
3893         u16 program_retries;
3894
3895         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3896
3897         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3898         if (!ret_val)
3899                 return ret_val;
3900
3901         for (program_retries = 0; program_retries < 100; program_retries++) {
3902                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3903                 usec_delay(100);
3904                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3905                 if (ret_val == E1000_SUCCESS)
3906                         break;
3907         }
3908         if (program_retries == 100)
3909                 return -E1000_ERR_NVM;
3910
3911         return E1000_SUCCESS;
3912 }
3913
3914 /**
3915  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3916  *  @hw: pointer to the HW structure
3917  *  @bank: 0 for first bank, 1 for second bank, etc.
3918  *
3919  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3920  *  bank N is 4096 * N + flash_reg_addr.
3921  **/
3922 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3923 {
3924         struct e1000_nvm_info *nvm = &hw->nvm;
3925         union ich8_hws_flash_status hsfsts;
3926         union ich8_hws_flash_ctrl hsflctl;
3927         u32 flash_linear_addr;
3928         /* bank size is in 16bit words - adjust to bytes */
3929         u32 flash_bank_size = nvm->flash_bank_size * 2;
3930         s32 ret_val;
3931         s32 count = 0;
3932         s32 j, iteration, sector_size;
3933
3934         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3935
3936         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3937
3938         /* Determine HW Sector size: Read BERASE bits of hw flash status
3939          * register
3940          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3941          *     consecutive sectors.  The start index for the nth Hw sector
3942          *     can be calculated as = bank * 4096 + n * 256
3943          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3944          *     The start index for the nth Hw sector can be calculated
3945          *     as = bank * 4096
3946          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3947          *     (ich9 only, otherwise error condition)
3948          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3949          */
3950         switch (hsfsts.hsf_status.berasesz) {
3951         case 0:
3952                 /* Hw sector size 256 */
3953                 sector_size = ICH_FLASH_SEG_SIZE_256;
3954                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3955                 break;
3956         case 1:
3957                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3958                 iteration = 1;
3959                 break;
3960         case 2:
3961                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3962                 iteration = 1;
3963                 break;
3964         case 3:
3965                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3966                 iteration = 1;
3967                 break;
3968         default:
3969                 return -E1000_ERR_NVM;
3970         }
3971
3972         /* Start with the base address, then add the sector offset. */
3973         flash_linear_addr = hw->nvm.flash_base_addr;
3974         flash_linear_addr += (bank) ? flash_bank_size : 0;
3975
3976         for (j = 0; j < iteration; j++) {
3977                 do {
3978                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3979
3980                         /* Steps */
3981                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3982                         if (ret_val)
3983                                 return ret_val;
3984
3985                         /* Write a value 11 (block Erase) in Flash
3986                          * Cycle field in hw flash control
3987                          */
3988                         hsflctl.regval =
3989                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3990
3991                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3992                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3993                                                 hsflctl.regval);
3994
3995                         /* Write the last 24 bits of an index within the
3996                          * block into Flash Linear address field in Flash
3997                          * Address.
3998                          */
3999                         flash_linear_addr += (j * sector_size);
4000                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4001                                               flash_linear_addr);
4002
4003                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4004                         if (ret_val == E1000_SUCCESS)
4005                                 break;
4006
4007                         /* Check if FCERR is set to 1.  If 1,
4008                          * clear it and try the whole sequence
4009                          * a few more times else Done
4010                          */
4011                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4012                                                       ICH_FLASH_HSFSTS);
4013                         if (hsfsts.hsf_status.flcerr)
4014                                 /* repeat for some time before giving up */
4015                                 continue;
4016                         else if (!hsfsts.hsf_status.flcdone)
4017                                 return ret_val;
4018                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4019         }
4020
4021         return E1000_SUCCESS;
4022 }
4023
4024 /**
4025  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4026  *  @hw: pointer to the HW structure
4027  *  @data: Pointer to the LED settings
4028  *
4029  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4030  *  settings is all 0's or F's, set the LED default to a valid LED default
4031  *  setting.
4032  **/
4033 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4034 {
4035         s32 ret_val;
4036
4037         DEBUGFUNC("e1000_valid_led_default_ich8lan");
4038
4039         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4040         if (ret_val) {
4041                 DEBUGOUT("NVM Read Error\n");
4042                 return ret_val;
4043         }
4044
4045         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4046                 *data = ID_LED_DEFAULT_ICH8LAN;
4047
4048         return E1000_SUCCESS;
4049 }
4050
4051 /**
4052  *  e1000_id_led_init_pchlan - store LED configurations
4053  *  @hw: pointer to the HW structure
4054  *
4055  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4056  *  the PHY LED configuration register.
4057  *
4058  *  PCH also does not have an "always on" or "always off" mode which
4059  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4060  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4061  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4062  *  link based on logic in e1000_led_[on|off]_pchlan().
4063  **/
4064 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4065 {
4066         struct e1000_mac_info *mac = &hw->mac;
4067         s32 ret_val;
4068         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4069         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4070         u16 data, i, temp, shift;
4071
4072         DEBUGFUNC("e1000_id_led_init_pchlan");
4073
4074         /* Get default ID LED modes */
4075         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4076         if (ret_val)
4077                 return ret_val;
4078
4079         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4080         mac->ledctl_mode1 = mac->ledctl_default;
4081         mac->ledctl_mode2 = mac->ledctl_default;
4082
4083         for (i = 0; i < 4; i++) {
4084                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4085                 shift = (i * 5);
4086                 switch (temp) {
4087                 case ID_LED_ON1_DEF2:
4088                 case ID_LED_ON1_ON2:
4089                 case ID_LED_ON1_OFF2:
4090                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4091                         mac->ledctl_mode1 |= (ledctl_on << shift);
4092                         break;
4093                 case ID_LED_OFF1_DEF2:
4094                 case ID_LED_OFF1_ON2:
4095                 case ID_LED_OFF1_OFF2:
4096                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4097                         mac->ledctl_mode1 |= (ledctl_off << shift);
4098                         break;
4099                 default:
4100                         /* Do nothing */
4101                         break;
4102                 }
4103                 switch (temp) {
4104                 case ID_LED_DEF1_ON2:
4105                 case ID_LED_ON1_ON2:
4106                 case ID_LED_OFF1_ON2:
4107                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4108                         mac->ledctl_mode2 |= (ledctl_on << shift);
4109                         break;
4110                 case ID_LED_DEF1_OFF2:
4111                 case ID_LED_ON1_OFF2:
4112                 case ID_LED_OFF1_OFF2:
4113                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4114                         mac->ledctl_mode2 |= (ledctl_off << shift);
4115                         break;
4116                 default:
4117                         /* Do nothing */
4118                         break;
4119                 }
4120         }
4121
4122         return E1000_SUCCESS;
4123 }
4124
4125 /**
4126  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4127  *  @hw: pointer to the HW structure
4128  *
4129  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4130  *  register, so the the bus width is hard coded.
4131  **/
4132 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4133 {
4134         struct e1000_bus_info *bus = &hw->bus;
4135         s32 ret_val;
4136
4137         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4138
4139         ret_val = e1000_get_bus_info_pcie_generic(hw);
4140
4141         /* ICH devices are "PCI Express"-ish.  They have
4142          * a configuration space, but do not contain
4143          * PCI Express Capability registers, so bus width
4144          * must be hardcoded.
4145          */
4146         if (bus->width == e1000_bus_width_unknown)
4147                 bus->width = e1000_bus_width_pcie_x1;
4148
4149         return ret_val;
4150 }
4151
4152 /**
4153  *  e1000_reset_hw_ich8lan - Reset the hardware
4154  *  @hw: pointer to the HW structure
4155  *
4156  *  Does a full reset of the hardware which includes a reset of the PHY and
4157  *  MAC.
4158  **/
4159 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4160 {
4161         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4162         u16 kum_cfg;
4163         u32 ctrl, reg;
4164         s32 ret_val;
4165
4166         DEBUGFUNC("e1000_reset_hw_ich8lan");
4167
4168         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4169          * on the last TLP read/write transaction when MAC is reset.
4170          */
4171         ret_val = e1000_disable_pcie_master_generic(hw);
4172         if (ret_val)
4173                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4174
4175         DEBUGOUT("Masking off all interrupts\n");
4176         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4177
4178         /* Disable the Transmit and Receive units.  Then delay to allow
4179          * any pending transactions to complete before we hit the MAC
4180          * with the global reset.
4181          */
4182         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4183         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4184         E1000_WRITE_FLUSH(hw);
4185
4186         msec_delay(10);
4187
4188         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4189         if (hw->mac.type == e1000_ich8lan) {
4190                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4191                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4192                 /* Set Packet Buffer Size to 16k. */
4193                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4194         }
4195
4196         if (hw->mac.type == e1000_pchlan) {
4197                 /* Save the NVM K1 bit setting*/
4198                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4199                 if (ret_val)
4200                         return ret_val;
4201
4202                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4203                         dev_spec->nvm_k1_enabled = true;
4204                 else
4205                         dev_spec->nvm_k1_enabled = false;
4206         }
4207
4208         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4209
4210         if (!hw->phy.ops.check_reset_block(hw)) {
4211                 /* Full-chip reset requires MAC and PHY reset at the same
4212                  * time to make sure the interface between MAC and the
4213                  * external PHY is reset.
4214                  */
4215                 ctrl |= E1000_CTRL_PHY_RST;
4216
4217                 /* Gate automatic PHY configuration by hardware on
4218                  * non-managed 82579
4219                  */
4220                 if ((hw->mac.type == e1000_pch2lan) &&
4221                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4222                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4223         }
4224         ret_val = e1000_acquire_swflag_ich8lan(hw);
4225         DEBUGOUT("Issuing a global reset to ich8lan\n");
4226         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4227         /* cannot issue a flush here because it hangs the hardware */
4228         msec_delay(20);
4229
4230         /* Set Phy Config Counter to 50msec */
4231         if (hw->mac.type == e1000_pch2lan) {
4232                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4233                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4234                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4235                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4236         }
4237
4238         if (!ret_val)
4239                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4240
4241         if (ctrl & E1000_CTRL_PHY_RST) {
4242                 ret_val = hw->phy.ops.get_cfg_done(hw);
4243                 if (ret_val)
4244                         return ret_val;
4245
4246                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4247                 if (ret_val)
4248                         return ret_val;
4249         }
4250
4251         /* For PCH, this write will make sure that any noise
4252          * will be detected as a CRC error and be dropped rather than show up
4253          * as a bad packet to the DMA engine.
4254          */
4255         if (hw->mac.type == e1000_pchlan)
4256                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4257
4258         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4259         E1000_READ_REG(hw, E1000_ICR);
4260
4261         reg = E1000_READ_REG(hw, E1000_KABGTXD);
4262         reg |= E1000_KABGTXD_BGSQLBIAS;
4263         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4264
4265         return E1000_SUCCESS;
4266 }
4267
4268 /**
4269  *  e1000_init_hw_ich8lan - Initialize the hardware
4270  *  @hw: pointer to the HW structure
4271  *
4272  *  Prepares the hardware for transmit and receive by doing the following:
4273  *   - initialize hardware bits
4274  *   - initialize LED identification
4275  *   - setup receive address registers
4276  *   - setup flow control
4277  *   - setup transmit descriptors
4278  *   - clear statistics
4279  **/
4280 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4281 {
4282         struct e1000_mac_info *mac = &hw->mac;
4283         u32 ctrl_ext, txdctl, snoop;
4284         s32 ret_val;
4285         u16 i;
4286
4287         DEBUGFUNC("e1000_init_hw_ich8lan");
4288
4289         e1000_initialize_hw_bits_ich8lan(hw);
4290
4291         /* Initialize identification LED */
4292         ret_val = mac->ops.id_led_init(hw);
4293         /* An error is not fatal and we should not stop init due to this */
4294         if (ret_val)
4295                 DEBUGOUT("Error initializing identification LED\n");
4296
4297         /* Setup the receive address. */
4298         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4299
4300         /* Zero out the Multicast HASH table */
4301         DEBUGOUT("Zeroing the MTA\n");
4302         for (i = 0; i < mac->mta_reg_count; i++)
4303                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4304
4305         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4306          * the ME.  Disable wakeup by clearing the host wakeup bit.
4307          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4308          */
4309         if (hw->phy.type == e1000_phy_82578) {
4310                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4311                 i &= ~BM_WUC_HOST_WU_BIT;
4312                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4313                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4314                 if (ret_val)
4315                         return ret_val;
4316         }
4317
4318         /* Setup link and flow control */
4319         ret_val = mac->ops.setup_link(hw);
4320
4321         /* Set the transmit descriptor write-back policy for both queues */
4322         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4323         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4324                   E1000_TXDCTL_FULL_TX_DESC_WB);
4325         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4326                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4327         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4328         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4329         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4330                   E1000_TXDCTL_FULL_TX_DESC_WB);
4331         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4332                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4333         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4334
4335         /* ICH8 has opposite polarity of no_snoop bits.
4336          * By default, we should use snoop behavior.
4337          */
4338         if (mac->type == e1000_ich8lan)
4339                 snoop = PCIE_ICH8_SNOOP_ALL;
4340         else
4341                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4342         e1000_set_pcie_no_snoop_generic(hw, snoop);
4343
4344         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4345         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4346         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4347
4348         /* Clear all of the statistics registers (clear on read).  It is
4349          * important that we do this after we have tried to establish link
4350          * because the symbol error count will increment wildly if there
4351          * is no link.
4352          */
4353         e1000_clear_hw_cntrs_ich8lan(hw);
4354
4355         return ret_val;
4356 }
4357
4358 /**
4359  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4360  *  @hw: pointer to the HW structure
4361  *
4362  *  Sets/Clears required hardware bits necessary for correctly setting up the
4363  *  hardware for transmit and receive.
4364  **/
4365 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4366 {
4367         u32 reg;
4368
4369         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4370
4371         /* Extended Device Control */
4372         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4373         reg |= (1 << 22);
4374         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4375         if (hw->mac.type >= e1000_pchlan)
4376                 reg |= E1000_CTRL_EXT_PHYPDEN;
4377         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4378
4379         /* Transmit Descriptor Control 0 */
4380         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4381         reg |= (1 << 22);
4382         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4383
4384         /* Transmit Descriptor Control 1 */
4385         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4386         reg |= (1 << 22);
4387         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4388
4389         /* Transmit Arbitration Control 0 */
4390         reg = E1000_READ_REG(hw, E1000_TARC(0));
4391         if (hw->mac.type == e1000_ich8lan)
4392                 reg |= (1 << 28) | (1 << 29);
4393         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4394         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4395
4396         /* Transmit Arbitration Control 1 */
4397         reg = E1000_READ_REG(hw, E1000_TARC(1));
4398         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4399                 reg &= ~(1 << 28);
4400         else
4401                 reg |= (1 << 28);
4402         reg |= (1 << 24) | (1 << 26) | (1 << 30);
4403         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4404
4405         /* Device Status */
4406         if (hw->mac.type == e1000_ich8lan) {
4407                 reg = E1000_READ_REG(hw, E1000_STATUS);
4408                 reg &= ~(1 << 31);
4409                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4410         }
4411
4412         /* work-around descriptor data corruption issue during nfs v2 udp
4413          * traffic, just disable the nfs filtering capability
4414          */
4415         reg = E1000_READ_REG(hw, E1000_RFCTL);
4416         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4417
4418         /* Disable IPv6 extension header parsing because some malformed
4419          * IPv6 headers can hang the Rx.
4420          */
4421         if (hw->mac.type == e1000_ich8lan)
4422                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4423         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4424
4425         /* Enable ECC on Lynxpoint */
4426         if (hw->mac.type == e1000_pch_lpt) {
4427                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4428                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4429                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4430
4431                 reg = E1000_READ_REG(hw, E1000_CTRL);
4432                 reg |= E1000_CTRL_MEHE;
4433                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4434         }
4435
4436         return;
4437 }
4438
4439 /**
4440  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4441  *  @hw: pointer to the HW structure
4442  *
4443  *  Determines which flow control settings to use, then configures flow
4444  *  control.  Calls the appropriate media-specific link configuration
4445  *  function.  Assuming the adapter has a valid link partner, a valid link
4446  *  should be established.  Assumes the hardware has previously been reset
4447  *  and the transmitter and receiver are not enabled.
4448  **/
4449 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4450 {
4451         s32 ret_val;
4452
4453         DEBUGFUNC("e1000_setup_link_ich8lan");
4454
4455         if (hw->phy.ops.check_reset_block(hw))
4456                 return E1000_SUCCESS;
4457
4458         /* ICH parts do not have a word in the NVM to determine
4459          * the default flow control setting, so we explicitly
4460          * set it to full.
4461          */
4462         if (hw->fc.requested_mode == e1000_fc_default)
4463                 hw->fc.requested_mode = e1000_fc_full;
4464
4465         /* Save off the requested flow control mode for use later.  Depending
4466          * on the link partner's capabilities, we may or may not use this mode.
4467          */
4468         hw->fc.current_mode = hw->fc.requested_mode;
4469
4470         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4471                 hw->fc.current_mode);
4472
4473         /* Continue to configure the copper link. */
4474         ret_val = hw->mac.ops.setup_physical_interface(hw);
4475         if (ret_val)
4476                 return ret_val;
4477
4478         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4479         if ((hw->phy.type == e1000_phy_82578) ||
4480             (hw->phy.type == e1000_phy_82579) ||
4481             (hw->phy.type == e1000_phy_i217) ||
4482             (hw->phy.type == e1000_phy_82577)) {
4483                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4484
4485                 ret_val = hw->phy.ops.write_reg(hw,
4486                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
4487                                              hw->fc.pause_time);
4488                 if (ret_val)
4489                         return ret_val;
4490         }
4491
4492         return e1000_set_fc_watermarks_generic(hw);
4493 }
4494
4495 /**
4496  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4497  *  @hw: pointer to the HW structure
4498  *
4499  *  Configures the kumeran interface to the PHY to wait the appropriate time
4500  *  when polling the PHY, then call the generic setup_copper_link to finish
4501  *  configuring the copper link.
4502  **/
4503 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4504 {
4505         u32 ctrl;
4506         s32 ret_val;
4507         u16 reg_data;
4508
4509         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4510
4511         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4512         ctrl |= E1000_CTRL_SLU;
4513         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4514         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4515
4516         /* Set the mac to wait the maximum time between each iteration
4517          * and increase the max iterations when polling the phy;
4518          * this fixes erroneous timeouts at 10Mbps.
4519          */
4520         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4521                                                0xFFFF);
4522         if (ret_val)
4523                 return ret_val;
4524         ret_val = e1000_read_kmrn_reg_generic(hw,
4525                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
4526                                               &reg_data);
4527         if (ret_val)
4528                 return ret_val;
4529         reg_data |= 0x3F;
4530         ret_val = e1000_write_kmrn_reg_generic(hw,
4531                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
4532                                                reg_data);
4533         if (ret_val)
4534                 return ret_val;
4535
4536         switch (hw->phy.type) {
4537         case e1000_phy_igp_3:
4538                 ret_val = e1000_copper_link_setup_igp(hw);
4539                 if (ret_val)
4540                         return ret_val;
4541                 break;
4542         case e1000_phy_bm:
4543         case e1000_phy_82578:
4544                 ret_val = e1000_copper_link_setup_m88(hw);
4545                 if (ret_val)
4546                         return ret_val;
4547                 break;
4548         case e1000_phy_82577:
4549         case e1000_phy_82579:
4550                 ret_val = e1000_copper_link_setup_82577(hw);
4551                 if (ret_val)
4552                         return ret_val;
4553                 break;
4554         case e1000_phy_ife:
4555                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4556                                                &reg_data);
4557                 if (ret_val)
4558                         return ret_val;
4559
4560                 reg_data &= ~IFE_PMC_AUTO_MDIX;
4561
4562                 switch (hw->phy.mdix) {
4563                 case 1:
4564                         reg_data &= ~IFE_PMC_FORCE_MDIX;
4565                         break;
4566                 case 2:
4567                         reg_data |= IFE_PMC_FORCE_MDIX;
4568                         break;
4569                 case 0:
4570                 default:
4571                         reg_data |= IFE_PMC_AUTO_MDIX;
4572                         break;
4573                 }
4574                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4575                                                 reg_data);
4576                 if (ret_val)
4577                         return ret_val;
4578                 break;
4579         default:
4580                 break;
4581         }
4582
4583         return e1000_setup_copper_link_generic(hw);
4584 }
4585
4586 /**
4587  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4588  *  @hw: pointer to the HW structure
4589  *
4590  *  Calls the PHY specific link setup function and then calls the
4591  *  generic setup_copper_link to finish configuring the link for
4592  *  Lynxpoint PCH devices
4593  **/
4594 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4595 {
4596         u32 ctrl;
4597         s32 ret_val;
4598
4599         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4600
4601         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4602         ctrl |= E1000_CTRL_SLU;
4603         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4604         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4605
4606         ret_val = e1000_copper_link_setup_82577(hw);
4607         if (ret_val)
4608                 return ret_val;
4609
4610         return e1000_setup_copper_link_generic(hw);
4611 }
4612
4613 /**
4614  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4615  *  @hw: pointer to the HW structure
4616  *  @speed: pointer to store current link speed
4617  *  @duplex: pointer to store the current link duplex
4618  *
4619  *  Calls the generic get_speed_and_duplex to retrieve the current link
4620  *  information and then calls the Kumeran lock loss workaround for links at
4621  *  gigabit speeds.
4622  **/
4623 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4624                                           u16 *duplex)
4625 {
4626         s32 ret_val;
4627
4628         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4629
4630         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4631         if (ret_val)
4632                 return ret_val;
4633
4634         if ((hw->mac.type == e1000_ich8lan) &&
4635             (hw->phy.type == e1000_phy_igp_3) &&
4636             (*speed == SPEED_1000)) {
4637                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4638         }
4639
4640         return ret_val;
4641 }
4642
4643 /**
4644  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4645  *  @hw: pointer to the HW structure
4646  *
4647  *  Work-around for 82566 Kumeran PCS lock loss:
4648  *  On link status change (i.e. PCI reset, speed change) and link is up and
4649  *  speed is gigabit-
4650  *    0) if workaround is optionally disabled do nothing
4651  *    1) wait 1ms for Kumeran link to come up
4652  *    2) check Kumeran Diagnostic register PCS lock loss bit
4653  *    3) if not set the link is locked (all is good), otherwise...
4654  *    4) reset the PHY
4655  *    5) repeat up to 10 times
4656  *  Note: this is only called for IGP3 copper when speed is 1gb.
4657  **/
4658 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4659 {
4660         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4661         u32 phy_ctrl;
4662         s32 ret_val;
4663         u16 i, data;
4664         bool link;
4665
4666         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4667
4668         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4669                 return E1000_SUCCESS;
4670
4671         /* Make sure link is up before proceeding.  If not just return.
4672          * Attempting this while link is negotiating fouled up link
4673          * stability
4674          */
4675         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4676         if (!link)
4677                 return E1000_SUCCESS;
4678
4679         for (i = 0; i < 10; i++) {
4680                 /* read once to clear */
4681                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4682                 if (ret_val)
4683                         return ret_val;
4684                 /* and again to get new status */
4685                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4686                 if (ret_val)
4687                         return ret_val;
4688
4689                 /* check for PCS lock */
4690                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4691                         return E1000_SUCCESS;
4692
4693                 /* Issue PHY reset */
4694                 hw->phy.ops.reset(hw);
4695                 msec_delay_irq(5);
4696         }
4697         /* Disable GigE link negotiation */
4698         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4699         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4700                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4701         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4702
4703         /* Call gig speed drop workaround on Gig disable before accessing
4704          * any PHY registers
4705          */
4706         e1000_gig_downshift_workaround_ich8lan(hw);
4707
4708         /* unable to acquire PCS lock */
4709         return -E1000_ERR_PHY;
4710 }
4711
4712 /**
4713  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4714  *  @hw: pointer to the HW structure
4715  *  @state: boolean value used to set the current Kumeran workaround state
4716  *
4717  *  If ICH8, set the current Kumeran workaround state (enabled - true
4718  *  /disabled - false).
4719  **/
4720 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4721                                                  bool state)
4722 {
4723         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4724
4725         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4726
4727         if (hw->mac.type != e1000_ich8lan) {
4728                 DEBUGOUT("Workaround applies to ICH8 only.\n");
4729                 return;
4730         }
4731
4732         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4733
4734         return;
4735 }
4736
4737 /**
4738  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4739  *  @hw: pointer to the HW structure
4740  *
4741  *  Workaround for 82566 power-down on D3 entry:
4742  *    1) disable gigabit link
4743  *    2) write VR power-down enable
4744  *    3) read it back
4745  *  Continue if successful, else issue LCD reset and repeat
4746  **/
4747 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4748 {
4749         u32 reg;
4750         u16 data;
4751         u8  retry = 0;
4752
4753         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4754
4755         if (hw->phy.type != e1000_phy_igp_3)
4756                 return;
4757
4758         /* Try the workaround twice (if needed) */
4759         do {
4760                 /* Disable link */
4761                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4762                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4763                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4764                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4765
4766                 /* Call gig speed drop workaround on Gig disable before
4767                  * accessing any PHY registers
4768                  */
4769                 if (hw->mac.type == e1000_ich8lan)
4770                         e1000_gig_downshift_workaround_ich8lan(hw);
4771
4772                 /* Write VR power-down enable */
4773                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4774                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4775                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4776                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4777
4778                 /* Read it back and test */
4779                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4780                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4781                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4782                         break;
4783
4784                 /* Issue PHY reset and repeat at most one more time */
4785                 reg = E1000_READ_REG(hw, E1000_CTRL);
4786                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4787                 retry++;
4788         } while (retry);
4789 }
4790
4791 /**
4792  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4793  *  @hw: pointer to the HW structure
4794  *
4795  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4796  *  LPLU, Gig disable, MDIC PHY reset):
4797  *    1) Set Kumeran Near-end loopback
4798  *    2) Clear Kumeran Near-end loopback
4799  *  Should only be called for ICH8[m] devices with any 1G Phy.
4800  **/
4801 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4802 {
4803         s32 ret_val;
4804         u16 reg_data;
4805
4806         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4807
4808         if ((hw->mac.type != e1000_ich8lan) ||
4809             (hw->phy.type == e1000_phy_ife))
4810                 return;
4811
4812         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4813                                               &reg_data);
4814         if (ret_val)
4815                 return;
4816         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4817         ret_val = e1000_write_kmrn_reg_generic(hw,
4818                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
4819                                                reg_data);
4820         if (ret_val)
4821                 return;
4822         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4823         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4824                                      reg_data);
4825 }
4826
4827 /**
4828  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4829  *  @hw: pointer to the HW structure
4830  *
4831  *  During S0 to Sx transition, it is possible the link remains at gig
4832  *  instead of negotiating to a lower speed.  Before going to Sx, set
4833  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4834  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4835  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4836  *  needs to be written.
4837  *  Parts that support (and are linked to a partner which support) EEE in
4838  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4839  *  than 10Mbps w/o EEE.
4840  **/
4841 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4842 {
4843         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4844         u32 phy_ctrl;
4845         s32 ret_val;
4846
4847         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4848
4849         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4850         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4851
4852         if (hw->phy.type == e1000_phy_i217) {
4853                 u16 phy_reg, device_id = hw->device_id;
4854
4855                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4856                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4857                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4858                     (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4859                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4860
4861                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4862                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4863                 }
4864
4865                 ret_val = hw->phy.ops.acquire(hw);
4866                 if (ret_val)
4867                         goto out;
4868
4869                 if (!dev_spec->eee_disable) {
4870                         u16 eee_advert;
4871
4872                         ret_val =
4873                             e1000_read_emi_reg_locked(hw,
4874                                                       I217_EEE_ADVERTISEMENT,
4875                                                       &eee_advert);
4876                         if (ret_val)
4877                                 goto release;
4878
4879                         /* Disable LPLU if both link partners support 100BaseT
4880                          * EEE and 100Full is advertised on both ends of the
4881                          * link, and enable Auto Enable LPI since there will
4882                          * be no driver to enable LPI while in Sx.
4883                          */
4884                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4885                             (dev_spec->eee_lp_ability &
4886                              I82579_EEE_100_SUPPORTED) &&
4887                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4888                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4889                                               E1000_PHY_CTRL_NOND0A_LPLU);
4890
4891                                 /* Set Auto Enable LPI after link up */
4892                                 hw->phy.ops.read_reg_locked(hw,
4893                                                             I217_LPI_GPIO_CTRL,
4894                                                             &phy_reg);
4895                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4896                                 hw->phy.ops.write_reg_locked(hw,
4897                                                              I217_LPI_GPIO_CTRL,
4898                                                              phy_reg);
4899                         }
4900                 }
4901
4902                 /* For i217 Intel Rapid Start Technology support,
4903                  * when the system is going into Sx and no manageability engine
4904                  * is present, the driver must configure proxy to reset only on
4905                  * power good.  LPI (Low Power Idle) state must also reset only
4906                  * on power good, as well as the MTA (Multicast table array).
4907                  * The SMBus release must also be disabled on LCD reset.
4908                  */
4909                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4910                       E1000_ICH_FWSM_FW_VALID)) {
4911                         /* Enable proxy to reset only on power good. */
4912                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4913                                                     &phy_reg);
4914                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4915                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4916                                                      phy_reg);
4917
4918                         /* Set bit enable LPI (EEE) to reset only on
4919                          * power good.
4920                         */
4921                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4922                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4923                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4924
4925                         /* Disable the SMB release on LCD reset. */
4926                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4927                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4928                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4929                 }
4930
4931                 /* Enable MTA to reset for Intel Rapid Start Technology
4932                  * Support
4933                  */
4934                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4935                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4936                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4937
4938 release:
4939                 hw->phy.ops.release(hw);
4940         }
4941 out:
4942         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4943
4944         if (hw->mac.type == e1000_ich8lan)
4945                 e1000_gig_downshift_workaround_ich8lan(hw);
4946
4947         if (hw->mac.type >= e1000_pchlan) {
4948                 e1000_oem_bits_config_ich8lan(hw, false);
4949
4950                 /* Reset PHY to activate OEM bits on 82577/8 */
4951                 if (hw->mac.type == e1000_pchlan)
4952                         e1000_phy_hw_reset_generic(hw);
4953
4954                 ret_val = hw->phy.ops.acquire(hw);
4955                 if (ret_val)
4956                         return;
4957                 e1000_write_smbus_addr(hw);
4958                 hw->phy.ops.release(hw);
4959         }
4960
4961         return;
4962 }
4963
4964 /**
4965  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4966  *  @hw: pointer to the HW structure
4967  *
4968  *  During Sx to S0 transitions on non-managed devices or managed devices
4969  *  on which PHY resets are not blocked, if the PHY registers cannot be
4970  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4971  *  the PHY.
4972  *  On i217, setup Intel Rapid Start Technology.
4973  **/
4974 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4975 {
4976         s32 ret_val;
4977
4978         DEBUGFUNC("e1000_resume_workarounds_pchlan");
4979         if (hw->mac.type < e1000_pch2lan)
4980                 return E1000_SUCCESS;
4981
4982         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4983         if (ret_val) {
4984                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
4985                 return ret_val;
4986         }
4987
4988         /* For i217 Intel Rapid Start Technology support when the system
4989          * is transitioning from Sx and no manageability engine is present
4990          * configure SMBus to restore on reset, disable proxy, and enable
4991          * the reset on MTA (Multicast table array).
4992          */
4993         if (hw->phy.type == e1000_phy_i217) {
4994                 u16 phy_reg;
4995
4996                 ret_val = hw->phy.ops.acquire(hw);
4997                 if (ret_val) {
4998                         DEBUGOUT("Failed to setup iRST\n");
4999                         return ret_val;
5000                 }
5001
5002                 /* Clear Auto Enable LPI after link up */
5003                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5004                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5005                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5006
5007                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5008                     E1000_ICH_FWSM_FW_VALID)) {
5009                         /* Restore clear on SMB if no manageability engine
5010                          * is present
5011                          */
5012                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5013                                                               &phy_reg);
5014                         if (ret_val)
5015                                 goto release;
5016                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5017                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5018
5019                         /* Disable Proxy */
5020                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5021                 }
5022                 /* Enable reset on MTA */
5023                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5024                                                       &phy_reg);
5025                 if (ret_val)
5026                         goto release;
5027                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5028                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5029 release:
5030                 if (ret_val)
5031                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5032                 hw->phy.ops.release(hw);
5033                 return ret_val;
5034         }
5035         return E1000_SUCCESS;
5036 }
5037
5038 /**
5039  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5040  *  @hw: pointer to the HW structure
5041  *
5042  *  Return the LED back to the default configuration.
5043  **/
5044 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5045 {
5046         DEBUGFUNC("e1000_cleanup_led_ich8lan");
5047
5048         if (hw->phy.type == e1000_phy_ife)
5049                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5050                                              0);
5051
5052         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5053         return E1000_SUCCESS;
5054 }
5055
5056 /**
5057  *  e1000_led_on_ich8lan - Turn LEDs on
5058  *  @hw: pointer to the HW structure
5059  *
5060  *  Turn on the LEDs.
5061  **/
5062 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5063 {
5064         DEBUGFUNC("e1000_led_on_ich8lan");
5065
5066         if (hw->phy.type == e1000_phy_ife)
5067                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5068                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5069
5070         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5071         return E1000_SUCCESS;
5072 }
5073
5074 /**
5075  *  e1000_led_off_ich8lan - Turn LEDs off
5076  *  @hw: pointer to the HW structure
5077  *
5078  *  Turn off the LEDs.
5079  **/
5080 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5081 {
5082         DEBUGFUNC("e1000_led_off_ich8lan");
5083
5084         if (hw->phy.type == e1000_phy_ife)
5085                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5086                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5087
5088         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5089         return E1000_SUCCESS;
5090 }
5091
5092 /**
5093  *  e1000_setup_led_pchlan - Configures SW controllable LED
5094  *  @hw: pointer to the HW structure
5095  *
5096  *  This prepares the SW controllable LED for use.
5097  **/
5098 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5099 {
5100         DEBUGFUNC("e1000_setup_led_pchlan");
5101
5102         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5103                                      (u16)hw->mac.ledctl_mode1);
5104 }
5105
5106 /**
5107  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5108  *  @hw: pointer to the HW structure
5109  *
5110  *  Return the LED back to the default configuration.
5111  **/
5112 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5113 {
5114         DEBUGFUNC("e1000_cleanup_led_pchlan");
5115
5116         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5117                                      (u16)hw->mac.ledctl_default);
5118 }
5119
5120 /**
5121  *  e1000_led_on_pchlan - Turn LEDs on
5122  *  @hw: pointer to the HW structure
5123  *
5124  *  Turn on the LEDs.
5125  **/
5126 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5127 {
5128         u16 data = (u16)hw->mac.ledctl_mode2;
5129         u32 i, led;
5130
5131         DEBUGFUNC("e1000_led_on_pchlan");
5132
5133         /* If no link, then turn LED on by setting the invert bit
5134          * for each LED that's mode is "link_up" in ledctl_mode2.
5135          */
5136         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5137                 for (i = 0; i < 3; i++) {
5138                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5139                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5140                             E1000_LEDCTL_MODE_LINK_UP)
5141                                 continue;
5142                         if (led & E1000_PHY_LED0_IVRT)
5143                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5144                         else
5145                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5146                 }
5147         }
5148
5149         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5150 }
5151
5152 /**
5153  *  e1000_led_off_pchlan - Turn LEDs off
5154  *  @hw: pointer to the HW structure
5155  *
5156  *  Turn off the LEDs.
5157  **/
5158 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5159 {
5160         u16 data = (u16)hw->mac.ledctl_mode1;
5161         u32 i, led;
5162
5163         DEBUGFUNC("e1000_led_off_pchlan");
5164
5165         /* If no link, then turn LED off by clearing the invert bit
5166          * for each LED that's mode is "link_up" in ledctl_mode1.
5167          */
5168         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5169                 for (i = 0; i < 3; i++) {
5170                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5171                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5172                             E1000_LEDCTL_MODE_LINK_UP)
5173                                 continue;
5174                         if (led & E1000_PHY_LED0_IVRT)
5175                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5176                         else
5177                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5178                 }
5179         }
5180
5181         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5182 }
5183
5184 /**
5185  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5186  *  @hw: pointer to the HW structure
5187  *
5188  *  Read appropriate register for the config done bit for completion status
5189  *  and configure the PHY through s/w for EEPROM-less parts.
5190  *
5191  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5192  *  config done bit, so only an error is logged and continues.  If we were
5193  *  to return with error, EEPROM-less silicon would not be able to be reset
5194  *  or change link.
5195  **/
5196 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5197 {
5198         s32 ret_val = E1000_SUCCESS;
5199         u32 bank = 0;
5200         u32 status;
5201
5202         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5203
5204         e1000_get_cfg_done_generic(hw);
5205
5206         /* Wait for indication from h/w that it has completed basic config */
5207         if (hw->mac.type >= e1000_ich10lan) {
5208                 e1000_lan_init_done_ich8lan(hw);
5209         } else {
5210                 ret_val = e1000_get_auto_rd_done_generic(hw);
5211                 if (ret_val) {
5212                         /* When auto config read does not complete, do not
5213                          * return with an error. This can happen in situations
5214                          * where there is no eeprom and prevents getting link.
5215                          */
5216                         DEBUGOUT("Auto Read Done did not complete\n");
5217                         ret_val = E1000_SUCCESS;
5218                 }
5219         }
5220
5221         /* Clear PHY Reset Asserted bit */
5222         status = E1000_READ_REG(hw, E1000_STATUS);
5223         if (status & E1000_STATUS_PHYRA)
5224                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5225         else
5226                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5227
5228         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5229         if (hw->mac.type <= e1000_ich9lan) {
5230                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5231                     (hw->phy.type == e1000_phy_igp_3)) {
5232                         e1000_phy_init_script_igp3(hw);
5233                 }
5234         } else {
5235                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5236                         /* Maybe we should do a basic PHY config */
5237                         DEBUGOUT("EEPROM not present\n");
5238                         ret_val = -E1000_ERR_CONFIG;
5239                 }
5240         }
5241
5242         return ret_val;
5243 }
5244
5245 /**
5246  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5247  * @hw: pointer to the HW structure
5248  *
5249  * In the case of a PHY power down to save power, or to turn off link during a
5250  * driver unload, or wake on lan is not enabled, remove the link.
5251  **/
5252 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5253 {
5254         /* If the management interface is not enabled, then power down */
5255         if (!(hw->mac.ops.check_mng_mode(hw) ||
5256               hw->phy.ops.check_reset_block(hw)))
5257                 e1000_power_down_phy_copper(hw);
5258
5259         return;
5260 }
5261
5262 /**
5263  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5264  *  @hw: pointer to the HW structure
5265  *
5266  *  Clears hardware counters specific to the silicon family and calls
5267  *  clear_hw_cntrs_generic to clear all general purpose counters.
5268  **/
5269 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5270 {
5271         u16 phy_data;
5272         s32 ret_val;
5273
5274         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5275
5276         e1000_clear_hw_cntrs_base_generic(hw);
5277
5278         E1000_READ_REG(hw, E1000_ALGNERRC);
5279         E1000_READ_REG(hw, E1000_RXERRC);
5280         E1000_READ_REG(hw, E1000_TNCRS);
5281         E1000_READ_REG(hw, E1000_CEXTERR);
5282         E1000_READ_REG(hw, E1000_TSCTC);
5283         E1000_READ_REG(hw, E1000_TSCTFC);
5284
5285         E1000_READ_REG(hw, E1000_MGTPRC);
5286         E1000_READ_REG(hw, E1000_MGTPDC);
5287         E1000_READ_REG(hw, E1000_MGTPTC);
5288
5289         E1000_READ_REG(hw, E1000_IAC);
5290         E1000_READ_REG(hw, E1000_ICRXOC);
5291
5292         /* Clear PHY statistics registers */
5293         if ((hw->phy.type == e1000_phy_82578) ||
5294             (hw->phy.type == e1000_phy_82579) ||
5295             (hw->phy.type == e1000_phy_i217) ||
5296             (hw->phy.type == e1000_phy_82577)) {
5297                 ret_val = hw->phy.ops.acquire(hw);
5298                 if (ret_val)
5299                         return;
5300                 ret_val = hw->phy.ops.set_page(hw,
5301                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5302                 if (ret_val)
5303                         goto release;
5304                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5305                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5306                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5307                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5308                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5309                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5310                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5311                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5312                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5313                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5314                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5315                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5316                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5317                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5318 release:
5319                 hw->phy.ops.release(hw);
5320         }
5321 }
5322
5323 /**
5324  *  e1000_configure_k0s_lpt - Configure K0s power state
5325  *  @hw: pointer to the HW structure
5326  *  @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
5327  *      0 corresponds to 128ns, each value over 0 doubles the duration.
5328  *  @min_time: Minimum Tx idle period allowed  - valid values are 0 to 4.
5329  *      0 corresponds to 128ns, each value over 0 doubles the duration.
5330  *
5331  *  Configure the K1 power state based on the provided parameter.
5332  *  Assumes semaphore already acquired.
5333  *
5334  *  Success returns 0, Failure returns:
5335  *      -E1000_ERR_PHY (-2) in case of access error
5336  *      -E1000_ERR_PARAM (-4) in case of parameters error
5337  **/
5338 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
5339 {
5340         s32 ret_val;
5341         u16 kmrn_reg = 0;
5342
5343         DEBUGFUNC("e1000_configure_k0s_lpt");
5344
5345         if (entry_latency > 3 || min_time > 4)
5346                 return -E1000_ERR_PARAM;
5347
5348         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5349                                              &kmrn_reg);
5350         if (ret_val)
5351                 return ret_val;
5352
5353         /* for now don't touch the latency */
5354         kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
5355         kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
5356
5357         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5358                                               kmrn_reg);
5359         if (ret_val)
5360                 return ret_val;
5361
5362         return E1000_SUCCESS;
5363 }