1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
7 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
8 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
9 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw);
10 STATIC int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
13 * e1000_init_mac_ops_generic - Initialize MAC function pointers
14 * @hw: pointer to the HW structure
16 * Setups up the function pointers to no-op functions
18 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
20 struct e1000_mac_info *mac = &hw->mac;
21 DEBUGFUNC("e1000_init_mac_ops_generic");
24 mac->ops.init_params = e1000_null_ops_generic;
25 mac->ops.init_hw = e1000_null_ops_generic;
26 mac->ops.reset_hw = e1000_null_ops_generic;
27 mac->ops.setup_physical_interface = e1000_null_ops_generic;
28 mac->ops.get_bus_info = e1000_null_ops_generic;
29 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
30 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
31 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
32 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
34 mac->ops.cleanup_led = e1000_null_ops_generic;
35 mac->ops.setup_led = e1000_null_ops_generic;
36 mac->ops.blink_led = e1000_null_ops_generic;
37 mac->ops.led_on = e1000_null_ops_generic;
38 mac->ops.led_off = e1000_null_ops_generic;
40 mac->ops.setup_link = e1000_null_ops_generic;
41 mac->ops.get_link_up_info = e1000_null_link_info;
42 mac->ops.check_for_link = e1000_null_ops_generic;
44 mac->ops.check_mng_mode = e1000_null_mng_mode;
46 mac->ops.update_mc_addr_list = e1000_null_update_mc;
47 mac->ops.clear_vfta = e1000_null_mac_generic;
48 mac->ops.write_vfta = e1000_null_write_vfta;
49 mac->ops.rar_set = e1000_rar_set_generic;
50 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
54 * e1000_null_ops_generic - No-op function, returns 0
55 * @hw: pointer to the HW structure
57 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
59 DEBUGFUNC("e1000_null_ops_generic");
60 UNREFERENCED_1PARAMETER(hw);
65 * e1000_null_mac_generic - No-op function, return void
66 * @hw: pointer to the HW structure
68 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
70 DEBUGFUNC("e1000_null_mac_generic");
71 UNREFERENCED_1PARAMETER(hw);
76 * e1000_null_link_info - No-op function, return 0
77 * @hw: pointer to the HW structure
81 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,
82 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)
84 DEBUGFUNC("e1000_null_link_info");
85 UNREFERENCED_3PARAMETER(hw, s, d);
90 * e1000_null_mng_mode - No-op function, return false
91 * @hw: pointer to the HW structure
93 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
95 DEBUGFUNC("e1000_null_mng_mode");
96 UNREFERENCED_1PARAMETER(hw);
101 * e1000_null_update_mc - No-op function, return void
102 * @hw: pointer to the HW structure
106 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,
107 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
109 DEBUGFUNC("e1000_null_update_mc");
110 UNREFERENCED_3PARAMETER(hw, h, a);
115 * e1000_null_write_vfta - No-op function, return void
116 * @hw: pointer to the HW structure
120 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,
121 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
123 DEBUGFUNC("e1000_null_write_vfta");
124 UNREFERENCED_3PARAMETER(hw, a, b);
129 * e1000_null_rar_set - No-op function, return 0
130 * @hw: pointer to the HW structure
134 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
135 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
137 DEBUGFUNC("e1000_null_rar_set");
138 UNREFERENCED_3PARAMETER(hw, h, a);
139 return E1000_SUCCESS;
143 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
144 * @hw: pointer to the HW structure
146 * Determines and stores the system bus information for a particular
147 * network interface. The following bus information is determined and stored:
148 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
150 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
152 struct e1000_mac_info *mac = &hw->mac;
153 struct e1000_bus_info *bus = &hw->bus;
154 u32 status = E1000_READ_REG(hw, E1000_STATUS);
155 s32 ret_val = E1000_SUCCESS;
157 DEBUGFUNC("e1000_get_bus_info_pci_generic");
160 bus->type = (status & E1000_STATUS_PCIX_MODE)
161 ? e1000_bus_type_pcix
162 : e1000_bus_type_pci;
165 if (bus->type == e1000_bus_type_pci) {
166 bus->speed = (status & E1000_STATUS_PCI66)
168 : e1000_bus_speed_33;
170 switch (status & E1000_STATUS_PCIX_SPEED) {
171 case E1000_STATUS_PCIX_SPEED_66:
172 bus->speed = e1000_bus_speed_66;
174 case E1000_STATUS_PCIX_SPEED_100:
175 bus->speed = e1000_bus_speed_100;
177 case E1000_STATUS_PCIX_SPEED_133:
178 bus->speed = e1000_bus_speed_133;
181 bus->speed = e1000_bus_speed_reserved;
187 bus->width = (status & E1000_STATUS_BUS64)
189 : e1000_bus_width_32;
191 /* Which PCI(-X) function? */
192 mac->ops.set_lan_id(hw);
198 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
199 * @hw: pointer to the HW structure
201 * Determines and stores the system bus information for a particular
202 * network interface. The following bus information is determined and stored:
203 * bus speed, bus width, type (PCIe), and PCIe function.
205 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
207 struct e1000_mac_info *mac = &hw->mac;
208 struct e1000_bus_info *bus = &hw->bus;
210 u16 pcie_link_status;
212 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
214 bus->type = e1000_bus_type_pci_express;
216 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
219 bus->width = e1000_bus_width_unknown;
220 bus->speed = e1000_bus_speed_unknown;
222 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
223 case PCIE_LINK_SPEED_2500:
224 bus->speed = e1000_bus_speed_2500;
226 case PCIE_LINK_SPEED_5000:
227 bus->speed = e1000_bus_speed_5000;
230 bus->speed = e1000_bus_speed_unknown;
234 bus->width = (enum e1000_bus_width)((pcie_link_status &
235 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
238 mac->ops.set_lan_id(hw);
240 return E1000_SUCCESS;
244 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
246 * @hw: pointer to the HW structure
248 * Determines the LAN function id by reading memory-mapped registers
249 * and swaps the port value if requested.
251 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
253 struct e1000_bus_info *bus = &hw->bus;
256 /* The status register reports the correct function number
257 * for the device regardless of function swap state.
259 reg = E1000_READ_REG(hw, E1000_STATUS);
260 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
264 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
265 * @hw: pointer to the HW structure
267 * Determines the LAN function id by reading PCI config space.
269 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
271 struct e1000_bus_info *bus = &hw->bus;
275 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
276 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
277 status = E1000_READ_REG(hw, E1000_STATUS);
278 bus->func = (status & E1000_STATUS_FUNC_MASK)
279 >> E1000_STATUS_FUNC_SHIFT;
286 * e1000_set_lan_id_single_port - Set LAN id for a single port device
287 * @hw: pointer to the HW structure
289 * Sets the LAN function id to zero for a single port device.
291 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
293 struct e1000_bus_info *bus = &hw->bus;
299 * e1000_clear_vfta_generic - Clear VLAN filter table
300 * @hw: pointer to the HW structure
302 * Clears the register array which contains the VLAN filter table by
303 * setting all the values to 0.
305 void e1000_clear_vfta_generic(struct e1000_hw *hw)
309 DEBUGFUNC("e1000_clear_vfta_generic");
311 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
312 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
313 E1000_WRITE_FLUSH(hw);
318 * e1000_write_vfta_generic - Write value to VLAN filter table
319 * @hw: pointer to the HW structure
320 * @offset: register offset in VLAN filter table
321 * @value: register value written to VLAN filter table
323 * Writes value at the given offset in the register array which stores
324 * the VLAN filter table.
326 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
328 DEBUGFUNC("e1000_write_vfta_generic");
330 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
331 E1000_WRITE_FLUSH(hw);
335 * e1000_init_rx_addrs_generic - Initialize receive address's
336 * @hw: pointer to the HW structure
337 * @rar_count: receive address registers
339 * Setup the receive address registers by setting the base receive address
340 * register to the devices MAC address and clearing all the other receive
341 * address registers to 0.
343 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
346 u8 mac_addr[ETH_ADDR_LEN] = {0};
348 DEBUGFUNC("e1000_init_rx_addrs_generic");
350 /* Setup the receive address */
351 DEBUGOUT("Programming MAC Address into RAR[0]\n");
353 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
355 /* Zero out the other (rar_entry_count - 1) receive addresses */
356 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
357 for (i = 1; i < rar_count; i++)
358 hw->mac.ops.rar_set(hw, mac_addr, i);
362 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
363 * @hw: pointer to the HW structure
365 * Checks the nvm for an alternate MAC address. An alternate MAC address
366 * can be setup by pre-boot software and must be treated like a permanent
367 * address and must override the actual permanent MAC address. If an
368 * alternate MAC address is found it is programmed into RAR0, replacing
369 * the permanent address that was installed into RAR0 by the Si on reset.
370 * This function will return SUCCESS unless it encounters an error while
371 * reading the EEPROM.
373 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
377 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
378 u8 alt_mac_addr[ETH_ADDR_LEN];
380 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
382 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
386 /* not supported on older hardware or 82573 */
387 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
388 return E1000_SUCCESS;
390 /* Alternate MAC address is handled by the option ROM for 82580
391 * and newer. SW support not required.
393 if (hw->mac.type >= e1000_82580)
394 return E1000_SUCCESS;
396 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
397 &nvm_alt_mac_addr_offset);
399 DEBUGOUT("NVM Read Error\n");
403 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
404 (nvm_alt_mac_addr_offset == 0x0000))
405 /* There is no Alternate MAC Address */
406 return E1000_SUCCESS;
408 if (hw->bus.func == E1000_FUNC_1)
409 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
410 if (hw->bus.func == E1000_FUNC_2)
411 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
413 if (hw->bus.func == E1000_FUNC_3)
414 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
415 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
416 offset = nvm_alt_mac_addr_offset + (i >> 1);
417 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
419 DEBUGOUT("NVM Read Error\n");
423 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
424 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
427 /* if multicast bit is set, the alternate address will not be used */
428 if (alt_mac_addr[0] & 0x01) {
429 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
430 return E1000_SUCCESS;
433 /* We have a valid alternate MAC address, and we want to treat it the
434 * same as the normal permanent MAC address stored by the HW into the
435 * RAR. Do this by mapping this address into RAR0.
437 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
439 return E1000_SUCCESS;
443 * e1000_rar_set_generic - Set receive address register
444 * @hw: pointer to the HW structure
445 * @addr: pointer to the receive address
446 * @index: receive address array register
448 * Sets the receive address array register at index to the address passed
451 STATIC int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
453 u32 rar_low, rar_high;
455 DEBUGFUNC("e1000_rar_set_generic");
457 /* HW expects these in little endian so we reverse the byte order
458 * from network order (big endian) to little endian
460 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
461 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
463 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
465 /* If MAC address zero, no need to set the AV bit */
466 if (rar_low || rar_high)
467 rar_high |= E1000_RAH_AV;
469 /* Some bridges will combine consecutive 32-bit writes into
470 * a single burst write, which will malfunction on some parts.
471 * The flushes avoid this.
473 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
474 E1000_WRITE_FLUSH(hw);
475 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
476 E1000_WRITE_FLUSH(hw);
478 return E1000_SUCCESS;
482 * e1000_hash_mc_addr_generic - Generate a multicast hash value
483 * @hw: pointer to the HW structure
484 * @mc_addr: pointer to a multicast address
486 * Generates a multicast address hash value which is used to determine
487 * the multicast filter table array address and new table value.
489 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
491 u32 hash_value, hash_mask;
494 DEBUGFUNC("e1000_hash_mc_addr_generic");
496 /* Register count multiplied by bits per register */
497 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
499 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
500 * where 0xFF would still fall within the hash mask.
502 while (hash_mask >> bit_shift != 0xFF)
505 /* The portion of the address that is used for the hash table
506 * is determined by the mc_filter_type setting.
507 * The algorithm is such that there is a total of 8 bits of shifting.
508 * The bit_shift for a mc_filter_type of 0 represents the number of
509 * left-shifts where the MSB of mc_addr[5] would still fall within
510 * the hash_mask. Case 0 does this exactly. Since there are a total
511 * of 8 bits of shifting, then mc_addr[4] will shift right the
512 * remaining number of bits. Thus 8 - bit_shift. The rest of the
513 * cases are a variation of this algorithm...essentially raising the
514 * number of bits to shift mc_addr[5] left, while still keeping the
515 * 8-bit shifting total.
517 * For example, given the following Destination MAC Address and an
518 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
519 * we can see that the bit_shift for case 0 is 4. These are the hash
520 * values resulting from each mc_filter_type...
521 * [0] [1] [2] [3] [4] [5]
525 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
526 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
527 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
528 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
530 switch (hw->mac.mc_filter_type) {
545 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
546 (((u16) mc_addr[5]) << bit_shift)));
552 * e1000_update_mc_addr_list_generic - Update Multicast addresses
553 * @hw: pointer to the HW structure
554 * @mc_addr_list: array of multicast addresses to program
555 * @mc_addr_count: number of multicast addresses to program
557 * Updates entire Multicast Table Array.
558 * The caller must have a packed mc_addr_list of multicast addresses.
560 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
561 u8 *mc_addr_list, u32 mc_addr_count)
563 u32 hash_value, hash_bit, hash_reg;
566 DEBUGFUNC("e1000_update_mc_addr_list_generic");
568 /* clear mta_shadow */
569 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
571 /* update mta_shadow from mc_addr_list */
572 for (i = 0; (u32) i < mc_addr_count; i++) {
573 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
575 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
576 hash_bit = hash_value & 0x1F;
578 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
579 mc_addr_list += (ETH_ADDR_LEN);
582 /* replace the entire MTA table */
583 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
584 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
585 E1000_WRITE_FLUSH(hw);
589 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
590 * @hw: pointer to the HW structure
592 * In certain situations, a system BIOS may report that the PCIx maximum
593 * memory read byte count (MMRBC) value is higher than than the actual
594 * value. We check the PCIx command register with the current PCIx status
597 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
601 u16 pcix_stat_hi_word;
604 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
606 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
607 if (hw->bus.type != e1000_bus_type_pcix)
610 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
611 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
612 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
613 PCIX_COMMAND_MMRBC_SHIFT;
614 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
615 PCIX_STATUS_HI_MMRBC_SHIFT;
616 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
617 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
618 if (cmd_mmrbc > stat_mmrbc) {
619 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
620 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
621 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
626 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
627 * @hw: pointer to the HW structure
629 * Clears the base hardware counters by reading the counter registers.
631 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
633 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
635 E1000_READ_REG(hw, E1000_CRCERRS);
636 E1000_READ_REG(hw, E1000_SYMERRS);
637 E1000_READ_REG(hw, E1000_MPC);
638 E1000_READ_REG(hw, E1000_SCC);
639 E1000_READ_REG(hw, E1000_ECOL);
640 E1000_READ_REG(hw, E1000_MCC);
641 E1000_READ_REG(hw, E1000_LATECOL);
642 E1000_READ_REG(hw, E1000_COLC);
643 E1000_READ_REG(hw, E1000_DC);
644 E1000_READ_REG(hw, E1000_SEC);
645 E1000_READ_REG(hw, E1000_RLEC);
646 E1000_READ_REG(hw, E1000_XONRXC);
647 E1000_READ_REG(hw, E1000_XONTXC);
648 E1000_READ_REG(hw, E1000_XOFFRXC);
649 E1000_READ_REG(hw, E1000_XOFFTXC);
650 E1000_READ_REG(hw, E1000_FCRUC);
651 E1000_READ_REG(hw, E1000_GPRC);
652 E1000_READ_REG(hw, E1000_BPRC);
653 E1000_READ_REG(hw, E1000_MPRC);
654 E1000_READ_REG(hw, E1000_GPTC);
655 E1000_READ_REG(hw, E1000_GORCL);
656 E1000_READ_REG(hw, E1000_GORCH);
657 E1000_READ_REG(hw, E1000_GOTCL);
658 E1000_READ_REG(hw, E1000_GOTCH);
659 E1000_READ_REG(hw, E1000_RNBC);
660 E1000_READ_REG(hw, E1000_RUC);
661 E1000_READ_REG(hw, E1000_RFC);
662 E1000_READ_REG(hw, E1000_ROC);
663 E1000_READ_REG(hw, E1000_RJC);
664 E1000_READ_REG(hw, E1000_TORL);
665 E1000_READ_REG(hw, E1000_TORH);
666 E1000_READ_REG(hw, E1000_TOTL);
667 E1000_READ_REG(hw, E1000_TOTH);
668 E1000_READ_REG(hw, E1000_TPR);
669 E1000_READ_REG(hw, E1000_TPT);
670 E1000_READ_REG(hw, E1000_MPTC);
671 E1000_READ_REG(hw, E1000_BPTC);
675 * e1000_check_for_copper_link_generic - Check for link (Copper)
676 * @hw: pointer to the HW structure
678 * Checks to see of the link status of the hardware has changed. If a
679 * change in link status has been detected, then we read the PHY registers
680 * to get the current speed/duplex if link exists.
682 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
684 struct e1000_mac_info *mac = &hw->mac;
688 DEBUGFUNC("e1000_check_for_copper_link");
690 /* We only want to go out to the PHY registers to see if Auto-Neg
691 * has completed and/or if our link status has changed. The
692 * get_link_status flag is set upon receiving a Link Status
693 * Change or Rx Sequence Error interrupt.
695 if (!mac->get_link_status)
696 return E1000_SUCCESS;
698 /* First we want to see if the MII Status Register reports
699 * link. If so, then we want to get the current speed/duplex
702 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
707 return E1000_SUCCESS; /* No link detected */
709 mac->get_link_status = false;
711 /* Check if there was DownShift, must be checked
712 * immediately after link-up
714 e1000_check_downshift_generic(hw);
716 /* If we are forcing speed/duplex, then we simply return since
717 * we have already determined whether we have link or not.
720 return -E1000_ERR_CONFIG;
722 /* Auto-Neg is enabled. Auto Speed Detection takes care
723 * of MAC speed/duplex configuration. So we only need to
724 * configure Collision Distance in the MAC.
726 mac->ops.config_collision_dist(hw);
728 /* Configure Flow Control now that Auto-Neg has completed.
729 * First, we need to restore the desired flow control
730 * settings because we may have had to re-autoneg with a
731 * different link partner.
733 ret_val = e1000_config_fc_after_link_up_generic(hw);
735 DEBUGOUT("Error configuring flow control\n");
741 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
742 * @hw: pointer to the HW structure
744 * Checks for link up on the hardware. If link is not up and we have
745 * a signal, then we need to force link up.
747 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
749 struct e1000_mac_info *mac = &hw->mac;
755 DEBUGFUNC("e1000_check_for_fiber_link_generic");
757 ctrl = E1000_READ_REG(hw, E1000_CTRL);
758 status = E1000_READ_REG(hw, E1000_STATUS);
759 rxcw = E1000_READ_REG(hw, E1000_RXCW);
761 /* If we don't have link (auto-negotiation failed or link partner
762 * cannot auto-negotiate), the cable is plugged in (we have signal),
763 * and our link partner is not trying to auto-negotiate with us (we
764 * are receiving idles or data), we need to force link up. We also
765 * need to give auto-negotiation time to complete, in case the cable
766 * was just plugged in. The autoneg_failed flag does this.
768 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
769 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
770 !(rxcw & E1000_RXCW_C)) {
771 if (!mac->autoneg_failed) {
772 mac->autoneg_failed = true;
773 return E1000_SUCCESS;
775 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
777 /* Disable auto-negotiation in the TXCW register */
778 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
780 /* Force link-up and also force full-duplex. */
781 ctrl = E1000_READ_REG(hw, E1000_CTRL);
782 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
783 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
785 /* Configure Flow Control after forcing link up. */
786 ret_val = e1000_config_fc_after_link_up_generic(hw);
788 DEBUGOUT("Error configuring flow control\n");
791 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
792 /* If we are forcing link and we are receiving /C/ ordered
793 * sets, re-enable auto-negotiation in the TXCW register
794 * and disable forced link in the Device Control register
795 * in an attempt to auto-negotiate with our link partner.
797 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
798 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
799 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
801 mac->serdes_has_link = true;
804 return E1000_SUCCESS;
808 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
809 * @hw: pointer to the HW structure
811 * Checks for link up on the hardware. If link is not up and we have
812 * a signal, then we need to force link up.
814 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
816 struct e1000_mac_info *mac = &hw->mac;
822 DEBUGFUNC("e1000_check_for_serdes_link_generic");
824 ctrl = E1000_READ_REG(hw, E1000_CTRL);
825 status = E1000_READ_REG(hw, E1000_STATUS);
826 rxcw = E1000_READ_REG(hw, E1000_RXCW);
828 /* If we don't have link (auto-negotiation failed or link partner
829 * cannot auto-negotiate), and our link partner is not trying to
830 * auto-negotiate with us (we are receiving idles or data),
831 * we need to force link up. We also need to give auto-negotiation
834 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
835 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
836 if (!mac->autoneg_failed) {
837 mac->autoneg_failed = true;
838 return E1000_SUCCESS;
840 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
842 /* Disable auto-negotiation in the TXCW register */
843 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
845 /* Force link-up and also force full-duplex. */
846 ctrl = E1000_READ_REG(hw, E1000_CTRL);
847 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
848 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
850 /* Configure Flow Control after forcing link up. */
851 ret_val = e1000_config_fc_after_link_up_generic(hw);
853 DEBUGOUT("Error configuring flow control\n");
856 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
857 /* If we are forcing link and we are receiving /C/ ordered
858 * sets, re-enable auto-negotiation in the TXCW register
859 * and disable forced link in the Device Control register
860 * in an attempt to auto-negotiate with our link partner.
862 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
863 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
864 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
866 mac->serdes_has_link = true;
867 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
868 /* If we force link for non-auto-negotiation switch, check
869 * link status based on MAC synchronization for internal
872 /* SYNCH bit and IV bit are sticky. */
874 rxcw = E1000_READ_REG(hw, E1000_RXCW);
875 if (rxcw & E1000_RXCW_SYNCH) {
876 if (!(rxcw & E1000_RXCW_IV)) {
877 mac->serdes_has_link = true;
878 DEBUGOUT("SERDES: Link up - forced.\n");
881 mac->serdes_has_link = false;
882 DEBUGOUT("SERDES: Link down - force failed.\n");
886 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
887 status = E1000_READ_REG(hw, E1000_STATUS);
888 if (status & E1000_STATUS_LU) {
889 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
891 rxcw = E1000_READ_REG(hw, E1000_RXCW);
892 if (rxcw & E1000_RXCW_SYNCH) {
893 if (!(rxcw & E1000_RXCW_IV)) {
894 mac->serdes_has_link = true;
895 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
897 mac->serdes_has_link = false;
898 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
901 mac->serdes_has_link = false;
902 DEBUGOUT("SERDES: Link down - no sync.\n");
905 mac->serdes_has_link = false;
906 DEBUGOUT("SERDES: Link down - autoneg failed\n");
910 return E1000_SUCCESS;
914 * e1000_set_default_fc_generic - Set flow control default values
915 * @hw: pointer to the HW structure
917 * Read the EEPROM for the default values for flow control and store the
920 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
926 DEBUGFUNC("e1000_set_default_fc_generic");
928 /* Read and store word 0x0F of the EEPROM. This word contains bits
929 * that determine the hardware's default PAUSE (flow control) mode,
930 * a bit that determines whether the HW defaults to enabling or
931 * disabling auto-negotiation, and the direction of the
932 * SW defined pins. If there is no SW over-ride of the flow
933 * control setting, then the variable hw->fc will
934 * be initialized based on a value in the EEPROM.
936 if (hw->mac.type == e1000_i350) {
937 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
938 ret_val = hw->nvm.ops.read(hw,
939 NVM_INIT_CONTROL2_REG +
943 ret_val = hw->nvm.ops.read(hw,
944 NVM_INIT_CONTROL2_REG,
950 DEBUGOUT("NVM Read Error\n");
954 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
955 hw->fc.requested_mode = e1000_fc_none;
956 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
958 hw->fc.requested_mode = e1000_fc_tx_pause;
960 hw->fc.requested_mode = e1000_fc_full;
962 return E1000_SUCCESS;
966 * e1000_setup_link_generic - Setup flow control and link settings
967 * @hw: pointer to the HW structure
969 * Determines which flow control settings to use, then configures flow
970 * control. Calls the appropriate media-specific link configuration
971 * function. Assuming the adapter has a valid link partner, a valid link
972 * should be established. Assumes the hardware has previously been reset
973 * and the transmitter and receiver are not enabled.
975 s32 e1000_setup_link_generic(struct e1000_hw *hw)
979 DEBUGFUNC("e1000_setup_link_generic");
981 /* In the case of the phy reset being blocked, we already have a link.
982 * We do not need to set it up again.
984 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
985 return E1000_SUCCESS;
987 /* If requested flow control is set to default, set flow control
988 * based on the EEPROM flow control settings.
990 if (hw->fc.requested_mode == e1000_fc_default) {
991 ret_val = e1000_set_default_fc_generic(hw);
996 /* Save off the requested flow control mode for use later. Depending
997 * on the link partner's capabilities, we may or may not use this mode.
999 hw->fc.current_mode = hw->fc.requested_mode;
1001 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1002 hw->fc.current_mode);
1004 /* Call the necessary media_type subroutine to configure the link. */
1005 ret_val = hw->mac.ops.setup_physical_interface(hw);
1009 /* Initialize the flow control address, type, and PAUSE timer
1010 * registers to their default values. This is done even if flow
1011 * control is disabled, because it does not hurt anything to
1012 * initialize these registers.
1014 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1015 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1016 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1017 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1019 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1021 return e1000_set_fc_watermarks_generic(hw);
1025 * e1000_commit_fc_settings_generic - Configure flow control
1026 * @hw: pointer to the HW structure
1028 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1029 * base on the flow control settings in e1000_mac_info.
1031 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1033 struct e1000_mac_info *mac = &hw->mac;
1036 DEBUGFUNC("e1000_commit_fc_settings_generic");
1038 /* Check for a software override of the flow control settings, and
1039 * setup the device accordingly. If auto-negotiation is enabled, then
1040 * software will have to set the "PAUSE" bits to the correct value in
1041 * the Transmit Config Word Register (TXCW) and re-start auto-
1042 * negotiation. However, if auto-negotiation is disabled, then
1043 * software will have to manually configure the two flow control enable
1044 * bits in the CTRL register.
1046 * The possible values of the "fc" parameter are:
1047 * 0: Flow control is completely disabled
1048 * 1: Rx flow control is enabled (we can receive pause frames,
1049 * but not send pause frames).
1050 * 2: Tx flow control is enabled (we can send pause frames but we
1051 * do not support receiving pause frames).
1052 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1054 switch (hw->fc.current_mode) {
1056 /* Flow control completely disabled by a software over-ride. */
1057 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1059 case e1000_fc_rx_pause:
1060 /* Rx Flow control is enabled and Tx Flow control is disabled
1061 * by a software over-ride. Since there really isn't a way to
1062 * advertise that we are capable of Rx Pause ONLY, we will
1063 * advertise that we support both symmetric and asymmetric Rx
1064 * PAUSE. Later, we will disable the adapter's ability to send
1067 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1069 case e1000_fc_tx_pause:
1070 /* Tx Flow control is enabled, and Rx Flow control is disabled,
1071 * by a software over-ride.
1073 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1076 /* Flow control (both Rx and Tx) is enabled by a software
1079 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1082 DEBUGOUT("Flow control param set incorrectly\n");
1083 return -E1000_ERR_CONFIG;
1087 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1090 return E1000_SUCCESS;
1094 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1095 * @hw: pointer to the HW structure
1097 * Polls for link up by reading the status register, if link fails to come
1098 * up with auto-negotiation, then the link is forced if a signal is detected.
1100 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1102 struct e1000_mac_info *mac = &hw->mac;
1106 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1108 /* If we have a signal (the cable is plugged in, or assumed true for
1109 * serdes media) then poll for a "Link-Up" indication in the Device
1110 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1111 * seconds (Auto-negotiation should complete in less than 500
1112 * milliseconds even if the other end is doing it in SW).
1114 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1116 status = E1000_READ_REG(hw, E1000_STATUS);
1117 if (status & E1000_STATUS_LU)
1120 if (i == FIBER_LINK_UP_LIMIT) {
1121 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1122 mac->autoneg_failed = true;
1123 /* AutoNeg failed to achieve a link, so we'll call
1124 * mac->check_for_link. This routine will force the
1125 * link up if we detect a signal. This will allow us to
1126 * communicate with non-autonegotiating link partners.
1128 ret_val = mac->ops.check_for_link(hw);
1130 DEBUGOUT("Error while checking for link\n");
1133 mac->autoneg_failed = false;
1135 mac->autoneg_failed = false;
1136 DEBUGOUT("Valid Link Found\n");
1139 return E1000_SUCCESS;
1143 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1144 * @hw: pointer to the HW structure
1146 * Configures collision distance and flow control for fiber and serdes
1147 * links. Upon successful setup, poll for link.
1149 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1154 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1156 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1158 /* Take the link out of reset */
1159 ctrl &= ~E1000_CTRL_LRST;
1161 hw->mac.ops.config_collision_dist(hw);
1163 ret_val = e1000_commit_fc_settings_generic(hw);
1167 /* Since auto-negotiation is enabled, take the link out of reset (the
1168 * link will be in reset, because we previously reset the chip). This
1169 * will restart auto-negotiation. If auto-negotiation is successful
1170 * then the link-up status bit will be set and the flow control enable
1171 * bits (RFCE and TFCE) will be set according to their negotiated value.
1173 DEBUGOUT("Auto-negotiation enabled\n");
1175 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1176 E1000_WRITE_FLUSH(hw);
1179 /* For these adapters, the SW definable pin 1 is set when the optics
1180 * detect a signal. If we have a signal, then poll for a "Link-Up"
1183 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1184 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1185 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1187 DEBUGOUT("No signal detected\n");
1194 * e1000_config_collision_dist_generic - Configure collision distance
1195 * @hw: pointer to the HW structure
1197 * Configures the collision distance to the default value and is used
1198 * during link setup.
1200 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1204 DEBUGFUNC("e1000_config_collision_dist_generic");
1206 tctl = E1000_READ_REG(hw, E1000_TCTL);
1208 tctl &= ~E1000_TCTL_COLD;
1209 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1211 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1212 E1000_WRITE_FLUSH(hw);
1216 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1217 * @hw: pointer to the HW structure
1219 * Sets the flow control high/low threshold (watermark) registers. If
1220 * flow control XON frame transmission is enabled, then set XON frame
1221 * transmission as well.
1223 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1225 u32 fcrtl = 0, fcrth = 0;
1227 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1229 /* Set the flow control receive threshold registers. Normally,
1230 * these registers will be set to a default threshold that may be
1231 * adjusted later by the driver's runtime code. However, if the
1232 * ability to transmit pause frames is not enabled, then these
1233 * registers will be set to 0.
1235 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1236 /* We need to set up the Receive Threshold high and low water
1237 * marks as well as (optionally) enabling the transmission of
1240 fcrtl = hw->fc.low_water;
1241 if (hw->fc.send_xon)
1242 fcrtl |= E1000_FCRTL_XONE;
1244 fcrth = hw->fc.high_water;
1246 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1247 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1249 return E1000_SUCCESS;
1253 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1254 * @hw: pointer to the HW structure
1256 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1257 * device control register to reflect the adapter settings. TFCE and RFCE
1258 * need to be explicitly set by software when a copper PHY is used because
1259 * autonegotiation is managed by the PHY rather than the MAC. Software must
1260 * also configure these bits when link is forced on a fiber connection.
1262 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1266 DEBUGFUNC("e1000_force_mac_fc_generic");
1268 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1270 /* Because we didn't get link via the internal auto-negotiation
1271 * mechanism (we either forced link or we got link via PHY
1272 * auto-neg), we have to manually enable/disable transmit an
1273 * receive flow control.
1275 * The "Case" statement below enables/disable flow control
1276 * according to the "hw->fc.current_mode" parameter.
1278 * The possible values of the "fc" parameter are:
1279 * 0: Flow control is completely disabled
1280 * 1: Rx flow control is enabled (we can receive pause
1281 * frames but not send pause frames).
1282 * 2: Tx flow control is enabled (we can send pause frames
1283 * frames but we do not receive pause frames).
1284 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1285 * other: No other values should be possible at this point.
1287 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1289 switch (hw->fc.current_mode) {
1291 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1293 case e1000_fc_rx_pause:
1294 ctrl &= (~E1000_CTRL_TFCE);
1295 ctrl |= E1000_CTRL_RFCE;
1297 case e1000_fc_tx_pause:
1298 ctrl &= (~E1000_CTRL_RFCE);
1299 ctrl |= E1000_CTRL_TFCE;
1302 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1305 DEBUGOUT("Flow control param set incorrectly\n");
1306 return -E1000_ERR_CONFIG;
1309 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1311 return E1000_SUCCESS;
1315 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1316 * @hw: pointer to the HW structure
1318 * Checks the status of auto-negotiation after link up to ensure that the
1319 * speed and duplex were not forced. If the link needed to be forced, then
1320 * flow control needs to be forced also. If auto-negotiation is enabled
1321 * and did not fail, then we configure flow control based on our link
1324 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1326 struct e1000_mac_info *mac = &hw->mac;
1327 s32 ret_val = E1000_SUCCESS;
1328 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1329 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1332 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1334 /* Check for the case where we have fiber media and auto-neg failed
1335 * so we had to force link. In this case, we need to force the
1336 * configuration of the MAC to match the "fc" parameter.
1338 if (mac->autoneg_failed) {
1339 if (hw->phy.media_type == e1000_media_type_fiber ||
1340 hw->phy.media_type == e1000_media_type_internal_serdes)
1341 ret_val = e1000_force_mac_fc_generic(hw);
1343 if (hw->phy.media_type == e1000_media_type_copper)
1344 ret_val = e1000_force_mac_fc_generic(hw);
1348 DEBUGOUT("Error forcing flow control settings\n");
1352 /* Check for the case where we have copper media and auto-neg is
1353 * enabled. In this case, we need to check and see if Auto-Neg
1354 * has completed, and if so, how the PHY and link partner has
1355 * flow control configured.
1357 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1358 /* Read the MII Status Register and check to see if AutoNeg
1359 * has completed. We read this twice because this reg has
1360 * some "sticky" (latched) bits.
1362 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1365 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1369 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1370 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1374 /* The AutoNeg process has completed, so we now need to
1375 * read both the Auto Negotiation Advertisement
1376 * Register (Address 4) and the Auto_Negotiation Base
1377 * Page Ability Register (Address 5) to determine how
1378 * flow control was negotiated.
1380 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1384 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1385 &mii_nway_lp_ability_reg);
1389 /* Two bits in the Auto Negotiation Advertisement Register
1390 * (Address 4) and two bits in the Auto Negotiation Base
1391 * Page Ability Register (Address 5) determine flow control
1392 * for both the PHY and the link partner. The following
1393 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1394 * 1999, describes these PAUSE resolution bits and how flow
1395 * control is determined based upon these settings.
1396 * NOTE: DC = Don't Care
1398 * LOCAL DEVICE | LINK PARTNER
1399 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1400 *-------|---------|-------|---------|--------------------
1401 * 0 | 0 | DC | DC | e1000_fc_none
1402 * 0 | 1 | 0 | DC | e1000_fc_none
1403 * 0 | 1 | 1 | 0 | e1000_fc_none
1404 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1405 * 1 | 0 | 0 | DC | e1000_fc_none
1406 * 1 | DC | 1 | DC | e1000_fc_full
1407 * 1 | 1 | 0 | 0 | e1000_fc_none
1408 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1410 * Are both PAUSE bits set to 1? If so, this implies
1411 * Symmetric Flow Control is enabled at both ends. The
1412 * ASM_DIR bits are irrelevant per the spec.
1414 * For Symmetric Flow Control:
1416 * LOCAL DEVICE | LINK PARTNER
1417 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1418 *-------|---------|-------|---------|--------------------
1419 * 1 | DC | 1 | DC | E1000_fc_full
1422 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1423 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1424 /* Now we need to check if the user selected Rx ONLY
1425 * of pause frames. In this case, we had to advertise
1426 * FULL flow control because we could not advertise Rx
1427 * ONLY. Hence, we must now check to see if we need to
1428 * turn OFF the TRANSMISSION of PAUSE frames.
1430 if (hw->fc.requested_mode == e1000_fc_full) {
1431 hw->fc.current_mode = e1000_fc_full;
1432 DEBUGOUT("Flow Control = FULL.\n");
1434 hw->fc.current_mode = e1000_fc_rx_pause;
1435 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1438 /* For receiving PAUSE frames ONLY.
1440 * LOCAL DEVICE | LINK PARTNER
1441 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1442 *-------|---------|-------|---------|--------------------
1443 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1445 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1446 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1447 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1448 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1449 hw->fc.current_mode = e1000_fc_tx_pause;
1450 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1452 /* For transmitting PAUSE frames ONLY.
1454 * LOCAL DEVICE | LINK PARTNER
1455 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1456 *-------|---------|-------|---------|--------------------
1457 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1459 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1460 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1461 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1462 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1463 hw->fc.current_mode = e1000_fc_rx_pause;
1464 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1466 /* Per the IEEE spec, at this point flow control
1467 * should be disabled.
1469 hw->fc.current_mode = e1000_fc_none;
1470 DEBUGOUT("Flow Control = NONE.\n");
1473 /* Now we need to do one last check... If we auto-
1474 * negotiated to HALF DUPLEX, flow control should not be
1475 * enabled per IEEE 802.3 spec.
1477 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1479 DEBUGOUT("Error getting link speed and duplex\n");
1483 if (duplex == HALF_DUPLEX)
1484 hw->fc.current_mode = e1000_fc_none;
1486 /* Now we call a subroutine to actually force the MAC
1487 * controller to use the correct flow control settings.
1489 ret_val = e1000_force_mac_fc_generic(hw);
1491 DEBUGOUT("Error forcing flow control settings\n");
1496 /* Check for the case where we have SerDes media and auto-neg is
1497 * enabled. In this case, we need to check and see if Auto-Neg
1498 * has completed, and if so, how the PHY and link partner has
1499 * flow control configured.
1501 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1503 /* Read the PCS_LSTS and check to see if AutoNeg
1506 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1508 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1509 DEBUGOUT("PCS Auto Neg has not completed.\n");
1513 /* The AutoNeg process has completed, so we now need to
1514 * read both the Auto Negotiation Advertisement
1515 * Register (PCS_ANADV) and the Auto_Negotiation Base
1516 * Page Ability Register (PCS_LPAB) to determine how
1517 * flow control was negotiated.
1519 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1520 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1522 /* Two bits in the Auto Negotiation Advertisement Register
1523 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1524 * Page Ability Register (PCS_LPAB) determine flow control
1525 * for both the PHY and the link partner. The following
1526 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1527 * 1999, describes these PAUSE resolution bits and how flow
1528 * control is determined based upon these settings.
1529 * NOTE: DC = Don't Care
1531 * LOCAL DEVICE | LINK PARTNER
1532 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1533 *-------|---------|-------|---------|--------------------
1534 * 0 | 0 | DC | DC | e1000_fc_none
1535 * 0 | 1 | 0 | DC | e1000_fc_none
1536 * 0 | 1 | 1 | 0 | e1000_fc_none
1537 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1538 * 1 | 0 | 0 | DC | e1000_fc_none
1539 * 1 | DC | 1 | DC | e1000_fc_full
1540 * 1 | 1 | 0 | 0 | e1000_fc_none
1541 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1543 * Are both PAUSE bits set to 1? If so, this implies
1544 * Symmetric Flow Control is enabled at both ends. The
1545 * ASM_DIR bits are irrelevant per the spec.
1547 * For Symmetric Flow Control:
1549 * LOCAL DEVICE | LINK PARTNER
1550 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1551 *-------|---------|-------|---------|--------------------
1552 * 1 | DC | 1 | DC | e1000_fc_full
1555 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1556 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1557 /* Now we need to check if the user selected Rx ONLY
1558 * of pause frames. In this case, we had to advertise
1559 * FULL flow control because we could not advertise Rx
1560 * ONLY. Hence, we must now check to see if we need to
1561 * turn OFF the TRANSMISSION of PAUSE frames.
1563 if (hw->fc.requested_mode == e1000_fc_full) {
1564 hw->fc.current_mode = e1000_fc_full;
1565 DEBUGOUT("Flow Control = FULL.\n");
1567 hw->fc.current_mode = e1000_fc_rx_pause;
1568 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1571 /* For receiving PAUSE frames ONLY.
1573 * LOCAL DEVICE | LINK PARTNER
1574 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1575 *-------|---------|-------|---------|--------------------
1576 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1578 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1579 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1580 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1581 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1582 hw->fc.current_mode = e1000_fc_tx_pause;
1583 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1585 /* For transmitting PAUSE frames ONLY.
1587 * LOCAL DEVICE | LINK PARTNER
1588 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1589 *-------|---------|-------|---------|--------------------
1590 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1592 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1593 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1594 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1595 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1596 hw->fc.current_mode = e1000_fc_rx_pause;
1597 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1599 /* Per the IEEE spec, at this point flow control
1600 * should be disabled.
1602 hw->fc.current_mode = e1000_fc_none;
1603 DEBUGOUT("Flow Control = NONE.\n");
1606 /* Now we call a subroutine to actually force the MAC
1607 * controller to use the correct flow control settings.
1609 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1610 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1611 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1613 ret_val = e1000_force_mac_fc_generic(hw);
1615 DEBUGOUT("Error forcing flow control settings\n");
1620 return E1000_SUCCESS;
1624 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1625 * @hw: pointer to the HW structure
1626 * @speed: stores the current speed
1627 * @duplex: stores the current duplex
1629 * Read the status register for the current speed/duplex and store the current
1630 * speed and duplex for copper connections.
1632 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1637 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1639 status = E1000_READ_REG(hw, E1000_STATUS);
1640 if (status & E1000_STATUS_SPEED_1000) {
1641 *speed = SPEED_1000;
1642 DEBUGOUT("1000 Mbs, ");
1643 } else if (status & E1000_STATUS_SPEED_100) {
1645 DEBUGOUT("100 Mbs, ");
1648 DEBUGOUT("10 Mbs, ");
1651 if (status & E1000_STATUS_FD) {
1652 *duplex = FULL_DUPLEX;
1653 DEBUGOUT("Full Duplex\n");
1655 *duplex = HALF_DUPLEX;
1656 DEBUGOUT("Half Duplex\n");
1659 return E1000_SUCCESS;
1663 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1664 * @hw: pointer to the HW structure
1665 * @speed: stores the current speed
1666 * @duplex: stores the current duplex
1668 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1669 * for fiber/serdes links.
1671 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,
1672 u16 *speed, u16 *duplex)
1674 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1675 UNREFERENCED_1PARAMETER(hw);
1677 *speed = SPEED_1000;
1678 *duplex = FULL_DUPLEX;
1680 return E1000_SUCCESS;
1684 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1685 * @hw: pointer to the HW structure
1687 * Acquire the HW semaphore to access the PHY or NVM
1689 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1692 s32 timeout = hw->nvm.word_size + 1;
1695 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1697 /* Get the SW semaphore */
1698 while (i < timeout) {
1699 swsm = E1000_READ_REG(hw, E1000_SWSM);
1700 if (!(swsm & E1000_SWSM_SMBI))
1708 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1709 return -E1000_ERR_NVM;
1712 /* Get the FW semaphore. */
1713 for (i = 0; i < timeout; i++) {
1714 swsm = E1000_READ_REG(hw, E1000_SWSM);
1715 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1717 /* Semaphore acquired if bit latched */
1718 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1725 /* Release semaphores */
1726 e1000_put_hw_semaphore_generic(hw);
1727 DEBUGOUT("Driver can't access the NVM\n");
1728 return -E1000_ERR_NVM;
1731 return E1000_SUCCESS;
1735 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1736 * @hw: pointer to the HW structure
1738 * Release hardware semaphore used to access the PHY or NVM
1740 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1744 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1746 swsm = E1000_READ_REG(hw, E1000_SWSM);
1748 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1750 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1754 * e1000_get_auto_rd_done_generic - Check for auto read completion
1755 * @hw: pointer to the HW structure
1757 * Check EEPROM for Auto Read done bit.
1759 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1763 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1765 while (i < AUTO_READ_DONE_TIMEOUT) {
1766 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1772 if (i == AUTO_READ_DONE_TIMEOUT) {
1773 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1774 return -E1000_ERR_RESET;
1777 return E1000_SUCCESS;
1781 * e1000_valid_led_default_generic - Verify a valid default LED config
1782 * @hw: pointer to the HW structure
1783 * @data: pointer to the NVM (EEPROM)
1785 * Read the EEPROM for the current default LED configuration. If the
1786 * LED configuration is not valid, set to a valid LED configuration.
1788 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1792 DEBUGFUNC("e1000_valid_led_default_generic");
1794 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1796 DEBUGOUT("NVM Read Error\n");
1800 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1801 *data = ID_LED_DEFAULT;
1803 return E1000_SUCCESS;
1807 * e1000_id_led_init_generic -
1808 * @hw: pointer to the HW structure
1811 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1813 struct e1000_mac_info *mac = &hw->mac;
1815 const u32 ledctl_mask = 0x000000FF;
1816 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1817 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1819 const u16 led_mask = 0x0F;
1821 DEBUGFUNC("e1000_id_led_init_generic");
1823 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1827 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1828 mac->ledctl_mode1 = mac->ledctl_default;
1829 mac->ledctl_mode2 = mac->ledctl_default;
1831 for (i = 0; i < 4; i++) {
1832 temp = (data >> (i << 2)) & led_mask;
1834 case ID_LED_ON1_DEF2:
1835 case ID_LED_ON1_ON2:
1836 case ID_LED_ON1_OFF2:
1837 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1838 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1840 case ID_LED_OFF1_DEF2:
1841 case ID_LED_OFF1_ON2:
1842 case ID_LED_OFF1_OFF2:
1843 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1844 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1851 case ID_LED_DEF1_ON2:
1852 case ID_LED_ON1_ON2:
1853 case ID_LED_OFF1_ON2:
1854 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1855 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1857 case ID_LED_DEF1_OFF2:
1858 case ID_LED_ON1_OFF2:
1859 case ID_LED_OFF1_OFF2:
1860 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1861 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1869 return E1000_SUCCESS;
1873 * e1000_setup_led_generic - Configures SW controllable LED
1874 * @hw: pointer to the HW structure
1876 * This prepares the SW controllable LED for use and saves the current state
1877 * of the LED so it can be later restored.
1879 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1883 DEBUGFUNC("e1000_setup_led_generic");
1885 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1886 return -E1000_ERR_CONFIG;
1888 if (hw->phy.media_type == e1000_media_type_fiber) {
1889 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1890 hw->mac.ledctl_default = ledctl;
1892 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1893 E1000_LEDCTL_LED0_MODE_MASK);
1894 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1895 E1000_LEDCTL_LED0_MODE_SHIFT);
1896 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1897 } else if (hw->phy.media_type == e1000_media_type_copper) {
1898 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1901 return E1000_SUCCESS;
1905 * e1000_cleanup_led_generic - Set LED config to default operation
1906 * @hw: pointer to the HW structure
1908 * Remove the current LED configuration and set the LED configuration
1909 * to the default value, saved from the EEPROM.
1911 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1913 DEBUGFUNC("e1000_cleanup_led_generic");
1915 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1916 return E1000_SUCCESS;
1920 * e1000_blink_led_generic - Blink LED
1921 * @hw: pointer to the HW structure
1923 * Blink the LEDs which are set to be on.
1925 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1927 u32 ledctl_blink = 0;
1930 DEBUGFUNC("e1000_blink_led_generic");
1932 if (hw->phy.media_type == e1000_media_type_fiber) {
1933 /* always blink LED0 for PCI-E fiber */
1934 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1935 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1937 /* Set the blink bit for each LED that's "on" (0x0E)
1938 * (or "off" if inverted) in ledctl_mode2. The blink
1939 * logic in hardware only works when mode is set to "on"
1940 * so it must be changed accordingly when the mode is
1941 * "off" and inverted.
1943 ledctl_blink = hw->mac.ledctl_mode2;
1944 for (i = 0; i < 32; i += 8) {
1945 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1946 E1000_LEDCTL_LED0_MODE_MASK;
1947 u32 led_default = hw->mac.ledctl_default >> i;
1949 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1950 (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1951 ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1952 (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1954 ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1955 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1956 E1000_LEDCTL_MODE_LED_ON) << i;
1961 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1963 return E1000_SUCCESS;
1967 * e1000_led_on_generic - Turn LED on
1968 * @hw: pointer to the HW structure
1972 s32 e1000_led_on_generic(struct e1000_hw *hw)
1976 DEBUGFUNC("e1000_led_on_generic");
1978 switch (hw->phy.media_type) {
1979 case e1000_media_type_fiber:
1980 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1981 ctrl &= ~E1000_CTRL_SWDPIN0;
1982 ctrl |= E1000_CTRL_SWDPIO0;
1983 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1985 case e1000_media_type_copper:
1986 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1992 return E1000_SUCCESS;
1996 * e1000_led_off_generic - Turn LED off
1997 * @hw: pointer to the HW structure
2001 s32 e1000_led_off_generic(struct e1000_hw *hw)
2005 DEBUGFUNC("e1000_led_off_generic");
2007 switch (hw->phy.media_type) {
2008 case e1000_media_type_fiber:
2009 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2010 ctrl |= E1000_CTRL_SWDPIN0;
2011 ctrl |= E1000_CTRL_SWDPIO0;
2012 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2014 case e1000_media_type_copper:
2015 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2021 return E1000_SUCCESS;
2025 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2026 * @hw: pointer to the HW structure
2027 * @no_snoop: bitmap of snoop events
2029 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2031 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2035 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2037 if (hw->bus.type != e1000_bus_type_pci_express)
2041 gcr = E1000_READ_REG(hw, E1000_GCR);
2042 gcr &= ~(PCIE_NO_SNOOP_ALL);
2044 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2049 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2050 * @hw: pointer to the HW structure
2052 * Returns E1000_SUCCESS if successful, else returns -10
2053 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2054 * the master requests to be disabled.
2056 * Disables PCI-Express master access and verifies there are no pending
2059 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2062 s32 timeout = MASTER_DISABLE_TIMEOUT;
2064 DEBUGFUNC("e1000_disable_pcie_master_generic");
2066 if (hw->bus.type != e1000_bus_type_pci_express)
2067 return E1000_SUCCESS;
2069 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2070 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2071 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2074 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2075 E1000_STATUS_GIO_MASTER_ENABLE) ||
2076 E1000_REMOVED(hw->hw_addr))
2083 DEBUGOUT("Master requests are pending.\n");
2084 return -E1000_ERR_MASTER_REQUESTS_PENDING;
2087 return E1000_SUCCESS;
2091 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2092 * @hw: pointer to the HW structure
2094 * Reset the Adaptive Interframe Spacing throttle to default values.
2096 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2098 struct e1000_mac_info *mac = &hw->mac;
2100 DEBUGFUNC("e1000_reset_adaptive_generic");
2102 if (!mac->adaptive_ifs) {
2103 DEBUGOUT("Not in Adaptive IFS mode!\n");
2107 mac->current_ifs_val = 0;
2108 mac->ifs_min_val = IFS_MIN;
2109 mac->ifs_max_val = IFS_MAX;
2110 mac->ifs_step_size = IFS_STEP;
2111 mac->ifs_ratio = IFS_RATIO;
2113 mac->in_ifs_mode = false;
2114 E1000_WRITE_REG(hw, E1000_AIT, 0);
2118 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2119 * @hw: pointer to the HW structure
2121 * Update the Adaptive Interframe Spacing Throttle value based on the
2122 * time between transmitted packets and time between collisions.
2124 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2126 struct e1000_mac_info *mac = &hw->mac;
2128 DEBUGFUNC("e1000_update_adaptive_generic");
2130 if (!mac->adaptive_ifs) {
2131 DEBUGOUT("Not in Adaptive IFS mode!\n");
2135 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2136 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2137 mac->in_ifs_mode = true;
2138 if (mac->current_ifs_val < mac->ifs_max_val) {
2139 if (!mac->current_ifs_val)
2140 mac->current_ifs_val = mac->ifs_min_val;
2142 mac->current_ifs_val +=
2144 E1000_WRITE_REG(hw, E1000_AIT,
2145 mac->current_ifs_val);
2149 if (mac->in_ifs_mode &&
2150 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2151 mac->current_ifs_val = 0;
2152 mac->in_ifs_mode = false;
2153 E1000_WRITE_REG(hw, E1000_AIT, 0);
2159 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2160 * @hw: pointer to the HW structure
2162 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2163 * set, which is forced to MDI mode only.
2165 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2167 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2169 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2170 DEBUGOUT("Invalid MDI setting detected\n");
2172 return -E1000_ERR_CONFIG;
2175 return E1000_SUCCESS;
2179 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2180 * @hw: pointer to the HW structure
2182 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2185 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2187 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2188 UNREFERENCED_1PARAMETER(hw);
2190 return E1000_SUCCESS;
2194 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2195 * @hw: pointer to the HW structure
2196 * @reg: 32bit register offset such as E1000_SCTL
2197 * @offset: register offset to write to
2198 * @data: data to write at register offset
2200 * Writes an address/data control type register. There are several of these
2201 * and they all have the format address << 8 | data and bit 31 is polled for
2204 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2205 u32 offset, u8 data)
2207 u32 i, regvalue = 0;
2209 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2211 /* Set up the address and data */
2212 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2213 E1000_WRITE_REG(hw, reg, regvalue);
2215 /* Poll the ready bit to see if the MDI read completed */
2216 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2218 regvalue = E1000_READ_REG(hw, reg);
2219 if (regvalue & E1000_GEN_CTL_READY)
2222 if (!(regvalue & E1000_GEN_CTL_READY)) {
2223 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2224 return -E1000_ERR_PHY;
2227 return E1000_SUCCESS;