1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
37 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
38 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw);
39 STATIC int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
42 * e1000_init_mac_ops_generic - Initialize MAC function pointers
43 * @hw: pointer to the HW structure
45 * Setups up the function pointers to no-op functions
47 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
49 struct e1000_mac_info *mac = &hw->mac;
50 DEBUGFUNC("e1000_init_mac_ops_generic");
53 mac->ops.init_params = e1000_null_ops_generic;
54 mac->ops.init_hw = e1000_null_ops_generic;
55 mac->ops.reset_hw = e1000_null_ops_generic;
56 mac->ops.setup_physical_interface = e1000_null_ops_generic;
57 mac->ops.get_bus_info = e1000_null_ops_generic;
58 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
59 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
60 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
61 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
63 mac->ops.cleanup_led = e1000_null_ops_generic;
64 mac->ops.setup_led = e1000_null_ops_generic;
65 mac->ops.blink_led = e1000_null_ops_generic;
66 mac->ops.led_on = e1000_null_ops_generic;
67 mac->ops.led_off = e1000_null_ops_generic;
69 mac->ops.setup_link = e1000_null_ops_generic;
70 mac->ops.get_link_up_info = e1000_null_link_info;
71 mac->ops.check_for_link = e1000_null_ops_generic;
73 mac->ops.check_mng_mode = e1000_null_mng_mode;
75 mac->ops.update_mc_addr_list = e1000_null_update_mc;
76 mac->ops.clear_vfta = e1000_null_mac_generic;
77 mac->ops.write_vfta = e1000_null_write_vfta;
78 mac->ops.rar_set = e1000_rar_set_generic;
79 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
83 * e1000_null_ops_generic - No-op function, returns 0
84 * @hw: pointer to the HW structure
86 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
88 DEBUGFUNC("e1000_null_ops_generic");
89 UNREFERENCED_1PARAMETER(hw);
94 * e1000_null_mac_generic - No-op function, return void
95 * @hw: pointer to the HW structure
97 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
99 DEBUGFUNC("e1000_null_mac_generic");
100 UNREFERENCED_1PARAMETER(hw);
105 * e1000_null_link_info - No-op function, return 0
106 * @hw: pointer to the HW structure
108 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,
109 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)
111 DEBUGFUNC("e1000_null_link_info");
112 UNREFERENCED_3PARAMETER(hw, s, d);
113 return E1000_SUCCESS;
117 * e1000_null_mng_mode - No-op function, return false
118 * @hw: pointer to the HW structure
120 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
122 DEBUGFUNC("e1000_null_mng_mode");
123 UNREFERENCED_1PARAMETER(hw);
128 * e1000_null_update_mc - No-op function, return void
129 * @hw: pointer to the HW structure
131 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,
132 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
134 DEBUGFUNC("e1000_null_update_mc");
135 UNREFERENCED_3PARAMETER(hw, h, a);
140 * e1000_null_write_vfta - No-op function, return void
141 * @hw: pointer to the HW structure
143 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,
144 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
146 DEBUGFUNC("e1000_null_write_vfta");
147 UNREFERENCED_3PARAMETER(hw, a, b);
152 * e1000_null_rar_set - No-op function, return 0
153 * @hw: pointer to the HW structure
155 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
156 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
158 DEBUGFUNC("e1000_null_rar_set");
159 UNREFERENCED_3PARAMETER(hw, h, a);
160 return E1000_SUCCESS;
164 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
165 * @hw: pointer to the HW structure
167 * Determines and stores the system bus information for a particular
168 * network interface. The following bus information is determined and stored:
169 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
171 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
173 struct e1000_mac_info *mac = &hw->mac;
174 struct e1000_bus_info *bus = &hw->bus;
175 u32 status = E1000_READ_REG(hw, E1000_STATUS);
176 s32 ret_val = E1000_SUCCESS;
178 DEBUGFUNC("e1000_get_bus_info_pci_generic");
181 bus->type = (status & E1000_STATUS_PCIX_MODE)
182 ? e1000_bus_type_pcix
183 : e1000_bus_type_pci;
186 if (bus->type == e1000_bus_type_pci) {
187 bus->speed = (status & E1000_STATUS_PCI66)
189 : e1000_bus_speed_33;
191 switch (status & E1000_STATUS_PCIX_SPEED) {
192 case E1000_STATUS_PCIX_SPEED_66:
193 bus->speed = e1000_bus_speed_66;
195 case E1000_STATUS_PCIX_SPEED_100:
196 bus->speed = e1000_bus_speed_100;
198 case E1000_STATUS_PCIX_SPEED_133:
199 bus->speed = e1000_bus_speed_133;
202 bus->speed = e1000_bus_speed_reserved;
208 bus->width = (status & E1000_STATUS_BUS64)
210 : e1000_bus_width_32;
212 /* Which PCI(-X) function? */
213 mac->ops.set_lan_id(hw);
219 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
220 * @hw: pointer to the HW structure
222 * Determines and stores the system bus information for a particular
223 * network interface. The following bus information is determined and stored:
224 * bus speed, bus width, type (PCIe), and PCIe function.
226 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
228 struct e1000_mac_info *mac = &hw->mac;
229 struct e1000_bus_info *bus = &hw->bus;
231 u16 pcie_link_status;
233 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
235 bus->type = e1000_bus_type_pci_express;
237 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
240 bus->width = e1000_bus_width_unknown;
241 bus->speed = e1000_bus_speed_unknown;
243 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
244 case PCIE_LINK_SPEED_2500:
245 bus->speed = e1000_bus_speed_2500;
247 case PCIE_LINK_SPEED_5000:
248 bus->speed = e1000_bus_speed_5000;
251 bus->speed = e1000_bus_speed_unknown;
255 bus->width = (enum e1000_bus_width)((pcie_link_status &
256 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
259 mac->ops.set_lan_id(hw);
261 return E1000_SUCCESS;
265 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
267 * @hw: pointer to the HW structure
269 * Determines the LAN function id by reading memory-mapped registers
270 * and swaps the port value if requested.
272 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
274 struct e1000_bus_info *bus = &hw->bus;
277 /* The status register reports the correct function number
278 * for the device regardless of function swap state.
280 reg = E1000_READ_REG(hw, E1000_STATUS);
281 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
285 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
286 * @hw: pointer to the HW structure
288 * Determines the LAN function id by reading PCI config space.
290 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
292 struct e1000_bus_info *bus = &hw->bus;
296 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
297 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
298 status = E1000_READ_REG(hw, E1000_STATUS);
299 bus->func = (status & E1000_STATUS_FUNC_MASK)
300 >> E1000_STATUS_FUNC_SHIFT;
307 * e1000_set_lan_id_single_port - Set LAN id for a single port device
308 * @hw: pointer to the HW structure
310 * Sets the LAN function id to zero for a single port device.
312 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
314 struct e1000_bus_info *bus = &hw->bus;
320 * e1000_clear_vfta_generic - Clear VLAN filter table
321 * @hw: pointer to the HW structure
323 * Clears the register array which contains the VLAN filter table by
324 * setting all the values to 0.
326 void e1000_clear_vfta_generic(struct e1000_hw *hw)
330 DEBUGFUNC("e1000_clear_vfta_generic");
332 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
333 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
334 E1000_WRITE_FLUSH(hw);
339 * e1000_write_vfta_generic - Write value to VLAN filter table
340 * @hw: pointer to the HW structure
341 * @offset: register offset in VLAN filter table
342 * @value: register value written to VLAN filter table
344 * Writes value at the given offset in the register array which stores
345 * the VLAN filter table.
347 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
349 DEBUGFUNC("e1000_write_vfta_generic");
351 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
352 E1000_WRITE_FLUSH(hw);
356 * e1000_init_rx_addrs_generic - Initialize receive address's
357 * @hw: pointer to the HW structure
358 * @rar_count: receive address registers
360 * Setup the receive address registers by setting the base receive address
361 * register to the devices MAC address and clearing all the other receive
362 * address registers to 0.
364 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
367 u8 mac_addr[ETH_ADDR_LEN] = {0};
369 DEBUGFUNC("e1000_init_rx_addrs_generic");
371 /* Setup the receive address */
372 DEBUGOUT("Programming MAC Address into RAR[0]\n");
374 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
376 /* Zero out the other (rar_entry_count - 1) receive addresses */
377 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
378 for (i = 1; i < rar_count; i++)
379 hw->mac.ops.rar_set(hw, mac_addr, i);
383 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
384 * @hw: pointer to the HW structure
386 * Checks the nvm for an alternate MAC address. An alternate MAC address
387 * can be setup by pre-boot software and must be treated like a permanent
388 * address and must override the actual permanent MAC address. If an
389 * alternate MAC address is found it is programmed into RAR0, replacing
390 * the permanent address that was installed into RAR0 by the Si on reset.
391 * This function will return SUCCESS unless it encounters an error while
392 * reading the EEPROM.
394 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
398 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
399 u8 alt_mac_addr[ETH_ADDR_LEN];
401 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
403 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
407 /* not supported on older hardware or 82573 */
408 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
409 return E1000_SUCCESS;
411 /* Alternate MAC address is handled by the option ROM for 82580
412 * and newer. SW support not required.
414 if (hw->mac.type >= e1000_82580)
415 return E1000_SUCCESS;
417 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
418 &nvm_alt_mac_addr_offset);
420 DEBUGOUT("NVM Read Error\n");
424 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
425 (nvm_alt_mac_addr_offset == 0x0000))
426 /* There is no Alternate MAC Address */
427 return E1000_SUCCESS;
429 if (hw->bus.func == E1000_FUNC_1)
430 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
431 if (hw->bus.func == E1000_FUNC_2)
432 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
434 if (hw->bus.func == E1000_FUNC_3)
435 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
436 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
437 offset = nvm_alt_mac_addr_offset + (i >> 1);
438 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
440 DEBUGOUT("NVM Read Error\n");
444 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
445 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
448 /* if multicast bit is set, the alternate address will not be used */
449 if (alt_mac_addr[0] & 0x01) {
450 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
451 return E1000_SUCCESS;
454 /* We have a valid alternate MAC address, and we want to treat it the
455 * same as the normal permanent MAC address stored by the HW into the
456 * RAR. Do this by mapping this address into RAR0.
458 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
460 return E1000_SUCCESS;
464 * e1000_rar_set_generic - Set receive address register
465 * @hw: pointer to the HW structure
466 * @addr: pointer to the receive address
467 * @index: receive address array register
469 * Sets the receive address array register at index to the address passed
472 STATIC int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
474 u32 rar_low, rar_high;
476 DEBUGFUNC("e1000_rar_set_generic");
478 /* HW expects these in little endian so we reverse the byte order
479 * from network order (big endian) to little endian
481 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
482 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
484 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
486 /* If MAC address zero, no need to set the AV bit */
487 if (rar_low || rar_high)
488 rar_high |= E1000_RAH_AV;
490 /* Some bridges will combine consecutive 32-bit writes into
491 * a single burst write, which will malfunction on some parts.
492 * The flushes avoid this.
494 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
495 E1000_WRITE_FLUSH(hw);
496 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
497 E1000_WRITE_FLUSH(hw);
499 return E1000_SUCCESS;
503 * e1000_hash_mc_addr_generic - Generate a multicast hash value
504 * @hw: pointer to the HW structure
505 * @mc_addr: pointer to a multicast address
507 * Generates a multicast address hash value which is used to determine
508 * the multicast filter table array address and new table value.
510 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
512 u32 hash_value, hash_mask;
515 DEBUGFUNC("e1000_hash_mc_addr_generic");
517 /* Register count multiplied by bits per register */
518 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
520 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
521 * where 0xFF would still fall within the hash mask.
523 while (hash_mask >> bit_shift != 0xFF)
526 /* The portion of the address that is used for the hash table
527 * is determined by the mc_filter_type setting.
528 * The algorithm is such that there is a total of 8 bits of shifting.
529 * The bit_shift for a mc_filter_type of 0 represents the number of
530 * left-shifts where the MSB of mc_addr[5] would still fall within
531 * the hash_mask. Case 0 does this exactly. Since there are a total
532 * of 8 bits of shifting, then mc_addr[4] will shift right the
533 * remaining number of bits. Thus 8 - bit_shift. The rest of the
534 * cases are a variation of this algorithm...essentially raising the
535 * number of bits to shift mc_addr[5] left, while still keeping the
536 * 8-bit shifting total.
538 * For example, given the following Destination MAC Address and an
539 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
540 * we can see that the bit_shift for case 0 is 4. These are the hash
541 * values resulting from each mc_filter_type...
542 * [0] [1] [2] [3] [4] [5]
546 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
547 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
548 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
549 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
551 switch (hw->mac.mc_filter_type) {
566 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
567 (((u16) mc_addr[5]) << bit_shift)));
573 * e1000_update_mc_addr_list_generic - Update Multicast addresses
574 * @hw: pointer to the HW structure
575 * @mc_addr_list: array of multicast addresses to program
576 * @mc_addr_count: number of multicast addresses to program
578 * Updates entire Multicast Table Array.
579 * The caller must have a packed mc_addr_list of multicast addresses.
581 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
582 u8 *mc_addr_list, u32 mc_addr_count)
584 u32 hash_value, hash_bit, hash_reg;
587 DEBUGFUNC("e1000_update_mc_addr_list_generic");
589 /* clear mta_shadow */
590 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
592 /* update mta_shadow from mc_addr_list */
593 for (i = 0; (u32) i < mc_addr_count; i++) {
594 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
596 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
597 hash_bit = hash_value & 0x1F;
599 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
600 mc_addr_list += (ETH_ADDR_LEN);
603 /* replace the entire MTA table */
604 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
605 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
606 E1000_WRITE_FLUSH(hw);
610 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
611 * @hw: pointer to the HW structure
613 * In certain situations, a system BIOS may report that the PCIx maximum
614 * memory read byte count (MMRBC) value is higher than than the actual
615 * value. We check the PCIx command register with the current PCIx status
618 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
622 u16 pcix_stat_hi_word;
625 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
627 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
628 if (hw->bus.type != e1000_bus_type_pcix)
631 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
632 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
633 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
634 PCIX_COMMAND_MMRBC_SHIFT;
635 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
636 PCIX_STATUS_HI_MMRBC_SHIFT;
637 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
638 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
639 if (cmd_mmrbc > stat_mmrbc) {
640 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
641 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
642 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
647 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
648 * @hw: pointer to the HW structure
650 * Clears the base hardware counters by reading the counter registers.
652 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
654 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
656 E1000_READ_REG(hw, E1000_CRCERRS);
657 E1000_READ_REG(hw, E1000_SYMERRS);
658 E1000_READ_REG(hw, E1000_MPC);
659 E1000_READ_REG(hw, E1000_SCC);
660 E1000_READ_REG(hw, E1000_ECOL);
661 E1000_READ_REG(hw, E1000_MCC);
662 E1000_READ_REG(hw, E1000_LATECOL);
663 E1000_READ_REG(hw, E1000_COLC);
664 E1000_READ_REG(hw, E1000_DC);
665 E1000_READ_REG(hw, E1000_SEC);
666 E1000_READ_REG(hw, E1000_RLEC);
667 E1000_READ_REG(hw, E1000_XONRXC);
668 E1000_READ_REG(hw, E1000_XONTXC);
669 E1000_READ_REG(hw, E1000_XOFFRXC);
670 E1000_READ_REG(hw, E1000_XOFFTXC);
671 E1000_READ_REG(hw, E1000_FCRUC);
672 E1000_READ_REG(hw, E1000_GPRC);
673 E1000_READ_REG(hw, E1000_BPRC);
674 E1000_READ_REG(hw, E1000_MPRC);
675 E1000_READ_REG(hw, E1000_GPTC);
676 E1000_READ_REG(hw, E1000_GORCL);
677 E1000_READ_REG(hw, E1000_GORCH);
678 E1000_READ_REG(hw, E1000_GOTCL);
679 E1000_READ_REG(hw, E1000_GOTCH);
680 E1000_READ_REG(hw, E1000_RNBC);
681 E1000_READ_REG(hw, E1000_RUC);
682 E1000_READ_REG(hw, E1000_RFC);
683 E1000_READ_REG(hw, E1000_ROC);
684 E1000_READ_REG(hw, E1000_RJC);
685 E1000_READ_REG(hw, E1000_TORL);
686 E1000_READ_REG(hw, E1000_TORH);
687 E1000_READ_REG(hw, E1000_TOTL);
688 E1000_READ_REG(hw, E1000_TOTH);
689 E1000_READ_REG(hw, E1000_TPR);
690 E1000_READ_REG(hw, E1000_TPT);
691 E1000_READ_REG(hw, E1000_MPTC);
692 E1000_READ_REG(hw, E1000_BPTC);
696 * e1000_check_for_copper_link_generic - Check for link (Copper)
697 * @hw: pointer to the HW structure
699 * Checks to see of the link status of the hardware has changed. If a
700 * change in link status has been detected, then we read the PHY registers
701 * to get the current speed/duplex if link exists.
703 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
705 struct e1000_mac_info *mac = &hw->mac;
709 DEBUGFUNC("e1000_check_for_copper_link");
711 /* We only want to go out to the PHY registers to see if Auto-Neg
712 * has completed and/or if our link status has changed. The
713 * get_link_status flag is set upon receiving a Link Status
714 * Change or Rx Sequence Error interrupt.
716 if (!mac->get_link_status)
717 return E1000_SUCCESS;
719 /* First we want to see if the MII Status Register reports
720 * link. If so, then we want to get the current speed/duplex
723 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
728 return E1000_SUCCESS; /* No link detected */
730 mac->get_link_status = false;
732 /* Check if there was DownShift, must be checked
733 * immediately after link-up
735 e1000_check_downshift_generic(hw);
737 /* If we are forcing speed/duplex, then we simply return since
738 * we have already determined whether we have link or not.
741 return -E1000_ERR_CONFIG;
743 /* Auto-Neg is enabled. Auto Speed Detection takes care
744 * of MAC speed/duplex configuration. So we only need to
745 * configure Collision Distance in the MAC.
747 mac->ops.config_collision_dist(hw);
749 /* Configure Flow Control now that Auto-Neg has completed.
750 * First, we need to restore the desired flow control
751 * settings because we may have had to re-autoneg with a
752 * different link partner.
754 ret_val = e1000_config_fc_after_link_up_generic(hw);
756 DEBUGOUT("Error configuring flow control\n");
762 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
763 * @hw: pointer to the HW structure
765 * Checks for link up on the hardware. If link is not up and we have
766 * a signal, then we need to force link up.
768 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
770 struct e1000_mac_info *mac = &hw->mac;
776 DEBUGFUNC("e1000_check_for_fiber_link_generic");
778 ctrl = E1000_READ_REG(hw, E1000_CTRL);
779 status = E1000_READ_REG(hw, E1000_STATUS);
780 rxcw = E1000_READ_REG(hw, E1000_RXCW);
782 /* If we don't have link (auto-negotiation failed or link partner
783 * cannot auto-negotiate), the cable is plugged in (we have signal),
784 * and our link partner is not trying to auto-negotiate with us (we
785 * are receiving idles or data), we need to force link up. We also
786 * need to give auto-negotiation time to complete, in case the cable
787 * was just plugged in. The autoneg_failed flag does this.
789 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
790 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
791 !(rxcw & E1000_RXCW_C)) {
792 if (!mac->autoneg_failed) {
793 mac->autoneg_failed = true;
794 return E1000_SUCCESS;
796 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
798 /* Disable auto-negotiation in the TXCW register */
799 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
801 /* Force link-up and also force full-duplex. */
802 ctrl = E1000_READ_REG(hw, E1000_CTRL);
803 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
804 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
806 /* Configure Flow Control after forcing link up. */
807 ret_val = e1000_config_fc_after_link_up_generic(hw);
809 DEBUGOUT("Error configuring flow control\n");
812 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
813 /* If we are forcing link and we are receiving /C/ ordered
814 * sets, re-enable auto-negotiation in the TXCW register
815 * and disable forced link in the Device Control register
816 * in an attempt to auto-negotiate with our link partner.
818 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
819 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
820 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
822 mac->serdes_has_link = true;
825 return E1000_SUCCESS;
829 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
830 * @hw: pointer to the HW structure
832 * Checks for link up on the hardware. If link is not up and we have
833 * a signal, then we need to force link up.
835 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
837 struct e1000_mac_info *mac = &hw->mac;
843 DEBUGFUNC("e1000_check_for_serdes_link_generic");
845 ctrl = E1000_READ_REG(hw, E1000_CTRL);
846 status = E1000_READ_REG(hw, E1000_STATUS);
847 rxcw = E1000_READ_REG(hw, E1000_RXCW);
849 /* If we don't have link (auto-negotiation failed or link partner
850 * cannot auto-negotiate), and our link partner is not trying to
851 * auto-negotiate with us (we are receiving idles or data),
852 * we need to force link up. We also need to give auto-negotiation
855 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
856 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
857 if (!mac->autoneg_failed) {
858 mac->autoneg_failed = true;
859 return E1000_SUCCESS;
861 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
863 /* Disable auto-negotiation in the TXCW register */
864 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
866 /* Force link-up and also force full-duplex. */
867 ctrl = E1000_READ_REG(hw, E1000_CTRL);
868 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
869 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
871 /* Configure Flow Control after forcing link up. */
872 ret_val = e1000_config_fc_after_link_up_generic(hw);
874 DEBUGOUT("Error configuring flow control\n");
877 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
878 /* If we are forcing link and we are receiving /C/ ordered
879 * sets, re-enable auto-negotiation in the TXCW register
880 * and disable forced link in the Device Control register
881 * in an attempt to auto-negotiate with our link partner.
883 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
884 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
885 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
887 mac->serdes_has_link = true;
888 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
889 /* If we force link for non-auto-negotiation switch, check
890 * link status based on MAC synchronization for internal
893 /* SYNCH bit and IV bit are sticky. */
895 rxcw = E1000_READ_REG(hw, E1000_RXCW);
896 if (rxcw & E1000_RXCW_SYNCH) {
897 if (!(rxcw & E1000_RXCW_IV)) {
898 mac->serdes_has_link = true;
899 DEBUGOUT("SERDES: Link up - forced.\n");
902 mac->serdes_has_link = false;
903 DEBUGOUT("SERDES: Link down - force failed.\n");
907 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
908 status = E1000_READ_REG(hw, E1000_STATUS);
909 if (status & E1000_STATUS_LU) {
910 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
912 rxcw = E1000_READ_REG(hw, E1000_RXCW);
913 if (rxcw & E1000_RXCW_SYNCH) {
914 if (!(rxcw & E1000_RXCW_IV)) {
915 mac->serdes_has_link = true;
916 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
918 mac->serdes_has_link = false;
919 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
922 mac->serdes_has_link = false;
923 DEBUGOUT("SERDES: Link down - no sync.\n");
926 mac->serdes_has_link = false;
927 DEBUGOUT("SERDES: Link down - autoneg failed\n");
931 return E1000_SUCCESS;
935 * e1000_set_default_fc_generic - Set flow control default values
936 * @hw: pointer to the HW structure
938 * Read the EEPROM for the default values for flow control and store the
941 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
947 DEBUGFUNC("e1000_set_default_fc_generic");
949 /* Read and store word 0x0F of the EEPROM. This word contains bits
950 * that determine the hardware's default PAUSE (flow control) mode,
951 * a bit that determines whether the HW defaults to enabling or
952 * disabling auto-negotiation, and the direction of the
953 * SW defined pins. If there is no SW over-ride of the flow
954 * control setting, then the variable hw->fc will
955 * be initialized based on a value in the EEPROM.
957 if (hw->mac.type == e1000_i350) {
958 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
959 ret_val = hw->nvm.ops.read(hw,
960 NVM_INIT_CONTROL2_REG +
964 ret_val = hw->nvm.ops.read(hw,
965 NVM_INIT_CONTROL2_REG,
971 DEBUGOUT("NVM Read Error\n");
975 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
976 hw->fc.requested_mode = e1000_fc_none;
977 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
979 hw->fc.requested_mode = e1000_fc_tx_pause;
981 hw->fc.requested_mode = e1000_fc_full;
983 return E1000_SUCCESS;
987 * e1000_setup_link_generic - Setup flow control and link settings
988 * @hw: pointer to the HW structure
990 * Determines which flow control settings to use, then configures flow
991 * control. Calls the appropriate media-specific link configuration
992 * function. Assuming the adapter has a valid link partner, a valid link
993 * should be established. Assumes the hardware has previously been reset
994 * and the transmitter and receiver are not enabled.
996 s32 e1000_setup_link_generic(struct e1000_hw *hw)
1000 DEBUGFUNC("e1000_setup_link_generic");
1002 /* In the case of the phy reset being blocked, we already have a link.
1003 * We do not need to set it up again.
1005 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
1006 return E1000_SUCCESS;
1008 /* If requested flow control is set to default, set flow control
1009 * based on the EEPROM flow control settings.
1011 if (hw->fc.requested_mode == e1000_fc_default) {
1012 ret_val = e1000_set_default_fc_generic(hw);
1017 /* Save off the requested flow control mode for use later. Depending
1018 * on the link partner's capabilities, we may or may not use this mode.
1020 hw->fc.current_mode = hw->fc.requested_mode;
1022 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1023 hw->fc.current_mode);
1025 /* Call the necessary media_type subroutine to configure the link. */
1026 ret_val = hw->mac.ops.setup_physical_interface(hw);
1030 /* Initialize the flow control address, type, and PAUSE timer
1031 * registers to their default values. This is done even if flow
1032 * control is disabled, because it does not hurt anything to
1033 * initialize these registers.
1035 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1036 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1037 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1038 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1040 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1042 return e1000_set_fc_watermarks_generic(hw);
1046 * e1000_commit_fc_settings_generic - Configure flow control
1047 * @hw: pointer to the HW structure
1049 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1050 * base on the flow control settings in e1000_mac_info.
1052 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1054 struct e1000_mac_info *mac = &hw->mac;
1057 DEBUGFUNC("e1000_commit_fc_settings_generic");
1059 /* Check for a software override of the flow control settings, and
1060 * setup the device accordingly. If auto-negotiation is enabled, then
1061 * software will have to set the "PAUSE" bits to the correct value in
1062 * the Transmit Config Word Register (TXCW) and re-start auto-
1063 * negotiation. However, if auto-negotiation is disabled, then
1064 * software will have to manually configure the two flow control enable
1065 * bits in the CTRL register.
1067 * The possible values of the "fc" parameter are:
1068 * 0: Flow control is completely disabled
1069 * 1: Rx flow control is enabled (we can receive pause frames,
1070 * but not send pause frames).
1071 * 2: Tx flow control is enabled (we can send pause frames but we
1072 * do not support receiving pause frames).
1073 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1075 switch (hw->fc.current_mode) {
1077 /* Flow control completely disabled by a software over-ride. */
1078 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1080 case e1000_fc_rx_pause:
1081 /* Rx Flow control is enabled and Tx Flow control is disabled
1082 * by a software over-ride. Since there really isn't a way to
1083 * advertise that we are capable of Rx Pause ONLY, we will
1084 * advertise that we support both symmetric and asymmetric Rx
1085 * PAUSE. Later, we will disable the adapter's ability to send
1088 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1090 case e1000_fc_tx_pause:
1091 /* Tx Flow control is enabled, and Rx Flow control is disabled,
1092 * by a software over-ride.
1094 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1097 /* Flow control (both Rx and Tx) is enabled by a software
1100 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1103 DEBUGOUT("Flow control param set incorrectly\n");
1104 return -E1000_ERR_CONFIG;
1108 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1111 return E1000_SUCCESS;
1115 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1116 * @hw: pointer to the HW structure
1118 * Polls for link up by reading the status register, if link fails to come
1119 * up with auto-negotiation, then the link is forced if a signal is detected.
1121 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1123 struct e1000_mac_info *mac = &hw->mac;
1127 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1129 /* If we have a signal (the cable is plugged in, or assumed true for
1130 * serdes media) then poll for a "Link-Up" indication in the Device
1131 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1132 * seconds (Auto-negotiation should complete in less than 500
1133 * milliseconds even if the other end is doing it in SW).
1135 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1137 status = E1000_READ_REG(hw, E1000_STATUS);
1138 if (status & E1000_STATUS_LU)
1141 if (i == FIBER_LINK_UP_LIMIT) {
1142 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1143 mac->autoneg_failed = true;
1144 /* AutoNeg failed to achieve a link, so we'll call
1145 * mac->check_for_link. This routine will force the
1146 * link up if we detect a signal. This will allow us to
1147 * communicate with non-autonegotiating link partners.
1149 ret_val = mac->ops.check_for_link(hw);
1151 DEBUGOUT("Error while checking for link\n");
1154 mac->autoneg_failed = false;
1156 mac->autoneg_failed = false;
1157 DEBUGOUT("Valid Link Found\n");
1160 return E1000_SUCCESS;
1164 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1165 * @hw: pointer to the HW structure
1167 * Configures collision distance and flow control for fiber and serdes
1168 * links. Upon successful setup, poll for link.
1170 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1175 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1177 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1179 /* Take the link out of reset */
1180 ctrl &= ~E1000_CTRL_LRST;
1182 hw->mac.ops.config_collision_dist(hw);
1184 ret_val = e1000_commit_fc_settings_generic(hw);
1188 /* Since auto-negotiation is enabled, take the link out of reset (the
1189 * link will be in reset, because we previously reset the chip). This
1190 * will restart auto-negotiation. If auto-negotiation is successful
1191 * then the link-up status bit will be set and the flow control enable
1192 * bits (RFCE and TFCE) will be set according to their negotiated value.
1194 DEBUGOUT("Auto-negotiation enabled\n");
1196 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1197 E1000_WRITE_FLUSH(hw);
1200 /* For these adapters, the SW definable pin 1 is set when the optics
1201 * detect a signal. If we have a signal, then poll for a "Link-Up"
1204 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1205 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1206 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1208 DEBUGOUT("No signal detected\n");
1215 * e1000_config_collision_dist_generic - Configure collision distance
1216 * @hw: pointer to the HW structure
1218 * Configures the collision distance to the default value and is used
1219 * during link setup.
1221 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1225 DEBUGFUNC("e1000_config_collision_dist_generic");
1227 tctl = E1000_READ_REG(hw, E1000_TCTL);
1229 tctl &= ~E1000_TCTL_COLD;
1230 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1232 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1233 E1000_WRITE_FLUSH(hw);
1237 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1238 * @hw: pointer to the HW structure
1240 * Sets the flow control high/low threshold (watermark) registers. If
1241 * flow control XON frame transmission is enabled, then set XON frame
1242 * transmission as well.
1244 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1246 u32 fcrtl = 0, fcrth = 0;
1248 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1250 /* Set the flow control receive threshold registers. Normally,
1251 * these registers will be set to a default threshold that may be
1252 * adjusted later by the driver's runtime code. However, if the
1253 * ability to transmit pause frames is not enabled, then these
1254 * registers will be set to 0.
1256 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1257 /* We need to set up the Receive Threshold high and low water
1258 * marks as well as (optionally) enabling the transmission of
1261 fcrtl = hw->fc.low_water;
1262 if (hw->fc.send_xon)
1263 fcrtl |= E1000_FCRTL_XONE;
1265 fcrth = hw->fc.high_water;
1267 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1268 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1270 return E1000_SUCCESS;
1274 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1275 * @hw: pointer to the HW structure
1277 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1278 * device control register to reflect the adapter settings. TFCE and RFCE
1279 * need to be explicitly set by software when a copper PHY is used because
1280 * autonegotiation is managed by the PHY rather than the MAC. Software must
1281 * also configure these bits when link is forced on a fiber connection.
1283 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1287 DEBUGFUNC("e1000_force_mac_fc_generic");
1289 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1291 /* Because we didn't get link via the internal auto-negotiation
1292 * mechanism (we either forced link or we got link via PHY
1293 * auto-neg), we have to manually enable/disable transmit an
1294 * receive flow control.
1296 * The "Case" statement below enables/disable flow control
1297 * according to the "hw->fc.current_mode" parameter.
1299 * The possible values of the "fc" parameter are:
1300 * 0: Flow control is completely disabled
1301 * 1: Rx flow control is enabled (we can receive pause
1302 * frames but not send pause frames).
1303 * 2: Tx flow control is enabled (we can send pause frames
1304 * frames but we do not receive pause frames).
1305 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1306 * other: No other values should be possible at this point.
1308 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1310 switch (hw->fc.current_mode) {
1312 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1314 case e1000_fc_rx_pause:
1315 ctrl &= (~E1000_CTRL_TFCE);
1316 ctrl |= E1000_CTRL_RFCE;
1318 case e1000_fc_tx_pause:
1319 ctrl &= (~E1000_CTRL_RFCE);
1320 ctrl |= E1000_CTRL_TFCE;
1323 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1326 DEBUGOUT("Flow control param set incorrectly\n");
1327 return -E1000_ERR_CONFIG;
1330 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1332 return E1000_SUCCESS;
1336 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1337 * @hw: pointer to the HW structure
1339 * Checks the status of auto-negotiation after link up to ensure that the
1340 * speed and duplex were not forced. If the link needed to be forced, then
1341 * flow control needs to be forced also. If auto-negotiation is enabled
1342 * and did not fail, then we configure flow control based on our link
1345 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1347 struct e1000_mac_info *mac = &hw->mac;
1348 s32 ret_val = E1000_SUCCESS;
1349 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1350 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1353 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1355 /* Check for the case where we have fiber media and auto-neg failed
1356 * so we had to force link. In this case, we need to force the
1357 * configuration of the MAC to match the "fc" parameter.
1359 if (mac->autoneg_failed) {
1360 if (hw->phy.media_type == e1000_media_type_fiber ||
1361 hw->phy.media_type == e1000_media_type_internal_serdes)
1362 ret_val = e1000_force_mac_fc_generic(hw);
1364 if (hw->phy.media_type == e1000_media_type_copper)
1365 ret_val = e1000_force_mac_fc_generic(hw);
1369 DEBUGOUT("Error forcing flow control settings\n");
1373 /* Check for the case where we have copper media and auto-neg is
1374 * enabled. In this case, we need to check and see if Auto-Neg
1375 * has completed, and if so, how the PHY and link partner has
1376 * flow control configured.
1378 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1379 /* Read the MII Status Register and check to see if AutoNeg
1380 * has completed. We read this twice because this reg has
1381 * some "sticky" (latched) bits.
1383 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1386 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1390 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1391 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1395 /* The AutoNeg process has completed, so we now need to
1396 * read both the Auto Negotiation Advertisement
1397 * Register (Address 4) and the Auto_Negotiation Base
1398 * Page Ability Register (Address 5) to determine how
1399 * flow control was negotiated.
1401 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1405 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1406 &mii_nway_lp_ability_reg);
1410 /* Two bits in the Auto Negotiation Advertisement Register
1411 * (Address 4) and two bits in the Auto Negotiation Base
1412 * Page Ability Register (Address 5) determine flow control
1413 * for both the PHY and the link partner. The following
1414 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1415 * 1999, describes these PAUSE resolution bits and how flow
1416 * control is determined based upon these settings.
1417 * NOTE: DC = Don't Care
1419 * LOCAL DEVICE | LINK PARTNER
1420 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1421 *-------|---------|-------|---------|--------------------
1422 * 0 | 0 | DC | DC | e1000_fc_none
1423 * 0 | 1 | 0 | DC | e1000_fc_none
1424 * 0 | 1 | 1 | 0 | e1000_fc_none
1425 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1426 * 1 | 0 | 0 | DC | e1000_fc_none
1427 * 1 | DC | 1 | DC | e1000_fc_full
1428 * 1 | 1 | 0 | 0 | e1000_fc_none
1429 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1431 * Are both PAUSE bits set to 1? If so, this implies
1432 * Symmetric Flow Control is enabled at both ends. The
1433 * ASM_DIR bits are irrelevant per the spec.
1435 * For Symmetric Flow Control:
1437 * LOCAL DEVICE | LINK PARTNER
1438 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1439 *-------|---------|-------|---------|--------------------
1440 * 1 | DC | 1 | DC | E1000_fc_full
1443 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1444 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1445 /* Now we need to check if the user selected Rx ONLY
1446 * of pause frames. In this case, we had to advertise
1447 * FULL flow control because we could not advertise Rx
1448 * ONLY. Hence, we must now check to see if we need to
1449 * turn OFF the TRANSMISSION of PAUSE frames.
1451 if (hw->fc.requested_mode == e1000_fc_full) {
1452 hw->fc.current_mode = e1000_fc_full;
1453 DEBUGOUT("Flow Control = FULL.\n");
1455 hw->fc.current_mode = e1000_fc_rx_pause;
1456 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1459 /* For receiving PAUSE frames ONLY.
1461 * LOCAL DEVICE | LINK PARTNER
1462 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1463 *-------|---------|-------|---------|--------------------
1464 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1466 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1467 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1468 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1469 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1470 hw->fc.current_mode = e1000_fc_tx_pause;
1471 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1473 /* For transmitting PAUSE frames ONLY.
1475 * LOCAL DEVICE | LINK PARTNER
1476 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1477 *-------|---------|-------|---------|--------------------
1478 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1480 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1481 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1482 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1483 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1484 hw->fc.current_mode = e1000_fc_rx_pause;
1485 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1487 /* Per the IEEE spec, at this point flow control
1488 * should be disabled.
1490 hw->fc.current_mode = e1000_fc_none;
1491 DEBUGOUT("Flow Control = NONE.\n");
1494 /* Now we need to do one last check... If we auto-
1495 * negotiated to HALF DUPLEX, flow control should not be
1496 * enabled per IEEE 802.3 spec.
1498 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1500 DEBUGOUT("Error getting link speed and duplex\n");
1504 if (duplex == HALF_DUPLEX)
1505 hw->fc.current_mode = e1000_fc_none;
1507 /* Now we call a subroutine to actually force the MAC
1508 * controller to use the correct flow control settings.
1510 ret_val = e1000_force_mac_fc_generic(hw);
1512 DEBUGOUT("Error forcing flow control settings\n");
1517 /* Check for the case where we have SerDes media and auto-neg is
1518 * enabled. In this case, we need to check and see if Auto-Neg
1519 * has completed, and if so, how the PHY and link partner has
1520 * flow control configured.
1522 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1524 /* Read the PCS_LSTS and check to see if AutoNeg
1527 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1529 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1530 DEBUGOUT("PCS Auto Neg has not completed.\n");
1534 /* The AutoNeg process has completed, so we now need to
1535 * read both the Auto Negotiation Advertisement
1536 * Register (PCS_ANADV) and the Auto_Negotiation Base
1537 * Page Ability Register (PCS_LPAB) to determine how
1538 * flow control was negotiated.
1540 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1541 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1543 /* Two bits in the Auto Negotiation Advertisement Register
1544 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1545 * Page Ability Register (PCS_LPAB) determine flow control
1546 * for both the PHY and the link partner. The following
1547 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1548 * 1999, describes these PAUSE resolution bits and how flow
1549 * control is determined based upon these settings.
1550 * NOTE: DC = Don't Care
1552 * LOCAL DEVICE | LINK PARTNER
1553 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1554 *-------|---------|-------|---------|--------------------
1555 * 0 | 0 | DC | DC | e1000_fc_none
1556 * 0 | 1 | 0 | DC | e1000_fc_none
1557 * 0 | 1 | 1 | 0 | e1000_fc_none
1558 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1559 * 1 | 0 | 0 | DC | e1000_fc_none
1560 * 1 | DC | 1 | DC | e1000_fc_full
1561 * 1 | 1 | 0 | 0 | e1000_fc_none
1562 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1564 * Are both PAUSE bits set to 1? If so, this implies
1565 * Symmetric Flow Control is enabled at both ends. The
1566 * ASM_DIR bits are irrelevant per the spec.
1568 * For Symmetric Flow Control:
1570 * LOCAL DEVICE | LINK PARTNER
1571 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1572 *-------|---------|-------|---------|--------------------
1573 * 1 | DC | 1 | DC | e1000_fc_full
1576 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1577 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1578 /* Now we need to check if the user selected Rx ONLY
1579 * of pause frames. In this case, we had to advertise
1580 * FULL flow control because we could not advertise Rx
1581 * ONLY. Hence, we must now check to see if we need to
1582 * turn OFF the TRANSMISSION of PAUSE frames.
1584 if (hw->fc.requested_mode == e1000_fc_full) {
1585 hw->fc.current_mode = e1000_fc_full;
1586 DEBUGOUT("Flow Control = FULL.\n");
1588 hw->fc.current_mode = e1000_fc_rx_pause;
1589 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1592 /* For receiving PAUSE frames ONLY.
1594 * LOCAL DEVICE | LINK PARTNER
1595 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1596 *-------|---------|-------|---------|--------------------
1597 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1599 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1600 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1601 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1602 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1603 hw->fc.current_mode = e1000_fc_tx_pause;
1604 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1606 /* For transmitting PAUSE frames ONLY.
1608 * LOCAL DEVICE | LINK PARTNER
1609 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1610 *-------|---------|-------|---------|--------------------
1611 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1613 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1614 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1615 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1616 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1617 hw->fc.current_mode = e1000_fc_rx_pause;
1618 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1620 /* Per the IEEE spec, at this point flow control
1621 * should be disabled.
1623 hw->fc.current_mode = e1000_fc_none;
1624 DEBUGOUT("Flow Control = NONE.\n");
1627 /* Now we call a subroutine to actually force the MAC
1628 * controller to use the correct flow control settings.
1630 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1631 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1632 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1634 ret_val = e1000_force_mac_fc_generic(hw);
1636 DEBUGOUT("Error forcing flow control settings\n");
1641 return E1000_SUCCESS;
1645 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1646 * @hw: pointer to the HW structure
1647 * @speed: stores the current speed
1648 * @duplex: stores the current duplex
1650 * Read the status register for the current speed/duplex and store the current
1651 * speed and duplex for copper connections.
1653 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1658 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1660 status = E1000_READ_REG(hw, E1000_STATUS);
1661 if (status & E1000_STATUS_SPEED_1000) {
1662 *speed = SPEED_1000;
1663 DEBUGOUT("1000 Mbs, ");
1664 } else if (status & E1000_STATUS_SPEED_100) {
1666 DEBUGOUT("100 Mbs, ");
1669 DEBUGOUT("10 Mbs, ");
1672 if (status & E1000_STATUS_FD) {
1673 *duplex = FULL_DUPLEX;
1674 DEBUGOUT("Full Duplex\n");
1676 *duplex = HALF_DUPLEX;
1677 DEBUGOUT("Half Duplex\n");
1680 return E1000_SUCCESS;
1684 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1685 * @hw: pointer to the HW structure
1686 * @speed: stores the current speed
1687 * @duplex: stores the current duplex
1689 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1690 * for fiber/serdes links.
1692 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,
1693 u16 *speed, u16 *duplex)
1695 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1696 UNREFERENCED_1PARAMETER(hw);
1698 *speed = SPEED_1000;
1699 *duplex = FULL_DUPLEX;
1701 return E1000_SUCCESS;
1705 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1706 * @hw: pointer to the HW structure
1708 * Acquire the HW semaphore to access the PHY or NVM
1710 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1713 s32 timeout = hw->nvm.word_size + 1;
1716 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1718 /* Get the SW semaphore */
1719 while (i < timeout) {
1720 swsm = E1000_READ_REG(hw, E1000_SWSM);
1721 if (!(swsm & E1000_SWSM_SMBI))
1729 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1730 return -E1000_ERR_NVM;
1733 /* Get the FW semaphore. */
1734 for (i = 0; i < timeout; i++) {
1735 swsm = E1000_READ_REG(hw, E1000_SWSM);
1736 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1738 /* Semaphore acquired if bit latched */
1739 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1746 /* Release semaphores */
1747 e1000_put_hw_semaphore_generic(hw);
1748 DEBUGOUT("Driver can't access the NVM\n");
1749 return -E1000_ERR_NVM;
1752 return E1000_SUCCESS;
1756 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1757 * @hw: pointer to the HW structure
1759 * Release hardware semaphore used to access the PHY or NVM
1761 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1765 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1767 swsm = E1000_READ_REG(hw, E1000_SWSM);
1769 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1771 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1775 * e1000_get_auto_rd_done_generic - Check for auto read completion
1776 * @hw: pointer to the HW structure
1778 * Check EEPROM for Auto Read done bit.
1780 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1784 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1786 while (i < AUTO_READ_DONE_TIMEOUT) {
1787 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1793 if (i == AUTO_READ_DONE_TIMEOUT) {
1794 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1795 return -E1000_ERR_RESET;
1798 return E1000_SUCCESS;
1802 * e1000_valid_led_default_generic - Verify a valid default LED config
1803 * @hw: pointer to the HW structure
1804 * @data: pointer to the NVM (EEPROM)
1806 * Read the EEPROM for the current default LED configuration. If the
1807 * LED configuration is not valid, set to a valid LED configuration.
1809 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1813 DEBUGFUNC("e1000_valid_led_default_generic");
1815 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1817 DEBUGOUT("NVM Read Error\n");
1821 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1822 *data = ID_LED_DEFAULT;
1824 return E1000_SUCCESS;
1828 * e1000_id_led_init_generic -
1829 * @hw: pointer to the HW structure
1832 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1834 struct e1000_mac_info *mac = &hw->mac;
1836 const u32 ledctl_mask = 0x000000FF;
1837 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1838 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1840 const u16 led_mask = 0x0F;
1842 DEBUGFUNC("e1000_id_led_init_generic");
1844 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1848 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1849 mac->ledctl_mode1 = mac->ledctl_default;
1850 mac->ledctl_mode2 = mac->ledctl_default;
1852 for (i = 0; i < 4; i++) {
1853 temp = (data >> (i << 2)) & led_mask;
1855 case ID_LED_ON1_DEF2:
1856 case ID_LED_ON1_ON2:
1857 case ID_LED_ON1_OFF2:
1858 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1859 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1861 case ID_LED_OFF1_DEF2:
1862 case ID_LED_OFF1_ON2:
1863 case ID_LED_OFF1_OFF2:
1864 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1865 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1872 case ID_LED_DEF1_ON2:
1873 case ID_LED_ON1_ON2:
1874 case ID_LED_OFF1_ON2:
1875 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1876 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1878 case ID_LED_DEF1_OFF2:
1879 case ID_LED_ON1_OFF2:
1880 case ID_LED_OFF1_OFF2:
1881 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1882 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1890 return E1000_SUCCESS;
1894 * e1000_setup_led_generic - Configures SW controllable LED
1895 * @hw: pointer to the HW structure
1897 * This prepares the SW controllable LED for use and saves the current state
1898 * of the LED so it can be later restored.
1900 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1904 DEBUGFUNC("e1000_setup_led_generic");
1906 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1907 return -E1000_ERR_CONFIG;
1909 if (hw->phy.media_type == e1000_media_type_fiber) {
1910 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1911 hw->mac.ledctl_default = ledctl;
1913 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1914 E1000_LEDCTL_LED0_MODE_MASK);
1915 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1916 E1000_LEDCTL_LED0_MODE_SHIFT);
1917 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1918 } else if (hw->phy.media_type == e1000_media_type_copper) {
1919 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1922 return E1000_SUCCESS;
1926 * e1000_cleanup_led_generic - Set LED config to default operation
1927 * @hw: pointer to the HW structure
1929 * Remove the current LED configuration and set the LED configuration
1930 * to the default value, saved from the EEPROM.
1932 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1934 DEBUGFUNC("e1000_cleanup_led_generic");
1936 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1937 return E1000_SUCCESS;
1941 * e1000_blink_led_generic - Blink LED
1942 * @hw: pointer to the HW structure
1944 * Blink the LEDs which are set to be on.
1946 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1948 u32 ledctl_blink = 0;
1951 DEBUGFUNC("e1000_blink_led_generic");
1953 if (hw->phy.media_type == e1000_media_type_fiber) {
1954 /* always blink LED0 for PCI-E fiber */
1955 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1956 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1958 /* Set the blink bit for each LED that's "on" (0x0E)
1959 * (or "off" if inverted) in ledctl_mode2. The blink
1960 * logic in hardware only works when mode is set to "on"
1961 * so it must be changed accordingly when the mode is
1962 * "off" and inverted.
1964 ledctl_blink = hw->mac.ledctl_mode2;
1965 for (i = 0; i < 32; i += 8) {
1966 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1967 E1000_LEDCTL_LED0_MODE_MASK;
1968 u32 led_default = hw->mac.ledctl_default >> i;
1970 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1971 (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1972 ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1973 (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1975 ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1976 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1977 E1000_LEDCTL_MODE_LED_ON) << i;
1982 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1984 return E1000_SUCCESS;
1988 * e1000_led_on_generic - Turn LED on
1989 * @hw: pointer to the HW structure
1993 s32 e1000_led_on_generic(struct e1000_hw *hw)
1997 DEBUGFUNC("e1000_led_on_generic");
1999 switch (hw->phy.media_type) {
2000 case e1000_media_type_fiber:
2001 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2002 ctrl &= ~E1000_CTRL_SWDPIN0;
2003 ctrl |= E1000_CTRL_SWDPIO0;
2004 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2006 case e1000_media_type_copper:
2007 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2013 return E1000_SUCCESS;
2017 * e1000_led_off_generic - Turn LED off
2018 * @hw: pointer to the HW structure
2022 s32 e1000_led_off_generic(struct e1000_hw *hw)
2026 DEBUGFUNC("e1000_led_off_generic");
2028 switch (hw->phy.media_type) {
2029 case e1000_media_type_fiber:
2030 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2031 ctrl |= E1000_CTRL_SWDPIN0;
2032 ctrl |= E1000_CTRL_SWDPIO0;
2033 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2035 case e1000_media_type_copper:
2036 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2042 return E1000_SUCCESS;
2046 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2047 * @hw: pointer to the HW structure
2048 * @no_snoop: bitmap of snoop events
2050 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2052 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2056 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2058 if (hw->bus.type != e1000_bus_type_pci_express)
2062 gcr = E1000_READ_REG(hw, E1000_GCR);
2063 gcr &= ~(PCIE_NO_SNOOP_ALL);
2065 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2070 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2071 * @hw: pointer to the HW structure
2073 * Returns E1000_SUCCESS if successful, else returns -10
2074 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2075 * the master requests to be disabled.
2077 * Disables PCI-Express master access and verifies there are no pending
2080 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2083 s32 timeout = MASTER_DISABLE_TIMEOUT;
2085 DEBUGFUNC("e1000_disable_pcie_master_generic");
2087 if (hw->bus.type != e1000_bus_type_pci_express)
2088 return E1000_SUCCESS;
2090 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2091 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2092 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2095 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2096 E1000_STATUS_GIO_MASTER_ENABLE) ||
2097 E1000_REMOVED(hw->hw_addr))
2104 DEBUGOUT("Master requests are pending.\n");
2105 return -E1000_ERR_MASTER_REQUESTS_PENDING;
2108 return E1000_SUCCESS;
2112 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2113 * @hw: pointer to the HW structure
2115 * Reset the Adaptive Interframe Spacing throttle to default values.
2117 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2119 struct e1000_mac_info *mac = &hw->mac;
2121 DEBUGFUNC("e1000_reset_adaptive_generic");
2123 if (!mac->adaptive_ifs) {
2124 DEBUGOUT("Not in Adaptive IFS mode!\n");
2128 mac->current_ifs_val = 0;
2129 mac->ifs_min_val = IFS_MIN;
2130 mac->ifs_max_val = IFS_MAX;
2131 mac->ifs_step_size = IFS_STEP;
2132 mac->ifs_ratio = IFS_RATIO;
2134 mac->in_ifs_mode = false;
2135 E1000_WRITE_REG(hw, E1000_AIT, 0);
2139 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2140 * @hw: pointer to the HW structure
2142 * Update the Adaptive Interframe Spacing Throttle value based on the
2143 * time between transmitted packets and time between collisions.
2145 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2147 struct e1000_mac_info *mac = &hw->mac;
2149 DEBUGFUNC("e1000_update_adaptive_generic");
2151 if (!mac->adaptive_ifs) {
2152 DEBUGOUT("Not in Adaptive IFS mode!\n");
2156 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2157 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2158 mac->in_ifs_mode = true;
2159 if (mac->current_ifs_val < mac->ifs_max_val) {
2160 if (!mac->current_ifs_val)
2161 mac->current_ifs_val = mac->ifs_min_val;
2163 mac->current_ifs_val +=
2165 E1000_WRITE_REG(hw, E1000_AIT,
2166 mac->current_ifs_val);
2170 if (mac->in_ifs_mode &&
2171 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2172 mac->current_ifs_val = 0;
2173 mac->in_ifs_mode = false;
2174 E1000_WRITE_REG(hw, E1000_AIT, 0);
2180 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2181 * @hw: pointer to the HW structure
2183 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2184 * set, which is forced to MDI mode only.
2186 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2188 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2190 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2191 DEBUGOUT("Invalid MDI setting detected\n");
2193 return -E1000_ERR_CONFIG;
2196 return E1000_SUCCESS;
2200 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2201 * @hw: pointer to the HW structure
2203 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2206 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2208 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2209 UNREFERENCED_1PARAMETER(hw);
2211 return E1000_SUCCESS;
2215 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2216 * @hw: pointer to the HW structure
2217 * @reg: 32bit register offset such as E1000_SCTL
2218 * @offset: register offset to write to
2219 * @data: data to write at register offset
2221 * Writes an address/data control type register. There are several of these
2222 * and they all have the format address << 8 | data and bit 31 is polled for
2225 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2226 u32 offset, u8 data)
2228 u32 i, regvalue = 0;
2230 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2232 /* Set up the address and data */
2233 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2234 E1000_WRITE_REG(hw, reg, regvalue);
2236 /* Poll the ready bit to see if the MDI read completed */
2237 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2239 regvalue = E1000_READ_REG(hw, reg);
2240 if (regvalue & E1000_GEN_CTL_READY)
2243 if (!(regvalue & E1000_GEN_CTL_READY)) {
2244 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2245 return -E1000_ERR_PHY;
2248 return E1000_SUCCESS;