drivers/net/e1000/base/e1000_manage.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 #include "e1000_api.h"
   6
   7 /**
   8  *  e1000_calculate_checksum - Calculate checksum for buffer
   9  *  @buffer: pointer to EEPROM
  10  *  @length: size of EEPROM to calculate a checksum for
  11  *
  12  *  Calculates the checksum for some buffer on a specified length.  The
  13  *  checksum calculated is returned.
  14  **/
  15 u8 e1000_calculate_checksum(u8 *buffer, u32 length)
  16 {
  17         u32 i;
  18         u8 sum = 0;
  19
  20         DEBUGFUNC("e1000_calculate_checksum");
  21
  22         if (!buffer)
  23                 return 0;
  24
  25         for (i = 0; i < length; i++)
  26                 sum += buffer[i];
  27
  28         return (u8) (0 - sum);
  29 }
  30
  31 /**
  32  *  e1000_mng_enable_host_if_generic - Checks host interface is enabled
  33  *  @hw: pointer to the HW structure
  34  *
  35  *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
  36  *
  37  *  This function checks whether the HOST IF is enabled for command operation
  38  *  and also checks whether the previous command is completed.  It busy waits
  39  *  in case of previous command is not completed.
  40  **/
  41 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
  42 {
  43         u32 hicr;
  44         u8 i;
  45
  46         DEBUGFUNC("e1000_mng_enable_host_if_generic");
  47
  48         if (!hw->mac.arc_subsystem_valid) {
  49                 DEBUGOUT("ARC subsystem not valid.\n");
  50                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
  51         }
  52
  53         /* Check that the host interface is enabled. */
  54         hicr = E1000_READ_REG(hw, E1000_HICR);
  55         if (!(hicr & E1000_HICR_EN)) {
  56                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
  57                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
  58         }
  59         /* check the previous command is completed */
  60         for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
  61                 hicr = E1000_READ_REG(hw, E1000_HICR);
  62                 if (!(hicr & E1000_HICR_C))
  63                         break;
  64                 msec_delay_irq(1);
  65         }
  66
  67         if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
  68                 DEBUGOUT("Previous command timeout failed .\n");
  69                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
  70         }
  71
  72         return E1000_SUCCESS;
  73 }
  74
  75 /**
  76  *  e1000_check_mng_mode_generic - Generic check management mode
  77  *  @hw: pointer to the HW structure
  78  *
  79  *  Reads the firmware semaphore register and returns true (>0) if
  80  *  manageability is enabled, else false (0).
  81  **/
  82 bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
  83 {
  84         u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
  85
  86         DEBUGFUNC("e1000_check_mng_mode_generic");
  87
  88
  89         return (fwsm & E1000_FWSM_MODE_MASK) ==
  90                 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
  91 }
  92
  93 /**
  94  *  e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
  95  *  @hw: pointer to the HW structure
  96  *
  97  *  Enables packet filtering on transmit packets if manageability is enabled
  98  *  and host interface is enabled.
  99  **/
 100 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
 101 {
 102         struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
 103         u32 *buffer = (u32 *)&hw->mng_cookie;
 104         u32 offset;
 105         s32 ret_val, hdr_csum, csum;
 106         u8 i, len;
 107
 108         DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
 109
 110         hw->mac.tx_pkt_filtering = true;
 111
 112         /* No manageability, no filtering */
 113         if (!hw->mac.ops.check_mng_mode(hw)) {
 114                 hw->mac.tx_pkt_filtering = false;
 115                 return hw->mac.tx_pkt_filtering;
 116         }
 117
 118         /* If we can't read from the host interface for whatever
 119          * reason, disable filtering.
 120          */
 121         ret_val = e1000_mng_enable_host_if_generic(hw);
 122         if (ret_val != E1000_SUCCESS) {
 123                 hw->mac.tx_pkt_filtering = false;
 124                 return hw->mac.tx_pkt_filtering;
 125         }
 126
 127         /* Read in the header.  Length and offset are in dwords. */
 128         len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
 129         offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
 130         for (i = 0; i < len; i++)
 131                 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
 132                                                            offset + i);
 133         hdr_csum = hdr->checksum;
 134         hdr->checksum = 0;
 135         csum = e1000_calculate_checksum((u8 *)hdr,
 136                                         E1000_MNG_DHCP_COOKIE_LENGTH);
 137         /* If either the checksums or signature don't match, then
 138          * the cookie area isn't considered valid, in which case we
 139          * take the safe route of assuming Tx filtering is enabled.
 140          */
 141         if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
 142                 hw->mac.tx_pkt_filtering = true;
 143                 return hw->mac.tx_pkt_filtering;
 144         }
 145
 146         /* Cookie area is valid, make the final check for filtering. */
 147         if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
 148                 hw->mac.tx_pkt_filtering = false;
 149
 150         return hw->mac.tx_pkt_filtering;
 151 }
 152
 153 /**
 154  *  e1000_mng_write_cmd_header_generic - Writes manageability command header
 155  *  @hw: pointer to the HW structure
 156  *  @hdr: pointer to the host interface command header
 157  *
 158  *  Writes the command header after does the checksum calculation.
 159  **/
 160 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
 161                                       struct e1000_host_mng_command_header *hdr)
 162 {
 163         u16 i, length = sizeof(struct e1000_host_mng_command_header);
 164
 165         DEBUGFUNC("e1000_mng_write_cmd_header_generic");
 166
 167         /* Write the whole command header structure with new checksum. */
 168
 169         hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
 170
 171         length >>= 2;
 172         /* Write the relevant command block into the ram area. */
 173         for (i = 0; i < length; i++) {
 174                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
 175                                             *((u32 *) hdr + i));
 176                 E1000_WRITE_FLUSH(hw);
 177         }
 178
 179         return E1000_SUCCESS;
 180 }
 181
 182 /**
 183  *  e1000_mng_host_if_write_generic - Write to the manageability host interface
 184  *  @hw: pointer to the HW structure
 185  *  @buffer: pointer to the host interface buffer
 186  *  @length: size of the buffer
 187  *  @offset: location in the buffer to write to
 188  *  @sum: sum of the data (not checksum)
 189  *
 190  *  This function writes the buffer content at the offset given on the host if.
 191  *  It also does alignment considerations to do the writes in most efficient
 192  *  way.  Also fills up the sum of the buffer in *buffer parameter.
 193  **/
 194 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
 195                                     u16 length, u16 offset, u8 *sum)
 196 {
 197         u8 *tmp;
 198         u8 *bufptr = buffer;
 199         u32 data = 0;
 200         u16 remaining, i, j, prev_bytes;
 201
 202         DEBUGFUNC("e1000_mng_host_if_write_generic");
 203
 204         /* sum = only sum of the data and it is not checksum */
 205
 206         if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
 207                 return -E1000_ERR_PARAM;
 208
 209         tmp = (u8 *)&data;
 210         prev_bytes = offset & 0x3;
 211         offset >>= 2;
 212
 213         if (prev_bytes) {
 214                 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
 215                 for (j = prev_bytes; j < sizeof(u32); j++) {
 216                         *(tmp + j) = *bufptr++;
 217                         *sum += *(tmp + j);
 218                 }
 219                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
 220                 length -= j - prev_bytes;
 221                 offset++;
 222         }
 223
 224         remaining = length & 0x3;
 225         length -= remaining;
 226
 227         /* Calculate length in DWORDs */
 228         length >>= 2;
 229
 230         /* The device driver writes the relevant command block into the
 231          * ram area.
 232          */
 233         for (i = 0; i < length; i++) {
 234                 for (j = 0; j < sizeof(u32); j++) {
 235                         *(tmp + j) = *bufptr++;
 236                         *sum += *(tmp + j);
 237                 }
 238
 239                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
 240                                             data);
 241         }
 242         if (remaining) {
 243                 for (j = 0; j < sizeof(u32); j++) {
 244                         if (j < remaining)
 245                                 *(tmp + j) = *bufptr++;
 246                         else
 247                                 *(tmp + j) = 0;
 248
 249                         *sum += *(tmp + j);
 250                 }
 251                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
 252                                             data);
 253         }
 254
 255         return E1000_SUCCESS;
 256 }
 257
 258 /**
 259  *  e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
 260  *  @hw: pointer to the HW structure
 261  *  @buffer: pointer to the host interface
 262  *  @length: size of the buffer
 263  *
 264  *  Writes the DHCP information to the host interface.
 265  **/
 266 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
 267                                       u16 length)
 268 {
 269         struct e1000_host_mng_command_header hdr;
 270         s32 ret_val;
 271         u32 hicr;
 272
 273         DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
 274
 275         hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
 276         hdr.command_length = length;
 277         hdr.reserved1 = 0;
 278         hdr.reserved2 = 0;
 279         hdr.checksum = 0;
 280
 281         /* Enable the host interface */
 282         ret_val = e1000_mng_enable_host_if_generic(hw);
 283         if (ret_val)
 284                 return ret_val;
 285
 286         /* Populate the host interface with the contents of "buffer". */
 287         ret_val = e1000_mng_host_if_write_generic(hw, buffer, length,
 288                                                   sizeof(hdr), &(hdr.checksum));
 289         if (ret_val)
 290                 return ret_val;
 291
 292         /* Write the manageability command header */
 293         ret_val = e1000_mng_write_cmd_header_generic(hw, &hdr);
 294         if (ret_val)
 295                 return ret_val;
 296
 297         /* Tell the ARC a new command is pending. */
 298         hicr = E1000_READ_REG(hw, E1000_HICR);
 299         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 300
 301         return E1000_SUCCESS;
 302 }
 303
 304 /**
 305  *  e1000_enable_mng_pass_thru - Check if management passthrough is needed
 306  *  @hw: pointer to the HW structure
 307  *
 308  *  Verifies the hardware needs to leave interface enabled so that frames can
 309  *  be directed to and from the management interface.
 310  **/
 311 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
 312 {
 313         u32 manc;
 314         u32 fwsm, factps;
 315
 316         DEBUGFUNC("e1000_enable_mng_pass_thru");
 317
 318         if (!hw->mac.asf_firmware_present)
 319                 return false;
 320
 321         manc = E1000_READ_REG(hw, E1000_MANC);
 322
 323         if (!(manc & E1000_MANC_RCV_TCO_EN))
 324                 return false;
 325
 326         if (hw->mac.has_fwsm) {
 327                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
 328                 factps = E1000_READ_REG(hw, E1000_FACTPS);
 329
 330                 if (!(factps & E1000_FACTPS_MNGCG) &&
 331                     ((fwsm & E1000_FWSM_MODE_MASK) ==
 332                      (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
 333                         return true;
 334         } else if ((hw->mac.type == e1000_82574) ||
 335                    (hw->mac.type == e1000_82583)) {
 336                 u16 data;
 337                 s32 ret_val;
 338
 339                 factps = E1000_READ_REG(hw, E1000_FACTPS);
 340                 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
 341                 if (ret_val)
 342                         return false;
 343
 344                 if (!(factps & E1000_FACTPS_MNGCG) &&
 345                     ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
 346                      (e1000_mng_mode_pt << 13)))
 347                         return true;
 348         } else if ((manc & E1000_MANC_SMBUS_EN) &&
 349                    !(manc & E1000_MANC_ASF_EN)) {
 350                 return true;
 351         }
 352
 353         return false;
 354 }
 355
 356 /**
 357  *  e1000_host_interface_command - Writes buffer to host interface
 358  *  @hw: pointer to the HW structure
 359  *  @buffer: contains a command to write
 360  *  @length: the byte length of the buffer, must be multiple of 4 bytes
 361  *
 362  *  Writes a buffer to the Host Interface.  Upon success, returns E1000_SUCCESS
 363  *  else returns E1000_ERR_HOST_INTERFACE_COMMAND.
 364  **/
 365 s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)
 366 {
 367         u32 hicr, i;
 368
 369         DEBUGFUNC("e1000_host_interface_command");
 370
 371         if (!(hw->mac.arc_subsystem_valid)) {
 372                 DEBUGOUT("Hardware doesn't support host interface command.\n");
 373                 return E1000_SUCCESS;
 374         }
 375
 376         if (!hw->mac.asf_firmware_present) {
 377                 DEBUGOUT("Firmware is not present.\n");
 378                 return E1000_SUCCESS;
 379         }
 380
 381         if (length == 0 || length & 0x3 ||
 382             length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {
 383                 DEBUGOUT("Buffer length failure.\n");
 384                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 385         }
 386
 387         /* Check that the host interface is enabled. */
 388         hicr = E1000_READ_REG(hw, E1000_HICR);
 389         if (!(hicr & E1000_HICR_EN)) {
 390                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
 391                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 392         }
 393
 394         /* Calculate length in DWORDs */
 395         length >>= 2;
 396
 397         /* The device driver writes the relevant command block
 398          * into the ram area.
 399          */
 400         for (i = 0; i < length; i++)
 401                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
 402                                             *((u32 *)buffer + i));
 403
 404         /* Setting this bit tells the ARC that a new command is pending. */
 405         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 406
 407         for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
 408                 hicr = E1000_READ_REG(hw, E1000_HICR);
 409                 if (!(hicr & E1000_HICR_C))
 410                         break;
 411                 msec_delay(1);
 412         }
 413
 414         /* Check command successful completion. */
 415         if (i == E1000_HI_COMMAND_TIMEOUT ||
 416             (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {
 417                 DEBUGOUT("Command has failed with no status valid.\n");
 418                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 419         }
 420
 421         for (i = 0; i < length; i++)
 422                 *((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
 423                                                                   E1000_HOST_IF,
 424                                                                   i);
 425
 426         return E1000_SUCCESS;
 427 }
 428 /**
 429  *  e1000_load_firmware - Writes proxy FW code buffer to host interface
 430  *                        and execute.
 431  *  @hw: pointer to the HW structure
 432  *  @buffer: contains a firmware to write
 433  *  @length: the byte length of the buffer, must be multiple of 4 bytes
 434  *
 435  *  Upon success returns E1000_SUCCESS, returns E1000_ERR_CONFIG if not enabled
 436  *  in HW else returns E1000_ERR_HOST_INTERFACE_COMMAND.
 437  **/
 438 s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)
 439 {
 440         u32 hicr, hibba, fwsm, icr, i;
 441
 442         DEBUGFUNC("e1000_load_firmware");
 443
 444         if (hw->mac.type < e1000_i210) {
 445                 DEBUGOUT("Hardware doesn't support loading FW by the driver\n");
 446                 return -E1000_ERR_CONFIG;
 447         }
 448
 449         /* Check that the host interface is enabled. */
 450         hicr = E1000_READ_REG(hw, E1000_HICR);
 451         if (!(hicr & E1000_HICR_EN)) {
 452                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
 453                 return -E1000_ERR_CONFIG;
 454         }
 455         if (!(hicr & E1000_HICR_MEMORY_BASE_EN)) {
 456                 DEBUGOUT("E1000_HICR_MEMORY_BASE_EN bit disabled.\n");
 457                 return -E1000_ERR_CONFIG;
 458         }
 459
 460         if (length == 0 || length & 0x3 || length > E1000_HI_FW_MAX_LENGTH) {
 461                 DEBUGOUT("Buffer length failure.\n");
 462                 return -E1000_ERR_INVALID_ARGUMENT;
 463         }
 464
 465         /* Clear notification from ROM-FW by reading ICR register */
 466         icr = E1000_READ_REG(hw, E1000_ICR_V2);
 467
 468         /* Reset ROM-FW */
 469         hicr = E1000_READ_REG(hw, E1000_HICR);
 470         hicr |= E1000_HICR_FW_RESET_ENABLE;
 471         E1000_WRITE_REG(hw, E1000_HICR, hicr);
 472         hicr |= E1000_HICR_FW_RESET;
 473         E1000_WRITE_REG(hw, E1000_HICR, hicr);
 474         E1000_WRITE_FLUSH(hw);
 475
 476         /* Wait till MAC notifies about its readiness after ROM-FW reset */
 477         for (i = 0; i < (E1000_HI_COMMAND_TIMEOUT * 2); i++) {
 478                 icr = E1000_READ_REG(hw, E1000_ICR_V2);
 479                 if (icr & E1000_ICR_MNG)
 480                         break;
 481                 msec_delay(1);
 482         }
 483
 484         /* Check for timeout */
 485         if (i == E1000_HI_COMMAND_TIMEOUT) {
 486                 DEBUGOUT("FW reset failed.\n");
 487                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 488         }
 489
 490         /* Wait till MAC is ready to accept new FW code */
 491         for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
 492                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
 493                 if ((fwsm & E1000_FWSM_FW_VALID) &&
 494                     ((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT ==
 495                     E1000_FWSM_HI_EN_ONLY_MODE))
 496                         break;
 497                 msec_delay(1);
 498         }
 499
 500         /* Check for timeout */
 501         if (i == E1000_HI_COMMAND_TIMEOUT) {
 502                 DEBUGOUT("FW reset failed.\n");
 503                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 504         }
 505
 506         /* Calculate length in DWORDs */
 507         length >>= 2;
 508
 509         /* The device driver writes the relevant FW code block
 510          * into the ram area in DWORDs via 1kB ram addressing window.
 511          */
 512         for (i = 0; i < length; i++) {
 513                 if (!(i % E1000_HI_FW_BLOCK_DWORD_LENGTH)) {
 514                         /* Point to correct 1kB ram window */
 515                         hibba = E1000_HI_FW_BASE_ADDRESS +
 516                                 ((E1000_HI_FW_BLOCK_DWORD_LENGTH << 2) *
 517                                 (i / E1000_HI_FW_BLOCK_DWORD_LENGTH));
 518
 519                         E1000_WRITE_REG(hw, E1000_HIBBA, hibba);
 520                 }
 521
 522                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
 523                                             i % E1000_HI_FW_BLOCK_DWORD_LENGTH,
 524                                             *((u32 *)buffer + i));
 525         }
 526
 527         /* Setting this bit tells the ARC that a new FW is ready to execute. */
 528         hicr = E1000_READ_REG(hw, E1000_HICR);
 529         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 530
 531         for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
 532                 hicr = E1000_READ_REG(hw, E1000_HICR);
 533                 if (!(hicr & E1000_HICR_C))
 534                         break;
 535                 msec_delay(1);
 536         }
 537
 538         /* Check for successful FW start. */
 539         if (i == E1000_HI_COMMAND_TIMEOUT) {
 540                 DEBUGOUT("New FW did not start within timeout period.\n");
 541                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 542         }
 543
 544         return E1000_SUCCESS;
 545 }
 546
 547