1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #ifndef _E1000_MANAGE_H_
6 #define _E1000_MANAGE_H_
8 bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
9 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
10 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
11 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
12 u16 length, u16 offset, u8 *sum);
13 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
14 struct e1000_host_mng_command_header *hdr);
15 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
16 u8 *buffer, u16 length);
17 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
18 u8 e1000_calculate_checksum(u8 *buffer, u32 length);
19 s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length);
20 s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length);
23 e1000_mng_mode_none = 0,
27 e1000_mng_mode_host_if_only
30 #define E1000_FACTPS_MNGCG 0x20000000
32 #define E1000_FWSM_MODE_MASK 0xE
33 #define E1000_FWSM_MODE_SHIFT 1
34 #define E1000_FWSM_FW_VALID 0x00008000
35 #define E1000_FWSM_HI_EN_ONLY_MODE 0x4
37 #define E1000_MNG_IAMT_MODE 0x3
38 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
39 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
40 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
41 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
42 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
43 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
45 #define E1000_VFTA_ENTRY_SHIFT 5
46 #define E1000_VFTA_ENTRY_MASK 0x7F
47 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
49 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
50 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
51 #define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI cmd limit */
52 #define E1000_HI_FW_BASE_ADDRESS 0x10000
53 #define E1000_HI_FW_MAX_LENGTH (64 * 1024) /* Num of bytes */
54 #define E1000_HI_FW_BLOCK_DWORD_LENGTH 256 /* Num of DWORDs per page */
55 #define E1000_HICR_MEMORY_BASE_EN 0x200 /* MB Enable bit - RO */
56 #define E1000_HICR_EN 0x01 /* Enable bit - RO */
57 /* Driver sets this bit when done to put command in RAM */
58 #define E1000_HICR_C 0x02
59 #define E1000_HICR_SV 0x04 /* Status Validity */
60 #define E1000_HICR_FW_RESET_ENABLE 0x40
61 #define E1000_HICR_FW_RESET 0x80
63 /* Intel(R) Active Management Technology signature */
64 #define E1000_IAMT_SIGNATURE 0x544D4149