drivers/net/e1000/base/e1000_nvm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 #include "e1000_api.h"
   6
   7 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);
   8
   9 /**
  10  *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
  11  *  @hw: pointer to the HW structure
  12  *
  13  *  Setups up the function pointers to no-op functions
  14  **/
  15 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
  16 {
  17         struct e1000_nvm_info *nvm = &hw->nvm;
  18         DEBUGFUNC("e1000_init_nvm_ops_generic");
  19
  20         /* Initialize function pointers */
  21         nvm->ops.init_params = e1000_null_ops_generic;
  22         nvm->ops.acquire = e1000_null_ops_generic;
  23         nvm->ops.read = e1000_null_read_nvm;
  24         nvm->ops.release = e1000_null_nvm_generic;
  25         nvm->ops.reload = e1000_reload_nvm_generic;
  26         nvm->ops.update = e1000_null_ops_generic;
  27         nvm->ops.valid_led_default = e1000_null_led_default;
  28         nvm->ops.validate = e1000_null_ops_generic;
  29         nvm->ops.write = e1000_null_write_nvm;
  30 }
  31
  32 /**
  33  *  e1000_null_nvm_read - No-op function, return 0
  34  *  @hw: pointer to the HW structure
  35  **/
  36 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
  37                         u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
  38                         u16 E1000_UNUSEDARG *c)
  39 {
  40         DEBUGFUNC("e1000_null_read_nvm");
  41         UNREFERENCED_4PARAMETER(hw, a, b, c);
  42         return E1000_SUCCESS;
  43 }
  44
  45 /**
  46  *  e1000_null_nvm_generic - No-op function, return void
  47  *  @hw: pointer to the HW structure
  48  **/
  49 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
  50 {
  51         DEBUGFUNC("e1000_null_nvm_generic");
  52         UNREFERENCED_1PARAMETER(hw);
  53         return;
  54 }
  55
  56 /**
  57  *  e1000_null_led_default - No-op function, return 0
  58  *  @hw: pointer to the HW structure
  59  **/
  60 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
  61                            u16 E1000_UNUSEDARG *data)
  62 {
  63         DEBUGFUNC("e1000_null_led_default");
  64         UNREFERENCED_2PARAMETER(hw, data);
  65         return E1000_SUCCESS;
  66 }
  67
  68 /**
  69  *  e1000_null_write_nvm - No-op function, return 0
  70  *  @hw: pointer to the HW structure
  71  **/
  72 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
  73                          u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
  74                          u16 E1000_UNUSEDARG *c)
  75 {
  76         DEBUGFUNC("e1000_null_write_nvm");
  77         UNREFERENCED_4PARAMETER(hw, a, b, c);
  78         return E1000_SUCCESS;
  79 }
  80
  81 /**
  82  *  e1000_raise_eec_clk - Raise EEPROM clock
  83  *  @hw: pointer to the HW structure
  84  *  @eecd: pointer to the EEPROM
  85  *
  86  *  Enable/Raise the EEPROM clock bit.
  87  **/
  88 STATIC void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
  89 {
  90         *eecd = *eecd | E1000_EECD_SK;
  91         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
  92         E1000_WRITE_FLUSH(hw);
  93         usec_delay(hw->nvm.delay_usec);
  94 }
  95
  96 /**
  97  *  e1000_lower_eec_clk - Lower EEPROM clock
  98  *  @hw: pointer to the HW structure
  99  *  @eecd: pointer to the EEPROM
 100  *
 101  *  Clear/Lower the EEPROM clock bit.
 102  **/
 103 STATIC void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
 104 {
 105         *eecd = *eecd & ~E1000_EECD_SK;
 106         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 107         E1000_WRITE_FLUSH(hw);
 108         usec_delay(hw->nvm.delay_usec);
 109 }
 110
 111 /**
 112  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
 113  *  @hw: pointer to the HW structure
 114  *  @data: data to send to the EEPROM
 115  *  @count: number of bits to shift out
 116  *
 117  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
 118  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
 119  *  In order to do this, "data" must be broken down into bits.
 120  **/
 121 STATIC void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
 122 {
 123         struct e1000_nvm_info *nvm = &hw->nvm;
 124         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 125         u32 mask;
 126
 127         DEBUGFUNC("e1000_shift_out_eec_bits");
 128
 129         mask = 0x01 << (count - 1);
 130         if (nvm->type == e1000_nvm_eeprom_microwire)
 131                 eecd &= ~E1000_EECD_DO;
 132         else
 133         if (nvm->type == e1000_nvm_eeprom_spi)
 134                 eecd |= E1000_EECD_DO;
 135
 136         do {
 137                 eecd &= ~E1000_EECD_DI;
 138
 139                 if (data & mask)
 140                         eecd |= E1000_EECD_DI;
 141
 142                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 143                 E1000_WRITE_FLUSH(hw);
 144
 145                 usec_delay(nvm->delay_usec);
 146
 147                 e1000_raise_eec_clk(hw, &eecd);
 148                 e1000_lower_eec_clk(hw, &eecd);
 149
 150                 mask >>= 1;
 151         } while (mask);
 152
 153         eecd &= ~E1000_EECD_DI;
 154         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 155 }
 156
 157 /**
 158  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
 159  *  @hw: pointer to the HW structure
 160  *  @count: number of bits to shift in
 161  *
 162  *  In order to read a register from the EEPROM, we need to shift 'count' bits
 163  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
 164  *  the EEPROM (setting the SK bit), and then reading the value of the data out
 165  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
 166  *  always be clear.
 167  **/
 168 STATIC u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
 169 {
 170         u32 eecd;
 171         u32 i;
 172         u16 data;
 173
 174         DEBUGFUNC("e1000_shift_in_eec_bits");
 175
 176         eecd = E1000_READ_REG(hw, E1000_EECD);
 177
 178         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 179         data = 0;
 180
 181         for (i = 0; i < count; i++) {
 182                 data <<= 1;
 183                 e1000_raise_eec_clk(hw, &eecd);
 184
 185                 eecd = E1000_READ_REG(hw, E1000_EECD);
 186
 187                 eecd &= ~E1000_EECD_DI;
 188                 if (eecd & E1000_EECD_DO)
 189                         data |= 1;
 190
 191                 e1000_lower_eec_clk(hw, &eecd);
 192         }
 193
 194         return data;
 195 }
 196
 197 /**
 198  *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
 199  *  @hw: pointer to the HW structure
 200  *  @ee_reg: EEPROM flag for polling
 201  *
 202  *  Polls the EEPROM status bit for either read or write completion based
 203  *  upon the value of 'ee_reg'.
 204  **/
 205 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
 206 {
 207         u32 attempts = 100000;
 208         u32 i, reg = 0;
 209
 210         DEBUGFUNC("e1000_poll_eerd_eewr_done");
 211
 212         for (i = 0; i < attempts; i++) {
 213                 if (ee_reg == E1000_NVM_POLL_READ)
 214                         reg = E1000_READ_REG(hw, E1000_EERD);
 215                 else
 216                         reg = E1000_READ_REG(hw, E1000_EEWR);
 217
 218                 if (reg & E1000_NVM_RW_REG_DONE)
 219                         return E1000_SUCCESS;
 220
 221                 usec_delay(5);
 222         }
 223
 224         return -E1000_ERR_NVM;
 225 }
 226
 227 /**
 228  *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
 229  *  @hw: pointer to the HW structure
 230  *
 231  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 232  *  Return successful if access grant bit set, else clear the request for
 233  *  EEPROM access and return -E1000_ERR_NVM (-1).
 234  **/
 235 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
 236 {
 237         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 238         s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
 239
 240         DEBUGFUNC("e1000_acquire_nvm_generic");
 241
 242         E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
 243         eecd = E1000_READ_REG(hw, E1000_EECD);
 244
 245         while (timeout) {
 246                 if (eecd & E1000_EECD_GNT)
 247                         break;
 248                 usec_delay(5);
 249                 eecd = E1000_READ_REG(hw, E1000_EECD);
 250                 timeout--;
 251         }
 252
 253         if (!timeout) {
 254                 eecd &= ~E1000_EECD_REQ;
 255                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 256                 DEBUGOUT("Could not acquire NVM grant\n");
 257                 return -E1000_ERR_NVM;
 258         }
 259
 260         return E1000_SUCCESS;
 261 }
 262
 263 /**
 264  *  e1000_standby_nvm - Return EEPROM to standby state
 265  *  @hw: pointer to the HW structure
 266  *
 267  *  Return the EEPROM to a standby state.
 268  **/
 269 STATIC void e1000_standby_nvm(struct e1000_hw *hw)
 270 {
 271         struct e1000_nvm_info *nvm = &hw->nvm;
 272         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 273
 274         DEBUGFUNC("e1000_standby_nvm");
 275
 276         if (nvm->type == e1000_nvm_eeprom_microwire) {
 277                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 278                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 279                 E1000_WRITE_FLUSH(hw);
 280                 usec_delay(nvm->delay_usec);
 281
 282                 e1000_raise_eec_clk(hw, &eecd);
 283
 284                 /* Select EEPROM */
 285                 eecd |= E1000_EECD_CS;
 286                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 287                 E1000_WRITE_FLUSH(hw);
 288                 usec_delay(nvm->delay_usec);
 289
 290                 e1000_lower_eec_clk(hw, &eecd);
 291         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 292                 /* Toggle CS to flush commands */
 293                 eecd |= E1000_EECD_CS;
 294                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 295                 E1000_WRITE_FLUSH(hw);
 296                 usec_delay(nvm->delay_usec);
 297                 eecd &= ~E1000_EECD_CS;
 298                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 299                 E1000_WRITE_FLUSH(hw);
 300                 usec_delay(nvm->delay_usec);
 301         }
 302 }
 303
 304 /**
 305  *  e1000_stop_nvm - Terminate EEPROM command
 306  *  @hw: pointer to the HW structure
 307  *
 308  *  Terminates the current command by inverting the EEPROM's chip select pin.
 309  **/
 310 void e1000_stop_nvm(struct e1000_hw *hw)
 311 {
 312         u32 eecd;
 313
 314         DEBUGFUNC("e1000_stop_nvm");
 315
 316         eecd = E1000_READ_REG(hw, E1000_EECD);
 317         if (hw->nvm.type == e1000_nvm_eeprom_spi) {
 318                 /* Pull CS high */
 319                 eecd |= E1000_EECD_CS;
 320                 e1000_lower_eec_clk(hw, &eecd);
 321         } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
 322                 /* CS on Microwire is active-high */
 323                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 324                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 325                 e1000_raise_eec_clk(hw, &eecd);
 326                 e1000_lower_eec_clk(hw, &eecd);
 327         }
 328 }
 329
 330 /**
 331  *  e1000_release_nvm_generic - Release exclusive access to EEPROM
 332  *  @hw: pointer to the HW structure
 333  *
 334  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 335  **/
 336 void e1000_release_nvm_generic(struct e1000_hw *hw)
 337 {
 338         u32 eecd;
 339
 340         DEBUGFUNC("e1000_release_nvm_generic");
 341
 342         e1000_stop_nvm(hw);
 343
 344         eecd = E1000_READ_REG(hw, E1000_EECD);
 345         eecd &= ~E1000_EECD_REQ;
 346         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 347 }
 348
 349 /**
 350  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
 351  *  @hw: pointer to the HW structure
 352  *
 353  *  Setups the EEPROM for reading and writing.
 354  **/
 355 STATIC s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
 356 {
 357         struct e1000_nvm_info *nvm = &hw->nvm;
 358         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 359         u8 spi_stat_reg;
 360
 361         DEBUGFUNC("e1000_ready_nvm_eeprom");
 362
 363         if (nvm->type == e1000_nvm_eeprom_microwire) {
 364                 /* Clear SK and DI */
 365                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 366                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 367                 /* Set CS */
 368                 eecd |= E1000_EECD_CS;
 369                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 370         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 371                 u16 timeout = NVM_MAX_RETRY_SPI;
 372
 373                 /* Clear SK and CS */
 374                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 375                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 376                 E1000_WRITE_FLUSH(hw);
 377                 usec_delay(1);
 378
 379                 /* Read "Status Register" repeatedly until the LSB is cleared.
 380                  * The EEPROM will signal that the command has been completed
 381                  * by clearing bit 0 of the internal status register.  If it's
 382                  * not cleared within 'timeout', then error out.
 383                  */
 384                 while (timeout) {
 385                         e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
 386                                                  hw->nvm.opcode_bits);
 387                         spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
 388                         if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
 389                                 break;
 390
 391                         usec_delay(5);
 392                         e1000_standby_nvm(hw);
 393                         timeout--;
 394                 }
 395
 396                 if (!timeout) {
 397                         DEBUGOUT("SPI NVM Status error\n");
 398                         return -E1000_ERR_NVM;
 399                 }
 400         }
 401
 402         return E1000_SUCCESS;
 403 }
 404
 405 /**
 406  *  e1000_read_nvm_spi - Read EEPROM's using SPI
 407  *  @hw: pointer to the HW structure
 408  *  @offset: offset of word in the EEPROM to read
 409  *  @words: number of words to read
 410  *  @data: word read from the EEPROM
 411  *
 412  *  Reads a 16 bit word from the EEPROM.
 413  **/
 414 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 415 {
 416         struct e1000_nvm_info *nvm = &hw->nvm;
 417         u32 i = 0;
 418         s32 ret_val;
 419         u16 word_in;
 420         u8 read_opcode = NVM_READ_OPCODE_SPI;
 421
 422         DEBUGFUNC("e1000_read_nvm_spi");
 423
 424         /* A check for invalid values:  offset too large, too many words,
 425          * and not enough words.
 426          */
 427         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 428             (words == 0)) {
 429                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 430                 return -E1000_ERR_NVM;
 431         }
 432
 433         ret_val = nvm->ops.acquire(hw);
 434         if (ret_val)
 435                 return ret_val;
 436
 437         ret_val = e1000_ready_nvm_eeprom(hw);
 438         if (ret_val)
 439                 goto release;
 440
 441         e1000_standby_nvm(hw);
 442
 443         if ((nvm->address_bits == 8) && (offset >= 128))
 444                 read_opcode |= NVM_A8_OPCODE_SPI;
 445
 446         /* Send the READ command (opcode + addr) */
 447         e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 448         e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
 449
 450         /* Read the data.  SPI NVMs increment the address with each byte
 451          * read and will roll over if reading beyond the end.  This allows
 452          * us to read the whole NVM from any offset
 453          */
 454         for (i = 0; i < words; i++) {
 455                 word_in = e1000_shift_in_eec_bits(hw, 16);
 456                 data[i] = (word_in >> 8) | (word_in << 8);
 457         }
 458
 459 release:
 460         nvm->ops.release(hw);
 461
 462         return ret_val;
 463 }
 464
 465 /**
 466  *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
 467  *  @hw: pointer to the HW structure
 468  *  @offset: offset of word in the EEPROM to read
 469  *  @words: number of words to read
 470  *  @data: word read from the EEPROM
 471  *
 472  *  Reads a 16 bit word from the EEPROM.
 473  **/
 474 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 475                              u16 *data)
 476 {
 477         struct e1000_nvm_info *nvm = &hw->nvm;
 478         u32 i = 0;
 479         s32 ret_val;
 480         u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
 481
 482         DEBUGFUNC("e1000_read_nvm_microwire");
 483
 484         /* A check for invalid values:  offset too large, too many words,
 485          * and not enough words.
 486          */
 487         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 488             (words == 0)) {
 489                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 490                 return -E1000_ERR_NVM;
 491         }
 492
 493         ret_val = nvm->ops.acquire(hw);
 494         if (ret_val)
 495                 return ret_val;
 496
 497         ret_val = e1000_ready_nvm_eeprom(hw);
 498         if (ret_val)
 499                 goto release;
 500
 501         for (i = 0; i < words; i++) {
 502                 /* Send the READ command (opcode + addr) */
 503                 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 504                 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
 505                                         nvm->address_bits);
 506
 507                 /* Read the data.  For microwire, each word requires the
 508                  * overhead of setup and tear-down.
 509                  */
 510                 data[i] = e1000_shift_in_eec_bits(hw, 16);
 511                 e1000_standby_nvm(hw);
 512         }
 513
 514 release:
 515         nvm->ops.release(hw);
 516
 517         return ret_val;
 518 }
 519
 520 /**
 521  *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
 522  *  @hw: pointer to the HW structure
 523  *  @offset: offset of word in the EEPROM to read
 524  *  @words: number of words to read
 525  *  @data: word read from the EEPROM
 526  *
 527  *  Reads a 16 bit word from the EEPROM using the EERD register.
 528  **/
 529 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 530 {
 531         struct e1000_nvm_info *nvm = &hw->nvm;
 532         u32 i, eerd = 0;
 533         s32 ret_val = E1000_SUCCESS;
 534
 535         DEBUGFUNC("e1000_read_nvm_eerd");
 536
 537         /* A check for invalid values:  offset too large, too many words,
 538          * too many words for the offset, and not enough words.
 539          */
 540         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 541             (words == 0)) {
 542                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 543                 return -E1000_ERR_NVM;
 544         }
 545
 546         for (i = 0; i < words; i++) {
 547                 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
 548                        E1000_NVM_RW_REG_START;
 549
 550                 E1000_WRITE_REG(hw, E1000_EERD, eerd);
 551                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
 552                 if (ret_val)
 553                         break;
 554
 555                 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
 556                            E1000_NVM_RW_REG_DATA);
 557         }
 558
 559         if (ret_val)
 560                 DEBUGOUT1("NVM read error: %d\n", ret_val);
 561
 562         return ret_val;
 563 }
 564
 565 /**
 566  *  e1000_write_nvm_spi - Write to EEPROM using SPI
 567  *  @hw: pointer to the HW structure
 568  *  @offset: offset within the EEPROM to be written to
 569  *  @words: number of words to write
 570  *  @data: 16 bit word(s) to be written to the EEPROM
 571  *
 572  *  Writes data to EEPROM at offset using SPI interface.
 573  *
 574  *  If e1000_update_nvm_checksum is not called after this function , the
 575  *  EEPROM will most likely contain an invalid checksum.
 576  **/
 577 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 578 {
 579         struct e1000_nvm_info *nvm = &hw->nvm;
 580         s32 ret_val = -E1000_ERR_NVM;
 581         u16 widx = 0;
 582
 583         DEBUGFUNC("e1000_write_nvm_spi");
 584
 585         /* A check for invalid values:  offset too large, too many words,
 586          * and not enough words.
 587          */
 588         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 589             (words == 0)) {
 590                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 591                 return -E1000_ERR_NVM;
 592         }
 593
 594         while (widx < words) {
 595                 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
 596
 597                 ret_val = nvm->ops.acquire(hw);
 598                 if (ret_val)
 599                         return ret_val;
 600
 601                 ret_val = e1000_ready_nvm_eeprom(hw);
 602                 if (ret_val) {
 603                         nvm->ops.release(hw);
 604                         return ret_val;
 605                 }
 606
 607                 e1000_standby_nvm(hw);
 608
 609                 /* Send the WRITE ENABLE command (8 bit opcode) */
 610                 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
 611                                          nvm->opcode_bits);
 612
 613                 e1000_standby_nvm(hw);
 614
 615                 /* Some SPI eeproms use the 8th address bit embedded in the
 616                  * opcode
 617                  */
 618                 if ((nvm->address_bits == 8) && (offset >= 128))
 619                         write_opcode |= NVM_A8_OPCODE_SPI;
 620
 621                 /* Send the Write command (8-bit opcode + addr) */
 622                 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
 623                 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
 624                                          nvm->address_bits);
 625
 626                 /* Loop to allow for up to whole page write of eeprom */
 627                 while (widx < words) {
 628                         u16 word_out = data[widx];
 629                         word_out = (word_out >> 8) | (word_out << 8);
 630                         e1000_shift_out_eec_bits(hw, word_out, 16);
 631                         widx++;
 632
 633                         if ((((offset + widx) * 2) % nvm->page_size) == 0) {
 634                                 e1000_standby_nvm(hw);
 635                                 break;
 636                         }
 637                 }
 638                 msec_delay(10);
 639                 nvm->ops.release(hw);
 640         }
 641
 642         return ret_val;
 643 }
 644
 645 /**
 646  *  e1000_write_nvm_microwire - Writes EEPROM using microwire
 647  *  @hw: pointer to the HW structure
 648  *  @offset: offset within the EEPROM to be written to
 649  *  @words: number of words to write
 650  *  @data: 16 bit word(s) to be written to the EEPROM
 651  *
 652  *  Writes data to EEPROM at offset using microwire interface.
 653  *
 654  *  If e1000_update_nvm_checksum is not called after this function , the
 655  *  EEPROM will most likely contain an invalid checksum.
 656  **/
 657 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 658                               u16 *data)
 659 {
 660         struct e1000_nvm_info *nvm = &hw->nvm;
 661         s32  ret_val;
 662         u32 eecd;
 663         u16 words_written = 0;
 664         u16 widx = 0;
 665
 666         DEBUGFUNC("e1000_write_nvm_microwire");
 667
 668         /* A check for invalid values:  offset too large, too many words,
 669          * and not enough words.
 670          */
 671         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 672             (words == 0)) {
 673                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 674                 return -E1000_ERR_NVM;
 675         }
 676
 677         ret_val = nvm->ops.acquire(hw);
 678         if (ret_val)
 679                 return ret_val;
 680
 681         ret_val = e1000_ready_nvm_eeprom(hw);
 682         if (ret_val)
 683                 goto release;
 684
 685         e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
 686                                  (u16)(nvm->opcode_bits + 2));
 687
 688         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 689
 690         e1000_standby_nvm(hw);
 691
 692         while (words_written < words) {
 693                 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
 694                                          nvm->opcode_bits);
 695
 696                 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
 697                                          nvm->address_bits);
 698
 699                 e1000_shift_out_eec_bits(hw, data[words_written], 16);
 700
 701                 e1000_standby_nvm(hw);
 702
 703                 for (widx = 0; widx < 200; widx++) {
 704                         eecd = E1000_READ_REG(hw, E1000_EECD);
 705                         if (eecd & E1000_EECD_DO)
 706                                 break;
 707                         usec_delay(50);
 708                 }
 709
 710                 if (widx == 200) {
 711                         DEBUGOUT("NVM Write did not complete\n");
 712                         ret_val = -E1000_ERR_NVM;
 713                         goto release;
 714                 }
 715
 716                 e1000_standby_nvm(hw);
 717
 718                 words_written++;
 719         }
 720
 721         e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
 722                                  (u16)(nvm->opcode_bits + 2));
 723
 724         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 725
 726 release:
 727         nvm->ops.release(hw);
 728
 729         return ret_val;
 730 }
 731
 732 /**
 733  *  e1000_read_pba_string_generic - Read device part number
 734  *  @hw: pointer to the HW structure
 735  *  @pba_num: pointer to device part number
 736  *  @pba_num_size: size of part number buffer
 737  *
 738  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 739  *  the value in pba_num.
 740  **/
 741 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 742                                   u32 pba_num_size)
 743 {
 744         s32 ret_val;
 745         u16 nvm_data;
 746         u16 pba_ptr;
 747         u16 offset;
 748         u16 length;
 749
 750         DEBUGFUNC("e1000_read_pba_string_generic");
 751
 752         if ((hw->mac.type >= e1000_i210) &&
 753             !e1000_get_flash_presence_i210(hw)) {
 754                 DEBUGOUT("Flashless no PBA string\n");
 755                 return -E1000_ERR_NVM_PBA_SECTION;
 756         }
 757
 758         if (pba_num == NULL) {
 759                 DEBUGOUT("PBA string buffer was null\n");
 760                 return -E1000_ERR_INVALID_ARGUMENT;
 761         }
 762
 763         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 764         if (ret_val) {
 765                 DEBUGOUT("NVM Read Error\n");
 766                 return ret_val;
 767         }
 768
 769         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 770         if (ret_val) {
 771                 DEBUGOUT("NVM Read Error\n");
 772                 return ret_val;
 773         }
 774
 775         /* if nvm_data is not ptr guard the PBA must be in legacy format which
 776          * means pba_ptr is actually our second data word for the PBA number
 777          * and we can decode it into an ascii string
 778          */
 779         if (nvm_data != NVM_PBA_PTR_GUARD) {
 780                 DEBUGOUT("NVM PBA number is not stored as string\n");
 781
 782                 /* make sure callers buffer is big enough to store the PBA */
 783                 if (pba_num_size < E1000_PBANUM_LENGTH) {
 784                         DEBUGOUT("PBA string buffer too small\n");
 785                         return E1000_ERR_NO_SPACE;
 786                 }
 787
 788                 /* extract hex string from data and pba_ptr */
 789                 pba_num[0] = (nvm_data >> 12) & 0xF;
 790                 pba_num[1] = (nvm_data >> 8) & 0xF;
 791                 pba_num[2] = (nvm_data >> 4) & 0xF;
 792                 pba_num[3] = nvm_data & 0xF;
 793                 pba_num[4] = (pba_ptr >> 12) & 0xF;
 794                 pba_num[5] = (pba_ptr >> 8) & 0xF;
 795                 pba_num[6] = '-';
 796                 pba_num[7] = 0;
 797                 pba_num[8] = (pba_ptr >> 4) & 0xF;
 798                 pba_num[9] = pba_ptr & 0xF;
 799
 800                 /* put a null character on the end of our string */
 801                 pba_num[10] = '\0';
 802
 803                 /* switch all the data but the '-' to hex char */
 804                 for (offset = 0; offset < 10; offset++) {
 805                         if (pba_num[offset] < 0xA)
 806                                 pba_num[offset] += '0';
 807                         else if (pba_num[offset] < 0x10)
 808                                 pba_num[offset] += 'A' - 0xA;
 809                 }
 810
 811                 return E1000_SUCCESS;
 812         }
 813
 814         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 815         if (ret_val) {
 816                 DEBUGOUT("NVM Read Error\n");
 817                 return ret_val;
 818         }
 819
 820         if (length == 0xFFFF || length == 0) {
 821                 DEBUGOUT("NVM PBA number section invalid length\n");
 822                 return -E1000_ERR_NVM_PBA_SECTION;
 823         }
 824         /* check if pba_num buffer is big enough */
 825         if (pba_num_size < (((u32)length * 2) - 1)) {
 826                 DEBUGOUT("PBA string buffer too small\n");
 827                 return -E1000_ERR_NO_SPACE;
 828         }
 829
 830         /* trim pba length from start of string */
 831         pba_ptr++;
 832         length--;
 833
 834         for (offset = 0; offset < length; offset++) {
 835                 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
 836                 if (ret_val) {
 837                         DEBUGOUT("NVM Read Error\n");
 838                         return ret_val;
 839                 }
 840                 pba_num[offset * 2] = (u8)(nvm_data >> 8);
 841                 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
 842         }
 843         pba_num[offset * 2] = '\0';
 844
 845         return E1000_SUCCESS;
 846 }
 847
 848 /**
 849  *  e1000_read_pba_length_generic - Read device part number length
 850  *  @hw: pointer to the HW structure
 851  *  @pba_num_size: size of part number buffer
 852  *
 853  *  Reads the product board assembly (PBA) number length from the EEPROM and
 854  *  stores the value in pba_num_size.
 855  **/
 856 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
 857 {
 858         s32 ret_val;
 859         u16 nvm_data;
 860         u16 pba_ptr;
 861         u16 length;
 862
 863         DEBUGFUNC("e1000_read_pba_length_generic");
 864
 865         if (pba_num_size == NULL) {
 866                 DEBUGOUT("PBA buffer size was null\n");
 867                 return -E1000_ERR_INVALID_ARGUMENT;
 868         }
 869
 870         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 871         if (ret_val) {
 872                 DEBUGOUT("NVM Read Error\n");
 873                 return ret_val;
 874         }
 875
 876         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 877         if (ret_val) {
 878                 DEBUGOUT("NVM Read Error\n");
 879                 return ret_val;
 880         }
 881
 882          /* if data is not ptr guard the PBA must be in legacy format */
 883         if (nvm_data != NVM_PBA_PTR_GUARD) {
 884                 *pba_num_size = E1000_PBANUM_LENGTH;
 885                 return E1000_SUCCESS;
 886         }
 887
 888         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 889         if (ret_val) {
 890                 DEBUGOUT("NVM Read Error\n");
 891                 return ret_val;
 892         }
 893
 894         if (length == 0xFFFF || length == 0) {
 895                 DEBUGOUT("NVM PBA number section invalid length\n");
 896                 return -E1000_ERR_NVM_PBA_SECTION;
 897         }
 898
 899         /* Convert from length in u16 values to u8 chars, add 1 for NULL,
 900          * and subtract 2 because length field is included in length.
 901          */
 902         *pba_num_size = ((u32)length * 2) - 1;
 903
 904         return E1000_SUCCESS;
 905 }
 906
 907 /**
 908  *  e1000_read_pba_num_generic - Read device part number
 909  *  @hw: pointer to the HW structure
 910  *  @pba_num: pointer to device part number
 911  *
 912  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 913  *  the value in pba_num.
 914  **/
 915 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
 916 {
 917         s32 ret_val;
 918         u16 nvm_data;
 919
 920         DEBUGFUNC("e1000_read_pba_num_generic");
 921
 922         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 923         if (ret_val) {
 924                 DEBUGOUT("NVM Read Error\n");
 925                 return ret_val;
 926         } else if (nvm_data == NVM_PBA_PTR_GUARD) {
 927                 DEBUGOUT("NVM Not Supported\n");
 928                 return -E1000_NOT_IMPLEMENTED;
 929         }
 930         *pba_num = (u32)(nvm_data << 16);
 931
 932         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
 933         if (ret_val) {
 934                 DEBUGOUT("NVM Read Error\n");
 935                 return ret_val;
 936         }
 937         *pba_num |= nvm_data;
 938
 939         return E1000_SUCCESS;
 940 }
 941
 942
 943 /**
 944  *  e1000_read_pba_raw
 945  *  @hw: pointer to the HW structure
 946  *  @eeprom_buf: optional pointer to EEPROM image
 947  *  @eeprom_buf_size: size of EEPROM image in words
 948  *  @max_pba_block_size: PBA block size limit
 949  *  @pba: pointer to output PBA structure
 950  *
 951  *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
 952  *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
 953  *
 954  **/
 955 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
 956                        u32 eeprom_buf_size, u16 max_pba_block_size,
 957                        struct e1000_pba *pba)
 958 {
 959         s32 ret_val;
 960         u16 pba_block_size;
 961
 962         if (pba == NULL)
 963                 return -E1000_ERR_PARAM;
 964
 965         if (eeprom_buf == NULL) {
 966                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
 967                                          &pba->word[0]);
 968                 if (ret_val)
 969                         return ret_val;
 970         } else {
 971                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
 972                         pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
 973                         pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
 974                 } else {
 975                         return -E1000_ERR_PARAM;
 976                 }
 977         }
 978
 979         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
 980                 if (pba->pba_block == NULL)
 981                         return -E1000_ERR_PARAM;
 982
 983                 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
 984                                                    eeprom_buf_size,
 985                                                    &pba_block_size);
 986                 if (ret_val)
 987                         return ret_val;
 988
 989                 if (pba_block_size > max_pba_block_size)
 990                         return -E1000_ERR_PARAM;
 991
 992                 if (eeprom_buf == NULL) {
 993                         ret_val = e1000_read_nvm(hw, pba->word[1],
 994                                                  pba_block_size,
 995                                                  pba->pba_block);
 996                         if (ret_val)
 997                                 return ret_val;
 998                 } else {
 999                         if (eeprom_buf_size > (u32)(pba->word[1] +
1000                                               pba_block_size)) {
1001                                 memcpy(pba->pba_block,
1002                                        &eeprom_buf[pba->word[1]],
1003                                        pba_block_size * sizeof(u16));
1004                         } else {
1005                                 return -E1000_ERR_PARAM;
1006                         }
1007                 }
1008         }
1009
1010         return E1000_SUCCESS;
1011 }
1012
1013 /**
1014  *  e1000_write_pba_raw
1015  *  @hw: pointer to the HW structure
1016  *  @eeprom_buf: optional pointer to EEPROM image
1017  *  @eeprom_buf_size: size of EEPROM image in words
1018  *  @pba: pointer to PBA structure
1019  *
1020  *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
1021  *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1022  *
1023  **/
1024 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1025                         u32 eeprom_buf_size, struct e1000_pba *pba)
1026 {
1027         s32 ret_val;
1028
1029         if (pba == NULL)
1030                 return -E1000_ERR_PARAM;
1031
1032         if (eeprom_buf == NULL) {
1033                 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1034                                           &pba->word[0]);
1035                 if (ret_val)
1036                         return ret_val;
1037         } else {
1038                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1039                         eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1040                         eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1041                 } else {
1042                         return -E1000_ERR_PARAM;
1043                 }
1044         }
1045
1046         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1047                 if (pba->pba_block == NULL)
1048                         return -E1000_ERR_PARAM;
1049
1050                 if (eeprom_buf == NULL) {
1051                         ret_val = e1000_write_nvm(hw, pba->word[1],
1052                                                   pba->pba_block[0],
1053                                                   pba->pba_block);
1054                         if (ret_val)
1055                                 return ret_val;
1056                 } else {
1057                         if (eeprom_buf_size > (u32)(pba->word[1] +
1058                                               pba->pba_block[0])) {
1059                                 memcpy(&eeprom_buf[pba->word[1]],
1060                                        pba->pba_block,
1061                                        pba->pba_block[0] * sizeof(u16));
1062                         } else {
1063                                 return -E1000_ERR_PARAM;
1064                         }
1065                 }
1066         }
1067
1068         return E1000_SUCCESS;
1069 }
1070
1071 /**
1072  *  e1000_get_pba_block_size
1073  *  @hw: pointer to the HW structure
1074  *  @eeprom_buf: optional pointer to EEPROM image
1075  *  @eeprom_buf_size: size of EEPROM image in words
1076  *  @pba_data_size: pointer to output variable
1077  *
1078  *  Returns the size of the PBA block in words. Function operates on EEPROM
1079  *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1080  *  EEPROM device.
1081  *
1082  **/
1083 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1084                              u32 eeprom_buf_size, u16 *pba_block_size)
1085 {
1086         s32 ret_val;
1087         u16 pba_word[2];
1088         u16 length;
1089
1090         DEBUGFUNC("e1000_get_pba_block_size");
1091
1092         if (eeprom_buf == NULL) {
1093                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1094                 if (ret_val)
1095                         return ret_val;
1096         } else {
1097                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1098                         pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1099                         pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1100                 } else {
1101                         return -E1000_ERR_PARAM;
1102                 }
1103         }
1104
1105         if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1106                 if (eeprom_buf == NULL) {
1107                         ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1108                                                  &length);
1109                         if (ret_val)
1110                                 return ret_val;
1111                 } else {
1112                         if (eeprom_buf_size > pba_word[1])
1113                                 length = eeprom_buf[pba_word[1] + 0];
1114                         else
1115                                 return -E1000_ERR_PARAM;
1116                 }
1117
1118                 if (length == 0xFFFF || length == 0)
1119                         return -E1000_ERR_NVM_PBA_SECTION;
1120         } else {
1121                 /* PBA number in legacy format, there is no PBA Block. */
1122                 length = 0;
1123         }
1124
1125         if (pba_block_size != NULL)
1126                 *pba_block_size = length;
1127
1128         return E1000_SUCCESS;
1129 }
1130
1131 /**
1132  *  e1000_read_mac_addr_generic - Read device MAC address
1133  *  @hw: pointer to the HW structure
1134  *
1135  *  Reads the device MAC address from the EEPROM and stores the value.
1136  *  Since devices with two ports use the same EEPROM, we increment the
1137  *  last bit in the MAC address for the second port.
1138  **/
1139 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1140 {
1141         u32 rar_high;
1142         u32 rar_low;
1143         u16 i;
1144
1145         rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1146         rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1147
1148         for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1149                 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1150
1151         for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1152                 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1153
1154         for (i = 0; i < ETH_ADDR_LEN; i++)
1155                 hw->mac.addr[i] = hw->mac.perm_addr[i];
1156
1157         return E1000_SUCCESS;
1158 }
1159
1160 /**
1161  *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1162  *  @hw: pointer to the HW structure
1163  *
1164  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1165  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1166  **/
1167 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1168 {
1169         s32 ret_val;
1170         u16 checksum = 0;
1171         u16 i, nvm_data;
1172
1173         DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1174
1175         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1176                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1177                 if (ret_val) {
1178                         DEBUGOUT("NVM Read Error\n");
1179                         return ret_val;
1180                 }
1181                 checksum += nvm_data;
1182         }
1183
1184         if (checksum != (u16) NVM_SUM) {
1185                 DEBUGOUT("NVM Checksum Invalid\n");
1186                 return -E1000_ERR_NVM;
1187         }
1188
1189         return E1000_SUCCESS;
1190 }
1191
1192 /**
1193  *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1194  *  @hw: pointer to the HW structure
1195  *
1196  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1197  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1198  *  value to the EEPROM.
1199  **/
1200 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1201 {
1202         s32 ret_val;
1203         u16 checksum = 0;
1204         u16 i, nvm_data;
1205
1206         DEBUGFUNC("e1000_update_nvm_checksum");
1207
1208         for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1209                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1210                 if (ret_val) {
1211                         DEBUGOUT("NVM Read Error while updating checksum.\n");
1212                         return ret_val;
1213                 }
1214                 checksum += nvm_data;
1215         }
1216         checksum = (u16) NVM_SUM - checksum;
1217         ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1218         if (ret_val)
1219                 DEBUGOUT("NVM Write Error while updating checksum.\n");
1220
1221         return ret_val;
1222 }
1223
1224 /**
1225  *  e1000_reload_nvm_generic - Reloads EEPROM
1226  *  @hw: pointer to the HW structure
1227  *
1228  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1229  *  extended control register.
1230  **/
1231 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)
1232 {
1233         u32 ctrl_ext;
1234
1235         DEBUGFUNC("e1000_reload_nvm_generic");
1236
1237         usec_delay(10);
1238         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1239         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1240         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1241         E1000_WRITE_FLUSH(hw);
1242 }
1243
1244 /**
1245  *  e1000_get_fw_version - Get firmware version information
1246  *  @hw: pointer to the HW structure
1247  *  @fw_vers: pointer to output version structure
1248  *
1249  *  unsupported/not present features return 0 in version structure
1250  **/
1251 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1252 {
1253         u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
1254         u8 q, hval, rem, result;
1255         u16 comb_verh, comb_verl, comb_offset;
1256
1257         memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1258
1259         /* basic eeprom version numbers, bits used vary by part and by tool
1260          * used to create the nvm images */
1261         /* Check which data format we have */
1262         switch (hw->mac.type) {
1263         case e1000_i211:
1264                 e1000_read_invm_version(hw, fw_vers);
1265                 return;
1266         case e1000_82575:
1267         case e1000_82576:
1268         case e1000_82580:
1269         case e1000_i354:
1270                 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1271                 /* Use this format, unless EETRACK ID exists,
1272                  * then use alternate format
1273                  */
1274                 if ((etrack_test &  NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
1275                         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1276                         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1277                                               >> NVM_MAJOR_SHIFT;
1278                         fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
1279                                               >> NVM_MINOR_SHIFT;
1280                         fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
1281                         goto etrack_id;
1282                 }
1283                 break;
1284         case e1000_i210:
1285                 if (!(e1000_get_flash_presence_i210(hw))) {
1286                         e1000_read_invm_version(hw, fw_vers);
1287                         return;
1288                 }
1289                 /* fall through */
1290         case e1000_i350:
1291                 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1292                 /* find combo image version */
1293                 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1294                 if ((comb_offset != 0x0) &&
1295                     (comb_offset != NVM_VER_INVALID)) {
1296
1297                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1298                                          + 1), 1, &comb_verh);
1299                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1300                                          1, &comb_verl);
1301
1302                         /* get Option Rom version if it exists and is valid */
1303                         if ((comb_verh && comb_verl) &&
1304                             ((comb_verh != NVM_VER_INVALID) &&
1305                              (comb_verl != NVM_VER_INVALID))) {
1306
1307                                 fw_vers->or_valid = true;
1308                                 fw_vers->or_major =
1309                                         comb_verl >> NVM_COMB_VER_SHFT;
1310                                 fw_vers->or_build =
1311                                         (comb_verl << NVM_COMB_VER_SHFT)
1312                                         | (comb_verh >> NVM_COMB_VER_SHFT);
1313                                 fw_vers->or_patch =
1314                                         comb_verh & NVM_COMB_VER_MASK;
1315                         }
1316                 }
1317                 break;
1318         default:
1319                 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1320                 return;
1321         }
1322         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1323         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1324                               >> NVM_MAJOR_SHIFT;
1325
1326         /* check for old style version format in newer images*/
1327         if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
1328                 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
1329         } else {
1330                 eeprom_verl = (fw_version & NVM_MINOR_MASK)
1331                                 >> NVM_MINOR_SHIFT;
1332         }
1333         /* Convert minor value to hex before assigning to output struct
1334          * Val to be converted will not be higher than 99, per tool output
1335          */
1336         q = eeprom_verl / NVM_HEX_CONV;
1337         hval = q * NVM_HEX_TENS;
1338         rem = eeprom_verl % NVM_HEX_CONV;
1339         result = hval + rem;
1340         fw_vers->eep_minor = result;
1341
1342 etrack_id:
1343         if ((etrack_test &  NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
1344                 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1345                 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1346                 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
1347                         | eeprom_verl;
1348         } else if ((etrack_test & NVM_ETRACK_VALID) == 0) {
1349                 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
1350                 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
1351                 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |
1352                                      eeprom_verl;
1353         }
1354 }
1355
1356