1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
7 STATIC s32 e1000_wait_autoneg(struct e1000_hw *hw);
8 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
9 u16 *data, bool read, bool page_set);
10 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page);
11 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
12 u16 *data, bool read);
14 /* Cable length tables */
15 STATIC const u16 e1000_m88_cable_length_table[] = {
16 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
17 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
18 (sizeof(e1000_m88_cable_length_table) / \
19 sizeof(e1000_m88_cable_length_table[0]))
21 STATIC const u16 e1000_igp_2_cable_length_table[] = {
22 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
23 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
24 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
25 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
26 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
27 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
28 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
30 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
31 (sizeof(e1000_igp_2_cable_length_table) / \
32 sizeof(e1000_igp_2_cable_length_table[0]))
35 * e1000_init_phy_ops_generic - Initialize PHY function pointers
36 * @hw: pointer to the HW structure
38 * Setups up the function pointers to no-op functions
40 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
42 struct e1000_phy_info *phy = &hw->phy;
43 DEBUGFUNC("e1000_init_phy_ops_generic");
45 /* Initialize function pointers */
46 phy->ops.init_params = e1000_null_ops_generic;
47 phy->ops.acquire = e1000_null_ops_generic;
48 phy->ops.check_polarity = e1000_null_ops_generic;
49 phy->ops.check_reset_block = e1000_null_ops_generic;
50 phy->ops.commit = e1000_null_ops_generic;
51 phy->ops.force_speed_duplex = e1000_null_ops_generic;
52 phy->ops.get_cfg_done = e1000_null_ops_generic;
53 phy->ops.get_cable_length = e1000_null_ops_generic;
54 phy->ops.get_info = e1000_null_ops_generic;
55 phy->ops.set_page = e1000_null_set_page;
56 phy->ops.read_reg = e1000_null_read_reg;
57 phy->ops.read_reg_locked = e1000_null_read_reg;
58 phy->ops.read_reg_page = e1000_null_read_reg;
59 phy->ops.release = e1000_null_phy_generic;
60 phy->ops.reset = e1000_null_ops_generic;
61 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
62 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
63 phy->ops.write_reg = e1000_null_write_reg;
64 phy->ops.write_reg_locked = e1000_null_write_reg;
65 phy->ops.write_reg_page = e1000_null_write_reg;
66 phy->ops.power_up = e1000_null_phy_generic;
67 phy->ops.power_down = e1000_null_phy_generic;
68 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
69 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
70 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
74 * e1000_null_set_page - No-op function, return 0
75 * @hw: pointer to the HW structure
77 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
78 u16 E1000_UNUSEDARG data)
80 DEBUGFUNC("e1000_null_set_page");
81 UNREFERENCED_2PARAMETER(hw, data);
86 * e1000_null_read_reg - No-op function, return 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
90 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
92 DEBUGFUNC("e1000_null_read_reg");
93 UNREFERENCED_3PARAMETER(hw, offset, data);
98 * e1000_null_phy_generic - No-op function, return void
99 * @hw: pointer to the HW structure
101 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
103 DEBUGFUNC("e1000_null_phy_generic");
104 UNREFERENCED_1PARAMETER(hw);
109 * e1000_null_lplu_state - No-op function, return 0
110 * @hw: pointer to the HW structure
112 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
113 bool E1000_UNUSEDARG active)
115 DEBUGFUNC("e1000_null_lplu_state");
116 UNREFERENCED_2PARAMETER(hw, active);
117 return E1000_SUCCESS;
121 * e1000_null_write_reg - No-op function, return 0
122 * @hw: pointer to the HW structure
124 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
125 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
127 DEBUGFUNC("e1000_null_write_reg");
128 UNREFERENCED_3PARAMETER(hw, offset, data);
129 return E1000_SUCCESS;
133 * e1000_read_i2c_byte_null - No-op function, return 0
134 * @hw: pointer to hardware structure
135 * @byte_offset: byte offset to write
136 * @dev_addr: device address
137 * @data: data value read
140 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
141 u8 E1000_UNUSEDARG byte_offset,
142 u8 E1000_UNUSEDARG dev_addr,
143 u8 E1000_UNUSEDARG *data)
145 DEBUGFUNC("e1000_read_i2c_byte_null");
146 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
147 return E1000_SUCCESS;
151 * e1000_write_i2c_byte_null - No-op function, return 0
152 * @hw: pointer to hardware structure
153 * @byte_offset: byte offset to write
154 * @dev_addr: device address
155 * @data: data value to write
158 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
159 u8 E1000_UNUSEDARG byte_offset,
160 u8 E1000_UNUSEDARG dev_addr,
161 u8 E1000_UNUSEDARG data)
163 DEBUGFUNC("e1000_write_i2c_byte_null");
164 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
165 return E1000_SUCCESS;
169 * e1000_check_reset_block_generic - Check if PHY reset is blocked
170 * @hw: pointer to the HW structure
172 * Read the PHY management control register and check whether a PHY reset
173 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
174 * return E1000_BLK_PHY_RESET (12).
176 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
180 DEBUGFUNC("e1000_check_reset_block");
182 manc = E1000_READ_REG(hw, E1000_MANC);
184 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
185 E1000_BLK_PHY_RESET : E1000_SUCCESS;
189 * e1000_get_phy_id - Retrieve the PHY ID and revision
190 * @hw: pointer to the HW structure
192 * Reads the PHY registers and stores the PHY ID and possibly the PHY
193 * revision in the hardware structure.
195 s32 e1000_get_phy_id(struct e1000_hw *hw)
197 struct e1000_phy_info *phy = &hw->phy;
198 s32 ret_val = E1000_SUCCESS;
202 DEBUGFUNC("e1000_get_phy_id");
204 if (!phy->ops.read_reg)
205 return E1000_SUCCESS;
207 while (retry_count < 2) {
208 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
212 phy->id = (u32)(phy_id << 16);
214 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
218 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
219 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
221 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
222 return E1000_SUCCESS;
227 return E1000_SUCCESS;
231 * e1000_phy_reset_dsp_generic - Reset PHY DSP
232 * @hw: pointer to the HW structure
234 * Reset the digital signal processor.
236 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
240 DEBUGFUNC("e1000_phy_reset_dsp_generic");
242 if (!hw->phy.ops.write_reg)
243 return E1000_SUCCESS;
245 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
249 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
253 * e1000_read_phy_reg_mdic - Read MDI control register
254 * @hw: pointer to the HW structure
255 * @offset: register offset to be read
256 * @data: pointer to the read data
258 * Reads the MDI control register in the PHY at offset and stores the
259 * information read to data.
261 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
263 struct e1000_phy_info *phy = &hw->phy;
266 DEBUGFUNC("e1000_read_phy_reg_mdic");
268 if (offset > MAX_PHY_REG_ADDRESS) {
269 DEBUGOUT1("PHY Address %d is out of range\n", offset);
270 return -E1000_ERR_PARAM;
273 /* Set up Op-code, Phy Address, and register offset in the MDI
274 * Control register. The MAC will take care of interfacing with the
275 * PHY to retrieve the desired data.
277 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
278 (phy->addr << E1000_MDIC_PHY_SHIFT) |
279 (E1000_MDIC_OP_READ));
281 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
283 /* Poll the ready bit to see if the MDI read completed
284 * Increasing the time out as testing showed failures with
287 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
289 mdic = E1000_READ_REG(hw, E1000_MDIC);
290 if (mdic & E1000_MDIC_READY)
293 if (!(mdic & E1000_MDIC_READY)) {
294 DEBUGOUT("MDI Read did not complete\n");
295 return -E1000_ERR_PHY;
297 if (mdic & E1000_MDIC_ERROR) {
298 DEBUGOUT("MDI Error\n");
299 return -E1000_ERR_PHY;
301 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
302 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
304 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
305 return -E1000_ERR_PHY;
309 /* Allow some time after each MDIC transaction to avoid
310 * reading duplicate data in the next MDIC transaction.
312 if (hw->mac.type == e1000_pch2lan)
315 return E1000_SUCCESS;
319 * e1000_write_phy_reg_mdic - Write MDI control register
320 * @hw: pointer to the HW structure
321 * @offset: register offset to write to
322 * @data: data to write to register at offset
324 * Writes data to MDI control register in the PHY at offset.
326 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
328 struct e1000_phy_info *phy = &hw->phy;
331 DEBUGFUNC("e1000_write_phy_reg_mdic");
333 if (offset > MAX_PHY_REG_ADDRESS) {
334 DEBUGOUT1("PHY Address %d is out of range\n", offset);
335 return -E1000_ERR_PARAM;
338 /* Set up Op-code, Phy Address, and register offset in the MDI
339 * Control register. The MAC will take care of interfacing with the
340 * PHY to retrieve the desired data.
342 mdic = (((u32)data) |
343 (offset << E1000_MDIC_REG_SHIFT) |
344 (phy->addr << E1000_MDIC_PHY_SHIFT) |
345 (E1000_MDIC_OP_WRITE));
347 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
349 /* Poll the ready bit to see if the MDI read completed
350 * Increasing the time out as testing showed failures with
353 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
355 mdic = E1000_READ_REG(hw, E1000_MDIC);
356 if (mdic & E1000_MDIC_READY)
359 if (!(mdic & E1000_MDIC_READY)) {
360 DEBUGOUT("MDI Write did not complete\n");
361 return -E1000_ERR_PHY;
363 if (mdic & E1000_MDIC_ERROR) {
364 DEBUGOUT("MDI Error\n");
365 return -E1000_ERR_PHY;
367 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
368 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
370 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
371 return -E1000_ERR_PHY;
374 /* Allow some time after each MDIC transaction to avoid
375 * reading duplicate data in the next MDIC transaction.
377 if (hw->mac.type == e1000_pch2lan)
380 return E1000_SUCCESS;
384 * e1000_read_phy_reg_i2c - Read PHY register using i2c
385 * @hw: pointer to the HW structure
386 * @offset: register offset to be read
387 * @data: pointer to the read data
389 * Reads the PHY register at offset using the i2c interface and stores the
390 * retrieved information in data.
392 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
394 struct e1000_phy_info *phy = &hw->phy;
397 DEBUGFUNC("e1000_read_phy_reg_i2c");
399 /* Set up Op-code, Phy Address, and register address in the I2CCMD
400 * register. The MAC will take care of interfacing with the
401 * PHY to retrieve the desired data.
403 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
404 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
405 (E1000_I2CCMD_OPCODE_READ));
407 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
409 /* Poll the ready bit to see if the I2C read completed */
410 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
412 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
413 if (i2ccmd & E1000_I2CCMD_READY)
416 if (!(i2ccmd & E1000_I2CCMD_READY)) {
417 DEBUGOUT("I2CCMD Read did not complete\n");
418 return -E1000_ERR_PHY;
420 if (i2ccmd & E1000_I2CCMD_ERROR) {
421 DEBUGOUT("I2CCMD Error bit set\n");
422 return -E1000_ERR_PHY;
425 /* Need to byte-swap the 16-bit value. */
426 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
428 return E1000_SUCCESS;
432 * e1000_write_phy_reg_i2c - Write PHY register using i2c
433 * @hw: pointer to the HW structure
434 * @offset: register offset to write to
435 * @data: data to write at register offset
437 * Writes the data to PHY register at the offset using the i2c interface.
439 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
441 struct e1000_phy_info *phy = &hw->phy;
443 u16 phy_data_swapped;
445 DEBUGFUNC("e1000_write_phy_reg_i2c");
447 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
448 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
449 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
451 return -E1000_ERR_CONFIG;
454 /* Swap the data bytes for the I2C interface */
455 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
457 /* Set up Op-code, Phy Address, and register address in the I2CCMD
458 * register. The MAC will take care of interfacing with the
459 * PHY to retrieve the desired data.
461 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
462 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
463 E1000_I2CCMD_OPCODE_WRITE |
466 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
468 /* Poll the ready bit to see if the I2C read completed */
469 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
471 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
472 if (i2ccmd & E1000_I2CCMD_READY)
475 if (!(i2ccmd & E1000_I2CCMD_READY)) {
476 DEBUGOUT("I2CCMD Write did not complete\n");
477 return -E1000_ERR_PHY;
479 if (i2ccmd & E1000_I2CCMD_ERROR) {
480 DEBUGOUT("I2CCMD Error bit set\n");
481 return -E1000_ERR_PHY;
484 return E1000_SUCCESS;
488 * e1000_read_sfp_data_byte - Reads SFP module data.
489 * @hw: pointer to the HW structure
490 * @offset: byte location offset to be read
491 * @data: read data buffer pointer
493 * Reads one byte from SFP module data stored
494 * in SFP resided EEPROM memory or SFP diagnostic area.
495 * Function should be called with
496 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
497 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
500 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
506 DEBUGFUNC("e1000_read_sfp_data_byte");
508 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
509 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
510 return -E1000_ERR_PHY;
513 /* Set up Op-code, EEPROM Address,in the I2CCMD
514 * register. The MAC will take care of interfacing with the
515 * EEPROM to retrieve the desired data.
517 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
518 E1000_I2CCMD_OPCODE_READ);
520 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
522 /* Poll the ready bit to see if the I2C read completed */
523 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
525 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
526 if (data_local & E1000_I2CCMD_READY)
529 if (!(data_local & E1000_I2CCMD_READY)) {
530 DEBUGOUT("I2CCMD Read did not complete\n");
531 return -E1000_ERR_PHY;
533 if (data_local & E1000_I2CCMD_ERROR) {
534 DEBUGOUT("I2CCMD Error bit set\n");
535 return -E1000_ERR_PHY;
537 *data = (u8) data_local & 0xFF;
539 return E1000_SUCCESS;
543 * e1000_write_sfp_data_byte - Writes SFP module data.
544 * @hw: pointer to the HW structure
545 * @offset: byte location offset to write to
546 * @data: data to write
548 * Writes one byte to SFP module data stored
549 * in SFP resided EEPROM memory or SFP diagnostic area.
550 * Function should be called with
551 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
552 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
555 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
561 DEBUGFUNC("e1000_write_sfp_data_byte");
563 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
564 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
565 return -E1000_ERR_PHY;
567 /* The programming interface is 16 bits wide
568 * so we need to read the whole word first
569 * then update appropriate byte lane and write
570 * the updated word back.
572 /* Set up Op-code, EEPROM Address,in the I2CCMD
573 * register. The MAC will take care of interfacing
574 * with an EEPROM to write the data given.
576 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
577 E1000_I2CCMD_OPCODE_READ);
578 /* Set a command to read single word */
579 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
580 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
582 /* Poll the ready bit to see if lastly
583 * launched I2C operation completed
585 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
586 if (i2ccmd & E1000_I2CCMD_READY) {
587 /* Check if this is READ or WRITE phase */
588 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
589 E1000_I2CCMD_OPCODE_READ) {
590 /* Write the selected byte
591 * lane and update whole word
593 data_local = i2ccmd & 0xFF00;
596 E1000_I2CCMD_REG_ADDR_SHIFT) |
597 E1000_I2CCMD_OPCODE_WRITE | data_local);
598 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
604 if (!(i2ccmd & E1000_I2CCMD_READY)) {
605 DEBUGOUT("I2CCMD Write did not complete\n");
606 return -E1000_ERR_PHY;
608 if (i2ccmd & E1000_I2CCMD_ERROR) {
609 DEBUGOUT("I2CCMD Error bit set\n");
610 return -E1000_ERR_PHY;
612 return E1000_SUCCESS;
616 * e1000_read_phy_reg_m88 - Read m88 PHY register
617 * @hw: pointer to the HW structure
618 * @offset: register offset to be read
619 * @data: pointer to the read data
621 * Acquires semaphore, if necessary, then reads the PHY register at offset
622 * and storing the retrieved information in data. Release any acquired
623 * semaphores before exiting.
625 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
629 DEBUGFUNC("e1000_read_phy_reg_m88");
631 if (!hw->phy.ops.acquire)
632 return E1000_SUCCESS;
634 ret_val = hw->phy.ops.acquire(hw);
638 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
641 hw->phy.ops.release(hw);
647 * e1000_write_phy_reg_m88 - Write m88 PHY register
648 * @hw: pointer to the HW structure
649 * @offset: register offset to write to
650 * @data: data to write at register offset
652 * Acquires semaphore, if necessary, then writes the data to PHY register
653 * at the offset. Release any acquired semaphores before exiting.
655 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
659 DEBUGFUNC("e1000_write_phy_reg_m88");
661 if (!hw->phy.ops.acquire)
662 return E1000_SUCCESS;
664 ret_val = hw->phy.ops.acquire(hw);
668 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
671 hw->phy.ops.release(hw);
677 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
678 * @hw: pointer to the HW structure
679 * @page: page to set (shifted left when necessary)
681 * Sets PHY page required for PHY register access. Assumes semaphore is
682 * already acquired. Note, this function sets phy.addr to 1 so the caller
683 * must set it appropriately (if necessary) after this function returns.
685 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
687 DEBUGFUNC("e1000_set_page_igp");
689 DEBUGOUT1("Setting page 0x%x\n", page);
693 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
697 * __e1000_read_phy_reg_igp - Read igp PHY register
698 * @hw: pointer to the HW structure
699 * @offset: register offset to be read
700 * @data: pointer to the read data
701 * @locked: semaphore has already been acquired or not
703 * Acquires semaphore, if necessary, then reads the PHY register at offset
704 * and stores the retrieved information in data. Release any acquired
705 * semaphores before exiting.
707 STATIC s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
710 s32 ret_val = E1000_SUCCESS;
712 DEBUGFUNC("__e1000_read_phy_reg_igp");
715 if (!hw->phy.ops.acquire)
716 return E1000_SUCCESS;
718 ret_val = hw->phy.ops.acquire(hw);
723 if (offset > MAX_PHY_MULTI_PAGE_REG)
724 ret_val = e1000_write_phy_reg_mdic(hw,
725 IGP01E1000_PHY_PAGE_SELECT,
728 ret_val = e1000_read_phy_reg_mdic(hw,
729 MAX_PHY_REG_ADDRESS & offset,
732 hw->phy.ops.release(hw);
738 * e1000_read_phy_reg_igp - Read igp PHY register
739 * @hw: pointer to the HW structure
740 * @offset: register offset to be read
741 * @data: pointer to the read data
743 * Acquires semaphore then reads the PHY register at offset and stores the
744 * retrieved information in data.
745 * Release the acquired semaphore before exiting.
747 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
749 return __e1000_read_phy_reg_igp(hw, offset, data, false);
753 * e1000_read_phy_reg_igp_locked - Read igp PHY register
754 * @hw: pointer to the HW structure
755 * @offset: register offset to be read
756 * @data: pointer to the read data
758 * Reads the PHY register at offset and stores the retrieved information
759 * in data. Assumes semaphore already acquired.
761 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
763 return __e1000_read_phy_reg_igp(hw, offset, data, true);
767 * e1000_write_phy_reg_igp - Write igp PHY register
768 * @hw: pointer to the HW structure
769 * @offset: register offset to write to
770 * @data: data to write at register offset
771 * @locked: semaphore has already been acquired or not
773 * Acquires semaphore, if necessary, then writes the data to PHY register
774 * at the offset. Release any acquired semaphores before exiting.
776 STATIC s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
779 s32 ret_val = E1000_SUCCESS;
781 DEBUGFUNC("e1000_write_phy_reg_igp");
784 if (!hw->phy.ops.acquire)
785 return E1000_SUCCESS;
787 ret_val = hw->phy.ops.acquire(hw);
792 if (offset > MAX_PHY_MULTI_PAGE_REG)
793 ret_val = e1000_write_phy_reg_mdic(hw,
794 IGP01E1000_PHY_PAGE_SELECT,
797 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
801 hw->phy.ops.release(hw);
807 * e1000_write_phy_reg_igp - Write igp PHY register
808 * @hw: pointer to the HW structure
809 * @offset: register offset to write to
810 * @data: data to write at register offset
812 * Acquires semaphore then writes the data to PHY register
813 * at the offset. Release any acquired semaphores before exiting.
815 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
817 return __e1000_write_phy_reg_igp(hw, offset, data, false);
821 * e1000_write_phy_reg_igp_locked - Write igp PHY register
822 * @hw: pointer to the HW structure
823 * @offset: register offset to write to
824 * @data: data to write at register offset
826 * Writes the data to PHY register at the offset.
827 * Assumes semaphore already acquired.
829 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
831 return __e1000_write_phy_reg_igp(hw, offset, data, true);
835 * __e1000_read_kmrn_reg - Read kumeran register
836 * @hw: pointer to the HW structure
837 * @offset: register offset to be read
838 * @data: pointer to the read data
839 * @locked: semaphore has already been acquired or not
841 * Acquires semaphore, if necessary. Then reads the PHY register at offset
842 * using the kumeran interface. The information retrieved is stored in data.
843 * Release any acquired semaphores before exiting.
845 STATIC s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
850 DEBUGFUNC("__e1000_read_kmrn_reg");
853 s32 ret_val = E1000_SUCCESS;
855 if (!hw->phy.ops.acquire)
856 return E1000_SUCCESS;
858 ret_val = hw->phy.ops.acquire(hw);
863 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
864 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
865 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
866 E1000_WRITE_FLUSH(hw);
870 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
871 *data = (u16)kmrnctrlsta;
874 hw->phy.ops.release(hw);
876 return E1000_SUCCESS;
880 * e1000_read_kmrn_reg_generic - Read kumeran register
881 * @hw: pointer to the HW structure
882 * @offset: register offset to be read
883 * @data: pointer to the read data
885 * Acquires semaphore then reads the PHY register at offset using the
886 * kumeran interface. The information retrieved is stored in data.
887 * Release the acquired semaphore before exiting.
889 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
891 return __e1000_read_kmrn_reg(hw, offset, data, false);
895 * e1000_read_kmrn_reg_locked - Read kumeran register
896 * @hw: pointer to the HW structure
897 * @offset: register offset to be read
898 * @data: pointer to the read data
900 * Reads the PHY register at offset using the kumeran interface. The
901 * information retrieved is stored in data.
902 * Assumes semaphore already acquired.
904 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
906 return __e1000_read_kmrn_reg(hw, offset, data, true);
910 * __e1000_write_kmrn_reg - Write kumeran register
911 * @hw: pointer to the HW structure
912 * @offset: register offset to write to
913 * @data: data to write at register offset
914 * @locked: semaphore has already been acquired or not
916 * Acquires semaphore, if necessary. Then write the data to PHY register
917 * at the offset using the kumeran interface. Release any acquired semaphores
920 STATIC s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
925 DEBUGFUNC("e1000_write_kmrn_reg_generic");
928 s32 ret_val = E1000_SUCCESS;
930 if (!hw->phy.ops.acquire)
931 return E1000_SUCCESS;
933 ret_val = hw->phy.ops.acquire(hw);
938 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
939 E1000_KMRNCTRLSTA_OFFSET) | data;
940 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
941 E1000_WRITE_FLUSH(hw);
946 hw->phy.ops.release(hw);
948 return E1000_SUCCESS;
952 * e1000_write_kmrn_reg_generic - Write kumeran register
953 * @hw: pointer to the HW structure
954 * @offset: register offset to write to
955 * @data: data to write at register offset
957 * Acquires semaphore then writes the data to the PHY register at the offset
958 * using the kumeran interface. Release the acquired semaphore before exiting.
960 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
962 return __e1000_write_kmrn_reg(hw, offset, data, false);
966 * e1000_write_kmrn_reg_locked - Write kumeran register
967 * @hw: pointer to the HW structure
968 * @offset: register offset to write to
969 * @data: data to write at register offset
971 * Write the data to PHY register at the offset using the kumeran interface.
972 * Assumes semaphore already acquired.
974 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
976 return __e1000_write_kmrn_reg(hw, offset, data, true);
980 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
981 * @hw: pointer to the HW structure
983 * Sets up Master/slave mode
985 STATIC s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
990 /* Resolve Master/Slave mode */
991 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
995 /* load defaults for future use */
996 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
997 ((phy_data & CR_1000T_MS_VALUE) ?
998 e1000_ms_force_master :
999 e1000_ms_force_slave) : e1000_ms_auto;
1001 switch (hw->phy.ms_type) {
1002 case e1000_ms_force_master:
1003 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1005 case e1000_ms_force_slave:
1006 phy_data |= CR_1000T_MS_ENABLE;
1007 phy_data &= ~(CR_1000T_MS_VALUE);
1010 phy_data &= ~CR_1000T_MS_ENABLE;
1016 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1020 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1021 * @hw: pointer to the HW structure
1023 * Sets up Carrier-sense on Transmit and downshift values.
1025 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1030 DEBUGFUNC("e1000_copper_link_setup_82577");
1032 if (hw->phy.type == e1000_phy_82580) {
1033 ret_val = hw->phy.ops.reset(hw);
1035 DEBUGOUT("Error resetting the PHY.\n");
1040 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1041 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1045 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1047 /* Enable downshift */
1048 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1050 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1054 /* Set MDI/MDIX mode */
1055 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1058 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1060 * 0 - Auto (default)
1064 switch (hw->phy.mdix) {
1068 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1072 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1075 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1079 return e1000_set_master_slave_mode(hw);
1083 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1084 * @hw: pointer to the HW structure
1086 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1087 * and downshift values are set also.
1089 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1091 struct e1000_phy_info *phy = &hw->phy;
1095 DEBUGFUNC("e1000_copper_link_setup_m88");
1098 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1099 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1103 /* For BM PHY this bit is downshift enable */
1104 if (phy->type != e1000_phy_bm)
1105 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1108 * MDI/MDI-X = 0 (default)
1109 * 0 - Auto for all speeds
1112 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1114 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1116 switch (phy->mdix) {
1118 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1121 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1124 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1128 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1133 * disable_polarity_correction = 0 (default)
1134 * Automatic Correction for Reversed Cable Polarity
1138 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1139 if (phy->disable_polarity_correction)
1140 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1142 /* Enable downshift on BM (disabled by default) */
1143 if (phy->type == e1000_phy_bm) {
1144 /* For 82574/82583, first disable then enable downshift */
1145 if (phy->id == BME1000_E_PHY_ID_R2) {
1146 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1147 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1151 /* Commit the changes. */
1152 ret_val = phy->ops.commit(hw);
1154 DEBUGOUT("Error committing the PHY changes\n");
1159 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1162 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1166 if ((phy->type == e1000_phy_m88) &&
1167 (phy->revision < E1000_REVISION_4) &&
1168 (phy->id != BME1000_E_PHY_ID_R2)) {
1169 /* Force TX_CLK in the Extended PHY Specific Control Register
1172 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1177 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1179 if ((phy->revision == E1000_REVISION_2) &&
1180 (phy->id == M88E1111_I_PHY_ID)) {
1181 /* 82573L PHY - set the downshift counter to 5x. */
1182 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1183 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1185 /* Configure Master and Slave downshift values */
1186 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1187 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1188 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1189 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1191 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1197 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1198 /* Set PHY page 0, register 29 to 0x0003 */
1199 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1203 /* Set PHY page 0, register 30 to 0x0000 */
1204 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1209 /* Commit the changes. */
1210 ret_val = phy->ops.commit(hw);
1212 DEBUGOUT("Error committing the PHY changes\n");
1216 if (phy->type == e1000_phy_82578) {
1217 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1222 /* 82578 PHY - set the downshift count to 1x. */
1223 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1224 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1225 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1231 return E1000_SUCCESS;
1235 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1236 * @hw: pointer to the HW structure
1238 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1239 * Also enables and sets the downshift parameters.
1241 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1243 struct e1000_phy_info *phy = &hw->phy;
1247 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1250 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1251 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1256 * MDI/MDI-X = 0 (default)
1257 * 0 - Auto for all speeds
1260 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1262 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1264 switch (phy->mdix) {
1266 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1269 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1272 /* M88E1112 does not support this mode) */
1273 if (phy->id != M88E1112_E_PHY_ID) {
1274 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1280 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1285 * disable_polarity_correction = 0 (default)
1286 * Automatic Correction for Reversed Cable Polarity
1290 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1291 if (phy->disable_polarity_correction)
1292 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1294 /* Enable downshift and setting it to X6 */
1295 if (phy->id == M88E1543_E_PHY_ID) {
1296 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1298 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1302 ret_val = phy->ops.commit(hw);
1304 DEBUGOUT("Error committing the PHY changes\n");
1309 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1310 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1311 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1313 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1317 /* Commit the changes. */
1318 ret_val = phy->ops.commit(hw);
1320 DEBUGOUT("Error committing the PHY changes\n");
1324 ret_val = e1000_set_master_slave_mode(hw);
1328 return E1000_SUCCESS;
1332 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1333 * @hw: pointer to the HW structure
1335 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1338 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1340 struct e1000_phy_info *phy = &hw->phy;
1344 DEBUGFUNC("e1000_copper_link_setup_igp");
1347 ret_val = hw->phy.ops.reset(hw);
1349 DEBUGOUT("Error resetting the PHY.\n");
1353 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1354 * timeout issues when LFS is enabled.
1358 /* The NVM settings will configure LPLU in D3 for
1361 if (phy->type == e1000_phy_igp) {
1362 /* disable lplu d3 during driver init */
1363 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1365 DEBUGOUT("Error Disabling LPLU D3\n");
1370 /* disable lplu d0 during driver init */
1371 if (hw->phy.ops.set_d0_lplu_state) {
1372 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1374 DEBUGOUT("Error Disabling LPLU D0\n");
1378 /* Configure mdi-mdix settings */
1379 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1383 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1385 switch (phy->mdix) {
1387 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1390 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1394 data |= IGP01E1000_PSCR_AUTO_MDIX;
1397 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1401 /* set auto-master slave resolution settings */
1402 if (hw->mac.autoneg) {
1403 /* when autonegotiation advertisement is only 1000Mbps then we
1404 * should disable SmartSpeed and enable Auto MasterSlave
1405 * resolution as hardware default.
1407 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1408 /* Disable SmartSpeed */
1409 ret_val = phy->ops.read_reg(hw,
1410 IGP01E1000_PHY_PORT_CONFIG,
1415 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1416 ret_val = phy->ops.write_reg(hw,
1417 IGP01E1000_PHY_PORT_CONFIG,
1422 /* Set auto Master/Slave resolution process */
1423 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1427 data &= ~CR_1000T_MS_ENABLE;
1428 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1433 ret_val = e1000_set_master_slave_mode(hw);
1440 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1441 * @hw: pointer to the HW structure
1443 * Reads the MII auto-neg advertisement register and/or the 1000T control
1444 * register and if the PHY is already setup for auto-negotiation, then
1445 * return successful. Otherwise, setup advertisement and flow control to
1446 * the appropriate values for the wanted auto-negotiation.
1448 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1450 struct e1000_phy_info *phy = &hw->phy;
1452 u16 mii_autoneg_adv_reg;
1453 u16 mii_1000t_ctrl_reg = 0;
1455 DEBUGFUNC("e1000_phy_setup_autoneg");
1457 phy->autoneg_advertised &= phy->autoneg_mask;
1459 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1460 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1464 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1465 /* Read the MII 1000Base-T Control Register (Address 9). */
1466 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1467 &mii_1000t_ctrl_reg);
1472 /* Need to parse both autoneg_advertised and fc and set up
1473 * the appropriate PHY registers. First we will parse for
1474 * autoneg_advertised software override. Since we can advertise
1475 * a plethora of combinations, we need to check each bit
1479 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1480 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1481 * the 1000Base-T Control Register (Address 9).
1483 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1484 NWAY_AR_100TX_HD_CAPS |
1485 NWAY_AR_10T_FD_CAPS |
1486 NWAY_AR_10T_HD_CAPS);
1487 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1489 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1491 /* Do we want to advertise 10 Mb Half Duplex? */
1492 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1493 DEBUGOUT("Advertise 10mb Half duplex\n");
1494 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1497 /* Do we want to advertise 10 Mb Full Duplex? */
1498 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1499 DEBUGOUT("Advertise 10mb Full duplex\n");
1500 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1503 /* Do we want to advertise 100 Mb Half Duplex? */
1504 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1505 DEBUGOUT("Advertise 100mb Half duplex\n");
1506 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1509 /* Do we want to advertise 100 Mb Full Duplex? */
1510 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1511 DEBUGOUT("Advertise 100mb Full duplex\n");
1512 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1515 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1516 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1517 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1519 /* Do we want to advertise 1000 Mb Full Duplex? */
1520 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1521 DEBUGOUT("Advertise 1000mb Full duplex\n");
1522 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1525 /* Check for a software override of the flow control settings, and
1526 * setup the PHY advertisement registers accordingly. If
1527 * auto-negotiation is enabled, then software will have to set the
1528 * "PAUSE" bits to the correct value in the Auto-Negotiation
1529 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1532 * The possible values of the "fc" parameter are:
1533 * 0: Flow control is completely disabled
1534 * 1: Rx flow control is enabled (we can receive pause frames
1535 * but not send pause frames).
1536 * 2: Tx flow control is enabled (we can send pause frames
1537 * but we do not support receiving pause frames).
1538 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1539 * other: No software override. The flow control configuration
1540 * in the EEPROM is used.
1542 switch (hw->fc.current_mode) {
1544 /* Flow control (Rx & Tx) is completely disabled by a
1545 * software over-ride.
1547 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1549 case e1000_fc_rx_pause:
1550 /* Rx Flow control is enabled, and Tx Flow control is
1551 * disabled, by a software over-ride.
1553 * Since there really isn't a way to advertise that we are
1554 * capable of Rx Pause ONLY, we will advertise that we
1555 * support both symmetric and asymmetric Rx PAUSE. Later
1556 * (in e1000_config_fc_after_link_up) we will disable the
1557 * hw's ability to send PAUSE frames.
1559 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1561 case e1000_fc_tx_pause:
1562 /* Tx Flow control is enabled, and Rx Flow control is
1563 * disabled, by a software over-ride.
1565 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1566 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1569 /* Flow control (both Rx and Tx) is enabled by a software
1572 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1575 DEBUGOUT("Flow control param set incorrectly\n");
1576 return -E1000_ERR_CONFIG;
1579 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1583 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1585 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1586 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1587 mii_1000t_ctrl_reg);
1593 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1594 * @hw: pointer to the HW structure
1596 * Performs initial bounds checking on autoneg advertisement parameter, then
1597 * configure to advertise the full capability. Setup the PHY to autoneg
1598 * and restart the negotiation process between the link partner. If
1599 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1601 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1603 struct e1000_phy_info *phy = &hw->phy;
1607 DEBUGFUNC("e1000_copper_link_autoneg");
1609 /* Perform some bounds checking on the autoneg advertisement
1612 phy->autoneg_advertised &= phy->autoneg_mask;
1614 /* If autoneg_advertised is zero, we assume it was not defaulted
1615 * by the calling code so we set to advertise full capability.
1617 if (!phy->autoneg_advertised)
1618 phy->autoneg_advertised = phy->autoneg_mask;
1620 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1621 ret_val = e1000_phy_setup_autoneg(hw);
1623 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1626 DEBUGOUT("Restarting Auto-Neg\n");
1628 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1629 * the Auto Neg Restart bit in the PHY control register.
1631 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1635 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1636 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1640 /* Does the user want to wait for Auto-Neg to complete here, or
1641 * check at a later time (for example, callback routine).
1643 if (phy->autoneg_wait_to_complete) {
1644 ret_val = e1000_wait_autoneg(hw);
1646 DEBUGOUT("Error while waiting for autoneg to complete\n");
1651 hw->mac.get_link_status = true;
1657 * e1000_setup_copper_link_generic - Configure copper link settings
1658 * @hw: pointer to the HW structure
1660 * Calls the appropriate function to configure the link for auto-neg or forced
1661 * speed and duplex. Then we check for link, once link is established calls
1662 * to configure collision distance and flow control are called. If link is
1663 * not established, we return -E1000_ERR_PHY (-2).
1665 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1670 DEBUGFUNC("e1000_setup_copper_link_generic");
1672 if (hw->mac.autoneg) {
1673 /* Setup autoneg and flow control advertisement and perform
1676 ret_val = e1000_copper_link_autoneg(hw);
1680 /* PHY will be set to 10H, 10F, 100H or 100F
1681 * depending on user settings.
1683 DEBUGOUT("Forcing Speed and Duplex\n");
1684 ret_val = hw->phy.ops.force_speed_duplex(hw);
1686 DEBUGOUT("Error Forcing Speed and Duplex\n");
1691 /* Check link status. Wait up to 100 microseconds for link to become
1694 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1700 DEBUGOUT("Valid link established!!!\n");
1701 hw->mac.ops.config_collision_dist(hw);
1702 ret_val = e1000_config_fc_after_link_up_generic(hw);
1704 DEBUGOUT("Unable to establish link!!!\n");
1711 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1712 * @hw: pointer to the HW structure
1714 * Calls the PHY setup function to force speed and duplex. Clears the
1715 * auto-crossover to force MDI manually. Waits for link and returns
1716 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1718 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1720 struct e1000_phy_info *phy = &hw->phy;
1725 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1727 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1731 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1733 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1737 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1738 * forced whenever speed and duplex are forced.
1740 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1744 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1745 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1747 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1751 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1755 if (phy->autoneg_wait_to_complete) {
1756 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1758 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1764 DEBUGOUT("Link taking longer than expected.\n");
1767 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1775 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1776 * @hw: pointer to the HW structure
1778 * Calls the PHY setup function to force speed and duplex. Clears the
1779 * auto-crossover to force MDI manually. Resets the PHY to commit the
1780 * changes. If time expires while waiting for link up, we reset the DSP.
1781 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1782 * successful completion, else return corresponding error code.
1784 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1786 struct e1000_phy_info *phy = &hw->phy;
1791 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1793 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1794 if (phy->type != e1000_phy_i210) {
1795 /* Clear Auto-Crossover to force MDI manually. M88E1000
1796 * requires MDI forced whenever speed and duplex are forced.
1798 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1803 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1804 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1809 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1812 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1816 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1818 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1822 /* Reset the phy to commit changes. */
1823 ret_val = hw->phy.ops.commit(hw);
1827 if (phy->autoneg_wait_to_complete) {
1828 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1830 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1836 bool reset_dsp = true;
1838 switch (hw->phy.id) {
1839 case I347AT4_E_PHY_ID:
1840 case M88E1340M_E_PHY_ID:
1841 case M88E1112_E_PHY_ID:
1842 case M88E1543_E_PHY_ID:
1843 case M88E1512_E_PHY_ID:
1848 if (hw->phy.type != e1000_phy_m88)
1854 DEBUGOUT("Link taking longer than expected.\n");
1856 /* We didn't get link.
1857 * Reset the DSP and cross our fingers.
1859 ret_val = phy->ops.write_reg(hw,
1860 M88E1000_PHY_PAGE_SELECT,
1864 ret_val = e1000_phy_reset_dsp_generic(hw);
1871 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1877 if (hw->phy.type != e1000_phy_m88)
1878 return E1000_SUCCESS;
1880 if (hw->phy.id == I347AT4_E_PHY_ID ||
1881 hw->phy.id == M88E1340M_E_PHY_ID ||
1882 hw->phy.id == M88E1112_E_PHY_ID)
1883 return E1000_SUCCESS;
1884 if (hw->phy.id == I210_I_PHY_ID)
1885 return E1000_SUCCESS;
1886 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1887 (hw->phy.id == M88E1512_E_PHY_ID))
1888 return E1000_SUCCESS;
1889 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1893 /* Resetting the phy means we need to re-force TX_CLK in the
1894 * Extended PHY Specific Control Register to 25MHz clock from
1895 * the reset value of 2.5MHz.
1897 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1898 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1902 /* In addition, we must re-enable CRS on Tx for both half and full
1905 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1909 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1910 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1916 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1917 * @hw: pointer to the HW structure
1919 * Forces the speed and duplex settings of the PHY.
1920 * This is a function pointer entry point only called by
1921 * PHY setup routines.
1923 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1925 struct e1000_phy_info *phy = &hw->phy;
1930 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1932 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1936 e1000_phy_force_speed_duplex_setup(hw, &data);
1938 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1942 /* Disable MDI-X support for 10/100 */
1943 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1947 data &= ~IFE_PMC_AUTO_MDIX;
1948 data &= ~IFE_PMC_FORCE_MDIX;
1950 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1954 DEBUGOUT1("IFE PMC: %X\n", data);
1958 if (phy->autoneg_wait_to_complete) {
1959 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1961 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1967 DEBUGOUT("Link taking longer than expected.\n");
1970 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1976 return E1000_SUCCESS;
1980 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1981 * @hw: pointer to the HW structure
1982 * @phy_ctrl: pointer to current value of PHY_CONTROL
1984 * Forces speed and duplex on the PHY by doing the following: disable flow
1985 * control, force speed/duplex on the MAC, disable auto speed detection,
1986 * disable auto-negotiation, configure duplex, configure speed, configure
1987 * the collision distance, write configuration to CTRL register. The
1988 * caller must write to the PHY_CONTROL register for these settings to
1991 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1993 struct e1000_mac_info *mac = &hw->mac;
1996 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1998 /* Turn off flow control when forcing speed/duplex */
1999 hw->fc.current_mode = e1000_fc_none;
2001 /* Force speed/duplex on the mac */
2002 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2003 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2004 ctrl &= ~E1000_CTRL_SPD_SEL;
2006 /* Disable Auto Speed Detection */
2007 ctrl &= ~E1000_CTRL_ASDE;
2009 /* Disable autoneg on the phy */
2010 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2012 /* Forcing Full or Half Duplex? */
2013 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2014 ctrl &= ~E1000_CTRL_FD;
2015 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2016 DEBUGOUT("Half Duplex\n");
2018 ctrl |= E1000_CTRL_FD;
2019 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2020 DEBUGOUT("Full Duplex\n");
2023 /* Forcing 10mb or 100mb? */
2024 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2025 ctrl |= E1000_CTRL_SPD_100;
2026 *phy_ctrl |= MII_CR_SPEED_100;
2027 *phy_ctrl &= ~MII_CR_SPEED_1000;
2028 DEBUGOUT("Forcing 100mb\n");
2030 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2031 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2032 DEBUGOUT("Forcing 10mb\n");
2035 hw->mac.ops.config_collision_dist(hw);
2037 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2041 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2042 * @hw: pointer to the HW structure
2043 * @active: boolean used to enable/disable lplu
2045 * Success returns 0, Failure returns 1
2047 * The low power link up (lplu) state is set to the power management level D3
2048 * and SmartSpeed is disabled when active is true, else clear lplu for D3
2049 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2050 * is used during Dx states where the power conservation is most important.
2051 * During driver activity, SmartSpeed should be enabled so performance is
2054 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2056 struct e1000_phy_info *phy = &hw->phy;
2060 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2062 if (!hw->phy.ops.read_reg)
2063 return E1000_SUCCESS;
2065 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2070 data &= ~IGP02E1000_PM_D3_LPLU;
2071 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2075 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2076 * during Dx states where the power conservation is most
2077 * important. During driver activity we should enable
2078 * SmartSpeed, so performance is maintained.
2080 if (phy->smart_speed == e1000_smart_speed_on) {
2081 ret_val = phy->ops.read_reg(hw,
2082 IGP01E1000_PHY_PORT_CONFIG,
2087 data |= IGP01E1000_PSCFR_SMART_SPEED;
2088 ret_val = phy->ops.write_reg(hw,
2089 IGP01E1000_PHY_PORT_CONFIG,
2093 } else if (phy->smart_speed == e1000_smart_speed_off) {
2094 ret_val = phy->ops.read_reg(hw,
2095 IGP01E1000_PHY_PORT_CONFIG,
2100 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2101 ret_val = phy->ops.write_reg(hw,
2102 IGP01E1000_PHY_PORT_CONFIG,
2107 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2108 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2109 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2110 data |= IGP02E1000_PM_D3_LPLU;
2111 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2116 /* When LPLU is enabled, we should disable SmartSpeed */
2117 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2122 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2123 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2131 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2132 * @hw: pointer to the HW structure
2134 * Success returns 0, Failure returns 1
2136 * A downshift is detected by querying the PHY link health.
2138 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2140 struct e1000_phy_info *phy = &hw->phy;
2142 u16 phy_data, offset, mask;
2144 DEBUGFUNC("e1000_check_downshift_generic");
2146 switch (phy->type) {
2147 case e1000_phy_i210:
2149 case e1000_phy_gg82563:
2151 case e1000_phy_82578:
2152 offset = M88E1000_PHY_SPEC_STATUS;
2153 mask = M88E1000_PSSR_DOWNSHIFT;
2156 case e1000_phy_igp_2:
2157 case e1000_phy_igp_3:
2158 offset = IGP01E1000_PHY_LINK_HEALTH;
2159 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2162 /* speed downshift not supported */
2163 phy->speed_downgraded = false;
2164 return E1000_SUCCESS;
2167 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2170 phy->speed_downgraded = !!(phy_data & mask);
2176 * e1000_check_polarity_m88 - Checks the polarity.
2177 * @hw: pointer to the HW structure
2179 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2181 * Polarity is determined based on the PHY specific status register.
2183 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2185 struct e1000_phy_info *phy = &hw->phy;
2189 DEBUGFUNC("e1000_check_polarity_m88");
2191 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2194 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2195 ? e1000_rev_polarity_reversed
2196 : e1000_rev_polarity_normal);
2202 * e1000_check_polarity_igp - Checks the polarity.
2203 * @hw: pointer to the HW structure
2205 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2207 * Polarity is determined based on the PHY port status register, and the
2208 * current speed (since there is no polarity at 100Mbps).
2210 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2212 struct e1000_phy_info *phy = &hw->phy;
2214 u16 data, offset, mask;
2216 DEBUGFUNC("e1000_check_polarity_igp");
2218 /* Polarity is determined based on the speed of
2221 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2225 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2226 IGP01E1000_PSSR_SPEED_1000MBPS) {
2227 offset = IGP01E1000_PHY_PCS_INIT_REG;
2228 mask = IGP01E1000_PHY_POLARITY_MASK;
2230 /* This really only applies to 10Mbps since
2231 * there is no polarity for 100Mbps (always 0).
2233 offset = IGP01E1000_PHY_PORT_STATUS;
2234 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2237 ret_val = phy->ops.read_reg(hw, offset, &data);
2240 phy->cable_polarity = ((data & mask)
2241 ? e1000_rev_polarity_reversed
2242 : e1000_rev_polarity_normal);
2248 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2249 * @hw: pointer to the HW structure
2251 * Polarity is determined on the polarity reversal feature being enabled.
2253 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2255 struct e1000_phy_info *phy = &hw->phy;
2257 u16 phy_data, offset, mask;
2259 DEBUGFUNC("e1000_check_polarity_ife");
2261 /* Polarity is determined based on the reversal feature being enabled.
2263 if (phy->polarity_correction) {
2264 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2265 mask = IFE_PESC_POLARITY_REVERSED;
2267 offset = IFE_PHY_SPECIAL_CONTROL;
2268 mask = IFE_PSC_FORCE_POLARITY;
2271 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2274 phy->cable_polarity = ((phy_data & mask)
2275 ? e1000_rev_polarity_reversed
2276 : e1000_rev_polarity_normal);
2282 * e1000_wait_autoneg - Wait for auto-neg completion
2283 * @hw: pointer to the HW structure
2285 * Waits for auto-negotiation to complete or for the auto-negotiation time
2286 * limit to expire, which ever happens first.
2288 STATIC s32 e1000_wait_autoneg(struct e1000_hw *hw)
2290 s32 ret_val = E1000_SUCCESS;
2293 DEBUGFUNC("e1000_wait_autoneg");
2295 if (!hw->phy.ops.read_reg)
2296 return E1000_SUCCESS;
2298 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2299 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2300 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2303 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2306 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2311 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2318 * e1000_phy_has_link_generic - Polls PHY for link
2319 * @hw: pointer to the HW structure
2320 * @iterations: number of times to poll for link
2321 * @usec_interval: delay between polling attempts
2322 * @success: pointer to whether polling was successful or not
2324 * Polls the PHY status register for link, 'iterations' number of times.
2326 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2327 u32 usec_interval, bool *success)
2329 s32 ret_val = E1000_SUCCESS;
2332 DEBUGFUNC("e1000_phy_has_link_generic");
2334 if (!hw->phy.ops.read_reg)
2335 return E1000_SUCCESS;
2337 for (i = 0; i < iterations; i++) {
2338 /* Some PHYs require the PHY_STATUS register to be read
2339 * twice due to the link bit being sticky. No harm doing
2340 * it across the board.
2342 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2344 /* If the first read fails, another entity may have
2345 * ownership of the resources, wait and try again to
2346 * see if they have relinquished the resources yet.
2348 if (usec_interval >= 1000)
2349 msec_delay(usec_interval/1000);
2351 usec_delay(usec_interval);
2353 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2356 if (phy_status & MII_SR_LINK_STATUS)
2358 if (usec_interval >= 1000)
2359 msec_delay(usec_interval/1000);
2361 usec_delay(usec_interval);
2364 *success = (i < iterations);
2370 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2371 * @hw: pointer to the HW structure
2373 * Reads the PHY specific status register to retrieve the cable length
2374 * information. The cable length is determined by averaging the minimum and
2375 * maximum values to get the "average" cable length. The m88 PHY has four
2376 * possible cable length values, which are:
2377 * Register Value Cable Length
2381 * 3 110 - 140 meters
2384 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2386 struct e1000_phy_info *phy = &hw->phy;
2388 u16 phy_data, index;
2390 DEBUGFUNC("e1000_get_cable_length_m88");
2392 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2396 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2397 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2399 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2400 return -E1000_ERR_PHY;
2402 phy->min_cable_length = e1000_m88_cable_length_table[index];
2403 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2405 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2407 return E1000_SUCCESS;
2410 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2412 struct e1000_phy_info *phy = &hw->phy;
2414 u16 phy_data, phy_data2, is_cm;
2415 u16 index, default_page;
2417 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2419 switch (hw->phy.id) {
2421 /* Get cable length from PHY Cable Diagnostics Control Reg */
2422 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2423 (I347AT4_PCDL + phy->addr),
2428 /* Check if the unit of cable length is meters or cm */
2429 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2430 I347AT4_PCDC, &phy_data2);
2434 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2436 /* Populate the phy structure with cable length in meters */
2437 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2438 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2439 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2441 case M88E1543_E_PHY_ID:
2442 case M88E1512_E_PHY_ID:
2443 case M88E1340M_E_PHY_ID:
2444 case I347AT4_E_PHY_ID:
2445 /* Remember the original page select and set it to 7 */
2446 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2451 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2455 /* Get cable length from PHY Cable Diagnostics Control Reg */
2456 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2461 /* Check if the unit of cable length is meters or cm */
2462 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2466 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2468 /* Populate the phy structure with cable length in meters */
2469 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2470 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2471 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2473 /* Reset the page select to its original value */
2474 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2480 case M88E1112_E_PHY_ID:
2481 /* Remember the original page select and set it to 5 */
2482 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2487 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2491 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2496 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2497 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2499 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2500 return -E1000_ERR_PHY;
2502 phy->min_cable_length = e1000_m88_cable_length_table[index];
2503 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2505 phy->cable_length = (phy->min_cable_length +
2506 phy->max_cable_length) / 2;
2508 /* Reset the page select to its original value */
2509 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2516 return -E1000_ERR_PHY;
2523 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2524 * @hw: pointer to the HW structure
2526 * The automatic gain control (agc) normalizes the amplitude of the
2527 * received signal, adjusting for the attenuation produced by the
2528 * cable. By reading the AGC registers, which represent the
2529 * combination of coarse and fine gain value, the value can be put
2530 * into a lookup table to obtain the approximate cable length
2533 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2535 struct e1000_phy_info *phy = &hw->phy;
2537 u16 phy_data, i, agc_value = 0;
2538 u16 cur_agc_index, max_agc_index = 0;
2539 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2540 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2541 IGP02E1000_PHY_AGC_A,
2542 IGP02E1000_PHY_AGC_B,
2543 IGP02E1000_PHY_AGC_C,
2544 IGP02E1000_PHY_AGC_D
2547 DEBUGFUNC("e1000_get_cable_length_igp_2");
2549 /* Read the AGC registers for all channels */
2550 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2551 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2555 /* Getting bits 15:9, which represent the combination of
2556 * coarse and fine gain values. The result is a number
2557 * that can be put into the lookup table to obtain the
2558 * approximate cable length.
2560 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2561 IGP02E1000_AGC_LENGTH_MASK);
2563 /* Array index bound check. */
2564 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2565 (cur_agc_index == 0))
2566 return -E1000_ERR_PHY;
2568 /* Remove min & max AGC values from calculation. */
2569 if (e1000_igp_2_cable_length_table[min_agc_index] >
2570 e1000_igp_2_cable_length_table[cur_agc_index])
2571 min_agc_index = cur_agc_index;
2572 if (e1000_igp_2_cable_length_table[max_agc_index] <
2573 e1000_igp_2_cable_length_table[cur_agc_index])
2574 max_agc_index = cur_agc_index;
2576 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2579 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2580 e1000_igp_2_cable_length_table[max_agc_index]);
2581 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2583 /* Calculate cable length with the error range of +/- 10 meters. */
2584 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2585 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2586 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2588 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2590 return E1000_SUCCESS;
2594 * e1000_get_phy_info_m88 - Retrieve PHY information
2595 * @hw: pointer to the HW structure
2597 * Valid for only copper links. Read the PHY status register (sticky read)
2598 * to verify that link is up. Read the PHY special control register to
2599 * determine the polarity and 10base-T extended distance. Read the PHY
2600 * special status register to determine MDI/MDIx and current speed. If
2601 * speed is 1000, then determine cable length, local and remote receiver.
2603 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2605 struct e1000_phy_info *phy = &hw->phy;
2610 DEBUGFUNC("e1000_get_phy_info_m88");
2612 if (phy->media_type != e1000_media_type_copper) {
2613 DEBUGOUT("Phy info is only valid for copper media\n");
2614 return -E1000_ERR_CONFIG;
2617 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2622 DEBUGOUT("Phy info is only valid if link is up\n");
2623 return -E1000_ERR_CONFIG;
2626 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2630 phy->polarity_correction = !!(phy_data &
2631 M88E1000_PSCR_POLARITY_REVERSAL);
2633 ret_val = e1000_check_polarity_m88(hw);
2637 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2641 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2643 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2644 ret_val = hw->phy.ops.get_cable_length(hw);
2648 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2652 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2653 ? e1000_1000t_rx_status_ok
2654 : e1000_1000t_rx_status_not_ok;
2656 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2657 ? e1000_1000t_rx_status_ok
2658 : e1000_1000t_rx_status_not_ok;
2660 /* Set values to "undefined" */
2661 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2662 phy->local_rx = e1000_1000t_rx_status_undefined;
2663 phy->remote_rx = e1000_1000t_rx_status_undefined;
2670 * e1000_get_phy_info_igp - Retrieve igp PHY information
2671 * @hw: pointer to the HW structure
2673 * Read PHY status to determine if link is up. If link is up, then
2674 * set/determine 10base-T extended distance and polarity correction. Read
2675 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2676 * determine on the cable length, local and remote receiver.
2678 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2680 struct e1000_phy_info *phy = &hw->phy;
2685 DEBUGFUNC("e1000_get_phy_info_igp");
2687 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2692 DEBUGOUT("Phy info is only valid if link is up\n");
2693 return -E1000_ERR_CONFIG;
2696 phy->polarity_correction = true;
2698 ret_val = e1000_check_polarity_igp(hw);
2702 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2706 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2708 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2709 IGP01E1000_PSSR_SPEED_1000MBPS) {
2710 ret_val = phy->ops.get_cable_length(hw);
2714 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2718 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2719 ? e1000_1000t_rx_status_ok
2720 : e1000_1000t_rx_status_not_ok;
2722 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2723 ? e1000_1000t_rx_status_ok
2724 : e1000_1000t_rx_status_not_ok;
2726 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2727 phy->local_rx = e1000_1000t_rx_status_undefined;
2728 phy->remote_rx = e1000_1000t_rx_status_undefined;
2735 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2736 * @hw: pointer to the HW structure
2738 * Populates "phy" structure with various feature states.
2740 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2742 struct e1000_phy_info *phy = &hw->phy;
2747 DEBUGFUNC("e1000_get_phy_info_ife");
2749 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2754 DEBUGOUT("Phy info is only valid if link is up\n");
2755 return -E1000_ERR_CONFIG;
2758 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2761 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2763 if (phy->polarity_correction) {
2764 ret_val = e1000_check_polarity_ife(hw);
2768 /* Polarity is forced */
2769 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2770 ? e1000_rev_polarity_reversed
2771 : e1000_rev_polarity_normal);
2774 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2778 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2780 /* The following parameters are undefined for 10/100 operation. */
2781 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2782 phy->local_rx = e1000_1000t_rx_status_undefined;
2783 phy->remote_rx = e1000_1000t_rx_status_undefined;
2785 return E1000_SUCCESS;
2789 * e1000_phy_sw_reset_generic - PHY software reset
2790 * @hw: pointer to the HW structure
2792 * Does a software reset of the PHY by reading the PHY control register and
2793 * setting/write the control register reset bit to the PHY.
2795 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2800 DEBUGFUNC("e1000_phy_sw_reset_generic");
2802 if (!hw->phy.ops.read_reg)
2803 return E1000_SUCCESS;
2805 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2809 phy_ctrl |= MII_CR_RESET;
2810 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2820 * e1000_phy_hw_reset_generic - PHY hardware reset
2821 * @hw: pointer to the HW structure
2823 * Verify the reset block is not blocking us from resetting. Acquire
2824 * semaphore (if necessary) and read/set/write the device control reset
2825 * bit in the PHY. Wait the appropriate delay time for the device to
2826 * reset and release the semaphore (if necessary).
2828 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2830 struct e1000_phy_info *phy = &hw->phy;
2834 DEBUGFUNC("e1000_phy_hw_reset_generic");
2836 if (phy->ops.check_reset_block) {
2837 ret_val = phy->ops.check_reset_block(hw);
2839 return E1000_SUCCESS;
2842 ret_val = phy->ops.acquire(hw);
2846 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2847 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2848 E1000_WRITE_FLUSH(hw);
2850 usec_delay(phy->reset_delay_us);
2852 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2853 E1000_WRITE_FLUSH(hw);
2857 phy->ops.release(hw);
2859 return phy->ops.get_cfg_done(hw);
2863 * e1000_get_cfg_done_generic - Generic configuration done
2864 * @hw: pointer to the HW structure
2866 * Generic function to wait 10 milli-seconds for configuration to complete
2867 * and return success.
2869 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2871 DEBUGFUNC("e1000_get_cfg_done_generic");
2872 UNREFERENCED_1PARAMETER(hw);
2876 return E1000_SUCCESS;
2880 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2881 * @hw: pointer to the HW structure
2883 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2885 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2887 DEBUGOUT("Running IGP 3 PHY init script\n");
2889 /* PHY init IGP 3 */
2890 /* Enable rise/fall, 10-mode work in class-A */
2891 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2892 /* Remove all caps from Replica path filter */
2893 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2894 /* Bias trimming for ADC, AFE and Driver (Default) */
2895 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2896 /* Increase Hybrid poly bias */
2897 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2898 /* Add 4% to Tx amplitude in Gig mode */
2899 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2900 /* Disable trimming (TTT) */
2901 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2902 /* Poly DC correction to 94.6% + 2% for all channels */
2903 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2904 /* ABS DC correction to 95.9% */
2905 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2906 /* BG temp curve trim */
2907 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2908 /* Increasing ADC OPAMP stage 1 currents to max */
2909 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2910 /* Force 1000 ( required for enabling PHY regs configuration) */
2911 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2912 /* Set upd_freq to 6 */
2913 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2915 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2916 /* Disable adaptive fixed FFE (Default) */
2917 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2918 /* Enable FFE hysteresis */
2919 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2920 /* Fixed FFE for short cable lengths */
2921 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2922 /* Fixed FFE for medium cable lengths */
2923 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2924 /* Fixed FFE for long cable lengths */
2925 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2926 /* Enable Adaptive Clip Threshold */
2927 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2928 /* AHT reset limit to 1 */
2929 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2930 /* Set AHT master delay to 127 msec */
2931 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2932 /* Set scan bits for AHT */
2933 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2934 /* Set AHT Preset bits */
2935 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2936 /* Change integ_factor of channel A to 3 */
2937 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2938 /* Change prop_factor of channels BCD to 8 */
2939 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2940 /* Change cg_icount + enable integbp for channels BCD */
2941 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2942 /* Change cg_icount + enable integbp + change prop_factor_master
2943 * to 8 for channel A
2945 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2946 /* Disable AHT in Slave mode on channel A */
2947 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2948 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2951 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2952 /* Enable restart AN on an1000_dis change */
2953 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2954 /* Enable wh_fifo read clock in 10/100 modes */
2955 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2956 /* Restart AN, Speed selection is 1000 */
2957 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2959 return E1000_SUCCESS;
2963 * e1000_get_phy_type_from_id - Get PHY type from id
2964 * @phy_id: phy_id read from the phy
2966 * Returns the phy type from the id.
2968 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2970 enum e1000_phy_type phy_type = e1000_phy_unknown;
2973 case M88E1000_I_PHY_ID:
2974 case M88E1000_E_PHY_ID:
2975 case M88E1111_I_PHY_ID:
2976 case M88E1011_I_PHY_ID:
2977 case M88E1543_E_PHY_ID:
2978 case M88E1512_E_PHY_ID:
2979 case I347AT4_E_PHY_ID:
2980 case M88E1112_E_PHY_ID:
2981 case M88E1340M_E_PHY_ID:
2982 phy_type = e1000_phy_m88;
2984 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2985 phy_type = e1000_phy_igp_2;
2987 case GG82563_E_PHY_ID:
2988 phy_type = e1000_phy_gg82563;
2990 case IGP03E1000_E_PHY_ID:
2991 phy_type = e1000_phy_igp_3;
2994 case IFE_PLUS_E_PHY_ID:
2995 case IFE_C_E_PHY_ID:
2996 phy_type = e1000_phy_ife;
2998 case BME1000_E_PHY_ID:
2999 case BME1000_E_PHY_ID_R2:
3000 phy_type = e1000_phy_bm;
3002 case I82578_E_PHY_ID:
3003 phy_type = e1000_phy_82578;
3005 case I82577_E_PHY_ID:
3006 phy_type = e1000_phy_82577;
3008 case I82579_E_PHY_ID:
3009 phy_type = e1000_phy_82579;
3012 phy_type = e1000_phy_i217;
3014 case I82580_I_PHY_ID:
3015 phy_type = e1000_phy_82580;
3018 phy_type = e1000_phy_i210;
3021 phy_type = e1000_phy_unknown;
3028 * e1000_determine_phy_address - Determines PHY address.
3029 * @hw: pointer to the HW structure
3031 * This uses a trial and error method to loop through possible PHY
3032 * addresses. It tests each by reading the PHY ID registers and
3033 * checking for a match.
3035 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3039 enum e1000_phy_type phy_type = e1000_phy_unknown;
3041 hw->phy.id = phy_type;
3043 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3044 hw->phy.addr = phy_addr;
3048 e1000_get_phy_id(hw);
3049 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3051 /* If phy_type is valid, break - we found our
3054 if (phy_type != e1000_phy_unknown)
3055 return E1000_SUCCESS;
3062 return -E1000_ERR_PHY_TYPE;
3066 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3067 * @page: page to access
3069 * Returns the phy address for the page requested.
3071 STATIC u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3075 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3082 * e1000_write_phy_reg_bm - Write BM PHY register
3083 * @hw: pointer to the HW structure
3084 * @offset: register offset to write to
3085 * @data: data to write at register offset
3087 * Acquires semaphore, if necessary, then writes the data to PHY register
3088 * at the offset. Release any acquired semaphores before exiting.
3090 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3093 u32 page = offset >> IGP_PAGE_SHIFT;
3095 DEBUGFUNC("e1000_write_phy_reg_bm");
3097 ret_val = hw->phy.ops.acquire(hw);
3101 /* Page 800 works differently than the rest so it has its own func */
3102 if (page == BM_WUC_PAGE) {
3103 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3108 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3110 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3111 u32 page_shift, page_select;
3113 /* Page select is register 31 for phy address 1 and 22 for
3114 * phy address 2 and 3. Page select is shifted only for
3117 if (hw->phy.addr == 1) {
3118 page_shift = IGP_PAGE_SHIFT;
3119 page_select = IGP01E1000_PHY_PAGE_SELECT;
3122 page_select = BM_PHY_PAGE_SELECT;
3125 /* Page is shifted left, PHY expects (page x 32) */
3126 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3127 (page << page_shift));
3132 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3136 hw->phy.ops.release(hw);
3141 * e1000_read_phy_reg_bm - Read BM PHY register
3142 * @hw: pointer to the HW structure
3143 * @offset: register offset to be read
3144 * @data: pointer to the read data
3146 * Acquires semaphore, if necessary, then reads the PHY register at offset
3147 * and storing the retrieved information in data. Release any acquired
3148 * semaphores before exiting.
3150 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3153 u32 page = offset >> IGP_PAGE_SHIFT;
3155 DEBUGFUNC("e1000_read_phy_reg_bm");
3157 ret_val = hw->phy.ops.acquire(hw);
3161 /* Page 800 works differently than the rest so it has its own func */
3162 if (page == BM_WUC_PAGE) {
3163 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3168 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3170 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3171 u32 page_shift, page_select;
3173 /* Page select is register 31 for phy address 1 and 22 for
3174 * phy address 2 and 3. Page select is shifted only for
3177 if (hw->phy.addr == 1) {
3178 page_shift = IGP_PAGE_SHIFT;
3179 page_select = IGP01E1000_PHY_PAGE_SELECT;
3182 page_select = BM_PHY_PAGE_SELECT;
3185 /* Page is shifted left, PHY expects (page x 32) */
3186 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3187 (page << page_shift));
3192 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3195 hw->phy.ops.release(hw);
3200 * e1000_read_phy_reg_bm2 - Read BM PHY register
3201 * @hw: pointer to the HW structure
3202 * @offset: register offset to be read
3203 * @data: pointer to the read data
3205 * Acquires semaphore, if necessary, then reads the PHY register at offset
3206 * and storing the retrieved information in data. Release any acquired
3207 * semaphores before exiting.
3209 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3212 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3214 DEBUGFUNC("e1000_read_phy_reg_bm2");
3216 ret_val = hw->phy.ops.acquire(hw);
3220 /* Page 800 works differently than the rest so it has its own func */
3221 if (page == BM_WUC_PAGE) {
3222 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3229 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3230 /* Page is shifted left, PHY expects (page x 32) */
3231 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3238 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3241 hw->phy.ops.release(hw);
3246 * e1000_write_phy_reg_bm2 - Write BM PHY register
3247 * @hw: pointer to the HW structure
3248 * @offset: register offset to write to
3249 * @data: data to write at register offset
3251 * Acquires semaphore, if necessary, then writes the data to PHY register
3252 * at the offset. Release any acquired semaphores before exiting.
3254 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3257 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3259 DEBUGFUNC("e1000_write_phy_reg_bm2");
3261 ret_val = hw->phy.ops.acquire(hw);
3265 /* Page 800 works differently than the rest so it has its own func */
3266 if (page == BM_WUC_PAGE) {
3267 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3274 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3275 /* Page is shifted left, PHY expects (page x 32) */
3276 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3283 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3287 hw->phy.ops.release(hw);
3292 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3293 * @hw: pointer to the HW structure
3294 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3296 * Assumes semaphore already acquired and phy_reg points to a valid memory
3297 * address to store contents of the BM_WUC_ENABLE_REG register.
3299 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3304 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3307 return -E1000_ERR_PARAM;
3309 /* All page select, port ctrl and wakeup registers use phy address 1 */
3312 /* Select Port Control Registers page */
3313 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3315 DEBUGOUT("Could not set Port Control page\n");
3319 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3321 DEBUGOUT2("Could not read PHY register %d.%d\n",
3322 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3326 /* Enable both PHY wakeup mode and Wakeup register page writes.
3327 * Prevent a power state change by disabling ME and Host PHY wakeup.
3330 temp |= BM_WUC_ENABLE_BIT;
3331 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3333 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3335 DEBUGOUT2("Could not write PHY register %d.%d\n",
3336 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3340 /* Select Host Wakeup Registers page - caller now able to write
3341 * registers on the Wakeup registers page
3343 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3347 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3348 * @hw: pointer to the HW structure
3349 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3351 * Restore BM_WUC_ENABLE_REG to its original value.
3353 * Assumes semaphore already acquired and *phy_reg is the contents of the
3354 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3357 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3361 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3364 return -E1000_ERR_PARAM;
3366 /* Select Port Control Registers page */
3367 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3369 DEBUGOUT("Could not set Port Control page\n");
3373 /* Restore 769.17 to its original value */
3374 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3376 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3377 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3383 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3384 * @hw: pointer to the HW structure
3385 * @offset: register offset to be read or written
3386 * @data: pointer to the data to read or write
3387 * @read: determines if operation is read or write
3388 * @page_set: BM_WUC_PAGE already set and access enabled
3390 * Read the PHY register at offset and store the retrieved information in
3391 * data, or write data to PHY register at offset. Note the procedure to
3392 * access the PHY wakeup registers is different than reading the other PHY
3393 * registers. It works as such:
3394 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3395 * 2) Set page to 800 for host (801 if we were manageability)
3396 * 3) Write the address using the address opcode (0x11)
3397 * 4) Read or write the data using the data opcode (0x12)
3398 * 5) Restore 769.17.2 to its original value
3400 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3401 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3403 * Assumes semaphore is already acquired. When page_set==true, assumes
3404 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3405 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3407 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3408 u16 *data, bool read, bool page_set)
3411 u16 reg = BM_PHY_REG_NUM(offset);
3412 u16 page = BM_PHY_REG_PAGE(offset);
3415 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3417 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3418 if ((hw->mac.type == e1000_pchlan) &&
3419 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3420 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3424 /* Enable access to PHY wakeup registers */
3425 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3427 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3432 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3434 /* Write the Wakeup register page offset value using opcode 0x11 */
3435 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3437 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3442 /* Read the Wakeup register page value using opcode 0x12 */
3443 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3446 /* Write the Wakeup register page value using opcode 0x12 */
3447 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3452 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3457 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3463 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3464 * @hw: pointer to the HW structure
3466 * In the case of a PHY power down to save power, or to turn off link during a
3467 * driver unload, or wake on lan is not enabled, restore the link to previous
3470 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3474 /* The PHY will retain its settings across a power down/up cycle */
3475 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3476 mii_reg &= ~MII_CR_POWER_DOWN;
3477 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3481 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3482 * @hw: pointer to the HW structure
3484 * In the case of a PHY power down to save power, or to turn off link during a
3485 * driver unload, or wake on lan is not enabled, restore the link to previous
3488 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3492 /* The PHY will retain its settings across a power down/up cycle */
3493 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3494 mii_reg |= MII_CR_POWER_DOWN;
3495 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3500 * __e1000_read_phy_reg_hv - Read HV PHY register
3501 * @hw: pointer to the HW structure
3502 * @offset: register offset to be read
3503 * @data: pointer to the read data
3504 * @locked: semaphore has already been acquired or not
3506 * Acquires semaphore, if necessary, then reads the PHY register at offset
3507 * and stores the retrieved information in data. Release any acquired
3508 * semaphore before exiting.
3510 STATIC s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3511 bool locked, bool page_set)
3514 u16 page = BM_PHY_REG_PAGE(offset);
3515 u16 reg = BM_PHY_REG_NUM(offset);
3516 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3518 DEBUGFUNC("__e1000_read_phy_reg_hv");
3521 ret_val = hw->phy.ops.acquire(hw);
3525 /* Page 800 works differently than the rest so it has its own func */
3526 if (page == BM_WUC_PAGE) {
3527 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3532 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3533 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3539 if (page == HV_INTC_FC_PAGE_START)
3542 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3543 /* Page is shifted left, PHY expects (page x 32) */
3544 ret_val = e1000_set_page_igp(hw,
3545 (page << IGP_PAGE_SHIFT));
3547 hw->phy.addr = phy_addr;
3554 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3555 page << IGP_PAGE_SHIFT, reg);
3557 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3561 hw->phy.ops.release(hw);
3567 * e1000_read_phy_reg_hv - Read HV PHY register
3568 * @hw: pointer to the HW structure
3569 * @offset: register offset to be read
3570 * @data: pointer to the read data
3572 * Acquires semaphore then reads the PHY register at offset and stores
3573 * the retrieved information in data. Release the acquired semaphore
3576 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3578 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3582 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3583 * @hw: pointer to the HW structure
3584 * @offset: register offset to be read
3585 * @data: pointer to the read data
3587 * Reads the PHY register at offset and stores the retrieved information
3588 * in data. Assumes semaphore already acquired.
3590 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3592 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3596 * e1000_read_phy_reg_page_hv - Read HV PHY register
3597 * @hw: pointer to the HW structure
3598 * @offset: register offset to write to
3599 * @data: data to write at register offset
3601 * Reads the PHY register at offset and stores the retrieved information
3602 * in data. Assumes semaphore already acquired and page already set.
3604 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3606 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3610 * __e1000_write_phy_reg_hv - Write HV PHY register
3611 * @hw: pointer to the HW structure
3612 * @offset: register offset to write to
3613 * @data: data to write at register offset
3614 * @locked: semaphore has already been acquired or not
3616 * Acquires semaphore, if necessary, then writes the data to PHY register
3617 * at the offset. Release any acquired semaphores before exiting.
3619 STATIC s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3620 bool locked, bool page_set)
3623 u16 page = BM_PHY_REG_PAGE(offset);
3624 u16 reg = BM_PHY_REG_NUM(offset);
3625 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3627 DEBUGFUNC("__e1000_write_phy_reg_hv");
3630 ret_val = hw->phy.ops.acquire(hw);
3634 /* Page 800 works differently than the rest so it has its own func */
3635 if (page == BM_WUC_PAGE) {
3636 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3641 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3642 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3648 if (page == HV_INTC_FC_PAGE_START)
3651 /* Workaround MDIO accesses being disabled after entering IEEE
3652 * Power Down (when bit 11 of the PHY Control register is set)
3654 if ((hw->phy.type == e1000_phy_82578) &&
3655 (hw->phy.revision >= 1) &&
3656 (hw->phy.addr == 2) &&
3657 !(MAX_PHY_REG_ADDRESS & reg) &&
3658 (data & (1 << 11))) {
3660 ret_val = e1000_access_phy_debug_regs_hv(hw,
3667 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3668 /* Page is shifted left, PHY expects (page x 32) */
3669 ret_val = e1000_set_page_igp(hw,
3670 (page << IGP_PAGE_SHIFT));
3672 hw->phy.addr = phy_addr;
3679 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3680 page << IGP_PAGE_SHIFT, reg);
3682 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3687 hw->phy.ops.release(hw);
3693 * e1000_write_phy_reg_hv - Write HV PHY register
3694 * @hw: pointer to the HW structure
3695 * @offset: register offset to write to
3696 * @data: data to write at register offset
3698 * Acquires semaphore then writes the data to PHY register at the offset.
3699 * Release the acquired semaphores before exiting.
3701 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3703 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3707 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3708 * @hw: pointer to the HW structure
3709 * @offset: register offset to write to
3710 * @data: data to write at register offset
3712 * Writes the data to PHY register at the offset. Assumes semaphore
3715 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3717 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3721 * e1000_write_phy_reg_page_hv - Write HV PHY register
3722 * @hw: pointer to the HW structure
3723 * @offset: register offset to write to
3724 * @data: data to write at register offset
3726 * Writes the data to PHY register at the offset. Assumes semaphore
3727 * already acquired and page already set.
3729 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3731 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3735 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3736 * @page: page to be accessed
3738 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page)
3742 if (page >= HV_INTC_FC_PAGE_START)
3749 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3750 * @hw: pointer to the HW structure
3751 * @offset: register offset to be read or written
3752 * @data: pointer to the data to be read or written
3753 * @read: determines if operation is read or write
3755 * Reads the PHY register at offset and stores the retreived information
3756 * in data. Assumes semaphore already acquired. Note that the procedure
3757 * to access these regs uses the address port and data port to read/write.
3758 * These accesses done with PHY address 2 and without using pages.
3760 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3761 u16 *data, bool read)
3767 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3769 /* This takes care of the difference with desktop vs mobile phy */
3770 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3771 I82578_ADDR_REG : I82577_ADDR_REG);
3772 data_reg = addr_reg + 1;
3774 /* All operations in this function are phy address 2 */
3777 /* masking with 0x3F to remove the page from offset */
3778 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3780 DEBUGOUT("Could not write the Address Offset port register\n");
3784 /* Read or write the data value next */
3786 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3788 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3791 DEBUGOUT("Could not access the Data port register\n");
3797 * e1000_link_stall_workaround_hv - Si workaround
3798 * @hw: pointer to the HW structure
3800 * This function works around a Si bug where the link partner can get
3801 * a link up indication before the PHY does. If small packets are sent
3802 * by the link partner they can be placed in the packet buffer without
3803 * being properly accounted for by the PHY and will stall preventing
3804 * further packets from being received. The workaround is to clear the
3805 * packet buffer after the PHY detects link up.
3807 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3809 s32 ret_val = E1000_SUCCESS;
3812 DEBUGFUNC("e1000_link_stall_workaround_hv");
3814 if (hw->phy.type != e1000_phy_82578)
3815 return E1000_SUCCESS;
3817 /* Do not apply workaround if in PHY loopback bit 14 set */
3818 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3819 if (data & PHY_CONTROL_LB)
3820 return E1000_SUCCESS;
3822 /* check if link is up and at 1Gbps */
3823 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3827 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3828 BM_CS_STATUS_SPEED_MASK);
3830 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3831 BM_CS_STATUS_SPEED_1000))
3832 return E1000_SUCCESS;
3836 /* flush the packets in the fifo buffer */
3837 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3838 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3839 HV_MUX_DATA_CTRL_FORCE_SPEED));
3843 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3844 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3848 * e1000_check_polarity_82577 - Checks the polarity.
3849 * @hw: pointer to the HW structure
3851 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3853 * Polarity is determined based on the PHY specific status register.
3855 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3857 struct e1000_phy_info *phy = &hw->phy;
3861 DEBUGFUNC("e1000_check_polarity_82577");
3863 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3866 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3867 ? e1000_rev_polarity_reversed
3868 : e1000_rev_polarity_normal);
3874 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3875 * @hw: pointer to the HW structure
3877 * Calls the PHY setup function to force speed and duplex.
3879 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3881 struct e1000_phy_info *phy = &hw->phy;
3886 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3888 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3892 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3894 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3900 if (phy->autoneg_wait_to_complete) {
3901 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3903 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3909 DEBUGOUT("Link taking longer than expected.\n");
3912 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3920 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3921 * @hw: pointer to the HW structure
3923 * Read PHY status to determine if link is up. If link is up, then
3924 * set/determine 10base-T extended distance and polarity correction. Read
3925 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3926 * determine on the cable length, local and remote receiver.
3928 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3930 struct e1000_phy_info *phy = &hw->phy;
3935 DEBUGFUNC("e1000_get_phy_info_82577");
3937 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3942 DEBUGOUT("Phy info is only valid if link is up\n");
3943 return -E1000_ERR_CONFIG;
3946 phy->polarity_correction = true;
3948 ret_val = e1000_check_polarity_82577(hw);
3952 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3956 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3958 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3959 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3960 ret_val = hw->phy.ops.get_cable_length(hw);
3964 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3968 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3969 ? e1000_1000t_rx_status_ok
3970 : e1000_1000t_rx_status_not_ok;
3972 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3973 ? e1000_1000t_rx_status_ok
3974 : e1000_1000t_rx_status_not_ok;
3976 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3977 phy->local_rx = e1000_1000t_rx_status_undefined;
3978 phy->remote_rx = e1000_1000t_rx_status_undefined;
3981 return E1000_SUCCESS;
3985 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3986 * @hw: pointer to the HW structure
3988 * Reads the diagnostic status register and verifies result is valid before
3989 * placing it in the phy_cable_length field.
3991 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3993 struct e1000_phy_info *phy = &hw->phy;
3995 u16 phy_data, length;
3997 DEBUGFUNC("e1000_get_cable_length_82577");
3999 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4003 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4004 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4006 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4007 return -E1000_ERR_PHY;
4009 phy->cable_length = length;
4011 return E1000_SUCCESS;
4015 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4016 * @hw: pointer to the HW structure
4017 * @offset: register offset to write to
4018 * @data: data to write at register offset
4020 * Acquires semaphore, if necessary, then writes the data to PHY register
4021 * at the offset. Release any acquired semaphores before exiting.
4023 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4026 u16 page = offset >> GS40G_PAGE_SHIFT;
4028 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4030 offset = offset & GS40G_OFFSET_MASK;
4031 ret_val = hw->phy.ops.acquire(hw);
4035 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4038 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4041 hw->phy.ops.release(hw);
4046 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4047 * @hw: pointer to the HW structure
4048 * @offset: lower half is register offset to read to
4049 * upper half is page to use.
4050 * @data: data to read at register offset
4052 * Acquires semaphore, if necessary, then reads the data in the PHY register
4053 * at the offset. Release any acquired semaphores before exiting.
4055 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4058 u16 page = offset >> GS40G_PAGE_SHIFT;
4060 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4062 offset = offset & GS40G_OFFSET_MASK;
4063 ret_val = hw->phy.ops.acquire(hw);
4067 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4070 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4073 hw->phy.ops.release(hw);
4078 * e1000_read_phy_reg_mphy - Read mPHY control register
4079 * @hw: pointer to the HW structure
4080 * @address: address to be read
4081 * @data: pointer to the read data
4083 * Reads the mPHY control register in the PHY at offset and stores the
4084 * information read to data.
4086 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4089 bool locked = false;
4092 DEBUGFUNC("e1000_read_phy_reg_mphy");
4094 /* Check if mPHY is ready to read/write operations */
4095 ready = e1000_is_mphy_ready(hw);
4097 return -E1000_ERR_PHY;
4099 /* Check if mPHY access is disabled and enable it if so */
4100 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4101 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4103 ready = e1000_is_mphy_ready(hw);
4105 return -E1000_ERR_PHY;
4106 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4107 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4110 /* Set the address that we want to read */
4111 ready = e1000_is_mphy_ready(hw);
4113 return -E1000_ERR_PHY;
4115 /* We mask address, because we want to use only current lane */
4116 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4117 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4118 (address & E1000_MPHY_ADDRESS_MASK);
4119 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4121 /* Read data from the address */
4122 ready = e1000_is_mphy_ready(hw);
4124 return -E1000_ERR_PHY;
4125 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4127 /* Disable access to mPHY if it was originally disabled */
4129 ready = e1000_is_mphy_ready(hw);
4131 return -E1000_ERR_PHY;
4132 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4133 E1000_MPHY_DIS_ACCESS);
4136 return E1000_SUCCESS;
4140 * e1000_write_phy_reg_mphy - Write mPHY control register
4141 * @hw: pointer to the HW structure
4142 * @address: address to write to
4143 * @data: data to write to register at offset
4144 * @line_override: used when we want to use different line than default one
4146 * Writes data to mPHY control register.
4148 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4152 bool locked = false;
4155 DEBUGFUNC("e1000_write_phy_reg_mphy");
4157 /* Check if mPHY is ready to read/write operations */
4158 ready = e1000_is_mphy_ready(hw);
4160 return -E1000_ERR_PHY;
4162 /* Check if mPHY access is disabled and enable it if so */
4163 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4164 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4166 ready = e1000_is_mphy_ready(hw);
4168 return -E1000_ERR_PHY;
4169 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4170 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4173 /* Set the address that we want to read */
4174 ready = e1000_is_mphy_ready(hw);
4176 return -E1000_ERR_PHY;
4178 /* We mask address, because we want to use only current lane */
4180 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4182 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4183 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4184 (address & E1000_MPHY_ADDRESS_MASK);
4185 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4187 /* Read data from the address */
4188 ready = e1000_is_mphy_ready(hw);
4190 return -E1000_ERR_PHY;
4191 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4193 /* Disable access to mPHY if it was originally disabled */
4195 ready = e1000_is_mphy_ready(hw);
4197 return -E1000_ERR_PHY;
4198 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4199 E1000_MPHY_DIS_ACCESS);
4202 return E1000_SUCCESS;
4206 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4207 * @hw: pointer to the HW structure
4209 * Returns mPHY control register status.
4211 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4213 u16 retry_count = 0;
4217 while (retry_count < 2) {
4218 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4219 if (mphy_ctrl & E1000_MPHY_BUSY) {
4229 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4235 * __e1000_access_xmdio_reg - Read/write XMDIO register
4236 * @hw: pointer to the HW structure
4237 * @address: XMDIO address to program
4238 * @dev_addr: device address to program
4239 * @data: pointer to value to read/write from/to the XMDIO address
4240 * @read: boolean flag to indicate read or write
4242 STATIC s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
4243 u8 dev_addr, u16 *data, bool read)
4247 DEBUGFUNC("__e1000_access_xmdio_reg");
4249 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
4253 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
4257 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
4263 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
4265 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
4269 /* Recalibrate the device back to 0 */
4270 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
4278 * e1000_read_xmdio_reg - Read XMDIO register
4279 * @hw: pointer to the HW structure
4280 * @addr: XMDIO address to program
4281 * @dev_addr: device address to program
4282 * @data: value to be read from the EMI address
4284 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
4286 DEBUGFUNC("e1000_read_xmdio_reg");
4288 return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);
4292 * e1000_write_xmdio_reg - Write XMDIO register
4293 * @hw: pointer to the HW structure
4294 * @addr: XMDIO address to program
4295 * @dev_addr: device address to program
4296 * @data: value to be written to the XMDIO address
4298 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
4300 DEBUGFUNC("e1000_write_xmdio_reg");
4302 return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data,