1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
7 STATIC s32 e1000_wait_autoneg(struct e1000_hw *hw);
8 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
9 u16 *data, bool read, bool page_set);
10 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page);
11 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
12 u16 *data, bool read);
14 /* Cable length tables */
15 STATIC const u16 e1000_m88_cable_length_table[] = {
16 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
17 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
18 (sizeof(e1000_m88_cable_length_table) / \
19 sizeof(e1000_m88_cable_length_table[0]))
21 STATIC const u16 e1000_igp_2_cable_length_table[] = {
22 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
23 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
24 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
25 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
26 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
27 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
28 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
30 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
31 (sizeof(e1000_igp_2_cable_length_table) / \
32 sizeof(e1000_igp_2_cable_length_table[0]))
35 * e1000_init_phy_ops_generic - Initialize PHY function pointers
36 * @hw: pointer to the HW structure
38 * Setups up the function pointers to no-op functions
40 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
42 struct e1000_phy_info *phy = &hw->phy;
43 DEBUGFUNC("e1000_init_phy_ops_generic");
45 /* Initialize function pointers */
46 phy->ops.init_params = e1000_null_ops_generic;
47 phy->ops.acquire = e1000_null_ops_generic;
48 phy->ops.check_polarity = e1000_null_ops_generic;
49 phy->ops.check_reset_block = e1000_null_ops_generic;
50 phy->ops.commit = e1000_null_ops_generic;
51 phy->ops.force_speed_duplex = e1000_null_ops_generic;
52 phy->ops.get_cfg_done = e1000_null_ops_generic;
53 phy->ops.get_cable_length = e1000_null_ops_generic;
54 phy->ops.get_info = e1000_null_ops_generic;
55 phy->ops.set_page = e1000_null_set_page;
56 phy->ops.read_reg = e1000_null_read_reg;
57 phy->ops.read_reg_locked = e1000_null_read_reg;
58 phy->ops.read_reg_page = e1000_null_read_reg;
59 phy->ops.release = e1000_null_phy_generic;
60 phy->ops.reset = e1000_null_ops_generic;
61 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
62 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
63 phy->ops.write_reg = e1000_null_write_reg;
64 phy->ops.write_reg_locked = e1000_null_write_reg;
65 phy->ops.write_reg_page = e1000_null_write_reg;
66 phy->ops.power_up = e1000_null_phy_generic;
67 phy->ops.power_down = e1000_null_phy_generic;
68 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
69 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
70 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
74 * e1000_null_set_page - No-op function, return 0
75 * @hw: pointer to the HW structure
77 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
78 u16 E1000_UNUSEDARG data)
80 DEBUGFUNC("e1000_null_set_page");
81 UNREFERENCED_2PARAMETER(hw, data);
86 * e1000_null_read_reg - No-op function, return 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
90 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
92 DEBUGFUNC("e1000_null_read_reg");
93 UNREFERENCED_3PARAMETER(hw, offset, data);
98 * e1000_null_phy_generic - No-op function, return void
99 * @hw: pointer to the HW structure
101 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
103 DEBUGFUNC("e1000_null_phy_generic");
104 UNREFERENCED_1PARAMETER(hw);
109 * e1000_null_lplu_state - No-op function, return 0
110 * @hw: pointer to the HW structure
112 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
113 bool E1000_UNUSEDARG active)
115 DEBUGFUNC("e1000_null_lplu_state");
116 UNREFERENCED_2PARAMETER(hw, active);
117 return E1000_SUCCESS;
121 * e1000_null_write_reg - No-op function, return 0
122 * @hw: pointer to the HW structure
124 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
125 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
127 DEBUGFUNC("e1000_null_write_reg");
128 UNREFERENCED_3PARAMETER(hw, offset, data);
129 return E1000_SUCCESS;
133 * e1000_read_i2c_byte_null - No-op function, return 0
134 * @hw: pointer to hardware structure
135 * @byte_offset: byte offset to write
136 * @dev_addr: device address
137 * @data: data value read
140 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
141 u8 E1000_UNUSEDARG byte_offset,
142 u8 E1000_UNUSEDARG dev_addr,
143 u8 E1000_UNUSEDARG *data)
145 DEBUGFUNC("e1000_read_i2c_byte_null");
146 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
147 return E1000_SUCCESS;
151 * e1000_write_i2c_byte_null - No-op function, return 0
152 * @hw: pointer to hardware structure
153 * @byte_offset: byte offset to write
154 * @dev_addr: device address
155 * @data: data value to write
158 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
159 u8 E1000_UNUSEDARG byte_offset,
160 u8 E1000_UNUSEDARG dev_addr,
161 u8 E1000_UNUSEDARG data)
163 DEBUGFUNC("e1000_write_i2c_byte_null");
164 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
165 return E1000_SUCCESS;
169 * e1000_check_reset_block_generic - Check if PHY reset is blocked
170 * @hw: pointer to the HW structure
172 * Read the PHY management control register and check whether a PHY reset
173 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
174 * return E1000_BLK_PHY_RESET (12).
176 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
180 DEBUGFUNC("e1000_check_reset_block");
182 manc = E1000_READ_REG(hw, E1000_MANC);
184 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
185 E1000_BLK_PHY_RESET : E1000_SUCCESS;
189 * e1000_get_phy_id - Retrieve the PHY ID and revision
190 * @hw: pointer to the HW structure
192 * Reads the PHY registers and stores the PHY ID and possibly the PHY
193 * revision in the hardware structure.
195 s32 e1000_get_phy_id(struct e1000_hw *hw)
197 struct e1000_phy_info *phy = &hw->phy;
198 s32 ret_val = E1000_SUCCESS;
202 DEBUGFUNC("e1000_get_phy_id");
204 if (!phy->ops.read_reg)
205 return E1000_SUCCESS;
207 while (retry_count < 2) {
208 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
212 phy->id = (u32)(phy_id << 16);
214 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
218 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
219 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
221 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
222 return E1000_SUCCESS;
227 return E1000_SUCCESS;
231 * e1000_phy_reset_dsp_generic - Reset PHY DSP
232 * @hw: pointer to the HW structure
234 * Reset the digital signal processor.
236 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
240 DEBUGFUNC("e1000_phy_reset_dsp_generic");
242 if (!hw->phy.ops.write_reg)
243 return E1000_SUCCESS;
245 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
249 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
253 * e1000_read_phy_reg_mdic - Read MDI control register
254 * @hw: pointer to the HW structure
255 * @offset: register offset to be read
256 * @data: pointer to the read data
258 * Reads the MDI control register in the PHY at offset and stores the
259 * information read to data.
261 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
263 struct e1000_phy_info *phy = &hw->phy;
266 DEBUGFUNC("e1000_read_phy_reg_mdic");
268 if (offset > MAX_PHY_REG_ADDRESS) {
269 DEBUGOUT1("PHY Address %d is out of range\n", offset);
270 return -E1000_ERR_PARAM;
273 /* Set up Op-code, Phy Address, and register offset in the MDI
274 * Control register. The MAC will take care of interfacing with the
275 * PHY to retrieve the desired data.
277 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
278 (phy->addr << E1000_MDIC_PHY_SHIFT) |
279 (E1000_MDIC_OP_READ));
281 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
283 /* Poll the ready bit to see if the MDI read completed
284 * Increasing the time out as testing showed failures with
287 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
289 mdic = E1000_READ_REG(hw, E1000_MDIC);
290 if (mdic & E1000_MDIC_READY)
293 if (!(mdic & E1000_MDIC_READY)) {
294 DEBUGOUT("MDI Read did not complete\n");
295 return -E1000_ERR_PHY;
297 if (mdic & E1000_MDIC_ERROR) {
298 DEBUGOUT("MDI Error\n");
299 return -E1000_ERR_PHY;
301 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
302 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
304 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
305 return -E1000_ERR_PHY;
309 /* Allow some time after each MDIC transaction to avoid
310 * reading duplicate data in the next MDIC transaction.
312 if (hw->mac.type == e1000_pch2lan)
315 return E1000_SUCCESS;
319 * e1000_write_phy_reg_mdic - Write MDI control register
320 * @hw: pointer to the HW structure
321 * @offset: register offset to write to
322 * @data: data to write to register at offset
324 * Writes data to MDI control register in the PHY at offset.
326 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
328 struct e1000_phy_info *phy = &hw->phy;
331 DEBUGFUNC("e1000_write_phy_reg_mdic");
333 if (offset > MAX_PHY_REG_ADDRESS) {
334 DEBUGOUT1("PHY Address %d is out of range\n", offset);
335 return -E1000_ERR_PARAM;
338 /* Set up Op-code, Phy Address, and register offset in the MDI
339 * Control register. The MAC will take care of interfacing with the
340 * PHY to retrieve the desired data.
342 mdic = (((u32)data) |
343 (offset << E1000_MDIC_REG_SHIFT) |
344 (phy->addr << E1000_MDIC_PHY_SHIFT) |
345 (E1000_MDIC_OP_WRITE));
347 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
349 /* Poll the ready bit to see if the MDI read completed
350 * Increasing the time out as testing showed failures with
353 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
355 mdic = E1000_READ_REG(hw, E1000_MDIC);
356 if (mdic & E1000_MDIC_READY)
359 if (!(mdic & E1000_MDIC_READY)) {
360 DEBUGOUT("MDI Write did not complete\n");
361 return -E1000_ERR_PHY;
363 if (mdic & E1000_MDIC_ERROR) {
364 DEBUGOUT("MDI Error\n");
365 return -E1000_ERR_PHY;
367 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
368 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
370 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
371 return -E1000_ERR_PHY;
374 /* Allow some time after each MDIC transaction to avoid
375 * reading duplicate data in the next MDIC transaction.
377 if (hw->mac.type == e1000_pch2lan)
380 return E1000_SUCCESS;
384 * e1000_read_phy_reg_i2c - Read PHY register using i2c
385 * @hw: pointer to the HW structure
386 * @offset: register offset to be read
387 * @data: pointer to the read data
389 * Reads the PHY register at offset using the i2c interface and stores the
390 * retrieved information in data.
392 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
394 struct e1000_phy_info *phy = &hw->phy;
397 DEBUGFUNC("e1000_read_phy_reg_i2c");
399 /* Set up Op-code, Phy Address, and register address in the I2CCMD
400 * register. The MAC will take care of interfacing with the
401 * PHY to retrieve the desired data.
403 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
404 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
405 (E1000_I2CCMD_OPCODE_READ));
407 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
409 /* Poll the ready bit to see if the I2C read completed */
410 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
412 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
413 if (i2ccmd & E1000_I2CCMD_READY)
416 if (!(i2ccmd & E1000_I2CCMD_READY)) {
417 DEBUGOUT("I2CCMD Read did not complete\n");
418 return -E1000_ERR_PHY;
420 if (i2ccmd & E1000_I2CCMD_ERROR) {
421 DEBUGOUT("I2CCMD Error bit set\n");
422 return -E1000_ERR_PHY;
425 /* Need to byte-swap the 16-bit value. */
426 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
428 return E1000_SUCCESS;
432 * e1000_write_phy_reg_i2c - Write PHY register using i2c
433 * @hw: pointer to the HW structure
434 * @offset: register offset to write to
435 * @data: data to write at register offset
437 * Writes the data to PHY register at the offset using the i2c interface.
439 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
441 struct e1000_phy_info *phy = &hw->phy;
443 u16 phy_data_swapped;
445 DEBUGFUNC("e1000_write_phy_reg_i2c");
447 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
448 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
449 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
451 return -E1000_ERR_CONFIG;
454 /* Swap the data bytes for the I2C interface */
455 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
457 /* Set up Op-code, Phy Address, and register address in the I2CCMD
458 * register. The MAC will take care of interfacing with the
459 * PHY to retrieve the desired data.
461 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
462 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
463 E1000_I2CCMD_OPCODE_WRITE |
466 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
468 /* Poll the ready bit to see if the I2C read completed */
469 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
471 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
472 if (i2ccmd & E1000_I2CCMD_READY)
475 if (!(i2ccmd & E1000_I2CCMD_READY)) {
476 DEBUGOUT("I2CCMD Write did not complete\n");
477 return -E1000_ERR_PHY;
479 if (i2ccmd & E1000_I2CCMD_ERROR) {
480 DEBUGOUT("I2CCMD Error bit set\n");
481 return -E1000_ERR_PHY;
484 return E1000_SUCCESS;
488 * e1000_read_sfp_data_byte - Reads SFP module data.
489 * @hw: pointer to the HW structure
490 * @offset: byte location offset to be read
491 * @data: read data buffer pointer
493 * Reads one byte from SFP module data stored
494 * in SFP resided EEPROM memory or SFP diagnostic area.
495 * Function should be called with
496 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
497 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
500 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
506 DEBUGFUNC("e1000_read_sfp_data_byte");
508 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
509 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
510 return -E1000_ERR_PHY;
513 /* Set up Op-code, EEPROM Address,in the I2CCMD
514 * register. The MAC will take care of interfacing with the
515 * EEPROM to retrieve the desired data.
517 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
518 E1000_I2CCMD_OPCODE_READ);
520 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
522 /* Poll the ready bit to see if the I2C read completed */
523 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
525 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
526 if (data_local & E1000_I2CCMD_READY)
529 if (!(data_local & E1000_I2CCMD_READY)) {
530 DEBUGOUT("I2CCMD Read did not complete\n");
531 return -E1000_ERR_PHY;
533 if (data_local & E1000_I2CCMD_ERROR) {
534 DEBUGOUT("I2CCMD Error bit set\n");
535 return -E1000_ERR_PHY;
537 *data = (u8) data_local & 0xFF;
539 return E1000_SUCCESS;
543 * e1000_write_sfp_data_byte - Writes SFP module data.
544 * @hw: pointer to the HW structure
545 * @offset: byte location offset to write to
546 * @data: data to write
548 * Writes one byte to SFP module data stored
549 * in SFP resided EEPROM memory or SFP diagnostic area.
550 * Function should be called with
551 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
552 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
555 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
561 DEBUGFUNC("e1000_write_sfp_data_byte");
563 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
564 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
565 return -E1000_ERR_PHY;
567 /* The programming interface is 16 bits wide
568 * so we need to read the whole word first
569 * then update appropriate byte lane and write
570 * the updated word back.
572 /* Set up Op-code, EEPROM Address,in the I2CCMD
573 * register. The MAC will take care of interfacing
574 * with an EEPROM to write the data given.
576 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
577 E1000_I2CCMD_OPCODE_READ);
578 /* Set a command to read single word */
579 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
580 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
582 /* Poll the ready bit to see if lastly
583 * launched I2C operation completed
585 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
586 if (i2ccmd & E1000_I2CCMD_READY) {
587 /* Check if this is READ or WRITE phase */
588 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
589 E1000_I2CCMD_OPCODE_READ) {
590 /* Write the selected byte
591 * lane and update whole word
593 data_local = i2ccmd & 0xFF00;
596 E1000_I2CCMD_REG_ADDR_SHIFT) |
597 E1000_I2CCMD_OPCODE_WRITE | data_local);
598 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
604 if (!(i2ccmd & E1000_I2CCMD_READY)) {
605 DEBUGOUT("I2CCMD Write did not complete\n");
606 return -E1000_ERR_PHY;
608 if (i2ccmd & E1000_I2CCMD_ERROR) {
609 DEBUGOUT("I2CCMD Error bit set\n");
610 return -E1000_ERR_PHY;
612 return E1000_SUCCESS;
616 * e1000_read_phy_reg_m88 - Read m88 PHY register
617 * @hw: pointer to the HW structure
618 * @offset: register offset to be read
619 * @data: pointer to the read data
621 * Acquires semaphore, if necessary, then reads the PHY register at offset
622 * and storing the retrieved information in data. Release any acquired
623 * semaphores before exiting.
625 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
629 DEBUGFUNC("e1000_read_phy_reg_m88");
631 if (!hw->phy.ops.acquire)
632 return E1000_SUCCESS;
634 ret_val = hw->phy.ops.acquire(hw);
638 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
641 hw->phy.ops.release(hw);
647 * e1000_write_phy_reg_m88 - Write m88 PHY register
648 * @hw: pointer to the HW structure
649 * @offset: register offset to write to
650 * @data: data to write at register offset
652 * Acquires semaphore, if necessary, then writes the data to PHY register
653 * at the offset. Release any acquired semaphores before exiting.
655 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
659 DEBUGFUNC("e1000_write_phy_reg_m88");
661 if (!hw->phy.ops.acquire)
662 return E1000_SUCCESS;
664 ret_val = hw->phy.ops.acquire(hw);
668 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
671 hw->phy.ops.release(hw);
677 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
678 * @hw: pointer to the HW structure
679 * @page: page to set (shifted left when necessary)
681 * Sets PHY page required for PHY register access. Assumes semaphore is
682 * already acquired. Note, this function sets phy.addr to 1 so the caller
683 * must set it appropriately (if necessary) after this function returns.
685 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
687 DEBUGFUNC("e1000_set_page_igp");
689 DEBUGOUT1("Setting page 0x%x\n", page);
693 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
697 * __e1000_read_phy_reg_igp - Read igp PHY register
698 * @hw: pointer to the HW structure
699 * @offset: register offset to be read
700 * @data: pointer to the read data
701 * @locked: semaphore has already been acquired or not
703 * Acquires semaphore, if necessary, then reads the PHY register at offset
704 * and stores the retrieved information in data. Release any acquired
705 * semaphores before exiting.
707 STATIC s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
710 s32 ret_val = E1000_SUCCESS;
712 DEBUGFUNC("__e1000_read_phy_reg_igp");
715 if (!hw->phy.ops.acquire)
716 return E1000_SUCCESS;
718 ret_val = hw->phy.ops.acquire(hw);
723 if (offset > MAX_PHY_MULTI_PAGE_REG)
724 ret_val = e1000_write_phy_reg_mdic(hw,
725 IGP01E1000_PHY_PAGE_SELECT,
728 ret_val = e1000_read_phy_reg_mdic(hw,
729 MAX_PHY_REG_ADDRESS & offset,
732 hw->phy.ops.release(hw);
738 * e1000_read_phy_reg_igp - Read igp PHY register
739 * @hw: pointer to the HW structure
740 * @offset: register offset to be read
741 * @data: pointer to the read data
743 * Acquires semaphore then reads the PHY register at offset and stores the
744 * retrieved information in data.
745 * Release the acquired semaphore before exiting.
747 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
749 return __e1000_read_phy_reg_igp(hw, offset, data, false);
753 * e1000_read_phy_reg_igp_locked - Read igp PHY register
754 * @hw: pointer to the HW structure
755 * @offset: register offset to be read
756 * @data: pointer to the read data
758 * Reads the PHY register at offset and stores the retrieved information
759 * in data. Assumes semaphore already acquired.
761 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
763 return __e1000_read_phy_reg_igp(hw, offset, data, true);
767 * e1000_write_phy_reg_igp - Write igp PHY register
768 * @hw: pointer to the HW structure
769 * @offset: register offset to write to
770 * @data: data to write at register offset
771 * @locked: semaphore has already been acquired or not
773 * Acquires semaphore, if necessary, then writes the data to PHY register
774 * at the offset. Release any acquired semaphores before exiting.
776 STATIC s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
779 s32 ret_val = E1000_SUCCESS;
781 DEBUGFUNC("e1000_write_phy_reg_igp");
784 if (!hw->phy.ops.acquire)
785 return E1000_SUCCESS;
787 ret_val = hw->phy.ops.acquire(hw);
792 if (offset > MAX_PHY_MULTI_PAGE_REG)
793 ret_val = e1000_write_phy_reg_mdic(hw,
794 IGP01E1000_PHY_PAGE_SELECT,
797 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
801 hw->phy.ops.release(hw);
807 * e1000_write_phy_reg_igp - Write igp PHY register
808 * @hw: pointer to the HW structure
809 * @offset: register offset to write to
810 * @data: data to write at register offset
812 * Acquires semaphore then writes the data to PHY register
813 * at the offset. Release any acquired semaphores before exiting.
815 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
817 return __e1000_write_phy_reg_igp(hw, offset, data, false);
821 * e1000_write_phy_reg_igp_locked - Write igp PHY register
822 * @hw: pointer to the HW structure
823 * @offset: register offset to write to
824 * @data: data to write at register offset
826 * Writes the data to PHY register at the offset.
827 * Assumes semaphore already acquired.
829 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
831 return __e1000_write_phy_reg_igp(hw, offset, data, true);
835 * __e1000_read_kmrn_reg - Read kumeran register
836 * @hw: pointer to the HW structure
837 * @offset: register offset to be read
838 * @data: pointer to the read data
839 * @locked: semaphore has already been acquired or not
841 * Acquires semaphore, if necessary. Then reads the PHY register at offset
842 * using the kumeran interface. The information retrieved is stored in data.
843 * Release any acquired semaphores before exiting.
845 STATIC s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
850 DEBUGFUNC("__e1000_read_kmrn_reg");
853 s32 ret_val = E1000_SUCCESS;
855 if (!hw->phy.ops.acquire)
856 return E1000_SUCCESS;
858 ret_val = hw->phy.ops.acquire(hw);
863 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
864 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
865 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
866 E1000_WRITE_FLUSH(hw);
870 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
871 *data = (u16)kmrnctrlsta;
874 hw->phy.ops.release(hw);
876 return E1000_SUCCESS;
880 * e1000_read_kmrn_reg_generic - Read kumeran register
881 * @hw: pointer to the HW structure
882 * @offset: register offset to be read
883 * @data: pointer to the read data
885 * Acquires semaphore then reads the PHY register at offset using the
886 * kumeran interface. The information retrieved is stored in data.
887 * Release the acquired semaphore before exiting.
889 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
891 return __e1000_read_kmrn_reg(hw, offset, data, false);
895 * e1000_read_kmrn_reg_locked - Read kumeran register
896 * @hw: pointer to the HW structure
897 * @offset: register offset to be read
898 * @data: pointer to the read data
900 * Reads the PHY register at offset using the kumeran interface. The
901 * information retrieved is stored in data.
902 * Assumes semaphore already acquired.
904 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
906 return __e1000_read_kmrn_reg(hw, offset, data, true);
910 * __e1000_write_kmrn_reg - Write kumeran register
911 * @hw: pointer to the HW structure
912 * @offset: register offset to write to
913 * @data: data to write at register offset
914 * @locked: semaphore has already been acquired or not
916 * Acquires semaphore, if necessary. Then write the data to PHY register
917 * at the offset using the kumeran interface. Release any acquired semaphores
920 STATIC s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
925 DEBUGFUNC("e1000_write_kmrn_reg_generic");
928 s32 ret_val = E1000_SUCCESS;
930 if (!hw->phy.ops.acquire)
931 return E1000_SUCCESS;
933 ret_val = hw->phy.ops.acquire(hw);
938 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
939 E1000_KMRNCTRLSTA_OFFSET) | data;
940 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
941 E1000_WRITE_FLUSH(hw);
946 hw->phy.ops.release(hw);
948 return E1000_SUCCESS;
952 * e1000_write_kmrn_reg_generic - Write kumeran register
953 * @hw: pointer to the HW structure
954 * @offset: register offset to write to
955 * @data: data to write at register offset
957 * Acquires semaphore then writes the data to the PHY register at the offset
958 * using the kumeran interface. Release the acquired semaphore before exiting.
960 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
962 return __e1000_write_kmrn_reg(hw, offset, data, false);
966 * e1000_write_kmrn_reg_locked - Write kumeran register
967 * @hw: pointer to the HW structure
968 * @offset: register offset to write to
969 * @data: data to write at register offset
971 * Write the data to PHY register at the offset using the kumeran interface.
972 * Assumes semaphore already acquired.
974 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
976 return __e1000_write_kmrn_reg(hw, offset, data, true);
980 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
981 * @hw: pointer to the HW structure
983 * Sets up Master/slave mode
985 STATIC s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
990 /* Resolve Master/Slave mode */
991 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
995 /* load defaults for future use */
996 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
997 ((phy_data & CR_1000T_MS_VALUE) ?
998 e1000_ms_force_master :
999 e1000_ms_force_slave) : e1000_ms_auto;
1001 switch (hw->phy.ms_type) {
1002 case e1000_ms_force_master:
1003 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1005 case e1000_ms_force_slave:
1006 phy_data |= CR_1000T_MS_ENABLE;
1007 phy_data &= ~(CR_1000T_MS_VALUE);
1010 phy_data &= ~CR_1000T_MS_ENABLE;
1016 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1020 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1021 * @hw: pointer to the HW structure
1023 * Sets up Carrier-sense on Transmit and downshift values.
1025 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1030 DEBUGFUNC("e1000_copper_link_setup_82577");
1032 if (hw->phy.type == e1000_phy_82580) {
1033 ret_val = hw->phy.ops.reset(hw);
1035 DEBUGOUT("Error resetting the PHY.\n");
1040 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1041 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1045 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1047 /* Enable downshift */
1048 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1050 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1054 /* Set MDI/MDIX mode */
1055 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1058 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1060 * 0 - Auto (default)
1064 switch (hw->phy.mdix) {
1068 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1072 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1075 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1079 return e1000_set_master_slave_mode(hw);
1083 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1084 * @hw: pointer to the HW structure
1086 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1087 * and downshift values are set also.
1089 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1091 struct e1000_phy_info *phy = &hw->phy;
1095 DEBUGFUNC("e1000_copper_link_setup_m88");
1098 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1099 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1103 /* For BM PHY this bit is downshift enable */
1104 if (phy->type != e1000_phy_bm)
1105 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1108 * MDI/MDI-X = 0 (default)
1109 * 0 - Auto for all speeds
1112 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1114 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1116 switch (phy->mdix) {
1118 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1121 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1124 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1128 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1133 * disable_polarity_correction = 0 (default)
1134 * Automatic Correction for Reversed Cable Polarity
1138 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1139 if (phy->disable_polarity_correction)
1140 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1142 /* Enable downshift on BM (disabled by default) */
1143 if (phy->type == e1000_phy_bm) {
1144 /* For 82574/82583, first disable then enable downshift */
1145 if (phy->id == BME1000_E_PHY_ID_R2) {
1146 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1147 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1151 /* Commit the changes. */
1152 ret_val = phy->ops.commit(hw);
1154 DEBUGOUT("Error committing the PHY changes\n");
1159 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1162 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1166 if ((phy->type == e1000_phy_m88) &&
1167 (phy->revision < E1000_REVISION_4) &&
1168 (phy->id != BME1000_E_PHY_ID_R2)) {
1169 /* Force TX_CLK in the Extended PHY Specific Control Register
1172 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1177 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1179 if ((phy->revision == E1000_REVISION_2) &&
1180 (phy->id == M88E1111_I_PHY_ID)) {
1181 /* 82573L PHY - set the downshift counter to 5x. */
1182 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1183 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1185 /* Configure Master and Slave downshift values */
1186 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1187 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1188 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1189 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1191 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1197 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1198 /* Set PHY page 0, register 29 to 0x0003 */
1199 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1203 /* Set PHY page 0, register 30 to 0x0000 */
1204 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1209 /* Commit the changes. */
1210 ret_val = phy->ops.commit(hw);
1212 DEBUGOUT("Error committing the PHY changes\n");
1216 if (phy->type == e1000_phy_82578) {
1217 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1222 /* 82578 PHY - set the downshift count to 1x. */
1223 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1224 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1225 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1231 return E1000_SUCCESS;
1235 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1236 * @hw: pointer to the HW structure
1238 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1239 * Also enables and sets the downshift parameters.
1241 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1243 struct e1000_phy_info *phy = &hw->phy;
1247 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1250 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1251 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1256 * MDI/MDI-X = 0 (default)
1257 * 0 - Auto for all speeds
1260 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1262 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1264 switch (phy->mdix) {
1266 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1269 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1272 /* M88E1112 does not support this mode) */
1273 if (phy->id != M88E1112_E_PHY_ID) {
1274 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1279 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1284 * disable_polarity_correction = 0 (default)
1285 * Automatic Correction for Reversed Cable Polarity
1289 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1290 if (phy->disable_polarity_correction)
1291 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1293 /* Enable downshift and setting it to X6 */
1294 if (phy->id == M88E1543_E_PHY_ID) {
1295 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1297 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1301 ret_val = phy->ops.commit(hw);
1303 DEBUGOUT("Error committing the PHY changes\n");
1308 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1309 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1310 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1312 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1316 /* Commit the changes. */
1317 ret_val = phy->ops.commit(hw);
1319 DEBUGOUT("Error committing the PHY changes\n");
1323 ret_val = e1000_set_master_slave_mode(hw);
1327 return E1000_SUCCESS;
1331 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1332 * @hw: pointer to the HW structure
1334 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1337 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1339 struct e1000_phy_info *phy = &hw->phy;
1343 DEBUGFUNC("e1000_copper_link_setup_igp");
1346 ret_val = hw->phy.ops.reset(hw);
1348 DEBUGOUT("Error resetting the PHY.\n");
1352 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1353 * timeout issues when LFS is enabled.
1357 /* The NVM settings will configure LPLU in D3 for
1360 if (phy->type == e1000_phy_igp) {
1361 /* disable lplu d3 during driver init */
1362 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1364 DEBUGOUT("Error Disabling LPLU D3\n");
1369 /* disable lplu d0 during driver init */
1370 if (hw->phy.ops.set_d0_lplu_state) {
1371 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1373 DEBUGOUT("Error Disabling LPLU D0\n");
1377 /* Configure mdi-mdix settings */
1378 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1382 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1384 switch (phy->mdix) {
1386 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1389 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1393 data |= IGP01E1000_PSCR_AUTO_MDIX;
1396 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1400 /* set auto-master slave resolution settings */
1401 if (hw->mac.autoneg) {
1402 /* when autonegotiation advertisement is only 1000Mbps then we
1403 * should disable SmartSpeed and enable Auto MasterSlave
1404 * resolution as hardware default.
1406 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1407 /* Disable SmartSpeed */
1408 ret_val = phy->ops.read_reg(hw,
1409 IGP01E1000_PHY_PORT_CONFIG,
1414 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1415 ret_val = phy->ops.write_reg(hw,
1416 IGP01E1000_PHY_PORT_CONFIG,
1421 /* Set auto Master/Slave resolution process */
1422 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1426 data &= ~CR_1000T_MS_ENABLE;
1427 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1432 ret_val = e1000_set_master_slave_mode(hw);
1439 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1440 * @hw: pointer to the HW structure
1442 * Reads the MII auto-neg advertisement register and/or the 1000T control
1443 * register and if the PHY is already setup for auto-negotiation, then
1444 * return successful. Otherwise, setup advertisement and flow control to
1445 * the appropriate values for the wanted auto-negotiation.
1447 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1449 struct e1000_phy_info *phy = &hw->phy;
1451 u16 mii_autoneg_adv_reg;
1452 u16 mii_1000t_ctrl_reg = 0;
1454 DEBUGFUNC("e1000_phy_setup_autoneg");
1456 phy->autoneg_advertised &= phy->autoneg_mask;
1458 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1459 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1463 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1464 /* Read the MII 1000Base-T Control Register (Address 9). */
1465 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1466 &mii_1000t_ctrl_reg);
1471 /* Need to parse both autoneg_advertised and fc and set up
1472 * the appropriate PHY registers. First we will parse for
1473 * autoneg_advertised software override. Since we can advertise
1474 * a plethora of combinations, we need to check each bit
1478 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1479 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1480 * the 1000Base-T Control Register (Address 9).
1482 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1483 NWAY_AR_100TX_HD_CAPS |
1484 NWAY_AR_10T_FD_CAPS |
1485 NWAY_AR_10T_HD_CAPS);
1486 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1488 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1490 /* Do we want to advertise 10 Mb Half Duplex? */
1491 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1492 DEBUGOUT("Advertise 10mb Half duplex\n");
1493 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1496 /* Do we want to advertise 10 Mb Full Duplex? */
1497 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1498 DEBUGOUT("Advertise 10mb Full duplex\n");
1499 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1502 /* Do we want to advertise 100 Mb Half Duplex? */
1503 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1504 DEBUGOUT("Advertise 100mb Half duplex\n");
1505 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1508 /* Do we want to advertise 100 Mb Full Duplex? */
1509 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1510 DEBUGOUT("Advertise 100mb Full duplex\n");
1511 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1514 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1515 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1516 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1518 /* Do we want to advertise 1000 Mb Full Duplex? */
1519 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1520 DEBUGOUT("Advertise 1000mb Full duplex\n");
1521 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1524 /* Check for a software override of the flow control settings, and
1525 * setup the PHY advertisement registers accordingly. If
1526 * auto-negotiation is enabled, then software will have to set the
1527 * "PAUSE" bits to the correct value in the Auto-Negotiation
1528 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1531 * The possible values of the "fc" parameter are:
1532 * 0: Flow control is completely disabled
1533 * 1: Rx flow control is enabled (we can receive pause frames
1534 * but not send pause frames).
1535 * 2: Tx flow control is enabled (we can send pause frames
1536 * but we do not support receiving pause frames).
1537 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1538 * other: No software override. The flow control configuration
1539 * in the EEPROM is used.
1541 switch (hw->fc.current_mode) {
1543 /* Flow control (Rx & Tx) is completely disabled by a
1544 * software over-ride.
1546 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1548 case e1000_fc_rx_pause:
1549 /* Rx Flow control is enabled, and Tx Flow control is
1550 * disabled, by a software over-ride.
1552 * Since there really isn't a way to advertise that we are
1553 * capable of Rx Pause ONLY, we will advertise that we
1554 * support both symmetric and asymmetric Rx PAUSE. Later
1555 * (in e1000_config_fc_after_link_up) we will disable the
1556 * hw's ability to send PAUSE frames.
1558 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1560 case e1000_fc_tx_pause:
1561 /* Tx Flow control is enabled, and Rx Flow control is
1562 * disabled, by a software over-ride.
1564 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1565 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1568 /* Flow control (both Rx and Tx) is enabled by a software
1571 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1574 DEBUGOUT("Flow control param set incorrectly\n");
1575 return -E1000_ERR_CONFIG;
1578 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1582 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1584 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1585 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1586 mii_1000t_ctrl_reg);
1592 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1593 * @hw: pointer to the HW structure
1595 * Performs initial bounds checking on autoneg advertisement parameter, then
1596 * configure to advertise the full capability. Setup the PHY to autoneg
1597 * and restart the negotiation process between the link partner. If
1598 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1600 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1602 struct e1000_phy_info *phy = &hw->phy;
1606 DEBUGFUNC("e1000_copper_link_autoneg");
1608 /* Perform some bounds checking on the autoneg advertisement
1611 phy->autoneg_advertised &= phy->autoneg_mask;
1613 /* If autoneg_advertised is zero, we assume it was not defaulted
1614 * by the calling code so we set to advertise full capability.
1616 if (!phy->autoneg_advertised)
1617 phy->autoneg_advertised = phy->autoneg_mask;
1619 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1620 ret_val = e1000_phy_setup_autoneg(hw);
1622 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1625 DEBUGOUT("Restarting Auto-Neg\n");
1627 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1628 * the Auto Neg Restart bit in the PHY control register.
1630 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1634 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1635 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1639 /* Does the user want to wait for Auto-Neg to complete here, or
1640 * check at a later time (for example, callback routine).
1642 if (phy->autoneg_wait_to_complete) {
1643 ret_val = e1000_wait_autoneg(hw);
1645 DEBUGOUT("Error while waiting for autoneg to complete\n");
1650 hw->mac.get_link_status = true;
1656 * e1000_setup_copper_link_generic - Configure copper link settings
1657 * @hw: pointer to the HW structure
1659 * Calls the appropriate function to configure the link for auto-neg or forced
1660 * speed and duplex. Then we check for link, once link is established calls
1661 * to configure collision distance and flow control are called. If link is
1662 * not established, we return -E1000_ERR_PHY (-2).
1664 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1669 DEBUGFUNC("e1000_setup_copper_link_generic");
1671 if (hw->mac.autoneg) {
1672 /* Setup autoneg and flow control advertisement and perform
1675 ret_val = e1000_copper_link_autoneg(hw);
1679 /* PHY will be set to 10H, 10F, 100H or 100F
1680 * depending on user settings.
1682 DEBUGOUT("Forcing Speed and Duplex\n");
1683 ret_val = hw->phy.ops.force_speed_duplex(hw);
1685 DEBUGOUT("Error Forcing Speed and Duplex\n");
1690 /* Check link status. Wait up to 100 microseconds for link to become
1693 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1699 DEBUGOUT("Valid link established!!!\n");
1700 hw->mac.ops.config_collision_dist(hw);
1701 ret_val = e1000_config_fc_after_link_up_generic(hw);
1703 DEBUGOUT("Unable to establish link!!!\n");
1710 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1711 * @hw: pointer to the HW structure
1713 * Calls the PHY setup function to force speed and duplex. Clears the
1714 * auto-crossover to force MDI manually. Waits for link and returns
1715 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1717 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1719 struct e1000_phy_info *phy = &hw->phy;
1724 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1726 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1730 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1732 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1736 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1737 * forced whenever speed and duplex are forced.
1739 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1743 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1744 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1746 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1750 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1754 if (phy->autoneg_wait_to_complete) {
1755 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1757 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1763 DEBUGOUT("Link taking longer than expected.\n");
1766 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1774 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1775 * @hw: pointer to the HW structure
1777 * Calls the PHY setup function to force speed and duplex. Clears the
1778 * auto-crossover to force MDI manually. Resets the PHY to commit the
1779 * changes. If time expires while waiting for link up, we reset the DSP.
1780 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1781 * successful completion, else return corresponding error code.
1783 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1785 struct e1000_phy_info *phy = &hw->phy;
1790 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1792 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1793 if (phy->type != e1000_phy_i210) {
1794 /* Clear Auto-Crossover to force MDI manually. M88E1000
1795 * requires MDI forced whenever speed and duplex are forced.
1797 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1802 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1803 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1808 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1811 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1815 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1817 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1821 /* Reset the phy to commit changes. */
1822 ret_val = hw->phy.ops.commit(hw);
1826 if (phy->autoneg_wait_to_complete) {
1827 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1829 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1835 bool reset_dsp = true;
1837 switch (hw->phy.id) {
1838 case I347AT4_E_PHY_ID:
1839 case M88E1340M_E_PHY_ID:
1840 case M88E1112_E_PHY_ID:
1841 case M88E1543_E_PHY_ID:
1842 case M88E1512_E_PHY_ID:
1847 if (hw->phy.type != e1000_phy_m88)
1853 DEBUGOUT("Link taking longer than expected.\n");
1855 /* We didn't get link.
1856 * Reset the DSP and cross our fingers.
1858 ret_val = phy->ops.write_reg(hw,
1859 M88E1000_PHY_PAGE_SELECT,
1863 ret_val = e1000_phy_reset_dsp_generic(hw);
1870 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1876 if (hw->phy.type != e1000_phy_m88)
1877 return E1000_SUCCESS;
1879 if (hw->phy.id == I347AT4_E_PHY_ID ||
1880 hw->phy.id == M88E1340M_E_PHY_ID ||
1881 hw->phy.id == M88E1112_E_PHY_ID)
1882 return E1000_SUCCESS;
1883 if (hw->phy.id == I210_I_PHY_ID)
1884 return E1000_SUCCESS;
1885 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1886 (hw->phy.id == M88E1512_E_PHY_ID))
1887 return E1000_SUCCESS;
1888 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1892 /* Resetting the phy means we need to re-force TX_CLK in the
1893 * Extended PHY Specific Control Register to 25MHz clock from
1894 * the reset value of 2.5MHz.
1896 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1897 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1901 /* In addition, we must re-enable CRS on Tx for both half and full
1904 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1908 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1909 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1915 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1916 * @hw: pointer to the HW structure
1918 * Forces the speed and duplex settings of the PHY.
1919 * This is a function pointer entry point only called by
1920 * PHY setup routines.
1922 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1924 struct e1000_phy_info *phy = &hw->phy;
1929 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1931 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1935 e1000_phy_force_speed_duplex_setup(hw, &data);
1937 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1941 /* Disable MDI-X support for 10/100 */
1942 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1946 data &= ~IFE_PMC_AUTO_MDIX;
1947 data &= ~IFE_PMC_FORCE_MDIX;
1949 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1953 DEBUGOUT1("IFE PMC: %X\n", data);
1957 if (phy->autoneg_wait_to_complete) {
1958 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1960 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1966 DEBUGOUT("Link taking longer than expected.\n");
1969 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1975 return E1000_SUCCESS;
1979 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1980 * @hw: pointer to the HW structure
1981 * @phy_ctrl: pointer to current value of PHY_CONTROL
1983 * Forces speed and duplex on the PHY by doing the following: disable flow
1984 * control, force speed/duplex on the MAC, disable auto speed detection,
1985 * disable auto-negotiation, configure duplex, configure speed, configure
1986 * the collision distance, write configuration to CTRL register. The
1987 * caller must write to the PHY_CONTROL register for these settings to
1990 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1992 struct e1000_mac_info *mac = &hw->mac;
1995 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1997 /* Turn off flow control when forcing speed/duplex */
1998 hw->fc.current_mode = e1000_fc_none;
2000 /* Force speed/duplex on the mac */
2001 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2002 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2003 ctrl &= ~E1000_CTRL_SPD_SEL;
2005 /* Disable Auto Speed Detection */
2006 ctrl &= ~E1000_CTRL_ASDE;
2008 /* Disable autoneg on the phy */
2009 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2011 /* Forcing Full or Half Duplex? */
2012 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2013 ctrl &= ~E1000_CTRL_FD;
2014 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2015 DEBUGOUT("Half Duplex\n");
2017 ctrl |= E1000_CTRL_FD;
2018 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2019 DEBUGOUT("Full Duplex\n");
2022 /* Forcing 10mb or 100mb? */
2023 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2024 ctrl |= E1000_CTRL_SPD_100;
2025 *phy_ctrl |= MII_CR_SPEED_100;
2026 *phy_ctrl &= ~MII_CR_SPEED_1000;
2027 DEBUGOUT("Forcing 100mb\n");
2029 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2030 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2031 DEBUGOUT("Forcing 10mb\n");
2034 hw->mac.ops.config_collision_dist(hw);
2036 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2040 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2041 * @hw: pointer to the HW structure
2042 * @active: boolean used to enable/disable lplu
2044 * Success returns 0, Failure returns 1
2046 * The low power link up (lplu) state is set to the power management level D3
2047 * and SmartSpeed is disabled when active is true, else clear lplu for D3
2048 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2049 * is used during Dx states where the power conservation is most important.
2050 * During driver activity, SmartSpeed should be enabled so performance is
2053 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2055 struct e1000_phy_info *phy = &hw->phy;
2059 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2061 if (!hw->phy.ops.read_reg)
2062 return E1000_SUCCESS;
2064 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2069 data &= ~IGP02E1000_PM_D3_LPLU;
2070 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2074 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2075 * during Dx states where the power conservation is most
2076 * important. During driver activity we should enable
2077 * SmartSpeed, so performance is maintained.
2079 if (phy->smart_speed == e1000_smart_speed_on) {
2080 ret_val = phy->ops.read_reg(hw,
2081 IGP01E1000_PHY_PORT_CONFIG,
2086 data |= IGP01E1000_PSCFR_SMART_SPEED;
2087 ret_val = phy->ops.write_reg(hw,
2088 IGP01E1000_PHY_PORT_CONFIG,
2092 } else if (phy->smart_speed == e1000_smart_speed_off) {
2093 ret_val = phy->ops.read_reg(hw,
2094 IGP01E1000_PHY_PORT_CONFIG,
2099 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2100 ret_val = phy->ops.write_reg(hw,
2101 IGP01E1000_PHY_PORT_CONFIG,
2106 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2107 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2108 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2109 data |= IGP02E1000_PM_D3_LPLU;
2110 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2115 /* When LPLU is enabled, we should disable SmartSpeed */
2116 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2121 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2122 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2130 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2131 * @hw: pointer to the HW structure
2133 * Success returns 0, Failure returns 1
2135 * A downshift is detected by querying the PHY link health.
2137 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2139 struct e1000_phy_info *phy = &hw->phy;
2141 u16 phy_data, offset, mask;
2143 DEBUGFUNC("e1000_check_downshift_generic");
2145 switch (phy->type) {
2146 case e1000_phy_i210:
2148 case e1000_phy_gg82563:
2150 case e1000_phy_82578:
2151 offset = M88E1000_PHY_SPEC_STATUS;
2152 mask = M88E1000_PSSR_DOWNSHIFT;
2155 case e1000_phy_igp_2:
2156 case e1000_phy_igp_3:
2157 offset = IGP01E1000_PHY_LINK_HEALTH;
2158 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2161 /* speed downshift not supported */
2162 phy->speed_downgraded = false;
2163 return E1000_SUCCESS;
2166 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2169 phy->speed_downgraded = !!(phy_data & mask);
2175 * e1000_check_polarity_m88 - Checks the polarity.
2176 * @hw: pointer to the HW structure
2178 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2180 * Polarity is determined based on the PHY specific status register.
2182 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2184 struct e1000_phy_info *phy = &hw->phy;
2188 DEBUGFUNC("e1000_check_polarity_m88");
2190 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2193 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2194 ? e1000_rev_polarity_reversed
2195 : e1000_rev_polarity_normal);
2201 * e1000_check_polarity_igp - Checks the polarity.
2202 * @hw: pointer to the HW structure
2204 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2206 * Polarity is determined based on the PHY port status register, and the
2207 * current speed (since there is no polarity at 100Mbps).
2209 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2211 struct e1000_phy_info *phy = &hw->phy;
2213 u16 data, offset, mask;
2215 DEBUGFUNC("e1000_check_polarity_igp");
2217 /* Polarity is determined based on the speed of
2220 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2224 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2225 IGP01E1000_PSSR_SPEED_1000MBPS) {
2226 offset = IGP01E1000_PHY_PCS_INIT_REG;
2227 mask = IGP01E1000_PHY_POLARITY_MASK;
2229 /* This really only applies to 10Mbps since
2230 * there is no polarity for 100Mbps (always 0).
2232 offset = IGP01E1000_PHY_PORT_STATUS;
2233 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2236 ret_val = phy->ops.read_reg(hw, offset, &data);
2239 phy->cable_polarity = ((data & mask)
2240 ? e1000_rev_polarity_reversed
2241 : e1000_rev_polarity_normal);
2247 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2248 * @hw: pointer to the HW structure
2250 * Polarity is determined on the polarity reversal feature being enabled.
2252 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2254 struct e1000_phy_info *phy = &hw->phy;
2256 u16 phy_data, offset, mask;
2258 DEBUGFUNC("e1000_check_polarity_ife");
2260 /* Polarity is determined based on the reversal feature being enabled.
2262 if (phy->polarity_correction) {
2263 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2264 mask = IFE_PESC_POLARITY_REVERSED;
2266 offset = IFE_PHY_SPECIAL_CONTROL;
2267 mask = IFE_PSC_FORCE_POLARITY;
2270 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2273 phy->cable_polarity = ((phy_data & mask)
2274 ? e1000_rev_polarity_reversed
2275 : e1000_rev_polarity_normal);
2281 * e1000_wait_autoneg - Wait for auto-neg completion
2282 * @hw: pointer to the HW structure
2284 * Waits for auto-negotiation to complete or for the auto-negotiation time
2285 * limit to expire, which ever happens first.
2287 STATIC s32 e1000_wait_autoneg(struct e1000_hw *hw)
2289 s32 ret_val = E1000_SUCCESS;
2292 DEBUGFUNC("e1000_wait_autoneg");
2294 if (!hw->phy.ops.read_reg)
2295 return E1000_SUCCESS;
2297 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2298 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2299 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2302 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2305 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2310 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2317 * e1000_phy_has_link_generic - Polls PHY for link
2318 * @hw: pointer to the HW structure
2319 * @iterations: number of times to poll for link
2320 * @usec_interval: delay between polling attempts
2321 * @success: pointer to whether polling was successful or not
2323 * Polls the PHY status register for link, 'iterations' number of times.
2325 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2326 u32 usec_interval, bool *success)
2328 s32 ret_val = E1000_SUCCESS;
2331 DEBUGFUNC("e1000_phy_has_link_generic");
2333 if (!hw->phy.ops.read_reg)
2334 return E1000_SUCCESS;
2336 for (i = 0; i < iterations; i++) {
2337 /* Some PHYs require the PHY_STATUS register to be read
2338 * twice due to the link bit being sticky. No harm doing
2339 * it across the board.
2341 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2343 /* If the first read fails, another entity may have
2344 * ownership of the resources, wait and try again to
2345 * see if they have relinquished the resources yet.
2347 if (usec_interval >= 1000)
2348 msec_delay(usec_interval/1000);
2350 usec_delay(usec_interval);
2352 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2355 if (phy_status & MII_SR_LINK_STATUS)
2357 if (usec_interval >= 1000)
2358 msec_delay(usec_interval/1000);
2360 usec_delay(usec_interval);
2363 *success = (i < iterations);
2369 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2370 * @hw: pointer to the HW structure
2372 * Reads the PHY specific status register to retrieve the cable length
2373 * information. The cable length is determined by averaging the minimum and
2374 * maximum values to get the "average" cable length. The m88 PHY has four
2375 * possible cable length values, which are:
2376 * Register Value Cable Length
2380 * 3 110 - 140 meters
2383 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2385 struct e1000_phy_info *phy = &hw->phy;
2387 u16 phy_data, index;
2389 DEBUGFUNC("e1000_get_cable_length_m88");
2391 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2395 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2396 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2398 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2399 return -E1000_ERR_PHY;
2401 phy->min_cable_length = e1000_m88_cable_length_table[index];
2402 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2404 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2406 return E1000_SUCCESS;
2409 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2411 struct e1000_phy_info *phy = &hw->phy;
2413 u16 phy_data, phy_data2, is_cm;
2414 u16 index, default_page;
2416 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2418 switch (hw->phy.id) {
2420 /* Get cable length from PHY Cable Diagnostics Control Reg */
2421 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2422 (I347AT4_PCDL + phy->addr),
2427 /* Check if the unit of cable length is meters or cm */
2428 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2429 I347AT4_PCDC, &phy_data2);
2433 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2435 /* Populate the phy structure with cable length in meters */
2436 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2437 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2438 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2440 case M88E1543_E_PHY_ID:
2441 case M88E1512_E_PHY_ID:
2442 case M88E1340M_E_PHY_ID:
2443 case I347AT4_E_PHY_ID:
2444 /* Remember the original page select and set it to 7 */
2445 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2450 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2454 /* Get cable length from PHY Cable Diagnostics Control Reg */
2455 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2460 /* Check if the unit of cable length is meters or cm */
2461 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2465 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2467 /* Populate the phy structure with cable length in meters */
2468 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2469 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2470 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2472 /* Reset the page select to its original value */
2473 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2479 case M88E1112_E_PHY_ID:
2480 /* Remember the original page select and set it to 5 */
2481 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2486 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2490 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2495 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2496 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2498 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2499 return -E1000_ERR_PHY;
2501 phy->min_cable_length = e1000_m88_cable_length_table[index];
2502 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2504 phy->cable_length = (phy->min_cable_length +
2505 phy->max_cable_length) / 2;
2507 /* Reset the page select to its original value */
2508 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2515 return -E1000_ERR_PHY;
2522 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2523 * @hw: pointer to the HW structure
2525 * The automatic gain control (agc) normalizes the amplitude of the
2526 * received signal, adjusting for the attenuation produced by the
2527 * cable. By reading the AGC registers, which represent the
2528 * combination of coarse and fine gain value, the value can be put
2529 * into a lookup table to obtain the approximate cable length
2532 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2534 struct e1000_phy_info *phy = &hw->phy;
2536 u16 phy_data, i, agc_value = 0;
2537 u16 cur_agc_index, max_agc_index = 0;
2538 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2539 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2540 IGP02E1000_PHY_AGC_A,
2541 IGP02E1000_PHY_AGC_B,
2542 IGP02E1000_PHY_AGC_C,
2543 IGP02E1000_PHY_AGC_D
2546 DEBUGFUNC("e1000_get_cable_length_igp_2");
2548 /* Read the AGC registers for all channels */
2549 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2550 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2554 /* Getting bits 15:9, which represent the combination of
2555 * coarse and fine gain values. The result is a number
2556 * that can be put into the lookup table to obtain the
2557 * approximate cable length.
2559 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2560 IGP02E1000_AGC_LENGTH_MASK);
2562 /* Array index bound check. */
2563 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2564 (cur_agc_index == 0))
2565 return -E1000_ERR_PHY;
2567 /* Remove min & max AGC values from calculation. */
2568 if (e1000_igp_2_cable_length_table[min_agc_index] >
2569 e1000_igp_2_cable_length_table[cur_agc_index])
2570 min_agc_index = cur_agc_index;
2571 if (e1000_igp_2_cable_length_table[max_agc_index] <
2572 e1000_igp_2_cable_length_table[cur_agc_index])
2573 max_agc_index = cur_agc_index;
2575 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2578 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2579 e1000_igp_2_cable_length_table[max_agc_index]);
2580 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2582 /* Calculate cable length with the error range of +/- 10 meters. */
2583 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2584 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2585 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2587 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2589 return E1000_SUCCESS;
2593 * e1000_get_phy_info_m88 - Retrieve PHY information
2594 * @hw: pointer to the HW structure
2596 * Valid for only copper links. Read the PHY status register (sticky read)
2597 * to verify that link is up. Read the PHY special control register to
2598 * determine the polarity and 10base-T extended distance. Read the PHY
2599 * special status register to determine MDI/MDIx and current speed. If
2600 * speed is 1000, then determine cable length, local and remote receiver.
2602 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2604 struct e1000_phy_info *phy = &hw->phy;
2609 DEBUGFUNC("e1000_get_phy_info_m88");
2611 if (phy->media_type != e1000_media_type_copper) {
2612 DEBUGOUT("Phy info is only valid for copper media\n");
2613 return -E1000_ERR_CONFIG;
2616 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2621 DEBUGOUT("Phy info is only valid if link is up\n");
2622 return -E1000_ERR_CONFIG;
2625 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2629 phy->polarity_correction = !!(phy_data &
2630 M88E1000_PSCR_POLARITY_REVERSAL);
2632 ret_val = e1000_check_polarity_m88(hw);
2636 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2640 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2642 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2643 ret_val = hw->phy.ops.get_cable_length(hw);
2647 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2651 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2652 ? e1000_1000t_rx_status_ok
2653 : e1000_1000t_rx_status_not_ok;
2655 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2656 ? e1000_1000t_rx_status_ok
2657 : e1000_1000t_rx_status_not_ok;
2659 /* Set values to "undefined" */
2660 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2661 phy->local_rx = e1000_1000t_rx_status_undefined;
2662 phy->remote_rx = e1000_1000t_rx_status_undefined;
2669 * e1000_get_phy_info_igp - Retrieve igp PHY information
2670 * @hw: pointer to the HW structure
2672 * Read PHY status to determine if link is up. If link is up, then
2673 * set/determine 10base-T extended distance and polarity correction. Read
2674 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2675 * determine on the cable length, local and remote receiver.
2677 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2679 struct e1000_phy_info *phy = &hw->phy;
2684 DEBUGFUNC("e1000_get_phy_info_igp");
2686 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2691 DEBUGOUT("Phy info is only valid if link is up\n");
2692 return -E1000_ERR_CONFIG;
2695 phy->polarity_correction = true;
2697 ret_val = e1000_check_polarity_igp(hw);
2701 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2705 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2707 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2708 IGP01E1000_PSSR_SPEED_1000MBPS) {
2709 ret_val = phy->ops.get_cable_length(hw);
2713 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2717 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2718 ? e1000_1000t_rx_status_ok
2719 : e1000_1000t_rx_status_not_ok;
2721 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2722 ? e1000_1000t_rx_status_ok
2723 : e1000_1000t_rx_status_not_ok;
2725 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2726 phy->local_rx = e1000_1000t_rx_status_undefined;
2727 phy->remote_rx = e1000_1000t_rx_status_undefined;
2734 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2735 * @hw: pointer to the HW structure
2737 * Populates "phy" structure with various feature states.
2739 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2741 struct e1000_phy_info *phy = &hw->phy;
2746 DEBUGFUNC("e1000_get_phy_info_ife");
2748 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2753 DEBUGOUT("Phy info is only valid if link is up\n");
2754 return -E1000_ERR_CONFIG;
2757 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2760 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2762 if (phy->polarity_correction) {
2763 ret_val = e1000_check_polarity_ife(hw);
2767 /* Polarity is forced */
2768 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2769 ? e1000_rev_polarity_reversed
2770 : e1000_rev_polarity_normal);
2773 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2777 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2779 /* The following parameters are undefined for 10/100 operation. */
2780 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2781 phy->local_rx = e1000_1000t_rx_status_undefined;
2782 phy->remote_rx = e1000_1000t_rx_status_undefined;
2784 return E1000_SUCCESS;
2788 * e1000_phy_sw_reset_generic - PHY software reset
2789 * @hw: pointer to the HW structure
2791 * Does a software reset of the PHY by reading the PHY control register and
2792 * setting/write the control register reset bit to the PHY.
2794 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2799 DEBUGFUNC("e1000_phy_sw_reset_generic");
2801 if (!hw->phy.ops.read_reg)
2802 return E1000_SUCCESS;
2804 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2808 phy_ctrl |= MII_CR_RESET;
2809 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2819 * e1000_phy_hw_reset_generic - PHY hardware reset
2820 * @hw: pointer to the HW structure
2822 * Verify the reset block is not blocking us from resetting. Acquire
2823 * semaphore (if necessary) and read/set/write the device control reset
2824 * bit in the PHY. Wait the appropriate delay time for the device to
2825 * reset and release the semaphore (if necessary).
2827 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2829 struct e1000_phy_info *phy = &hw->phy;
2833 DEBUGFUNC("e1000_phy_hw_reset_generic");
2835 if (phy->ops.check_reset_block) {
2836 ret_val = phy->ops.check_reset_block(hw);
2838 return E1000_SUCCESS;
2841 ret_val = phy->ops.acquire(hw);
2845 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2846 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2847 E1000_WRITE_FLUSH(hw);
2849 usec_delay(phy->reset_delay_us);
2851 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2852 E1000_WRITE_FLUSH(hw);
2856 phy->ops.release(hw);
2858 return phy->ops.get_cfg_done(hw);
2862 * e1000_get_cfg_done_generic - Generic configuration done
2863 * @hw: pointer to the HW structure
2865 * Generic function to wait 10 milli-seconds for configuration to complete
2866 * and return success.
2868 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2870 DEBUGFUNC("e1000_get_cfg_done_generic");
2871 UNREFERENCED_1PARAMETER(hw);
2875 return E1000_SUCCESS;
2879 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2880 * @hw: pointer to the HW structure
2882 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2884 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2886 DEBUGOUT("Running IGP 3 PHY init script\n");
2888 /* PHY init IGP 3 */
2889 /* Enable rise/fall, 10-mode work in class-A */
2890 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2891 /* Remove all caps from Replica path filter */
2892 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2893 /* Bias trimming for ADC, AFE and Driver (Default) */
2894 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2895 /* Increase Hybrid poly bias */
2896 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2897 /* Add 4% to Tx amplitude in Gig mode */
2898 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2899 /* Disable trimming (TTT) */
2900 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2901 /* Poly DC correction to 94.6% + 2% for all channels */
2902 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2903 /* ABS DC correction to 95.9% */
2904 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2905 /* BG temp curve trim */
2906 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2907 /* Increasing ADC OPAMP stage 1 currents to max */
2908 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2909 /* Force 1000 ( required for enabling PHY regs configuration) */
2910 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2911 /* Set upd_freq to 6 */
2912 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2914 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2915 /* Disable adaptive fixed FFE (Default) */
2916 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2917 /* Enable FFE hysteresis */
2918 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2919 /* Fixed FFE for short cable lengths */
2920 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2921 /* Fixed FFE for medium cable lengths */
2922 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2923 /* Fixed FFE for long cable lengths */
2924 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2925 /* Enable Adaptive Clip Threshold */
2926 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2927 /* AHT reset limit to 1 */
2928 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2929 /* Set AHT master delay to 127 msec */
2930 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2931 /* Set scan bits for AHT */
2932 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2933 /* Set AHT Preset bits */
2934 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2935 /* Change integ_factor of channel A to 3 */
2936 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2937 /* Change prop_factor of channels BCD to 8 */
2938 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2939 /* Change cg_icount + enable integbp for channels BCD */
2940 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2941 /* Change cg_icount + enable integbp + change prop_factor_master
2942 * to 8 for channel A
2944 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2945 /* Disable AHT in Slave mode on channel A */
2946 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2947 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2950 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2951 /* Enable restart AN on an1000_dis change */
2952 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2953 /* Enable wh_fifo read clock in 10/100 modes */
2954 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2955 /* Restart AN, Speed selection is 1000 */
2956 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2958 return E1000_SUCCESS;
2962 * e1000_get_phy_type_from_id - Get PHY type from id
2963 * @phy_id: phy_id read from the phy
2965 * Returns the phy type from the id.
2967 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2969 enum e1000_phy_type phy_type = e1000_phy_unknown;
2972 case M88E1000_I_PHY_ID:
2973 case M88E1000_E_PHY_ID:
2974 case M88E1111_I_PHY_ID:
2975 case M88E1011_I_PHY_ID:
2976 case M88E1543_E_PHY_ID:
2977 case M88E1512_E_PHY_ID:
2978 case I347AT4_E_PHY_ID:
2979 case M88E1112_E_PHY_ID:
2980 case M88E1340M_E_PHY_ID:
2981 phy_type = e1000_phy_m88;
2983 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2984 phy_type = e1000_phy_igp_2;
2986 case GG82563_E_PHY_ID:
2987 phy_type = e1000_phy_gg82563;
2989 case IGP03E1000_E_PHY_ID:
2990 phy_type = e1000_phy_igp_3;
2993 case IFE_PLUS_E_PHY_ID:
2994 case IFE_C_E_PHY_ID:
2995 phy_type = e1000_phy_ife;
2997 case BME1000_E_PHY_ID:
2998 case BME1000_E_PHY_ID_R2:
2999 phy_type = e1000_phy_bm;
3001 case I82578_E_PHY_ID:
3002 phy_type = e1000_phy_82578;
3004 case I82577_E_PHY_ID:
3005 phy_type = e1000_phy_82577;
3007 case I82579_E_PHY_ID:
3008 phy_type = e1000_phy_82579;
3011 phy_type = e1000_phy_i217;
3013 case I82580_I_PHY_ID:
3014 phy_type = e1000_phy_82580;
3017 phy_type = e1000_phy_i210;
3020 phy_type = e1000_phy_unknown;
3027 * e1000_determine_phy_address - Determines PHY address.
3028 * @hw: pointer to the HW structure
3030 * This uses a trial and error method to loop through possible PHY
3031 * addresses. It tests each by reading the PHY ID registers and
3032 * checking for a match.
3034 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3038 enum e1000_phy_type phy_type = e1000_phy_unknown;
3040 hw->phy.id = phy_type;
3042 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3043 hw->phy.addr = phy_addr;
3047 e1000_get_phy_id(hw);
3048 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3050 /* If phy_type is valid, break - we found our
3053 if (phy_type != e1000_phy_unknown)
3054 return E1000_SUCCESS;
3061 return -E1000_ERR_PHY_TYPE;
3065 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3066 * @page: page to access
3068 * Returns the phy address for the page requested.
3070 STATIC u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3074 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3081 * e1000_write_phy_reg_bm - Write BM PHY register
3082 * @hw: pointer to the HW structure
3083 * @offset: register offset to write to
3084 * @data: data to write at register offset
3086 * Acquires semaphore, if necessary, then writes the data to PHY register
3087 * at the offset. Release any acquired semaphores before exiting.
3089 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3092 u32 page = offset >> IGP_PAGE_SHIFT;
3094 DEBUGFUNC("e1000_write_phy_reg_bm");
3096 ret_val = hw->phy.ops.acquire(hw);
3100 /* Page 800 works differently than the rest so it has its own func */
3101 if (page == BM_WUC_PAGE) {
3102 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3107 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3109 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3110 u32 page_shift, page_select;
3112 /* Page select is register 31 for phy address 1 and 22 for
3113 * phy address 2 and 3. Page select is shifted only for
3116 if (hw->phy.addr == 1) {
3117 page_shift = IGP_PAGE_SHIFT;
3118 page_select = IGP01E1000_PHY_PAGE_SELECT;
3121 page_select = BM_PHY_PAGE_SELECT;
3124 /* Page is shifted left, PHY expects (page x 32) */
3125 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3126 (page << page_shift));
3131 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3135 hw->phy.ops.release(hw);
3140 * e1000_read_phy_reg_bm - Read BM PHY register
3141 * @hw: pointer to the HW structure
3142 * @offset: register offset to be read
3143 * @data: pointer to the read data
3145 * Acquires semaphore, if necessary, then reads the PHY register at offset
3146 * and storing the retrieved information in data. Release any acquired
3147 * semaphores before exiting.
3149 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3152 u32 page = offset >> IGP_PAGE_SHIFT;
3154 DEBUGFUNC("e1000_read_phy_reg_bm");
3156 ret_val = hw->phy.ops.acquire(hw);
3160 /* Page 800 works differently than the rest so it has its own func */
3161 if (page == BM_WUC_PAGE) {
3162 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3167 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3169 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3170 u32 page_shift, page_select;
3172 /* Page select is register 31 for phy address 1 and 22 for
3173 * phy address 2 and 3. Page select is shifted only for
3176 if (hw->phy.addr == 1) {
3177 page_shift = IGP_PAGE_SHIFT;
3178 page_select = IGP01E1000_PHY_PAGE_SELECT;
3181 page_select = BM_PHY_PAGE_SELECT;
3184 /* Page is shifted left, PHY expects (page x 32) */
3185 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3186 (page << page_shift));
3191 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3194 hw->phy.ops.release(hw);
3199 * e1000_read_phy_reg_bm2 - Read BM PHY register
3200 * @hw: pointer to the HW structure
3201 * @offset: register offset to be read
3202 * @data: pointer to the read data
3204 * Acquires semaphore, if necessary, then reads the PHY register at offset
3205 * and storing the retrieved information in data. Release any acquired
3206 * semaphores before exiting.
3208 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3211 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3213 DEBUGFUNC("e1000_read_phy_reg_bm2");
3215 ret_val = hw->phy.ops.acquire(hw);
3219 /* Page 800 works differently than the rest so it has its own func */
3220 if (page == BM_WUC_PAGE) {
3221 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3228 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3229 /* Page is shifted left, PHY expects (page x 32) */
3230 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3237 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3240 hw->phy.ops.release(hw);
3245 * e1000_write_phy_reg_bm2 - Write BM PHY register
3246 * @hw: pointer to the HW structure
3247 * @offset: register offset to write to
3248 * @data: data to write at register offset
3250 * Acquires semaphore, if necessary, then writes the data to PHY register
3251 * at the offset. Release any acquired semaphores before exiting.
3253 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3256 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3258 DEBUGFUNC("e1000_write_phy_reg_bm2");
3260 ret_val = hw->phy.ops.acquire(hw);
3264 /* Page 800 works differently than the rest so it has its own func */
3265 if (page == BM_WUC_PAGE) {
3266 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3273 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3274 /* Page is shifted left, PHY expects (page x 32) */
3275 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3282 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3286 hw->phy.ops.release(hw);
3291 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3292 * @hw: pointer to the HW structure
3293 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3295 * Assumes semaphore already acquired and phy_reg points to a valid memory
3296 * address to store contents of the BM_WUC_ENABLE_REG register.
3298 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3303 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3306 return -E1000_ERR_PARAM;
3308 /* All page select, port ctrl and wakeup registers use phy address 1 */
3311 /* Select Port Control Registers page */
3312 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3314 DEBUGOUT("Could not set Port Control page\n");
3318 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3320 DEBUGOUT2("Could not read PHY register %d.%d\n",
3321 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3325 /* Enable both PHY wakeup mode and Wakeup register page writes.
3326 * Prevent a power state change by disabling ME and Host PHY wakeup.
3329 temp |= BM_WUC_ENABLE_BIT;
3330 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3332 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3334 DEBUGOUT2("Could not write PHY register %d.%d\n",
3335 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3339 /* Select Host Wakeup Registers page - caller now able to write
3340 * registers on the Wakeup registers page
3342 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3346 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3347 * @hw: pointer to the HW structure
3348 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3350 * Restore BM_WUC_ENABLE_REG to its original value.
3352 * Assumes semaphore already acquired and *phy_reg is the contents of the
3353 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3356 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3360 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3363 return -E1000_ERR_PARAM;
3365 /* Select Port Control Registers page */
3366 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3368 DEBUGOUT("Could not set Port Control page\n");
3372 /* Restore 769.17 to its original value */
3373 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3375 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3376 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3382 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3383 * @hw: pointer to the HW structure
3384 * @offset: register offset to be read or written
3385 * @data: pointer to the data to read or write
3386 * @read: determines if operation is read or write
3387 * @page_set: BM_WUC_PAGE already set and access enabled
3389 * Read the PHY register at offset and store the retrieved information in
3390 * data, or write data to PHY register at offset. Note the procedure to
3391 * access the PHY wakeup registers is different than reading the other PHY
3392 * registers. It works as such:
3393 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3394 * 2) Set page to 800 for host (801 if we were manageability)
3395 * 3) Write the address using the address opcode (0x11)
3396 * 4) Read or write the data using the data opcode (0x12)
3397 * 5) Restore 769.17.2 to its original value
3399 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3400 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3402 * Assumes semaphore is already acquired. When page_set==true, assumes
3403 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3404 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3406 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3407 u16 *data, bool read, bool page_set)
3410 u16 reg = BM_PHY_REG_NUM(offset);
3411 u16 page = BM_PHY_REG_PAGE(offset);
3414 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3416 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3417 if ((hw->mac.type == e1000_pchlan) &&
3418 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3419 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3423 /* Enable access to PHY wakeup registers */
3424 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3426 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3431 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3433 /* Write the Wakeup register page offset value using opcode 0x11 */
3434 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3436 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3441 /* Read the Wakeup register page value using opcode 0x12 */
3442 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3445 /* Write the Wakeup register page value using opcode 0x12 */
3446 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3451 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3456 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3462 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3463 * @hw: pointer to the HW structure
3465 * In the case of a PHY power down to save power, or to turn off link during a
3466 * driver unload, or wake on lan is not enabled, restore the link to previous
3469 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3473 /* The PHY will retain its settings across a power down/up cycle */
3474 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3475 mii_reg &= ~MII_CR_POWER_DOWN;
3476 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3480 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3481 * @hw: pointer to the HW structure
3483 * In the case of a PHY power down to save power, or to turn off link during a
3484 * driver unload, or wake on lan is not enabled, restore the link to previous
3487 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3491 /* The PHY will retain its settings across a power down/up cycle */
3492 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3493 mii_reg |= MII_CR_POWER_DOWN;
3494 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3499 * __e1000_read_phy_reg_hv - Read HV PHY register
3500 * @hw: pointer to the HW structure
3501 * @offset: register offset to be read
3502 * @data: pointer to the read data
3503 * @locked: semaphore has already been acquired or not
3505 * Acquires semaphore, if necessary, then reads the PHY register at offset
3506 * and stores the retrieved information in data. Release any acquired
3507 * semaphore before exiting.
3509 STATIC s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3510 bool locked, bool page_set)
3513 u16 page = BM_PHY_REG_PAGE(offset);
3514 u16 reg = BM_PHY_REG_NUM(offset);
3515 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3517 DEBUGFUNC("__e1000_read_phy_reg_hv");
3520 ret_val = hw->phy.ops.acquire(hw);
3524 /* Page 800 works differently than the rest so it has its own func */
3525 if (page == BM_WUC_PAGE) {
3526 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3531 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3532 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3538 if (page == HV_INTC_FC_PAGE_START)
3541 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3542 /* Page is shifted left, PHY expects (page x 32) */
3543 ret_val = e1000_set_page_igp(hw,
3544 (page << IGP_PAGE_SHIFT));
3546 hw->phy.addr = phy_addr;
3553 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3554 page << IGP_PAGE_SHIFT, reg);
3556 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3560 hw->phy.ops.release(hw);
3566 * e1000_read_phy_reg_hv - Read HV PHY register
3567 * @hw: pointer to the HW structure
3568 * @offset: register offset to be read
3569 * @data: pointer to the read data
3571 * Acquires semaphore then reads the PHY register at offset and stores
3572 * the retrieved information in data. Release the acquired semaphore
3575 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3577 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3581 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3582 * @hw: pointer to the HW structure
3583 * @offset: register offset to be read
3584 * @data: pointer to the read data
3586 * Reads the PHY register at offset and stores the retrieved information
3587 * in data. Assumes semaphore already acquired.
3589 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3591 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3595 * e1000_read_phy_reg_page_hv - Read HV PHY register
3596 * @hw: pointer to the HW structure
3597 * @offset: register offset to write to
3598 * @data: data to write at register offset
3600 * Reads the PHY register at offset and stores the retrieved information
3601 * in data. Assumes semaphore already acquired and page already set.
3603 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3605 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3609 * __e1000_write_phy_reg_hv - Write HV PHY register
3610 * @hw: pointer to the HW structure
3611 * @offset: register offset to write to
3612 * @data: data to write at register offset
3613 * @locked: semaphore has already been acquired or not
3615 * Acquires semaphore, if necessary, then writes the data to PHY register
3616 * at the offset. Release any acquired semaphores before exiting.
3618 STATIC s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3619 bool locked, bool page_set)
3622 u16 page = BM_PHY_REG_PAGE(offset);
3623 u16 reg = BM_PHY_REG_NUM(offset);
3624 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3626 DEBUGFUNC("__e1000_write_phy_reg_hv");
3629 ret_val = hw->phy.ops.acquire(hw);
3633 /* Page 800 works differently than the rest so it has its own func */
3634 if (page == BM_WUC_PAGE) {
3635 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3640 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3641 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3647 if (page == HV_INTC_FC_PAGE_START)
3650 /* Workaround MDIO accesses being disabled after entering IEEE
3651 * Power Down (when bit 11 of the PHY Control register is set)
3653 if ((hw->phy.type == e1000_phy_82578) &&
3654 (hw->phy.revision >= 1) &&
3655 (hw->phy.addr == 2) &&
3656 !(MAX_PHY_REG_ADDRESS & reg) &&
3657 (data & (1 << 11))) {
3659 ret_val = e1000_access_phy_debug_regs_hv(hw,
3666 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3667 /* Page is shifted left, PHY expects (page x 32) */
3668 ret_val = e1000_set_page_igp(hw,
3669 (page << IGP_PAGE_SHIFT));
3671 hw->phy.addr = phy_addr;
3678 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3679 page << IGP_PAGE_SHIFT, reg);
3681 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3686 hw->phy.ops.release(hw);
3692 * e1000_write_phy_reg_hv - Write HV PHY register
3693 * @hw: pointer to the HW structure
3694 * @offset: register offset to write to
3695 * @data: data to write at register offset
3697 * Acquires semaphore then writes the data to PHY register at the offset.
3698 * Release the acquired semaphores before exiting.
3700 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3702 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3706 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3707 * @hw: pointer to the HW structure
3708 * @offset: register offset to write to
3709 * @data: data to write at register offset
3711 * Writes the data to PHY register at the offset. Assumes semaphore
3714 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3716 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3720 * e1000_write_phy_reg_page_hv - Write HV PHY register
3721 * @hw: pointer to the HW structure
3722 * @offset: register offset to write to
3723 * @data: data to write at register offset
3725 * Writes the data to PHY register at the offset. Assumes semaphore
3726 * already acquired and page already set.
3728 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3730 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3734 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3735 * @page: page to be accessed
3737 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page)
3741 if (page >= HV_INTC_FC_PAGE_START)
3748 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3749 * @hw: pointer to the HW structure
3750 * @offset: register offset to be read or written
3751 * @data: pointer to the data to be read or written
3752 * @read: determines if operation is read or write
3754 * Reads the PHY register at offset and stores the retreived information
3755 * in data. Assumes semaphore already acquired. Note that the procedure
3756 * to access these regs uses the address port and data port to read/write.
3757 * These accesses done with PHY address 2 and without using pages.
3759 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3760 u16 *data, bool read)
3766 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3768 /* This takes care of the difference with desktop vs mobile phy */
3769 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3770 I82578_ADDR_REG : I82577_ADDR_REG);
3771 data_reg = addr_reg + 1;
3773 /* All operations in this function are phy address 2 */
3776 /* masking with 0x3F to remove the page from offset */
3777 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3779 DEBUGOUT("Could not write the Address Offset port register\n");
3783 /* Read or write the data value next */
3785 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3787 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3790 DEBUGOUT("Could not access the Data port register\n");
3796 * e1000_link_stall_workaround_hv - Si workaround
3797 * @hw: pointer to the HW structure
3799 * This function works around a Si bug where the link partner can get
3800 * a link up indication before the PHY does. If small packets are sent
3801 * by the link partner they can be placed in the packet buffer without
3802 * being properly accounted for by the PHY and will stall preventing
3803 * further packets from being received. The workaround is to clear the
3804 * packet buffer after the PHY detects link up.
3806 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3808 s32 ret_val = E1000_SUCCESS;
3811 DEBUGFUNC("e1000_link_stall_workaround_hv");
3813 if (hw->phy.type != e1000_phy_82578)
3814 return E1000_SUCCESS;
3816 /* Do not apply workaround if in PHY loopback bit 14 set */
3817 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3818 if (data & PHY_CONTROL_LB)
3819 return E1000_SUCCESS;
3821 /* check if link is up and at 1Gbps */
3822 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3826 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3827 BM_CS_STATUS_SPEED_MASK);
3829 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3830 BM_CS_STATUS_SPEED_1000))
3831 return E1000_SUCCESS;
3835 /* flush the packets in the fifo buffer */
3836 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3837 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3838 HV_MUX_DATA_CTRL_FORCE_SPEED));
3842 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3843 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3847 * e1000_check_polarity_82577 - Checks the polarity.
3848 * @hw: pointer to the HW structure
3850 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3852 * Polarity is determined based on the PHY specific status register.
3854 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3856 struct e1000_phy_info *phy = &hw->phy;
3860 DEBUGFUNC("e1000_check_polarity_82577");
3862 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3865 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3866 ? e1000_rev_polarity_reversed
3867 : e1000_rev_polarity_normal);
3873 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3874 * @hw: pointer to the HW structure
3876 * Calls the PHY setup function to force speed and duplex.
3878 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3880 struct e1000_phy_info *phy = &hw->phy;
3885 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3887 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3891 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3893 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3899 if (phy->autoneg_wait_to_complete) {
3900 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3902 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3908 DEBUGOUT("Link taking longer than expected.\n");
3911 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3919 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3920 * @hw: pointer to the HW structure
3922 * Read PHY status to determine if link is up. If link is up, then
3923 * set/determine 10base-T extended distance and polarity correction. Read
3924 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3925 * determine on the cable length, local and remote receiver.
3927 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3929 struct e1000_phy_info *phy = &hw->phy;
3934 DEBUGFUNC("e1000_get_phy_info_82577");
3936 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3941 DEBUGOUT("Phy info is only valid if link is up\n");
3942 return -E1000_ERR_CONFIG;
3945 phy->polarity_correction = true;
3947 ret_val = e1000_check_polarity_82577(hw);
3951 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3955 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3957 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3958 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3959 ret_val = hw->phy.ops.get_cable_length(hw);
3963 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3967 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3968 ? e1000_1000t_rx_status_ok
3969 : e1000_1000t_rx_status_not_ok;
3971 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3972 ? e1000_1000t_rx_status_ok
3973 : e1000_1000t_rx_status_not_ok;
3975 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3976 phy->local_rx = e1000_1000t_rx_status_undefined;
3977 phy->remote_rx = e1000_1000t_rx_status_undefined;
3980 return E1000_SUCCESS;
3984 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3985 * @hw: pointer to the HW structure
3987 * Reads the diagnostic status register and verifies result is valid before
3988 * placing it in the phy_cable_length field.
3990 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3992 struct e1000_phy_info *phy = &hw->phy;
3994 u16 phy_data, length;
3996 DEBUGFUNC("e1000_get_cable_length_82577");
3998 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4002 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4003 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4005 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4006 return -E1000_ERR_PHY;
4008 phy->cable_length = length;
4010 return E1000_SUCCESS;
4014 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4015 * @hw: pointer to the HW structure
4016 * @offset: register offset to write to
4017 * @data: data to write at register offset
4019 * Acquires semaphore, if necessary, then writes the data to PHY register
4020 * at the offset. Release any acquired semaphores before exiting.
4022 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4025 u16 page = offset >> GS40G_PAGE_SHIFT;
4027 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4029 offset = offset & GS40G_OFFSET_MASK;
4030 ret_val = hw->phy.ops.acquire(hw);
4034 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4037 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4040 hw->phy.ops.release(hw);
4045 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4046 * @hw: pointer to the HW structure
4047 * @offset: lower half is register offset to read to
4048 * upper half is page to use.
4049 * @data: data to read at register offset
4051 * Acquires semaphore, if necessary, then reads the data in the PHY register
4052 * at the offset. Release any acquired semaphores before exiting.
4054 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4057 u16 page = offset >> GS40G_PAGE_SHIFT;
4059 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4061 offset = offset & GS40G_OFFSET_MASK;
4062 ret_val = hw->phy.ops.acquire(hw);
4066 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4069 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4072 hw->phy.ops.release(hw);
4077 * e1000_read_phy_reg_mphy - Read mPHY control register
4078 * @hw: pointer to the HW structure
4079 * @address: address to be read
4080 * @data: pointer to the read data
4082 * Reads the mPHY control register in the PHY at offset and stores the
4083 * information read to data.
4085 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4088 bool locked = false;
4091 DEBUGFUNC("e1000_read_phy_reg_mphy");
4093 /* Check if mPHY is ready to read/write operations */
4094 ready = e1000_is_mphy_ready(hw);
4096 return -E1000_ERR_PHY;
4098 /* Check if mPHY access is disabled and enable it if so */
4099 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4100 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4102 ready = e1000_is_mphy_ready(hw);
4104 return -E1000_ERR_PHY;
4105 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4106 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4109 /* Set the address that we want to read */
4110 ready = e1000_is_mphy_ready(hw);
4112 return -E1000_ERR_PHY;
4114 /* We mask address, because we want to use only current lane */
4115 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4116 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4117 (address & E1000_MPHY_ADDRESS_MASK);
4118 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4120 /* Read data from the address */
4121 ready = e1000_is_mphy_ready(hw);
4123 return -E1000_ERR_PHY;
4124 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4126 /* Disable access to mPHY if it was originally disabled */
4128 ready = e1000_is_mphy_ready(hw);
4130 return -E1000_ERR_PHY;
4131 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4132 E1000_MPHY_DIS_ACCESS);
4135 return E1000_SUCCESS;
4139 * e1000_write_phy_reg_mphy - Write mPHY control register
4140 * @hw: pointer to the HW structure
4141 * @address: address to write to
4142 * @data: data to write to register at offset
4143 * @line_override: used when we want to use different line than default one
4145 * Writes data to mPHY control register.
4147 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4151 bool locked = false;
4154 DEBUGFUNC("e1000_write_phy_reg_mphy");
4156 /* Check if mPHY is ready to read/write operations */
4157 ready = e1000_is_mphy_ready(hw);
4159 return -E1000_ERR_PHY;
4161 /* Check if mPHY access is disabled and enable it if so */
4162 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4163 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4165 ready = e1000_is_mphy_ready(hw);
4167 return -E1000_ERR_PHY;
4168 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4169 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4172 /* Set the address that we want to read */
4173 ready = e1000_is_mphy_ready(hw);
4175 return -E1000_ERR_PHY;
4177 /* We mask address, because we want to use only current lane */
4179 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4181 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4182 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4183 (address & E1000_MPHY_ADDRESS_MASK);
4184 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4186 /* Read data from the address */
4187 ready = e1000_is_mphy_ready(hw);
4189 return -E1000_ERR_PHY;
4190 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4192 /* Disable access to mPHY if it was originally disabled */
4194 ready = e1000_is_mphy_ready(hw);
4196 return -E1000_ERR_PHY;
4197 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4198 E1000_MPHY_DIS_ACCESS);
4201 return E1000_SUCCESS;
4205 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4206 * @hw: pointer to the HW structure
4208 * Returns mPHY control register status.
4210 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4212 u16 retry_count = 0;
4216 while (retry_count < 2) {
4217 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4218 if (mphy_ctrl & E1000_MPHY_BUSY) {
4228 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4234 * __e1000_access_xmdio_reg - Read/write XMDIO register
4235 * @hw: pointer to the HW structure
4236 * @address: XMDIO address to program
4237 * @dev_addr: device address to program
4238 * @data: pointer to value to read/write from/to the XMDIO address
4239 * @read: boolean flag to indicate read or write
4241 STATIC s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
4242 u8 dev_addr, u16 *data, bool read)
4246 DEBUGFUNC("__e1000_access_xmdio_reg");
4248 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
4252 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
4256 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
4262 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
4264 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
4268 /* Recalibrate the device back to 0 */
4269 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
4277 * e1000_read_xmdio_reg - Read XMDIO register
4278 * @hw: pointer to the HW structure
4279 * @addr: XMDIO address to program
4280 * @dev_addr: device address to program
4281 * @data: value to be read from the EMI address
4283 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
4285 DEBUGFUNC("e1000_read_xmdio_reg");
4287 return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);
4291 * e1000_write_xmdio_reg - Write XMDIO register
4292 * @hw: pointer to the HW structure
4293 * @addr: XMDIO address to program
4294 * @dev_addr: device address to program
4295 * @data: value to be written to the XMDIO address
4297 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
4299 DEBUGFUNC("e1000_write_xmdio_reg");
4301 return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data,