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34 #ifndef _E1000_ETHDEV_H_
35 #define _E1000_ETHDEV_H_
38 /* need update link, bit flag */
39 #define E1000_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
40 #define E1000_FLAG_MAILBOX (uint32_t)(1 << 1)
43 * Defines that were not part of e1000_hw.h as they are not used by the FreeBSD
46 #define E1000_ADVTXD_POPTS_TXSM 0x00000200 /* L4 Checksum offload request */
47 #define E1000_ADVTXD_POPTS_IXSM 0x00000100 /* IP Checksum offload request */
48 #define E1000_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE of Reserved */
49 #define E1000_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
50 #define E1000_RXD_ERR_CKSUM_BIT 29
51 #define E1000_RXD_ERR_CKSUM_MSK 3
52 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
53 #define E1000_CTRL_EXT_EXTEND_VLAN (1<<26) /* EXTENDED VLAN */
54 #define IGB_VFTA_SIZE 128
56 #define IGB_MAX_RX_QUEUE_NUM 8
57 #define IGB_MAX_RX_QUEUE_NUM_82576 16
59 #define E1000_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
60 #define E1000_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */
61 #define E1000_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */
62 #define E1000_RFCTL_SYNQFP 0x00080000 /* SYNQFP in RFCTL register */
64 #define E1000_ETQF_ETHERTYPE 0x0000FFFF
65 #define E1000_ETQF_QUEUE 0x00070000
66 #define E1000_ETQF_QUEUE_SHIFT 16
67 #define E1000_MAX_ETQF_FILTERS 8
69 #define E1000_IMIR_DSTPORT 0x0000FFFF
70 #define E1000_IMIR_PRIORITY 0xE0000000
71 #define E1000_MAX_TTQF_FILTERS 8
72 #define E1000_2TUPLE_MAX_PRI 7
74 #define E1000_MAX_FLEX_FILTERS 8
75 #define E1000_MAX_FHFT 4
76 #define E1000_MAX_FHFT_EXT 4
77 #define E1000_FHFT_SIZE_IN_DWD 64
78 #define E1000_MAX_FLEX_FILTER_PRI 7
79 #define E1000_MAX_FLEX_FILTER_LEN 128
80 #define E1000_MAX_FLEX_FILTER_DWDS \
81 (E1000_MAX_FLEX_FILTER_LEN / sizeof(uint32_t))
82 #define E1000_FLEX_FILTERS_MASK_SIZE \
83 (E1000_MAX_FLEX_FILTER_DWDS / 4)
84 #define E1000_FHFT_QUEUEING_LEN 0x0000007F
85 #define E1000_FHFT_QUEUEING_QUEUE 0x00000700
86 #define E1000_FHFT_QUEUEING_PRIO 0x00070000
87 #define E1000_FHFT_QUEUEING_OFFSET 0xFC
88 #define E1000_FHFT_QUEUEING_QUEUE_SHIFT 8
89 #define E1000_FHFT_QUEUEING_PRIO_SHIFT 16
90 #define E1000_WUFC_FLEX_HQ 0x00004000
92 #define E1000_SPQF_SRCPORT 0x0000FFFF
94 #define E1000_MAX_FTQF_FILTERS 8
95 #define E1000_FTQF_PROTOCOL_MASK 0x000000FF
96 #define E1000_FTQF_5TUPLE_MASK_SHIFT 28
97 #define E1000_FTQF_QUEUE_MASK 0x03ff0000
98 #define E1000_FTQF_QUEUE_SHIFT 16
99 #define E1000_FTQF_QUEUE_ENABLE 0x00000100
101 #define IGB_RSS_OFFLOAD_ALL ( \
103 ETH_RSS_NONFRAG_IPV4_TCP | \
104 ETH_RSS_NONFRAG_IPV4_UDP | \
106 ETH_RSS_NONFRAG_IPV6_TCP | \
107 ETH_RSS_NONFRAG_IPV6_UDP | \
109 ETH_RSS_IPV6_TCP_EX | \
113 * Maximum number of Ring Descriptors.
115 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
116 * desscriptors should meet the following condition:
117 * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
119 #define E1000_MIN_RING_DESC 32
120 #define E1000_MAX_RING_DESC 4096
123 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
124 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
125 * This will also optimize cache line size effect.
126 * H/W supports up to cache line size 128.
128 #define E1000_ALIGN 128
130 #define IGB_RXD_ALIGN (E1000_ALIGN / sizeof(union e1000_adv_rx_desc))
131 #define IGB_TXD_ALIGN (E1000_ALIGN / sizeof(union e1000_adv_tx_desc))
133 #define EM_RXD_ALIGN (E1000_ALIGN / sizeof(struct e1000_rx_desc))
134 #define EM_TXD_ALIGN (E1000_ALIGN / sizeof(struct e1000_data_desc))
136 #define E1000_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
137 #define E1000_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
139 /* structure for interrupt relative data */
140 struct e1000_interrupt {
145 /* local vfta copy */
147 uint32_t vfta[IGB_VFTA_SIZE];
151 * VF data which used by PF host only
153 #define E1000_MAX_VF_MC_ENTRIES 30
154 struct e1000_vf_info {
155 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
156 uint16_t vf_mc_hashes[E1000_MAX_VF_MC_ENTRIES];
157 uint16_t num_vf_mc_hashes;
158 uint16_t default_vf_vlan_id;
159 uint16_t vlans_enabled;
165 TAILQ_HEAD(e1000_flex_filter_list, e1000_flex_filter);
167 struct e1000_flex_filter_info {
169 uint32_t dwords[E1000_MAX_FLEX_FILTER_DWDS]; /* flex bytes in dword. */
170 /* if mask bit is 1b, do not compare corresponding byte in dwords. */
171 uint8_t mask[E1000_FLEX_FILTERS_MASK_SIZE];
175 /* Flex filter structure */
176 struct e1000_flex_filter {
177 TAILQ_ENTRY(e1000_flex_filter) entries;
178 uint16_t index; /* index of flex filter */
179 struct e1000_flex_filter_info filter_info;
180 uint16_t queue; /* rx queue assigned to */
183 TAILQ_HEAD(e1000_5tuple_filter_list, e1000_5tuple_filter);
184 TAILQ_HEAD(e1000_2tuple_filter_list, e1000_2tuple_filter);
186 struct e1000_5tuple_filter_info {
191 uint8_t proto; /* l4 protocol. */
192 /* the packet matched above 5tuple and contain any set bit will hit this filter. */
194 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
195 used when more than one filter matches. */
196 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
197 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
198 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
199 src_port_mask:1, /* if mask is 1b, do not compare src port. */
200 proto_mask:1; /* if mask is 1b, do not compare protocol. */
203 struct e1000_2tuple_filter_info {
205 uint8_t proto; /* l4 protocol. */
206 /* the packet matched above 2tuple and contain any set bit will hit this filter. */
208 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
209 used when more than one filter matches. */
210 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
211 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
212 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
213 src_port_mask:1, /* if mask is 1b, do not compare src port. */
214 proto_mask:1; /* if mask is 1b, do not compare protocol. */
217 /* 5tuple filter structure */
218 struct e1000_5tuple_filter {
219 TAILQ_ENTRY(e1000_5tuple_filter) entries;
220 uint16_t index; /* the index of 5tuple filter */
221 struct e1000_5tuple_filter_info filter_info;
222 uint16_t queue; /* rx queue assigned to */
225 /* 2tuple filter structure */
226 struct e1000_2tuple_filter {
227 TAILQ_ENTRY(e1000_2tuple_filter) entries;
228 uint16_t index; /* the index of 2tuple filter */
229 struct e1000_2tuple_filter_info filter_info;
230 uint16_t queue; /* rx queue assigned to */
234 * Structure to store filters' info.
236 struct e1000_filter_info {
237 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
238 /* store used ethertype filters*/
239 uint16_t ethertype_filters[E1000_MAX_ETQF_FILTERS];
240 uint8_t flex_mask; /* Bit mask for every used flex filter */
241 struct e1000_flex_filter_list flex_list;
242 /* Bit mask for every used 5tuple filter */
243 uint8_t fivetuple_mask;
244 struct e1000_5tuple_filter_list fivetuple_list;
245 /* Bit mask for every used 2tuple filter */
246 uint8_t twotuple_mask;
247 struct e1000_2tuple_filter_list twotuple_list;
251 * Structure to store private data for each driver instance (for each port).
253 struct e1000_adapter {
255 struct e1000_hw_stats stats;
256 struct e1000_interrupt intr;
257 struct e1000_vfta shadow_vfta;
258 struct e1000_vf_info *vfdata;
259 struct e1000_filter_info filter;
261 struct rte_timecounter systime_tc;
262 struct rte_timecounter rx_tstamp_tc;
263 struct rte_timecounter tx_tstamp_tc;
266 #define E1000_DEV_PRIVATE(adapter) \
267 ((struct e1000_adapter *)adapter)
269 #define E1000_DEV_PRIVATE_TO_HW(adapter) \
270 (&((struct e1000_adapter *)adapter)->hw)
272 #define E1000_DEV_PRIVATE_TO_STATS(adapter) \
273 (&((struct e1000_adapter *)adapter)->stats)
275 #define E1000_DEV_PRIVATE_TO_INTR(adapter) \
276 (&((struct e1000_adapter *)adapter)->intr)
278 #define E1000_DEV_PRIVATE_TO_VFTA(adapter) \
279 (&((struct e1000_adapter *)adapter)->shadow_vfta)
281 #define E1000_DEV_PRIVATE_TO_P_VFDATA(adapter) \
282 (&((struct e1000_adapter *)adapter)->vfdata)
284 #define E1000_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
285 (&((struct e1000_adapter *)adapter)->filter)
288 * RX/TX IGB function prototypes
290 void eth_igb_tx_queue_release(void *txq);
291 void eth_igb_rx_queue_release(void *rxq);
292 void igb_dev_clear_queues(struct rte_eth_dev *dev);
293 void igb_dev_free_queues(struct rte_eth_dev *dev);
295 int eth_igb_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
296 uint16_t nb_rx_desc, unsigned int socket_id,
297 const struct rte_eth_rxconf *rx_conf,
298 struct rte_mempool *mb_pool);
300 uint32_t eth_igb_rx_queue_count(struct rte_eth_dev *dev,
301 uint16_t rx_queue_id);
303 int eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset);
305 int eth_igb_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
306 uint16_t nb_tx_desc, unsigned int socket_id,
307 const struct rte_eth_txconf *tx_conf);
309 int eth_igb_rx_init(struct rte_eth_dev *dev);
311 void eth_igb_tx_init(struct rte_eth_dev *dev);
313 uint16_t eth_igb_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts,
316 uint16_t eth_igb_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts,
319 uint16_t eth_igb_recv_scattered_pkts(void *rxq,
320 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
322 int eth_igb_rss_hash_update(struct rte_eth_dev *dev,
323 struct rte_eth_rss_conf *rss_conf);
325 int eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev,
326 struct rte_eth_rss_conf *rss_conf);
328 int eth_igbvf_rx_init(struct rte_eth_dev *dev);
330 void eth_igbvf_tx_init(struct rte_eth_dev *dev);
333 * misc function prototypes
335 void igb_pf_host_init(struct rte_eth_dev *eth_dev);
337 void igb_pf_mbx_process(struct rte_eth_dev *eth_dev);
339 int igb_pf_host_configure(struct rte_eth_dev *eth_dev);
341 void igb_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
342 struct rte_eth_rxq_info *qinfo);
344 void igb_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
345 struct rte_eth_txq_info *qinfo);
348 * RX/TX EM function prototypes
350 void eth_em_tx_queue_release(void *txq);
351 void eth_em_rx_queue_release(void *rxq);
353 void em_dev_clear_queues(struct rte_eth_dev *dev);
354 void em_dev_free_queues(struct rte_eth_dev *dev);
356 int eth_em_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
357 uint16_t nb_rx_desc, unsigned int socket_id,
358 const struct rte_eth_rxconf *rx_conf,
359 struct rte_mempool *mb_pool);
361 uint32_t eth_em_rx_queue_count(struct rte_eth_dev *dev,
362 uint16_t rx_queue_id);
364 int eth_em_rx_descriptor_done(void *rx_queue, uint16_t offset);
366 int eth_em_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
367 uint16_t nb_tx_desc, unsigned int socket_id,
368 const struct rte_eth_txconf *tx_conf);
370 int eth_em_rx_init(struct rte_eth_dev *dev);
372 void eth_em_tx_init(struct rte_eth_dev *dev);
374 uint16_t eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
377 uint16_t eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
380 uint16_t eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
383 void em_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
384 struct rte_eth_rxq_info *qinfo);
386 void em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
387 struct rte_eth_txq_info *qinfo);
389 void igb_pf_host_uninit(struct rte_eth_dev *dev);
391 #endif /* _E1000_ETHDEV_H_ */