1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
15 #include <rte_debug.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memory.h>
23 #include <rte_atomic.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
31 #define EM_EIAC 0x000DC
33 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
36 static int eth_em_configure(struct rte_eth_dev *dev);
37 static int eth_em_start(struct rte_eth_dev *dev);
38 static void eth_em_stop(struct rte_eth_dev *dev);
39 static void eth_em_close(struct rte_eth_dev *dev);
40 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
41 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
42 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
43 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
44 static int eth_em_link_update(struct rte_eth_dev *dev,
45 int wait_to_complete);
46 static int eth_em_stats_get(struct rte_eth_dev *dev,
47 struct rte_eth_stats *rte_stats);
48 static void eth_em_stats_reset(struct rte_eth_dev *dev);
49 static void eth_em_infos_get(struct rte_eth_dev *dev,
50 struct rte_eth_dev_info *dev_info);
51 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
52 struct rte_eth_fc_conf *fc_conf);
53 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
54 struct rte_eth_fc_conf *fc_conf);
55 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
56 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
57 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
58 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
59 struct rte_intr_handle *handle);
60 static void eth_em_interrupt_handler(void *param);
62 static int em_hw_init(struct e1000_hw *hw);
63 static int em_hardware_init(struct e1000_hw *hw);
64 static void em_hw_control_acquire(struct e1000_hw *hw);
65 static void em_hw_control_release(struct e1000_hw *hw);
66 static void em_init_manageability(struct e1000_hw *hw);
67 static void em_release_manageability(struct e1000_hw *hw);
69 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
71 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
72 uint16_t vlan_id, int on);
73 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
74 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
75 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
76 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
77 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
80 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
81 uint16_t vlan_id, int on);
84 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
85 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
86 static void em_lsc_intr_disable(struct e1000_hw *hw);
87 static void em_rxq_intr_enable(struct e1000_hw *hw);
88 static void em_rxq_intr_disable(struct e1000_hw *hw);
90 static int eth_em_led_on(struct rte_eth_dev *dev);
91 static int eth_em_led_off(struct rte_eth_dev *dev);
93 static int em_get_rx_buffer_size(struct e1000_hw *hw);
94 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
95 uint32_t index, uint32_t pool);
96 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
98 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
99 struct ether_addr *mc_addr_set,
100 uint32_t nb_mc_addr);
102 #define EM_FC_PAUSE_TIME 0x0680
103 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
104 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
106 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
108 int e1000_logtype_init;
109 int e1000_logtype_driver;
112 * The set of PCI devices this driver supports
114 static const struct rte_pci_id pci_id_em_map[] = {
115 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
116 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
117 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
118 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
119 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
120 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
121 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
122 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
123 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
124 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
125 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
126 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
127 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
128 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
129 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
130 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
131 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
132 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
133 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
134 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
135 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
136 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
137 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
138 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
139 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
140 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
160 { .vendor_id = 0, /* sentinel */ },
163 static const struct eth_dev_ops eth_em_ops = {
164 .dev_configure = eth_em_configure,
165 .dev_start = eth_em_start,
166 .dev_stop = eth_em_stop,
167 .dev_close = eth_em_close,
168 .promiscuous_enable = eth_em_promiscuous_enable,
169 .promiscuous_disable = eth_em_promiscuous_disable,
170 .allmulticast_enable = eth_em_allmulticast_enable,
171 .allmulticast_disable = eth_em_allmulticast_disable,
172 .link_update = eth_em_link_update,
173 .stats_get = eth_em_stats_get,
174 .stats_reset = eth_em_stats_reset,
175 .dev_infos_get = eth_em_infos_get,
176 .mtu_set = eth_em_mtu_set,
177 .vlan_filter_set = eth_em_vlan_filter_set,
178 .vlan_offload_set = eth_em_vlan_offload_set,
179 .rx_queue_setup = eth_em_rx_queue_setup,
180 .rx_queue_release = eth_em_rx_queue_release,
181 .rx_queue_count = eth_em_rx_queue_count,
182 .rx_descriptor_done = eth_em_rx_descriptor_done,
183 .rx_descriptor_status = eth_em_rx_descriptor_status,
184 .tx_descriptor_status = eth_em_tx_descriptor_status,
185 .tx_queue_setup = eth_em_tx_queue_setup,
186 .tx_queue_release = eth_em_tx_queue_release,
187 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
188 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
189 .dev_led_on = eth_em_led_on,
190 .dev_led_off = eth_em_led_off,
191 .flow_ctrl_get = eth_em_flow_ctrl_get,
192 .flow_ctrl_set = eth_em_flow_ctrl_set,
193 .mac_addr_add = eth_em_rar_set,
194 .mac_addr_remove = eth_em_rar_clear,
195 .set_mc_addr_list = eth_em_set_mc_addr_list,
196 .rxq_info_get = em_rxq_info_get,
197 .txq_info_get = em_txq_info_get,
201 * Atomically reads the link status information from global
202 * structure rte_eth_dev.
205 * - Pointer to the structure rte_eth_dev to read from.
206 * - Pointer to the buffer to be saved with the link status.
209 * - On success, zero.
210 * - On failure, negative value.
213 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
214 struct rte_eth_link *link)
216 struct rte_eth_link *dst = link;
217 struct rte_eth_link *src = &(dev->data->dev_link);
219 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
220 *(uint64_t *)src) == 0)
227 * Atomically writes the link status information into global
228 * structure rte_eth_dev.
231 * - Pointer to the structure rte_eth_dev to read from.
232 * - Pointer to the buffer to be saved with the link status.
235 * - On success, zero.
236 * - On failure, negative value.
239 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
240 struct rte_eth_link *link)
242 struct rte_eth_link *dst = &(dev->data->dev_link);
243 struct rte_eth_link *src = link;
245 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
246 *(uint64_t *)src) == 0)
253 * eth_em_dev_is_ich8 - Check for ICH8 device
254 * @hw: pointer to the HW structure
256 * return TRUE for ICH8, otherwise FALSE
259 eth_em_dev_is_ich8(struct e1000_hw *hw)
261 DEBUGFUNC("eth_em_dev_is_ich8");
263 switch (hw->device_id) {
264 case E1000_DEV_ID_PCH2_LV_LM:
265 case E1000_DEV_ID_PCH_LPT_I217_LM:
266 case E1000_DEV_ID_PCH_LPT_I217_V:
267 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
268 case E1000_DEV_ID_PCH_LPTLP_I218_V:
269 case E1000_DEV_ID_PCH_I218_V2:
270 case E1000_DEV_ID_PCH_I218_LM2:
271 case E1000_DEV_ID_PCH_I218_V3:
272 case E1000_DEV_ID_PCH_I218_LM3:
273 case E1000_DEV_ID_PCH_SPT_I219_LM:
274 case E1000_DEV_ID_PCH_SPT_I219_V:
275 case E1000_DEV_ID_PCH_SPT_I219_LM2:
276 case E1000_DEV_ID_PCH_SPT_I219_V2:
277 case E1000_DEV_ID_PCH_LBG_I219_LM3:
278 case E1000_DEV_ID_PCH_SPT_I219_LM4:
279 case E1000_DEV_ID_PCH_SPT_I219_V4:
280 case E1000_DEV_ID_PCH_SPT_I219_LM5:
281 case E1000_DEV_ID_PCH_SPT_I219_V5:
282 case E1000_DEV_ID_PCH_CNP_I219_LM6:
283 case E1000_DEV_ID_PCH_CNP_I219_V6:
284 case E1000_DEV_ID_PCH_CNP_I219_LM7:
285 case E1000_DEV_ID_PCH_CNP_I219_V7:
293 eth_em_dev_init(struct rte_eth_dev *eth_dev)
295 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
296 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
297 struct e1000_adapter *adapter =
298 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
299 struct e1000_hw *hw =
300 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
301 struct e1000_vfta * shadow_vfta =
302 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
304 eth_dev->dev_ops = ð_em_ops;
305 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
306 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
307 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
309 /* for secondary processes, we don't initialise any further as primary
310 * has already done this work. Only check we don't need a different
312 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
313 if (eth_dev->data->scattered_rx)
314 eth_dev->rx_pkt_burst =
315 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
319 rte_eth_copy_pci_info(eth_dev, pci_dev);
321 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
322 hw->device_id = pci_dev->id.device_id;
323 adapter->stopped = 0;
325 /* For ICH8 support we'll need to map the flash memory BAR */
326 if (eth_em_dev_is_ich8(hw))
327 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
329 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
330 em_hw_init(hw) != 0) {
331 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
333 eth_dev->data->port_id, pci_dev->id.vendor_id,
334 pci_dev->id.device_id);
338 /* Allocate memory for storing MAC addresses */
339 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
340 hw->mac.rar_entry_count, 0);
341 if (eth_dev->data->mac_addrs == NULL) {
342 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
343 "store MAC addresses",
344 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
348 /* Copy the permanent MAC address */
349 ether_addr_copy((struct ether_addr *) hw->mac.addr,
350 eth_dev->data->mac_addrs);
352 /* initialize the vfta */
353 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
355 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
356 eth_dev->data->port_id, pci_dev->id.vendor_id,
357 pci_dev->id.device_id);
359 rte_intr_callback_register(intr_handle,
360 eth_em_interrupt_handler, eth_dev);
366 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
368 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
369 struct e1000_adapter *adapter =
370 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
371 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
373 PMD_INIT_FUNC_TRACE();
375 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
378 if (adapter->stopped == 0)
379 eth_em_close(eth_dev);
381 eth_dev->dev_ops = NULL;
382 eth_dev->rx_pkt_burst = NULL;
383 eth_dev->tx_pkt_burst = NULL;
385 rte_free(eth_dev->data->mac_addrs);
386 eth_dev->data->mac_addrs = NULL;
388 /* disable uio intr before callback unregister */
389 rte_intr_disable(intr_handle);
390 rte_intr_callback_unregister(intr_handle,
391 eth_em_interrupt_handler, eth_dev);
396 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
397 struct rte_pci_device *pci_dev)
399 return rte_eth_dev_pci_generic_probe(pci_dev,
400 sizeof(struct e1000_adapter), eth_em_dev_init);
403 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
405 return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
408 static struct rte_pci_driver rte_em_pmd = {
409 .id_table = pci_id_em_map,
410 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
411 RTE_PCI_DRV_IOVA_AS_VA,
412 .probe = eth_em_pci_probe,
413 .remove = eth_em_pci_remove,
417 em_hw_init(struct e1000_hw *hw)
421 diag = hw->mac.ops.init_params(hw);
423 PMD_INIT_LOG(ERR, "MAC Initialization Error");
426 diag = hw->nvm.ops.init_params(hw);
428 PMD_INIT_LOG(ERR, "NVM Initialization Error");
431 diag = hw->phy.ops.init_params(hw);
433 PMD_INIT_LOG(ERR, "PHY Initialization Error");
436 (void) e1000_get_bus_info(hw);
439 hw->phy.autoneg_wait_to_complete = 0;
440 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
442 e1000_init_script_state_82541(hw, TRUE);
443 e1000_set_tbi_compatibility_82543(hw, TRUE);
446 if (hw->phy.media_type == e1000_media_type_copper) {
447 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
448 hw->phy.disable_polarity_correction = 0;
449 hw->phy.ms_type = e1000_ms_hw_default;
453 * Start from a known state, this is important in reading the nvm
458 /* Make sure we have a good EEPROM before we read from it */
459 if (e1000_validate_nvm_checksum(hw) < 0) {
461 * Some PCI-E parts fail the first check due to
462 * the link being in sleep state, call it again,
463 * if it fails a second time its a real issue.
465 diag = e1000_validate_nvm_checksum(hw);
467 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
472 /* Read the permanent MAC address out of the EEPROM */
473 diag = e1000_read_mac_addr(hw);
475 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
479 /* Now initialize the hardware */
480 diag = em_hardware_init(hw);
482 PMD_INIT_LOG(ERR, "Hardware initialization failed");
486 hw->mac.get_link_status = 1;
488 /* Indicate SOL/IDER usage */
489 diag = e1000_check_reset_block(hw);
491 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
497 em_hw_control_release(hw);
502 eth_em_configure(struct rte_eth_dev *dev)
504 struct e1000_interrupt *intr =
505 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
507 PMD_INIT_FUNC_TRACE();
508 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
509 PMD_INIT_FUNC_TRACE();
515 em_set_pba(struct e1000_hw *hw)
520 * Packet Buffer Allocation (PBA)
521 * Writing PBA sets the receive portion of the buffer
522 * the remainder is used for the transmit buffer.
523 * Devices before the 82547 had a Packet Buffer of 64K.
524 * After the 82547 the buffer was reduced to 40K.
526 switch (hw->mac.type) {
528 case e1000_82547_rev_2:
529 /* 82547: Total Packet Buffer is 40K */
530 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
534 case e1000_80003es2lan:
535 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
537 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
538 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
542 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
559 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
562 E1000_WRITE_REG(hw, E1000_PBA, pba);
566 eth_em_rxtx_control(struct rte_eth_dev *dev,
569 struct e1000_hw *hw =
570 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
573 tctl = E1000_READ_REG(hw, E1000_TCTL);
574 rctl = E1000_READ_REG(hw, E1000_RCTL);
577 tctl |= E1000_TCTL_EN;
578 rctl |= E1000_RCTL_EN;
581 tctl &= ~E1000_TCTL_EN;
582 rctl &= ~E1000_RCTL_EN;
584 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
585 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
586 E1000_WRITE_FLUSH(hw);
590 eth_em_start(struct rte_eth_dev *dev)
592 struct e1000_adapter *adapter =
593 E1000_DEV_PRIVATE(dev->data->dev_private);
594 struct e1000_hw *hw =
595 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
596 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
597 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
599 uint32_t intr_vector = 0;
604 PMD_INIT_FUNC_TRACE();
608 e1000_power_up_phy(hw);
610 /* Set default PBA value */
613 /* Put the address into the Receive Address Array */
614 e1000_rar_set(hw, hw->mac.addr, 0);
617 * With the 82571 adapter, RAR[0] may be overwritten
618 * when the other port is reset, we make a duplicate
619 * in RAR[14] for that eventuality, this assures
620 * the interface continues to function.
622 if (hw->mac.type == e1000_82571) {
623 e1000_set_laa_state_82571(hw, TRUE);
624 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
627 /* Initialize the hardware */
628 if (em_hardware_init(hw)) {
629 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
633 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
635 /* Configure for OS presence */
636 em_init_manageability(hw);
638 if (dev->data->dev_conf.intr_conf.rxq != 0) {
639 intr_vector = dev->data->nb_rx_queues;
640 if (rte_intr_efd_enable(intr_handle, intr_vector))
644 if (rte_intr_dp_is_en(intr_handle)) {
645 intr_handle->intr_vec =
646 rte_zmalloc("intr_vec",
647 dev->data->nb_rx_queues * sizeof(int), 0);
648 if (intr_handle->intr_vec == NULL) {
649 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
650 " intr_vec", dev->data->nb_rx_queues);
654 /* enable rx interrupt */
655 em_rxq_intr_enable(hw);
660 ret = eth_em_rx_init(dev);
662 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
663 em_dev_clear_queues(dev);
667 e1000_clear_hw_cntrs_base_generic(hw);
669 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
670 ETH_VLAN_EXTEND_MASK;
671 ret = eth_em_vlan_offload_set(dev, mask);
673 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
674 em_dev_clear_queues(dev);
678 /* Set Interrupt Throttling Rate to maximum allowed value. */
679 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
681 /* Setup link speed and duplex */
682 speeds = &dev->data->dev_conf.link_speeds;
683 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
684 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
688 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
691 hw->phy.autoneg_advertised = 0;
693 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
694 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
695 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
697 goto error_invalid_config;
699 if (*speeds & ETH_LINK_SPEED_10M_HD) {
700 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
703 if (*speeds & ETH_LINK_SPEED_10M) {
704 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
707 if (*speeds & ETH_LINK_SPEED_100M_HD) {
708 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
711 if (*speeds & ETH_LINK_SPEED_100M) {
712 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
715 if (*speeds & ETH_LINK_SPEED_1G) {
716 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
719 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
720 goto error_invalid_config;
722 /* Set/reset the mac.autoneg based on the link speed,
727 hw->mac.forced_speed_duplex =
728 hw->phy.autoneg_advertised;
734 e1000_setup_link(hw);
736 if (rte_intr_allow_others(intr_handle)) {
737 /* check if lsc interrupt is enabled */
738 if (dev->data->dev_conf.intr_conf.lsc != 0) {
739 ret = eth_em_interrupt_setup(dev);
741 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
742 em_dev_clear_queues(dev);
747 rte_intr_callback_unregister(intr_handle,
748 eth_em_interrupt_handler,
750 if (dev->data->dev_conf.intr_conf.lsc != 0)
751 PMD_INIT_LOG(INFO, "lsc won't enable because of"
752 " no intr multiplexn");
754 /* check if rxq interrupt is enabled */
755 if (dev->data->dev_conf.intr_conf.rxq != 0)
756 eth_em_rxq_interrupt_setup(dev);
758 rte_intr_enable(intr_handle);
760 adapter->stopped = 0;
762 eth_em_rxtx_control(dev, true);
763 eth_em_link_update(dev, 0);
765 PMD_INIT_LOG(DEBUG, "<<");
769 error_invalid_config:
770 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
771 dev->data->dev_conf.link_speeds, dev->data->port_id);
772 em_dev_clear_queues(dev);
776 /*********************************************************************
778 * This routine disables all traffic on the adapter by issuing a
779 * global reset on the MAC.
781 **********************************************************************/
783 eth_em_stop(struct rte_eth_dev *dev)
785 struct rte_eth_link link;
786 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
787 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
788 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
790 eth_em_rxtx_control(dev, false);
791 em_rxq_intr_disable(hw);
792 em_lsc_intr_disable(hw);
795 if (hw->mac.type >= e1000_82544)
796 E1000_WRITE_REG(hw, E1000_WUC, 0);
798 /* Power down the phy. Needed to make the link go down */
799 e1000_power_down_phy(hw);
801 em_dev_clear_queues(dev);
803 /* clear the recorded link status */
804 memset(&link, 0, sizeof(link));
805 rte_em_dev_atomic_write_link_status(dev, &link);
807 if (!rte_intr_allow_others(intr_handle))
808 /* resume to the default handler */
809 rte_intr_callback_register(intr_handle,
810 eth_em_interrupt_handler,
813 /* Clean datapath event and queue/vec mapping */
814 rte_intr_efd_disable(intr_handle);
815 if (intr_handle->intr_vec != NULL) {
816 rte_free(intr_handle->intr_vec);
817 intr_handle->intr_vec = NULL;
822 eth_em_close(struct rte_eth_dev *dev)
824 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
825 struct e1000_adapter *adapter =
826 E1000_DEV_PRIVATE(dev->data->dev_private);
829 adapter->stopped = 1;
830 em_dev_free_queues(dev);
831 e1000_phy_hw_reset(hw);
832 em_release_manageability(hw);
833 em_hw_control_release(hw);
837 em_get_rx_buffer_size(struct e1000_hw *hw)
839 uint32_t rx_buf_size;
841 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
845 /*********************************************************************
847 * Initialize the hardware
849 **********************************************************************/
851 em_hardware_init(struct e1000_hw *hw)
853 uint32_t rx_buf_size;
856 /* Issue a global reset */
859 /* Let the firmware know the OS is in control */
860 em_hw_control_acquire(hw);
863 * These parameters control the automatic generation (Tx) and
864 * response (Rx) to Ethernet PAUSE frames.
865 * - High water mark should allow for at least two standard size (1518)
866 * frames to be received after sending an XOFF.
867 * - Low water mark works best when it is very near the high water mark.
868 * This allows the receiver to restart by sending XON when it has
869 * drained a bit. Here we use an arbitrary value of 1500 which will
870 * restart after one full frame is pulled from the buffer. There
871 * could be several smaller frames in the buffer and if so they will
872 * not trigger the XON until their total number reduces the buffer
874 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
876 rx_buf_size = em_get_rx_buffer_size(hw);
878 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
879 hw->fc.low_water = hw->fc.high_water - 1500;
881 if (hw->mac.type == e1000_80003es2lan)
882 hw->fc.pause_time = UINT16_MAX;
884 hw->fc.pause_time = EM_FC_PAUSE_TIME;
888 /* Set Flow control, use the tunable location if sane */
889 if (em_fc_setting <= e1000_fc_full)
890 hw->fc.requested_mode = em_fc_setting;
892 hw->fc.requested_mode = e1000_fc_none;
894 /* Workaround: no TX flow ctrl for PCH */
895 if (hw->mac.type == e1000_pchlan)
896 hw->fc.requested_mode = e1000_fc_rx_pause;
898 /* Override - settings for PCH2LAN, ya its magic :) */
899 if (hw->mac.type == e1000_pch2lan) {
900 hw->fc.high_water = 0x5C20;
901 hw->fc.low_water = 0x5048;
902 hw->fc.pause_time = 0x0650;
903 hw->fc.refresh_time = 0x0400;
904 } else if (hw->mac.type == e1000_pch_lpt ||
905 hw->mac.type == e1000_pch_spt ||
906 hw->mac.type == e1000_pch_cnp) {
907 hw->fc.requested_mode = e1000_fc_full;
910 diag = e1000_init_hw(hw);
913 e1000_check_for_link(hw);
917 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
919 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
921 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
922 struct e1000_hw_stats *stats =
923 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
926 if(hw->phy.media_type == e1000_media_type_copper ||
927 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
928 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
929 stats->sec += E1000_READ_REG(hw, E1000_SEC);
932 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
933 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
934 stats->scc += E1000_READ_REG(hw, E1000_SCC);
935 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
937 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
938 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
939 stats->colc += E1000_READ_REG(hw, E1000_COLC);
940 stats->dc += E1000_READ_REG(hw, E1000_DC);
941 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
942 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
943 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
946 * For watchdog management we need to know if we have been
947 * paused during the last interval, so capture that here.
949 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
950 stats->xoffrxc += pause_frames;
951 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
952 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
953 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
954 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
955 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
956 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
957 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
958 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
959 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
960 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
961 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
962 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
965 * For the 64-bit byte counters the low dword must be read first.
966 * Both registers clear on the read of the high dword.
969 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
970 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
971 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
972 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
974 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
975 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
976 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
977 stats->roc += E1000_READ_REG(hw, E1000_ROC);
978 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
980 stats->tor += E1000_READ_REG(hw, E1000_TORH);
981 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
983 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
984 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
985 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
986 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
987 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
988 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
989 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
990 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
991 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
992 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
994 /* Interrupt Counts */
996 if (hw->mac.type >= e1000_82571) {
997 stats->iac += E1000_READ_REG(hw, E1000_IAC);
998 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
999 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1000 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1001 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1002 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1003 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1004 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1005 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1008 if (hw->mac.type >= e1000_82543) {
1009 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1010 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1011 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1012 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1013 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1014 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1017 if (rte_stats == NULL)
1021 rte_stats->imissed = stats->mpc;
1022 rte_stats->ierrors = stats->crcerrs +
1023 stats->rlec + stats->ruc + stats->roc +
1024 stats->rxerrc + stats->algnerrc + stats->cexterr;
1027 rte_stats->oerrors = stats->ecol + stats->latecol;
1029 rte_stats->ipackets = stats->gprc;
1030 rte_stats->opackets = stats->gptc;
1031 rte_stats->ibytes = stats->gorc;
1032 rte_stats->obytes = stats->gotc;
1037 eth_em_stats_reset(struct rte_eth_dev *dev)
1039 struct e1000_hw_stats *hw_stats =
1040 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1042 /* HW registers are cleared on read */
1043 eth_em_stats_get(dev, NULL);
1045 /* Reset software totals */
1046 memset(hw_stats, 0, sizeof(*hw_stats));
1050 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1052 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1056 em_rxq_intr_enable(hw);
1057 rte_intr_enable(intr_handle);
1063 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1065 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1067 em_rxq_intr_disable(hw);
1073 em_get_max_pktlen(const struct e1000_hw *hw)
1075 switch (hw->mac.type) {
1079 case e1000_ich10lan:
1085 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1090 /* Adapters that do not support jumbo frames */
1092 return ETHER_MAX_LEN;
1094 return MAX_JUMBO_FRAME_SIZE;
1099 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1101 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1104 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1105 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1106 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1107 dev_info->rx_offload_capa =
1108 DEV_RX_OFFLOAD_VLAN_STRIP |
1109 DEV_RX_OFFLOAD_IPV4_CKSUM |
1110 DEV_RX_OFFLOAD_UDP_CKSUM |
1111 DEV_RX_OFFLOAD_TCP_CKSUM;
1112 dev_info->tx_offload_capa =
1113 DEV_TX_OFFLOAD_VLAN_INSERT |
1114 DEV_TX_OFFLOAD_IPV4_CKSUM |
1115 DEV_TX_OFFLOAD_UDP_CKSUM |
1116 DEV_TX_OFFLOAD_TCP_CKSUM;
1119 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1120 * Unfortunatelly, all these nics have just one TX context.
1121 * So we have few choises for TX:
1122 * - Use just one TX queue.
1123 * - Allow cksum offload only for one TX queue.
1124 * - Don't allow TX cksum offload at all.
1125 * For now, option #1 was chosen.
1126 * To use second RX queue we have to use extended RX descriptor
1127 * (Multiple Receive Queues are mutually exclusive with UDP
1128 * fragmentation and are not supported when a legacy receive
1129 * descriptor format is used).
1130 * Which means separate RX routinies - as legacy nics (82540, 82545)
1131 * don't support extended RXD.
1132 * To avoid it we support just one RX queue for now (no RSS).
1135 dev_info->max_rx_queues = 1;
1136 dev_info->max_tx_queues = 1;
1138 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1139 .nb_max = E1000_MAX_RING_DESC,
1140 .nb_min = E1000_MIN_RING_DESC,
1141 .nb_align = EM_RXD_ALIGN,
1144 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1145 .nb_max = E1000_MAX_RING_DESC,
1146 .nb_min = E1000_MIN_RING_DESC,
1147 .nb_align = EM_TXD_ALIGN,
1148 .nb_seg_max = EM_TX_MAX_SEG,
1149 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1152 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1153 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1157 /* return 0 means link status changed, -1 means not changed */
1159 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1161 struct e1000_hw *hw =
1162 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1163 struct rte_eth_link link, old;
1164 int link_check, count;
1167 hw->mac.get_link_status = 1;
1169 /* possible wait-to-complete in up to 9 seconds */
1170 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1171 /* Read the real link status */
1172 switch (hw->phy.media_type) {
1173 case e1000_media_type_copper:
1174 /* Do the work to read phy */
1175 e1000_check_for_link(hw);
1176 link_check = !hw->mac.get_link_status;
1179 case e1000_media_type_fiber:
1180 e1000_check_for_link(hw);
1181 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1185 case e1000_media_type_internal_serdes:
1186 e1000_check_for_link(hw);
1187 link_check = hw->mac.serdes_has_link;
1193 if (link_check || wait_to_complete == 0)
1195 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1197 memset(&link, 0, sizeof(link));
1198 rte_em_dev_atomic_read_link_status(dev, &link);
1201 /* Now we check if a transition has happened */
1202 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1203 uint16_t duplex, speed;
1204 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1205 link.link_duplex = (duplex == FULL_DUPLEX) ?
1206 ETH_LINK_FULL_DUPLEX :
1207 ETH_LINK_HALF_DUPLEX;
1208 link.link_speed = speed;
1209 link.link_status = ETH_LINK_UP;
1210 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1211 ETH_LINK_SPEED_FIXED);
1212 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1213 link.link_speed = 0;
1214 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1215 link.link_status = ETH_LINK_DOWN;
1216 link.link_autoneg = ETH_LINK_FIXED;
1218 rte_em_dev_atomic_write_link_status(dev, &link);
1221 if (old.link_status == link.link_status)
1229 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1230 * For ASF and Pass Through versions of f/w this means
1231 * that the driver is loaded. For AMT version type f/w
1232 * this means that the network i/f is open.
1235 em_hw_control_acquire(struct e1000_hw *hw)
1237 uint32_t ctrl_ext, swsm;
1239 /* Let firmware know the driver has taken over */
1240 if (hw->mac.type == e1000_82573) {
1241 swsm = E1000_READ_REG(hw, E1000_SWSM);
1242 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1245 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1246 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1247 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1252 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1253 * For ASF and Pass Through versions of f/w this means that the
1254 * driver is no longer loaded. For AMT versions of the
1255 * f/w this means that the network i/f is closed.
1258 em_hw_control_release(struct e1000_hw *hw)
1260 uint32_t ctrl_ext, swsm;
1262 /* Let firmware taken over control of h/w */
1263 if (hw->mac.type == e1000_82573) {
1264 swsm = E1000_READ_REG(hw, E1000_SWSM);
1265 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1267 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1268 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1269 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1274 * Bit of a misnomer, what this really means is
1275 * to enable OS management of the system... aka
1276 * to disable special hardware management features.
1279 em_init_manageability(struct e1000_hw *hw)
1281 if (e1000_enable_mng_pass_thru(hw)) {
1282 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1283 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1285 /* disable hardware interception of ARP */
1286 manc &= ~(E1000_MANC_ARP_EN);
1288 /* enable receiving management packets to the host */
1289 manc |= E1000_MANC_EN_MNG2HOST;
1290 manc2h |= 1 << 5; /* Mng Port 623 */
1291 manc2h |= 1 << 6; /* Mng Port 664 */
1292 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1293 E1000_WRITE_REG(hw, E1000_MANC, manc);
1298 * Give control back to hardware management
1299 * controller if there is one.
1302 em_release_manageability(struct e1000_hw *hw)
1306 if (e1000_enable_mng_pass_thru(hw)) {
1307 manc = E1000_READ_REG(hw, E1000_MANC);
1309 /* re-enable hardware interception of ARP */
1310 manc |= E1000_MANC_ARP_EN;
1311 manc &= ~E1000_MANC_EN_MNG2HOST;
1313 E1000_WRITE_REG(hw, E1000_MANC, manc);
1318 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1320 struct e1000_hw *hw =
1321 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324 rctl = E1000_READ_REG(hw, E1000_RCTL);
1325 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1326 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1330 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1332 struct e1000_hw *hw =
1333 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1336 rctl = E1000_READ_REG(hw, E1000_RCTL);
1337 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1338 if (dev->data->all_multicast == 1)
1339 rctl |= E1000_RCTL_MPE;
1341 rctl &= (~E1000_RCTL_MPE);
1342 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1346 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1348 struct e1000_hw *hw =
1349 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352 rctl = E1000_READ_REG(hw, E1000_RCTL);
1353 rctl |= E1000_RCTL_MPE;
1354 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1358 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1360 struct e1000_hw *hw =
1361 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364 if (dev->data->promiscuous == 1)
1365 return; /* must remain in all_multicast mode */
1366 rctl = E1000_READ_REG(hw, E1000_RCTL);
1367 rctl &= (~E1000_RCTL_MPE);
1368 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1372 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1374 struct e1000_hw *hw =
1375 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376 struct e1000_vfta * shadow_vfta =
1377 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1382 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1383 E1000_VFTA_ENTRY_MASK);
1384 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1385 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1390 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1392 /* update local VFTA copy */
1393 shadow_vfta->vfta[vid_idx] = vfta;
1399 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1401 struct e1000_hw *hw =
1402 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1405 /* Filter Table Disable */
1406 reg = E1000_READ_REG(hw, E1000_RCTL);
1407 reg &= ~E1000_RCTL_CFIEN;
1408 reg &= ~E1000_RCTL_VFE;
1409 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1413 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1415 struct e1000_hw *hw =
1416 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 struct e1000_vfta * shadow_vfta =
1418 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1422 /* Filter Table Enable, CFI not used for packet acceptance */
1423 reg = E1000_READ_REG(hw, E1000_RCTL);
1424 reg &= ~E1000_RCTL_CFIEN;
1425 reg |= E1000_RCTL_VFE;
1426 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1428 /* restore vfta from local copy */
1429 for (i = 0; i < IGB_VFTA_SIZE; i++)
1430 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1434 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1436 struct e1000_hw *hw =
1437 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1440 /* VLAN Mode Disable */
1441 reg = E1000_READ_REG(hw, E1000_CTRL);
1442 reg &= ~E1000_CTRL_VME;
1443 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1448 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1450 struct e1000_hw *hw =
1451 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454 /* VLAN Mode Enable */
1455 reg = E1000_READ_REG(hw, E1000_CTRL);
1456 reg |= E1000_CTRL_VME;
1457 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1461 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1463 if(mask & ETH_VLAN_STRIP_MASK){
1464 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1465 em_vlan_hw_strip_enable(dev);
1467 em_vlan_hw_strip_disable(dev);
1470 if(mask & ETH_VLAN_FILTER_MASK){
1471 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1472 em_vlan_hw_filter_enable(dev);
1474 em_vlan_hw_filter_disable(dev);
1481 * It enables the interrupt mask and then enable the interrupt.
1484 * Pointer to struct rte_eth_dev.
1487 * - On success, zero.
1488 * - On failure, a negative value.
1491 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1494 struct e1000_hw *hw =
1495 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1497 /* clear interrupt */
1498 E1000_READ_REG(hw, E1000_ICR);
1499 regval = E1000_READ_REG(hw, E1000_IMS);
1500 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1505 * It clears the interrupt causes and enables the interrupt.
1506 * It will be called once only during nic initialized.
1509 * Pointer to struct rte_eth_dev.
1512 * - On success, zero.
1513 * - On failure, a negative value.
1516 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1518 struct e1000_hw *hw =
1519 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521 E1000_READ_REG(hw, E1000_ICR);
1522 em_rxq_intr_enable(hw);
1527 * It enable receive packet interrupt.
1529 * Pointer to struct e1000_hw
1534 em_rxq_intr_enable(struct e1000_hw *hw)
1536 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1537 E1000_WRITE_FLUSH(hw);
1541 * It disabled lsc interrupt.
1543 * Pointer to struct e1000_hw
1548 em_lsc_intr_disable(struct e1000_hw *hw)
1550 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1551 E1000_WRITE_FLUSH(hw);
1555 * It disabled receive packet interrupt.
1557 * Pointer to struct e1000_hw
1562 em_rxq_intr_disable(struct e1000_hw *hw)
1564 E1000_READ_REG(hw, E1000_ICR);
1565 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1566 E1000_WRITE_FLUSH(hw);
1570 * It reads ICR and gets interrupt causes, check it and set a bit flag
1571 * to update link status.
1574 * Pointer to struct rte_eth_dev.
1577 * - On success, zero.
1578 * - On failure, a negative value.
1581 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1584 struct e1000_hw *hw =
1585 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586 struct e1000_interrupt *intr =
1587 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1589 /* read-on-clear nic registers here */
1590 icr = E1000_READ_REG(hw, E1000_ICR);
1591 if (icr & E1000_ICR_LSC) {
1592 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1599 * It executes link_update after knowing an interrupt is prsent.
1602 * Pointer to struct rte_eth_dev.
1605 * - On success, zero.
1606 * - On failure, a negative value.
1609 eth_em_interrupt_action(struct rte_eth_dev *dev,
1610 struct rte_intr_handle *intr_handle)
1612 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1613 struct e1000_hw *hw =
1614 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615 struct e1000_interrupt *intr =
1616 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1617 struct rte_eth_link link;
1620 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1623 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1624 rte_intr_enable(intr_handle);
1626 /* set get_link_status to check register later */
1627 hw->mac.get_link_status = 1;
1628 ret = eth_em_link_update(dev, 0);
1630 /* check if link has changed */
1634 memset(&link, 0, sizeof(link));
1635 rte_em_dev_atomic_read_link_status(dev, &link);
1636 if (link.link_status) {
1637 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1638 dev->data->port_id, link.link_speed,
1639 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1640 "full-duplex" : "half-duplex");
1642 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1644 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1645 pci_dev->addr.domain, pci_dev->addr.bus,
1646 pci_dev->addr.devid, pci_dev->addr.function);
1652 * Interrupt handler which shall be registered at first.
1655 * Pointer to interrupt handle.
1657 * The address of parameter (struct rte_eth_dev *) regsitered before.
1663 eth_em_interrupt_handler(void *param)
1665 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1667 eth_em_interrupt_get_status(dev);
1668 eth_em_interrupt_action(dev, dev->intr_handle);
1669 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1673 eth_em_led_on(struct rte_eth_dev *dev)
1675 struct e1000_hw *hw;
1677 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1682 eth_em_led_off(struct rte_eth_dev *dev)
1684 struct e1000_hw *hw;
1686 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1691 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1693 struct e1000_hw *hw;
1698 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699 fc_conf->pause_time = hw->fc.pause_time;
1700 fc_conf->high_water = hw->fc.high_water;
1701 fc_conf->low_water = hw->fc.low_water;
1702 fc_conf->send_xon = hw->fc.send_xon;
1703 fc_conf->autoneg = hw->mac.autoneg;
1706 * Return rx_pause and tx_pause status according to actual setting of
1707 * the TFCE and RFCE bits in the CTRL register.
1709 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1710 if (ctrl & E1000_CTRL_TFCE)
1715 if (ctrl & E1000_CTRL_RFCE)
1720 if (rx_pause && tx_pause)
1721 fc_conf->mode = RTE_FC_FULL;
1723 fc_conf->mode = RTE_FC_RX_PAUSE;
1725 fc_conf->mode = RTE_FC_TX_PAUSE;
1727 fc_conf->mode = RTE_FC_NONE;
1733 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1735 struct e1000_hw *hw;
1737 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1743 uint32_t rx_buf_size;
1744 uint32_t max_high_water;
1747 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748 if (fc_conf->autoneg != hw->mac.autoneg)
1750 rx_buf_size = em_get_rx_buffer_size(hw);
1751 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1753 /* At least reserve one Ethernet frame for watermark */
1754 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1755 if ((fc_conf->high_water > max_high_water) ||
1756 (fc_conf->high_water < fc_conf->low_water)) {
1757 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1758 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1762 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1763 hw->fc.pause_time = fc_conf->pause_time;
1764 hw->fc.high_water = fc_conf->high_water;
1765 hw->fc.low_water = fc_conf->low_water;
1766 hw->fc.send_xon = fc_conf->send_xon;
1768 err = e1000_setup_link_generic(hw);
1769 if (err == E1000_SUCCESS) {
1771 /* check if we want to forward MAC frames - driver doesn't have native
1772 * capability to do that, so we'll write the registers ourselves */
1774 rctl = E1000_READ_REG(hw, E1000_RCTL);
1776 /* set or clear MFLCN.PMCF bit depending on configuration */
1777 if (fc_conf->mac_ctrl_frame_fwd != 0)
1778 rctl |= E1000_RCTL_PMCF;
1780 rctl &= ~E1000_RCTL_PMCF;
1782 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1783 E1000_WRITE_FLUSH(hw);
1788 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1793 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1794 uint32_t index, __rte_unused uint32_t pool)
1796 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798 return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1802 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1804 uint8_t addr[ETHER_ADDR_LEN];
1805 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807 memset(addr, 0, sizeof(addr));
1809 e1000_rar_set(hw, addr, index);
1813 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1815 struct rte_eth_dev_info dev_info;
1816 struct e1000_hw *hw;
1817 uint32_t frame_size;
1820 eth_em_infos_get(dev, &dev_info);
1821 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1823 /* check that mtu is within the allowed range */
1824 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1827 /* refuse mtu that requires the support of scattered packets when this
1828 * feature has not been enabled before. */
1829 if (!dev->data->scattered_rx &&
1830 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1833 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834 rctl = E1000_READ_REG(hw, E1000_RCTL);
1836 /* switch to jumbo mode if needed */
1837 if (frame_size > ETHER_MAX_LEN) {
1838 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1839 rctl |= E1000_RCTL_LPE;
1841 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1842 rctl &= ~E1000_RCTL_LPE;
1844 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1846 /* update max frame size */
1847 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1852 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1853 struct ether_addr *mc_addr_set,
1854 uint32_t nb_mc_addr)
1856 struct e1000_hw *hw;
1858 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1863 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1864 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1865 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1867 RTE_INIT(e1000_init_log);
1869 e1000_init_log(void)
1871 e1000_logtype_init = rte_log_register("pmd.e1000.init");
1872 if (e1000_logtype_init >= 0)
1873 rte_log_set_level(e1000_logtype_init, RTE_LOG_NOTICE);
1874 e1000_logtype_driver = rte_log_register("pmd.e1000.driver");
1875 if (e1000_logtype_driver >= 0)
1876 rte_log_set_level(e1000_logtype_driver, RTE_LOG_NOTICE);