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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
59 #define EM_EIAC 0x000DC
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
90 static int em_hw_init(struct e1000_hw *hw);
91 static int em_hardware_init(struct e1000_hw *hw);
92 static void em_hw_control_acquire(struct e1000_hw *hw);
93 static void em_hw_control_release(struct e1000_hw *hw);
94 static void em_init_manageability(struct e1000_hw *hw);
95 static void em_release_manageability(struct e1000_hw *hw);
97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
100 uint16_t vlan_id, int on);
101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
109 uint16_t vlan_id, int on);
112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static void em_lsc_intr_disable(struct e1000_hw *hw);
115 static void em_rxq_intr_enable(struct e1000_hw *hw);
116 static void em_rxq_intr_disable(struct e1000_hw *hw);
118 static int eth_em_led_on(struct rte_eth_dev *dev);
119 static int eth_em_led_off(struct rte_eth_dev *dev);
121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
123 uint32_t index, uint32_t pool);
124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
127 struct ether_addr *mc_addr_set,
128 uint32_t nb_mc_addr);
130 #define EM_FC_PAUSE_TIME 0x0680
131 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
137 * The set of PCI devices this driver supports
139 static const struct rte_pci_id pci_id_em_map[] = {
141 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
142 #include "rte_pci_dev_ids.h"
147 static const struct eth_dev_ops eth_em_ops = {
148 .dev_configure = eth_em_configure,
149 .dev_start = eth_em_start,
150 .dev_stop = eth_em_stop,
151 .dev_close = eth_em_close,
152 .promiscuous_enable = eth_em_promiscuous_enable,
153 .promiscuous_disable = eth_em_promiscuous_disable,
154 .allmulticast_enable = eth_em_allmulticast_enable,
155 .allmulticast_disable = eth_em_allmulticast_disable,
156 .link_update = eth_em_link_update,
157 .stats_get = eth_em_stats_get,
158 .stats_reset = eth_em_stats_reset,
159 .dev_infos_get = eth_em_infos_get,
160 .mtu_set = eth_em_mtu_set,
161 .vlan_filter_set = eth_em_vlan_filter_set,
162 .vlan_offload_set = eth_em_vlan_offload_set,
163 .rx_queue_setup = eth_em_rx_queue_setup,
164 .rx_queue_release = eth_em_rx_queue_release,
165 .rx_queue_count = eth_em_rx_queue_count,
166 .rx_descriptor_done = eth_em_rx_descriptor_done,
167 .tx_queue_setup = eth_em_tx_queue_setup,
168 .tx_queue_release = eth_em_tx_queue_release,
169 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
170 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
171 .dev_led_on = eth_em_led_on,
172 .dev_led_off = eth_em_led_off,
173 .flow_ctrl_get = eth_em_flow_ctrl_get,
174 .flow_ctrl_set = eth_em_flow_ctrl_set,
175 .mac_addr_add = eth_em_rar_set,
176 .mac_addr_remove = eth_em_rar_clear,
177 .set_mc_addr_list = eth_em_set_mc_addr_list,
181 * Atomically reads the link status information from global
182 * structure rte_eth_dev.
185 * - Pointer to the structure rte_eth_dev to read from.
186 * - Pointer to the buffer to be saved with the link status.
189 * - On success, zero.
190 * - On failure, negative value.
193 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
194 struct rte_eth_link *link)
196 struct rte_eth_link *dst = link;
197 struct rte_eth_link *src = &(dev->data->dev_link);
199 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
200 *(uint64_t *)src) == 0)
207 * Atomically writes the link status information into global
208 * structure rte_eth_dev.
211 * - Pointer to the structure rte_eth_dev to read from.
212 * - Pointer to the buffer to be saved with the link status.
215 * - On success, zero.
216 * - On failure, negative value.
219 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
220 struct rte_eth_link *link)
222 struct rte_eth_link *dst = &(dev->data->dev_link);
223 struct rte_eth_link *src = link;
225 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
226 *(uint64_t *)src) == 0)
233 eth_em_dev_init(struct rte_eth_dev *eth_dev)
235 struct rte_pci_device *pci_dev;
236 struct e1000_adapter *adapter =
237 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
238 struct e1000_hw *hw =
239 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
240 struct e1000_vfta * shadow_vfta =
241 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
243 pci_dev = eth_dev->pci_dev;
244 eth_dev->dev_ops = ð_em_ops;
245 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
246 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
248 /* for secondary processes, we don't initialise any further as primary
249 * has already done this work. Only check we don't need a different
251 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
252 if (eth_dev->data->scattered_rx)
253 eth_dev->rx_pkt_burst =
254 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
258 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
259 hw->device_id = pci_dev->id.device_id;
260 adapter->stopped = 0;
262 /* For ICH8 support we'll need to map the flash memory BAR */
264 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
265 em_hw_init(hw) != 0) {
266 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
268 eth_dev->data->port_id, pci_dev->id.vendor_id,
269 pci_dev->id.device_id);
273 /* Allocate memory for storing MAC addresses */
274 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
275 hw->mac.rar_entry_count, 0);
276 if (eth_dev->data->mac_addrs == NULL) {
277 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
278 "store MAC addresses",
279 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
283 /* Copy the permanent MAC address */
284 ether_addr_copy((struct ether_addr *) hw->mac.addr,
285 eth_dev->data->mac_addrs);
287 /* initialize the vfta */
288 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
290 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
291 eth_dev->data->port_id, pci_dev->id.vendor_id,
292 pci_dev->id.device_id);
294 rte_intr_callback_register(&(pci_dev->intr_handle),
295 eth_em_interrupt_handler, (void *)eth_dev);
301 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
303 struct rte_pci_device *pci_dev;
304 struct e1000_adapter *adapter =
305 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
307 PMD_INIT_FUNC_TRACE();
309 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
312 pci_dev = eth_dev->pci_dev;
314 if (adapter->stopped == 0)
315 eth_em_close(eth_dev);
317 eth_dev->dev_ops = NULL;
318 eth_dev->rx_pkt_burst = NULL;
319 eth_dev->tx_pkt_burst = NULL;
321 rte_free(eth_dev->data->mac_addrs);
322 eth_dev->data->mac_addrs = NULL;
324 /* disable uio intr before callback unregister */
325 rte_intr_disable(&(pci_dev->intr_handle));
326 rte_intr_callback_unregister(&(pci_dev->intr_handle),
327 eth_em_interrupt_handler, (void *)eth_dev);
332 static struct eth_driver rte_em_pmd = {
334 .name = "rte_em_pmd",
335 .id_table = pci_id_em_map,
336 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
337 RTE_PCI_DRV_DETACHABLE,
339 .eth_dev_init = eth_em_dev_init,
340 .eth_dev_uninit = eth_em_dev_uninit,
341 .dev_private_size = sizeof(struct e1000_adapter),
345 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
347 rte_eth_driver_register(&rte_em_pmd);
352 em_hw_init(struct e1000_hw *hw)
356 diag = hw->mac.ops.init_params(hw);
358 PMD_INIT_LOG(ERR, "MAC Initialization Error");
361 diag = hw->nvm.ops.init_params(hw);
363 PMD_INIT_LOG(ERR, "NVM Initialization Error");
366 diag = hw->phy.ops.init_params(hw);
368 PMD_INIT_LOG(ERR, "PHY Initialization Error");
371 (void) e1000_get_bus_info(hw);
374 hw->phy.autoneg_wait_to_complete = 0;
375 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
377 e1000_init_script_state_82541(hw, TRUE);
378 e1000_set_tbi_compatibility_82543(hw, TRUE);
381 if (hw->phy.media_type == e1000_media_type_copper) {
382 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
383 hw->phy.disable_polarity_correction = 0;
384 hw->phy.ms_type = e1000_ms_hw_default;
388 * Start from a known state, this is important in reading the nvm
393 /* Make sure we have a good EEPROM before we read from it */
394 if (e1000_validate_nvm_checksum(hw) < 0) {
396 * Some PCI-E parts fail the first check due to
397 * the link being in sleep state, call it again,
398 * if it fails a second time its a real issue.
400 diag = e1000_validate_nvm_checksum(hw);
402 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
407 /* Read the permanent MAC address out of the EEPROM */
408 diag = e1000_read_mac_addr(hw);
410 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
414 /* Now initialize the hardware */
415 diag = em_hardware_init(hw);
417 PMD_INIT_LOG(ERR, "Hardware initialization failed");
421 hw->mac.get_link_status = 1;
423 /* Indicate SOL/IDER usage */
424 diag = e1000_check_reset_block(hw);
426 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
432 em_hw_control_release(hw);
437 eth_em_configure(struct rte_eth_dev *dev)
439 struct e1000_interrupt *intr =
440 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
442 PMD_INIT_FUNC_TRACE();
443 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
444 PMD_INIT_FUNC_TRACE();
450 em_set_pba(struct e1000_hw *hw)
455 * Packet Buffer Allocation (PBA)
456 * Writing PBA sets the receive portion of the buffer
457 * the remainder is used for the transmit buffer.
458 * Devices before the 82547 had a Packet Buffer of 64K.
459 * After the 82547 the buffer was reduced to 40K.
461 switch (hw->mac.type) {
463 case e1000_82547_rev_2:
464 /* 82547: Total Packet Buffer is 40K */
465 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
469 case e1000_80003es2lan:
470 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
472 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
473 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
477 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
491 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
494 E1000_WRITE_REG(hw, E1000_PBA, pba);
498 eth_em_start(struct rte_eth_dev *dev)
500 struct e1000_adapter *adapter =
501 E1000_DEV_PRIVATE(dev->data->dev_private);
502 struct e1000_hw *hw =
503 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
504 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
506 uint32_t intr_vector = 0;
508 PMD_INIT_FUNC_TRACE();
512 e1000_power_up_phy(hw);
514 /* Set default PBA value */
517 /* Put the address into the Receive Address Array */
518 e1000_rar_set(hw, hw->mac.addr, 0);
521 * With the 82571 adapter, RAR[0] may be overwritten
522 * when the other port is reset, we make a duplicate
523 * in RAR[14] for that eventuality, this assures
524 * the interface continues to function.
526 if (hw->mac.type == e1000_82571) {
527 e1000_set_laa_state_82571(hw, TRUE);
528 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
531 /* Initialize the hardware */
532 if (em_hardware_init(hw)) {
533 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
537 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
539 /* Configure for OS presence */
540 em_init_manageability(hw);
542 if (dev->data->dev_conf.intr_conf.rxq != 0) {
543 intr_vector = dev->data->nb_rx_queues;
544 if (rte_intr_efd_enable(intr_handle, intr_vector))
548 if (rte_intr_dp_is_en(intr_handle)) {
549 intr_handle->intr_vec =
550 rte_zmalloc("intr_vec",
551 dev->data->nb_rx_queues * sizeof(int), 0);
552 if (intr_handle->intr_vec == NULL) {
553 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
554 " intr_vec\n", dev->data->nb_rx_queues);
558 /* enable rx interrupt */
559 em_rxq_intr_enable(hw);
564 ret = eth_em_rx_init(dev);
566 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
567 em_dev_clear_queues(dev);
571 e1000_clear_hw_cntrs_base_generic(hw);
573 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
574 ETH_VLAN_EXTEND_MASK;
575 eth_em_vlan_offload_set(dev, mask);
577 /* Set Interrupt Throttling Rate to maximum allowed value. */
578 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
580 /* Setup link speed and duplex */
581 switch (dev->data->dev_conf.link_speed) {
582 case ETH_LINK_SPEED_AUTONEG:
583 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
584 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
585 else if (dev->data->dev_conf.link_duplex ==
586 ETH_LINK_HALF_DUPLEX)
587 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
588 else if (dev->data->dev_conf.link_duplex ==
589 ETH_LINK_FULL_DUPLEX)
590 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
592 goto error_invalid_config;
594 case ETH_LINK_SPEED_10:
595 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
596 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
597 else if (dev->data->dev_conf.link_duplex ==
598 ETH_LINK_HALF_DUPLEX)
599 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
600 else if (dev->data->dev_conf.link_duplex ==
601 ETH_LINK_FULL_DUPLEX)
602 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
604 goto error_invalid_config;
606 case ETH_LINK_SPEED_100:
607 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
608 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
609 else if (dev->data->dev_conf.link_duplex ==
610 ETH_LINK_HALF_DUPLEX)
611 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
612 else if (dev->data->dev_conf.link_duplex ==
613 ETH_LINK_FULL_DUPLEX)
614 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
616 goto error_invalid_config;
618 case ETH_LINK_SPEED_1000:
619 if ((dev->data->dev_conf.link_duplex ==
620 ETH_LINK_AUTONEG_DUPLEX) ||
621 (dev->data->dev_conf.link_duplex ==
622 ETH_LINK_FULL_DUPLEX))
623 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
625 goto error_invalid_config;
627 case ETH_LINK_SPEED_10000:
629 goto error_invalid_config;
631 e1000_setup_link(hw);
633 if (rte_intr_allow_others(intr_handle)) {
634 /* check if lsc interrupt is enabled */
635 if (dev->data->dev_conf.intr_conf.lsc != 0)
636 ret = eth_em_interrupt_setup(dev);
638 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
639 em_dev_clear_queues(dev);
643 rte_intr_callback_unregister(intr_handle,
644 eth_em_interrupt_handler,
646 if (dev->data->dev_conf.intr_conf.lsc != 0)
647 PMD_INIT_LOG(INFO, "lsc won't enable because of"
648 " no intr multiplex\n");
650 /* check if rxq interrupt is enabled */
651 if (dev->data->dev_conf.intr_conf.rxq != 0)
652 eth_em_rxq_interrupt_setup(dev);
654 rte_intr_enable(intr_handle);
656 adapter->stopped = 0;
658 PMD_INIT_LOG(DEBUG, "<<");
662 error_invalid_config:
663 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
664 dev->data->dev_conf.link_speed,
665 dev->data->dev_conf.link_duplex, dev->data->port_id);
666 em_dev_clear_queues(dev);
670 /*********************************************************************
672 * This routine disables all traffic on the adapter by issuing a
673 * global reset on the MAC.
675 **********************************************************************/
677 eth_em_stop(struct rte_eth_dev *dev)
679 struct rte_eth_link link;
680 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
681 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
683 em_rxq_intr_disable(hw);
684 em_lsc_intr_disable(hw);
687 if (hw->mac.type >= e1000_82544)
688 E1000_WRITE_REG(hw, E1000_WUC, 0);
690 /* Power down the phy. Needed to make the link go down */
691 e1000_power_down_phy(hw);
693 em_dev_clear_queues(dev);
695 /* clear the recorded link status */
696 memset(&link, 0, sizeof(link));
697 rte_em_dev_atomic_write_link_status(dev, &link);
699 if (!rte_intr_allow_others(intr_handle))
700 /* resume to the default handler */
701 rte_intr_callback_register(intr_handle,
702 eth_em_interrupt_handler,
705 /* Clean datapath event and queue/vec mapping */
706 rte_intr_efd_disable(intr_handle);
707 if (intr_handle->intr_vec != NULL) {
708 rte_free(intr_handle->intr_vec);
709 intr_handle->intr_vec = NULL;
714 eth_em_close(struct rte_eth_dev *dev)
716 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
717 struct e1000_adapter *adapter =
718 E1000_DEV_PRIVATE(dev->data->dev_private);
721 adapter->stopped = 1;
722 em_dev_free_queues(dev);
723 e1000_phy_hw_reset(hw);
724 em_release_manageability(hw);
725 em_hw_control_release(hw);
729 em_get_rx_buffer_size(struct e1000_hw *hw)
731 uint32_t rx_buf_size;
733 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
737 /*********************************************************************
739 * Initialize the hardware
741 **********************************************************************/
743 em_hardware_init(struct e1000_hw *hw)
745 uint32_t rx_buf_size;
748 /* Issue a global reset */
751 /* Let the firmware know the OS is in control */
752 em_hw_control_acquire(hw);
755 * These parameters control the automatic generation (Tx) and
756 * response (Rx) to Ethernet PAUSE frames.
757 * - High water mark should allow for at least two standard size (1518)
758 * frames to be received after sending an XOFF.
759 * - Low water mark works best when it is very near the high water mark.
760 * This allows the receiver to restart by sending XON when it has
761 * drained a bit. Here we use an arbitrary value of 1500 which will
762 * restart after one full frame is pulled from the buffer. There
763 * could be several smaller frames in the buffer and if so they will
764 * not trigger the XON until their total number reduces the buffer
766 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
768 rx_buf_size = em_get_rx_buffer_size(hw);
770 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
771 hw->fc.low_water = hw->fc.high_water - 1500;
773 if (hw->mac.type == e1000_80003es2lan)
774 hw->fc.pause_time = UINT16_MAX;
776 hw->fc.pause_time = EM_FC_PAUSE_TIME;
780 /* Set Flow control, use the tunable location if sane */
781 if (em_fc_setting <= e1000_fc_full)
782 hw->fc.requested_mode = em_fc_setting;
784 hw->fc.requested_mode = e1000_fc_none;
786 /* Workaround: no TX flow ctrl for PCH */
787 if (hw->mac.type == e1000_pchlan)
788 hw->fc.requested_mode = e1000_fc_rx_pause;
790 /* Override - settings for PCH2LAN, ya its magic :) */
791 if (hw->mac.type == e1000_pch2lan) {
792 hw->fc.high_water = 0x5C20;
793 hw->fc.low_water = 0x5048;
794 hw->fc.pause_time = 0x0650;
795 hw->fc.refresh_time = 0x0400;
798 diag = e1000_init_hw(hw);
801 e1000_check_for_link(hw);
805 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
807 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
809 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
810 struct e1000_hw_stats *stats =
811 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
814 if(hw->phy.media_type == e1000_media_type_copper ||
815 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
816 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
817 stats->sec += E1000_READ_REG(hw, E1000_SEC);
820 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
821 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
822 stats->scc += E1000_READ_REG(hw, E1000_SCC);
823 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
825 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
826 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
827 stats->colc += E1000_READ_REG(hw, E1000_COLC);
828 stats->dc += E1000_READ_REG(hw, E1000_DC);
829 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
830 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
831 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
834 * For watchdog management we need to know if we have been
835 * paused during the last interval, so capture that here.
837 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
838 stats->xoffrxc += pause_frames;
839 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
840 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
841 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
842 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
843 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
844 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
845 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
846 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
847 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
848 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
849 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
850 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
853 * For the 64-bit byte counters the low dword must be read first.
854 * Both registers clear on the read of the high dword.
857 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
858 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
859 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
860 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
862 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
863 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
864 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
865 stats->roc += E1000_READ_REG(hw, E1000_ROC);
866 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
868 stats->tor += E1000_READ_REG(hw, E1000_TORH);
869 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
871 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
872 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
873 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
874 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
875 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
876 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
877 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
878 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
879 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
880 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
882 /* Interrupt Counts */
884 if (hw->mac.type >= e1000_82571) {
885 stats->iac += E1000_READ_REG(hw, E1000_IAC);
886 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
887 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
888 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
889 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
890 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
891 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
892 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
893 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
896 if (hw->mac.type >= e1000_82543) {
897 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
898 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
899 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
900 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
901 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
902 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
905 if (rte_stats == NULL)
909 rte_stats->ibadcrc = stats->crcerrs;
910 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
911 rte_stats->imissed = stats->mpc;
912 rte_stats->ierrors = rte_stats->ibadcrc +
915 stats->rxerrc + stats->algnerrc + stats->cexterr;
918 rte_stats->oerrors = stats->ecol + stats->latecol;
920 rte_stats->ipackets = stats->gprc;
921 rte_stats->opackets = stats->gptc;
922 rte_stats->ibytes = stats->gorc;
923 rte_stats->obytes = stats->gotc;
925 /* XON/XOFF pause frames stats registers */
926 rte_stats->tx_pause_xon = stats->xontxc;
927 rte_stats->rx_pause_xon = stats->xonrxc;
928 rte_stats->tx_pause_xoff = stats->xofftxc;
929 rte_stats->rx_pause_xoff = stats->xoffrxc;
933 eth_em_stats_reset(struct rte_eth_dev *dev)
935 struct e1000_hw_stats *hw_stats =
936 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
938 /* HW registers are cleared on read */
939 eth_em_stats_get(dev, NULL);
941 /* Reset software totals */
942 memset(hw_stats, 0, sizeof(*hw_stats));
946 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
948 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
950 em_rxq_intr_enable(hw);
951 rte_intr_enable(&dev->pci_dev->intr_handle);
957 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
959 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
961 em_rxq_intr_disable(hw);
967 em_get_max_pktlen(const struct e1000_hw *hw)
969 switch (hw->mac.type) {
976 case e1000_80003es2lan: /* 9K Jumbo Frame size */
981 /* Adapters that do not support jumbo frames */
983 return (ETHER_MAX_LEN);
985 return (MAX_JUMBO_FRAME_SIZE);
990 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
992 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
994 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
995 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
996 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
999 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1000 * Unfortunatelly, all these nics have just one TX context.
1001 * So we have few choises for TX:
1002 * - Use just one TX queue.
1003 * - Allow cksum offload only for one TX queue.
1004 * - Don't allow TX cksum offload at all.
1005 * For now, option #1 was chosen.
1006 * To use second RX queue we have to use extended RX descriptor
1007 * (Multiple Receive Queues are mutually exclusive with UDP
1008 * fragmentation and are not supported when a legacy receive
1009 * descriptor format is used).
1010 * Which means separate RX routinies - as legacy nics (82540, 82545)
1011 * don't support extended RXD.
1012 * To avoid it we support just one RX queue for now (no RSS).
1015 dev_info->max_rx_queues = 1;
1016 dev_info->max_tx_queues = 1;
1019 /* return 0 means link status changed, -1 means not changed */
1021 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1023 struct e1000_hw *hw =
1024 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1025 struct rte_eth_link link, old;
1026 int link_check, count;
1029 hw->mac.get_link_status = 1;
1031 /* possible wait-to-complete in up to 9 seconds */
1032 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1033 /* Read the real link status */
1034 switch (hw->phy.media_type) {
1035 case e1000_media_type_copper:
1036 /* Do the work to read phy */
1037 e1000_check_for_link(hw);
1038 link_check = !hw->mac.get_link_status;
1041 case e1000_media_type_fiber:
1042 e1000_check_for_link(hw);
1043 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1047 case e1000_media_type_internal_serdes:
1048 e1000_check_for_link(hw);
1049 link_check = hw->mac.serdes_has_link;
1055 if (link_check || wait_to_complete == 0)
1057 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1059 memset(&link, 0, sizeof(link));
1060 rte_em_dev_atomic_read_link_status(dev, &link);
1063 /* Now we check if a transition has happened */
1064 if (link_check && (link.link_status == 0)) {
1065 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1067 link.link_status = 1;
1068 } else if (!link_check && (link.link_status == 1)) {
1069 link.link_speed = 0;
1070 link.link_duplex = 0;
1071 link.link_status = 0;
1073 rte_em_dev_atomic_write_link_status(dev, &link);
1076 if (old.link_status == link.link_status)
1084 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1085 * For ASF and Pass Through versions of f/w this means
1086 * that the driver is loaded. For AMT version type f/w
1087 * this means that the network i/f is open.
1090 em_hw_control_acquire(struct e1000_hw *hw)
1092 uint32_t ctrl_ext, swsm;
1094 /* Let firmware know the driver has taken over */
1095 if (hw->mac.type == e1000_82573) {
1096 swsm = E1000_READ_REG(hw, E1000_SWSM);
1097 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1100 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1101 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1102 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1107 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1108 * For ASF and Pass Through versions of f/w this means that the
1109 * driver is no longer loaded. For AMT versions of the
1110 * f/w this means that the network i/f is closed.
1113 em_hw_control_release(struct e1000_hw *hw)
1115 uint32_t ctrl_ext, swsm;
1117 /* Let firmware taken over control of h/w */
1118 if (hw->mac.type == e1000_82573) {
1119 swsm = E1000_READ_REG(hw, E1000_SWSM);
1120 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1122 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1123 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1124 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1129 * Bit of a misnomer, what this really means is
1130 * to enable OS management of the system... aka
1131 * to disable special hardware management features.
1134 em_init_manageability(struct e1000_hw *hw)
1136 if (e1000_enable_mng_pass_thru(hw)) {
1137 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1138 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1140 /* disable hardware interception of ARP */
1141 manc &= ~(E1000_MANC_ARP_EN);
1143 /* enable receiving management packets to the host */
1144 manc |= E1000_MANC_EN_MNG2HOST;
1145 manc2h |= 1 << 5; /* Mng Port 623 */
1146 manc2h |= 1 << 6; /* Mng Port 664 */
1147 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1148 E1000_WRITE_REG(hw, E1000_MANC, manc);
1153 * Give control back to hardware management
1154 * controller if there is one.
1157 em_release_manageability(struct e1000_hw *hw)
1161 if (e1000_enable_mng_pass_thru(hw)) {
1162 manc = E1000_READ_REG(hw, E1000_MANC);
1164 /* re-enable hardware interception of ARP */
1165 manc |= E1000_MANC_ARP_EN;
1166 manc &= ~E1000_MANC_EN_MNG2HOST;
1168 E1000_WRITE_REG(hw, E1000_MANC, manc);
1173 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1175 struct e1000_hw *hw =
1176 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1179 rctl = E1000_READ_REG(hw, E1000_RCTL);
1180 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1181 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1185 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1187 struct e1000_hw *hw =
1188 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191 rctl = E1000_READ_REG(hw, E1000_RCTL);
1192 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1193 if (dev->data->all_multicast == 1)
1194 rctl |= E1000_RCTL_MPE;
1196 rctl &= (~E1000_RCTL_MPE);
1197 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1201 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1203 struct e1000_hw *hw =
1204 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207 rctl = E1000_READ_REG(hw, E1000_RCTL);
1208 rctl |= E1000_RCTL_MPE;
1209 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1213 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1215 struct e1000_hw *hw =
1216 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1219 if (dev->data->promiscuous == 1)
1220 return; /* must remain in all_multicast mode */
1221 rctl = E1000_READ_REG(hw, E1000_RCTL);
1222 rctl &= (~E1000_RCTL_MPE);
1223 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1227 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1229 struct e1000_hw *hw =
1230 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231 struct e1000_vfta * shadow_vfta =
1232 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1237 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1238 E1000_VFTA_ENTRY_MASK);
1239 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1240 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1245 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1247 /* update local VFTA copy */
1248 shadow_vfta->vfta[vid_idx] = vfta;
1254 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1256 struct e1000_hw *hw =
1257 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260 /* Filter Table Disable */
1261 reg = E1000_READ_REG(hw, E1000_RCTL);
1262 reg &= ~E1000_RCTL_CFIEN;
1263 reg &= ~E1000_RCTL_VFE;
1264 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1268 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1270 struct e1000_hw *hw =
1271 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1272 struct e1000_vfta * shadow_vfta =
1273 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1277 /* Filter Table Enable, CFI not used for packet acceptance */
1278 reg = E1000_READ_REG(hw, E1000_RCTL);
1279 reg &= ~E1000_RCTL_CFIEN;
1280 reg |= E1000_RCTL_VFE;
1281 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1283 /* restore vfta from local copy */
1284 for (i = 0; i < IGB_VFTA_SIZE; i++)
1285 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1289 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1291 struct e1000_hw *hw =
1292 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1295 /* VLAN Mode Disable */
1296 reg = E1000_READ_REG(hw, E1000_CTRL);
1297 reg &= ~E1000_CTRL_VME;
1298 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1303 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1305 struct e1000_hw *hw =
1306 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309 /* VLAN Mode Enable */
1310 reg = E1000_READ_REG(hw, E1000_CTRL);
1311 reg |= E1000_CTRL_VME;
1312 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1316 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1318 if(mask & ETH_VLAN_STRIP_MASK){
1319 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1320 em_vlan_hw_strip_enable(dev);
1322 em_vlan_hw_strip_disable(dev);
1325 if(mask & ETH_VLAN_FILTER_MASK){
1326 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1327 em_vlan_hw_filter_enable(dev);
1329 em_vlan_hw_filter_disable(dev);
1334 * It enables the interrupt mask and then enable the interrupt.
1337 * Pointer to struct rte_eth_dev.
1340 * - On success, zero.
1341 * - On failure, a negative value.
1344 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1347 struct e1000_hw *hw =
1348 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1350 /* clear interrupt */
1351 E1000_READ_REG(hw, E1000_ICR);
1352 regval = E1000_READ_REG(hw, E1000_IMS);
1353 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1358 * It clears the interrupt causes and enables the interrupt.
1359 * It will be called once only during nic initialized.
1362 * Pointer to struct rte_eth_dev.
1365 * - On success, zero.
1366 * - On failure, a negative value.
1369 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1371 struct e1000_hw *hw =
1372 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1374 E1000_READ_REG(hw, E1000_ICR);
1375 em_rxq_intr_enable(hw);
1380 * It enable receive packet interrupt.
1382 * Pointer to struct e1000_hw
1387 em_rxq_intr_enable(struct e1000_hw *hw)
1389 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1390 E1000_WRITE_FLUSH(hw);
1394 * It disabled lsc interrupt.
1396 * Pointer to struct e1000_hw
1401 em_lsc_intr_disable(struct e1000_hw *hw)
1403 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1404 E1000_WRITE_FLUSH(hw);
1408 * It disabled receive packet interrupt.
1410 * Pointer to struct e1000_hw
1415 em_rxq_intr_disable(struct e1000_hw *hw)
1417 E1000_READ_REG(hw, E1000_ICR);
1418 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1419 E1000_WRITE_FLUSH(hw);
1423 * It reads ICR and gets interrupt causes, check it and set a bit flag
1424 * to update link status.
1427 * Pointer to struct rte_eth_dev.
1430 * - On success, zero.
1431 * - On failure, a negative value.
1434 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1437 struct e1000_hw *hw =
1438 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1439 struct e1000_interrupt *intr =
1440 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1442 /* read-on-clear nic registers here */
1443 icr = E1000_READ_REG(hw, E1000_ICR);
1444 if (icr & E1000_ICR_LSC) {
1445 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1452 * It executes link_update after knowing an interrupt is prsent.
1455 * Pointer to struct rte_eth_dev.
1458 * - On success, zero.
1459 * - On failure, a negative value.
1462 eth_em_interrupt_action(struct rte_eth_dev *dev)
1464 struct e1000_hw *hw =
1465 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466 struct e1000_interrupt *intr =
1467 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1468 uint32_t tctl, rctl;
1469 struct rte_eth_link link;
1472 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1475 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1476 rte_intr_enable(&(dev->pci_dev->intr_handle));
1478 /* set get_link_status to check register later */
1479 hw->mac.get_link_status = 1;
1480 ret = eth_em_link_update(dev, 0);
1482 /* check if link has changed */
1486 memset(&link, 0, sizeof(link));
1487 rte_em_dev_atomic_read_link_status(dev, &link);
1488 if (link.link_status) {
1489 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1490 dev->data->port_id, (unsigned)link.link_speed,
1491 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1492 "full-duplex" : "half-duplex");
1494 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1496 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1497 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1498 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1500 tctl = E1000_READ_REG(hw, E1000_TCTL);
1501 rctl = E1000_READ_REG(hw, E1000_RCTL);
1502 if (link.link_status) {
1504 tctl |= E1000_TCTL_EN;
1505 rctl |= E1000_RCTL_EN;
1508 tctl &= ~E1000_TCTL_EN;
1509 rctl &= ~E1000_RCTL_EN;
1511 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1512 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1513 E1000_WRITE_FLUSH(hw);
1519 * Interrupt handler which shall be registered at first.
1522 * Pointer to interrupt handle.
1524 * The address of parameter (struct rte_eth_dev *) regsitered before.
1530 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1533 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1535 eth_em_interrupt_get_status(dev);
1536 eth_em_interrupt_action(dev);
1537 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1541 eth_em_led_on(struct rte_eth_dev *dev)
1543 struct e1000_hw *hw;
1545 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1546 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1550 eth_em_led_off(struct rte_eth_dev *dev)
1552 struct e1000_hw *hw;
1554 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1559 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1561 struct e1000_hw *hw;
1566 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567 fc_conf->pause_time = hw->fc.pause_time;
1568 fc_conf->high_water = hw->fc.high_water;
1569 fc_conf->low_water = hw->fc.low_water;
1570 fc_conf->send_xon = hw->fc.send_xon;
1571 fc_conf->autoneg = hw->mac.autoneg;
1574 * Return rx_pause and tx_pause status according to actual setting of
1575 * the TFCE and RFCE bits in the CTRL register.
1577 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1578 if (ctrl & E1000_CTRL_TFCE)
1583 if (ctrl & E1000_CTRL_RFCE)
1588 if (rx_pause && tx_pause)
1589 fc_conf->mode = RTE_FC_FULL;
1591 fc_conf->mode = RTE_FC_RX_PAUSE;
1593 fc_conf->mode = RTE_FC_TX_PAUSE;
1595 fc_conf->mode = RTE_FC_NONE;
1601 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1603 struct e1000_hw *hw;
1605 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1611 uint32_t rx_buf_size;
1612 uint32_t max_high_water;
1615 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616 if (fc_conf->autoneg != hw->mac.autoneg)
1618 rx_buf_size = em_get_rx_buffer_size(hw);
1619 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1621 /* At least reserve one Ethernet frame for watermark */
1622 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1623 if ((fc_conf->high_water > max_high_water) ||
1624 (fc_conf->high_water < fc_conf->low_water)) {
1625 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1626 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1630 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1631 hw->fc.pause_time = fc_conf->pause_time;
1632 hw->fc.high_water = fc_conf->high_water;
1633 hw->fc.low_water = fc_conf->low_water;
1634 hw->fc.send_xon = fc_conf->send_xon;
1636 err = e1000_setup_link_generic(hw);
1637 if (err == E1000_SUCCESS) {
1639 /* check if we want to forward MAC frames - driver doesn't have native
1640 * capability to do that, so we'll write the registers ourselves */
1642 rctl = E1000_READ_REG(hw, E1000_RCTL);
1644 /* set or clear MFLCN.PMCF bit depending on configuration */
1645 if (fc_conf->mac_ctrl_frame_fwd != 0)
1646 rctl |= E1000_RCTL_PMCF;
1648 rctl &= ~E1000_RCTL_PMCF;
1650 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1651 E1000_WRITE_FLUSH(hw);
1656 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1661 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1662 uint32_t index, __rte_unused uint32_t pool)
1664 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1670 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1672 uint8_t addr[ETHER_ADDR_LEN];
1673 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675 memset(addr, 0, sizeof(addr));
1677 e1000_rar_set(hw, addr, index);
1681 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1683 struct rte_eth_dev_info dev_info;
1684 struct e1000_hw *hw;
1685 uint32_t frame_size;
1688 eth_em_infos_get(dev, &dev_info);
1689 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1691 /* check that mtu is within the allowed range */
1692 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1695 /* refuse mtu that requires the support of scattered packets when this
1696 * feature has not been enabled before. */
1697 if (!dev->data->scattered_rx &&
1698 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1701 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702 rctl = E1000_READ_REG(hw, E1000_RCTL);
1704 /* switch to jumbo mode if needed */
1705 if (frame_size > ETHER_MAX_LEN) {
1706 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1707 rctl |= E1000_RCTL_LPE;
1709 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1710 rctl &= ~E1000_RCTL_LPE;
1712 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1714 /* update max frame size */
1715 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1720 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1721 struct ether_addr *mc_addr_set,
1722 uint32_t nb_mc_addr)
1724 struct e1000_hw *hw;
1726 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1731 struct rte_driver em_pmd_drv = {
1733 .init = rte_em_pmd_init,
1736 PMD_REGISTER_DRIVER(em_pmd_drv);