drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_malloc.h>
  24 #include <rte_dev.h>
  25
  26 #include "e1000_logs.h"
  27 #include "base/e1000_api.h"
  28 #include "e1000_ethdev.h"
  29
  30 #define EM_EIAC                 0x000DC
  31
  32 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  33
  34
  35 static int eth_em_configure(struct rte_eth_dev *dev);
  36 static int eth_em_start(struct rte_eth_dev *dev);
  37 static void eth_em_stop(struct rte_eth_dev *dev);
  38 static void eth_em_close(struct rte_eth_dev *dev);
  39 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  40 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  41 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  42 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  43 static int eth_em_link_update(struct rte_eth_dev *dev,
  44                                 int wait_to_complete);
  45 static int eth_em_stats_get(struct rte_eth_dev *dev,
  46                                 struct rte_eth_stats *rte_stats);
  47 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  48 static void eth_em_infos_get(struct rte_eth_dev *dev,
  49                                 struct rte_eth_dev_info *dev_info);
  50 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  51                                 struct rte_eth_fc_conf *fc_conf);
  52 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  53                                 struct rte_eth_fc_conf *fc_conf);
  54 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  55 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  56 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  57 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  58                                    struct rte_intr_handle *handle);
  59 static void eth_em_interrupt_handler(void *param);
  60
  61 static int em_hw_init(struct e1000_hw *hw);
  62 static int em_hardware_init(struct e1000_hw *hw);
  63 static void em_hw_control_acquire(struct e1000_hw *hw);
  64 static void em_hw_control_release(struct e1000_hw *hw);
  65 static void em_init_manageability(struct e1000_hw *hw);
  66 static void em_release_manageability(struct e1000_hw *hw);
  67
  68 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69
  70 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  71                 uint16_t vlan_id, int on);
  72 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  73 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  74 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  76 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  77
  78 /*
  79 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  80                                         uint16_t vlan_id, int on);
  81 */
  82
  83 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  84 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  85 static void em_lsc_intr_disable(struct e1000_hw *hw);
  86 static void em_rxq_intr_enable(struct e1000_hw *hw);
  87 static void em_rxq_intr_disable(struct e1000_hw *hw);
  88
  89 static int eth_em_led_on(struct rte_eth_dev *dev);
  90 static int eth_em_led_off(struct rte_eth_dev *dev);
  91
  92 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  93 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
  94                           uint32_t index, uint32_t pool);
  95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  96 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
  97                                          struct ether_addr *addr);
  98
  99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 100                                    struct ether_addr *mc_addr_set,
 101                                    uint32_t nb_mc_addr);
 102
 103 #define EM_FC_PAUSE_TIME 0x0680
 104 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 106
 107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 108
 109 int e1000_logtype_init;
 110 int e1000_logtype_driver;
 111
 112 /*
 113  * The set of PCI devices this driver supports
 114  */
 115 static const struct rte_pci_id pci_id_em_map[] = {
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 159         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 160         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 161         { .vendor_id = 0, /* sentinel */ },
 162 };
 163
 164 static const struct eth_dev_ops eth_em_ops = {
 165         .dev_configure        = eth_em_configure,
 166         .dev_start            = eth_em_start,
 167         .dev_stop             = eth_em_stop,
 168         .dev_close            = eth_em_close,
 169         .promiscuous_enable   = eth_em_promiscuous_enable,
 170         .promiscuous_disable  = eth_em_promiscuous_disable,
 171         .allmulticast_enable  = eth_em_allmulticast_enable,
 172         .allmulticast_disable = eth_em_allmulticast_disable,
 173         .link_update          = eth_em_link_update,
 174         .stats_get            = eth_em_stats_get,
 175         .stats_reset          = eth_em_stats_reset,
 176         .dev_infos_get        = eth_em_infos_get,
 177         .mtu_set              = eth_em_mtu_set,
 178         .vlan_filter_set      = eth_em_vlan_filter_set,
 179         .vlan_offload_set     = eth_em_vlan_offload_set,
 180         .rx_queue_setup       = eth_em_rx_queue_setup,
 181         .rx_queue_release     = eth_em_rx_queue_release,
 182         .rx_queue_count       = eth_em_rx_queue_count,
 183         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 184         .rx_descriptor_status = eth_em_rx_descriptor_status,
 185         .tx_descriptor_status = eth_em_tx_descriptor_status,
 186         .tx_queue_setup       = eth_em_tx_queue_setup,
 187         .tx_queue_release     = eth_em_tx_queue_release,
 188         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 189         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 190         .dev_led_on           = eth_em_led_on,
 191         .dev_led_off          = eth_em_led_off,
 192         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 193         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 194         .mac_addr_set         = eth_em_default_mac_addr_set,
 195         .mac_addr_add         = eth_em_rar_set,
 196         .mac_addr_remove      = eth_em_rar_clear,
 197         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 198         .rxq_info_get         = em_rxq_info_get,
 199         .txq_info_get         = em_txq_info_get,
 200 };
 201
 202
 203 /**
 204  *  eth_em_dev_is_ich8 - Check for ICH8 device
 205  *  @hw: pointer to the HW structure
 206  *
 207  *  return TRUE for ICH8, otherwise FALSE
 208  **/
 209 static bool
 210 eth_em_dev_is_ich8(struct e1000_hw *hw)
 211 {
 212         DEBUGFUNC("eth_em_dev_is_ich8");
 213
 214         switch (hw->device_id) {
 215         case E1000_DEV_ID_PCH2_LV_LM:
 216         case E1000_DEV_ID_PCH_LPT_I217_LM:
 217         case E1000_DEV_ID_PCH_LPT_I217_V:
 218         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 219         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 220         case E1000_DEV_ID_PCH_I218_V2:
 221         case E1000_DEV_ID_PCH_I218_LM2:
 222         case E1000_DEV_ID_PCH_I218_V3:
 223         case E1000_DEV_ID_PCH_I218_LM3:
 224         case E1000_DEV_ID_PCH_SPT_I219_LM:
 225         case E1000_DEV_ID_PCH_SPT_I219_V:
 226         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 227         case E1000_DEV_ID_PCH_SPT_I219_V2:
 228         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 229         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 230         case E1000_DEV_ID_PCH_SPT_I219_V4:
 231         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 232         case E1000_DEV_ID_PCH_SPT_I219_V5:
 233         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 234         case E1000_DEV_ID_PCH_CNP_I219_V6:
 235         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 236         case E1000_DEV_ID_PCH_CNP_I219_V7:
 237                 return 1;
 238         default:
 239                 return 0;
 240         }
 241 }
 242
 243 static int
 244 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 245 {
 246         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 247         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 248         struct e1000_adapter *adapter =
 249                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 250         struct e1000_hw *hw =
 251                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 252         struct e1000_vfta * shadow_vfta =
 253                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 254
 255         eth_dev->dev_ops = &eth_em_ops;
 256         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 257         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 258         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 259
 260         /* for secondary processes, we don't initialise any further as primary
 261          * has already done this work. Only check we don't need a different
 262          * RX function */
 263         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 264                 if (eth_dev->data->scattered_rx)
 265                         eth_dev->rx_pkt_burst =
 266                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 267                 return 0;
 268         }
 269
 270         rte_eth_copy_pci_info(eth_dev, pci_dev);
 271
 272         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 273         hw->device_id = pci_dev->id.device_id;
 274         adapter->stopped = 0;
 275
 276         /* For ICH8 support we'll need to map the flash memory BAR */
 277         if (eth_em_dev_is_ich8(hw))
 278                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 279
 280         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 281                         em_hw_init(hw) != 0) {
 282                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 283                         "failed to init HW",
 284                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 285                         pci_dev->id.device_id);
 286                 return -ENODEV;
 287         }
 288
 289         /* Allocate memory for storing MAC addresses */
 290         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 291                         hw->mac.rar_entry_count, 0);
 292         if (eth_dev->data->mac_addrs == NULL) {
 293                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 294                         "store MAC addresses",
 295                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 296                 return -ENOMEM;
 297         }
 298
 299         /* Copy the permanent MAC address */
 300         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 301                 eth_dev->data->mac_addrs);
 302
 303         /* initialize the vfta */
 304         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 305
 306         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 307                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 308                      pci_dev->id.device_id);
 309
 310         rte_intr_callback_register(intr_handle,
 311                                    eth_em_interrupt_handler, eth_dev);
 312
 313         return 0;
 314 }
 315
 316 static int
 317 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 318 {
 319         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 320         struct e1000_adapter *adapter =
 321                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 322         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 323
 324         PMD_INIT_FUNC_TRACE();
 325
 326         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 327                 return -EPERM;
 328
 329         if (adapter->stopped == 0)
 330                 eth_em_close(eth_dev);
 331
 332         eth_dev->dev_ops = NULL;
 333         eth_dev->rx_pkt_burst = NULL;
 334         eth_dev->tx_pkt_burst = NULL;
 335
 336         rte_free(eth_dev->data->mac_addrs);
 337         eth_dev->data->mac_addrs = NULL;
 338
 339         /* disable uio intr before callback unregister */
 340         rte_intr_disable(intr_handle);
 341         rte_intr_callback_unregister(intr_handle,
 342                                      eth_em_interrupt_handler, eth_dev);
 343
 344         return 0;
 345 }
 346
 347 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 348         struct rte_pci_device *pci_dev)
 349 {
 350         return rte_eth_dev_pci_generic_probe(pci_dev,
 351                 sizeof(struct e1000_adapter), eth_em_dev_init);
 352 }
 353
 354 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 355 {
 356         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 357 }
 358
 359 static struct rte_pci_driver rte_em_pmd = {
 360         .id_table = pci_id_em_map,
 361         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 362                      RTE_PCI_DRV_IOVA_AS_VA,
 363         .probe = eth_em_pci_probe,
 364         .remove = eth_em_pci_remove,
 365 };
 366
 367 static int
 368 em_hw_init(struct e1000_hw *hw)
 369 {
 370         int diag;
 371
 372         diag = hw->mac.ops.init_params(hw);
 373         if (diag != 0) {
 374                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 375                 return diag;
 376         }
 377         diag = hw->nvm.ops.init_params(hw);
 378         if (diag != 0) {
 379                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 380                 return diag;
 381         }
 382         diag = hw->phy.ops.init_params(hw);
 383         if (diag != 0) {
 384                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 385                 return diag;
 386         }
 387         (void) e1000_get_bus_info(hw);
 388
 389         hw->mac.autoneg = 1;
 390         hw->phy.autoneg_wait_to_complete = 0;
 391         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 392
 393         e1000_init_script_state_82541(hw, TRUE);
 394         e1000_set_tbi_compatibility_82543(hw, TRUE);
 395
 396         /* Copper options */
 397         if (hw->phy.media_type == e1000_media_type_copper) {
 398                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 399                 hw->phy.disable_polarity_correction = 0;
 400                 hw->phy.ms_type = e1000_ms_hw_default;
 401         }
 402
 403         /*
 404          * Start from a known state, this is important in reading the nvm
 405          * and mac from that.
 406          */
 407         e1000_reset_hw(hw);
 408
 409         /* Make sure we have a good EEPROM before we read from it */
 410         if (e1000_validate_nvm_checksum(hw) < 0) {
 411                 /*
 412                  * Some PCI-E parts fail the first check due to
 413                  * the link being in sleep state, call it again,
 414                  * if it fails a second time its a real issue.
 415                  */
 416                 diag = e1000_validate_nvm_checksum(hw);
 417                 if (diag < 0) {
 418                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 419                         goto error;
 420                 }
 421         }
 422
 423         /* Read the permanent MAC address out of the EEPROM */
 424         diag = e1000_read_mac_addr(hw);
 425         if (diag != 0) {
 426                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 427                 goto error;
 428         }
 429
 430         /* Now initialize the hardware */
 431         diag = em_hardware_init(hw);
 432         if (diag != 0) {
 433                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 434                 goto error;
 435         }
 436
 437         hw->mac.get_link_status = 1;
 438
 439         /* Indicate SOL/IDER usage */
 440         diag = e1000_check_reset_block(hw);
 441         if (diag < 0) {
 442                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 443                         "SOL/IDER session");
 444         }
 445         return 0;
 446
 447 error:
 448         em_hw_control_release(hw);
 449         return diag;
 450 }
 451
 452 static int
 453 eth_em_configure(struct rte_eth_dev *dev)
 454 {
 455         struct e1000_interrupt *intr =
 456                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 457
 458         PMD_INIT_FUNC_TRACE();
 459         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 460
 461         PMD_INIT_FUNC_TRACE();
 462
 463         return 0;
 464 }
 465
 466 static void
 467 em_set_pba(struct e1000_hw *hw)
 468 {
 469         uint32_t pba;
 470
 471         /*
 472          * Packet Buffer Allocation (PBA)
 473          * Writing PBA sets the receive portion of the buffer
 474          * the remainder is used for the transmit buffer.
 475          * Devices before the 82547 had a Packet Buffer of 64K.
 476          * After the 82547 the buffer was reduced to 40K.
 477          */
 478         switch (hw->mac.type) {
 479                 case e1000_82547:
 480                 case e1000_82547_rev_2:
 481                 /* 82547: Total Packet Buffer is 40K */
 482                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 483                         break;
 484                 case e1000_82571:
 485                 case e1000_82572:
 486                 case e1000_80003es2lan:
 487                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 488                         break;
 489                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 490                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 491                         break;
 492                 case e1000_82574:
 493                 case e1000_82583:
 494                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 495                         break;
 496                 case e1000_ich8lan:
 497                         pba = E1000_PBA_8K;
 498                         break;
 499                 case e1000_ich9lan:
 500                 case e1000_ich10lan:
 501                         pba = E1000_PBA_10K;
 502                         break;
 503                 case e1000_pchlan:
 504                 case e1000_pch2lan:
 505                 case e1000_pch_lpt:
 506                 case e1000_pch_spt:
 507                 case e1000_pch_cnp:
 508                         pba = E1000_PBA_26K;
 509                         break;
 510                 default:
 511                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 512         }
 513
 514         E1000_WRITE_REG(hw, E1000_PBA, pba);
 515 }
 516
 517 static void
 518 eth_em_rxtx_control(struct rte_eth_dev *dev,
 519                     bool enable)
 520 {
 521         struct e1000_hw *hw =
 522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 523         uint32_t tctl, rctl;
 524
 525         tctl = E1000_READ_REG(hw, E1000_TCTL);
 526         rctl = E1000_READ_REG(hw, E1000_RCTL);
 527         if (enable) {
 528                 /* enable Tx/Rx */
 529                 tctl |= E1000_TCTL_EN;
 530                 rctl |= E1000_RCTL_EN;
 531         } else {
 532                 /* disable Tx/Rx */
 533                 tctl &= ~E1000_TCTL_EN;
 534                 rctl &= ~E1000_RCTL_EN;
 535         }
 536         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 537         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 538         E1000_WRITE_FLUSH(hw);
 539 }
 540
 541 static int
 542 eth_em_start(struct rte_eth_dev *dev)
 543 {
 544         struct e1000_adapter *adapter =
 545                 E1000_DEV_PRIVATE(dev->data->dev_private);
 546         struct e1000_hw *hw =
 547                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 548         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 549         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 550         int ret, mask;
 551         uint32_t intr_vector = 0;
 552         uint32_t *speeds;
 553         int num_speeds;
 554         bool autoneg;
 555
 556         PMD_INIT_FUNC_TRACE();
 557
 558         eth_em_stop(dev);
 559
 560         e1000_power_up_phy(hw);
 561
 562         /* Set default PBA value */
 563         em_set_pba(hw);
 564
 565         /* Put the address into the Receive Address Array */
 566         e1000_rar_set(hw, hw->mac.addr, 0);
 567
 568         /*
 569          * With the 82571 adapter, RAR[0] may be overwritten
 570          * when the other port is reset, we make a duplicate
 571          * in RAR[14] for that eventuality, this assures
 572          * the interface continues to function.
 573          */
 574         if (hw->mac.type == e1000_82571) {
 575                 e1000_set_laa_state_82571(hw, TRUE);
 576                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 577         }
 578
 579         /* Initialize the hardware */
 580         if (em_hardware_init(hw)) {
 581                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 582                 return -EIO;
 583         }
 584
 585         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 586
 587         /* Configure for OS presence */
 588         em_init_manageability(hw);
 589
 590         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 591                 intr_vector = dev->data->nb_rx_queues;
 592                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 593                         return -1;
 594         }
 595
 596         if (rte_intr_dp_is_en(intr_handle)) {
 597                 intr_handle->intr_vec =
 598                         rte_zmalloc("intr_vec",
 599                                         dev->data->nb_rx_queues * sizeof(int), 0);
 600                 if (intr_handle->intr_vec == NULL) {
 601                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 602                                                 " intr_vec", dev->data->nb_rx_queues);
 603                         return -ENOMEM;
 604                 }
 605
 606                 /* enable rx interrupt */
 607                 em_rxq_intr_enable(hw);
 608         }
 609
 610         eth_em_tx_init(dev);
 611
 612         ret = eth_em_rx_init(dev);
 613         if (ret) {
 614                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 615                 em_dev_clear_queues(dev);
 616                 return ret;
 617         }
 618
 619         e1000_clear_hw_cntrs_base_generic(hw);
 620
 621         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 622                         ETH_VLAN_EXTEND_MASK;
 623         ret = eth_em_vlan_offload_set(dev, mask);
 624         if (ret) {
 625                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 626                 em_dev_clear_queues(dev);
 627                 return ret;
 628         }
 629
 630         /* Set Interrupt Throttling Rate to maximum allowed value. */
 631         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 632
 633         /* Setup link speed and duplex */
 634         speeds = &dev->data->dev_conf.link_speeds;
 635         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 636                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 637                 hw->mac.autoneg = 1;
 638         } else {
 639                 num_speeds = 0;
 640                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 641
 642                 /* Reset */
 643                 hw->phy.autoneg_advertised = 0;
 644
 645                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 646                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 647                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 648                         num_speeds = -1;
 649                         goto error_invalid_config;
 650                 }
 651                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 652                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 653                         num_speeds++;
 654                 }
 655                 if (*speeds & ETH_LINK_SPEED_10M) {
 656                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 657                         num_speeds++;
 658                 }
 659                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 660                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 661                         num_speeds++;
 662                 }
 663                 if (*speeds & ETH_LINK_SPEED_100M) {
 664                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 665                         num_speeds++;
 666                 }
 667                 if (*speeds & ETH_LINK_SPEED_1G) {
 668                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 669                         num_speeds++;
 670                 }
 671                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 672                         goto error_invalid_config;
 673
 674                 /* Set/reset the mac.autoneg based on the link speed,
 675                  * fixed or not
 676                  */
 677                 if (!autoneg) {
 678                         hw->mac.autoneg = 0;
 679                         hw->mac.forced_speed_duplex =
 680                                         hw->phy.autoneg_advertised;
 681                 } else {
 682                         hw->mac.autoneg = 1;
 683                 }
 684         }
 685
 686         e1000_setup_link(hw);
 687
 688         if (rte_intr_allow_others(intr_handle)) {
 689                 /* check if lsc interrupt is enabled */
 690                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 691                         ret = eth_em_interrupt_setup(dev);
 692                         if (ret) {
 693                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 694                                 em_dev_clear_queues(dev);
 695                                 return ret;
 696                         }
 697                 }
 698         } else {
 699                 rte_intr_callback_unregister(intr_handle,
 700                                                 eth_em_interrupt_handler,
 701                                                 (void *)dev);
 702                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 703                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 704                                      " no intr multiplexn");
 705         }
 706         /* check if rxq interrupt is enabled */
 707         if (dev->data->dev_conf.intr_conf.rxq != 0)
 708                 eth_em_rxq_interrupt_setup(dev);
 709
 710         rte_intr_enable(intr_handle);
 711
 712         adapter->stopped = 0;
 713
 714         eth_em_rxtx_control(dev, true);
 715         eth_em_link_update(dev, 0);
 716
 717         PMD_INIT_LOG(DEBUG, "<<");
 718
 719         return 0;
 720
 721 error_invalid_config:
 722         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 723                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 724         em_dev_clear_queues(dev);
 725         return -EINVAL;
 726 }
 727
 728 /*********************************************************************
 729  *
 730  *  This routine disables all traffic on the adapter by issuing a
 731  *  global reset on the MAC.
 732  *
 733  **********************************************************************/
 734 static void
 735 eth_em_stop(struct rte_eth_dev *dev)
 736 {
 737         struct rte_eth_link link;
 738         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 739         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 741
 742         eth_em_rxtx_control(dev, false);
 743         em_rxq_intr_disable(hw);
 744         em_lsc_intr_disable(hw);
 745
 746         e1000_reset_hw(hw);
 747         if (hw->mac.type >= e1000_82544)
 748                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 749
 750         /* Power down the phy. Needed to make the link go down */
 751         e1000_power_down_phy(hw);
 752
 753         em_dev_clear_queues(dev);
 754
 755         /* clear the recorded link status */
 756         memset(&link, 0, sizeof(link));
 757         rte_eth_linkstatus_set(dev, &link);
 758
 759         if (!rte_intr_allow_others(intr_handle))
 760                 /* resume to the default handler */
 761                 rte_intr_callback_register(intr_handle,
 762                                            eth_em_interrupt_handler,
 763                                            (void *)dev);
 764
 765         /* Clean datapath event and queue/vec mapping */
 766         rte_intr_efd_disable(intr_handle);
 767         if (intr_handle->intr_vec != NULL) {
 768                 rte_free(intr_handle->intr_vec);
 769                 intr_handle->intr_vec = NULL;
 770         }
 771 }
 772
 773 static void
 774 eth_em_close(struct rte_eth_dev *dev)
 775 {
 776         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 777         struct e1000_adapter *adapter =
 778                 E1000_DEV_PRIVATE(dev->data->dev_private);
 779
 780         eth_em_stop(dev);
 781         adapter->stopped = 1;
 782         em_dev_free_queues(dev);
 783         e1000_phy_hw_reset(hw);
 784         em_release_manageability(hw);
 785         em_hw_control_release(hw);
 786 }
 787
 788 static int
 789 em_get_rx_buffer_size(struct e1000_hw *hw)
 790 {
 791         uint32_t rx_buf_size;
 792
 793         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 794         return rx_buf_size;
 795 }
 796
 797 /*********************************************************************
 798  *
 799  *  Initialize the hardware
 800  *
 801  **********************************************************************/
 802 static int
 803 em_hardware_init(struct e1000_hw *hw)
 804 {
 805         uint32_t rx_buf_size;
 806         int diag;
 807
 808         /* Issue a global reset */
 809         e1000_reset_hw(hw);
 810
 811         /* Let the firmware know the OS is in control */
 812         em_hw_control_acquire(hw);
 813
 814         /*
 815          * These parameters control the automatic generation (Tx) and
 816          * response (Rx) to Ethernet PAUSE frames.
 817          * - High water mark should allow for at least two standard size (1518)
 818          *   frames to be received after sending an XOFF.
 819          * - Low water mark works best when it is very near the high water mark.
 820          *   This allows the receiver to restart by sending XON when it has
 821          *   drained a bit. Here we use an arbitrary value of 1500 which will
 822          *   restart after one full frame is pulled from the buffer. There
 823          *   could be several smaller frames in the buffer and if so they will
 824          *   not trigger the XON until their total number reduces the buffer
 825          *   by 1500.
 826          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 827          */
 828         rx_buf_size = em_get_rx_buffer_size(hw);
 829
 830         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 831         hw->fc.low_water = hw->fc.high_water - 1500;
 832
 833         if (hw->mac.type == e1000_80003es2lan)
 834                 hw->fc.pause_time = UINT16_MAX;
 835         else
 836                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 837
 838         hw->fc.send_xon = 1;
 839
 840         /* Set Flow control, use the tunable location if sane */
 841         if (em_fc_setting <= e1000_fc_full)
 842                 hw->fc.requested_mode = em_fc_setting;
 843         else
 844                 hw->fc.requested_mode = e1000_fc_none;
 845
 846         /* Workaround: no TX flow ctrl for PCH */
 847         if (hw->mac.type == e1000_pchlan)
 848                 hw->fc.requested_mode = e1000_fc_rx_pause;
 849
 850         /* Override - settings for PCH2LAN, ya its magic :) */
 851         if (hw->mac.type == e1000_pch2lan) {
 852                 hw->fc.high_water = 0x5C20;
 853                 hw->fc.low_water = 0x5048;
 854                 hw->fc.pause_time = 0x0650;
 855                 hw->fc.refresh_time = 0x0400;
 856         } else if (hw->mac.type == e1000_pch_lpt ||
 857                    hw->mac.type == e1000_pch_spt ||
 858                    hw->mac.type == e1000_pch_cnp) {
 859                 hw->fc.requested_mode = e1000_fc_full;
 860         }
 861
 862         diag = e1000_init_hw(hw);
 863         if (diag < 0)
 864                 return diag;
 865         e1000_check_for_link(hw);
 866         return 0;
 867 }
 868
 869 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 870 static int
 871 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 872 {
 873         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 874         struct e1000_hw_stats *stats =
 875                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 876         int pause_frames;
 877
 878         if(hw->phy.media_type == e1000_media_type_copper ||
 879                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 880                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 881                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 882         }
 883
 884         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 885         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 886         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 887         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 888
 889         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 890         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 891         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 892         stats->dc += E1000_READ_REG(hw, E1000_DC);
 893         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 894         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 895         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 896
 897         /*
 898          * For watchdog management we need to know if we have been
 899          * paused during the last interval, so capture that here.
 900          */
 901         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 902         stats->xoffrxc += pause_frames;
 903         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 904         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 905         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 906         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 907         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 908         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 909         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 910         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 911         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 912         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 913         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 914         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 915
 916         /*
 917          * For the 64-bit byte counters the low dword must be read first.
 918          * Both registers clear on the read of the high dword.
 919          */
 920
 921         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 922         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 923         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 924         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 925
 926         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 927         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 928         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 929         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 930         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 931
 932         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 933         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 934
 935         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 936         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 937         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 938         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 939         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 940         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 941         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 942         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 943         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 944         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 945
 946         /* Interrupt Counts */
 947
 948         if (hw->mac.type >= e1000_82571) {
 949                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 950                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 951                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 952                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 953                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 954                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 955                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 956                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 957                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 958         }
 959
 960         if (hw->mac.type >= e1000_82543) {
 961                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 962                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 963                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 964                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 965                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 966                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 967         }
 968
 969         if (rte_stats == NULL)
 970                 return -EINVAL;
 971
 972         /* Rx Errors */
 973         rte_stats->imissed = stats->mpc;
 974         rte_stats->ierrors = stats->crcerrs +
 975                              stats->rlec + stats->ruc + stats->roc +
 976                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 977
 978         /* Tx Errors */
 979         rte_stats->oerrors = stats->ecol + stats->latecol;
 980
 981         rte_stats->ipackets = stats->gprc;
 982         rte_stats->opackets = stats->gptc;
 983         rte_stats->ibytes   = stats->gorc;
 984         rte_stats->obytes   = stats->gotc;
 985         return 0;
 986 }
 987
 988 static void
 989 eth_em_stats_reset(struct rte_eth_dev *dev)
 990 {
 991         struct e1000_hw_stats *hw_stats =
 992                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 993
 994         /* HW registers are cleared on read */
 995         eth_em_stats_get(dev, NULL);
 996
 997         /* Reset software totals */
 998         memset(hw_stats, 0, sizeof(*hw_stats));
 999 }
1000
1001 static int
1002 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1003 {
1004         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1005         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1006         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1007
1008         em_rxq_intr_enable(hw);
1009         rte_intr_enable(intr_handle);
1010
1011         return 0;
1012 }
1013
1014 static int
1015 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1016 {
1017         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1018
1019         em_rxq_intr_disable(hw);
1020
1021         return 0;
1022 }
1023
1024 uint32_t
1025 em_get_max_pktlen(struct rte_eth_dev *dev)
1026 {
1027         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1028
1029         switch (hw->mac.type) {
1030         case e1000_82571:
1031         case e1000_82572:
1032         case e1000_ich9lan:
1033         case e1000_ich10lan:
1034         case e1000_pch2lan:
1035         case e1000_pch_lpt:
1036         case e1000_pch_spt:
1037         case e1000_pch_cnp:
1038         case e1000_82574:
1039         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1040         case e1000_82583:
1041                 return 0x2412;
1042         case e1000_pchlan:
1043                 return 0x1000;
1044         /* Adapters that do not support jumbo frames */
1045         case e1000_ich8lan:
1046                 return ETHER_MAX_LEN;
1047         default:
1048                 return MAX_JUMBO_FRAME_SIZE;
1049         }
1050 }
1051
1052 static void
1053 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1054 {
1055         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056
1057         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1058         dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1059         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1060
1061         /*
1062          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1063          * Unfortunatelly, all these nics have just one TX context.
1064          * So we have few choises for TX:
1065          * - Use just one TX queue.
1066          * - Allow cksum offload only for one TX queue.
1067          * - Don't allow TX cksum offload at all.
1068          * For now, option #1 was chosen.
1069          * To use second RX queue we have to use extended RX descriptor
1070          * (Multiple Receive Queues are mutually exclusive with UDP
1071          * fragmentation and are not supported when a legacy receive
1072          * descriptor format is used).
1073          * Which means separate RX routinies - as legacy nics (82540, 82545)
1074          * don't support extended RXD.
1075          * To avoid it we support just one RX queue for now (no RSS).
1076          */
1077
1078         dev_info->max_rx_queues = 1;
1079         dev_info->max_tx_queues = 1;
1080
1081         dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1082         dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1083                                     dev_info->rx_queue_offload_capa;
1084         dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1085         dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1086                                     dev_info->tx_queue_offload_capa;
1087
1088         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1089                 .nb_max = E1000_MAX_RING_DESC,
1090                 .nb_min = E1000_MIN_RING_DESC,
1091                 .nb_align = EM_RXD_ALIGN,
1092         };
1093
1094         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1095                 .nb_max = E1000_MAX_RING_DESC,
1096                 .nb_min = E1000_MIN_RING_DESC,
1097                 .nb_align = EM_TXD_ALIGN,
1098                 .nb_seg_max = EM_TX_MAX_SEG,
1099                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1100         };
1101
1102         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1103                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1104                         ETH_LINK_SPEED_1G;
1105
1106         /* Preferred queue parameters */
1107         dev_info->default_rxportconf.nb_queues = 1;
1108         dev_info->default_txportconf.nb_queues = 1;
1109         dev_info->default_txportconf.ring_size = 256;
1110         dev_info->default_rxportconf.ring_size = 256;
1111 }
1112
1113 /* return 0 means link status changed, -1 means not changed */
1114 static int
1115 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1116 {
1117         struct e1000_hw *hw =
1118                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1119         struct rte_eth_link link;
1120         int link_check, count;
1121
1122         link_check = 0;
1123         hw->mac.get_link_status = 1;
1124
1125         /* possible wait-to-complete in up to 9 seconds */
1126         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1127                 /* Read the real link status */
1128                 switch (hw->phy.media_type) {
1129                 case e1000_media_type_copper:
1130                         /* Do the work to read phy */
1131                         e1000_check_for_link(hw);
1132                         link_check = !hw->mac.get_link_status;
1133                         break;
1134
1135                 case e1000_media_type_fiber:
1136                         e1000_check_for_link(hw);
1137                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1138                                         E1000_STATUS_LU);
1139                         break;
1140
1141                 case e1000_media_type_internal_serdes:
1142                         e1000_check_for_link(hw);
1143                         link_check = hw->mac.serdes_has_link;
1144                         break;
1145
1146                 default:
1147                         break;
1148                 }
1149                 if (link_check || wait_to_complete == 0)
1150                         break;
1151                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1152         }
1153         memset(&link, 0, sizeof(link));
1154
1155         /* Now we check if a transition has happened */
1156         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1157                 uint16_t duplex, speed;
1158                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1159                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1160                                 ETH_LINK_FULL_DUPLEX :
1161                                 ETH_LINK_HALF_DUPLEX;
1162                 link.link_speed = speed;
1163                 link.link_status = ETH_LINK_UP;
1164                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1165                                 ETH_LINK_SPEED_FIXED);
1166         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1167                 link.link_speed = ETH_SPEED_NUM_NONE;
1168                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1169                 link.link_status = ETH_LINK_DOWN;
1170                 link.link_autoneg = ETH_LINK_FIXED;
1171         }
1172
1173         return rte_eth_linkstatus_set(dev, &link);
1174 }
1175
1176 /*
1177  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1178  * For ASF and Pass Through versions of f/w this means
1179  * that the driver is loaded. For AMT version type f/w
1180  * this means that the network i/f is open.
1181  */
1182 static void
1183 em_hw_control_acquire(struct e1000_hw *hw)
1184 {
1185         uint32_t ctrl_ext, swsm;
1186
1187         /* Let firmware know the driver has taken over */
1188         if (hw->mac.type == e1000_82573) {
1189                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1190                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1191
1192         } else {
1193                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1194                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1195                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1196         }
1197 }
1198
1199 /*
1200  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1201  * For ASF and Pass Through versions of f/w this means that the
1202  * driver is no longer loaded. For AMT versions of the
1203  * f/w this means that the network i/f is closed.
1204  */
1205 static void
1206 em_hw_control_release(struct e1000_hw *hw)
1207 {
1208         uint32_t ctrl_ext, swsm;
1209
1210         /* Let firmware taken over control of h/w */
1211         if (hw->mac.type == e1000_82573) {
1212                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1213                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1214         } else {
1215                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1216                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1217                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1218         }
1219 }
1220
1221 /*
1222  * Bit of a misnomer, what this really means is
1223  * to enable OS management of the system... aka
1224  * to disable special hardware management features.
1225  */
1226 static void
1227 em_init_manageability(struct e1000_hw *hw)
1228 {
1229         if (e1000_enable_mng_pass_thru(hw)) {
1230                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1231                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1232
1233                 /* disable hardware interception of ARP */
1234                 manc &= ~(E1000_MANC_ARP_EN);
1235
1236                 /* enable receiving management packets to the host */
1237                 manc |= E1000_MANC_EN_MNG2HOST;
1238                 manc2h |= 1 << 5;  /* Mng Port 623 */
1239                 manc2h |= 1 << 6;  /* Mng Port 664 */
1240                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1241                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1242         }
1243 }
1244
1245 /*
1246  * Give control back to hardware management
1247  * controller if there is one.
1248  */
1249 static void
1250 em_release_manageability(struct e1000_hw *hw)
1251 {
1252         uint32_t manc;
1253
1254         if (e1000_enable_mng_pass_thru(hw)) {
1255                 manc = E1000_READ_REG(hw, E1000_MANC);
1256
1257                 /* re-enable hardware interception of ARP */
1258                 manc |= E1000_MANC_ARP_EN;
1259                 manc &= ~E1000_MANC_EN_MNG2HOST;
1260
1261                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1262         }
1263 }
1264
1265 static void
1266 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1267 {
1268         struct e1000_hw *hw =
1269                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1270         uint32_t rctl;
1271
1272         rctl = E1000_READ_REG(hw, E1000_RCTL);
1273         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1274         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1275 }
1276
1277 static void
1278 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1279 {
1280         struct e1000_hw *hw =
1281                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1282         uint32_t rctl;
1283
1284         rctl = E1000_READ_REG(hw, E1000_RCTL);
1285         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1286         if (dev->data->all_multicast == 1)
1287                 rctl |= E1000_RCTL_MPE;
1288         else
1289                 rctl &= (~E1000_RCTL_MPE);
1290         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1291 }
1292
1293 static void
1294 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1295 {
1296         struct e1000_hw *hw =
1297                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1298         uint32_t rctl;
1299
1300         rctl = E1000_READ_REG(hw, E1000_RCTL);
1301         rctl |= E1000_RCTL_MPE;
1302         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1303 }
1304
1305 static void
1306 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1307 {
1308         struct e1000_hw *hw =
1309                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310         uint32_t rctl;
1311
1312         if (dev->data->promiscuous == 1)
1313                 return; /* must remain in all_multicast mode */
1314         rctl = E1000_READ_REG(hw, E1000_RCTL);
1315         rctl &= (~E1000_RCTL_MPE);
1316         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1317 }
1318
1319 static int
1320 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1321 {
1322         struct e1000_hw *hw =
1323                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324         struct e1000_vfta * shadow_vfta =
1325                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1326         uint32_t vfta;
1327         uint32_t vid_idx;
1328         uint32_t vid_bit;
1329
1330         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1331                               E1000_VFTA_ENTRY_MASK);
1332         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1333         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1334         if (on)
1335                 vfta |= vid_bit;
1336         else
1337                 vfta &= ~vid_bit;
1338         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1339
1340         /* update local VFTA copy */
1341         shadow_vfta->vfta[vid_idx] = vfta;
1342
1343         return 0;
1344 }
1345
1346 static void
1347 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1348 {
1349         struct e1000_hw *hw =
1350                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351         uint32_t reg;
1352
1353         /* Filter Table Disable */
1354         reg = E1000_READ_REG(hw, E1000_RCTL);
1355         reg &= ~E1000_RCTL_CFIEN;
1356         reg &= ~E1000_RCTL_VFE;
1357         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1358 }
1359
1360 static void
1361 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1362 {
1363         struct e1000_hw *hw =
1364                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1365         struct e1000_vfta * shadow_vfta =
1366                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1367         uint32_t reg;
1368         int i;
1369
1370         /* Filter Table Enable, CFI not used for packet acceptance */
1371         reg = E1000_READ_REG(hw, E1000_RCTL);
1372         reg &= ~E1000_RCTL_CFIEN;
1373         reg |= E1000_RCTL_VFE;
1374         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1375
1376         /* restore vfta from local copy */
1377         for (i = 0; i < IGB_VFTA_SIZE; i++)
1378                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1379 }
1380
1381 static void
1382 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1383 {
1384         struct e1000_hw *hw =
1385                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1386         uint32_t reg;
1387
1388         /* VLAN Mode Disable */
1389         reg = E1000_READ_REG(hw, E1000_CTRL);
1390         reg &= ~E1000_CTRL_VME;
1391         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1392
1393 }
1394
1395 static void
1396 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1397 {
1398         struct e1000_hw *hw =
1399                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400         uint32_t reg;
1401
1402         /* VLAN Mode Enable */
1403         reg = E1000_READ_REG(hw, E1000_CTRL);
1404         reg |= E1000_CTRL_VME;
1405         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1406 }
1407
1408 static int
1409 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1410 {
1411         struct rte_eth_rxmode *rxmode;
1412
1413         rxmode = &dev->data->dev_conf.rxmode;
1414         if(mask & ETH_VLAN_STRIP_MASK){
1415                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1416                         em_vlan_hw_strip_enable(dev);
1417                 else
1418                         em_vlan_hw_strip_disable(dev);
1419         }
1420
1421         if(mask & ETH_VLAN_FILTER_MASK){
1422                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1423                         em_vlan_hw_filter_enable(dev);
1424                 else
1425                         em_vlan_hw_filter_disable(dev);
1426         }
1427
1428         return 0;
1429 }
1430
1431 /*
1432  * It enables the interrupt mask and then enable the interrupt.
1433  *
1434  * @param dev
1435  *  Pointer to struct rte_eth_dev.
1436  *
1437  * @return
1438  *  - On success, zero.
1439  *  - On failure, a negative value.
1440  */
1441 static int
1442 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1443 {
1444         uint32_t regval;
1445         struct e1000_hw *hw =
1446                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1447
1448         /* clear interrupt */
1449         E1000_READ_REG(hw, E1000_ICR);
1450         regval = E1000_READ_REG(hw, E1000_IMS);
1451         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1452         return 0;
1453 }
1454
1455 /*
1456  * It clears the interrupt causes and enables the interrupt.
1457  * It will be called once only during nic initialized.
1458  *
1459  * @param dev
1460  *  Pointer to struct rte_eth_dev.
1461  *
1462  * @return
1463  *  - On success, zero.
1464  *  - On failure, a negative value.
1465  */
1466 static int
1467 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1468 {
1469         struct e1000_hw *hw =
1470         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1471
1472         E1000_READ_REG(hw, E1000_ICR);
1473         em_rxq_intr_enable(hw);
1474         return 0;
1475 }
1476
1477 /*
1478  * It enable receive packet interrupt.
1479  * @param hw
1480  * Pointer to struct e1000_hw
1481  *
1482  * @return
1483  */
1484 static void
1485 em_rxq_intr_enable(struct e1000_hw *hw)
1486 {
1487         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1488         E1000_WRITE_FLUSH(hw);
1489 }
1490
1491 /*
1492  * It disabled lsc interrupt.
1493  * @param hw
1494  * Pointer to struct e1000_hw
1495  *
1496  * @return
1497  */
1498 static void
1499 em_lsc_intr_disable(struct e1000_hw *hw)
1500 {
1501         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1502         E1000_WRITE_FLUSH(hw);
1503 }
1504
1505 /*
1506  * It disabled receive packet interrupt.
1507  * @param hw
1508  * Pointer to struct e1000_hw
1509  *
1510  * @return
1511  */
1512 static void
1513 em_rxq_intr_disable(struct e1000_hw *hw)
1514 {
1515         E1000_READ_REG(hw, E1000_ICR);
1516         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1517         E1000_WRITE_FLUSH(hw);
1518 }
1519
1520 /*
1521  * It reads ICR and gets interrupt causes, check it and set a bit flag
1522  * to update link status.
1523  *
1524  * @param dev
1525  *  Pointer to struct rte_eth_dev.
1526  *
1527  * @return
1528  *  - On success, zero.
1529  *  - On failure, a negative value.
1530  */
1531 static int
1532 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1533 {
1534         uint32_t icr;
1535         struct e1000_hw *hw =
1536                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         struct e1000_interrupt *intr =
1538                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1539
1540         /* read-on-clear nic registers here */
1541         icr = E1000_READ_REG(hw, E1000_ICR);
1542         if (icr & E1000_ICR_LSC) {
1543                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1544         }
1545
1546         return 0;
1547 }
1548
1549 /*
1550  * It executes link_update after knowing an interrupt is prsent.
1551  *
1552  * @param dev
1553  *  Pointer to struct rte_eth_dev.
1554  *
1555  * @return
1556  *  - On success, zero.
1557  *  - On failure, a negative value.
1558  */
1559 static int
1560 eth_em_interrupt_action(struct rte_eth_dev *dev,
1561                         struct rte_intr_handle *intr_handle)
1562 {
1563         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1564         struct e1000_hw *hw =
1565                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566         struct e1000_interrupt *intr =
1567                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1568         struct rte_eth_link link;
1569         int ret;
1570
1571         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1572                 return -1;
1573
1574         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1575         rte_intr_enable(intr_handle);
1576
1577         /* set get_link_status to check register later */
1578         hw->mac.get_link_status = 1;
1579         ret = eth_em_link_update(dev, 0);
1580
1581         /* check if link has changed */
1582         if (ret < 0)
1583                 return 0;
1584
1585         rte_eth_linkstatus_get(dev, &link);
1586
1587         if (link.link_status) {
1588                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1589                              dev->data->port_id, link.link_speed,
1590                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1591                              "full-duplex" : "half-duplex");
1592         } else {
1593                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1594         }
1595         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1596                      pci_dev->addr.domain, pci_dev->addr.bus,
1597                      pci_dev->addr.devid, pci_dev->addr.function);
1598
1599         return 0;
1600 }
1601
1602 /**
1603  * Interrupt handler which shall be registered at first.
1604  *
1605  * @param handle
1606  *  Pointer to interrupt handle.
1607  * @param param
1608  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1609  *
1610  * @return
1611  *  void
1612  */
1613 static void
1614 eth_em_interrupt_handler(void *param)
1615 {
1616         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1617
1618         eth_em_interrupt_get_status(dev);
1619         eth_em_interrupt_action(dev, dev->intr_handle);
1620         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1621 }
1622
1623 static int
1624 eth_em_led_on(struct rte_eth_dev *dev)
1625 {
1626         struct e1000_hw *hw;
1627
1628         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1629         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1630 }
1631
1632 static int
1633 eth_em_led_off(struct rte_eth_dev *dev)
1634 {
1635         struct e1000_hw *hw;
1636
1637         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1639 }
1640
1641 static int
1642 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1643 {
1644         struct e1000_hw *hw;
1645         uint32_t ctrl;
1646         int tx_pause;
1647         int rx_pause;
1648
1649         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         fc_conf->pause_time = hw->fc.pause_time;
1651         fc_conf->high_water = hw->fc.high_water;
1652         fc_conf->low_water = hw->fc.low_water;
1653         fc_conf->send_xon = hw->fc.send_xon;
1654         fc_conf->autoneg = hw->mac.autoneg;
1655
1656         /*
1657          * Return rx_pause and tx_pause status according to actual setting of
1658          * the TFCE and RFCE bits in the CTRL register.
1659          */
1660         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1661         if (ctrl & E1000_CTRL_TFCE)
1662                 tx_pause = 1;
1663         else
1664                 tx_pause = 0;
1665
1666         if (ctrl & E1000_CTRL_RFCE)
1667                 rx_pause = 1;
1668         else
1669                 rx_pause = 0;
1670
1671         if (rx_pause && tx_pause)
1672                 fc_conf->mode = RTE_FC_FULL;
1673         else if (rx_pause)
1674                 fc_conf->mode = RTE_FC_RX_PAUSE;
1675         else if (tx_pause)
1676                 fc_conf->mode = RTE_FC_TX_PAUSE;
1677         else
1678                 fc_conf->mode = RTE_FC_NONE;
1679
1680         return 0;
1681 }
1682
1683 static int
1684 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1685 {
1686         struct e1000_hw *hw;
1687         int err;
1688         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1689                 e1000_fc_none,
1690                 e1000_fc_rx_pause,
1691                 e1000_fc_tx_pause,
1692                 e1000_fc_full
1693         };
1694         uint32_t rx_buf_size;
1695         uint32_t max_high_water;
1696         uint32_t rctl;
1697
1698         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699         if (fc_conf->autoneg != hw->mac.autoneg)
1700                 return -ENOTSUP;
1701         rx_buf_size = em_get_rx_buffer_size(hw);
1702         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1703
1704         /* At least reserve one Ethernet frame for watermark */
1705         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1706         if ((fc_conf->high_water > max_high_water) ||
1707             (fc_conf->high_water < fc_conf->low_water)) {
1708                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1709                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1710                 return -EINVAL;
1711         }
1712
1713         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1714         hw->fc.pause_time     = fc_conf->pause_time;
1715         hw->fc.high_water     = fc_conf->high_water;
1716         hw->fc.low_water      = fc_conf->low_water;
1717         hw->fc.send_xon       = fc_conf->send_xon;
1718
1719         err = e1000_setup_link_generic(hw);
1720         if (err == E1000_SUCCESS) {
1721
1722                 /* check if we want to forward MAC frames - driver doesn't have native
1723                  * capability to do that, so we'll write the registers ourselves */
1724
1725                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1726
1727                 /* set or clear MFLCN.PMCF bit depending on configuration */
1728                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1729                         rctl |= E1000_RCTL_PMCF;
1730                 else
1731                         rctl &= ~E1000_RCTL_PMCF;
1732
1733                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1734                 E1000_WRITE_FLUSH(hw);
1735
1736                 return 0;
1737         }
1738
1739         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1740         return -EIO;
1741 }
1742
1743 static int
1744 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1745                 uint32_t index, __rte_unused uint32_t pool)
1746 {
1747         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748
1749         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1750 }
1751
1752 static void
1753 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1754 {
1755         uint8_t addr[ETHER_ADDR_LEN];
1756         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757
1758         memset(addr, 0, sizeof(addr));
1759
1760         e1000_rar_set(hw, addr, index);
1761 }
1762
1763 static int
1764 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1765                             struct ether_addr *addr)
1766 {
1767         eth_em_rar_clear(dev, 0);
1768
1769         return eth_em_rar_set(dev, (void *)addr, 0, 0);
1770 }
1771
1772 static int
1773 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1774 {
1775         struct rte_eth_dev_info dev_info;
1776         struct e1000_hw *hw;
1777         uint32_t frame_size;
1778         uint32_t rctl;
1779
1780         eth_em_infos_get(dev, &dev_info);
1781         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1782
1783         /* check that mtu is within the allowed range */
1784         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1785                 return -EINVAL;
1786
1787         /* refuse mtu that requires the support of scattered packets when this
1788          * feature has not been enabled before. */
1789         if (!dev->data->scattered_rx &&
1790             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1791                 return -EINVAL;
1792
1793         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1794         rctl = E1000_READ_REG(hw, E1000_RCTL);
1795
1796         /* switch to jumbo mode if needed */
1797         if (frame_size > ETHER_MAX_LEN) {
1798                 dev->data->dev_conf.rxmode.offloads |=
1799                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1800                 rctl |= E1000_RCTL_LPE;
1801         } else {
1802                 dev->data->dev_conf.rxmode.offloads &=
1803                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1804                 rctl &= ~E1000_RCTL_LPE;
1805         }
1806         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1807
1808         /* update max frame size */
1809         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1810         return 0;
1811 }
1812
1813 static int
1814 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1815                         struct ether_addr *mc_addr_set,
1816                         uint32_t nb_mc_addr)
1817 {
1818         struct e1000_hw *hw;
1819
1820         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1822         return 0;
1823 }
1824
1825 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1826 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1827 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1828
1829 RTE_INIT(e1000_init_log);
1830 static void
1831 e1000_init_log(void)
1832 {
1833         e1000_logtype_init = rte_log_register("pmd.net.e1000.init");
1834         if (e1000_logtype_init >= 0)
1835                 rte_log_set_level(e1000_logtype_init, RTE_LOG_NOTICE);
1836         e1000_logtype_driver = rte_log_register("pmd.net.e1000.driver");
1837         if (e1000_logtype_driver >= 0)
1838                 rte_log_set_level(e1000_logtype_driver, RTE_LOG_NOTICE);
1839 }