6e97530a0a54e58730b45ed9f59f0bcbd4439a7f
[dpdk.git] / drivers / net / e1000 / em_ethdev.c
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5  *   All rights reserved.
6  *
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  *
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Intel Corporation nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  *
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 #include <sys/queue.h>
35 #include <stdio.h>
36 #include <errno.h>
37 #include <stdint.h>
38 #include <stdarg.h>
39
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
43 #include <rte_log.h>
44 #include <rte_debug.h>
45 #include <rte_pci.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_eal.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
53 #include <rte_dev.h>
54
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
58
59 #define EM_EIAC                 0x000DC
60
61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
62
63
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73                                 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75                                 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78                                 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80                                 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82                                 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
88                                                         void *param);
89
90 static int em_hw_init(struct e1000_hw *hw);
91 static int em_hardware_init(struct e1000_hw *hw);
92 static void em_hw_control_acquire(struct e1000_hw *hw);
93 static void em_hw_control_release(struct e1000_hw *hw);
94 static void em_init_manageability(struct e1000_hw *hw);
95 static void em_release_manageability(struct e1000_hw *hw);
96
97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
98
99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
100                 uint16_t vlan_id, int on);
101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
106
107 /*
108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
109                                         uint16_t vlan_id, int on);
110 */
111
112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static void em_lsc_intr_disable(struct e1000_hw *hw);
115 static void em_rxq_intr_enable(struct e1000_hw *hw);
116 static void em_rxq_intr_disable(struct e1000_hw *hw);
117
118 static int eth_em_led_on(struct rte_eth_dev *dev);
119 static int eth_em_led_off(struct rte_eth_dev *dev);
120
121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
123                 uint32_t index, uint32_t pool);
124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
125
126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
127                                    struct ether_addr *mc_addr_set,
128                                    uint32_t nb_mc_addr);
129
130 #define EM_FC_PAUSE_TIME 0x0680
131 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
133
134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
135
136 /*
137  * The set of PCI devices this driver supports
138  */
139 static const struct rte_pci_id pci_id_em_map[] = {
140
141 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
142 #include "rte_pci_dev_ids.h"
143
144 {0},
145 };
146
147 static const struct eth_dev_ops eth_em_ops = {
148         .dev_configure        = eth_em_configure,
149         .dev_start            = eth_em_start,
150         .dev_stop             = eth_em_stop,
151         .dev_close            = eth_em_close,
152         .promiscuous_enable   = eth_em_promiscuous_enable,
153         .promiscuous_disable  = eth_em_promiscuous_disable,
154         .allmulticast_enable  = eth_em_allmulticast_enable,
155         .allmulticast_disable = eth_em_allmulticast_disable,
156         .link_update          = eth_em_link_update,
157         .stats_get            = eth_em_stats_get,
158         .stats_reset          = eth_em_stats_reset,
159         .dev_infos_get        = eth_em_infos_get,
160         .mtu_set              = eth_em_mtu_set,
161         .vlan_filter_set      = eth_em_vlan_filter_set,
162         .vlan_offload_set     = eth_em_vlan_offload_set,
163         .rx_queue_setup       = eth_em_rx_queue_setup,
164         .rx_queue_release     = eth_em_rx_queue_release,
165         .rx_queue_count       = eth_em_rx_queue_count,
166         .rx_descriptor_done   = eth_em_rx_descriptor_done,
167         .tx_queue_setup       = eth_em_tx_queue_setup,
168         .tx_queue_release     = eth_em_tx_queue_release,
169         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
170         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
171         .dev_led_on           = eth_em_led_on,
172         .dev_led_off          = eth_em_led_off,
173         .flow_ctrl_get        = eth_em_flow_ctrl_get,
174         .flow_ctrl_set        = eth_em_flow_ctrl_set,
175         .mac_addr_add         = eth_em_rar_set,
176         .mac_addr_remove      = eth_em_rar_clear,
177         .set_mc_addr_list     = eth_em_set_mc_addr_list,
178 };
179
180 /**
181  * Atomically reads the link status information from global
182  * structure rte_eth_dev.
183  *
184  * @param dev
185  *   - Pointer to the structure rte_eth_dev to read from.
186  *   - Pointer to the buffer to be saved with the link status.
187  *
188  * @return
189  *   - On success, zero.
190  *   - On failure, negative value.
191  */
192 static inline int
193 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
194                                 struct rte_eth_link *link)
195 {
196         struct rte_eth_link *dst = link;
197         struct rte_eth_link *src = &(dev->data->dev_link);
198
199         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
200                                         *(uint64_t *)src) == 0)
201                 return -1;
202
203         return 0;
204 }
205
206 /**
207  * Atomically writes the link status information into global
208  * structure rte_eth_dev.
209  *
210  * @param dev
211  *   - Pointer to the structure rte_eth_dev to read from.
212  *   - Pointer to the buffer to be saved with the link status.
213  *
214  * @return
215  *   - On success, zero.
216  *   - On failure, negative value.
217  */
218 static inline int
219 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
220                                 struct rte_eth_link *link)
221 {
222         struct rte_eth_link *dst = &(dev->data->dev_link);
223         struct rte_eth_link *src = link;
224
225         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
226                                         *(uint64_t *)src) == 0)
227                 return -1;
228
229         return 0;
230 }
231
232 static int
233 eth_em_dev_init(struct rte_eth_dev *eth_dev)
234 {
235         struct rte_pci_device *pci_dev;
236         struct e1000_adapter *adapter =
237                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
238         struct e1000_hw *hw =
239                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
240         struct e1000_vfta * shadow_vfta =
241                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
242
243         pci_dev = eth_dev->pci_dev;
244         eth_dev->dev_ops = &eth_em_ops;
245         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
246         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
247
248         /* for secondary processes, we don't initialise any further as primary
249          * has already done this work. Only check we don't need a different
250          * RX function */
251         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
252                 if (eth_dev->data->scattered_rx)
253                         eth_dev->rx_pkt_burst =
254                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
255                 return 0;
256         }
257
258         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
259         hw->device_id = pci_dev->id.device_id;
260         adapter->stopped = 0;
261
262         /* For ICH8 support we'll need to map the flash memory BAR */
263
264         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
265                         em_hw_init(hw) != 0) {
266                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
267                         "failed to init HW",
268                         eth_dev->data->port_id, pci_dev->id.vendor_id,
269                         pci_dev->id.device_id);
270                 return -(ENODEV);
271         }
272
273         /* Allocate memory for storing MAC addresses */
274         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
275                         hw->mac.rar_entry_count, 0);
276         if (eth_dev->data->mac_addrs == NULL) {
277                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
278                         "store MAC addresses",
279                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
280                 return -(ENOMEM);
281         }
282
283         /* Copy the permanent MAC address */
284         ether_addr_copy((struct ether_addr *) hw->mac.addr,
285                 eth_dev->data->mac_addrs);
286
287         /* initialize the vfta */
288         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
289
290         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
291                      eth_dev->data->port_id, pci_dev->id.vendor_id,
292                      pci_dev->id.device_id);
293
294         rte_intr_callback_register(&(pci_dev->intr_handle),
295                 eth_em_interrupt_handler, (void *)eth_dev);
296
297         return (0);
298 }
299
300 static int
301 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
302 {
303         struct rte_pci_device *pci_dev;
304         struct e1000_adapter *adapter =
305                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
306
307         PMD_INIT_FUNC_TRACE();
308
309         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
310                 return -EPERM;
311
312         pci_dev = eth_dev->pci_dev;
313
314         if (adapter->stopped == 0)
315                 eth_em_close(eth_dev);
316
317         eth_dev->dev_ops = NULL;
318         eth_dev->rx_pkt_burst = NULL;
319         eth_dev->tx_pkt_burst = NULL;
320
321         rte_free(eth_dev->data->mac_addrs);
322         eth_dev->data->mac_addrs = NULL;
323
324         /* disable uio intr before callback unregister */
325         rte_intr_disable(&(pci_dev->intr_handle));
326         rte_intr_callback_unregister(&(pci_dev->intr_handle),
327                 eth_em_interrupt_handler, (void *)eth_dev);
328
329         return 0;
330 }
331
332 static struct eth_driver rte_em_pmd = {
333         .pci_drv = {
334                 .name = "rte_em_pmd",
335                 .id_table = pci_id_em_map,
336                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
337                         RTE_PCI_DRV_DETACHABLE,
338         },
339         .eth_dev_init = eth_em_dev_init,
340         .eth_dev_uninit = eth_em_dev_uninit,
341         .dev_private_size = sizeof(struct e1000_adapter),
342 };
343
344 static int
345 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
346 {
347         rte_eth_driver_register(&rte_em_pmd);
348         return 0;
349 }
350
351 static int
352 em_hw_init(struct e1000_hw *hw)
353 {
354         int diag;
355
356         diag = hw->mac.ops.init_params(hw);
357         if (diag != 0) {
358                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
359                 return diag;
360         }
361         diag = hw->nvm.ops.init_params(hw);
362         if (diag != 0) {
363                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
364                 return diag;
365         }
366         diag = hw->phy.ops.init_params(hw);
367         if (diag != 0) {
368                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
369                 return diag;
370         }
371         (void) e1000_get_bus_info(hw);
372
373         hw->mac.autoneg = 1;
374         hw->phy.autoneg_wait_to_complete = 0;
375         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
376
377         e1000_init_script_state_82541(hw, TRUE);
378         e1000_set_tbi_compatibility_82543(hw, TRUE);
379
380         /* Copper options */
381         if (hw->phy.media_type == e1000_media_type_copper) {
382                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
383                 hw->phy.disable_polarity_correction = 0;
384                 hw->phy.ms_type = e1000_ms_hw_default;
385         }
386
387         /*
388          * Start from a known state, this is important in reading the nvm
389          * and mac from that.
390          */
391         e1000_reset_hw(hw);
392
393         /* Make sure we have a good EEPROM before we read from it */
394         if (e1000_validate_nvm_checksum(hw) < 0) {
395                 /*
396                  * Some PCI-E parts fail the first check due to
397                  * the link being in sleep state, call it again,
398                  * if it fails a second time its a real issue.
399                  */
400                 diag = e1000_validate_nvm_checksum(hw);
401                 if (diag < 0) {
402                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
403                         goto error;
404                 }
405         }
406
407         /* Read the permanent MAC address out of the EEPROM */
408         diag = e1000_read_mac_addr(hw);
409         if (diag != 0) {
410                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
411                 goto error;
412         }
413
414         /* Now initialize the hardware */
415         diag = em_hardware_init(hw);
416         if (diag != 0) {
417                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
418                 goto error;
419         }
420
421         hw->mac.get_link_status = 1;
422
423         /* Indicate SOL/IDER usage */
424         diag = e1000_check_reset_block(hw);
425         if (diag < 0) {
426                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
427                         "SOL/IDER session");
428         }
429         return (0);
430
431 error:
432         em_hw_control_release(hw);
433         return (diag);
434 }
435
436 static int
437 eth_em_configure(struct rte_eth_dev *dev)
438 {
439         struct e1000_interrupt *intr =
440                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
441
442         PMD_INIT_FUNC_TRACE();
443         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
444         PMD_INIT_FUNC_TRACE();
445
446         return (0);
447 }
448
449 static void
450 em_set_pba(struct e1000_hw *hw)
451 {
452         uint32_t pba;
453
454         /*
455          * Packet Buffer Allocation (PBA)
456          * Writing PBA sets the receive portion of the buffer
457          * the remainder is used for the transmit buffer.
458          * Devices before the 82547 had a Packet Buffer of 64K.
459          * After the 82547 the buffer was reduced to 40K.
460          */
461         switch (hw->mac.type) {
462                 case e1000_82547:
463                 case e1000_82547_rev_2:
464                 /* 82547: Total Packet Buffer is 40K */
465                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
466                         break;
467                 case e1000_82571:
468                 case e1000_82572:
469                 case e1000_80003es2lan:
470                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
471                         break;
472                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
473                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
474                         break;
475                 case e1000_82574:
476                 case e1000_82583:
477                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
478                         break;
479                 case e1000_ich8lan:
480                         pba = E1000_PBA_8K;
481                         break;
482                 case e1000_ich9lan:
483                 case e1000_ich10lan:
484                         pba = E1000_PBA_10K;
485                         break;
486                 case e1000_pchlan:
487                 case e1000_pch2lan:
488                         pba = E1000_PBA_26K;
489                         break;
490                 default:
491                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
492         }
493
494         E1000_WRITE_REG(hw, E1000_PBA, pba);
495 }
496
497 static int
498 eth_em_start(struct rte_eth_dev *dev)
499 {
500         struct e1000_adapter *adapter =
501                 E1000_DEV_PRIVATE(dev->data->dev_private);
502         struct e1000_hw *hw =
503                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
504         int ret, mask;
505
506         PMD_INIT_FUNC_TRACE();
507
508         eth_em_stop(dev);
509
510         e1000_power_up_phy(hw);
511
512         /* Set default PBA value */
513         em_set_pba(hw);
514
515         /* Put the address into the Receive Address Array */
516         e1000_rar_set(hw, hw->mac.addr, 0);
517
518         /*
519          * With the 82571 adapter, RAR[0] may be overwritten
520          * when the other port is reset, we make a duplicate
521          * in RAR[14] for that eventuality, this assures
522          * the interface continues to function.
523          */
524         if (hw->mac.type == e1000_82571) {
525                 e1000_set_laa_state_82571(hw, TRUE);
526                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
527         }
528
529         /* Initialize the hardware */
530         if (em_hardware_init(hw)) {
531                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
532                 return (-EIO);
533         }
534
535         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
536
537         /* Configure for OS presence */
538         em_init_manageability(hw);
539
540         eth_em_tx_init(dev);
541
542         ret = eth_em_rx_init(dev);
543         if (ret) {
544                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
545                 em_dev_clear_queues(dev);
546                 return ret;
547         }
548
549         e1000_clear_hw_cntrs_base_generic(hw);
550
551         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
552                         ETH_VLAN_EXTEND_MASK;
553         eth_em_vlan_offload_set(dev, mask);
554
555         /* Set Interrupt Throttling Rate to maximum allowed value. */
556         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
557
558         /* Setup link speed and duplex */
559         switch (dev->data->dev_conf.link_speed) {
560         case ETH_LINK_SPEED_AUTONEG:
561                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
562                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
563                 else if (dev->data->dev_conf.link_duplex ==
564                                         ETH_LINK_HALF_DUPLEX)
565                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
566                 else if (dev->data->dev_conf.link_duplex ==
567                                         ETH_LINK_FULL_DUPLEX)
568                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
569                 else
570                         goto error_invalid_config;
571                 break;
572         case ETH_LINK_SPEED_10:
573                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
574                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
575                 else if (dev->data->dev_conf.link_duplex ==
576                                         ETH_LINK_HALF_DUPLEX)
577                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
578                 else if (dev->data->dev_conf.link_duplex ==
579                                         ETH_LINK_FULL_DUPLEX)
580                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
581                 else
582                         goto error_invalid_config;
583                 break;
584         case ETH_LINK_SPEED_100:
585                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
586                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
587                 else if (dev->data->dev_conf.link_duplex ==
588                                         ETH_LINK_HALF_DUPLEX)
589                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
590                 else if (dev->data->dev_conf.link_duplex ==
591                                         ETH_LINK_FULL_DUPLEX)
592                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
593                 else
594                         goto error_invalid_config;
595                 break;
596         case ETH_LINK_SPEED_1000:
597                 if ((dev->data->dev_conf.link_duplex ==
598                                 ETH_LINK_AUTONEG_DUPLEX) ||
599                         (dev->data->dev_conf.link_duplex ==
600                                         ETH_LINK_FULL_DUPLEX))
601                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
602                 else
603                         goto error_invalid_config;
604                 break;
605         case ETH_LINK_SPEED_10000:
606         default:
607                 goto error_invalid_config;
608         }
609         e1000_setup_link(hw);
610
611         /* check if lsc interrupt feature is enabled */
612         if (dev->data->dev_conf.intr_conf.lsc != 0) {
613                 ret = eth_em_interrupt_setup(dev);
614                 if (ret) {
615                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
616                         em_dev_clear_queues(dev);
617                         return ret;
618                 }
619         }
620         /* check if rxq interrupt is enabled */
621         if (dev->data->dev_conf.intr_conf.rxq != 0)
622                 eth_em_rxq_interrupt_setup(dev);
623
624         adapter->stopped = 0;
625
626         PMD_INIT_LOG(DEBUG, "<<");
627
628         return (0);
629
630 error_invalid_config:
631         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
632                      dev->data->dev_conf.link_speed,
633                      dev->data->dev_conf.link_duplex, dev->data->port_id);
634         em_dev_clear_queues(dev);
635         return (-EINVAL);
636 }
637
638 /*********************************************************************
639  *
640  *  This routine disables all traffic on the adapter by issuing a
641  *  global reset on the MAC.
642  *
643  **********************************************************************/
644 static void
645 eth_em_stop(struct rte_eth_dev *dev)
646 {
647         struct rte_eth_link link;
648         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
649
650         em_rxq_intr_disable(hw);
651         em_lsc_intr_disable(hw);
652
653         e1000_reset_hw(hw);
654         if (hw->mac.type >= e1000_82544)
655                 E1000_WRITE_REG(hw, E1000_WUC, 0);
656
657         /* Power down the phy. Needed to make the link go down */
658         e1000_power_down_phy(hw);
659
660         em_dev_clear_queues(dev);
661
662         /* clear the recorded link status */
663         memset(&link, 0, sizeof(link));
664         rte_em_dev_atomic_write_link_status(dev, &link);
665 }
666
667 static void
668 eth_em_close(struct rte_eth_dev *dev)
669 {
670         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
671         struct e1000_adapter *adapter =
672                 E1000_DEV_PRIVATE(dev->data->dev_private);
673
674         eth_em_stop(dev);
675         adapter->stopped = 1;
676         em_dev_free_queues(dev);
677         e1000_phy_hw_reset(hw);
678         em_release_manageability(hw);
679         em_hw_control_release(hw);
680 }
681
682 static int
683 em_get_rx_buffer_size(struct e1000_hw *hw)
684 {
685         uint32_t rx_buf_size;
686
687         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
688         return rx_buf_size;
689 }
690
691 /*********************************************************************
692  *
693  *  Initialize the hardware
694  *
695  **********************************************************************/
696 static int
697 em_hardware_init(struct e1000_hw *hw)
698 {
699         uint32_t rx_buf_size;
700         int diag;
701
702         /* Issue a global reset */
703         e1000_reset_hw(hw);
704
705         /* Let the firmware know the OS is in control */
706         em_hw_control_acquire(hw);
707
708         /*
709          * These parameters control the automatic generation (Tx) and
710          * response (Rx) to Ethernet PAUSE frames.
711          * - High water mark should allow for at least two standard size (1518)
712          *   frames to be received after sending an XOFF.
713          * - Low water mark works best when it is very near the high water mark.
714          *   This allows the receiver to restart by sending XON when it has
715          *   drained a bit. Here we use an arbitrary value of 1500 which will
716          *   restart after one full frame is pulled from the buffer. There
717          *   could be several smaller frames in the buffer and if so they will
718          *   not trigger the XON until their total number reduces the buffer
719          *   by 1500.
720          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
721          */
722         rx_buf_size = em_get_rx_buffer_size(hw);
723
724         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
725         hw->fc.low_water = hw->fc.high_water - 1500;
726
727         if (hw->mac.type == e1000_80003es2lan)
728                 hw->fc.pause_time = UINT16_MAX;
729         else
730                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
731
732         hw->fc.send_xon = 1;
733
734         /* Set Flow control, use the tunable location if sane */
735         if (em_fc_setting <= e1000_fc_full)
736                 hw->fc.requested_mode = em_fc_setting;
737         else
738                 hw->fc.requested_mode = e1000_fc_none;
739
740         /* Workaround: no TX flow ctrl for PCH */
741         if (hw->mac.type == e1000_pchlan)
742                 hw->fc.requested_mode = e1000_fc_rx_pause;
743
744         /* Override - settings for PCH2LAN, ya its magic :) */
745         if (hw->mac.type == e1000_pch2lan) {
746                 hw->fc.high_water = 0x5C20;
747                 hw->fc.low_water = 0x5048;
748                 hw->fc.pause_time = 0x0650;
749                 hw->fc.refresh_time = 0x0400;
750         }
751
752         diag = e1000_init_hw(hw);
753         if (diag < 0)
754                 return (diag);
755         e1000_check_for_link(hw);
756         return (0);
757 }
758
759 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
760 static void
761 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
762 {
763         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
764         struct e1000_hw_stats *stats =
765                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
766         int pause_frames;
767
768         if(hw->phy.media_type == e1000_media_type_copper ||
769                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
770                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
771                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
772         }
773
774         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
775         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
776         stats->scc += E1000_READ_REG(hw, E1000_SCC);
777         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
778
779         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
780         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
781         stats->colc += E1000_READ_REG(hw, E1000_COLC);
782         stats->dc += E1000_READ_REG(hw, E1000_DC);
783         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
784         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
785         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
786
787         /*
788          * For watchdog management we need to know if we have been
789          * paused during the last interval, so capture that here.
790          */
791         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
792         stats->xoffrxc += pause_frames;
793         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
794         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
795         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
796         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
797         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
798         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
799         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
800         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
801         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
802         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
803         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
804         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
805
806         /*
807          * For the 64-bit byte counters the low dword must be read first.
808          * Both registers clear on the read of the high dword.
809          */
810
811         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
812         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
813         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
814         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
815
816         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
817         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
818         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
819         stats->roc += E1000_READ_REG(hw, E1000_ROC);
820         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
821
822         stats->tor += E1000_READ_REG(hw, E1000_TORH);
823         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
824
825         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
826         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
827         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
828         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
829         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
830         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
831         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
832         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
833         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
834         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
835
836         /* Interrupt Counts */
837
838         if (hw->mac.type >= e1000_82571) {
839                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
840                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
841                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
842                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
843                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
844                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
845                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
846                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
847                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
848         }
849
850         if (hw->mac.type >= e1000_82543) {
851                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
852                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
853                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
854                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
855                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
856                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
857         }
858
859         if (rte_stats == NULL)
860                 return;
861
862         /* Rx Errors */
863         rte_stats->ibadcrc = stats->crcerrs;
864         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
865         rte_stats->imissed = stats->mpc;
866         rte_stats->ierrors = rte_stats->ibadcrc +
867                              rte_stats->ibadlen +
868                              rte_stats->imissed +
869                              stats->rxerrc + stats->algnerrc + stats->cexterr;
870
871         /* Tx Errors */
872         rte_stats->oerrors = stats->ecol + stats->latecol;
873
874         rte_stats->ipackets = stats->gprc;
875         rte_stats->opackets = stats->gptc;
876         rte_stats->ibytes   = stats->gorc;
877         rte_stats->obytes   = stats->gotc;
878
879         /* XON/XOFF pause frames stats registers */
880         rte_stats->tx_pause_xon  = stats->xontxc;
881         rte_stats->rx_pause_xon  = stats->xonrxc;
882         rte_stats->tx_pause_xoff = stats->xofftxc;
883         rte_stats->rx_pause_xoff = stats->xoffrxc;
884 }
885
886 static void
887 eth_em_stats_reset(struct rte_eth_dev *dev)
888 {
889         struct e1000_hw_stats *hw_stats =
890                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
891
892         /* HW registers are cleared on read */
893         eth_em_stats_get(dev, NULL);
894
895         /* Reset software totals */
896         memset(hw_stats, 0, sizeof(*hw_stats));
897 }
898
899 static int
900 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
901 {
902         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
903
904         em_rxq_intr_enable(hw);
905         rte_intr_enable(&dev->pci_dev->intr_handle);
906
907         return 0;
908 }
909
910 static int
911 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
912 {
913         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
914
915         em_rxq_intr_disable(hw);
916
917         return 0;
918 }
919
920 static uint32_t
921 em_get_max_pktlen(const struct e1000_hw *hw)
922 {
923         switch (hw->mac.type) {
924         case e1000_82571:
925         case e1000_82572:
926         case e1000_ich9lan:
927         case e1000_ich10lan:
928         case e1000_pch2lan:
929         case e1000_82574:
930         case e1000_80003es2lan: /* 9K Jumbo Frame size */
931         case e1000_82583:
932                 return (0x2412);
933         case e1000_pchlan:
934                 return (0x1000);
935         /* Adapters that do not support jumbo frames */
936         case e1000_ich8lan:
937                 return (ETHER_MAX_LEN);
938         default:
939                 return (MAX_JUMBO_FRAME_SIZE);
940         }
941 }
942
943 static void
944 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
945 {
946         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
947
948         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
949         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
950         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
951
952         /*
953          * Starting with 631xESB hw supports 2 TX/RX queues per port.
954          * Unfortunatelly, all these nics have just one TX context.
955          * So we have few choises for TX:
956          * - Use just one TX queue.
957          * - Allow cksum offload only for one TX queue.
958          * - Don't allow TX cksum offload at all.
959          * For now, option #1 was chosen.
960          * To use second RX queue we have to use extended RX descriptor
961          * (Multiple Receive Queues are mutually exclusive with UDP
962          * fragmentation and are not supported when a legacy receive
963          * descriptor format is used).
964          * Which means separate RX routinies - as legacy nics (82540, 82545)
965          * don't support extended RXD.
966          * To avoid it we support just one RX queue for now (no RSS).
967          */
968
969         dev_info->max_rx_queues = 1;
970         dev_info->max_tx_queues = 1;
971 }
972
973 /* return 0 means link status changed, -1 means not changed */
974 static int
975 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
976 {
977         struct e1000_hw *hw =
978                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
979         struct rte_eth_link link, old;
980         int link_check, count;
981
982         link_check = 0;
983         hw->mac.get_link_status = 1;
984
985         /* possible wait-to-complete in up to 9 seconds */
986         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
987                 /* Read the real link status */
988                 switch (hw->phy.media_type) {
989                 case e1000_media_type_copper:
990                         /* Do the work to read phy */
991                         e1000_check_for_link(hw);
992                         link_check = !hw->mac.get_link_status;
993                         break;
994
995                 case e1000_media_type_fiber:
996                         e1000_check_for_link(hw);
997                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
998                                         E1000_STATUS_LU);
999                         break;
1000
1001                 case e1000_media_type_internal_serdes:
1002                         e1000_check_for_link(hw);
1003                         link_check = hw->mac.serdes_has_link;
1004                         break;
1005
1006                 default:
1007                         break;
1008                 }
1009                 if (link_check || wait_to_complete == 0)
1010                         break;
1011                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1012         }
1013         memset(&link, 0, sizeof(link));
1014         rte_em_dev_atomic_read_link_status(dev, &link);
1015         old = link;
1016
1017         /* Now we check if a transition has happened */
1018         if (link_check && (link.link_status == 0)) {
1019                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1020                         &link.link_duplex);
1021                 link.link_status = 1;
1022         } else if (!link_check && (link.link_status == 1)) {
1023                 link.link_speed = 0;
1024                 link.link_duplex = 0;
1025                 link.link_status = 0;
1026         }
1027         rte_em_dev_atomic_write_link_status(dev, &link);
1028
1029         /* not changed */
1030         if (old.link_status == link.link_status)
1031                 return -1;
1032
1033         /* changed */
1034         return 0;
1035 }
1036
1037 /*
1038  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1039  * For ASF and Pass Through versions of f/w this means
1040  * that the driver is loaded. For AMT version type f/w
1041  * this means that the network i/f is open.
1042  */
1043 static void
1044 em_hw_control_acquire(struct e1000_hw *hw)
1045 {
1046         uint32_t ctrl_ext, swsm;
1047
1048         /* Let firmware know the driver has taken over */
1049         if (hw->mac.type == e1000_82573) {
1050                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1051                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1052
1053         } else {
1054                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1055                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1056                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1057         }
1058 }
1059
1060 /*
1061  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1062  * For ASF and Pass Through versions of f/w this means that the
1063  * driver is no longer loaded. For AMT versions of the
1064  * f/w this means that the network i/f is closed.
1065  */
1066 static void
1067 em_hw_control_release(struct e1000_hw *hw)
1068 {
1069         uint32_t ctrl_ext, swsm;
1070
1071         /* Let firmware taken over control of h/w */
1072         if (hw->mac.type == e1000_82573) {
1073                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1074                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1075         } else {
1076                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1077                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1078                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1079         }
1080 }
1081
1082 /*
1083  * Bit of a misnomer, what this really means is
1084  * to enable OS management of the system... aka
1085  * to disable special hardware management features.
1086  */
1087 static void
1088 em_init_manageability(struct e1000_hw *hw)
1089 {
1090         if (e1000_enable_mng_pass_thru(hw)) {
1091                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1092                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1093
1094                 /* disable hardware interception of ARP */
1095                 manc &= ~(E1000_MANC_ARP_EN);
1096
1097                 /* enable receiving management packets to the host */
1098                 manc |= E1000_MANC_EN_MNG2HOST;
1099                 manc2h |= 1 << 5;  /* Mng Port 623 */
1100                 manc2h |= 1 << 6;  /* Mng Port 664 */
1101                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1102                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1103         }
1104 }
1105
1106 /*
1107  * Give control back to hardware management
1108  * controller if there is one.
1109  */
1110 static void
1111 em_release_manageability(struct e1000_hw *hw)
1112 {
1113         uint32_t manc;
1114
1115         if (e1000_enable_mng_pass_thru(hw)) {
1116                 manc = E1000_READ_REG(hw, E1000_MANC);
1117
1118                 /* re-enable hardware interception of ARP */
1119                 manc |= E1000_MANC_ARP_EN;
1120                 manc &= ~E1000_MANC_EN_MNG2HOST;
1121
1122                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1123         }
1124 }
1125
1126 static void
1127 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1128 {
1129         struct e1000_hw *hw =
1130                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1131         uint32_t rctl;
1132
1133         rctl = E1000_READ_REG(hw, E1000_RCTL);
1134         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1135         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1136 }
1137
1138 static void
1139 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1140 {
1141         struct e1000_hw *hw =
1142                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1143         uint32_t rctl;
1144
1145         rctl = E1000_READ_REG(hw, E1000_RCTL);
1146         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1147         if (dev->data->all_multicast == 1)
1148                 rctl |= E1000_RCTL_MPE;
1149         else
1150                 rctl &= (~E1000_RCTL_MPE);
1151         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1152 }
1153
1154 static void
1155 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1156 {
1157         struct e1000_hw *hw =
1158                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1159         uint32_t rctl;
1160
1161         rctl = E1000_READ_REG(hw, E1000_RCTL);
1162         rctl |= E1000_RCTL_MPE;
1163         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1164 }
1165
1166 static void
1167 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1168 {
1169         struct e1000_hw *hw =
1170                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1171         uint32_t rctl;
1172
1173         if (dev->data->promiscuous == 1)
1174                 return; /* must remain in all_multicast mode */
1175         rctl = E1000_READ_REG(hw, E1000_RCTL);
1176         rctl &= (~E1000_RCTL_MPE);
1177         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1178 }
1179
1180 static int
1181 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1182 {
1183         struct e1000_hw *hw =
1184                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1185         struct e1000_vfta * shadow_vfta =
1186                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1187         uint32_t vfta;
1188         uint32_t vid_idx;
1189         uint32_t vid_bit;
1190
1191         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1192                               E1000_VFTA_ENTRY_MASK);
1193         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1194         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1195         if (on)
1196                 vfta |= vid_bit;
1197         else
1198                 vfta &= ~vid_bit;
1199         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1200
1201         /* update local VFTA copy */
1202         shadow_vfta->vfta[vid_idx] = vfta;
1203
1204         return 0;
1205 }
1206
1207 static void
1208 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1209 {
1210         struct e1000_hw *hw =
1211                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212         uint32_t reg;
1213
1214         /* Filter Table Disable */
1215         reg = E1000_READ_REG(hw, E1000_RCTL);
1216         reg &= ~E1000_RCTL_CFIEN;
1217         reg &= ~E1000_RCTL_VFE;
1218         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1219 }
1220
1221 static void
1222 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1223 {
1224         struct e1000_hw *hw =
1225                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1226         struct e1000_vfta * shadow_vfta =
1227                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1228         uint32_t reg;
1229         int i;
1230
1231         /* Filter Table Enable, CFI not used for packet acceptance */
1232         reg = E1000_READ_REG(hw, E1000_RCTL);
1233         reg &= ~E1000_RCTL_CFIEN;
1234         reg |= E1000_RCTL_VFE;
1235         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1236
1237         /* restore vfta from local copy */
1238         for (i = 0; i < IGB_VFTA_SIZE; i++)
1239                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1240 }
1241
1242 static void
1243 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1244 {
1245         struct e1000_hw *hw =
1246                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247         uint32_t reg;
1248
1249         /* VLAN Mode Disable */
1250         reg = E1000_READ_REG(hw, E1000_CTRL);
1251         reg &= ~E1000_CTRL_VME;
1252         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1253
1254 }
1255
1256 static void
1257 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1258 {
1259         struct e1000_hw *hw =
1260                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1261         uint32_t reg;
1262
1263         /* VLAN Mode Enable */
1264         reg = E1000_READ_REG(hw, E1000_CTRL);
1265         reg |= E1000_CTRL_VME;
1266         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1267 }
1268
1269 static void
1270 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1271 {
1272         if(mask & ETH_VLAN_STRIP_MASK){
1273                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1274                         em_vlan_hw_strip_enable(dev);
1275                 else
1276                         em_vlan_hw_strip_disable(dev);
1277         }
1278
1279         if(mask & ETH_VLAN_FILTER_MASK){
1280                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1281                         em_vlan_hw_filter_enable(dev);
1282                 else
1283                         em_vlan_hw_filter_disable(dev);
1284         }
1285 }
1286
1287 /*
1288  * It enables the interrupt mask and then enable the interrupt.
1289  *
1290  * @param dev
1291  *  Pointer to struct rte_eth_dev.
1292  *
1293  * @return
1294  *  - On success, zero.
1295  *  - On failure, a negative value.
1296  */
1297 static int
1298 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1299 {
1300         uint32_t regval;
1301         struct e1000_hw *hw =
1302                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1303
1304         /* clear interrupt */
1305         E1000_READ_REG(hw, E1000_ICR);
1306         regval = E1000_READ_REG(hw, E1000_IMS);
1307         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1308         return (0);
1309 }
1310
1311 /*
1312  * It clears the interrupt causes and enables the interrupt.
1313  * It will be called once only during nic initialized.
1314  *
1315  * @param dev
1316  *  Pointer to struct rte_eth_dev.
1317  *
1318  * @return
1319  *  - On success, zero.
1320  *  - On failure, a negative value.
1321  */
1322 static int
1323 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1324 {
1325         struct e1000_hw *hw =
1326         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327
1328         E1000_READ_REG(hw, E1000_ICR);
1329         em_rxq_intr_enable(hw);
1330         return 0;
1331 }
1332
1333 /*
1334  * It enable receive packet interrupt.
1335  * @param hw
1336  * Pointer to struct e1000_hw
1337  *
1338  * @return
1339  */
1340 static void
1341 em_rxq_intr_enable(struct e1000_hw *hw)
1342 {
1343         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1344         E1000_WRITE_FLUSH(hw);
1345 }
1346
1347 /*
1348  * It disabled lsc interrupt.
1349  * @param hw
1350  * Pointer to struct e1000_hw
1351  *
1352  * @return
1353  */
1354 static void
1355 em_lsc_intr_disable(struct e1000_hw *hw)
1356 {
1357         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1358         E1000_WRITE_FLUSH(hw);
1359 }
1360
1361 /*
1362  * It disabled receive packet interrupt.
1363  * @param hw
1364  * Pointer to struct e1000_hw
1365  *
1366  * @return
1367  */
1368 static void
1369 em_rxq_intr_disable(struct e1000_hw *hw)
1370 {
1371         E1000_READ_REG(hw, E1000_ICR);
1372         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1373         E1000_WRITE_FLUSH(hw);
1374 }
1375
1376 /*
1377  * It reads ICR and gets interrupt causes, check it and set a bit flag
1378  * to update link status.
1379  *
1380  * @param dev
1381  *  Pointer to struct rte_eth_dev.
1382  *
1383  * @return
1384  *  - On success, zero.
1385  *  - On failure, a negative value.
1386  */
1387 static int
1388 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1389 {
1390         uint32_t icr;
1391         struct e1000_hw *hw =
1392                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1393         struct e1000_interrupt *intr =
1394                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1395
1396         /* read-on-clear nic registers here */
1397         icr = E1000_READ_REG(hw, E1000_ICR);
1398         if (icr & E1000_ICR_LSC) {
1399                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1400         }
1401
1402         return 0;
1403 }
1404
1405 /*
1406  * It executes link_update after knowing an interrupt is prsent.
1407  *
1408  * @param dev
1409  *  Pointer to struct rte_eth_dev.
1410  *
1411  * @return
1412  *  - On success, zero.
1413  *  - On failure, a negative value.
1414  */
1415 static int
1416 eth_em_interrupt_action(struct rte_eth_dev *dev)
1417 {
1418         struct e1000_hw *hw =
1419                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1420         struct e1000_interrupt *intr =
1421                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1422         uint32_t tctl, rctl;
1423         struct rte_eth_link link;
1424         int ret;
1425
1426         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1427                 return -1;
1428
1429         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1430         rte_intr_enable(&(dev->pci_dev->intr_handle));
1431
1432         /* set get_link_status to check register later */
1433         hw->mac.get_link_status = 1;
1434         ret = eth_em_link_update(dev, 0);
1435
1436         /* check if link has changed */
1437         if (ret < 0)
1438                 return 0;
1439
1440         memset(&link, 0, sizeof(link));
1441         rte_em_dev_atomic_read_link_status(dev, &link);
1442         if (link.link_status) {
1443                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1444                              dev->data->port_id, (unsigned)link.link_speed,
1445                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1446                              "full-duplex" : "half-duplex");
1447         } else {
1448                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1449         }
1450         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1451                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1452                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1453
1454         tctl = E1000_READ_REG(hw, E1000_TCTL);
1455         rctl = E1000_READ_REG(hw, E1000_RCTL);
1456         if (link.link_status) {
1457                 /* enable Tx/Rx */
1458                 tctl |= E1000_TCTL_EN;
1459                 rctl |= E1000_RCTL_EN;
1460         } else {
1461                 /* disable Tx/Rx */
1462                 tctl &= ~E1000_TCTL_EN;
1463                 rctl &= ~E1000_RCTL_EN;
1464         }
1465         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1466         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1467         E1000_WRITE_FLUSH(hw);
1468
1469         return 0;
1470 }
1471
1472 /**
1473  * Interrupt handler which shall be registered at first.
1474  *
1475  * @param handle
1476  *  Pointer to interrupt handle.
1477  * @param param
1478  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1479  *
1480  * @return
1481  *  void
1482  */
1483 static void
1484 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1485                                                         void *param)
1486 {
1487         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1488
1489         eth_em_interrupt_get_status(dev);
1490         eth_em_interrupt_action(dev);
1491         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1492 }
1493
1494 static int
1495 eth_em_led_on(struct rte_eth_dev *dev)
1496 {
1497         struct e1000_hw *hw;
1498
1499         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1500         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1501 }
1502
1503 static int
1504 eth_em_led_off(struct rte_eth_dev *dev)
1505 {
1506         struct e1000_hw *hw;
1507
1508         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1509         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1510 }
1511
1512 static int
1513 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1514 {
1515         struct e1000_hw *hw;
1516         uint32_t ctrl;
1517         int tx_pause;
1518         int rx_pause;
1519
1520         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521         fc_conf->pause_time = hw->fc.pause_time;
1522         fc_conf->high_water = hw->fc.high_water;
1523         fc_conf->low_water = hw->fc.low_water;
1524         fc_conf->send_xon = hw->fc.send_xon;
1525         fc_conf->autoneg = hw->mac.autoneg;
1526
1527         /*
1528          * Return rx_pause and tx_pause status according to actual setting of
1529          * the TFCE and RFCE bits in the CTRL register.
1530          */
1531         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1532         if (ctrl & E1000_CTRL_TFCE)
1533                 tx_pause = 1;
1534         else
1535                 tx_pause = 0;
1536
1537         if (ctrl & E1000_CTRL_RFCE)
1538                 rx_pause = 1;
1539         else
1540                 rx_pause = 0;
1541
1542         if (rx_pause && tx_pause)
1543                 fc_conf->mode = RTE_FC_FULL;
1544         else if (rx_pause)
1545                 fc_conf->mode = RTE_FC_RX_PAUSE;
1546         else if (tx_pause)
1547                 fc_conf->mode = RTE_FC_TX_PAUSE;
1548         else
1549                 fc_conf->mode = RTE_FC_NONE;
1550
1551         return 0;
1552 }
1553
1554 static int
1555 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1556 {
1557         struct e1000_hw *hw;
1558         int err;
1559         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1560                 e1000_fc_none,
1561                 e1000_fc_rx_pause,
1562                 e1000_fc_tx_pause,
1563                 e1000_fc_full
1564         };
1565         uint32_t rx_buf_size;
1566         uint32_t max_high_water;
1567         uint32_t rctl;
1568
1569         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570         if (fc_conf->autoneg != hw->mac.autoneg)
1571                 return -ENOTSUP;
1572         rx_buf_size = em_get_rx_buffer_size(hw);
1573         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1574
1575         /* At least reserve one Ethernet frame for watermark */
1576         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1577         if ((fc_conf->high_water > max_high_water) ||
1578             (fc_conf->high_water < fc_conf->low_water)) {
1579                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1580                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1581                 return (-EINVAL);
1582         }
1583
1584         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1585         hw->fc.pause_time     = fc_conf->pause_time;
1586         hw->fc.high_water     = fc_conf->high_water;
1587         hw->fc.low_water      = fc_conf->low_water;
1588         hw->fc.send_xon       = fc_conf->send_xon;
1589
1590         err = e1000_setup_link_generic(hw);
1591         if (err == E1000_SUCCESS) {
1592
1593                 /* check if we want to forward MAC frames - driver doesn't have native
1594                  * capability to do that, so we'll write the registers ourselves */
1595
1596                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1597
1598                 /* set or clear MFLCN.PMCF bit depending on configuration */
1599                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1600                         rctl |= E1000_RCTL_PMCF;
1601                 else
1602                         rctl &= ~E1000_RCTL_PMCF;
1603
1604                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1605                 E1000_WRITE_FLUSH(hw);
1606
1607                 return 0;
1608         }
1609
1610         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1611         return (-EIO);
1612 }
1613
1614 static void
1615 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1616                 uint32_t index, __rte_unused uint32_t pool)
1617 {
1618         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619
1620         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1621 }
1622
1623 static void
1624 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1625 {
1626         uint8_t addr[ETHER_ADDR_LEN];
1627         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628
1629         memset(addr, 0, sizeof(addr));
1630
1631         e1000_rar_set(hw, addr, index);
1632 }
1633
1634 static int
1635 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1636 {
1637         struct rte_eth_dev_info dev_info;
1638         struct e1000_hw *hw;
1639         uint32_t frame_size;
1640         uint32_t rctl;
1641
1642         eth_em_infos_get(dev, &dev_info);
1643         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1644
1645         /* check that mtu is within the allowed range */
1646         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1647                 return -EINVAL;
1648
1649         /* refuse mtu that requires the support of scattered packets when this
1650          * feature has not been enabled before. */
1651         if (!dev->data->scattered_rx &&
1652             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1653                 return -EINVAL;
1654
1655         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656         rctl = E1000_READ_REG(hw, E1000_RCTL);
1657
1658         /* switch to jumbo mode if needed */
1659         if (frame_size > ETHER_MAX_LEN) {
1660                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1661                 rctl |= E1000_RCTL_LPE;
1662         } else {
1663                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1664                 rctl &= ~E1000_RCTL_LPE;
1665         }
1666         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1667
1668         /* update max frame size */
1669         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1670         return 0;
1671 }
1672
1673 static int
1674 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1675                         struct ether_addr *mc_addr_set,
1676                         uint32_t nb_mc_addr)
1677 {
1678         struct e1000_hw *hw;
1679
1680         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1682         return 0;
1683 }
1684
1685 struct rte_driver em_pmd_drv = {
1686         .type = PMD_PDEV,
1687         .init = rte_em_pmd_init,
1688 };
1689
1690 PMD_REGISTER_DRIVER(em_pmd_drv);