4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
59 #define EM_EIAC 0x000DC
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
87 struct rte_intr_handle *handle);
88 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
91 static int em_hw_init(struct e1000_hw *hw);
92 static int em_hardware_init(struct e1000_hw *hw);
93 static void em_hw_control_acquire(struct e1000_hw *hw);
94 static void em_hw_control_release(struct e1000_hw *hw);
95 static void em_init_manageability(struct e1000_hw *hw);
96 static void em_release_manageability(struct e1000_hw *hw);
98 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
100 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
101 uint16_t vlan_id, int on);
102 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
103 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
106 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
109 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
110 uint16_t vlan_id, int on);
113 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
115 static void em_lsc_intr_disable(struct e1000_hw *hw);
116 static void em_rxq_intr_enable(struct e1000_hw *hw);
117 static void em_rxq_intr_disable(struct e1000_hw *hw);
119 static int eth_em_led_on(struct rte_eth_dev *dev);
120 static int eth_em_led_off(struct rte_eth_dev *dev);
122 static int em_get_rx_buffer_size(struct e1000_hw *hw);
123 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
124 uint32_t index, uint32_t pool);
125 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
127 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
128 struct ether_addr *mc_addr_set,
129 uint32_t nb_mc_addr);
131 #define EM_FC_PAUSE_TIME 0x0680
132 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
133 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
135 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
138 * The set of PCI devices this driver supports
140 static const struct rte_pci_id pci_id_em_map[] = {
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
160 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
161 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
162 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
163 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
164 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
165 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
166 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
167 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
168 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
169 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
170 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
171 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
172 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
173 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
174 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
175 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
176 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
177 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
178 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
179 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
180 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
181 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
182 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
183 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
184 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
185 { .vendor_id = 0, /* sentinel */ },
188 static const struct eth_dev_ops eth_em_ops = {
189 .dev_configure = eth_em_configure,
190 .dev_start = eth_em_start,
191 .dev_stop = eth_em_stop,
192 .dev_close = eth_em_close,
193 .promiscuous_enable = eth_em_promiscuous_enable,
194 .promiscuous_disable = eth_em_promiscuous_disable,
195 .allmulticast_enable = eth_em_allmulticast_enable,
196 .allmulticast_disable = eth_em_allmulticast_disable,
197 .link_update = eth_em_link_update,
198 .stats_get = eth_em_stats_get,
199 .stats_reset = eth_em_stats_reset,
200 .dev_infos_get = eth_em_infos_get,
201 .mtu_set = eth_em_mtu_set,
202 .vlan_filter_set = eth_em_vlan_filter_set,
203 .vlan_offload_set = eth_em_vlan_offload_set,
204 .rx_queue_setup = eth_em_rx_queue_setup,
205 .rx_queue_release = eth_em_rx_queue_release,
206 .rx_queue_count = eth_em_rx_queue_count,
207 .rx_descriptor_done = eth_em_rx_descriptor_done,
208 .rx_descriptor_status = eth_em_rx_descriptor_status,
209 .tx_descriptor_status = eth_em_tx_descriptor_status,
210 .tx_queue_setup = eth_em_tx_queue_setup,
211 .tx_queue_release = eth_em_tx_queue_release,
212 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
213 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
214 .dev_led_on = eth_em_led_on,
215 .dev_led_off = eth_em_led_off,
216 .flow_ctrl_get = eth_em_flow_ctrl_get,
217 .flow_ctrl_set = eth_em_flow_ctrl_set,
218 .mac_addr_add = eth_em_rar_set,
219 .mac_addr_remove = eth_em_rar_clear,
220 .set_mc_addr_list = eth_em_set_mc_addr_list,
221 .rxq_info_get = em_rxq_info_get,
222 .txq_info_get = em_txq_info_get,
226 * Atomically reads the link status information from global
227 * structure rte_eth_dev.
230 * - Pointer to the structure rte_eth_dev to read from.
231 * - Pointer to the buffer to be saved with the link status.
234 * - On success, zero.
235 * - On failure, negative value.
238 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
239 struct rte_eth_link *link)
241 struct rte_eth_link *dst = link;
242 struct rte_eth_link *src = &(dev->data->dev_link);
244 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
245 *(uint64_t *)src) == 0)
252 * Atomically writes the link status information into global
253 * structure rte_eth_dev.
256 * - Pointer to the structure rte_eth_dev to read from.
257 * - Pointer to the buffer to be saved with the link status.
260 * - On success, zero.
261 * - On failure, negative value.
264 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
265 struct rte_eth_link *link)
267 struct rte_eth_link *dst = &(dev->data->dev_link);
268 struct rte_eth_link *src = link;
270 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
271 *(uint64_t *)src) == 0)
278 * eth_em_dev_is_ich8 - Check for ICH8 device
279 * @hw: pointer to the HW structure
281 * return TRUE for ICH8, otherwise FALSE
284 eth_em_dev_is_ich8(struct e1000_hw *hw)
286 DEBUGFUNC("eth_em_dev_is_ich8");
288 switch (hw->device_id) {
289 case E1000_DEV_ID_PCH_LPT_I217_LM:
290 case E1000_DEV_ID_PCH_LPT_I217_V:
291 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
292 case E1000_DEV_ID_PCH_LPTLP_I218_V:
293 case E1000_DEV_ID_PCH_I218_V2:
294 case E1000_DEV_ID_PCH_I218_LM2:
295 case E1000_DEV_ID_PCH_I218_V3:
296 case E1000_DEV_ID_PCH_I218_LM3:
297 case E1000_DEV_ID_PCH_SPT_I219_LM:
298 case E1000_DEV_ID_PCH_SPT_I219_V:
299 case E1000_DEV_ID_PCH_SPT_I219_LM2:
300 case E1000_DEV_ID_PCH_SPT_I219_V2:
301 case E1000_DEV_ID_PCH_LBG_I219_LM3:
302 case E1000_DEV_ID_PCH_SPT_I219_LM4:
303 case E1000_DEV_ID_PCH_SPT_I219_V4:
304 case E1000_DEV_ID_PCH_SPT_I219_LM5:
305 case E1000_DEV_ID_PCH_SPT_I219_V5:
306 case E1000_DEV_ID_PCH_CNP_I219_LM6:
307 case E1000_DEV_ID_PCH_CNP_I219_V6:
308 case E1000_DEV_ID_PCH_CNP_I219_LM7:
309 case E1000_DEV_ID_PCH_CNP_I219_V7:
317 eth_em_dev_init(struct rte_eth_dev *eth_dev)
319 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
320 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
321 struct e1000_adapter *adapter =
322 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
323 struct e1000_hw *hw =
324 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
325 struct e1000_vfta * shadow_vfta =
326 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
328 eth_dev->dev_ops = ð_em_ops;
329 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
330 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
331 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
333 /* for secondary processes, we don't initialise any further as primary
334 * has already done this work. Only check we don't need a different
336 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
337 if (eth_dev->data->scattered_rx)
338 eth_dev->rx_pkt_burst =
339 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
343 rte_eth_copy_pci_info(eth_dev, pci_dev);
344 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
346 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
347 hw->device_id = pci_dev->id.device_id;
348 adapter->stopped = 0;
350 /* For ICH8 support we'll need to map the flash memory BAR */
351 if (eth_em_dev_is_ich8(hw))
352 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
354 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
355 em_hw_init(hw) != 0) {
356 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
358 eth_dev->data->port_id, pci_dev->id.vendor_id,
359 pci_dev->id.device_id);
363 /* Allocate memory for storing MAC addresses */
364 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
365 hw->mac.rar_entry_count, 0);
366 if (eth_dev->data->mac_addrs == NULL) {
367 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
368 "store MAC addresses",
369 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
373 /* Copy the permanent MAC address */
374 ether_addr_copy((struct ether_addr *) hw->mac.addr,
375 eth_dev->data->mac_addrs);
377 /* initialize the vfta */
378 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
380 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
381 eth_dev->data->port_id, pci_dev->id.vendor_id,
382 pci_dev->id.device_id);
384 rte_intr_callback_register(intr_handle,
385 eth_em_interrupt_handler, eth_dev);
391 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
393 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
394 struct e1000_adapter *adapter =
395 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
396 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
398 PMD_INIT_FUNC_TRACE();
400 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
403 if (adapter->stopped == 0)
404 eth_em_close(eth_dev);
406 eth_dev->dev_ops = NULL;
407 eth_dev->rx_pkt_burst = NULL;
408 eth_dev->tx_pkt_burst = NULL;
410 rte_free(eth_dev->data->mac_addrs);
411 eth_dev->data->mac_addrs = NULL;
413 /* disable uio intr before callback unregister */
414 rte_intr_disable(intr_handle);
415 rte_intr_callback_unregister(intr_handle,
416 eth_em_interrupt_handler, eth_dev);
421 static struct eth_driver rte_em_pmd = {
423 .id_table = pci_id_em_map,
424 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
425 .probe = rte_eth_dev_pci_probe,
426 .remove = rte_eth_dev_pci_remove,
428 .eth_dev_init = eth_em_dev_init,
429 .eth_dev_uninit = eth_em_dev_uninit,
430 .dev_private_size = sizeof(struct e1000_adapter),
434 em_hw_init(struct e1000_hw *hw)
438 diag = hw->mac.ops.init_params(hw);
440 PMD_INIT_LOG(ERR, "MAC Initialization Error");
443 diag = hw->nvm.ops.init_params(hw);
445 PMD_INIT_LOG(ERR, "NVM Initialization Error");
448 diag = hw->phy.ops.init_params(hw);
450 PMD_INIT_LOG(ERR, "PHY Initialization Error");
453 (void) e1000_get_bus_info(hw);
456 hw->phy.autoneg_wait_to_complete = 0;
457 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
459 e1000_init_script_state_82541(hw, TRUE);
460 e1000_set_tbi_compatibility_82543(hw, TRUE);
463 if (hw->phy.media_type == e1000_media_type_copper) {
464 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
465 hw->phy.disable_polarity_correction = 0;
466 hw->phy.ms_type = e1000_ms_hw_default;
470 * Start from a known state, this is important in reading the nvm
475 /* Make sure we have a good EEPROM before we read from it */
476 if (e1000_validate_nvm_checksum(hw) < 0) {
478 * Some PCI-E parts fail the first check due to
479 * the link being in sleep state, call it again,
480 * if it fails a second time its a real issue.
482 diag = e1000_validate_nvm_checksum(hw);
484 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
489 /* Read the permanent MAC address out of the EEPROM */
490 diag = e1000_read_mac_addr(hw);
492 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
496 /* Now initialize the hardware */
497 diag = em_hardware_init(hw);
499 PMD_INIT_LOG(ERR, "Hardware initialization failed");
503 hw->mac.get_link_status = 1;
505 /* Indicate SOL/IDER usage */
506 diag = e1000_check_reset_block(hw);
508 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
514 em_hw_control_release(hw);
519 eth_em_configure(struct rte_eth_dev *dev)
521 struct e1000_interrupt *intr =
522 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
524 PMD_INIT_FUNC_TRACE();
525 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
526 PMD_INIT_FUNC_TRACE();
532 em_set_pba(struct e1000_hw *hw)
537 * Packet Buffer Allocation (PBA)
538 * Writing PBA sets the receive portion of the buffer
539 * the remainder is used for the transmit buffer.
540 * Devices before the 82547 had a Packet Buffer of 64K.
541 * After the 82547 the buffer was reduced to 40K.
543 switch (hw->mac.type) {
545 case e1000_82547_rev_2:
546 /* 82547: Total Packet Buffer is 40K */
547 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
551 case e1000_80003es2lan:
552 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
554 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
555 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
559 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
576 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
579 E1000_WRITE_REG(hw, E1000_PBA, pba);
583 eth_em_start(struct rte_eth_dev *dev)
585 struct e1000_adapter *adapter =
586 E1000_DEV_PRIVATE(dev->data->dev_private);
587 struct e1000_hw *hw =
588 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
589 struct rte_pci_device *pci_dev =
590 E1000_DEV_TO_PCI(dev);
591 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
593 uint32_t intr_vector = 0;
598 PMD_INIT_FUNC_TRACE();
602 e1000_power_up_phy(hw);
604 /* Set default PBA value */
607 /* Put the address into the Receive Address Array */
608 e1000_rar_set(hw, hw->mac.addr, 0);
611 * With the 82571 adapter, RAR[0] may be overwritten
612 * when the other port is reset, we make a duplicate
613 * in RAR[14] for that eventuality, this assures
614 * the interface continues to function.
616 if (hw->mac.type == e1000_82571) {
617 e1000_set_laa_state_82571(hw, TRUE);
618 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
621 /* Initialize the hardware */
622 if (em_hardware_init(hw)) {
623 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
627 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
629 /* Configure for OS presence */
630 em_init_manageability(hw);
632 if (dev->data->dev_conf.intr_conf.rxq != 0) {
633 intr_vector = dev->data->nb_rx_queues;
634 if (rte_intr_efd_enable(intr_handle, intr_vector))
638 if (rte_intr_dp_is_en(intr_handle)) {
639 intr_handle->intr_vec =
640 rte_zmalloc("intr_vec",
641 dev->data->nb_rx_queues * sizeof(int), 0);
642 if (intr_handle->intr_vec == NULL) {
643 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
644 " intr_vec", dev->data->nb_rx_queues);
648 /* enable rx interrupt */
649 em_rxq_intr_enable(hw);
654 ret = eth_em_rx_init(dev);
656 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
657 em_dev_clear_queues(dev);
661 e1000_clear_hw_cntrs_base_generic(hw);
663 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
664 ETH_VLAN_EXTEND_MASK;
665 eth_em_vlan_offload_set(dev, mask);
667 /* Set Interrupt Throttling Rate to maximum allowed value. */
668 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
670 /* Setup link speed and duplex */
671 speeds = &dev->data->dev_conf.link_speeds;
672 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
673 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
677 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
680 hw->phy.autoneg_advertised = 0;
682 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
683 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
684 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
686 goto error_invalid_config;
688 if (*speeds & ETH_LINK_SPEED_10M_HD) {
689 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
692 if (*speeds & ETH_LINK_SPEED_10M) {
693 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
696 if (*speeds & ETH_LINK_SPEED_100M_HD) {
697 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
700 if (*speeds & ETH_LINK_SPEED_100M) {
701 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
704 if (*speeds & ETH_LINK_SPEED_1G) {
705 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
708 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
709 goto error_invalid_config;
711 /* Set/reset the mac.autoneg based on the link speed,
716 hw->mac.forced_speed_duplex =
717 hw->phy.autoneg_advertised;
723 e1000_setup_link(hw);
725 if (rte_intr_allow_others(intr_handle)) {
726 /* check if lsc interrupt is enabled */
727 if (dev->data->dev_conf.intr_conf.lsc != 0) {
728 ret = eth_em_interrupt_setup(dev);
730 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
731 em_dev_clear_queues(dev);
736 rte_intr_callback_unregister(intr_handle,
737 eth_em_interrupt_handler,
739 if (dev->data->dev_conf.intr_conf.lsc != 0)
740 PMD_INIT_LOG(INFO, "lsc won't enable because of"
741 " no intr multiplexn");
743 /* check if rxq interrupt is enabled */
744 if (dev->data->dev_conf.intr_conf.rxq != 0)
745 eth_em_rxq_interrupt_setup(dev);
747 rte_intr_enable(intr_handle);
749 adapter->stopped = 0;
751 PMD_INIT_LOG(DEBUG, "<<");
755 error_invalid_config:
756 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
757 dev->data->dev_conf.link_speeds, dev->data->port_id);
758 em_dev_clear_queues(dev);
762 /*********************************************************************
764 * This routine disables all traffic on the adapter by issuing a
765 * global reset on the MAC.
767 **********************************************************************/
769 eth_em_stop(struct rte_eth_dev *dev)
771 struct rte_eth_link link;
772 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
773 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
774 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
776 em_rxq_intr_disable(hw);
777 em_lsc_intr_disable(hw);
780 if (hw->mac.type >= e1000_82544)
781 E1000_WRITE_REG(hw, E1000_WUC, 0);
783 /* Power down the phy. Needed to make the link go down */
784 e1000_power_down_phy(hw);
786 em_dev_clear_queues(dev);
788 /* clear the recorded link status */
789 memset(&link, 0, sizeof(link));
790 rte_em_dev_atomic_write_link_status(dev, &link);
792 if (!rte_intr_allow_others(intr_handle))
793 /* resume to the default handler */
794 rte_intr_callback_register(intr_handle,
795 eth_em_interrupt_handler,
798 /* Clean datapath event and queue/vec mapping */
799 rte_intr_efd_disable(intr_handle);
800 if (intr_handle->intr_vec != NULL) {
801 rte_free(intr_handle->intr_vec);
802 intr_handle->intr_vec = NULL;
807 eth_em_close(struct rte_eth_dev *dev)
809 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
810 struct e1000_adapter *adapter =
811 E1000_DEV_PRIVATE(dev->data->dev_private);
814 adapter->stopped = 1;
815 em_dev_free_queues(dev);
816 e1000_phy_hw_reset(hw);
817 em_release_manageability(hw);
818 em_hw_control_release(hw);
822 em_get_rx_buffer_size(struct e1000_hw *hw)
824 uint32_t rx_buf_size;
826 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
830 /*********************************************************************
832 * Initialize the hardware
834 **********************************************************************/
836 em_hardware_init(struct e1000_hw *hw)
838 uint32_t rx_buf_size;
841 /* Issue a global reset */
844 /* Let the firmware know the OS is in control */
845 em_hw_control_acquire(hw);
848 * These parameters control the automatic generation (Tx) and
849 * response (Rx) to Ethernet PAUSE frames.
850 * - High water mark should allow for at least two standard size (1518)
851 * frames to be received after sending an XOFF.
852 * - Low water mark works best when it is very near the high water mark.
853 * This allows the receiver to restart by sending XON when it has
854 * drained a bit. Here we use an arbitrary value of 1500 which will
855 * restart after one full frame is pulled from the buffer. There
856 * could be several smaller frames in the buffer and if so they will
857 * not trigger the XON until their total number reduces the buffer
859 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
861 rx_buf_size = em_get_rx_buffer_size(hw);
863 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
864 hw->fc.low_water = hw->fc.high_water - 1500;
866 if (hw->mac.type == e1000_80003es2lan)
867 hw->fc.pause_time = UINT16_MAX;
869 hw->fc.pause_time = EM_FC_PAUSE_TIME;
873 /* Set Flow control, use the tunable location if sane */
874 if (em_fc_setting <= e1000_fc_full)
875 hw->fc.requested_mode = em_fc_setting;
877 hw->fc.requested_mode = e1000_fc_none;
879 /* Workaround: no TX flow ctrl for PCH */
880 if (hw->mac.type == e1000_pchlan)
881 hw->fc.requested_mode = e1000_fc_rx_pause;
883 /* Override - settings for PCH2LAN, ya its magic :) */
884 if (hw->mac.type == e1000_pch2lan) {
885 hw->fc.high_water = 0x5C20;
886 hw->fc.low_water = 0x5048;
887 hw->fc.pause_time = 0x0650;
888 hw->fc.refresh_time = 0x0400;
889 } else if (hw->mac.type == e1000_pch_lpt ||
890 hw->mac.type == e1000_pch_spt ||
891 hw->mac.type == e1000_pch_cnp) {
892 hw->fc.requested_mode = e1000_fc_full;
895 diag = e1000_init_hw(hw);
898 e1000_check_for_link(hw);
902 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
904 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
906 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
907 struct e1000_hw_stats *stats =
908 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
911 if(hw->phy.media_type == e1000_media_type_copper ||
912 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
913 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
914 stats->sec += E1000_READ_REG(hw, E1000_SEC);
917 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
918 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
919 stats->scc += E1000_READ_REG(hw, E1000_SCC);
920 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
922 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
923 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
924 stats->colc += E1000_READ_REG(hw, E1000_COLC);
925 stats->dc += E1000_READ_REG(hw, E1000_DC);
926 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
927 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
928 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
931 * For watchdog management we need to know if we have been
932 * paused during the last interval, so capture that here.
934 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
935 stats->xoffrxc += pause_frames;
936 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
937 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
938 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
939 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
940 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
941 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
942 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
943 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
944 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
945 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
946 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
947 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
950 * For the 64-bit byte counters the low dword must be read first.
951 * Both registers clear on the read of the high dword.
954 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
955 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
956 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
957 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
959 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
960 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
961 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
962 stats->roc += E1000_READ_REG(hw, E1000_ROC);
963 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
965 stats->tor += E1000_READ_REG(hw, E1000_TORH);
966 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
968 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
969 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
970 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
971 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
972 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
973 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
974 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
975 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
976 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
977 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
979 /* Interrupt Counts */
981 if (hw->mac.type >= e1000_82571) {
982 stats->iac += E1000_READ_REG(hw, E1000_IAC);
983 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
984 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
985 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
986 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
987 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
988 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
989 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
990 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
993 if (hw->mac.type >= e1000_82543) {
994 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
995 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
996 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
997 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
998 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
999 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1002 if (rte_stats == NULL)
1006 rte_stats->imissed = stats->mpc;
1007 rte_stats->ierrors = stats->crcerrs +
1008 stats->rlec + stats->ruc + stats->roc +
1009 stats->rxerrc + stats->algnerrc + stats->cexterr;
1012 rte_stats->oerrors = stats->ecol + stats->latecol;
1014 rte_stats->ipackets = stats->gprc;
1015 rte_stats->opackets = stats->gptc;
1016 rte_stats->ibytes = stats->gorc;
1017 rte_stats->obytes = stats->gotc;
1021 eth_em_stats_reset(struct rte_eth_dev *dev)
1023 struct e1000_hw_stats *hw_stats =
1024 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1026 /* HW registers are cleared on read */
1027 eth_em_stats_get(dev, NULL);
1029 /* Reset software totals */
1030 memset(hw_stats, 0, sizeof(*hw_stats));
1034 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1036 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1038 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1040 em_rxq_intr_enable(hw);
1041 rte_intr_enable(intr_handle);
1047 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1049 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1051 em_rxq_intr_disable(hw);
1057 em_get_max_pktlen(const struct e1000_hw *hw)
1059 switch (hw->mac.type) {
1063 case e1000_ich10lan:
1069 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1074 /* Adapters that do not support jumbo frames */
1076 return ETHER_MAX_LEN;
1078 return MAX_JUMBO_FRAME_SIZE;
1083 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1085 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1088 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1089 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1090 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1091 dev_info->rx_offload_capa =
1092 DEV_RX_OFFLOAD_VLAN_STRIP |
1093 DEV_RX_OFFLOAD_IPV4_CKSUM |
1094 DEV_RX_OFFLOAD_UDP_CKSUM |
1095 DEV_RX_OFFLOAD_TCP_CKSUM;
1096 dev_info->tx_offload_capa =
1097 DEV_TX_OFFLOAD_VLAN_INSERT |
1098 DEV_TX_OFFLOAD_IPV4_CKSUM |
1099 DEV_TX_OFFLOAD_UDP_CKSUM |
1100 DEV_TX_OFFLOAD_TCP_CKSUM;
1103 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1104 * Unfortunatelly, all these nics have just one TX context.
1105 * So we have few choises for TX:
1106 * - Use just one TX queue.
1107 * - Allow cksum offload only for one TX queue.
1108 * - Don't allow TX cksum offload at all.
1109 * For now, option #1 was chosen.
1110 * To use second RX queue we have to use extended RX descriptor
1111 * (Multiple Receive Queues are mutually exclusive with UDP
1112 * fragmentation and are not supported when a legacy receive
1113 * descriptor format is used).
1114 * Which means separate RX routinies - as legacy nics (82540, 82545)
1115 * don't support extended RXD.
1116 * To avoid it we support just one RX queue for now (no RSS).
1119 dev_info->max_rx_queues = 1;
1120 dev_info->max_tx_queues = 1;
1122 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1123 .nb_max = E1000_MAX_RING_DESC,
1124 .nb_min = E1000_MIN_RING_DESC,
1125 .nb_align = EM_RXD_ALIGN,
1128 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1129 .nb_max = E1000_MAX_RING_DESC,
1130 .nb_min = E1000_MIN_RING_DESC,
1131 .nb_align = EM_TXD_ALIGN,
1132 .nb_seg_max = EM_TX_MAX_SEG,
1133 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1136 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1137 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1141 /* return 0 means link status changed, -1 means not changed */
1143 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1145 struct e1000_hw *hw =
1146 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1147 struct rte_eth_link link, old;
1148 int link_check, count;
1151 hw->mac.get_link_status = 1;
1153 /* possible wait-to-complete in up to 9 seconds */
1154 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1155 /* Read the real link status */
1156 switch (hw->phy.media_type) {
1157 case e1000_media_type_copper:
1158 /* Do the work to read phy */
1159 e1000_check_for_link(hw);
1160 link_check = !hw->mac.get_link_status;
1163 case e1000_media_type_fiber:
1164 e1000_check_for_link(hw);
1165 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1169 case e1000_media_type_internal_serdes:
1170 e1000_check_for_link(hw);
1171 link_check = hw->mac.serdes_has_link;
1177 if (link_check || wait_to_complete == 0)
1179 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1181 memset(&link, 0, sizeof(link));
1182 rte_em_dev_atomic_read_link_status(dev, &link);
1185 /* Now we check if a transition has happened */
1186 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1187 uint16_t duplex, speed;
1188 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1189 link.link_duplex = (duplex == FULL_DUPLEX) ?
1190 ETH_LINK_FULL_DUPLEX :
1191 ETH_LINK_HALF_DUPLEX;
1192 link.link_speed = speed;
1193 link.link_status = ETH_LINK_UP;
1194 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1195 ETH_LINK_SPEED_FIXED);
1196 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1197 link.link_speed = 0;
1198 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1199 link.link_status = ETH_LINK_DOWN;
1200 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1202 rte_em_dev_atomic_write_link_status(dev, &link);
1205 if (old.link_status == link.link_status)
1213 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1214 * For ASF and Pass Through versions of f/w this means
1215 * that the driver is loaded. For AMT version type f/w
1216 * this means that the network i/f is open.
1219 em_hw_control_acquire(struct e1000_hw *hw)
1221 uint32_t ctrl_ext, swsm;
1223 /* Let firmware know the driver has taken over */
1224 if (hw->mac.type == e1000_82573) {
1225 swsm = E1000_READ_REG(hw, E1000_SWSM);
1226 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1229 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1230 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1231 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1236 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1237 * For ASF and Pass Through versions of f/w this means that the
1238 * driver is no longer loaded. For AMT versions of the
1239 * f/w this means that the network i/f is closed.
1242 em_hw_control_release(struct e1000_hw *hw)
1244 uint32_t ctrl_ext, swsm;
1246 /* Let firmware taken over control of h/w */
1247 if (hw->mac.type == e1000_82573) {
1248 swsm = E1000_READ_REG(hw, E1000_SWSM);
1249 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1251 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1252 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1253 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1258 * Bit of a misnomer, what this really means is
1259 * to enable OS management of the system... aka
1260 * to disable special hardware management features.
1263 em_init_manageability(struct e1000_hw *hw)
1265 if (e1000_enable_mng_pass_thru(hw)) {
1266 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1267 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1269 /* disable hardware interception of ARP */
1270 manc &= ~(E1000_MANC_ARP_EN);
1272 /* enable receiving management packets to the host */
1273 manc |= E1000_MANC_EN_MNG2HOST;
1274 manc2h |= 1 << 5; /* Mng Port 623 */
1275 manc2h |= 1 << 6; /* Mng Port 664 */
1276 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1277 E1000_WRITE_REG(hw, E1000_MANC, manc);
1282 * Give control back to hardware management
1283 * controller if there is one.
1286 em_release_manageability(struct e1000_hw *hw)
1290 if (e1000_enable_mng_pass_thru(hw)) {
1291 manc = E1000_READ_REG(hw, E1000_MANC);
1293 /* re-enable hardware interception of ARP */
1294 manc |= E1000_MANC_ARP_EN;
1295 manc &= ~E1000_MANC_EN_MNG2HOST;
1297 E1000_WRITE_REG(hw, E1000_MANC, manc);
1302 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1304 struct e1000_hw *hw =
1305 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308 rctl = E1000_READ_REG(hw, E1000_RCTL);
1309 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1310 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1314 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1316 struct e1000_hw *hw =
1317 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320 rctl = E1000_READ_REG(hw, E1000_RCTL);
1321 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1322 if (dev->data->all_multicast == 1)
1323 rctl |= E1000_RCTL_MPE;
1325 rctl &= (~E1000_RCTL_MPE);
1326 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1330 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1332 struct e1000_hw *hw =
1333 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1336 rctl = E1000_READ_REG(hw, E1000_RCTL);
1337 rctl |= E1000_RCTL_MPE;
1338 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1342 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1344 struct e1000_hw *hw =
1345 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348 if (dev->data->promiscuous == 1)
1349 return; /* must remain in all_multicast mode */
1350 rctl = E1000_READ_REG(hw, E1000_RCTL);
1351 rctl &= (~E1000_RCTL_MPE);
1352 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1356 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1358 struct e1000_hw *hw =
1359 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1360 struct e1000_vfta * shadow_vfta =
1361 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1366 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1367 E1000_VFTA_ENTRY_MASK);
1368 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1369 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1374 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1376 /* update local VFTA copy */
1377 shadow_vfta->vfta[vid_idx] = vfta;
1383 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1385 struct e1000_hw *hw =
1386 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389 /* Filter Table Disable */
1390 reg = E1000_READ_REG(hw, E1000_RCTL);
1391 reg &= ~E1000_RCTL_CFIEN;
1392 reg &= ~E1000_RCTL_VFE;
1393 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1397 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1399 struct e1000_hw *hw =
1400 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1401 struct e1000_vfta * shadow_vfta =
1402 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1406 /* Filter Table Enable, CFI not used for packet acceptance */
1407 reg = E1000_READ_REG(hw, E1000_RCTL);
1408 reg &= ~E1000_RCTL_CFIEN;
1409 reg |= E1000_RCTL_VFE;
1410 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1412 /* restore vfta from local copy */
1413 for (i = 0; i < IGB_VFTA_SIZE; i++)
1414 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1418 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1420 struct e1000_hw *hw =
1421 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1424 /* VLAN Mode Disable */
1425 reg = E1000_READ_REG(hw, E1000_CTRL);
1426 reg &= ~E1000_CTRL_VME;
1427 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1432 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1434 struct e1000_hw *hw =
1435 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1438 /* VLAN Mode Enable */
1439 reg = E1000_READ_REG(hw, E1000_CTRL);
1440 reg |= E1000_CTRL_VME;
1441 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1445 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1447 if(mask & ETH_VLAN_STRIP_MASK){
1448 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1449 em_vlan_hw_strip_enable(dev);
1451 em_vlan_hw_strip_disable(dev);
1454 if(mask & ETH_VLAN_FILTER_MASK){
1455 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1456 em_vlan_hw_filter_enable(dev);
1458 em_vlan_hw_filter_disable(dev);
1463 * It enables the interrupt mask and then enable the interrupt.
1466 * Pointer to struct rte_eth_dev.
1469 * - On success, zero.
1470 * - On failure, a negative value.
1473 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1476 struct e1000_hw *hw =
1477 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1479 /* clear interrupt */
1480 E1000_READ_REG(hw, E1000_ICR);
1481 regval = E1000_READ_REG(hw, E1000_IMS);
1482 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1487 * It clears the interrupt causes and enables the interrupt.
1488 * It will be called once only during nic initialized.
1491 * Pointer to struct rte_eth_dev.
1494 * - On success, zero.
1495 * - On failure, a negative value.
1498 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1500 struct e1000_hw *hw =
1501 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503 E1000_READ_REG(hw, E1000_ICR);
1504 em_rxq_intr_enable(hw);
1509 * It enable receive packet interrupt.
1511 * Pointer to struct e1000_hw
1516 em_rxq_intr_enable(struct e1000_hw *hw)
1518 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1519 E1000_WRITE_FLUSH(hw);
1523 * It disabled lsc interrupt.
1525 * Pointer to struct e1000_hw
1530 em_lsc_intr_disable(struct e1000_hw *hw)
1532 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1533 E1000_WRITE_FLUSH(hw);
1537 * It disabled receive packet interrupt.
1539 * Pointer to struct e1000_hw
1544 em_rxq_intr_disable(struct e1000_hw *hw)
1546 E1000_READ_REG(hw, E1000_ICR);
1547 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1548 E1000_WRITE_FLUSH(hw);
1552 * It reads ICR and gets interrupt causes, check it and set a bit flag
1553 * to update link status.
1556 * Pointer to struct rte_eth_dev.
1559 * - On success, zero.
1560 * - On failure, a negative value.
1563 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1566 struct e1000_hw *hw =
1567 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568 struct e1000_interrupt *intr =
1569 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1571 /* read-on-clear nic registers here */
1572 icr = E1000_READ_REG(hw, E1000_ICR);
1573 if (icr & E1000_ICR_LSC) {
1574 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1581 * It executes link_update after knowing an interrupt is prsent.
1584 * Pointer to struct rte_eth_dev.
1587 * - On success, zero.
1588 * - On failure, a negative value.
1591 eth_em_interrupt_action(struct rte_eth_dev *dev,
1592 struct rte_intr_handle *intr_handle)
1594 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1595 struct e1000_hw *hw =
1596 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597 struct e1000_interrupt *intr =
1598 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1599 uint32_t tctl, rctl;
1600 struct rte_eth_link link;
1603 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1606 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1607 rte_intr_enable(intr_handle);
1609 /* set get_link_status to check register later */
1610 hw->mac.get_link_status = 1;
1611 ret = eth_em_link_update(dev, 0);
1613 /* check if link has changed */
1617 memset(&link, 0, sizeof(link));
1618 rte_em_dev_atomic_read_link_status(dev, &link);
1619 if (link.link_status) {
1620 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1621 dev->data->port_id, (unsigned)link.link_speed,
1622 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1623 "full-duplex" : "half-duplex");
1625 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1627 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1628 pci_dev->addr.domain, pci_dev->addr.bus,
1629 pci_dev->addr.devid, pci_dev->addr.function);
1631 tctl = E1000_READ_REG(hw, E1000_TCTL);
1632 rctl = E1000_READ_REG(hw, E1000_RCTL);
1633 if (link.link_status) {
1635 tctl |= E1000_TCTL_EN;
1636 rctl |= E1000_RCTL_EN;
1639 tctl &= ~E1000_TCTL_EN;
1640 rctl &= ~E1000_RCTL_EN;
1642 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1643 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1644 E1000_WRITE_FLUSH(hw);
1650 * Interrupt handler which shall be registered at first.
1653 * Pointer to interrupt handle.
1655 * The address of parameter (struct rte_eth_dev *) regsitered before.
1661 eth_em_interrupt_handler(struct rte_intr_handle *handle,
1664 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1666 eth_em_interrupt_get_status(dev);
1667 eth_em_interrupt_action(dev, handle);
1668 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1672 eth_em_led_on(struct rte_eth_dev *dev)
1674 struct e1000_hw *hw;
1676 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1681 eth_em_led_off(struct rte_eth_dev *dev)
1683 struct e1000_hw *hw;
1685 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1690 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1692 struct e1000_hw *hw;
1697 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698 fc_conf->pause_time = hw->fc.pause_time;
1699 fc_conf->high_water = hw->fc.high_water;
1700 fc_conf->low_water = hw->fc.low_water;
1701 fc_conf->send_xon = hw->fc.send_xon;
1702 fc_conf->autoneg = hw->mac.autoneg;
1705 * Return rx_pause and tx_pause status according to actual setting of
1706 * the TFCE and RFCE bits in the CTRL register.
1708 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1709 if (ctrl & E1000_CTRL_TFCE)
1714 if (ctrl & E1000_CTRL_RFCE)
1719 if (rx_pause && tx_pause)
1720 fc_conf->mode = RTE_FC_FULL;
1722 fc_conf->mode = RTE_FC_RX_PAUSE;
1724 fc_conf->mode = RTE_FC_TX_PAUSE;
1726 fc_conf->mode = RTE_FC_NONE;
1732 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1734 struct e1000_hw *hw;
1736 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1742 uint32_t rx_buf_size;
1743 uint32_t max_high_water;
1746 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1747 if (fc_conf->autoneg != hw->mac.autoneg)
1749 rx_buf_size = em_get_rx_buffer_size(hw);
1750 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1752 /* At least reserve one Ethernet frame for watermark */
1753 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1754 if ((fc_conf->high_water > max_high_water) ||
1755 (fc_conf->high_water < fc_conf->low_water)) {
1756 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1757 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1761 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1762 hw->fc.pause_time = fc_conf->pause_time;
1763 hw->fc.high_water = fc_conf->high_water;
1764 hw->fc.low_water = fc_conf->low_water;
1765 hw->fc.send_xon = fc_conf->send_xon;
1767 err = e1000_setup_link_generic(hw);
1768 if (err == E1000_SUCCESS) {
1770 /* check if we want to forward MAC frames - driver doesn't have native
1771 * capability to do that, so we'll write the registers ourselves */
1773 rctl = E1000_READ_REG(hw, E1000_RCTL);
1775 /* set or clear MFLCN.PMCF bit depending on configuration */
1776 if (fc_conf->mac_ctrl_frame_fwd != 0)
1777 rctl |= E1000_RCTL_PMCF;
1779 rctl &= ~E1000_RCTL_PMCF;
1781 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1782 E1000_WRITE_FLUSH(hw);
1787 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1792 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1793 uint32_t index, __rte_unused uint32_t pool)
1795 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1797 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1801 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1803 uint8_t addr[ETHER_ADDR_LEN];
1804 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1806 memset(addr, 0, sizeof(addr));
1808 e1000_rar_set(hw, addr, index);
1812 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1814 struct rte_eth_dev_info dev_info;
1815 struct e1000_hw *hw;
1816 uint32_t frame_size;
1819 eth_em_infos_get(dev, &dev_info);
1820 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1822 /* check that mtu is within the allowed range */
1823 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1826 /* refuse mtu that requires the support of scattered packets when this
1827 * feature has not been enabled before. */
1828 if (!dev->data->scattered_rx &&
1829 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1832 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833 rctl = E1000_READ_REG(hw, E1000_RCTL);
1835 /* switch to jumbo mode if needed */
1836 if (frame_size > ETHER_MAX_LEN) {
1837 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1838 rctl |= E1000_RCTL_LPE;
1840 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1841 rctl &= ~E1000_RCTL_LPE;
1843 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1845 /* update max frame size */
1846 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1851 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1852 struct ether_addr *mc_addr_set,
1853 uint32_t nb_mc_addr)
1855 struct e1000_hw *hw;
1857 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1862 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd.pci_drv);
1863 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1864 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio");