1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
14 #include <rte_debug.h>
16 #include <rte_bus_pci.h>
17 #include <rte_ether.h>
18 #include <ethdev_driver.h>
19 #include <ethdev_pci.h>
20 #include <rte_memory.h>
22 #include <rte_malloc.h>
25 #include "e1000_logs.h"
26 #include "base/e1000_api.h"
27 #include "e1000_ethdev.h"
29 #define EM_EIAC 0x000DC
31 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
34 static int eth_em_configure(struct rte_eth_dev *dev);
35 static int eth_em_start(struct rte_eth_dev *dev);
36 static int eth_em_stop(struct rte_eth_dev *dev);
37 static int eth_em_close(struct rte_eth_dev *dev);
38 static int eth_em_promiscuous_enable(struct rte_eth_dev *dev);
39 static int eth_em_promiscuous_disable(struct rte_eth_dev *dev);
40 static int eth_em_allmulticast_enable(struct rte_eth_dev *dev);
41 static int eth_em_allmulticast_disable(struct rte_eth_dev *dev);
42 static int eth_em_link_update(struct rte_eth_dev *dev,
43 int wait_to_complete);
44 static int eth_em_stats_get(struct rte_eth_dev *dev,
45 struct rte_eth_stats *rte_stats);
46 static int eth_em_stats_reset(struct rte_eth_dev *dev);
47 static int eth_em_infos_get(struct rte_eth_dev *dev,
48 struct rte_eth_dev_info *dev_info);
49 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
50 struct rte_eth_fc_conf *fc_conf);
51 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
52 struct rte_eth_fc_conf *fc_conf);
53 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
54 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
55 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
56 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
57 struct rte_intr_handle *handle);
58 static void eth_em_interrupt_handler(void *param);
60 static int em_hw_init(struct e1000_hw *hw);
61 static int em_hardware_init(struct e1000_hw *hw);
62 static void em_hw_control_acquire(struct e1000_hw *hw);
63 static void em_hw_control_release(struct e1000_hw *hw);
64 static void em_init_manageability(struct e1000_hw *hw);
65 static void em_release_manageability(struct e1000_hw *hw);
67 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
70 uint16_t vlan_id, int on);
71 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
72 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
73 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
74 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
75 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
78 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
79 uint16_t vlan_id, int on);
82 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
83 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
84 static void em_lsc_intr_disable(struct e1000_hw *hw);
85 static void em_rxq_intr_enable(struct e1000_hw *hw);
86 static void em_rxq_intr_disable(struct e1000_hw *hw);
88 static int eth_em_led_on(struct rte_eth_dev *dev);
89 static int eth_em_led_off(struct rte_eth_dev *dev);
91 static int em_get_rx_buffer_size(struct e1000_hw *hw);
92 static int eth_em_rar_set(struct rte_eth_dev *dev,
93 struct rte_ether_addr *mac_addr,
94 uint32_t index, uint32_t pool);
95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
96 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
97 struct rte_ether_addr *addr);
99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
100 struct rte_ether_addr *mc_addr_set,
101 uint32_t nb_mc_addr);
103 #define EM_FC_PAUSE_TIME 0x0680
104 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
110 * The set of PCI devices this driver supports
112 static const struct rte_pci_id pci_id_em_map[] = {
113 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
114 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
115 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
116 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
117 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
118 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
119 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
120 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
121 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
122 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
123 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
124 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
125 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
126 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
127 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
128 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
129 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
130 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
131 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
132 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
133 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
134 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
135 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
136 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
137 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
138 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
139 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
140 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
158 { .vendor_id = 0, /* sentinel */ },
161 static const struct eth_dev_ops eth_em_ops = {
162 .dev_configure = eth_em_configure,
163 .dev_start = eth_em_start,
164 .dev_stop = eth_em_stop,
165 .dev_close = eth_em_close,
166 .promiscuous_enable = eth_em_promiscuous_enable,
167 .promiscuous_disable = eth_em_promiscuous_disable,
168 .allmulticast_enable = eth_em_allmulticast_enable,
169 .allmulticast_disable = eth_em_allmulticast_disable,
170 .link_update = eth_em_link_update,
171 .stats_get = eth_em_stats_get,
172 .stats_reset = eth_em_stats_reset,
173 .dev_infos_get = eth_em_infos_get,
174 .mtu_set = eth_em_mtu_set,
175 .vlan_filter_set = eth_em_vlan_filter_set,
176 .vlan_offload_set = eth_em_vlan_offload_set,
177 .rx_queue_setup = eth_em_rx_queue_setup,
178 .rx_queue_release = eth_em_rx_queue_release,
179 .tx_queue_setup = eth_em_tx_queue_setup,
180 .tx_queue_release = eth_em_tx_queue_release,
181 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
182 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
183 .dev_led_on = eth_em_led_on,
184 .dev_led_off = eth_em_led_off,
185 .flow_ctrl_get = eth_em_flow_ctrl_get,
186 .flow_ctrl_set = eth_em_flow_ctrl_set,
187 .mac_addr_set = eth_em_default_mac_addr_set,
188 .mac_addr_add = eth_em_rar_set,
189 .mac_addr_remove = eth_em_rar_clear,
190 .set_mc_addr_list = eth_em_set_mc_addr_list,
191 .rxq_info_get = em_rxq_info_get,
192 .txq_info_get = em_txq_info_get,
197 * eth_em_dev_is_ich8 - Check for ICH8 device
198 * @hw: pointer to the HW structure
200 * return TRUE for ICH8, otherwise FALSE
203 eth_em_dev_is_ich8(struct e1000_hw *hw)
205 DEBUGFUNC("eth_em_dev_is_ich8");
207 switch (hw->device_id) {
208 case E1000_DEV_ID_PCH2_LV_LM:
209 case E1000_DEV_ID_PCH_LPT_I217_LM:
210 case E1000_DEV_ID_PCH_LPT_I217_V:
211 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
212 case E1000_DEV_ID_PCH_LPTLP_I218_V:
213 case E1000_DEV_ID_PCH_I218_V2:
214 case E1000_DEV_ID_PCH_I218_LM2:
215 case E1000_DEV_ID_PCH_I218_V3:
216 case E1000_DEV_ID_PCH_I218_LM3:
217 case E1000_DEV_ID_PCH_SPT_I219_LM:
218 case E1000_DEV_ID_PCH_SPT_I219_V:
219 case E1000_DEV_ID_PCH_SPT_I219_LM2:
220 case E1000_DEV_ID_PCH_SPT_I219_V2:
221 case E1000_DEV_ID_PCH_LBG_I219_LM3:
222 case E1000_DEV_ID_PCH_SPT_I219_LM4:
223 case E1000_DEV_ID_PCH_SPT_I219_V4:
224 case E1000_DEV_ID_PCH_SPT_I219_LM5:
225 case E1000_DEV_ID_PCH_SPT_I219_V5:
226 case E1000_DEV_ID_PCH_CNP_I219_LM6:
227 case E1000_DEV_ID_PCH_CNP_I219_V6:
228 case E1000_DEV_ID_PCH_CNP_I219_LM7:
229 case E1000_DEV_ID_PCH_CNP_I219_V7:
237 eth_em_dev_init(struct rte_eth_dev *eth_dev)
239 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
240 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
241 struct e1000_adapter *adapter =
242 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
243 struct e1000_hw *hw =
244 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
245 struct e1000_vfta * shadow_vfta =
246 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
248 eth_dev->dev_ops = ð_em_ops;
249 eth_dev->rx_queue_count = eth_em_rx_queue_count;
250 eth_dev->rx_descriptor_done = eth_em_rx_descriptor_done;
251 eth_dev->rx_descriptor_status = eth_em_rx_descriptor_status;
252 eth_dev->tx_descriptor_status = eth_em_tx_descriptor_status;
253 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
254 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
255 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
257 /* for secondary processes, we don't initialise any further as primary
258 * has already done this work. Only check we don't need a different
260 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
261 if (eth_dev->data->scattered_rx)
262 eth_dev->rx_pkt_burst =
263 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
267 rte_eth_copy_pci_info(eth_dev, pci_dev);
268 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
270 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
271 hw->device_id = pci_dev->id.device_id;
272 adapter->stopped = 0;
274 /* For ICH8 support we'll need to map the flash memory BAR */
275 if (eth_em_dev_is_ich8(hw))
276 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
278 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
279 em_hw_init(hw) != 0) {
280 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
282 eth_dev->data->port_id, pci_dev->id.vendor_id,
283 pci_dev->id.device_id);
287 /* Allocate memory for storing MAC addresses */
288 eth_dev->data->mac_addrs = rte_zmalloc("e1000", RTE_ETHER_ADDR_LEN *
289 hw->mac.rar_entry_count, 0);
290 if (eth_dev->data->mac_addrs == NULL) {
291 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
292 "store MAC addresses",
293 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
297 /* Copy the permanent MAC address */
298 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
299 eth_dev->data->mac_addrs);
301 /* initialize the vfta */
302 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
304 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
305 eth_dev->data->port_id, pci_dev->id.vendor_id,
306 pci_dev->id.device_id);
308 rte_intr_callback_register(intr_handle,
309 eth_em_interrupt_handler, eth_dev);
315 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
317 PMD_INIT_FUNC_TRACE();
319 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
322 eth_em_close(eth_dev);
327 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
328 struct rte_pci_device *pci_dev)
330 return rte_eth_dev_pci_generic_probe(pci_dev,
331 sizeof(struct e1000_adapter), eth_em_dev_init);
334 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
336 return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
339 static struct rte_pci_driver rte_em_pmd = {
340 .id_table = pci_id_em_map,
341 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
342 .probe = eth_em_pci_probe,
343 .remove = eth_em_pci_remove,
347 em_hw_init(struct e1000_hw *hw)
351 diag = hw->mac.ops.init_params(hw);
353 PMD_INIT_LOG(ERR, "MAC Initialization Error");
356 diag = hw->nvm.ops.init_params(hw);
358 PMD_INIT_LOG(ERR, "NVM Initialization Error");
361 diag = hw->phy.ops.init_params(hw);
363 PMD_INIT_LOG(ERR, "PHY Initialization Error");
366 (void) e1000_get_bus_info(hw);
369 hw->phy.autoneg_wait_to_complete = 0;
370 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
372 e1000_init_script_state_82541(hw, TRUE);
373 e1000_set_tbi_compatibility_82543(hw, TRUE);
376 if (hw->phy.media_type == e1000_media_type_copper) {
377 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
378 hw->phy.disable_polarity_correction = 0;
379 hw->phy.ms_type = e1000_ms_hw_default;
383 * Start from a known state, this is important in reading the nvm
388 /* Make sure we have a good EEPROM before we read from it */
389 if (e1000_validate_nvm_checksum(hw) < 0) {
391 * Some PCI-E parts fail the first check due to
392 * the link being in sleep state, call it again,
393 * if it fails a second time its a real issue.
395 diag = e1000_validate_nvm_checksum(hw);
397 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
402 /* Read the permanent MAC address out of the EEPROM */
403 diag = e1000_read_mac_addr(hw);
405 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
409 /* Now initialize the hardware */
410 diag = em_hardware_init(hw);
412 PMD_INIT_LOG(ERR, "Hardware initialization failed");
416 hw->mac.get_link_status = 1;
418 /* Indicate SOL/IDER usage */
419 diag = e1000_check_reset_block(hw);
421 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
427 em_hw_control_release(hw);
432 eth_em_configure(struct rte_eth_dev *dev)
434 struct e1000_interrupt *intr =
435 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
437 PMD_INIT_FUNC_TRACE();
438 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
440 PMD_INIT_FUNC_TRACE();
446 em_set_pba(struct e1000_hw *hw)
451 * Packet Buffer Allocation (PBA)
452 * Writing PBA sets the receive portion of the buffer
453 * the remainder is used for the transmit buffer.
454 * Devices before the 82547 had a Packet Buffer of 64K.
455 * After the 82547 the buffer was reduced to 40K.
457 switch (hw->mac.type) {
459 case e1000_82547_rev_2:
460 /* 82547: Total Packet Buffer is 40K */
461 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
465 case e1000_80003es2lan:
466 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
468 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
469 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
473 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
490 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
493 E1000_WRITE_REG(hw, E1000_PBA, pba);
497 eth_em_rxtx_control(struct rte_eth_dev *dev,
500 struct e1000_hw *hw =
501 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
504 tctl = E1000_READ_REG(hw, E1000_TCTL);
505 rctl = E1000_READ_REG(hw, E1000_RCTL);
508 tctl |= E1000_TCTL_EN;
509 rctl |= E1000_RCTL_EN;
512 tctl &= ~E1000_TCTL_EN;
513 rctl &= ~E1000_RCTL_EN;
515 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
516 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
517 E1000_WRITE_FLUSH(hw);
521 eth_em_start(struct rte_eth_dev *dev)
523 struct e1000_adapter *adapter =
524 E1000_DEV_PRIVATE(dev->data->dev_private);
525 struct e1000_hw *hw =
526 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
527 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
528 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
530 uint32_t intr_vector = 0;
535 PMD_INIT_FUNC_TRACE();
537 ret = eth_em_stop(dev);
541 e1000_power_up_phy(hw);
543 /* Set default PBA value */
546 /* Put the address into the Receive Address Array */
547 e1000_rar_set(hw, hw->mac.addr, 0);
550 * With the 82571 adapter, RAR[0] may be overwritten
551 * when the other port is reset, we make a duplicate
552 * in RAR[14] for that eventuality, this assures
553 * the interface continues to function.
555 if (hw->mac.type == e1000_82571) {
556 e1000_set_laa_state_82571(hw, TRUE);
557 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
560 /* Initialize the hardware */
561 if (em_hardware_init(hw)) {
562 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
566 E1000_WRITE_REG(hw, E1000_VET, RTE_ETHER_TYPE_VLAN);
568 /* Configure for OS presence */
569 em_init_manageability(hw);
571 if (dev->data->dev_conf.intr_conf.rxq != 0) {
572 intr_vector = dev->data->nb_rx_queues;
573 if (rte_intr_efd_enable(intr_handle, intr_vector))
577 if (rte_intr_dp_is_en(intr_handle)) {
578 intr_handle->intr_vec =
579 rte_zmalloc("intr_vec",
580 dev->data->nb_rx_queues * sizeof(int), 0);
581 if (intr_handle->intr_vec == NULL) {
582 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
583 " intr_vec", dev->data->nb_rx_queues);
587 /* enable rx interrupt */
588 em_rxq_intr_enable(hw);
593 ret = eth_em_rx_init(dev);
595 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
596 em_dev_clear_queues(dev);
600 e1000_clear_hw_cntrs_base_generic(hw);
602 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
603 ETH_VLAN_EXTEND_MASK;
604 ret = eth_em_vlan_offload_set(dev, mask);
606 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
607 em_dev_clear_queues(dev);
611 /* Set Interrupt Throttling Rate to maximum allowed value. */
612 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
614 /* Setup link speed and duplex */
615 speeds = &dev->data->dev_conf.link_speeds;
616 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
617 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
621 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
624 hw->phy.autoneg_advertised = 0;
626 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
627 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
628 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
630 goto error_invalid_config;
632 if (*speeds & ETH_LINK_SPEED_10M_HD) {
633 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
636 if (*speeds & ETH_LINK_SPEED_10M) {
637 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
640 if (*speeds & ETH_LINK_SPEED_100M_HD) {
641 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
644 if (*speeds & ETH_LINK_SPEED_100M) {
645 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
648 if (*speeds & ETH_LINK_SPEED_1G) {
649 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
652 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
653 goto error_invalid_config;
655 /* Set/reset the mac.autoneg based on the link speed,
660 hw->mac.forced_speed_duplex =
661 hw->phy.autoneg_advertised;
667 e1000_setup_link(hw);
669 if (rte_intr_allow_others(intr_handle)) {
670 /* check if lsc interrupt is enabled */
671 if (dev->data->dev_conf.intr_conf.lsc != 0) {
672 ret = eth_em_interrupt_setup(dev);
674 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
675 em_dev_clear_queues(dev);
680 rte_intr_callback_unregister(intr_handle,
681 eth_em_interrupt_handler,
683 if (dev->data->dev_conf.intr_conf.lsc != 0)
684 PMD_INIT_LOG(INFO, "lsc won't enable because of"
685 " no intr multiplexn");
687 /* check if rxq interrupt is enabled */
688 if (dev->data->dev_conf.intr_conf.rxq != 0)
689 eth_em_rxq_interrupt_setup(dev);
691 rte_intr_enable(intr_handle);
693 adapter->stopped = 0;
695 eth_em_rxtx_control(dev, true);
696 eth_em_link_update(dev, 0);
698 PMD_INIT_LOG(DEBUG, "<<");
702 error_invalid_config:
703 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
704 dev->data->dev_conf.link_speeds, dev->data->port_id);
705 em_dev_clear_queues(dev);
709 /*********************************************************************
711 * This routine disables all traffic on the adapter by issuing a
712 * global reset on the MAC.
714 **********************************************************************/
716 eth_em_stop(struct rte_eth_dev *dev)
718 struct rte_eth_link link;
719 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
720 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
721 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
723 dev->data->dev_started = 0;
725 eth_em_rxtx_control(dev, false);
726 em_rxq_intr_disable(hw);
727 em_lsc_intr_disable(hw);
731 /* Flush desc rings for i219 */
732 if (hw->mac.type == e1000_pch_spt || hw->mac.type == e1000_pch_cnp)
733 em_flush_desc_rings(dev);
735 if (hw->mac.type >= e1000_82544)
736 E1000_WRITE_REG(hw, E1000_WUC, 0);
738 /* Power down the phy. Needed to make the link go down */
739 e1000_power_down_phy(hw);
741 em_dev_clear_queues(dev);
743 /* clear the recorded link status */
744 memset(&link, 0, sizeof(link));
745 rte_eth_linkstatus_set(dev, &link);
747 if (!rte_intr_allow_others(intr_handle))
748 /* resume to the default handler */
749 rte_intr_callback_register(intr_handle,
750 eth_em_interrupt_handler,
753 /* Clean datapath event and queue/vec mapping */
754 rte_intr_efd_disable(intr_handle);
755 if (intr_handle->intr_vec != NULL) {
756 rte_free(intr_handle->intr_vec);
757 intr_handle->intr_vec = NULL;
764 eth_em_close(struct rte_eth_dev *dev)
766 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
767 struct e1000_adapter *adapter =
768 E1000_DEV_PRIVATE(dev->data->dev_private);
769 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
770 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
773 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
776 ret = eth_em_stop(dev);
777 adapter->stopped = 1;
778 em_dev_free_queues(dev);
779 e1000_phy_hw_reset(hw);
780 em_release_manageability(hw);
781 em_hw_control_release(hw);
783 /* disable uio intr before callback unregister */
784 rte_intr_disable(intr_handle);
785 rte_intr_callback_unregister(intr_handle,
786 eth_em_interrupt_handler, dev);
792 em_get_rx_buffer_size(struct e1000_hw *hw)
794 uint32_t rx_buf_size;
796 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
800 /*********************************************************************
802 * Initialize the hardware
804 **********************************************************************/
806 em_hardware_init(struct e1000_hw *hw)
808 uint32_t rx_buf_size;
811 /* Issue a global reset */
814 /* Let the firmware know the OS is in control */
815 em_hw_control_acquire(hw);
818 * These parameters control the automatic generation (Tx) and
819 * response (Rx) to Ethernet PAUSE frames.
820 * - High water mark should allow for at least two standard size (1518)
821 * frames to be received after sending an XOFF.
822 * - Low water mark works best when it is very near the high water mark.
823 * This allows the receiver to restart by sending XON when it has
824 * drained a bit. Here we use an arbitrary value of 1500 which will
825 * restart after one full frame is pulled from the buffer. There
826 * could be several smaller frames in the buffer and if so they will
827 * not trigger the XON until their total number reduces the buffer
829 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
831 rx_buf_size = em_get_rx_buffer_size(hw);
833 hw->fc.high_water = rx_buf_size -
834 PMD_ROUNDUP(RTE_ETHER_MAX_LEN * 2, 1024);
835 hw->fc.low_water = hw->fc.high_water - 1500;
837 if (hw->mac.type == e1000_80003es2lan)
838 hw->fc.pause_time = UINT16_MAX;
840 hw->fc.pause_time = EM_FC_PAUSE_TIME;
844 /* Set Flow control, use the tunable location if sane */
845 if (em_fc_setting <= e1000_fc_full)
846 hw->fc.requested_mode = em_fc_setting;
848 hw->fc.requested_mode = e1000_fc_none;
850 /* Workaround: no TX flow ctrl for PCH */
851 if (hw->mac.type == e1000_pchlan)
852 hw->fc.requested_mode = e1000_fc_rx_pause;
854 /* Override - settings for PCH2LAN, ya its magic :) */
855 if (hw->mac.type == e1000_pch2lan) {
856 hw->fc.high_water = 0x5C20;
857 hw->fc.low_water = 0x5048;
858 hw->fc.pause_time = 0x0650;
859 hw->fc.refresh_time = 0x0400;
860 } else if (hw->mac.type == e1000_pch_lpt ||
861 hw->mac.type == e1000_pch_spt ||
862 hw->mac.type == e1000_pch_cnp) {
863 hw->fc.requested_mode = e1000_fc_full;
866 diag = e1000_init_hw(hw);
869 e1000_check_for_link(hw);
873 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
875 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
877 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
878 struct e1000_hw_stats *stats =
879 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
882 if(hw->phy.media_type == e1000_media_type_copper ||
883 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
884 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
885 stats->sec += E1000_READ_REG(hw, E1000_SEC);
888 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
889 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
890 stats->scc += E1000_READ_REG(hw, E1000_SCC);
891 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
893 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
894 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
895 stats->colc += E1000_READ_REG(hw, E1000_COLC);
896 stats->dc += E1000_READ_REG(hw, E1000_DC);
897 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
898 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
899 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
902 * For watchdog management we need to know if we have been
903 * paused during the last interval, so capture that here.
905 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
906 stats->xoffrxc += pause_frames;
907 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
908 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
909 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
910 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
911 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
912 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
913 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
914 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
915 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
916 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
917 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
918 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
921 * For the 64-bit byte counters the low dword must be read first.
922 * Both registers clear on the read of the high dword.
925 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
926 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
927 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
928 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
930 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
931 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
932 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
933 stats->roc += E1000_READ_REG(hw, E1000_ROC);
934 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
936 stats->tor += E1000_READ_REG(hw, E1000_TORH);
937 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
939 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
940 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
941 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
942 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
943 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
944 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
945 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
946 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
947 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
948 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
950 /* Interrupt Counts */
952 if (hw->mac.type >= e1000_82571) {
953 stats->iac += E1000_READ_REG(hw, E1000_IAC);
954 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
955 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
956 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
957 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
958 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
959 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
960 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
961 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
964 if (hw->mac.type >= e1000_82543) {
965 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
966 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
967 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
968 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
969 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
970 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
973 if (rte_stats == NULL)
977 rte_stats->imissed = stats->mpc;
978 rte_stats->ierrors = stats->crcerrs +
979 stats->rlec + stats->ruc + stats->roc +
980 stats->rxerrc + stats->algnerrc + stats->cexterr;
983 rte_stats->oerrors = stats->ecol + stats->latecol;
985 rte_stats->ipackets = stats->gprc;
986 rte_stats->opackets = stats->gptc;
987 rte_stats->ibytes = stats->gorc;
988 rte_stats->obytes = stats->gotc;
993 eth_em_stats_reset(struct rte_eth_dev *dev)
995 struct e1000_hw_stats *hw_stats =
996 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
998 /* HW registers are cleared on read */
999 eth_em_stats_get(dev, NULL);
1001 /* Reset software totals */
1002 memset(hw_stats, 0, sizeof(*hw_stats));
1008 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1010 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1011 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1012 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1014 em_rxq_intr_enable(hw);
1015 rte_intr_ack(intr_handle);
1021 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1023 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1025 em_rxq_intr_disable(hw);
1031 em_get_max_pktlen(struct rte_eth_dev *dev)
1033 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1035 switch (hw->mac.type) {
1039 case e1000_ich10lan:
1045 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1050 /* Adapters that do not support jumbo frames */
1052 return RTE_ETHER_MAX_LEN;
1054 return MAX_JUMBO_FRAME_SIZE;
1059 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1061 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1063 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1064 dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1065 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1068 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1069 * Unfortunatelly, all these nics have just one TX context.
1070 * So we have few choises for TX:
1071 * - Use just one TX queue.
1072 * - Allow cksum offload only for one TX queue.
1073 * - Don't allow TX cksum offload at all.
1074 * For now, option #1 was chosen.
1075 * To use second RX queue we have to use extended RX descriptor
1076 * (Multiple Receive Queues are mutually exclusive with UDP
1077 * fragmentation and are not supported when a legacy receive
1078 * descriptor format is used).
1079 * Which means separate RX routinies - as legacy nics (82540, 82545)
1080 * don't support extended RXD.
1081 * To avoid it we support just one RX queue for now (no RSS).
1084 dev_info->max_rx_queues = 1;
1085 dev_info->max_tx_queues = 1;
1087 dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1088 dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1089 dev_info->rx_queue_offload_capa;
1090 dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1091 dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1092 dev_info->tx_queue_offload_capa;
1094 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1095 .nb_max = E1000_MAX_RING_DESC,
1096 .nb_min = E1000_MIN_RING_DESC,
1097 .nb_align = EM_RXD_ALIGN,
1100 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1101 .nb_max = E1000_MAX_RING_DESC,
1102 .nb_min = E1000_MIN_RING_DESC,
1103 .nb_align = EM_TXD_ALIGN,
1104 .nb_seg_max = EM_TX_MAX_SEG,
1105 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1108 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1109 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1112 /* Preferred queue parameters */
1113 dev_info->default_rxportconf.nb_queues = 1;
1114 dev_info->default_txportconf.nb_queues = 1;
1115 dev_info->default_txportconf.ring_size = 256;
1116 dev_info->default_rxportconf.ring_size = 256;
1121 /* return 0 means link status changed, -1 means not changed */
1123 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1125 struct e1000_hw *hw =
1126 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127 struct rte_eth_link link;
1131 hw->mac.get_link_status = 1;
1133 /* possible wait-to-complete in up to 9 seconds */
1134 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1135 /* Read the real link status */
1136 switch (hw->phy.media_type) {
1137 case e1000_media_type_copper:
1138 /* Do the work to read phy */
1139 e1000_check_for_link(hw);
1140 link_up = !hw->mac.get_link_status;
1143 case e1000_media_type_fiber:
1144 e1000_check_for_link(hw);
1145 link_up = (E1000_READ_REG(hw, E1000_STATUS) &
1149 case e1000_media_type_internal_serdes:
1150 e1000_check_for_link(hw);
1151 link_up = hw->mac.serdes_has_link;
1157 if (link_up || wait_to_complete == 0)
1159 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1161 memset(&link, 0, sizeof(link));
1163 /* Now we check if a transition has happened */
1165 uint16_t duplex, speed;
1166 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1167 link.link_duplex = (duplex == FULL_DUPLEX) ?
1168 ETH_LINK_FULL_DUPLEX :
1169 ETH_LINK_HALF_DUPLEX;
1170 link.link_speed = speed;
1171 link.link_status = ETH_LINK_UP;
1172 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1173 ETH_LINK_SPEED_FIXED);
1175 link.link_speed = ETH_SPEED_NUM_NONE;
1176 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1177 link.link_status = ETH_LINK_DOWN;
1178 link.link_autoneg = ETH_LINK_FIXED;
1181 return rte_eth_linkstatus_set(dev, &link);
1185 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1186 * For ASF and Pass Through versions of f/w this means
1187 * that the driver is loaded. For AMT version type f/w
1188 * this means that the network i/f is open.
1191 em_hw_control_acquire(struct e1000_hw *hw)
1193 uint32_t ctrl_ext, swsm;
1195 /* Let firmware know the driver has taken over */
1196 if (hw->mac.type == e1000_82573) {
1197 swsm = E1000_READ_REG(hw, E1000_SWSM);
1198 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1201 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1202 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1203 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1208 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1209 * For ASF and Pass Through versions of f/w this means that the
1210 * driver is no longer loaded. For AMT versions of the
1211 * f/w this means that the network i/f is closed.
1214 em_hw_control_release(struct e1000_hw *hw)
1216 uint32_t ctrl_ext, swsm;
1218 /* Let firmware taken over control of h/w */
1219 if (hw->mac.type == e1000_82573) {
1220 swsm = E1000_READ_REG(hw, E1000_SWSM);
1221 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1223 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1224 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1225 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1230 * Bit of a misnomer, what this really means is
1231 * to enable OS management of the system... aka
1232 * to disable special hardware management features.
1235 em_init_manageability(struct e1000_hw *hw)
1237 if (e1000_enable_mng_pass_thru(hw)) {
1238 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1239 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1241 /* disable hardware interception of ARP */
1242 manc &= ~(E1000_MANC_ARP_EN);
1244 /* enable receiving management packets to the host */
1245 manc |= E1000_MANC_EN_MNG2HOST;
1246 manc2h |= 1 << 5; /* Mng Port 623 */
1247 manc2h |= 1 << 6; /* Mng Port 664 */
1248 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1249 E1000_WRITE_REG(hw, E1000_MANC, manc);
1254 * Give control back to hardware management
1255 * controller if there is one.
1258 em_release_manageability(struct e1000_hw *hw)
1262 if (e1000_enable_mng_pass_thru(hw)) {
1263 manc = E1000_READ_REG(hw, E1000_MANC);
1265 /* re-enable hardware interception of ARP */
1266 manc |= E1000_MANC_ARP_EN;
1267 manc &= ~E1000_MANC_EN_MNG2HOST;
1269 E1000_WRITE_REG(hw, E1000_MANC, manc);
1274 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1276 struct e1000_hw *hw =
1277 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1280 rctl = E1000_READ_REG(hw, E1000_RCTL);
1281 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1282 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1288 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1290 struct e1000_hw *hw =
1291 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1294 rctl = E1000_READ_REG(hw, E1000_RCTL);
1295 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1296 if (dev->data->all_multicast == 1)
1297 rctl |= E1000_RCTL_MPE;
1299 rctl &= (~E1000_RCTL_MPE);
1300 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1306 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1308 struct e1000_hw *hw =
1309 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1312 rctl = E1000_READ_REG(hw, E1000_RCTL);
1313 rctl |= E1000_RCTL_MPE;
1314 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1320 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1322 struct e1000_hw *hw =
1323 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326 if (dev->data->promiscuous == 1)
1327 return 0; /* must remain in all_multicast mode */
1328 rctl = E1000_READ_REG(hw, E1000_RCTL);
1329 rctl &= (~E1000_RCTL_MPE);
1330 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1336 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1338 struct e1000_hw *hw =
1339 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340 struct e1000_vfta * shadow_vfta =
1341 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1346 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1347 E1000_VFTA_ENTRY_MASK);
1348 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1349 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1354 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1356 /* update local VFTA copy */
1357 shadow_vfta->vfta[vid_idx] = vfta;
1363 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1365 struct e1000_hw *hw =
1366 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1369 /* Filter Table Disable */
1370 reg = E1000_READ_REG(hw, E1000_RCTL);
1371 reg &= ~E1000_RCTL_CFIEN;
1372 reg &= ~E1000_RCTL_VFE;
1373 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1377 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1379 struct e1000_hw *hw =
1380 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1381 struct e1000_vfta * shadow_vfta =
1382 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1386 /* Filter Table Enable, CFI not used for packet acceptance */
1387 reg = E1000_READ_REG(hw, E1000_RCTL);
1388 reg &= ~E1000_RCTL_CFIEN;
1389 reg |= E1000_RCTL_VFE;
1390 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1392 /* restore vfta from local copy */
1393 for (i = 0; i < IGB_VFTA_SIZE; i++)
1394 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1398 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1400 struct e1000_hw *hw =
1401 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1404 /* VLAN Mode Disable */
1405 reg = E1000_READ_REG(hw, E1000_CTRL);
1406 reg &= ~E1000_CTRL_VME;
1407 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1412 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1414 struct e1000_hw *hw =
1415 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418 /* VLAN Mode Enable */
1419 reg = E1000_READ_REG(hw, E1000_CTRL);
1420 reg |= E1000_CTRL_VME;
1421 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1425 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1427 struct rte_eth_rxmode *rxmode;
1429 rxmode = &dev->data->dev_conf.rxmode;
1430 if(mask & ETH_VLAN_STRIP_MASK){
1431 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1432 em_vlan_hw_strip_enable(dev);
1434 em_vlan_hw_strip_disable(dev);
1437 if(mask & ETH_VLAN_FILTER_MASK){
1438 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1439 em_vlan_hw_filter_enable(dev);
1441 em_vlan_hw_filter_disable(dev);
1448 * It enables the interrupt mask and then enable the interrupt.
1451 * Pointer to struct rte_eth_dev.
1454 * - On success, zero.
1455 * - On failure, a negative value.
1458 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1461 struct e1000_hw *hw =
1462 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1464 /* clear interrupt */
1465 E1000_READ_REG(hw, E1000_ICR);
1466 regval = E1000_READ_REG(hw, E1000_IMS);
1467 E1000_WRITE_REG(hw, E1000_IMS,
1468 regval | E1000_ICR_LSC | E1000_ICR_OTHER);
1473 * It clears the interrupt causes and enables the interrupt.
1474 * It will be called once only during nic initialized.
1477 * Pointer to struct rte_eth_dev.
1480 * - On success, zero.
1481 * - On failure, a negative value.
1484 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1486 struct e1000_hw *hw =
1487 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489 E1000_READ_REG(hw, E1000_ICR);
1490 em_rxq_intr_enable(hw);
1495 * It enable receive packet interrupt.
1497 * Pointer to struct e1000_hw
1502 em_rxq_intr_enable(struct e1000_hw *hw)
1504 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1505 E1000_WRITE_FLUSH(hw);
1509 * It disabled lsc interrupt.
1511 * Pointer to struct e1000_hw
1516 em_lsc_intr_disable(struct e1000_hw *hw)
1518 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC | E1000_IMS_OTHER);
1519 E1000_WRITE_FLUSH(hw);
1523 * It disabled receive packet interrupt.
1525 * Pointer to struct e1000_hw
1530 em_rxq_intr_disable(struct e1000_hw *hw)
1532 E1000_READ_REG(hw, E1000_ICR);
1533 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1534 E1000_WRITE_FLUSH(hw);
1538 * It reads ICR and gets interrupt causes, check it and set a bit flag
1539 * to update link status.
1542 * Pointer to struct rte_eth_dev.
1545 * - On success, zero.
1546 * - On failure, a negative value.
1549 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1552 struct e1000_hw *hw =
1553 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1554 struct e1000_interrupt *intr =
1555 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1557 /* read-on-clear nic registers here */
1558 icr = E1000_READ_REG(hw, E1000_ICR);
1559 if (icr & E1000_ICR_LSC) {
1560 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1567 * It executes link_update after knowing an interrupt is prsent.
1570 * Pointer to struct rte_eth_dev.
1573 * - On success, zero.
1574 * - On failure, a negative value.
1577 eth_em_interrupt_action(struct rte_eth_dev *dev,
1578 struct rte_intr_handle *intr_handle)
1580 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1581 struct e1000_hw *hw =
1582 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583 struct e1000_interrupt *intr =
1584 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1585 struct rte_eth_link link;
1588 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1591 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1592 rte_intr_ack(intr_handle);
1594 /* set get_link_status to check register later */
1595 hw->mac.get_link_status = 1;
1596 ret = eth_em_link_update(dev, 0);
1598 /* check if link has changed */
1602 rte_eth_linkstatus_get(dev, &link);
1604 if (link.link_status) {
1605 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1606 dev->data->port_id, link.link_speed,
1607 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1608 "full-duplex" : "half-duplex");
1610 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1612 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
1613 pci_dev->addr.domain, pci_dev->addr.bus,
1614 pci_dev->addr.devid, pci_dev->addr.function);
1620 * Interrupt handler which shall be registered at first.
1623 * Pointer to interrupt handle.
1625 * The address of parameter (struct rte_eth_dev *) regsitered before.
1631 eth_em_interrupt_handler(void *param)
1633 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1635 eth_em_interrupt_get_status(dev);
1636 eth_em_interrupt_action(dev, dev->intr_handle);
1637 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1641 eth_em_led_on(struct rte_eth_dev *dev)
1643 struct e1000_hw *hw;
1645 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1650 eth_em_led_off(struct rte_eth_dev *dev)
1652 struct e1000_hw *hw;
1654 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1659 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1661 struct e1000_hw *hw;
1666 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667 fc_conf->pause_time = hw->fc.pause_time;
1668 fc_conf->high_water = hw->fc.high_water;
1669 fc_conf->low_water = hw->fc.low_water;
1670 fc_conf->send_xon = hw->fc.send_xon;
1671 fc_conf->autoneg = hw->mac.autoneg;
1674 * Return rx_pause and tx_pause status according to actual setting of
1675 * the TFCE and RFCE bits in the CTRL register.
1677 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1678 if (ctrl & E1000_CTRL_TFCE)
1683 if (ctrl & E1000_CTRL_RFCE)
1688 if (rx_pause && tx_pause)
1689 fc_conf->mode = RTE_FC_FULL;
1691 fc_conf->mode = RTE_FC_RX_PAUSE;
1693 fc_conf->mode = RTE_FC_TX_PAUSE;
1695 fc_conf->mode = RTE_FC_NONE;
1701 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1703 struct e1000_hw *hw;
1705 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1711 uint32_t rx_buf_size;
1712 uint32_t max_high_water;
1715 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1716 if (fc_conf->autoneg != hw->mac.autoneg)
1718 rx_buf_size = em_get_rx_buffer_size(hw);
1719 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1721 /* At least reserve one Ethernet frame for watermark */
1722 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
1723 if ((fc_conf->high_water > max_high_water) ||
1724 (fc_conf->high_water < fc_conf->low_water)) {
1725 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1726 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1730 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1731 hw->fc.pause_time = fc_conf->pause_time;
1732 hw->fc.high_water = fc_conf->high_water;
1733 hw->fc.low_water = fc_conf->low_water;
1734 hw->fc.send_xon = fc_conf->send_xon;
1736 err = e1000_setup_link_generic(hw);
1737 if (err == E1000_SUCCESS) {
1739 /* check if we want to forward MAC frames - driver doesn't have native
1740 * capability to do that, so we'll write the registers ourselves */
1742 rctl = E1000_READ_REG(hw, E1000_RCTL);
1744 /* set or clear MFLCN.PMCF bit depending on configuration */
1745 if (fc_conf->mac_ctrl_frame_fwd != 0)
1746 rctl |= E1000_RCTL_PMCF;
1748 rctl &= ~E1000_RCTL_PMCF;
1750 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1751 E1000_WRITE_FLUSH(hw);
1756 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1761 eth_em_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1762 uint32_t index, __rte_unused uint32_t pool)
1764 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766 return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1770 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1772 uint8_t addr[RTE_ETHER_ADDR_LEN];
1773 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775 memset(addr, 0, sizeof(addr));
1777 e1000_rar_set(hw, addr, index);
1781 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1782 struct rte_ether_addr *addr)
1784 eth_em_rar_clear(dev, 0);
1786 return eth_em_rar_set(dev, (void *)addr, 0, 0);
1790 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1792 struct rte_eth_dev_info dev_info;
1793 struct e1000_hw *hw;
1794 uint32_t frame_size;
1798 ret = eth_em_infos_get(dev, &dev_info);
1802 frame_size = mtu + E1000_ETH_OVERHEAD;
1804 /* check that mtu is within the allowed range */
1805 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
1808 /* refuse mtu that requires the support of scattered packets when this
1809 * feature has not been enabled before. */
1810 if (!dev->data->scattered_rx &&
1811 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1814 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1815 rctl = E1000_READ_REG(hw, E1000_RCTL);
1817 /* switch to jumbo mode if needed */
1818 if (frame_size > E1000_ETH_MAX_LEN) {
1819 dev->data->dev_conf.rxmode.offloads |=
1820 DEV_RX_OFFLOAD_JUMBO_FRAME;
1821 rctl |= E1000_RCTL_LPE;
1823 dev->data->dev_conf.rxmode.offloads &=
1824 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1825 rctl &= ~E1000_RCTL_LPE;
1827 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1829 /* update max frame size */
1830 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1835 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1836 struct rte_ether_addr *mc_addr_set,
1837 uint32_t nb_mc_addr)
1839 struct e1000_hw *hw;
1841 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1846 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1847 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1848 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1850 /* see e1000_logs.c */
1851 RTE_INIT(igb_init_log)
1853 e1000_igb_init_log();