4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_bus_pci.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_ethdev_pci.h>
50 #include <rte_memory.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "base/e1000_api.h"
58 #include "e1000_ethdev.h"
60 #define EM_EIAC 0x000DC
62 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
65 static int eth_em_configure(struct rte_eth_dev *dev);
66 static int eth_em_start(struct rte_eth_dev *dev);
67 static void eth_em_stop(struct rte_eth_dev *dev);
68 static void eth_em_close(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
73 static int eth_em_link_update(struct rte_eth_dev *dev,
74 int wait_to_complete);
75 static int eth_em_stats_get(struct rte_eth_dev *dev,
76 struct rte_eth_stats *rte_stats);
77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
78 static void eth_em_infos_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
81 struct rte_eth_fc_conf *fc_conf);
82 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
83 struct rte_eth_fc_conf *fc_conf);
84 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
87 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
88 struct rte_intr_handle *handle);
89 static void eth_em_interrupt_handler(void *param);
91 static int em_hw_init(struct e1000_hw *hw);
92 static int em_hardware_init(struct e1000_hw *hw);
93 static void em_hw_control_acquire(struct e1000_hw *hw);
94 static void em_hw_control_release(struct e1000_hw *hw);
95 static void em_init_manageability(struct e1000_hw *hw);
96 static void em_release_manageability(struct e1000_hw *hw);
98 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
100 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
101 uint16_t vlan_id, int on);
102 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
103 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
106 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
109 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
110 uint16_t vlan_id, int on);
113 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
115 static void em_lsc_intr_disable(struct e1000_hw *hw);
116 static void em_rxq_intr_enable(struct e1000_hw *hw);
117 static void em_rxq_intr_disable(struct e1000_hw *hw);
119 static int eth_em_led_on(struct rte_eth_dev *dev);
120 static int eth_em_led_off(struct rte_eth_dev *dev);
122 static int em_get_rx_buffer_size(struct e1000_hw *hw);
123 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
124 uint32_t index, uint32_t pool);
125 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
127 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
128 struct ether_addr *mc_addr_set,
129 uint32_t nb_mc_addr);
131 #define EM_FC_PAUSE_TIME 0x0680
132 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
133 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
135 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
138 * The set of PCI devices this driver supports
140 static const struct rte_pci_id pci_id_em_map[] = {
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
160 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
161 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
162 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
163 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
164 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
165 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
166 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
167 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
168 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
169 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
170 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
171 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
172 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
173 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
174 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
175 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
176 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
177 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
178 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
179 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
180 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
181 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
182 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
183 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
184 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
185 { .vendor_id = 0, /* sentinel */ },
188 static const struct eth_dev_ops eth_em_ops = {
189 .dev_configure = eth_em_configure,
190 .dev_start = eth_em_start,
191 .dev_stop = eth_em_stop,
192 .dev_close = eth_em_close,
193 .promiscuous_enable = eth_em_promiscuous_enable,
194 .promiscuous_disable = eth_em_promiscuous_disable,
195 .allmulticast_enable = eth_em_allmulticast_enable,
196 .allmulticast_disable = eth_em_allmulticast_disable,
197 .link_update = eth_em_link_update,
198 .stats_get = eth_em_stats_get,
199 .stats_reset = eth_em_stats_reset,
200 .dev_infos_get = eth_em_infos_get,
201 .mtu_set = eth_em_mtu_set,
202 .vlan_filter_set = eth_em_vlan_filter_set,
203 .vlan_offload_set = eth_em_vlan_offload_set,
204 .rx_queue_setup = eth_em_rx_queue_setup,
205 .rx_queue_release = eth_em_rx_queue_release,
206 .rx_queue_count = eth_em_rx_queue_count,
207 .rx_descriptor_done = eth_em_rx_descriptor_done,
208 .rx_descriptor_status = eth_em_rx_descriptor_status,
209 .tx_descriptor_status = eth_em_tx_descriptor_status,
210 .tx_queue_setup = eth_em_tx_queue_setup,
211 .tx_queue_release = eth_em_tx_queue_release,
212 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
213 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
214 .dev_led_on = eth_em_led_on,
215 .dev_led_off = eth_em_led_off,
216 .flow_ctrl_get = eth_em_flow_ctrl_get,
217 .flow_ctrl_set = eth_em_flow_ctrl_set,
218 .mac_addr_add = eth_em_rar_set,
219 .mac_addr_remove = eth_em_rar_clear,
220 .set_mc_addr_list = eth_em_set_mc_addr_list,
221 .rxq_info_get = em_rxq_info_get,
222 .txq_info_get = em_txq_info_get,
226 * Atomically reads the link status information from global
227 * structure rte_eth_dev.
230 * - Pointer to the structure rte_eth_dev to read from.
231 * - Pointer to the buffer to be saved with the link status.
234 * - On success, zero.
235 * - On failure, negative value.
238 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
239 struct rte_eth_link *link)
241 struct rte_eth_link *dst = link;
242 struct rte_eth_link *src = &(dev->data->dev_link);
244 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
245 *(uint64_t *)src) == 0)
252 * Atomically writes the link status information into global
253 * structure rte_eth_dev.
256 * - Pointer to the structure rte_eth_dev to read from.
257 * - Pointer to the buffer to be saved with the link status.
260 * - On success, zero.
261 * - On failure, negative value.
264 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
265 struct rte_eth_link *link)
267 struct rte_eth_link *dst = &(dev->data->dev_link);
268 struct rte_eth_link *src = link;
270 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
271 *(uint64_t *)src) == 0)
278 * eth_em_dev_is_ich8 - Check for ICH8 device
279 * @hw: pointer to the HW structure
281 * return TRUE for ICH8, otherwise FALSE
284 eth_em_dev_is_ich8(struct e1000_hw *hw)
286 DEBUGFUNC("eth_em_dev_is_ich8");
288 switch (hw->device_id) {
289 case E1000_DEV_ID_PCH_LPT_I217_LM:
290 case E1000_DEV_ID_PCH_LPT_I217_V:
291 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
292 case E1000_DEV_ID_PCH_LPTLP_I218_V:
293 case E1000_DEV_ID_PCH_I218_V2:
294 case E1000_DEV_ID_PCH_I218_LM2:
295 case E1000_DEV_ID_PCH_I218_V3:
296 case E1000_DEV_ID_PCH_I218_LM3:
297 case E1000_DEV_ID_PCH_SPT_I219_LM:
298 case E1000_DEV_ID_PCH_SPT_I219_V:
299 case E1000_DEV_ID_PCH_SPT_I219_LM2:
300 case E1000_DEV_ID_PCH_SPT_I219_V2:
301 case E1000_DEV_ID_PCH_LBG_I219_LM3:
302 case E1000_DEV_ID_PCH_SPT_I219_LM4:
303 case E1000_DEV_ID_PCH_SPT_I219_V4:
304 case E1000_DEV_ID_PCH_SPT_I219_LM5:
305 case E1000_DEV_ID_PCH_SPT_I219_V5:
306 case E1000_DEV_ID_PCH_CNP_I219_LM6:
307 case E1000_DEV_ID_PCH_CNP_I219_V6:
308 case E1000_DEV_ID_PCH_CNP_I219_LM7:
309 case E1000_DEV_ID_PCH_CNP_I219_V7:
317 eth_em_dev_init(struct rte_eth_dev *eth_dev)
319 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
320 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
321 struct e1000_adapter *adapter =
322 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
323 struct e1000_hw *hw =
324 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
325 struct e1000_vfta * shadow_vfta =
326 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
328 eth_dev->dev_ops = ð_em_ops;
329 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
330 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
331 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
333 /* for secondary processes, we don't initialise any further as primary
334 * has already done this work. Only check we don't need a different
336 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
337 if (eth_dev->data->scattered_rx)
338 eth_dev->rx_pkt_burst =
339 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
343 rte_eth_copy_pci_info(eth_dev, pci_dev);
345 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
346 hw->device_id = pci_dev->id.device_id;
347 adapter->stopped = 0;
349 /* For ICH8 support we'll need to map the flash memory BAR */
350 if (eth_em_dev_is_ich8(hw))
351 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
353 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
354 em_hw_init(hw) != 0) {
355 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
357 eth_dev->data->port_id, pci_dev->id.vendor_id,
358 pci_dev->id.device_id);
362 /* Allocate memory for storing MAC addresses */
363 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
364 hw->mac.rar_entry_count, 0);
365 if (eth_dev->data->mac_addrs == NULL) {
366 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
367 "store MAC addresses",
368 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
372 /* Copy the permanent MAC address */
373 ether_addr_copy((struct ether_addr *) hw->mac.addr,
374 eth_dev->data->mac_addrs);
376 /* initialize the vfta */
377 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
379 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
380 eth_dev->data->port_id, pci_dev->id.vendor_id,
381 pci_dev->id.device_id);
383 rte_intr_callback_register(intr_handle,
384 eth_em_interrupt_handler, eth_dev);
390 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
392 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
393 struct e1000_adapter *adapter =
394 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
395 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
397 PMD_INIT_FUNC_TRACE();
399 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
402 if (adapter->stopped == 0)
403 eth_em_close(eth_dev);
405 eth_dev->dev_ops = NULL;
406 eth_dev->rx_pkt_burst = NULL;
407 eth_dev->tx_pkt_burst = NULL;
409 rte_free(eth_dev->data->mac_addrs);
410 eth_dev->data->mac_addrs = NULL;
412 /* disable uio intr before callback unregister */
413 rte_intr_disable(intr_handle);
414 rte_intr_callback_unregister(intr_handle,
415 eth_em_interrupt_handler, eth_dev);
420 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
421 struct rte_pci_device *pci_dev)
423 return rte_eth_dev_pci_generic_probe(pci_dev,
424 sizeof(struct e1000_adapter), eth_em_dev_init);
427 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
429 return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
432 static struct rte_pci_driver rte_em_pmd = {
433 .id_table = pci_id_em_map,
434 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
435 RTE_PCI_DRV_IOVA_AS_VA,
436 .probe = eth_em_pci_probe,
437 .remove = eth_em_pci_remove,
441 em_hw_init(struct e1000_hw *hw)
445 diag = hw->mac.ops.init_params(hw);
447 PMD_INIT_LOG(ERR, "MAC Initialization Error");
450 diag = hw->nvm.ops.init_params(hw);
452 PMD_INIT_LOG(ERR, "NVM Initialization Error");
455 diag = hw->phy.ops.init_params(hw);
457 PMD_INIT_LOG(ERR, "PHY Initialization Error");
460 (void) e1000_get_bus_info(hw);
463 hw->phy.autoneg_wait_to_complete = 0;
464 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
466 e1000_init_script_state_82541(hw, TRUE);
467 e1000_set_tbi_compatibility_82543(hw, TRUE);
470 if (hw->phy.media_type == e1000_media_type_copper) {
471 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
472 hw->phy.disable_polarity_correction = 0;
473 hw->phy.ms_type = e1000_ms_hw_default;
477 * Start from a known state, this is important in reading the nvm
482 /* Make sure we have a good EEPROM before we read from it */
483 if (e1000_validate_nvm_checksum(hw) < 0) {
485 * Some PCI-E parts fail the first check due to
486 * the link being in sleep state, call it again,
487 * if it fails a second time its a real issue.
489 diag = e1000_validate_nvm_checksum(hw);
491 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
496 /* Read the permanent MAC address out of the EEPROM */
497 diag = e1000_read_mac_addr(hw);
499 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
503 /* Now initialize the hardware */
504 diag = em_hardware_init(hw);
506 PMD_INIT_LOG(ERR, "Hardware initialization failed");
510 hw->mac.get_link_status = 1;
512 /* Indicate SOL/IDER usage */
513 diag = e1000_check_reset_block(hw);
515 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
521 em_hw_control_release(hw);
526 eth_em_configure(struct rte_eth_dev *dev)
528 struct e1000_interrupt *intr =
529 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
531 PMD_INIT_FUNC_TRACE();
532 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
533 PMD_INIT_FUNC_TRACE();
539 em_set_pba(struct e1000_hw *hw)
544 * Packet Buffer Allocation (PBA)
545 * Writing PBA sets the receive portion of the buffer
546 * the remainder is used for the transmit buffer.
547 * Devices before the 82547 had a Packet Buffer of 64K.
548 * After the 82547 the buffer was reduced to 40K.
550 switch (hw->mac.type) {
552 case e1000_82547_rev_2:
553 /* 82547: Total Packet Buffer is 40K */
554 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
558 case e1000_80003es2lan:
559 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
561 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
562 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
566 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
583 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
586 E1000_WRITE_REG(hw, E1000_PBA, pba);
590 eth_em_start(struct rte_eth_dev *dev)
592 struct e1000_adapter *adapter =
593 E1000_DEV_PRIVATE(dev->data->dev_private);
594 struct e1000_hw *hw =
595 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
596 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
597 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
599 uint32_t intr_vector = 0;
604 PMD_INIT_FUNC_TRACE();
608 e1000_power_up_phy(hw);
610 /* Set default PBA value */
613 /* Put the address into the Receive Address Array */
614 e1000_rar_set(hw, hw->mac.addr, 0);
617 * With the 82571 adapter, RAR[0] may be overwritten
618 * when the other port is reset, we make a duplicate
619 * in RAR[14] for that eventuality, this assures
620 * the interface continues to function.
622 if (hw->mac.type == e1000_82571) {
623 e1000_set_laa_state_82571(hw, TRUE);
624 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
627 /* Initialize the hardware */
628 if (em_hardware_init(hw)) {
629 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
633 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
635 /* Configure for OS presence */
636 em_init_manageability(hw);
638 if (dev->data->dev_conf.intr_conf.rxq != 0) {
639 intr_vector = dev->data->nb_rx_queues;
640 if (rte_intr_efd_enable(intr_handle, intr_vector))
644 if (rte_intr_dp_is_en(intr_handle)) {
645 intr_handle->intr_vec =
646 rte_zmalloc("intr_vec",
647 dev->data->nb_rx_queues * sizeof(int), 0);
648 if (intr_handle->intr_vec == NULL) {
649 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
650 " intr_vec", dev->data->nb_rx_queues);
654 /* enable rx interrupt */
655 em_rxq_intr_enable(hw);
660 ret = eth_em_rx_init(dev);
662 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
663 em_dev_clear_queues(dev);
667 e1000_clear_hw_cntrs_base_generic(hw);
669 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
670 ETH_VLAN_EXTEND_MASK;
671 ret = eth_em_vlan_offload_set(dev, mask);
673 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
674 em_dev_clear_queues(dev);
678 /* Set Interrupt Throttling Rate to maximum allowed value. */
679 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
681 /* Setup link speed and duplex */
682 speeds = &dev->data->dev_conf.link_speeds;
683 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
684 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
688 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
691 hw->phy.autoneg_advertised = 0;
693 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
694 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
695 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
697 goto error_invalid_config;
699 if (*speeds & ETH_LINK_SPEED_10M_HD) {
700 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
703 if (*speeds & ETH_LINK_SPEED_10M) {
704 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
707 if (*speeds & ETH_LINK_SPEED_100M_HD) {
708 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
711 if (*speeds & ETH_LINK_SPEED_100M) {
712 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
715 if (*speeds & ETH_LINK_SPEED_1G) {
716 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
719 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
720 goto error_invalid_config;
722 /* Set/reset the mac.autoneg based on the link speed,
727 hw->mac.forced_speed_duplex =
728 hw->phy.autoneg_advertised;
734 e1000_setup_link(hw);
736 if (rte_intr_allow_others(intr_handle)) {
737 /* check if lsc interrupt is enabled */
738 if (dev->data->dev_conf.intr_conf.lsc != 0) {
739 ret = eth_em_interrupt_setup(dev);
741 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
742 em_dev_clear_queues(dev);
747 rte_intr_callback_unregister(intr_handle,
748 eth_em_interrupt_handler,
750 if (dev->data->dev_conf.intr_conf.lsc != 0)
751 PMD_INIT_LOG(INFO, "lsc won't enable because of"
752 " no intr multiplexn");
754 /* check if rxq interrupt is enabled */
755 if (dev->data->dev_conf.intr_conf.rxq != 0)
756 eth_em_rxq_interrupt_setup(dev);
758 rte_intr_enable(intr_handle);
760 adapter->stopped = 0;
762 PMD_INIT_LOG(DEBUG, "<<");
766 error_invalid_config:
767 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
768 dev->data->dev_conf.link_speeds, dev->data->port_id);
769 em_dev_clear_queues(dev);
773 /*********************************************************************
775 * This routine disables all traffic on the adapter by issuing a
776 * global reset on the MAC.
778 **********************************************************************/
780 eth_em_stop(struct rte_eth_dev *dev)
782 struct rte_eth_link link;
783 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
784 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
785 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
787 em_rxq_intr_disable(hw);
788 em_lsc_intr_disable(hw);
791 if (hw->mac.type >= e1000_82544)
792 E1000_WRITE_REG(hw, E1000_WUC, 0);
794 /* Power down the phy. Needed to make the link go down */
795 e1000_power_down_phy(hw);
797 em_dev_clear_queues(dev);
799 /* clear the recorded link status */
800 memset(&link, 0, sizeof(link));
801 rte_em_dev_atomic_write_link_status(dev, &link);
803 if (!rte_intr_allow_others(intr_handle))
804 /* resume to the default handler */
805 rte_intr_callback_register(intr_handle,
806 eth_em_interrupt_handler,
809 /* Clean datapath event and queue/vec mapping */
810 rte_intr_efd_disable(intr_handle);
811 if (intr_handle->intr_vec != NULL) {
812 rte_free(intr_handle->intr_vec);
813 intr_handle->intr_vec = NULL;
818 eth_em_close(struct rte_eth_dev *dev)
820 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
821 struct e1000_adapter *adapter =
822 E1000_DEV_PRIVATE(dev->data->dev_private);
825 adapter->stopped = 1;
826 em_dev_free_queues(dev);
827 e1000_phy_hw_reset(hw);
828 em_release_manageability(hw);
829 em_hw_control_release(hw);
833 em_get_rx_buffer_size(struct e1000_hw *hw)
835 uint32_t rx_buf_size;
837 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
841 /*********************************************************************
843 * Initialize the hardware
845 **********************************************************************/
847 em_hardware_init(struct e1000_hw *hw)
849 uint32_t rx_buf_size;
852 /* Issue a global reset */
855 /* Let the firmware know the OS is in control */
856 em_hw_control_acquire(hw);
859 * These parameters control the automatic generation (Tx) and
860 * response (Rx) to Ethernet PAUSE frames.
861 * - High water mark should allow for at least two standard size (1518)
862 * frames to be received after sending an XOFF.
863 * - Low water mark works best when it is very near the high water mark.
864 * This allows the receiver to restart by sending XON when it has
865 * drained a bit. Here we use an arbitrary value of 1500 which will
866 * restart after one full frame is pulled from the buffer. There
867 * could be several smaller frames in the buffer and if so they will
868 * not trigger the XON until their total number reduces the buffer
870 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
872 rx_buf_size = em_get_rx_buffer_size(hw);
874 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
875 hw->fc.low_water = hw->fc.high_water - 1500;
877 if (hw->mac.type == e1000_80003es2lan)
878 hw->fc.pause_time = UINT16_MAX;
880 hw->fc.pause_time = EM_FC_PAUSE_TIME;
884 /* Set Flow control, use the tunable location if sane */
885 if (em_fc_setting <= e1000_fc_full)
886 hw->fc.requested_mode = em_fc_setting;
888 hw->fc.requested_mode = e1000_fc_none;
890 /* Workaround: no TX flow ctrl for PCH */
891 if (hw->mac.type == e1000_pchlan)
892 hw->fc.requested_mode = e1000_fc_rx_pause;
894 /* Override - settings for PCH2LAN, ya its magic :) */
895 if (hw->mac.type == e1000_pch2lan) {
896 hw->fc.high_water = 0x5C20;
897 hw->fc.low_water = 0x5048;
898 hw->fc.pause_time = 0x0650;
899 hw->fc.refresh_time = 0x0400;
900 } else if (hw->mac.type == e1000_pch_lpt ||
901 hw->mac.type == e1000_pch_spt ||
902 hw->mac.type == e1000_pch_cnp) {
903 hw->fc.requested_mode = e1000_fc_full;
906 diag = e1000_init_hw(hw);
909 e1000_check_for_link(hw);
913 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
915 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
917 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
918 struct e1000_hw_stats *stats =
919 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
922 if(hw->phy.media_type == e1000_media_type_copper ||
923 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
924 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
925 stats->sec += E1000_READ_REG(hw, E1000_SEC);
928 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
929 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
930 stats->scc += E1000_READ_REG(hw, E1000_SCC);
931 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
933 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
934 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
935 stats->colc += E1000_READ_REG(hw, E1000_COLC);
936 stats->dc += E1000_READ_REG(hw, E1000_DC);
937 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
938 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
939 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
942 * For watchdog management we need to know if we have been
943 * paused during the last interval, so capture that here.
945 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
946 stats->xoffrxc += pause_frames;
947 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
948 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
949 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
950 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
951 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
952 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
953 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
954 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
955 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
956 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
957 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
958 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
961 * For the 64-bit byte counters the low dword must be read first.
962 * Both registers clear on the read of the high dword.
965 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
966 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
967 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
968 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
970 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
971 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
972 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
973 stats->roc += E1000_READ_REG(hw, E1000_ROC);
974 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
976 stats->tor += E1000_READ_REG(hw, E1000_TORH);
977 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
979 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
980 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
981 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
982 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
983 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
984 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
985 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
986 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
987 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
988 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
990 /* Interrupt Counts */
992 if (hw->mac.type >= e1000_82571) {
993 stats->iac += E1000_READ_REG(hw, E1000_IAC);
994 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
995 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
996 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
997 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
998 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
999 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1000 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1001 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1004 if (hw->mac.type >= e1000_82543) {
1005 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1006 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1007 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1008 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1009 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1010 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1013 if (rte_stats == NULL)
1017 rte_stats->imissed = stats->mpc;
1018 rte_stats->ierrors = stats->crcerrs +
1019 stats->rlec + stats->ruc + stats->roc +
1020 stats->rxerrc + stats->algnerrc + stats->cexterr;
1023 rte_stats->oerrors = stats->ecol + stats->latecol;
1025 rte_stats->ipackets = stats->gprc;
1026 rte_stats->opackets = stats->gptc;
1027 rte_stats->ibytes = stats->gorc;
1028 rte_stats->obytes = stats->gotc;
1033 eth_em_stats_reset(struct rte_eth_dev *dev)
1035 struct e1000_hw_stats *hw_stats =
1036 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1038 /* HW registers are cleared on read */
1039 eth_em_stats_get(dev, NULL);
1041 /* Reset software totals */
1042 memset(hw_stats, 0, sizeof(*hw_stats));
1046 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1048 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1050 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1052 em_rxq_intr_enable(hw);
1053 rte_intr_enable(intr_handle);
1059 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1061 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1063 em_rxq_intr_disable(hw);
1069 em_get_max_pktlen(const struct e1000_hw *hw)
1071 switch (hw->mac.type) {
1075 case e1000_ich10lan:
1081 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1086 /* Adapters that do not support jumbo frames */
1088 return ETHER_MAX_LEN;
1090 return MAX_JUMBO_FRAME_SIZE;
1095 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1097 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1099 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1100 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1101 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1102 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1103 dev_info->rx_offload_capa =
1104 DEV_RX_OFFLOAD_VLAN_STRIP |
1105 DEV_RX_OFFLOAD_IPV4_CKSUM |
1106 DEV_RX_OFFLOAD_UDP_CKSUM |
1107 DEV_RX_OFFLOAD_TCP_CKSUM;
1108 dev_info->tx_offload_capa =
1109 DEV_TX_OFFLOAD_VLAN_INSERT |
1110 DEV_TX_OFFLOAD_IPV4_CKSUM |
1111 DEV_TX_OFFLOAD_UDP_CKSUM |
1112 DEV_TX_OFFLOAD_TCP_CKSUM;
1115 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1116 * Unfortunatelly, all these nics have just one TX context.
1117 * So we have few choises for TX:
1118 * - Use just one TX queue.
1119 * - Allow cksum offload only for one TX queue.
1120 * - Don't allow TX cksum offload at all.
1121 * For now, option #1 was chosen.
1122 * To use second RX queue we have to use extended RX descriptor
1123 * (Multiple Receive Queues are mutually exclusive with UDP
1124 * fragmentation and are not supported when a legacy receive
1125 * descriptor format is used).
1126 * Which means separate RX routinies - as legacy nics (82540, 82545)
1127 * don't support extended RXD.
1128 * To avoid it we support just one RX queue for now (no RSS).
1131 dev_info->max_rx_queues = 1;
1132 dev_info->max_tx_queues = 1;
1134 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1135 .nb_max = E1000_MAX_RING_DESC,
1136 .nb_min = E1000_MIN_RING_DESC,
1137 .nb_align = EM_RXD_ALIGN,
1140 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1141 .nb_max = E1000_MAX_RING_DESC,
1142 .nb_min = E1000_MIN_RING_DESC,
1143 .nb_align = EM_TXD_ALIGN,
1144 .nb_seg_max = EM_TX_MAX_SEG,
1145 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1148 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1149 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1153 /* return 0 means link status changed, -1 means not changed */
1155 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1157 struct e1000_hw *hw =
1158 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1159 struct rte_eth_link link, old;
1160 int link_check, count;
1163 hw->mac.get_link_status = 1;
1165 /* possible wait-to-complete in up to 9 seconds */
1166 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1167 /* Read the real link status */
1168 switch (hw->phy.media_type) {
1169 case e1000_media_type_copper:
1170 /* Do the work to read phy */
1171 e1000_check_for_link(hw);
1172 link_check = !hw->mac.get_link_status;
1175 case e1000_media_type_fiber:
1176 e1000_check_for_link(hw);
1177 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1181 case e1000_media_type_internal_serdes:
1182 e1000_check_for_link(hw);
1183 link_check = hw->mac.serdes_has_link;
1189 if (link_check || wait_to_complete == 0)
1191 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1193 memset(&link, 0, sizeof(link));
1194 rte_em_dev_atomic_read_link_status(dev, &link);
1197 /* Now we check if a transition has happened */
1198 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1199 uint16_t duplex, speed;
1200 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1201 link.link_duplex = (duplex == FULL_DUPLEX) ?
1202 ETH_LINK_FULL_DUPLEX :
1203 ETH_LINK_HALF_DUPLEX;
1204 link.link_speed = speed;
1205 link.link_status = ETH_LINK_UP;
1206 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1207 ETH_LINK_SPEED_FIXED);
1208 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1209 link.link_speed = 0;
1210 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1211 link.link_status = ETH_LINK_DOWN;
1212 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1214 rte_em_dev_atomic_write_link_status(dev, &link);
1217 if (old.link_status == link.link_status)
1225 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1226 * For ASF and Pass Through versions of f/w this means
1227 * that the driver is loaded. For AMT version type f/w
1228 * this means that the network i/f is open.
1231 em_hw_control_acquire(struct e1000_hw *hw)
1233 uint32_t ctrl_ext, swsm;
1235 /* Let firmware know the driver has taken over */
1236 if (hw->mac.type == e1000_82573) {
1237 swsm = E1000_READ_REG(hw, E1000_SWSM);
1238 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1241 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1242 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1243 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1248 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1249 * For ASF and Pass Through versions of f/w this means that the
1250 * driver is no longer loaded. For AMT versions of the
1251 * f/w this means that the network i/f is closed.
1254 em_hw_control_release(struct e1000_hw *hw)
1256 uint32_t ctrl_ext, swsm;
1258 /* Let firmware taken over control of h/w */
1259 if (hw->mac.type == e1000_82573) {
1260 swsm = E1000_READ_REG(hw, E1000_SWSM);
1261 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1263 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1264 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1265 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1270 * Bit of a misnomer, what this really means is
1271 * to enable OS management of the system... aka
1272 * to disable special hardware management features.
1275 em_init_manageability(struct e1000_hw *hw)
1277 if (e1000_enable_mng_pass_thru(hw)) {
1278 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1279 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1281 /* disable hardware interception of ARP */
1282 manc &= ~(E1000_MANC_ARP_EN);
1284 /* enable receiving management packets to the host */
1285 manc |= E1000_MANC_EN_MNG2HOST;
1286 manc2h |= 1 << 5; /* Mng Port 623 */
1287 manc2h |= 1 << 6; /* Mng Port 664 */
1288 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1289 E1000_WRITE_REG(hw, E1000_MANC, manc);
1294 * Give control back to hardware management
1295 * controller if there is one.
1298 em_release_manageability(struct e1000_hw *hw)
1302 if (e1000_enable_mng_pass_thru(hw)) {
1303 manc = E1000_READ_REG(hw, E1000_MANC);
1305 /* re-enable hardware interception of ARP */
1306 manc |= E1000_MANC_ARP_EN;
1307 manc &= ~E1000_MANC_EN_MNG2HOST;
1309 E1000_WRITE_REG(hw, E1000_MANC, manc);
1314 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1316 struct e1000_hw *hw =
1317 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320 rctl = E1000_READ_REG(hw, E1000_RCTL);
1321 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1322 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1326 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1328 struct e1000_hw *hw =
1329 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332 rctl = E1000_READ_REG(hw, E1000_RCTL);
1333 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1334 if (dev->data->all_multicast == 1)
1335 rctl |= E1000_RCTL_MPE;
1337 rctl &= (~E1000_RCTL_MPE);
1338 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1342 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1344 struct e1000_hw *hw =
1345 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348 rctl = E1000_READ_REG(hw, E1000_RCTL);
1349 rctl |= E1000_RCTL_MPE;
1350 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1354 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1356 struct e1000_hw *hw =
1357 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1360 if (dev->data->promiscuous == 1)
1361 return; /* must remain in all_multicast mode */
1362 rctl = E1000_READ_REG(hw, E1000_RCTL);
1363 rctl &= (~E1000_RCTL_MPE);
1364 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1368 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1370 struct e1000_hw *hw =
1371 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1372 struct e1000_vfta * shadow_vfta =
1373 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1378 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1379 E1000_VFTA_ENTRY_MASK);
1380 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1381 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1386 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1388 /* update local VFTA copy */
1389 shadow_vfta->vfta[vid_idx] = vfta;
1395 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1397 struct e1000_hw *hw =
1398 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1401 /* Filter Table Disable */
1402 reg = E1000_READ_REG(hw, E1000_RCTL);
1403 reg &= ~E1000_RCTL_CFIEN;
1404 reg &= ~E1000_RCTL_VFE;
1405 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1409 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1411 struct e1000_hw *hw =
1412 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413 struct e1000_vfta * shadow_vfta =
1414 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1418 /* Filter Table Enable, CFI not used for packet acceptance */
1419 reg = E1000_READ_REG(hw, E1000_RCTL);
1420 reg &= ~E1000_RCTL_CFIEN;
1421 reg |= E1000_RCTL_VFE;
1422 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1424 /* restore vfta from local copy */
1425 for (i = 0; i < IGB_VFTA_SIZE; i++)
1426 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1430 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1432 struct e1000_hw *hw =
1433 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1436 /* VLAN Mode Disable */
1437 reg = E1000_READ_REG(hw, E1000_CTRL);
1438 reg &= ~E1000_CTRL_VME;
1439 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1444 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1446 struct e1000_hw *hw =
1447 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1450 /* VLAN Mode Enable */
1451 reg = E1000_READ_REG(hw, E1000_CTRL);
1452 reg |= E1000_CTRL_VME;
1453 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1457 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1459 if(mask & ETH_VLAN_STRIP_MASK){
1460 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1461 em_vlan_hw_strip_enable(dev);
1463 em_vlan_hw_strip_disable(dev);
1466 if(mask & ETH_VLAN_FILTER_MASK){
1467 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1468 em_vlan_hw_filter_enable(dev);
1470 em_vlan_hw_filter_disable(dev);
1477 * It enables the interrupt mask and then enable the interrupt.
1480 * Pointer to struct rte_eth_dev.
1483 * - On success, zero.
1484 * - On failure, a negative value.
1487 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1490 struct e1000_hw *hw =
1491 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1493 /* clear interrupt */
1494 E1000_READ_REG(hw, E1000_ICR);
1495 regval = E1000_READ_REG(hw, E1000_IMS);
1496 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1501 * It clears the interrupt causes and enables the interrupt.
1502 * It will be called once only during nic initialized.
1505 * Pointer to struct rte_eth_dev.
1508 * - On success, zero.
1509 * - On failure, a negative value.
1512 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1514 struct e1000_hw *hw =
1515 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517 E1000_READ_REG(hw, E1000_ICR);
1518 em_rxq_intr_enable(hw);
1523 * It enable receive packet interrupt.
1525 * Pointer to struct e1000_hw
1530 em_rxq_intr_enable(struct e1000_hw *hw)
1532 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1533 E1000_WRITE_FLUSH(hw);
1537 * It disabled lsc interrupt.
1539 * Pointer to struct e1000_hw
1544 em_lsc_intr_disable(struct e1000_hw *hw)
1546 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1547 E1000_WRITE_FLUSH(hw);
1551 * It disabled receive packet interrupt.
1553 * Pointer to struct e1000_hw
1558 em_rxq_intr_disable(struct e1000_hw *hw)
1560 E1000_READ_REG(hw, E1000_ICR);
1561 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1562 E1000_WRITE_FLUSH(hw);
1566 * It reads ICR and gets interrupt causes, check it and set a bit flag
1567 * to update link status.
1570 * Pointer to struct rte_eth_dev.
1573 * - On success, zero.
1574 * - On failure, a negative value.
1577 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1580 struct e1000_hw *hw =
1581 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582 struct e1000_interrupt *intr =
1583 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1585 /* read-on-clear nic registers here */
1586 icr = E1000_READ_REG(hw, E1000_ICR);
1587 if (icr & E1000_ICR_LSC) {
1588 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1595 * It executes link_update after knowing an interrupt is prsent.
1598 * Pointer to struct rte_eth_dev.
1601 * - On success, zero.
1602 * - On failure, a negative value.
1605 eth_em_interrupt_action(struct rte_eth_dev *dev,
1606 struct rte_intr_handle *intr_handle)
1608 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1609 struct e1000_hw *hw =
1610 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611 struct e1000_interrupt *intr =
1612 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1613 uint32_t tctl, rctl;
1614 struct rte_eth_link link;
1617 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1620 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1621 rte_intr_enable(intr_handle);
1623 /* set get_link_status to check register later */
1624 hw->mac.get_link_status = 1;
1625 ret = eth_em_link_update(dev, 0);
1627 /* check if link has changed */
1631 memset(&link, 0, sizeof(link));
1632 rte_em_dev_atomic_read_link_status(dev, &link);
1633 if (link.link_status) {
1634 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1635 dev->data->port_id, link.link_speed,
1636 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1637 "full-duplex" : "half-duplex");
1639 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1641 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1642 pci_dev->addr.domain, pci_dev->addr.bus,
1643 pci_dev->addr.devid, pci_dev->addr.function);
1645 tctl = E1000_READ_REG(hw, E1000_TCTL);
1646 rctl = E1000_READ_REG(hw, E1000_RCTL);
1647 if (link.link_status) {
1649 tctl |= E1000_TCTL_EN;
1650 rctl |= E1000_RCTL_EN;
1653 tctl &= ~E1000_TCTL_EN;
1654 rctl &= ~E1000_RCTL_EN;
1656 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1657 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1658 E1000_WRITE_FLUSH(hw);
1664 * Interrupt handler which shall be registered at first.
1667 * Pointer to interrupt handle.
1669 * The address of parameter (struct rte_eth_dev *) regsitered before.
1675 eth_em_interrupt_handler(void *param)
1677 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1679 eth_em_interrupt_get_status(dev);
1680 eth_em_interrupt_action(dev, dev->intr_handle);
1681 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1685 eth_em_led_on(struct rte_eth_dev *dev)
1687 struct e1000_hw *hw;
1689 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1690 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1694 eth_em_led_off(struct rte_eth_dev *dev)
1696 struct e1000_hw *hw;
1698 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1703 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1705 struct e1000_hw *hw;
1710 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1711 fc_conf->pause_time = hw->fc.pause_time;
1712 fc_conf->high_water = hw->fc.high_water;
1713 fc_conf->low_water = hw->fc.low_water;
1714 fc_conf->send_xon = hw->fc.send_xon;
1715 fc_conf->autoneg = hw->mac.autoneg;
1718 * Return rx_pause and tx_pause status according to actual setting of
1719 * the TFCE and RFCE bits in the CTRL register.
1721 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1722 if (ctrl & E1000_CTRL_TFCE)
1727 if (ctrl & E1000_CTRL_RFCE)
1732 if (rx_pause && tx_pause)
1733 fc_conf->mode = RTE_FC_FULL;
1735 fc_conf->mode = RTE_FC_RX_PAUSE;
1737 fc_conf->mode = RTE_FC_TX_PAUSE;
1739 fc_conf->mode = RTE_FC_NONE;
1745 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1747 struct e1000_hw *hw;
1749 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1755 uint32_t rx_buf_size;
1756 uint32_t max_high_water;
1759 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1760 if (fc_conf->autoneg != hw->mac.autoneg)
1762 rx_buf_size = em_get_rx_buffer_size(hw);
1763 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1765 /* At least reserve one Ethernet frame for watermark */
1766 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1767 if ((fc_conf->high_water > max_high_water) ||
1768 (fc_conf->high_water < fc_conf->low_water)) {
1769 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1770 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1774 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1775 hw->fc.pause_time = fc_conf->pause_time;
1776 hw->fc.high_water = fc_conf->high_water;
1777 hw->fc.low_water = fc_conf->low_water;
1778 hw->fc.send_xon = fc_conf->send_xon;
1780 err = e1000_setup_link_generic(hw);
1781 if (err == E1000_SUCCESS) {
1783 /* check if we want to forward MAC frames - driver doesn't have native
1784 * capability to do that, so we'll write the registers ourselves */
1786 rctl = E1000_READ_REG(hw, E1000_RCTL);
1788 /* set or clear MFLCN.PMCF bit depending on configuration */
1789 if (fc_conf->mac_ctrl_frame_fwd != 0)
1790 rctl |= E1000_RCTL_PMCF;
1792 rctl &= ~E1000_RCTL_PMCF;
1794 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1795 E1000_WRITE_FLUSH(hw);
1800 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1805 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1806 uint32_t index, __rte_unused uint32_t pool)
1808 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1810 return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1814 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1816 uint8_t addr[ETHER_ADDR_LEN];
1817 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1819 memset(addr, 0, sizeof(addr));
1821 e1000_rar_set(hw, addr, index);
1825 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1827 struct rte_eth_dev_info dev_info;
1828 struct e1000_hw *hw;
1829 uint32_t frame_size;
1832 eth_em_infos_get(dev, &dev_info);
1833 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1835 /* check that mtu is within the allowed range */
1836 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1839 /* refuse mtu that requires the support of scattered packets when this
1840 * feature has not been enabled before. */
1841 if (!dev->data->scattered_rx &&
1842 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1845 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846 rctl = E1000_READ_REG(hw, E1000_RCTL);
1848 /* switch to jumbo mode if needed */
1849 if (frame_size > ETHER_MAX_LEN) {
1850 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1851 rctl |= E1000_RCTL_LPE;
1853 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1854 rctl &= ~E1000_RCTL_LPE;
1856 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1858 /* update max frame size */
1859 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1864 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1865 struct ether_addr *mc_addr_set,
1866 uint32_t nb_mc_addr)
1868 struct e1000_hw *hw;
1870 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1875 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1876 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1877 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");