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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
59 #define EM_EIAC 0x000DC
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
86 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
89 static int em_hw_init(struct e1000_hw *hw);
90 static int em_hardware_init(struct e1000_hw *hw);
91 static void em_hw_control_acquire(struct e1000_hw *hw);
92 static void em_hw_control_release(struct e1000_hw *hw);
93 static void em_init_manageability(struct e1000_hw *hw);
94 static void em_release_manageability(struct e1000_hw *hw);
96 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
98 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
99 uint16_t vlan_id, int on);
100 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
101 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
102 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
107 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
108 uint16_t vlan_id, int on);
110 static int eth_em_led_on(struct rte_eth_dev *dev);
111 static int eth_em_led_off(struct rte_eth_dev *dev);
113 static void em_intr_disable(struct e1000_hw *hw);
114 static int em_get_rx_buffer_size(struct e1000_hw *hw);
115 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
116 uint32_t index, uint32_t pool);
117 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
119 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
120 struct ether_addr *mc_addr_set,
121 uint32_t nb_mc_addr);
123 #define EM_FC_PAUSE_TIME 0x0680
124 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
125 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
127 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
130 * The set of PCI devices this driver supports
132 static const struct rte_pci_id pci_id_em_map[] = {
134 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
135 #include "rte_pci_dev_ids.h"
140 static const struct eth_dev_ops eth_em_ops = {
141 .dev_configure = eth_em_configure,
142 .dev_start = eth_em_start,
143 .dev_stop = eth_em_stop,
144 .dev_close = eth_em_close,
145 .promiscuous_enable = eth_em_promiscuous_enable,
146 .promiscuous_disable = eth_em_promiscuous_disable,
147 .allmulticast_enable = eth_em_allmulticast_enable,
148 .allmulticast_disable = eth_em_allmulticast_disable,
149 .link_update = eth_em_link_update,
150 .stats_get = eth_em_stats_get,
151 .stats_reset = eth_em_stats_reset,
152 .dev_infos_get = eth_em_infos_get,
153 .mtu_set = eth_em_mtu_set,
154 .vlan_filter_set = eth_em_vlan_filter_set,
155 .vlan_offload_set = eth_em_vlan_offload_set,
156 .rx_queue_setup = eth_em_rx_queue_setup,
157 .rx_queue_release = eth_em_rx_queue_release,
158 .rx_queue_count = eth_em_rx_queue_count,
159 .rx_descriptor_done = eth_em_rx_descriptor_done,
160 .tx_queue_setup = eth_em_tx_queue_setup,
161 .tx_queue_release = eth_em_tx_queue_release,
162 .dev_led_on = eth_em_led_on,
163 .dev_led_off = eth_em_led_off,
164 .flow_ctrl_get = eth_em_flow_ctrl_get,
165 .flow_ctrl_set = eth_em_flow_ctrl_set,
166 .mac_addr_add = eth_em_rar_set,
167 .mac_addr_remove = eth_em_rar_clear,
168 .set_mc_addr_list = eth_em_set_mc_addr_list,
172 * Atomically reads the link status information from global
173 * structure rte_eth_dev.
176 * - Pointer to the structure rte_eth_dev to read from.
177 * - Pointer to the buffer to be saved with the link status.
180 * - On success, zero.
181 * - On failure, negative value.
184 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
185 struct rte_eth_link *link)
187 struct rte_eth_link *dst = link;
188 struct rte_eth_link *src = &(dev->data->dev_link);
190 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
191 *(uint64_t *)src) == 0)
198 * Atomically writes the link status information into global
199 * structure rte_eth_dev.
202 * - Pointer to the structure rte_eth_dev to read from.
203 * - Pointer to the buffer to be saved with the link status.
206 * - On success, zero.
207 * - On failure, negative value.
210 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
211 struct rte_eth_link *link)
213 struct rte_eth_link *dst = &(dev->data->dev_link);
214 struct rte_eth_link *src = link;
216 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
217 *(uint64_t *)src) == 0)
224 eth_em_dev_init(struct rte_eth_dev *eth_dev)
226 struct rte_pci_device *pci_dev;
227 struct e1000_hw *hw =
228 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
229 struct e1000_vfta * shadow_vfta =
230 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
232 pci_dev = eth_dev->pci_dev;
233 eth_dev->dev_ops = ð_em_ops;
234 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
235 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
237 /* for secondary processes, we don't initialise any further as primary
238 * has already done this work. Only check we don't need a different
240 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
241 if (eth_dev->data->scattered_rx)
242 eth_dev->rx_pkt_burst =
243 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
247 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
248 hw->device_id = pci_dev->id.device_id;
250 /* For ICH8 support we'll need to map the flash memory BAR */
252 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
253 em_hw_init(hw) != 0) {
254 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
256 eth_dev->data->port_id, pci_dev->id.vendor_id,
257 pci_dev->id.device_id);
261 /* Allocate memory for storing MAC addresses */
262 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
263 hw->mac.rar_entry_count, 0);
264 if (eth_dev->data->mac_addrs == NULL) {
265 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
266 "store MAC addresses",
267 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
271 /* Copy the permanent MAC address */
272 ether_addr_copy((struct ether_addr *) hw->mac.addr,
273 eth_dev->data->mac_addrs);
275 /* initialize the vfta */
276 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
278 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
279 eth_dev->data->port_id, pci_dev->id.vendor_id,
280 pci_dev->id.device_id);
282 rte_intr_callback_register(&(pci_dev->intr_handle),
283 eth_em_interrupt_handler, (void *)eth_dev);
288 static struct eth_driver rte_em_pmd = {
290 .name = "rte_em_pmd",
291 .id_table = pci_id_em_map,
292 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
294 .eth_dev_init = eth_em_dev_init,
295 .dev_private_size = sizeof(struct e1000_adapter),
299 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
301 rte_eth_driver_register(&rte_em_pmd);
306 em_hw_init(struct e1000_hw *hw)
310 diag = hw->mac.ops.init_params(hw);
312 PMD_INIT_LOG(ERR, "MAC Initialization Error");
315 diag = hw->nvm.ops.init_params(hw);
317 PMD_INIT_LOG(ERR, "NVM Initialization Error");
320 diag = hw->phy.ops.init_params(hw);
322 PMD_INIT_LOG(ERR, "PHY Initialization Error");
325 (void) e1000_get_bus_info(hw);
328 hw->phy.autoneg_wait_to_complete = 0;
329 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
331 e1000_init_script_state_82541(hw, TRUE);
332 e1000_set_tbi_compatibility_82543(hw, TRUE);
335 if (hw->phy.media_type == e1000_media_type_copper) {
336 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
337 hw->phy.disable_polarity_correction = 0;
338 hw->phy.ms_type = e1000_ms_hw_default;
342 * Start from a known state, this is important in reading the nvm
347 /* Make sure we have a good EEPROM before we read from it */
348 if (e1000_validate_nvm_checksum(hw) < 0) {
350 * Some PCI-E parts fail the first check due to
351 * the link being in sleep state, call it again,
352 * if it fails a second time its a real issue.
354 diag = e1000_validate_nvm_checksum(hw);
356 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
361 /* Read the permanent MAC address out of the EEPROM */
362 diag = e1000_read_mac_addr(hw);
364 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
368 /* Now initialize the hardware */
369 diag = em_hardware_init(hw);
371 PMD_INIT_LOG(ERR, "Hardware initialization failed");
375 hw->mac.get_link_status = 1;
377 /* Indicate SOL/IDER usage */
378 diag = e1000_check_reset_block(hw);
380 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
386 em_hw_control_release(hw);
391 eth_em_configure(struct rte_eth_dev *dev)
393 struct e1000_interrupt *intr =
394 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
396 PMD_INIT_FUNC_TRACE();
397 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
398 PMD_INIT_FUNC_TRACE();
404 em_set_pba(struct e1000_hw *hw)
409 * Packet Buffer Allocation (PBA)
410 * Writing PBA sets the receive portion of the buffer
411 * the remainder is used for the transmit buffer.
412 * Devices before the 82547 had a Packet Buffer of 64K.
413 * After the 82547 the buffer was reduced to 40K.
415 switch (hw->mac.type) {
417 case e1000_82547_rev_2:
418 /* 82547: Total Packet Buffer is 40K */
419 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
423 case e1000_80003es2lan:
424 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
426 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
427 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
431 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
445 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
448 E1000_WRITE_REG(hw, E1000_PBA, pba);
452 eth_em_start(struct rte_eth_dev *dev)
454 struct e1000_hw *hw =
455 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
458 PMD_INIT_FUNC_TRACE();
462 e1000_power_up_phy(hw);
464 /* Set default PBA value */
467 /* Put the address into the Receive Address Array */
468 e1000_rar_set(hw, hw->mac.addr, 0);
471 * With the 82571 adapter, RAR[0] may be overwritten
472 * when the other port is reset, we make a duplicate
473 * in RAR[14] for that eventuality, this assures
474 * the interface continues to function.
476 if (hw->mac.type == e1000_82571) {
477 e1000_set_laa_state_82571(hw, TRUE);
478 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
481 /* Initialize the hardware */
482 if (em_hardware_init(hw)) {
483 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
487 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
489 /* Configure for OS presence */
490 em_init_manageability(hw);
494 ret = eth_em_rx_init(dev);
496 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
497 em_dev_clear_queues(dev);
501 e1000_clear_hw_cntrs_base_generic(hw);
503 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
504 ETH_VLAN_EXTEND_MASK;
505 eth_em_vlan_offload_set(dev, mask);
507 /* Set Interrupt Throttling Rate to maximum allowed value. */
508 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
510 /* Setup link speed and duplex */
511 switch (dev->data->dev_conf.link_speed) {
512 case ETH_LINK_SPEED_AUTONEG:
513 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
514 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
515 else if (dev->data->dev_conf.link_duplex ==
516 ETH_LINK_HALF_DUPLEX)
517 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
518 else if (dev->data->dev_conf.link_duplex ==
519 ETH_LINK_FULL_DUPLEX)
520 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
522 goto error_invalid_config;
524 case ETH_LINK_SPEED_10:
525 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
526 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
527 else if (dev->data->dev_conf.link_duplex ==
528 ETH_LINK_HALF_DUPLEX)
529 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
530 else if (dev->data->dev_conf.link_duplex ==
531 ETH_LINK_FULL_DUPLEX)
532 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
534 goto error_invalid_config;
536 case ETH_LINK_SPEED_100:
537 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
538 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
539 else if (dev->data->dev_conf.link_duplex ==
540 ETH_LINK_HALF_DUPLEX)
541 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
542 else if (dev->data->dev_conf.link_duplex ==
543 ETH_LINK_FULL_DUPLEX)
544 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
546 goto error_invalid_config;
548 case ETH_LINK_SPEED_1000:
549 if ((dev->data->dev_conf.link_duplex ==
550 ETH_LINK_AUTONEG_DUPLEX) ||
551 (dev->data->dev_conf.link_duplex ==
552 ETH_LINK_FULL_DUPLEX))
553 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
555 goto error_invalid_config;
557 case ETH_LINK_SPEED_10000:
559 goto error_invalid_config;
561 e1000_setup_link(hw);
563 /* check if lsc interrupt feature is enabled */
564 if (dev->data->dev_conf.intr_conf.lsc != 0) {
565 ret = eth_em_interrupt_setup(dev);
567 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
568 em_dev_clear_queues(dev);
573 PMD_INIT_LOG(DEBUG, "<<");
577 error_invalid_config:
578 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
579 dev->data->dev_conf.link_speed,
580 dev->data->dev_conf.link_duplex, dev->data->port_id);
581 em_dev_clear_queues(dev);
585 /*********************************************************************
587 * This routine disables all traffic on the adapter by issuing a
588 * global reset on the MAC.
590 **********************************************************************/
592 eth_em_stop(struct rte_eth_dev *dev)
594 struct rte_eth_link link;
595 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
599 if (hw->mac.type >= e1000_82544)
600 E1000_WRITE_REG(hw, E1000_WUC, 0);
602 /* Power down the phy. Needed to make the link go down */
603 e1000_power_down_phy(hw);
605 em_dev_clear_queues(dev);
607 /* clear the recorded link status */
608 memset(&link, 0, sizeof(link));
609 rte_em_dev_atomic_write_link_status(dev, &link);
613 eth_em_close(struct rte_eth_dev *dev)
615 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
618 e1000_phy_hw_reset(hw);
619 em_release_manageability(hw);
620 em_hw_control_release(hw);
624 em_get_rx_buffer_size(struct e1000_hw *hw)
626 uint32_t rx_buf_size;
628 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
632 /*********************************************************************
634 * Initialize the hardware
636 **********************************************************************/
638 em_hardware_init(struct e1000_hw *hw)
640 uint32_t rx_buf_size;
643 /* Issue a global reset */
646 /* Let the firmware know the OS is in control */
647 em_hw_control_acquire(hw);
650 * These parameters control the automatic generation (Tx) and
651 * response (Rx) to Ethernet PAUSE frames.
652 * - High water mark should allow for at least two standard size (1518)
653 * frames to be received after sending an XOFF.
654 * - Low water mark works best when it is very near the high water mark.
655 * This allows the receiver to restart by sending XON when it has
656 * drained a bit. Here we use an arbitrary value of 1500 which will
657 * restart after one full frame is pulled from the buffer. There
658 * could be several smaller frames in the buffer and if so they will
659 * not trigger the XON until their total number reduces the buffer
661 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
663 rx_buf_size = em_get_rx_buffer_size(hw);
665 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
666 hw->fc.low_water = hw->fc.high_water - 1500;
668 if (hw->mac.type == e1000_80003es2lan)
669 hw->fc.pause_time = UINT16_MAX;
671 hw->fc.pause_time = EM_FC_PAUSE_TIME;
675 /* Set Flow control, use the tunable location if sane */
676 if (em_fc_setting <= e1000_fc_full)
677 hw->fc.requested_mode = em_fc_setting;
679 hw->fc.requested_mode = e1000_fc_none;
681 /* Workaround: no TX flow ctrl for PCH */
682 if (hw->mac.type == e1000_pchlan)
683 hw->fc.requested_mode = e1000_fc_rx_pause;
685 /* Override - settings for PCH2LAN, ya its magic :) */
686 if (hw->mac.type == e1000_pch2lan) {
687 hw->fc.high_water = 0x5C20;
688 hw->fc.low_water = 0x5048;
689 hw->fc.pause_time = 0x0650;
690 hw->fc.refresh_time = 0x0400;
693 diag = e1000_init_hw(hw);
696 e1000_check_for_link(hw);
700 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
702 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
704 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
705 struct e1000_hw_stats *stats =
706 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
709 if(hw->phy.media_type == e1000_media_type_copper ||
710 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
711 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
712 stats->sec += E1000_READ_REG(hw, E1000_SEC);
715 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
716 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
717 stats->scc += E1000_READ_REG(hw, E1000_SCC);
718 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
720 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
721 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
722 stats->colc += E1000_READ_REG(hw, E1000_COLC);
723 stats->dc += E1000_READ_REG(hw, E1000_DC);
724 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
725 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
726 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
729 * For watchdog management we need to know if we have been
730 * paused during the last interval, so capture that here.
732 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
733 stats->xoffrxc += pause_frames;
734 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
735 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
736 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
737 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
738 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
739 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
740 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
741 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
742 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
743 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
744 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
745 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
748 * For the 64-bit byte counters the low dword must be read first.
749 * Both registers clear on the read of the high dword.
752 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
753 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
754 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
755 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
757 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
758 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
759 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
760 stats->roc += E1000_READ_REG(hw, E1000_ROC);
761 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
763 stats->tor += E1000_READ_REG(hw, E1000_TORH);
764 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
766 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
767 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
768 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
769 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
770 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
771 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
772 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
773 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
774 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
775 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
777 /* Interrupt Counts */
779 if (hw->mac.type >= e1000_82571) {
780 stats->iac += E1000_READ_REG(hw, E1000_IAC);
781 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
782 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
783 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
784 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
785 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
786 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
787 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
788 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
791 if (hw->mac.type >= e1000_82543) {
792 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
793 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
794 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
795 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
796 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
797 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
800 if (rte_stats == NULL)
804 rte_stats->ibadcrc = stats->crcerrs;
805 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
806 rte_stats->imissed = stats->mpc;
807 rte_stats->ierrors = rte_stats->ibadcrc +
810 stats->rxerrc + stats->algnerrc + stats->cexterr;
813 rte_stats->oerrors = stats->ecol + stats->latecol;
815 rte_stats->ipackets = stats->gprc;
816 rte_stats->opackets = stats->gptc;
817 rte_stats->ibytes = stats->gorc;
818 rte_stats->obytes = stats->gotc;
820 /* XON/XOFF pause frames stats registers */
821 rte_stats->tx_pause_xon = stats->xontxc;
822 rte_stats->rx_pause_xon = stats->xonrxc;
823 rte_stats->tx_pause_xoff = stats->xofftxc;
824 rte_stats->rx_pause_xoff = stats->xoffrxc;
828 eth_em_stats_reset(struct rte_eth_dev *dev)
830 struct e1000_hw_stats *hw_stats =
831 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
833 /* HW registers are cleared on read */
834 eth_em_stats_get(dev, NULL);
836 /* Reset software totals */
837 memset(hw_stats, 0, sizeof(*hw_stats));
841 em_get_max_pktlen(const struct e1000_hw *hw)
843 switch (hw->mac.type) {
850 case e1000_80003es2lan: /* 9K Jumbo Frame size */
854 /* Adapters that do not support jumbo frames */
857 return (ETHER_MAX_LEN);
859 return (MAX_JUMBO_FRAME_SIZE);
864 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
866 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
868 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
869 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
870 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
873 * Starting with 631xESB hw supports 2 TX/RX queues per port.
874 * Unfortunatelly, all these nics have just one TX context.
875 * So we have few choises for TX:
876 * - Use just one TX queue.
877 * - Allow cksum offload only for one TX queue.
878 * - Don't allow TX cksum offload at all.
879 * For now, option #1 was chosen.
880 * To use second RX queue we have to use extended RX descriptor
881 * (Multiple Receive Queues are mutually exclusive with UDP
882 * fragmentation and are not supported when a legacy receive
883 * descriptor format is used).
884 * Which means separate RX routinies - as legacy nics (82540, 82545)
885 * don't support extended RXD.
886 * To avoid it we support just one RX queue for now (no RSS).
889 dev_info->max_rx_queues = 1;
890 dev_info->max_tx_queues = 1;
893 /* return 0 means link status changed, -1 means not changed */
895 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
897 struct e1000_hw *hw =
898 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
899 struct rte_eth_link link, old;
900 int link_check, count;
903 hw->mac.get_link_status = 1;
905 /* possible wait-to-complete in up to 9 seconds */
906 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
907 /* Read the real link status */
908 switch (hw->phy.media_type) {
909 case e1000_media_type_copper:
910 /* Do the work to read phy */
911 e1000_check_for_link(hw);
912 link_check = !hw->mac.get_link_status;
915 case e1000_media_type_fiber:
916 e1000_check_for_link(hw);
917 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
921 case e1000_media_type_internal_serdes:
922 e1000_check_for_link(hw);
923 link_check = hw->mac.serdes_has_link;
929 if (link_check || wait_to_complete == 0)
931 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
933 memset(&link, 0, sizeof(link));
934 rte_em_dev_atomic_read_link_status(dev, &link);
937 /* Now we check if a transition has happened */
938 if (link_check && (link.link_status == 0)) {
939 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
941 link.link_status = 1;
942 } else if (!link_check && (link.link_status == 1)) {
944 link.link_duplex = 0;
945 link.link_status = 0;
947 rte_em_dev_atomic_write_link_status(dev, &link);
950 if (old.link_status == link.link_status)
958 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
959 * For ASF and Pass Through versions of f/w this means
960 * that the driver is loaded. For AMT version type f/w
961 * this means that the network i/f is open.
964 em_hw_control_acquire(struct e1000_hw *hw)
966 uint32_t ctrl_ext, swsm;
968 /* Let firmware know the driver has taken over */
969 if (hw->mac.type == e1000_82573) {
970 swsm = E1000_READ_REG(hw, E1000_SWSM);
971 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
974 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
975 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
976 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
981 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
982 * For ASF and Pass Through versions of f/w this means that the
983 * driver is no longer loaded. For AMT versions of the
984 * f/w this means that the network i/f is closed.
987 em_hw_control_release(struct e1000_hw *hw)
989 uint32_t ctrl_ext, swsm;
991 /* Let firmware taken over control of h/w */
992 if (hw->mac.type == e1000_82573) {
993 swsm = E1000_READ_REG(hw, E1000_SWSM);
994 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
996 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
997 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
998 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1003 * Bit of a misnomer, what this really means is
1004 * to enable OS management of the system... aka
1005 * to disable special hardware management features.
1008 em_init_manageability(struct e1000_hw *hw)
1010 if (e1000_enable_mng_pass_thru(hw)) {
1011 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1012 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1014 /* disable hardware interception of ARP */
1015 manc &= ~(E1000_MANC_ARP_EN);
1017 /* enable receiving management packets to the host */
1018 manc |= E1000_MANC_EN_MNG2HOST;
1019 manc2h |= 1 << 5; /* Mng Port 623 */
1020 manc2h |= 1 << 6; /* Mng Port 664 */
1021 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1022 E1000_WRITE_REG(hw, E1000_MANC, manc);
1027 * Give control back to hardware management
1028 * controller if there is one.
1031 em_release_manageability(struct e1000_hw *hw)
1035 if (e1000_enable_mng_pass_thru(hw)) {
1036 manc = E1000_READ_REG(hw, E1000_MANC);
1038 /* re-enable hardware interception of ARP */
1039 manc |= E1000_MANC_ARP_EN;
1040 manc &= ~E1000_MANC_EN_MNG2HOST;
1042 E1000_WRITE_REG(hw, E1000_MANC, manc);
1047 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1049 struct e1000_hw *hw =
1050 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1053 rctl = E1000_READ_REG(hw, E1000_RCTL);
1054 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1055 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1059 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1061 struct e1000_hw *hw =
1062 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1065 rctl = E1000_READ_REG(hw, E1000_RCTL);
1066 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1067 if (dev->data->all_multicast == 1)
1068 rctl |= E1000_RCTL_MPE;
1070 rctl &= (~E1000_RCTL_MPE);
1071 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1075 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1077 struct e1000_hw *hw =
1078 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1081 rctl = E1000_READ_REG(hw, E1000_RCTL);
1082 rctl |= E1000_RCTL_MPE;
1083 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1087 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1089 struct e1000_hw *hw =
1090 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093 if (dev->data->promiscuous == 1)
1094 return; /* must remain in all_multicast mode */
1095 rctl = E1000_READ_REG(hw, E1000_RCTL);
1096 rctl &= (~E1000_RCTL_MPE);
1097 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1101 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1103 struct e1000_hw *hw =
1104 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105 struct e1000_vfta * shadow_vfta =
1106 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1111 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1112 E1000_VFTA_ENTRY_MASK);
1113 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1114 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1119 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1121 /* update local VFTA copy */
1122 shadow_vfta->vfta[vid_idx] = vfta;
1128 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1130 struct e1000_hw *hw =
1131 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1134 /* Filter Table Disable */
1135 reg = E1000_READ_REG(hw, E1000_RCTL);
1136 reg &= ~E1000_RCTL_CFIEN;
1137 reg &= ~E1000_RCTL_VFE;
1138 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1142 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1144 struct e1000_hw *hw =
1145 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1146 struct e1000_vfta * shadow_vfta =
1147 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1151 /* Filter Table Enable, CFI not used for packet acceptance */
1152 reg = E1000_READ_REG(hw, E1000_RCTL);
1153 reg &= ~E1000_RCTL_CFIEN;
1154 reg |= E1000_RCTL_VFE;
1155 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1157 /* restore vfta from local copy */
1158 for (i = 0; i < IGB_VFTA_SIZE; i++)
1159 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1163 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1165 struct e1000_hw *hw =
1166 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1169 /* VLAN Mode Disable */
1170 reg = E1000_READ_REG(hw, E1000_CTRL);
1171 reg &= ~E1000_CTRL_VME;
1172 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1177 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1179 struct e1000_hw *hw =
1180 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183 /* VLAN Mode Enable */
1184 reg = E1000_READ_REG(hw, E1000_CTRL);
1185 reg |= E1000_CTRL_VME;
1186 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1190 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1192 if(mask & ETH_VLAN_STRIP_MASK){
1193 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1194 em_vlan_hw_strip_enable(dev);
1196 em_vlan_hw_strip_disable(dev);
1199 if(mask & ETH_VLAN_FILTER_MASK){
1200 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1201 em_vlan_hw_filter_enable(dev);
1203 em_vlan_hw_filter_disable(dev);
1208 em_intr_disable(struct e1000_hw *hw)
1210 E1000_WRITE_REG(hw, E1000_IMC, ~0);
1214 * It enables the interrupt mask and then enable the interrupt.
1217 * Pointer to struct rte_eth_dev.
1220 * - On success, zero.
1221 * - On failure, a negative value.
1224 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1226 struct e1000_hw *hw =
1227 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1229 E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1230 rte_intr_enable(&(dev->pci_dev->intr_handle));
1235 * It reads ICR and gets interrupt causes, check it and set a bit flag
1236 * to update link status.
1239 * Pointer to struct rte_eth_dev.
1242 * - On success, zero.
1243 * - On failure, a negative value.
1246 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1249 struct e1000_hw *hw =
1250 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1251 struct e1000_interrupt *intr =
1252 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1254 /* read-on-clear nic registers here */
1255 icr = E1000_READ_REG(hw, E1000_ICR);
1256 if (icr & E1000_ICR_LSC) {
1257 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1264 * It executes link_update after knowing an interrupt is prsent.
1267 * Pointer to struct rte_eth_dev.
1270 * - On success, zero.
1271 * - On failure, a negative value.
1274 eth_em_interrupt_action(struct rte_eth_dev *dev)
1276 struct e1000_hw *hw =
1277 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1278 struct e1000_interrupt *intr =
1279 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1280 uint32_t tctl, rctl;
1281 struct rte_eth_link link;
1284 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1287 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1288 rte_intr_enable(&(dev->pci_dev->intr_handle));
1290 /* set get_link_status to check register later */
1291 hw->mac.get_link_status = 1;
1292 ret = eth_em_link_update(dev, 0);
1294 /* check if link has changed */
1298 memset(&link, 0, sizeof(link));
1299 rte_em_dev_atomic_read_link_status(dev, &link);
1300 if (link.link_status) {
1301 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1302 dev->data->port_id, (unsigned)link.link_speed,
1303 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1304 "full-duplex" : "half-duplex");
1306 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1308 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1309 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1310 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1311 tctl = E1000_READ_REG(hw, E1000_TCTL);
1312 rctl = E1000_READ_REG(hw, E1000_RCTL);
1313 if (link.link_status) {
1315 tctl |= E1000_TCTL_EN;
1316 rctl |= E1000_RCTL_EN;
1319 tctl &= ~E1000_TCTL_EN;
1320 rctl &= ~E1000_RCTL_EN;
1322 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1323 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1324 E1000_WRITE_FLUSH(hw);
1330 * Interrupt handler which shall be registered at first.
1333 * Pointer to interrupt handle.
1335 * The address of parameter (struct rte_eth_dev *) regsitered before.
1341 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1344 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1346 eth_em_interrupt_get_status(dev);
1347 eth_em_interrupt_action(dev);
1348 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1352 eth_em_led_on(struct rte_eth_dev *dev)
1354 struct e1000_hw *hw;
1356 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1361 eth_em_led_off(struct rte_eth_dev *dev)
1363 struct e1000_hw *hw;
1365 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1370 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1372 struct e1000_hw *hw;
1377 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378 fc_conf->pause_time = hw->fc.pause_time;
1379 fc_conf->high_water = hw->fc.high_water;
1380 fc_conf->low_water = hw->fc.low_water;
1381 fc_conf->send_xon = hw->fc.send_xon;
1382 fc_conf->autoneg = hw->mac.autoneg;
1385 * Return rx_pause and tx_pause status according to actual setting of
1386 * the TFCE and RFCE bits in the CTRL register.
1388 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1389 if (ctrl & E1000_CTRL_TFCE)
1394 if (ctrl & E1000_CTRL_RFCE)
1399 if (rx_pause && tx_pause)
1400 fc_conf->mode = RTE_FC_FULL;
1402 fc_conf->mode = RTE_FC_RX_PAUSE;
1404 fc_conf->mode = RTE_FC_TX_PAUSE;
1406 fc_conf->mode = RTE_FC_NONE;
1412 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1414 struct e1000_hw *hw;
1416 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1422 uint32_t rx_buf_size;
1423 uint32_t max_high_water;
1426 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1427 if (fc_conf->autoneg != hw->mac.autoneg)
1429 rx_buf_size = em_get_rx_buffer_size(hw);
1430 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1432 /* At least reserve one Ethernet frame for watermark */
1433 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1434 if ((fc_conf->high_water > max_high_water) ||
1435 (fc_conf->high_water < fc_conf->low_water)) {
1436 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1437 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1441 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1442 hw->fc.pause_time = fc_conf->pause_time;
1443 hw->fc.high_water = fc_conf->high_water;
1444 hw->fc.low_water = fc_conf->low_water;
1445 hw->fc.send_xon = fc_conf->send_xon;
1447 err = e1000_setup_link_generic(hw);
1448 if (err == E1000_SUCCESS) {
1450 /* check if we want to forward MAC frames - driver doesn't have native
1451 * capability to do that, so we'll write the registers ourselves */
1453 rctl = E1000_READ_REG(hw, E1000_RCTL);
1455 /* set or clear MFLCN.PMCF bit depending on configuration */
1456 if (fc_conf->mac_ctrl_frame_fwd != 0)
1457 rctl |= E1000_RCTL_PMCF;
1459 rctl &= ~E1000_RCTL_PMCF;
1461 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1462 E1000_WRITE_FLUSH(hw);
1467 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1472 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1473 uint32_t index, __rte_unused uint32_t pool)
1475 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1481 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1483 uint8_t addr[ETHER_ADDR_LEN];
1484 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486 memset(addr, 0, sizeof(addr));
1488 e1000_rar_set(hw, addr, index);
1492 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1494 struct rte_eth_dev_info dev_info;
1495 struct e1000_hw *hw;
1496 uint32_t frame_size;
1499 eth_em_infos_get(dev, &dev_info);
1500 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1502 /* check that mtu is within the allowed range */
1503 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1506 /* refuse mtu that requires the support of scattered packets when this
1507 * feature has not been enabled before. */
1508 if (!dev->data->scattered_rx &&
1509 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1512 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1513 rctl = E1000_READ_REG(hw, E1000_RCTL);
1515 /* switch to jumbo mode if needed */
1516 if (frame_size > ETHER_MAX_LEN) {
1517 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1518 rctl |= E1000_RCTL_LPE;
1520 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1521 rctl &= ~E1000_RCTL_LPE;
1523 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1525 /* update max frame size */
1526 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1531 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1532 struct ether_addr *mc_addr_set,
1533 uint32_t nb_mc_addr)
1535 struct e1000_hw *hw;
1537 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1538 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1542 struct rte_driver em_pmd_drv = {
1544 .init = rte_em_pmd_init,
1547 PMD_REGISTER_DRIVER(em_pmd_drv);