4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
59 #define EM_EIAC 0x000DC
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
90 static int em_hw_init(struct e1000_hw *hw);
91 static int em_hardware_init(struct e1000_hw *hw);
92 static void em_hw_control_acquire(struct e1000_hw *hw);
93 static void em_hw_control_release(struct e1000_hw *hw);
94 static void em_init_manageability(struct e1000_hw *hw);
95 static void em_release_manageability(struct e1000_hw *hw);
97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
100 uint16_t vlan_id, int on);
101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
109 uint16_t vlan_id, int on);
112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static void em_lsc_intr_disable(struct e1000_hw *hw);
115 static void em_rxq_intr_enable(struct e1000_hw *hw);
116 static void em_rxq_intr_disable(struct e1000_hw *hw);
118 static int eth_em_led_on(struct rte_eth_dev *dev);
119 static int eth_em_led_off(struct rte_eth_dev *dev);
121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
123 uint32_t index, uint32_t pool);
124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
127 struct ether_addr *mc_addr_set,
128 uint32_t nb_mc_addr);
130 #define EM_FC_PAUSE_TIME 0x0680
131 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
137 * The set of PCI devices this driver supports
139 static const struct rte_pci_id pci_id_em_map[] = {
140 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
160 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
161 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
162 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
163 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
164 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
165 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
166 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
167 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
168 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
169 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
170 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
171 { .vendor_id = 0, /* sentinel */ },
174 static const struct eth_dev_ops eth_em_ops = {
175 .dev_configure = eth_em_configure,
176 .dev_start = eth_em_start,
177 .dev_stop = eth_em_stop,
178 .dev_close = eth_em_close,
179 .promiscuous_enable = eth_em_promiscuous_enable,
180 .promiscuous_disable = eth_em_promiscuous_disable,
181 .allmulticast_enable = eth_em_allmulticast_enable,
182 .allmulticast_disable = eth_em_allmulticast_disable,
183 .link_update = eth_em_link_update,
184 .stats_get = eth_em_stats_get,
185 .stats_reset = eth_em_stats_reset,
186 .dev_infos_get = eth_em_infos_get,
187 .mtu_set = eth_em_mtu_set,
188 .vlan_filter_set = eth_em_vlan_filter_set,
189 .vlan_offload_set = eth_em_vlan_offload_set,
190 .rx_queue_setup = eth_em_rx_queue_setup,
191 .rx_queue_release = eth_em_rx_queue_release,
192 .rx_queue_count = eth_em_rx_queue_count,
193 .rx_descriptor_done = eth_em_rx_descriptor_done,
194 .tx_queue_setup = eth_em_tx_queue_setup,
195 .tx_queue_release = eth_em_tx_queue_release,
196 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
197 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
198 .dev_led_on = eth_em_led_on,
199 .dev_led_off = eth_em_led_off,
200 .flow_ctrl_get = eth_em_flow_ctrl_get,
201 .flow_ctrl_set = eth_em_flow_ctrl_set,
202 .mac_addr_add = eth_em_rar_set,
203 .mac_addr_remove = eth_em_rar_clear,
204 .set_mc_addr_list = eth_em_set_mc_addr_list,
205 .rxq_info_get = em_rxq_info_get,
206 .txq_info_get = em_txq_info_get,
210 * Atomically reads the link status information from global
211 * structure rte_eth_dev.
214 * - Pointer to the structure rte_eth_dev to read from.
215 * - Pointer to the buffer to be saved with the link status.
218 * - On success, zero.
219 * - On failure, negative value.
222 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
223 struct rte_eth_link *link)
225 struct rte_eth_link *dst = link;
226 struct rte_eth_link *src = &(dev->data->dev_link);
228 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
229 *(uint64_t *)src) == 0)
236 * Atomically writes the link status information into global
237 * structure rte_eth_dev.
240 * - Pointer to the structure rte_eth_dev to read from.
241 * - Pointer to the buffer to be saved with the link status.
244 * - On success, zero.
245 * - On failure, negative value.
248 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
249 struct rte_eth_link *link)
251 struct rte_eth_link *dst = &(dev->data->dev_link);
252 struct rte_eth_link *src = link;
254 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
255 *(uint64_t *)src) == 0)
262 * eth_em_dev_is_ich8 - Check for ICH8 device
263 * @hw: pointer to the HW structure
265 * return TRUE for ICH8, otherwise FALSE
268 eth_em_dev_is_ich8(struct e1000_hw *hw)
270 DEBUGFUNC("eth_em_dev_is_ich8");
272 switch (hw->device_id) {
273 case E1000_DEV_ID_PCH_LPT_I217_LM:
274 case E1000_DEV_ID_PCH_LPT_I217_V:
275 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
276 case E1000_DEV_ID_PCH_LPTLP_I218_V:
277 case E1000_DEV_ID_PCH_I218_V2:
278 case E1000_DEV_ID_PCH_I218_LM2:
279 case E1000_DEV_ID_PCH_I218_V3:
280 case E1000_DEV_ID_PCH_I218_LM3:
288 eth_em_dev_init(struct rte_eth_dev *eth_dev)
290 struct rte_pci_device *pci_dev;
291 struct e1000_adapter *adapter =
292 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
293 struct e1000_hw *hw =
294 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
295 struct e1000_vfta * shadow_vfta =
296 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
298 pci_dev = eth_dev->pci_dev;
300 eth_dev->dev_ops = ð_em_ops;
301 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
302 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
304 /* for secondary processes, we don't initialise any further as primary
305 * has already done this work. Only check we don't need a different
307 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
308 if (eth_dev->data->scattered_rx)
309 eth_dev->rx_pkt_burst =
310 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
314 rte_eth_copy_pci_info(eth_dev, pci_dev);
316 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
317 hw->device_id = pci_dev->id.device_id;
318 adapter->stopped = 0;
320 /* For ICH8 support we'll need to map the flash memory BAR */
321 if (eth_em_dev_is_ich8(hw))
322 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
324 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
325 em_hw_init(hw) != 0) {
326 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
328 eth_dev->data->port_id, pci_dev->id.vendor_id,
329 pci_dev->id.device_id);
333 /* Allocate memory for storing MAC addresses */
334 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
335 hw->mac.rar_entry_count, 0);
336 if (eth_dev->data->mac_addrs == NULL) {
337 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
338 "store MAC addresses",
339 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
343 /* Copy the permanent MAC address */
344 ether_addr_copy((struct ether_addr *) hw->mac.addr,
345 eth_dev->data->mac_addrs);
347 /* initialize the vfta */
348 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
350 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
351 eth_dev->data->port_id, pci_dev->id.vendor_id,
352 pci_dev->id.device_id);
354 rte_intr_callback_register(&(pci_dev->intr_handle),
355 eth_em_interrupt_handler, (void *)eth_dev);
361 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
363 struct rte_pci_device *pci_dev;
364 struct e1000_adapter *adapter =
365 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
367 PMD_INIT_FUNC_TRACE();
369 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
372 pci_dev = eth_dev->pci_dev;
374 if (adapter->stopped == 0)
375 eth_em_close(eth_dev);
377 eth_dev->dev_ops = NULL;
378 eth_dev->rx_pkt_burst = NULL;
379 eth_dev->tx_pkt_burst = NULL;
381 rte_free(eth_dev->data->mac_addrs);
382 eth_dev->data->mac_addrs = NULL;
384 /* disable uio intr before callback unregister */
385 rte_intr_disable(&(pci_dev->intr_handle));
386 rte_intr_callback_unregister(&(pci_dev->intr_handle),
387 eth_em_interrupt_handler, (void *)eth_dev);
392 static struct eth_driver rte_em_pmd = {
394 .name = "rte_em_pmd",
395 .id_table = pci_id_em_map,
396 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
397 RTE_PCI_DRV_DETACHABLE,
399 .eth_dev_init = eth_em_dev_init,
400 .eth_dev_uninit = eth_em_dev_uninit,
401 .dev_private_size = sizeof(struct e1000_adapter),
405 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
407 rte_eth_driver_register(&rte_em_pmd);
412 em_hw_init(struct e1000_hw *hw)
416 diag = hw->mac.ops.init_params(hw);
418 PMD_INIT_LOG(ERR, "MAC Initialization Error");
421 diag = hw->nvm.ops.init_params(hw);
423 PMD_INIT_LOG(ERR, "NVM Initialization Error");
426 diag = hw->phy.ops.init_params(hw);
428 PMD_INIT_LOG(ERR, "PHY Initialization Error");
431 (void) e1000_get_bus_info(hw);
434 hw->phy.autoneg_wait_to_complete = 0;
435 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
437 e1000_init_script_state_82541(hw, TRUE);
438 e1000_set_tbi_compatibility_82543(hw, TRUE);
441 if (hw->phy.media_type == e1000_media_type_copper) {
442 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
443 hw->phy.disable_polarity_correction = 0;
444 hw->phy.ms_type = e1000_ms_hw_default;
448 * Start from a known state, this is important in reading the nvm
453 /* Make sure we have a good EEPROM before we read from it */
454 if (e1000_validate_nvm_checksum(hw) < 0) {
456 * Some PCI-E parts fail the first check due to
457 * the link being in sleep state, call it again,
458 * if it fails a second time its a real issue.
460 diag = e1000_validate_nvm_checksum(hw);
462 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
467 /* Read the permanent MAC address out of the EEPROM */
468 diag = e1000_read_mac_addr(hw);
470 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
474 /* Now initialize the hardware */
475 diag = em_hardware_init(hw);
477 PMD_INIT_LOG(ERR, "Hardware initialization failed");
481 hw->mac.get_link_status = 1;
483 /* Indicate SOL/IDER usage */
484 diag = e1000_check_reset_block(hw);
486 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
492 em_hw_control_release(hw);
497 eth_em_configure(struct rte_eth_dev *dev)
499 struct e1000_interrupt *intr =
500 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
502 PMD_INIT_FUNC_TRACE();
503 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
504 PMD_INIT_FUNC_TRACE();
510 em_set_pba(struct e1000_hw *hw)
515 * Packet Buffer Allocation (PBA)
516 * Writing PBA sets the receive portion of the buffer
517 * the remainder is used for the transmit buffer.
518 * Devices before the 82547 had a Packet Buffer of 64K.
519 * After the 82547 the buffer was reduced to 40K.
521 switch (hw->mac.type) {
523 case e1000_82547_rev_2:
524 /* 82547: Total Packet Buffer is 40K */
525 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
529 case e1000_80003es2lan:
530 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
532 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
533 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
537 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
552 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
555 E1000_WRITE_REG(hw, E1000_PBA, pba);
559 eth_em_start(struct rte_eth_dev *dev)
561 struct e1000_adapter *adapter =
562 E1000_DEV_PRIVATE(dev->data->dev_private);
563 struct e1000_hw *hw =
564 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
565 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
567 uint32_t intr_vector = 0;
572 PMD_INIT_FUNC_TRACE();
576 e1000_power_up_phy(hw);
578 /* Set default PBA value */
581 /* Put the address into the Receive Address Array */
582 e1000_rar_set(hw, hw->mac.addr, 0);
585 * With the 82571 adapter, RAR[0] may be overwritten
586 * when the other port is reset, we make a duplicate
587 * in RAR[14] for that eventuality, this assures
588 * the interface continues to function.
590 if (hw->mac.type == e1000_82571) {
591 e1000_set_laa_state_82571(hw, TRUE);
592 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
595 /* Initialize the hardware */
596 if (em_hardware_init(hw)) {
597 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
601 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
603 /* Configure for OS presence */
604 em_init_manageability(hw);
606 if (dev->data->dev_conf.intr_conf.rxq != 0) {
607 intr_vector = dev->data->nb_rx_queues;
608 if (rte_intr_efd_enable(intr_handle, intr_vector))
612 if (rte_intr_dp_is_en(intr_handle)) {
613 intr_handle->intr_vec =
614 rte_zmalloc("intr_vec",
615 dev->data->nb_rx_queues * sizeof(int), 0);
616 if (intr_handle->intr_vec == NULL) {
617 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
618 " intr_vec\n", dev->data->nb_rx_queues);
622 /* enable rx interrupt */
623 em_rxq_intr_enable(hw);
628 ret = eth_em_rx_init(dev);
630 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
631 em_dev_clear_queues(dev);
635 e1000_clear_hw_cntrs_base_generic(hw);
637 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
638 ETH_VLAN_EXTEND_MASK;
639 eth_em_vlan_offload_set(dev, mask);
641 /* Set Interrupt Throttling Rate to maximum allowed value. */
642 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
644 /* Setup link speed and duplex */
645 speeds = &dev->data->dev_conf.link_speeds;
646 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
647 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
650 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
653 hw->phy.autoneg_advertised = 0;
655 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
656 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
657 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
659 goto error_invalid_config;
661 if (*speeds & ETH_LINK_SPEED_10M_HD) {
662 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
665 if (*speeds & ETH_LINK_SPEED_10M) {
666 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
669 if (*speeds & ETH_LINK_SPEED_100M_HD) {
670 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
673 if (*speeds & ETH_LINK_SPEED_100M) {
674 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
677 if (*speeds & ETH_LINK_SPEED_1G) {
678 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
681 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
682 goto error_invalid_config;
685 e1000_setup_link(hw);
687 if (rte_intr_allow_others(intr_handle)) {
688 /* check if lsc interrupt is enabled */
689 if (dev->data->dev_conf.intr_conf.lsc != 0) {
690 ret = eth_em_interrupt_setup(dev);
692 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
693 em_dev_clear_queues(dev);
698 rte_intr_callback_unregister(intr_handle,
699 eth_em_interrupt_handler,
701 if (dev->data->dev_conf.intr_conf.lsc != 0)
702 PMD_INIT_LOG(INFO, "lsc won't enable because of"
703 " no intr multiplex\n");
705 /* check if rxq interrupt is enabled */
706 if (dev->data->dev_conf.intr_conf.rxq != 0)
707 eth_em_rxq_interrupt_setup(dev);
709 rte_intr_enable(intr_handle);
711 adapter->stopped = 0;
713 PMD_INIT_LOG(DEBUG, "<<");
717 error_invalid_config:
718 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
719 dev->data->dev_conf.link_speeds, dev->data->port_id);
720 em_dev_clear_queues(dev);
724 /*********************************************************************
726 * This routine disables all traffic on the adapter by issuing a
727 * global reset on the MAC.
729 **********************************************************************/
731 eth_em_stop(struct rte_eth_dev *dev)
733 struct rte_eth_link link;
734 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
735 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
737 em_rxq_intr_disable(hw);
738 em_lsc_intr_disable(hw);
741 if (hw->mac.type >= e1000_82544)
742 E1000_WRITE_REG(hw, E1000_WUC, 0);
744 /* Power down the phy. Needed to make the link go down */
745 e1000_power_down_phy(hw);
747 em_dev_clear_queues(dev);
749 /* clear the recorded link status */
750 memset(&link, 0, sizeof(link));
751 rte_em_dev_atomic_write_link_status(dev, &link);
753 if (!rte_intr_allow_others(intr_handle))
754 /* resume to the default handler */
755 rte_intr_callback_register(intr_handle,
756 eth_em_interrupt_handler,
759 /* Clean datapath event and queue/vec mapping */
760 rte_intr_efd_disable(intr_handle);
761 if (intr_handle->intr_vec != NULL) {
762 rte_free(intr_handle->intr_vec);
763 intr_handle->intr_vec = NULL;
768 eth_em_close(struct rte_eth_dev *dev)
770 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
771 struct e1000_adapter *adapter =
772 E1000_DEV_PRIVATE(dev->data->dev_private);
775 adapter->stopped = 1;
776 em_dev_free_queues(dev);
777 e1000_phy_hw_reset(hw);
778 em_release_manageability(hw);
779 em_hw_control_release(hw);
783 em_get_rx_buffer_size(struct e1000_hw *hw)
785 uint32_t rx_buf_size;
787 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
791 /*********************************************************************
793 * Initialize the hardware
795 **********************************************************************/
797 em_hardware_init(struct e1000_hw *hw)
799 uint32_t rx_buf_size;
802 /* Issue a global reset */
805 /* Let the firmware know the OS is in control */
806 em_hw_control_acquire(hw);
809 * These parameters control the automatic generation (Tx) and
810 * response (Rx) to Ethernet PAUSE frames.
811 * - High water mark should allow for at least two standard size (1518)
812 * frames to be received after sending an XOFF.
813 * - Low water mark works best when it is very near the high water mark.
814 * This allows the receiver to restart by sending XON when it has
815 * drained a bit. Here we use an arbitrary value of 1500 which will
816 * restart after one full frame is pulled from the buffer. There
817 * could be several smaller frames in the buffer and if so they will
818 * not trigger the XON until their total number reduces the buffer
820 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
822 rx_buf_size = em_get_rx_buffer_size(hw);
824 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
825 hw->fc.low_water = hw->fc.high_water - 1500;
827 if (hw->mac.type == e1000_80003es2lan)
828 hw->fc.pause_time = UINT16_MAX;
830 hw->fc.pause_time = EM_FC_PAUSE_TIME;
834 /* Set Flow control, use the tunable location if sane */
835 if (em_fc_setting <= e1000_fc_full)
836 hw->fc.requested_mode = em_fc_setting;
838 hw->fc.requested_mode = e1000_fc_none;
840 /* Workaround: no TX flow ctrl for PCH */
841 if (hw->mac.type == e1000_pchlan)
842 hw->fc.requested_mode = e1000_fc_rx_pause;
844 /* Override - settings for PCH2LAN, ya its magic :) */
845 if (hw->mac.type == e1000_pch2lan) {
846 hw->fc.high_water = 0x5C20;
847 hw->fc.low_water = 0x5048;
848 hw->fc.pause_time = 0x0650;
849 hw->fc.refresh_time = 0x0400;
850 } else if (hw->mac.type == e1000_pch_lpt) {
851 hw->fc.requested_mode = e1000_fc_full;
854 diag = e1000_init_hw(hw);
857 e1000_check_for_link(hw);
861 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
863 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
865 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
866 struct e1000_hw_stats *stats =
867 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
870 if(hw->phy.media_type == e1000_media_type_copper ||
871 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
872 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
873 stats->sec += E1000_READ_REG(hw, E1000_SEC);
876 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
877 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
878 stats->scc += E1000_READ_REG(hw, E1000_SCC);
879 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
881 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
882 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
883 stats->colc += E1000_READ_REG(hw, E1000_COLC);
884 stats->dc += E1000_READ_REG(hw, E1000_DC);
885 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
886 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
887 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
890 * For watchdog management we need to know if we have been
891 * paused during the last interval, so capture that here.
893 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
894 stats->xoffrxc += pause_frames;
895 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
896 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
897 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
898 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
899 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
900 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
901 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
902 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
903 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
904 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
905 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
906 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
909 * For the 64-bit byte counters the low dword must be read first.
910 * Both registers clear on the read of the high dword.
913 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
914 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
915 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
916 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
918 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
919 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
920 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
921 stats->roc += E1000_READ_REG(hw, E1000_ROC);
922 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
924 stats->tor += E1000_READ_REG(hw, E1000_TORH);
925 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
927 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
928 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
929 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
930 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
931 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
932 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
933 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
934 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
935 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
936 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
938 /* Interrupt Counts */
940 if (hw->mac.type >= e1000_82571) {
941 stats->iac += E1000_READ_REG(hw, E1000_IAC);
942 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
943 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
944 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
945 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
946 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
947 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
948 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
949 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
952 if (hw->mac.type >= e1000_82543) {
953 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
954 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
955 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
956 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
957 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
958 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
961 if (rte_stats == NULL)
965 rte_stats->imissed = stats->mpc;
966 rte_stats->ierrors = stats->crcerrs +
967 stats->rlec + stats->ruc + stats->roc +
968 stats->rxerrc + stats->algnerrc + stats->cexterr;
971 rte_stats->oerrors = stats->ecol + stats->latecol;
973 rte_stats->ipackets = stats->gprc;
974 rte_stats->opackets = stats->gptc;
975 rte_stats->ibytes = stats->gorc;
976 rte_stats->obytes = stats->gotc;
980 eth_em_stats_reset(struct rte_eth_dev *dev)
982 struct e1000_hw_stats *hw_stats =
983 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
985 /* HW registers are cleared on read */
986 eth_em_stats_get(dev, NULL);
988 /* Reset software totals */
989 memset(hw_stats, 0, sizeof(*hw_stats));
993 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
995 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
997 em_rxq_intr_enable(hw);
998 rte_intr_enable(&dev->pci_dev->intr_handle);
1004 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1006 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1008 em_rxq_intr_disable(hw);
1014 em_get_max_pktlen(const struct e1000_hw *hw)
1016 switch (hw->mac.type) {
1020 case e1000_ich10lan:
1024 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1029 /* Adapters that do not support jumbo frames */
1031 return ETHER_MAX_LEN;
1033 return MAX_JUMBO_FRAME_SIZE;
1038 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1040 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1042 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1043 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1044 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1047 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1048 * Unfortunatelly, all these nics have just one TX context.
1049 * So we have few choises for TX:
1050 * - Use just one TX queue.
1051 * - Allow cksum offload only for one TX queue.
1052 * - Don't allow TX cksum offload at all.
1053 * For now, option #1 was chosen.
1054 * To use second RX queue we have to use extended RX descriptor
1055 * (Multiple Receive Queues are mutually exclusive with UDP
1056 * fragmentation and are not supported when a legacy receive
1057 * descriptor format is used).
1058 * Which means separate RX routinies - as legacy nics (82540, 82545)
1059 * don't support extended RXD.
1060 * To avoid it we support just one RX queue for now (no RSS).
1063 dev_info->max_rx_queues = 1;
1064 dev_info->max_tx_queues = 1;
1066 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1067 .nb_max = E1000_MAX_RING_DESC,
1068 .nb_min = E1000_MIN_RING_DESC,
1069 .nb_align = EM_RXD_ALIGN,
1072 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1073 .nb_max = E1000_MAX_RING_DESC,
1074 .nb_min = E1000_MIN_RING_DESC,
1075 .nb_align = EM_TXD_ALIGN,
1078 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1079 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1083 /* return 0 means link status changed, -1 means not changed */
1085 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1087 struct e1000_hw *hw =
1088 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089 struct rte_eth_link link, old;
1090 int link_check, count;
1093 hw->mac.get_link_status = 1;
1095 /* possible wait-to-complete in up to 9 seconds */
1096 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1097 /* Read the real link status */
1098 switch (hw->phy.media_type) {
1099 case e1000_media_type_copper:
1100 /* Do the work to read phy */
1101 e1000_check_for_link(hw);
1102 link_check = !hw->mac.get_link_status;
1105 case e1000_media_type_fiber:
1106 e1000_check_for_link(hw);
1107 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1111 case e1000_media_type_internal_serdes:
1112 e1000_check_for_link(hw);
1113 link_check = hw->mac.serdes_has_link;
1119 if (link_check || wait_to_complete == 0)
1121 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1123 memset(&link, 0, sizeof(link));
1124 rte_em_dev_atomic_read_link_status(dev, &link);
1127 /* Now we check if a transition has happened */
1128 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1129 uint16_t duplex, speed;
1130 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1131 link.link_duplex = (duplex == FULL_DUPLEX) ?
1132 ETH_LINK_FULL_DUPLEX :
1133 ETH_LINK_HALF_DUPLEX;
1134 link.link_speed = speed;
1135 link.link_status = ETH_LINK_UP;
1136 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1137 ETH_LINK_SPEED_FIXED);
1138 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1139 link.link_speed = 0;
1140 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1141 link.link_status = ETH_LINK_DOWN;
1142 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1144 rte_em_dev_atomic_write_link_status(dev, &link);
1147 if (old.link_status == link.link_status)
1155 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1156 * For ASF and Pass Through versions of f/w this means
1157 * that the driver is loaded. For AMT version type f/w
1158 * this means that the network i/f is open.
1161 em_hw_control_acquire(struct e1000_hw *hw)
1163 uint32_t ctrl_ext, swsm;
1165 /* Let firmware know the driver has taken over */
1166 if (hw->mac.type == e1000_82573) {
1167 swsm = E1000_READ_REG(hw, E1000_SWSM);
1168 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1171 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1172 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1173 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1178 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1179 * For ASF and Pass Through versions of f/w this means that the
1180 * driver is no longer loaded. For AMT versions of the
1181 * f/w this means that the network i/f is closed.
1184 em_hw_control_release(struct e1000_hw *hw)
1186 uint32_t ctrl_ext, swsm;
1188 /* Let firmware taken over control of h/w */
1189 if (hw->mac.type == e1000_82573) {
1190 swsm = E1000_READ_REG(hw, E1000_SWSM);
1191 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1193 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1194 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1195 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1200 * Bit of a misnomer, what this really means is
1201 * to enable OS management of the system... aka
1202 * to disable special hardware management features.
1205 em_init_manageability(struct e1000_hw *hw)
1207 if (e1000_enable_mng_pass_thru(hw)) {
1208 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1209 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1211 /* disable hardware interception of ARP */
1212 manc &= ~(E1000_MANC_ARP_EN);
1214 /* enable receiving management packets to the host */
1215 manc |= E1000_MANC_EN_MNG2HOST;
1216 manc2h |= 1 << 5; /* Mng Port 623 */
1217 manc2h |= 1 << 6; /* Mng Port 664 */
1218 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1219 E1000_WRITE_REG(hw, E1000_MANC, manc);
1224 * Give control back to hardware management
1225 * controller if there is one.
1228 em_release_manageability(struct e1000_hw *hw)
1232 if (e1000_enable_mng_pass_thru(hw)) {
1233 manc = E1000_READ_REG(hw, E1000_MANC);
1235 /* re-enable hardware interception of ARP */
1236 manc |= E1000_MANC_ARP_EN;
1237 manc &= ~E1000_MANC_EN_MNG2HOST;
1239 E1000_WRITE_REG(hw, E1000_MANC, manc);
1244 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1246 struct e1000_hw *hw =
1247 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1250 rctl = E1000_READ_REG(hw, E1000_RCTL);
1251 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1252 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1256 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1258 struct e1000_hw *hw =
1259 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1262 rctl = E1000_READ_REG(hw, E1000_RCTL);
1263 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1264 if (dev->data->all_multicast == 1)
1265 rctl |= E1000_RCTL_MPE;
1267 rctl &= (~E1000_RCTL_MPE);
1268 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1272 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1274 struct e1000_hw *hw =
1275 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1278 rctl = E1000_READ_REG(hw, E1000_RCTL);
1279 rctl |= E1000_RCTL_MPE;
1280 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1284 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1286 struct e1000_hw *hw =
1287 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1290 if (dev->data->promiscuous == 1)
1291 return; /* must remain in all_multicast mode */
1292 rctl = E1000_READ_REG(hw, E1000_RCTL);
1293 rctl &= (~E1000_RCTL_MPE);
1294 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1298 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1300 struct e1000_hw *hw =
1301 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1302 struct e1000_vfta * shadow_vfta =
1303 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1308 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1309 E1000_VFTA_ENTRY_MASK);
1310 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1311 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1316 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1318 /* update local VFTA copy */
1319 shadow_vfta->vfta[vid_idx] = vfta;
1325 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1327 struct e1000_hw *hw =
1328 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1331 /* Filter Table Disable */
1332 reg = E1000_READ_REG(hw, E1000_RCTL);
1333 reg &= ~E1000_RCTL_CFIEN;
1334 reg &= ~E1000_RCTL_VFE;
1335 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1339 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1341 struct e1000_hw *hw =
1342 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343 struct e1000_vfta * shadow_vfta =
1344 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1348 /* Filter Table Enable, CFI not used for packet acceptance */
1349 reg = E1000_READ_REG(hw, E1000_RCTL);
1350 reg &= ~E1000_RCTL_CFIEN;
1351 reg |= E1000_RCTL_VFE;
1352 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1354 /* restore vfta from local copy */
1355 for (i = 0; i < IGB_VFTA_SIZE; i++)
1356 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1360 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1362 struct e1000_hw *hw =
1363 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366 /* VLAN Mode Disable */
1367 reg = E1000_READ_REG(hw, E1000_CTRL);
1368 reg &= ~E1000_CTRL_VME;
1369 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1374 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1376 struct e1000_hw *hw =
1377 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380 /* VLAN Mode Enable */
1381 reg = E1000_READ_REG(hw, E1000_CTRL);
1382 reg |= E1000_CTRL_VME;
1383 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1387 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1389 if(mask & ETH_VLAN_STRIP_MASK){
1390 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1391 em_vlan_hw_strip_enable(dev);
1393 em_vlan_hw_strip_disable(dev);
1396 if(mask & ETH_VLAN_FILTER_MASK){
1397 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1398 em_vlan_hw_filter_enable(dev);
1400 em_vlan_hw_filter_disable(dev);
1405 * It enables the interrupt mask and then enable the interrupt.
1408 * Pointer to struct rte_eth_dev.
1411 * - On success, zero.
1412 * - On failure, a negative value.
1415 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1418 struct e1000_hw *hw =
1419 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421 /* clear interrupt */
1422 E1000_READ_REG(hw, E1000_ICR);
1423 regval = E1000_READ_REG(hw, E1000_IMS);
1424 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1429 * It clears the interrupt causes and enables the interrupt.
1430 * It will be called once only during nic initialized.
1433 * Pointer to struct rte_eth_dev.
1436 * - On success, zero.
1437 * - On failure, a negative value.
1440 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1442 struct e1000_hw *hw =
1443 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445 E1000_READ_REG(hw, E1000_ICR);
1446 em_rxq_intr_enable(hw);
1451 * It enable receive packet interrupt.
1453 * Pointer to struct e1000_hw
1458 em_rxq_intr_enable(struct e1000_hw *hw)
1460 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1461 E1000_WRITE_FLUSH(hw);
1465 * It disabled lsc interrupt.
1467 * Pointer to struct e1000_hw
1472 em_lsc_intr_disable(struct e1000_hw *hw)
1474 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1475 E1000_WRITE_FLUSH(hw);
1479 * It disabled receive packet interrupt.
1481 * Pointer to struct e1000_hw
1486 em_rxq_intr_disable(struct e1000_hw *hw)
1488 E1000_READ_REG(hw, E1000_ICR);
1489 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1490 E1000_WRITE_FLUSH(hw);
1494 * It reads ICR and gets interrupt causes, check it and set a bit flag
1495 * to update link status.
1498 * Pointer to struct rte_eth_dev.
1501 * - On success, zero.
1502 * - On failure, a negative value.
1505 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1508 struct e1000_hw *hw =
1509 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510 struct e1000_interrupt *intr =
1511 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1513 /* read-on-clear nic registers here */
1514 icr = E1000_READ_REG(hw, E1000_ICR);
1515 if (icr & E1000_ICR_LSC) {
1516 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1523 * It executes link_update after knowing an interrupt is prsent.
1526 * Pointer to struct rte_eth_dev.
1529 * - On success, zero.
1530 * - On failure, a negative value.
1533 eth_em_interrupt_action(struct rte_eth_dev *dev)
1535 struct e1000_hw *hw =
1536 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537 struct e1000_interrupt *intr =
1538 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1539 uint32_t tctl, rctl;
1540 struct rte_eth_link link;
1543 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1546 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1547 rte_intr_enable(&(dev->pci_dev->intr_handle));
1549 /* set get_link_status to check register later */
1550 hw->mac.get_link_status = 1;
1551 ret = eth_em_link_update(dev, 0);
1553 /* check if link has changed */
1557 memset(&link, 0, sizeof(link));
1558 rte_em_dev_atomic_read_link_status(dev, &link);
1559 if (link.link_status) {
1560 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1561 dev->data->port_id, (unsigned)link.link_speed,
1562 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1563 "full-duplex" : "half-duplex");
1565 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1567 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1568 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1569 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1571 tctl = E1000_READ_REG(hw, E1000_TCTL);
1572 rctl = E1000_READ_REG(hw, E1000_RCTL);
1573 if (link.link_status) {
1575 tctl |= E1000_TCTL_EN;
1576 rctl |= E1000_RCTL_EN;
1579 tctl &= ~E1000_TCTL_EN;
1580 rctl &= ~E1000_RCTL_EN;
1582 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1583 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1584 E1000_WRITE_FLUSH(hw);
1590 * Interrupt handler which shall be registered at first.
1593 * Pointer to interrupt handle.
1595 * The address of parameter (struct rte_eth_dev *) regsitered before.
1601 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1604 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1606 eth_em_interrupt_get_status(dev);
1607 eth_em_interrupt_action(dev);
1608 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1612 eth_em_led_on(struct rte_eth_dev *dev)
1614 struct e1000_hw *hw;
1616 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1621 eth_em_led_off(struct rte_eth_dev *dev)
1623 struct e1000_hw *hw;
1625 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1630 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1632 struct e1000_hw *hw;
1637 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638 fc_conf->pause_time = hw->fc.pause_time;
1639 fc_conf->high_water = hw->fc.high_water;
1640 fc_conf->low_water = hw->fc.low_water;
1641 fc_conf->send_xon = hw->fc.send_xon;
1642 fc_conf->autoneg = hw->mac.autoneg;
1645 * Return rx_pause and tx_pause status according to actual setting of
1646 * the TFCE and RFCE bits in the CTRL register.
1648 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1649 if (ctrl & E1000_CTRL_TFCE)
1654 if (ctrl & E1000_CTRL_RFCE)
1659 if (rx_pause && tx_pause)
1660 fc_conf->mode = RTE_FC_FULL;
1662 fc_conf->mode = RTE_FC_RX_PAUSE;
1664 fc_conf->mode = RTE_FC_TX_PAUSE;
1666 fc_conf->mode = RTE_FC_NONE;
1672 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1674 struct e1000_hw *hw;
1676 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1682 uint32_t rx_buf_size;
1683 uint32_t max_high_water;
1686 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687 if (fc_conf->autoneg != hw->mac.autoneg)
1689 rx_buf_size = em_get_rx_buffer_size(hw);
1690 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1692 /* At least reserve one Ethernet frame for watermark */
1693 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1694 if ((fc_conf->high_water > max_high_water) ||
1695 (fc_conf->high_water < fc_conf->low_water)) {
1696 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1697 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1701 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1702 hw->fc.pause_time = fc_conf->pause_time;
1703 hw->fc.high_water = fc_conf->high_water;
1704 hw->fc.low_water = fc_conf->low_water;
1705 hw->fc.send_xon = fc_conf->send_xon;
1707 err = e1000_setup_link_generic(hw);
1708 if (err == E1000_SUCCESS) {
1710 /* check if we want to forward MAC frames - driver doesn't have native
1711 * capability to do that, so we'll write the registers ourselves */
1713 rctl = E1000_READ_REG(hw, E1000_RCTL);
1715 /* set or clear MFLCN.PMCF bit depending on configuration */
1716 if (fc_conf->mac_ctrl_frame_fwd != 0)
1717 rctl |= E1000_RCTL_PMCF;
1719 rctl &= ~E1000_RCTL_PMCF;
1721 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1722 E1000_WRITE_FLUSH(hw);
1727 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1732 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1733 uint32_t index, __rte_unused uint32_t pool)
1735 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1741 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1743 uint8_t addr[ETHER_ADDR_LEN];
1744 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746 memset(addr, 0, sizeof(addr));
1748 e1000_rar_set(hw, addr, index);
1752 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1754 struct rte_eth_dev_info dev_info;
1755 struct e1000_hw *hw;
1756 uint32_t frame_size;
1759 eth_em_infos_get(dev, &dev_info);
1760 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1762 /* check that mtu is within the allowed range */
1763 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1766 /* refuse mtu that requires the support of scattered packets when this
1767 * feature has not been enabled before. */
1768 if (!dev->data->scattered_rx &&
1769 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1772 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1773 rctl = E1000_READ_REG(hw, E1000_RCTL);
1775 /* switch to jumbo mode if needed */
1776 if (frame_size > ETHER_MAX_LEN) {
1777 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1778 rctl |= E1000_RCTL_LPE;
1780 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1781 rctl &= ~E1000_RCTL_LPE;
1783 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1785 /* update max frame size */
1786 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1791 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1792 struct ether_addr *mc_addr_set,
1793 uint32_t nb_mc_addr)
1795 struct e1000_hw *hw;
1797 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1802 struct rte_driver em_pmd_drv = {
1804 .init = rte_em_pmd_init,
1807 PMD_REGISTER_DRIVER(em_pmd_drv, em);
1808 DRIVER_REGISTER_PCI_TABLE(em, pci_id_em_map);