drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  86 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  87                                                         void *param);
  88
  89 static int em_hw_init(struct e1000_hw *hw);
  90 static int em_hardware_init(struct e1000_hw *hw);
  91 static void em_hw_control_acquire(struct e1000_hw *hw);
  92 static void em_hw_control_release(struct e1000_hw *hw);
  93 static void em_init_manageability(struct e1000_hw *hw);
  94 static void em_release_manageability(struct e1000_hw *hw);
  95
  96 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  97
  98 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  99                 uint16_t vlan_id, int on);
 100 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 101 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 102 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 103 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 105
 106 /*
 107 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 108                                         uint16_t vlan_id, int on);
 109 */
 110 static int eth_em_led_on(struct rte_eth_dev *dev);
 111 static int eth_em_led_off(struct rte_eth_dev *dev);
 112
 113 static void em_intr_disable(struct e1000_hw *hw);
 114 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 115 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 116                 uint32_t index, uint32_t pool);
 117 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 118
 119 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 120                                    struct ether_addr *mc_addr_set,
 121                                    uint32_t nb_mc_addr);
 122
 123 #define EM_FC_PAUSE_TIME 0x0680
 124 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 125 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 126
 127 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 128
 129 /*
 130  * The set of PCI devices this driver supports
 131  */
 132 static const struct rte_pci_id pci_id_em_map[] = {
 133
 134 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 135 #include "rte_pci_dev_ids.h"
 136
 137 {0},
 138 };
 139
 140 static const struct eth_dev_ops eth_em_ops = {
 141         .dev_configure        = eth_em_configure,
 142         .dev_start            = eth_em_start,
 143         .dev_stop             = eth_em_stop,
 144         .dev_close            = eth_em_close,
 145         .promiscuous_enable   = eth_em_promiscuous_enable,
 146         .promiscuous_disable  = eth_em_promiscuous_disable,
 147         .allmulticast_enable  = eth_em_allmulticast_enable,
 148         .allmulticast_disable = eth_em_allmulticast_disable,
 149         .link_update          = eth_em_link_update,
 150         .stats_get            = eth_em_stats_get,
 151         .stats_reset          = eth_em_stats_reset,
 152         .dev_infos_get        = eth_em_infos_get,
 153         .mtu_set              = eth_em_mtu_set,
 154         .vlan_filter_set      = eth_em_vlan_filter_set,
 155         .vlan_offload_set     = eth_em_vlan_offload_set,
 156         .rx_queue_setup       = eth_em_rx_queue_setup,
 157         .rx_queue_release     = eth_em_rx_queue_release,
 158         .rx_queue_count       = eth_em_rx_queue_count,
 159         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 160         .tx_queue_setup       = eth_em_tx_queue_setup,
 161         .tx_queue_release     = eth_em_tx_queue_release,
 162         .dev_led_on           = eth_em_led_on,
 163         .dev_led_off          = eth_em_led_off,
 164         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 165         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 166         .mac_addr_add         = eth_em_rar_set,
 167         .mac_addr_remove      = eth_em_rar_clear,
 168         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 169 };
 170
 171 /**
 172  * Atomically reads the link status information from global
 173  * structure rte_eth_dev.
 174  *
 175  * @param dev
 176  *   - Pointer to the structure rte_eth_dev to read from.
 177  *   - Pointer to the buffer to be saved with the link status.
 178  *
 179  * @return
 180  *   - On success, zero.
 181  *   - On failure, negative value.
 182  */
 183 static inline int
 184 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 185                                 struct rte_eth_link *link)
 186 {
 187         struct rte_eth_link *dst = link;
 188         struct rte_eth_link *src = &(dev->data->dev_link);
 189
 190         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 191                                         *(uint64_t *)src) == 0)
 192                 return -1;
 193
 194         return 0;
 195 }
 196
 197 /**
 198  * Atomically writes the link status information into global
 199  * structure rte_eth_dev.
 200  *
 201  * @param dev
 202  *   - Pointer to the structure rte_eth_dev to read from.
 203  *   - Pointer to the buffer to be saved with the link status.
 204  *
 205  * @return
 206  *   - On success, zero.
 207  *   - On failure, negative value.
 208  */
 209 static inline int
 210 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 211                                 struct rte_eth_link *link)
 212 {
 213         struct rte_eth_link *dst = &(dev->data->dev_link);
 214         struct rte_eth_link *src = link;
 215
 216         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 217                                         *(uint64_t *)src) == 0)
 218                 return -1;
 219
 220         return 0;
 221 }
 222
 223 static int
 224 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 225 {
 226         struct rte_pci_device *pci_dev;
 227         struct e1000_adapter *adapter =
 228                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 229         struct e1000_hw *hw =
 230                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 231         struct e1000_vfta * shadow_vfta =
 232                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 233
 234         pci_dev = eth_dev->pci_dev;
 235         eth_dev->dev_ops = &eth_em_ops;
 236         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 237         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 238
 239         /* for secondary processes, we don't initialise any further as primary
 240          * has already done this work. Only check we don't need a different
 241          * RX function */
 242         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 243                 if (eth_dev->data->scattered_rx)
 244                         eth_dev->rx_pkt_burst =
 245                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 246                 return 0;
 247         }
 248
 249         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 250         hw->device_id = pci_dev->id.device_id;
 251         adapter->stopped = 0;
 252
 253         /* For ICH8 support we'll need to map the flash memory BAR */
 254
 255         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 256                         em_hw_init(hw) != 0) {
 257                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 258                         "failed to init HW",
 259                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 260                         pci_dev->id.device_id);
 261                 return -(ENODEV);
 262         }
 263
 264         /* Allocate memory for storing MAC addresses */
 265         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 266                         hw->mac.rar_entry_count, 0);
 267         if (eth_dev->data->mac_addrs == NULL) {
 268                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 269                         "store MAC addresses",
 270                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 271                 return -(ENOMEM);
 272         }
 273
 274         /* Copy the permanent MAC address */
 275         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 276                 eth_dev->data->mac_addrs);
 277
 278         /* initialize the vfta */
 279         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 280
 281         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 282                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 283                      pci_dev->id.device_id);
 284
 285         rte_intr_callback_register(&(pci_dev->intr_handle),
 286                 eth_em_interrupt_handler, (void *)eth_dev);
 287
 288         return (0);
 289 }
 290
 291 static int
 292 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 293 {
 294         struct rte_pci_device *pci_dev;
 295         struct e1000_adapter *adapter =
 296                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 297
 298         PMD_INIT_FUNC_TRACE();
 299
 300         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 301                 return -EPERM;
 302
 303         pci_dev = eth_dev->pci_dev;
 304
 305         if (adapter->stopped == 0)
 306                 eth_em_close(eth_dev);
 307
 308         eth_dev->dev_ops = NULL;
 309         eth_dev->rx_pkt_burst = NULL;
 310         eth_dev->tx_pkt_burst = NULL;
 311
 312         rte_free(eth_dev->data->mac_addrs);
 313         eth_dev->data->mac_addrs = NULL;
 314
 315         /* disable uio intr before callback unregister */
 316         rte_intr_disable(&(pci_dev->intr_handle));
 317         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 318                 eth_em_interrupt_handler, (void *)eth_dev);
 319
 320         return 0;
 321 }
 322
 323 static struct eth_driver rte_em_pmd = {
 324         .pci_drv = {
 325                 .name = "rte_em_pmd",
 326                 .id_table = pci_id_em_map,
 327                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 328                         RTE_PCI_DRV_DETACHABLE,
 329         },
 330         .eth_dev_init = eth_em_dev_init,
 331         .eth_dev_uninit = eth_em_dev_uninit,
 332         .dev_private_size = sizeof(struct e1000_adapter),
 333 };
 334
 335 static int
 336 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 337 {
 338         rte_eth_driver_register(&rte_em_pmd);
 339         return 0;
 340 }
 341
 342 static int
 343 em_hw_init(struct e1000_hw *hw)
 344 {
 345         int diag;
 346
 347         diag = hw->mac.ops.init_params(hw);
 348         if (diag != 0) {
 349                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 350                 return diag;
 351         }
 352         diag = hw->nvm.ops.init_params(hw);
 353         if (diag != 0) {
 354                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 355                 return diag;
 356         }
 357         diag = hw->phy.ops.init_params(hw);
 358         if (diag != 0) {
 359                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 360                 return diag;
 361         }
 362         (void) e1000_get_bus_info(hw);
 363
 364         hw->mac.autoneg = 1;
 365         hw->phy.autoneg_wait_to_complete = 0;
 366         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 367
 368         e1000_init_script_state_82541(hw, TRUE);
 369         e1000_set_tbi_compatibility_82543(hw, TRUE);
 370
 371         /* Copper options */
 372         if (hw->phy.media_type == e1000_media_type_copper) {
 373                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 374                 hw->phy.disable_polarity_correction = 0;
 375                 hw->phy.ms_type = e1000_ms_hw_default;
 376         }
 377
 378         /*
 379          * Start from a known state, this is important in reading the nvm
 380          * and mac from that.
 381          */
 382         e1000_reset_hw(hw);
 383
 384         /* Make sure we have a good EEPROM before we read from it */
 385         if (e1000_validate_nvm_checksum(hw) < 0) {
 386                 /*
 387                  * Some PCI-E parts fail the first check due to
 388                  * the link being in sleep state, call it again,
 389                  * if it fails a second time its a real issue.
 390                  */
 391                 diag = e1000_validate_nvm_checksum(hw);
 392                 if (diag < 0) {
 393                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 394                         goto error;
 395                 }
 396         }
 397
 398         /* Read the permanent MAC address out of the EEPROM */
 399         diag = e1000_read_mac_addr(hw);
 400         if (diag != 0) {
 401                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 402                 goto error;
 403         }
 404
 405         /* Now initialize the hardware */
 406         diag = em_hardware_init(hw);
 407         if (diag != 0) {
 408                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 409                 goto error;
 410         }
 411
 412         hw->mac.get_link_status = 1;
 413
 414         /* Indicate SOL/IDER usage */
 415         diag = e1000_check_reset_block(hw);
 416         if (diag < 0) {
 417                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 418                         "SOL/IDER session");
 419         }
 420         return (0);
 421
 422 error:
 423         em_hw_control_release(hw);
 424         return (diag);
 425 }
 426
 427 static int
 428 eth_em_configure(struct rte_eth_dev *dev)
 429 {
 430         struct e1000_interrupt *intr =
 431                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 432
 433         PMD_INIT_FUNC_TRACE();
 434         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 435         PMD_INIT_FUNC_TRACE();
 436
 437         return (0);
 438 }
 439
 440 static void
 441 em_set_pba(struct e1000_hw *hw)
 442 {
 443         uint32_t pba;
 444
 445         /*
 446          * Packet Buffer Allocation (PBA)
 447          * Writing PBA sets the receive portion of the buffer
 448          * the remainder is used for the transmit buffer.
 449          * Devices before the 82547 had a Packet Buffer of 64K.
 450          * After the 82547 the buffer was reduced to 40K.
 451          */
 452         switch (hw->mac.type) {
 453                 case e1000_82547:
 454                 case e1000_82547_rev_2:
 455                 /* 82547: Total Packet Buffer is 40K */
 456                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 457                         break;
 458                 case e1000_82571:
 459                 case e1000_82572:
 460                 case e1000_80003es2lan:
 461                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 462                         break;
 463                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 464                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 465                         break;
 466                 case e1000_82574:
 467                 case e1000_82583:
 468                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 469                         break;
 470                 case e1000_ich8lan:
 471                         pba = E1000_PBA_8K;
 472                         break;
 473                 case e1000_ich9lan:
 474                 case e1000_ich10lan:
 475                         pba = E1000_PBA_10K;
 476                         break;
 477                 case e1000_pchlan:
 478                 case e1000_pch2lan:
 479                         pba = E1000_PBA_26K;
 480                         break;
 481                 default:
 482                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 483         }
 484
 485         E1000_WRITE_REG(hw, E1000_PBA, pba);
 486 }
 487
 488 static int
 489 eth_em_start(struct rte_eth_dev *dev)
 490 {
 491         struct e1000_adapter *adapter =
 492                 E1000_DEV_PRIVATE(dev->data->dev_private);
 493         struct e1000_hw *hw =
 494                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 495         int ret, mask;
 496
 497         PMD_INIT_FUNC_TRACE();
 498
 499         eth_em_stop(dev);
 500
 501         e1000_power_up_phy(hw);
 502
 503         /* Set default PBA value */
 504         em_set_pba(hw);
 505
 506         /* Put the address into the Receive Address Array */
 507         e1000_rar_set(hw, hw->mac.addr, 0);
 508
 509         /*
 510          * With the 82571 adapter, RAR[0] may be overwritten
 511          * when the other port is reset, we make a duplicate
 512          * in RAR[14] for that eventuality, this assures
 513          * the interface continues to function.
 514          */
 515         if (hw->mac.type == e1000_82571) {
 516                 e1000_set_laa_state_82571(hw, TRUE);
 517                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 518         }
 519
 520         /* Initialize the hardware */
 521         if (em_hardware_init(hw)) {
 522                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 523                 return (-EIO);
 524         }
 525
 526         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 527
 528         /* Configure for OS presence */
 529         em_init_manageability(hw);
 530
 531         eth_em_tx_init(dev);
 532
 533         ret = eth_em_rx_init(dev);
 534         if (ret) {
 535                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 536                 em_dev_clear_queues(dev);
 537                 return ret;
 538         }
 539
 540         e1000_clear_hw_cntrs_base_generic(hw);
 541
 542         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 543                         ETH_VLAN_EXTEND_MASK;
 544         eth_em_vlan_offload_set(dev, mask);
 545
 546         /* Set Interrupt Throttling Rate to maximum allowed value. */
 547         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 548
 549         /* Setup link speed and duplex */
 550         switch (dev->data->dev_conf.link_speed) {
 551         case ETH_LINK_SPEED_AUTONEG:
 552                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 553                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 554                 else if (dev->data->dev_conf.link_duplex ==
 555                                         ETH_LINK_HALF_DUPLEX)
 556                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 557                 else if (dev->data->dev_conf.link_duplex ==
 558                                         ETH_LINK_FULL_DUPLEX)
 559                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 560                 else
 561                         goto error_invalid_config;
 562                 break;
 563         case ETH_LINK_SPEED_10:
 564                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 565                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 566                 else if (dev->data->dev_conf.link_duplex ==
 567                                         ETH_LINK_HALF_DUPLEX)
 568                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 569                 else if (dev->data->dev_conf.link_duplex ==
 570                                         ETH_LINK_FULL_DUPLEX)
 571                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 572                 else
 573                         goto error_invalid_config;
 574                 break;
 575         case ETH_LINK_SPEED_100:
 576                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 577                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 578                 else if (dev->data->dev_conf.link_duplex ==
 579                                         ETH_LINK_HALF_DUPLEX)
 580                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 581                 else if (dev->data->dev_conf.link_duplex ==
 582                                         ETH_LINK_FULL_DUPLEX)
 583                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 584                 else
 585                         goto error_invalid_config;
 586                 break;
 587         case ETH_LINK_SPEED_1000:
 588                 if ((dev->data->dev_conf.link_duplex ==
 589                                 ETH_LINK_AUTONEG_DUPLEX) ||
 590                         (dev->data->dev_conf.link_duplex ==
 591                                         ETH_LINK_FULL_DUPLEX))
 592                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 593                 else
 594                         goto error_invalid_config;
 595                 break;
 596         case ETH_LINK_SPEED_10000:
 597         default:
 598                 goto error_invalid_config;
 599         }
 600         e1000_setup_link(hw);
 601
 602         /* check if lsc interrupt feature is enabled */
 603         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 604                 ret = eth_em_interrupt_setup(dev);
 605                 if (ret) {
 606                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 607                         em_dev_clear_queues(dev);
 608                         return ret;
 609                 }
 610         }
 611
 612         adapter->stopped = 0;
 613
 614         PMD_INIT_LOG(DEBUG, "<<");
 615
 616         return (0);
 617
 618 error_invalid_config:
 619         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 620                      dev->data->dev_conf.link_speed,
 621                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 622         em_dev_clear_queues(dev);
 623         return (-EINVAL);
 624 }
 625
 626 /*********************************************************************
 627  *
 628  *  This routine disables all traffic on the adapter by issuing a
 629  *  global reset on the MAC.
 630  *
 631  **********************************************************************/
 632 static void
 633 eth_em_stop(struct rte_eth_dev *dev)
 634 {
 635         struct rte_eth_link link;
 636         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 637
 638         em_intr_disable(hw);
 639         e1000_reset_hw(hw);
 640         if (hw->mac.type >= e1000_82544)
 641                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 642
 643         /* Power down the phy. Needed to make the link go down */
 644         e1000_power_down_phy(hw);
 645
 646         em_dev_clear_queues(dev);
 647
 648         /* clear the recorded link status */
 649         memset(&link, 0, sizeof(link));
 650         rte_em_dev_atomic_write_link_status(dev, &link);
 651 }
 652
 653 static void
 654 eth_em_close(struct rte_eth_dev *dev)
 655 {
 656         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 657         struct e1000_adapter *adapter =
 658                 E1000_DEV_PRIVATE(dev->data->dev_private);
 659
 660         eth_em_stop(dev);
 661         adapter->stopped = 1;
 662         em_dev_free_queues(dev);
 663         e1000_phy_hw_reset(hw);
 664         em_release_manageability(hw);
 665         em_hw_control_release(hw);
 666 }
 667
 668 static int
 669 em_get_rx_buffer_size(struct e1000_hw *hw)
 670 {
 671         uint32_t rx_buf_size;
 672
 673         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 674         return rx_buf_size;
 675 }
 676
 677 /*********************************************************************
 678  *
 679  *  Initialize the hardware
 680  *
 681  **********************************************************************/
 682 static int
 683 em_hardware_init(struct e1000_hw *hw)
 684 {
 685         uint32_t rx_buf_size;
 686         int diag;
 687
 688         /* Issue a global reset */
 689         e1000_reset_hw(hw);
 690
 691         /* Let the firmware know the OS is in control */
 692         em_hw_control_acquire(hw);
 693
 694         /*
 695          * These parameters control the automatic generation (Tx) and
 696          * response (Rx) to Ethernet PAUSE frames.
 697          * - High water mark should allow for at least two standard size (1518)
 698          *   frames to be received after sending an XOFF.
 699          * - Low water mark works best when it is very near the high water mark.
 700          *   This allows the receiver to restart by sending XON when it has
 701          *   drained a bit. Here we use an arbitrary value of 1500 which will
 702          *   restart after one full frame is pulled from the buffer. There
 703          *   could be several smaller frames in the buffer and if so they will
 704          *   not trigger the XON until their total number reduces the buffer
 705          *   by 1500.
 706          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 707          */
 708         rx_buf_size = em_get_rx_buffer_size(hw);
 709
 710         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 711         hw->fc.low_water = hw->fc.high_water - 1500;
 712
 713         if (hw->mac.type == e1000_80003es2lan)
 714                 hw->fc.pause_time = UINT16_MAX;
 715         else
 716                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 717
 718         hw->fc.send_xon = 1;
 719
 720         /* Set Flow control, use the tunable location if sane */
 721         if (em_fc_setting <= e1000_fc_full)
 722                 hw->fc.requested_mode = em_fc_setting;
 723         else
 724                 hw->fc.requested_mode = e1000_fc_none;
 725
 726         /* Workaround: no TX flow ctrl for PCH */
 727         if (hw->mac.type == e1000_pchlan)
 728                 hw->fc.requested_mode = e1000_fc_rx_pause;
 729
 730         /* Override - settings for PCH2LAN, ya its magic :) */
 731         if (hw->mac.type == e1000_pch2lan) {
 732                 hw->fc.high_water = 0x5C20;
 733                 hw->fc.low_water = 0x5048;
 734                 hw->fc.pause_time = 0x0650;
 735                 hw->fc.refresh_time = 0x0400;
 736         }
 737
 738         diag = e1000_init_hw(hw);
 739         if (diag < 0)
 740                 return (diag);
 741         e1000_check_for_link(hw);
 742         return (0);
 743 }
 744
 745 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 746 static void
 747 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 748 {
 749         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 750         struct e1000_hw_stats *stats =
 751                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 752         int pause_frames;
 753
 754         if(hw->phy.media_type == e1000_media_type_copper ||
 755                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 756                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 757                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 758         }
 759
 760         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 761         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 762         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 763         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 764
 765         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 766         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 767         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 768         stats->dc += E1000_READ_REG(hw, E1000_DC);
 769         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 770         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 771         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 772
 773         /*
 774          * For watchdog management we need to know if we have been
 775          * paused during the last interval, so capture that here.
 776          */
 777         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 778         stats->xoffrxc += pause_frames;
 779         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 780         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 781         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 782         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 783         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 784         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 785         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 786         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 787         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 788         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 789         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 790         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 791
 792         /*
 793          * For the 64-bit byte counters the low dword must be read first.
 794          * Both registers clear on the read of the high dword.
 795          */
 796
 797         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 798         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 799         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 800         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 801
 802         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 803         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 804         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 805         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 806         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 807
 808         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 809         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 810
 811         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 812         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 813         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 814         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 815         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 816         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 817         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 818         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 819         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 820         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 821
 822         /* Interrupt Counts */
 823
 824         if (hw->mac.type >= e1000_82571) {
 825                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 826                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 827                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 828                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 829                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 830                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 831                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 832                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 833                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 834         }
 835
 836         if (hw->mac.type >= e1000_82543) {
 837                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 838                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 839                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 840                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 841                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 842                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 843         }
 844
 845         if (rte_stats == NULL)
 846                 return;
 847
 848         /* Rx Errors */
 849         rte_stats->ibadcrc = stats->crcerrs;
 850         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
 851         rte_stats->imissed = stats->mpc;
 852         rte_stats->ierrors = rte_stats->ibadcrc +
 853                              rte_stats->ibadlen +
 854                              rte_stats->imissed +
 855                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 856
 857         /* Tx Errors */
 858         rte_stats->oerrors = stats->ecol + stats->latecol;
 859
 860         rte_stats->ipackets = stats->gprc;
 861         rte_stats->opackets = stats->gptc;
 862         rte_stats->ibytes   = stats->gorc;
 863         rte_stats->obytes   = stats->gotc;
 864
 865         /* XON/XOFF pause frames stats registers */
 866         rte_stats->tx_pause_xon  = stats->xontxc;
 867         rte_stats->rx_pause_xon  = stats->xonrxc;
 868         rte_stats->tx_pause_xoff = stats->xofftxc;
 869         rte_stats->rx_pause_xoff = stats->xoffrxc;
 870 }
 871
 872 static void
 873 eth_em_stats_reset(struct rte_eth_dev *dev)
 874 {
 875         struct e1000_hw_stats *hw_stats =
 876                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 877
 878         /* HW registers are cleared on read */
 879         eth_em_stats_get(dev, NULL);
 880
 881         /* Reset software totals */
 882         memset(hw_stats, 0, sizeof(*hw_stats));
 883 }
 884
 885 static uint32_t
 886 em_get_max_pktlen(const struct e1000_hw *hw)
 887 {
 888         switch (hw->mac.type) {
 889         case e1000_82571:
 890         case e1000_82572:
 891         case e1000_ich9lan:
 892         case e1000_ich10lan:
 893         case e1000_pch2lan:
 894         case e1000_82574:
 895         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 896                 return (0x2412);
 897         case e1000_pchlan:
 898                 return (0x1000);
 899         /* Adapters that do not support jumbo frames */
 900         case e1000_82583:
 901         case e1000_ich8lan:
 902                 return (ETHER_MAX_LEN);
 903         default:
 904                 return (MAX_JUMBO_FRAME_SIZE);
 905         }
 906 }
 907
 908 static void
 909 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 910 {
 911         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 912
 913         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 914         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 915         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 916
 917         /*
 918          * Starting with 631xESB hw supports 2 TX/RX queues per port.
 919          * Unfortunatelly, all these nics have just one TX context.
 920          * So we have few choises for TX:
 921          * - Use just one TX queue.
 922          * - Allow cksum offload only for one TX queue.
 923          * - Don't allow TX cksum offload at all.
 924          * For now, option #1 was chosen.
 925          * To use second RX queue we have to use extended RX descriptor
 926          * (Multiple Receive Queues are mutually exclusive with UDP
 927          * fragmentation and are not supported when a legacy receive
 928          * descriptor format is used).
 929          * Which means separate RX routinies - as legacy nics (82540, 82545)
 930          * don't support extended RXD.
 931          * To avoid it we support just one RX queue for now (no RSS).
 932          */
 933
 934         dev_info->max_rx_queues = 1;
 935         dev_info->max_tx_queues = 1;
 936 }
 937
 938 /* return 0 means link status changed, -1 means not changed */
 939 static int
 940 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 941 {
 942         struct e1000_hw *hw =
 943                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 944         struct rte_eth_link link, old;
 945         int link_check, count;
 946
 947         link_check = 0;
 948         hw->mac.get_link_status = 1;
 949
 950         /* possible wait-to-complete in up to 9 seconds */
 951         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 952                 /* Read the real link status */
 953                 switch (hw->phy.media_type) {
 954                 case e1000_media_type_copper:
 955                         /* Do the work to read phy */
 956                         e1000_check_for_link(hw);
 957                         link_check = !hw->mac.get_link_status;
 958                         break;
 959
 960                 case e1000_media_type_fiber:
 961                         e1000_check_for_link(hw);
 962                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 963                                         E1000_STATUS_LU);
 964                         break;
 965
 966                 case e1000_media_type_internal_serdes:
 967                         e1000_check_for_link(hw);
 968                         link_check = hw->mac.serdes_has_link;
 969                         break;
 970
 971                 default:
 972                         break;
 973                 }
 974                 if (link_check || wait_to_complete == 0)
 975                         break;
 976                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
 977         }
 978         memset(&link, 0, sizeof(link));
 979         rte_em_dev_atomic_read_link_status(dev, &link);
 980         old = link;
 981
 982         /* Now we check if a transition has happened */
 983         if (link_check && (link.link_status == 0)) {
 984                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 985                         &link.link_duplex);
 986                 link.link_status = 1;
 987         } else if (!link_check && (link.link_status == 1)) {
 988                 link.link_speed = 0;
 989                 link.link_duplex = 0;
 990                 link.link_status = 0;
 991         }
 992         rte_em_dev_atomic_write_link_status(dev, &link);
 993
 994         /* not changed */
 995         if (old.link_status == link.link_status)
 996                 return -1;
 997
 998         /* changed */
 999         return 0;
1000 }
1001
1002 /*
1003  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1004  * For ASF and Pass Through versions of f/w this means
1005  * that the driver is loaded. For AMT version type f/w
1006  * this means that the network i/f is open.
1007  */
1008 static void
1009 em_hw_control_acquire(struct e1000_hw *hw)
1010 {
1011         uint32_t ctrl_ext, swsm;
1012
1013         /* Let firmware know the driver has taken over */
1014         if (hw->mac.type == e1000_82573) {
1015                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1016                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1017
1018         } else {
1019                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1020                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1021                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1022         }
1023 }
1024
1025 /*
1026  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1027  * For ASF and Pass Through versions of f/w this means that the
1028  * driver is no longer loaded. For AMT versions of the
1029  * f/w this means that the network i/f is closed.
1030  */
1031 static void
1032 em_hw_control_release(struct e1000_hw *hw)
1033 {
1034         uint32_t ctrl_ext, swsm;
1035
1036         /* Let firmware taken over control of h/w */
1037         if (hw->mac.type == e1000_82573) {
1038                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1039                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1040         } else {
1041                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1042                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1043                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1044         }
1045 }
1046
1047 /*
1048  * Bit of a misnomer, what this really means is
1049  * to enable OS management of the system... aka
1050  * to disable special hardware management features.
1051  */
1052 static void
1053 em_init_manageability(struct e1000_hw *hw)
1054 {
1055         if (e1000_enable_mng_pass_thru(hw)) {
1056                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1057                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1058
1059                 /* disable hardware interception of ARP */
1060                 manc &= ~(E1000_MANC_ARP_EN);
1061
1062                 /* enable receiving management packets to the host */
1063                 manc |= E1000_MANC_EN_MNG2HOST;
1064                 manc2h |= 1 << 5;  /* Mng Port 623 */
1065                 manc2h |= 1 << 6;  /* Mng Port 664 */
1066                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1067                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1068         }
1069 }
1070
1071 /*
1072  * Give control back to hardware management
1073  * controller if there is one.
1074  */
1075 static void
1076 em_release_manageability(struct e1000_hw *hw)
1077 {
1078         uint32_t manc;
1079
1080         if (e1000_enable_mng_pass_thru(hw)) {
1081                 manc = E1000_READ_REG(hw, E1000_MANC);
1082
1083                 /* re-enable hardware interception of ARP */
1084                 manc |= E1000_MANC_ARP_EN;
1085                 manc &= ~E1000_MANC_EN_MNG2HOST;
1086
1087                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1088         }
1089 }
1090
1091 static void
1092 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1093 {
1094         struct e1000_hw *hw =
1095                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1096         uint32_t rctl;
1097
1098         rctl = E1000_READ_REG(hw, E1000_RCTL);
1099         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1100         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1101 }
1102
1103 static void
1104 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1105 {
1106         struct e1000_hw *hw =
1107                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1108         uint32_t rctl;
1109
1110         rctl = E1000_READ_REG(hw, E1000_RCTL);
1111         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1112         if (dev->data->all_multicast == 1)
1113                 rctl |= E1000_RCTL_MPE;
1114         else
1115                 rctl &= (~E1000_RCTL_MPE);
1116         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1117 }
1118
1119 static void
1120 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1121 {
1122         struct e1000_hw *hw =
1123                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1124         uint32_t rctl;
1125
1126         rctl = E1000_READ_REG(hw, E1000_RCTL);
1127         rctl |= E1000_RCTL_MPE;
1128         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1129 }
1130
1131 static void
1132 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1133 {
1134         struct e1000_hw *hw =
1135                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1136         uint32_t rctl;
1137
1138         if (dev->data->promiscuous == 1)
1139                 return; /* must remain in all_multicast mode */
1140         rctl = E1000_READ_REG(hw, E1000_RCTL);
1141         rctl &= (~E1000_RCTL_MPE);
1142         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1143 }
1144
1145 static int
1146 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1147 {
1148         struct e1000_hw *hw =
1149                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1150         struct e1000_vfta * shadow_vfta =
1151                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1152         uint32_t vfta;
1153         uint32_t vid_idx;
1154         uint32_t vid_bit;
1155
1156         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1157                               E1000_VFTA_ENTRY_MASK);
1158         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1159         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1160         if (on)
1161                 vfta |= vid_bit;
1162         else
1163                 vfta &= ~vid_bit;
1164         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1165
1166         /* update local VFTA copy */
1167         shadow_vfta->vfta[vid_idx] = vfta;
1168
1169         return 0;
1170 }
1171
1172 static void
1173 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1174 {
1175         struct e1000_hw *hw =
1176                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1177         uint32_t reg;
1178
1179         /* Filter Table Disable */
1180         reg = E1000_READ_REG(hw, E1000_RCTL);
1181         reg &= ~E1000_RCTL_CFIEN;
1182         reg &= ~E1000_RCTL_VFE;
1183         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1184 }
1185
1186 static void
1187 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1188 {
1189         struct e1000_hw *hw =
1190                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191         struct e1000_vfta * shadow_vfta =
1192                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1193         uint32_t reg;
1194         int i;
1195
1196         /* Filter Table Enable, CFI not used for packet acceptance */
1197         reg = E1000_READ_REG(hw, E1000_RCTL);
1198         reg &= ~E1000_RCTL_CFIEN;
1199         reg |= E1000_RCTL_VFE;
1200         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1201
1202         /* restore vfta from local copy */
1203         for (i = 0; i < IGB_VFTA_SIZE; i++)
1204                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1205 }
1206
1207 static void
1208 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1209 {
1210         struct e1000_hw *hw =
1211                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212         uint32_t reg;
1213
1214         /* VLAN Mode Disable */
1215         reg = E1000_READ_REG(hw, E1000_CTRL);
1216         reg &= ~E1000_CTRL_VME;
1217         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1218
1219 }
1220
1221 static void
1222 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1223 {
1224         struct e1000_hw *hw =
1225                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1226         uint32_t reg;
1227
1228         /* VLAN Mode Enable */
1229         reg = E1000_READ_REG(hw, E1000_CTRL);
1230         reg |= E1000_CTRL_VME;
1231         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1232 }
1233
1234 static void
1235 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1236 {
1237         if(mask & ETH_VLAN_STRIP_MASK){
1238                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1239                         em_vlan_hw_strip_enable(dev);
1240                 else
1241                         em_vlan_hw_strip_disable(dev);
1242         }
1243
1244         if(mask & ETH_VLAN_FILTER_MASK){
1245                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1246                         em_vlan_hw_filter_enable(dev);
1247                 else
1248                         em_vlan_hw_filter_disable(dev);
1249         }
1250 }
1251
1252 static void
1253 em_intr_disable(struct e1000_hw *hw)
1254 {
1255         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1256 }
1257
1258 /**
1259  * It enables the interrupt mask and then enable the interrupt.
1260  *
1261  * @param dev
1262  *  Pointer to struct rte_eth_dev.
1263  *
1264  * @return
1265  *  - On success, zero.
1266  *  - On failure, a negative value.
1267  */
1268 static int
1269 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1270 {
1271         struct e1000_hw *hw =
1272                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273
1274         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1275         rte_intr_enable(&(dev->pci_dev->intr_handle));
1276         return (0);
1277 }
1278
1279 /*
1280  * It reads ICR and gets interrupt causes, check it and set a bit flag
1281  * to update link status.
1282  *
1283  * @param dev
1284  *  Pointer to struct rte_eth_dev.
1285  *
1286  * @return
1287  *  - On success, zero.
1288  *  - On failure, a negative value.
1289  */
1290 static int
1291 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1292 {
1293         uint32_t icr;
1294         struct e1000_hw *hw =
1295                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1296         struct e1000_interrupt *intr =
1297                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1298
1299         /* read-on-clear nic registers here */
1300         icr = E1000_READ_REG(hw, E1000_ICR);
1301         if (icr & E1000_ICR_LSC) {
1302                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1303         }
1304
1305         return 0;
1306 }
1307
1308 /*
1309  * It executes link_update after knowing an interrupt is prsent.
1310  *
1311  * @param dev
1312  *  Pointer to struct rte_eth_dev.
1313  *
1314  * @return
1315  *  - On success, zero.
1316  *  - On failure, a negative value.
1317  */
1318 static int
1319 eth_em_interrupt_action(struct rte_eth_dev *dev)
1320 {
1321         struct e1000_hw *hw =
1322                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1323         struct e1000_interrupt *intr =
1324                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1325         uint32_t tctl, rctl;
1326         struct rte_eth_link link;
1327         int ret;
1328
1329         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1330                 return -1;
1331
1332         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1333         rte_intr_enable(&(dev->pci_dev->intr_handle));
1334
1335         /* set get_link_status to check register later */
1336         hw->mac.get_link_status = 1;
1337         ret = eth_em_link_update(dev, 0);
1338
1339         /* check if link has changed */
1340         if (ret < 0)
1341                 return 0;
1342
1343         memset(&link, 0, sizeof(link));
1344         rte_em_dev_atomic_read_link_status(dev, &link);
1345         if (link.link_status) {
1346                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1347                              dev->data->port_id, (unsigned)link.link_speed,
1348                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1349                              "full-duplex" : "half-duplex");
1350         } else {
1351                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1352         }
1353         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1354                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1355                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1356         tctl = E1000_READ_REG(hw, E1000_TCTL);
1357         rctl = E1000_READ_REG(hw, E1000_RCTL);
1358         if (link.link_status) {
1359                 /* enable Tx/Rx */
1360                 tctl |= E1000_TCTL_EN;
1361                 rctl |= E1000_RCTL_EN;
1362         } else {
1363                 /* disable Tx/Rx */
1364                 tctl &= ~E1000_TCTL_EN;
1365                 rctl &= ~E1000_RCTL_EN;
1366         }
1367         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1368         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1369         E1000_WRITE_FLUSH(hw);
1370
1371         return 0;
1372 }
1373
1374 /**
1375  * Interrupt handler which shall be registered at first.
1376  *
1377  * @param handle
1378  *  Pointer to interrupt handle.
1379  * @param param
1380  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1381  *
1382  * @return
1383  *  void
1384  */
1385 static void
1386 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1387                                                         void *param)
1388 {
1389         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1390
1391         eth_em_interrupt_get_status(dev);
1392         eth_em_interrupt_action(dev);
1393         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1394 }
1395
1396 static int
1397 eth_em_led_on(struct rte_eth_dev *dev)
1398 {
1399         struct e1000_hw *hw;
1400
1401         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1402         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1403 }
1404
1405 static int
1406 eth_em_led_off(struct rte_eth_dev *dev)
1407 {
1408         struct e1000_hw *hw;
1409
1410         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1411         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1412 }
1413
1414 static int
1415 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1416 {
1417         struct e1000_hw *hw;
1418         uint32_t ctrl;
1419         int tx_pause;
1420         int rx_pause;
1421
1422         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1423         fc_conf->pause_time = hw->fc.pause_time;
1424         fc_conf->high_water = hw->fc.high_water;
1425         fc_conf->low_water = hw->fc.low_water;
1426         fc_conf->send_xon = hw->fc.send_xon;
1427         fc_conf->autoneg = hw->mac.autoneg;
1428
1429         /*
1430          * Return rx_pause and tx_pause status according to actual setting of
1431          * the TFCE and RFCE bits in the CTRL register.
1432          */
1433         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1434         if (ctrl & E1000_CTRL_TFCE)
1435                 tx_pause = 1;
1436         else
1437                 tx_pause = 0;
1438
1439         if (ctrl & E1000_CTRL_RFCE)
1440                 rx_pause = 1;
1441         else
1442                 rx_pause = 0;
1443
1444         if (rx_pause && tx_pause)
1445                 fc_conf->mode = RTE_FC_FULL;
1446         else if (rx_pause)
1447                 fc_conf->mode = RTE_FC_RX_PAUSE;
1448         else if (tx_pause)
1449                 fc_conf->mode = RTE_FC_TX_PAUSE;
1450         else
1451                 fc_conf->mode = RTE_FC_NONE;
1452
1453         return 0;
1454 }
1455
1456 static int
1457 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1458 {
1459         struct e1000_hw *hw;
1460         int err;
1461         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1462                 e1000_fc_none,
1463                 e1000_fc_rx_pause,
1464                 e1000_fc_tx_pause,
1465                 e1000_fc_full
1466         };
1467         uint32_t rx_buf_size;
1468         uint32_t max_high_water;
1469         uint32_t rctl;
1470
1471         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1472         if (fc_conf->autoneg != hw->mac.autoneg)
1473                 return -ENOTSUP;
1474         rx_buf_size = em_get_rx_buffer_size(hw);
1475         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1476
1477         /* At least reserve one Ethernet frame for watermark */
1478         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1479         if ((fc_conf->high_water > max_high_water) ||
1480             (fc_conf->high_water < fc_conf->low_water)) {
1481                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1482                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1483                 return (-EINVAL);
1484         }
1485
1486         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1487         hw->fc.pause_time     = fc_conf->pause_time;
1488         hw->fc.high_water     = fc_conf->high_water;
1489         hw->fc.low_water      = fc_conf->low_water;
1490         hw->fc.send_xon       = fc_conf->send_xon;
1491
1492         err = e1000_setup_link_generic(hw);
1493         if (err == E1000_SUCCESS) {
1494
1495                 /* check if we want to forward MAC frames - driver doesn't have native
1496                  * capability to do that, so we'll write the registers ourselves */
1497
1498                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1499
1500                 /* set or clear MFLCN.PMCF bit depending on configuration */
1501                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1502                         rctl |= E1000_RCTL_PMCF;
1503                 else
1504                         rctl &= ~E1000_RCTL_PMCF;
1505
1506                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1507                 E1000_WRITE_FLUSH(hw);
1508
1509                 return 0;
1510         }
1511
1512         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1513         return (-EIO);
1514 }
1515
1516 static void
1517 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1518                 uint32_t index, __rte_unused uint32_t pool)
1519 {
1520         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521
1522         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1523 }
1524
1525 static void
1526 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1527 {
1528         uint8_t addr[ETHER_ADDR_LEN];
1529         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1530
1531         memset(addr, 0, sizeof(addr));
1532
1533         e1000_rar_set(hw, addr, index);
1534 }
1535
1536 static int
1537 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1538 {
1539         struct rte_eth_dev_info dev_info;
1540         struct e1000_hw *hw;
1541         uint32_t frame_size;
1542         uint32_t rctl;
1543
1544         eth_em_infos_get(dev, &dev_info);
1545         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1546
1547         /* check that mtu is within the allowed range */
1548         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1549                 return -EINVAL;
1550
1551         /* refuse mtu that requires the support of scattered packets when this
1552          * feature has not been enabled before. */
1553         if (!dev->data->scattered_rx &&
1554             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1555                 return -EINVAL;
1556
1557         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1558         rctl = E1000_READ_REG(hw, E1000_RCTL);
1559
1560         /* switch to jumbo mode if needed */
1561         if (frame_size > ETHER_MAX_LEN) {
1562                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1563                 rctl |= E1000_RCTL_LPE;
1564         } else {
1565                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1566                 rctl &= ~E1000_RCTL_LPE;
1567         }
1568         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1569
1570         /* update max frame size */
1571         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1572         return 0;
1573 }
1574
1575 static int
1576 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1577                         struct ether_addr *mc_addr_set,
1578                         uint32_t nb_mc_addr)
1579 {
1580         struct e1000_hw *hw;
1581
1582         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1584         return 0;
1585 }
1586
1587 struct rte_driver em_pmd_drv = {
1588         .type = PMD_PDEV,
1589         .init = rte_em_pmd_init,
1590 };
1591
1592 PMD_REGISTER_DRIVER(em_pmd_drv);