1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
14 #include <rte_debug.h>
16 #include <rte_bus_pci.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_ethdev_pci.h>
20 #include <rte_memory.h>
22 #include <rte_malloc.h>
25 #include "e1000_logs.h"
26 #include "base/e1000_api.h"
27 #include "e1000_ethdev.h"
29 #define EM_EIAC 0x000DC
31 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
34 static int eth_em_configure(struct rte_eth_dev *dev);
35 static int eth_em_start(struct rte_eth_dev *dev);
36 static void eth_em_stop(struct rte_eth_dev *dev);
37 static void eth_em_close(struct rte_eth_dev *dev);
38 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
39 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
40 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
41 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
42 static int eth_em_link_update(struct rte_eth_dev *dev,
43 int wait_to_complete);
44 static int eth_em_stats_get(struct rte_eth_dev *dev,
45 struct rte_eth_stats *rte_stats);
46 static void eth_em_stats_reset(struct rte_eth_dev *dev);
47 static void eth_em_infos_get(struct rte_eth_dev *dev,
48 struct rte_eth_dev_info *dev_info);
49 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
50 struct rte_eth_fc_conf *fc_conf);
51 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
52 struct rte_eth_fc_conf *fc_conf);
53 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
54 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
55 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
56 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
57 struct rte_intr_handle *handle);
58 static void eth_em_interrupt_handler(void *param);
60 static int em_hw_init(struct e1000_hw *hw);
61 static int em_hardware_init(struct e1000_hw *hw);
62 static void em_hw_control_acquire(struct e1000_hw *hw);
63 static void em_hw_control_release(struct e1000_hw *hw);
64 static void em_init_manageability(struct e1000_hw *hw);
65 static void em_release_manageability(struct e1000_hw *hw);
67 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
70 uint16_t vlan_id, int on);
71 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
72 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
73 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
74 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
75 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
78 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
79 uint16_t vlan_id, int on);
82 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
83 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
84 static void em_lsc_intr_disable(struct e1000_hw *hw);
85 static void em_rxq_intr_enable(struct e1000_hw *hw);
86 static void em_rxq_intr_disable(struct e1000_hw *hw);
88 static int eth_em_led_on(struct rte_eth_dev *dev);
89 static int eth_em_led_off(struct rte_eth_dev *dev);
91 static int em_get_rx_buffer_size(struct e1000_hw *hw);
92 static int eth_em_rar_set(struct rte_eth_dev *dev,
93 struct rte_ether_addr *mac_addr,
94 uint32_t index, uint32_t pool);
95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
96 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
97 struct rte_ether_addr *addr);
99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
100 struct rte_ether_addr *mc_addr_set,
101 uint32_t nb_mc_addr);
103 #define EM_FC_PAUSE_TIME 0x0680
104 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
110 * The set of PCI devices this driver supports
112 static const struct rte_pci_id pci_id_em_map[] = {
113 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
114 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
115 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
116 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
117 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
118 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
119 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
120 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
121 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
122 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
123 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
124 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
125 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
126 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
127 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
128 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
129 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
130 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
131 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
132 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
133 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
134 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
135 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
136 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
137 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
138 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
139 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
140 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
158 { .vendor_id = 0, /* sentinel */ },
161 static const struct eth_dev_ops eth_em_ops = {
162 .dev_configure = eth_em_configure,
163 .dev_start = eth_em_start,
164 .dev_stop = eth_em_stop,
165 .dev_close = eth_em_close,
166 .promiscuous_enable = eth_em_promiscuous_enable,
167 .promiscuous_disable = eth_em_promiscuous_disable,
168 .allmulticast_enable = eth_em_allmulticast_enable,
169 .allmulticast_disable = eth_em_allmulticast_disable,
170 .link_update = eth_em_link_update,
171 .stats_get = eth_em_stats_get,
172 .stats_reset = eth_em_stats_reset,
173 .dev_infos_get = eth_em_infos_get,
174 .mtu_set = eth_em_mtu_set,
175 .vlan_filter_set = eth_em_vlan_filter_set,
176 .vlan_offload_set = eth_em_vlan_offload_set,
177 .rx_queue_setup = eth_em_rx_queue_setup,
178 .rx_queue_release = eth_em_rx_queue_release,
179 .rx_queue_count = eth_em_rx_queue_count,
180 .rx_descriptor_done = eth_em_rx_descriptor_done,
181 .rx_descriptor_status = eth_em_rx_descriptor_status,
182 .tx_descriptor_status = eth_em_tx_descriptor_status,
183 .tx_queue_setup = eth_em_tx_queue_setup,
184 .tx_queue_release = eth_em_tx_queue_release,
185 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
186 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
187 .dev_led_on = eth_em_led_on,
188 .dev_led_off = eth_em_led_off,
189 .flow_ctrl_get = eth_em_flow_ctrl_get,
190 .flow_ctrl_set = eth_em_flow_ctrl_set,
191 .mac_addr_set = eth_em_default_mac_addr_set,
192 .mac_addr_add = eth_em_rar_set,
193 .mac_addr_remove = eth_em_rar_clear,
194 .set_mc_addr_list = eth_em_set_mc_addr_list,
195 .rxq_info_get = em_rxq_info_get,
196 .txq_info_get = em_txq_info_get,
201 * eth_em_dev_is_ich8 - Check for ICH8 device
202 * @hw: pointer to the HW structure
204 * return TRUE for ICH8, otherwise FALSE
207 eth_em_dev_is_ich8(struct e1000_hw *hw)
209 DEBUGFUNC("eth_em_dev_is_ich8");
211 switch (hw->device_id) {
212 case E1000_DEV_ID_PCH2_LV_LM:
213 case E1000_DEV_ID_PCH_LPT_I217_LM:
214 case E1000_DEV_ID_PCH_LPT_I217_V:
215 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
216 case E1000_DEV_ID_PCH_LPTLP_I218_V:
217 case E1000_DEV_ID_PCH_I218_V2:
218 case E1000_DEV_ID_PCH_I218_LM2:
219 case E1000_DEV_ID_PCH_I218_V3:
220 case E1000_DEV_ID_PCH_I218_LM3:
221 case E1000_DEV_ID_PCH_SPT_I219_LM:
222 case E1000_DEV_ID_PCH_SPT_I219_V:
223 case E1000_DEV_ID_PCH_SPT_I219_LM2:
224 case E1000_DEV_ID_PCH_SPT_I219_V2:
225 case E1000_DEV_ID_PCH_LBG_I219_LM3:
226 case E1000_DEV_ID_PCH_SPT_I219_LM4:
227 case E1000_DEV_ID_PCH_SPT_I219_V4:
228 case E1000_DEV_ID_PCH_SPT_I219_LM5:
229 case E1000_DEV_ID_PCH_SPT_I219_V5:
230 case E1000_DEV_ID_PCH_CNP_I219_LM6:
231 case E1000_DEV_ID_PCH_CNP_I219_V6:
232 case E1000_DEV_ID_PCH_CNP_I219_LM7:
233 case E1000_DEV_ID_PCH_CNP_I219_V7:
241 eth_em_dev_init(struct rte_eth_dev *eth_dev)
243 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
244 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
245 struct e1000_adapter *adapter =
246 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
247 struct e1000_hw *hw =
248 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
249 struct e1000_vfta * shadow_vfta =
250 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
252 eth_dev->dev_ops = ð_em_ops;
253 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
254 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
255 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
257 /* for secondary processes, we don't initialise any further as primary
258 * has already done this work. Only check we don't need a different
260 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
261 if (eth_dev->data->scattered_rx)
262 eth_dev->rx_pkt_burst =
263 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
267 rte_eth_copy_pci_info(eth_dev, pci_dev);
269 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
270 hw->device_id = pci_dev->id.device_id;
271 adapter->stopped = 0;
273 /* For ICH8 support we'll need to map the flash memory BAR */
274 if (eth_em_dev_is_ich8(hw))
275 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
277 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
278 em_hw_init(hw) != 0) {
279 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
281 eth_dev->data->port_id, pci_dev->id.vendor_id,
282 pci_dev->id.device_id);
286 /* Allocate memory for storing MAC addresses */
287 eth_dev->data->mac_addrs = rte_zmalloc("e1000", RTE_ETHER_ADDR_LEN *
288 hw->mac.rar_entry_count, 0);
289 if (eth_dev->data->mac_addrs == NULL) {
290 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
291 "store MAC addresses",
292 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
296 /* Copy the permanent MAC address */
297 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
298 eth_dev->data->mac_addrs);
300 /* initialize the vfta */
301 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
303 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
304 eth_dev->data->port_id, pci_dev->id.vendor_id,
305 pci_dev->id.device_id);
307 rte_intr_callback_register(intr_handle,
308 eth_em_interrupt_handler, eth_dev);
314 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
316 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
317 struct e1000_adapter *adapter =
318 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
319 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
321 PMD_INIT_FUNC_TRACE();
323 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
326 if (adapter->stopped == 0)
327 eth_em_close(eth_dev);
329 eth_dev->dev_ops = NULL;
330 eth_dev->rx_pkt_burst = NULL;
331 eth_dev->tx_pkt_burst = NULL;
333 /* disable uio intr before callback unregister */
334 rte_intr_disable(intr_handle);
335 rte_intr_callback_unregister(intr_handle,
336 eth_em_interrupt_handler, eth_dev);
341 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
342 struct rte_pci_device *pci_dev)
344 return rte_eth_dev_pci_generic_probe(pci_dev,
345 sizeof(struct e1000_adapter), eth_em_dev_init);
348 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
350 return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
353 static struct rte_pci_driver rte_em_pmd = {
354 .id_table = pci_id_em_map,
355 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
356 RTE_PCI_DRV_IOVA_AS_VA,
357 .probe = eth_em_pci_probe,
358 .remove = eth_em_pci_remove,
362 em_hw_init(struct e1000_hw *hw)
366 diag = hw->mac.ops.init_params(hw);
368 PMD_INIT_LOG(ERR, "MAC Initialization Error");
371 diag = hw->nvm.ops.init_params(hw);
373 PMD_INIT_LOG(ERR, "NVM Initialization Error");
376 diag = hw->phy.ops.init_params(hw);
378 PMD_INIT_LOG(ERR, "PHY Initialization Error");
381 (void) e1000_get_bus_info(hw);
384 hw->phy.autoneg_wait_to_complete = 0;
385 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
387 e1000_init_script_state_82541(hw, TRUE);
388 e1000_set_tbi_compatibility_82543(hw, TRUE);
391 if (hw->phy.media_type == e1000_media_type_copper) {
392 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
393 hw->phy.disable_polarity_correction = 0;
394 hw->phy.ms_type = e1000_ms_hw_default;
398 * Start from a known state, this is important in reading the nvm
403 /* Make sure we have a good EEPROM before we read from it */
404 if (e1000_validate_nvm_checksum(hw) < 0) {
406 * Some PCI-E parts fail the first check due to
407 * the link being in sleep state, call it again,
408 * if it fails a second time its a real issue.
410 diag = e1000_validate_nvm_checksum(hw);
412 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
417 /* Read the permanent MAC address out of the EEPROM */
418 diag = e1000_read_mac_addr(hw);
420 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
424 /* Now initialize the hardware */
425 diag = em_hardware_init(hw);
427 PMD_INIT_LOG(ERR, "Hardware initialization failed");
431 hw->mac.get_link_status = 1;
433 /* Indicate SOL/IDER usage */
434 diag = e1000_check_reset_block(hw);
436 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
442 em_hw_control_release(hw);
447 eth_em_configure(struct rte_eth_dev *dev)
449 struct e1000_interrupt *intr =
450 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
452 PMD_INIT_FUNC_TRACE();
453 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
455 PMD_INIT_FUNC_TRACE();
461 em_set_pba(struct e1000_hw *hw)
466 * Packet Buffer Allocation (PBA)
467 * Writing PBA sets the receive portion of the buffer
468 * the remainder is used for the transmit buffer.
469 * Devices before the 82547 had a Packet Buffer of 64K.
470 * After the 82547 the buffer was reduced to 40K.
472 switch (hw->mac.type) {
474 case e1000_82547_rev_2:
475 /* 82547: Total Packet Buffer is 40K */
476 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
480 case e1000_80003es2lan:
481 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
483 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
484 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
488 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
505 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
508 E1000_WRITE_REG(hw, E1000_PBA, pba);
512 eth_em_rxtx_control(struct rte_eth_dev *dev,
515 struct e1000_hw *hw =
516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
519 tctl = E1000_READ_REG(hw, E1000_TCTL);
520 rctl = E1000_READ_REG(hw, E1000_RCTL);
523 tctl |= E1000_TCTL_EN;
524 rctl |= E1000_RCTL_EN;
527 tctl &= ~E1000_TCTL_EN;
528 rctl &= ~E1000_RCTL_EN;
530 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
531 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
532 E1000_WRITE_FLUSH(hw);
536 eth_em_start(struct rte_eth_dev *dev)
538 struct e1000_adapter *adapter =
539 E1000_DEV_PRIVATE(dev->data->dev_private);
540 struct e1000_hw *hw =
541 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
542 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
543 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
545 uint32_t intr_vector = 0;
550 PMD_INIT_FUNC_TRACE();
554 e1000_power_up_phy(hw);
556 /* Set default PBA value */
559 /* Put the address into the Receive Address Array */
560 e1000_rar_set(hw, hw->mac.addr, 0);
563 * With the 82571 adapter, RAR[0] may be overwritten
564 * when the other port is reset, we make a duplicate
565 * in RAR[14] for that eventuality, this assures
566 * the interface continues to function.
568 if (hw->mac.type == e1000_82571) {
569 e1000_set_laa_state_82571(hw, TRUE);
570 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
573 /* Initialize the hardware */
574 if (em_hardware_init(hw)) {
575 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
579 E1000_WRITE_REG(hw, E1000_VET, RTE_ETHER_TYPE_VLAN);
581 /* Configure for OS presence */
582 em_init_manageability(hw);
584 if (dev->data->dev_conf.intr_conf.rxq != 0) {
585 intr_vector = dev->data->nb_rx_queues;
586 if (rte_intr_efd_enable(intr_handle, intr_vector))
590 if (rte_intr_dp_is_en(intr_handle)) {
591 intr_handle->intr_vec =
592 rte_zmalloc("intr_vec",
593 dev->data->nb_rx_queues * sizeof(int), 0);
594 if (intr_handle->intr_vec == NULL) {
595 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
596 " intr_vec", dev->data->nb_rx_queues);
600 /* enable rx interrupt */
601 em_rxq_intr_enable(hw);
606 ret = eth_em_rx_init(dev);
608 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
609 em_dev_clear_queues(dev);
613 e1000_clear_hw_cntrs_base_generic(hw);
615 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
616 ETH_VLAN_EXTEND_MASK;
617 ret = eth_em_vlan_offload_set(dev, mask);
619 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
620 em_dev_clear_queues(dev);
624 /* Set Interrupt Throttling Rate to maximum allowed value. */
625 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
627 /* Setup link speed and duplex */
628 speeds = &dev->data->dev_conf.link_speeds;
629 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
630 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
634 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
637 hw->phy.autoneg_advertised = 0;
639 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
640 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
641 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
643 goto error_invalid_config;
645 if (*speeds & ETH_LINK_SPEED_10M_HD) {
646 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
649 if (*speeds & ETH_LINK_SPEED_10M) {
650 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
653 if (*speeds & ETH_LINK_SPEED_100M_HD) {
654 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
657 if (*speeds & ETH_LINK_SPEED_100M) {
658 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
661 if (*speeds & ETH_LINK_SPEED_1G) {
662 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
665 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
666 goto error_invalid_config;
668 /* Set/reset the mac.autoneg based on the link speed,
673 hw->mac.forced_speed_duplex =
674 hw->phy.autoneg_advertised;
680 e1000_setup_link(hw);
682 if (rte_intr_allow_others(intr_handle)) {
683 /* check if lsc interrupt is enabled */
684 if (dev->data->dev_conf.intr_conf.lsc != 0) {
685 ret = eth_em_interrupt_setup(dev);
687 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
688 em_dev_clear_queues(dev);
693 rte_intr_callback_unregister(intr_handle,
694 eth_em_interrupt_handler,
696 if (dev->data->dev_conf.intr_conf.lsc != 0)
697 PMD_INIT_LOG(INFO, "lsc won't enable because of"
698 " no intr multiplexn");
700 /* check if rxq interrupt is enabled */
701 if (dev->data->dev_conf.intr_conf.rxq != 0)
702 eth_em_rxq_interrupt_setup(dev);
704 rte_intr_enable(intr_handle);
706 adapter->stopped = 0;
708 eth_em_rxtx_control(dev, true);
709 eth_em_link_update(dev, 0);
711 PMD_INIT_LOG(DEBUG, "<<");
715 error_invalid_config:
716 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
717 dev->data->dev_conf.link_speeds, dev->data->port_id);
718 em_dev_clear_queues(dev);
722 /*********************************************************************
724 * This routine disables all traffic on the adapter by issuing a
725 * global reset on the MAC.
727 **********************************************************************/
729 eth_em_stop(struct rte_eth_dev *dev)
731 struct rte_eth_link link;
732 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
733 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
734 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
736 eth_em_rxtx_control(dev, false);
737 em_rxq_intr_disable(hw);
738 em_lsc_intr_disable(hw);
741 if (hw->mac.type >= e1000_82544)
742 E1000_WRITE_REG(hw, E1000_WUC, 0);
744 /* Power down the phy. Needed to make the link go down */
745 e1000_power_down_phy(hw);
747 em_dev_clear_queues(dev);
749 /* clear the recorded link status */
750 memset(&link, 0, sizeof(link));
751 rte_eth_linkstatus_set(dev, &link);
753 if (!rte_intr_allow_others(intr_handle))
754 /* resume to the default handler */
755 rte_intr_callback_register(intr_handle,
756 eth_em_interrupt_handler,
759 /* Clean datapath event and queue/vec mapping */
760 rte_intr_efd_disable(intr_handle);
761 if (intr_handle->intr_vec != NULL) {
762 rte_free(intr_handle->intr_vec);
763 intr_handle->intr_vec = NULL;
768 eth_em_close(struct rte_eth_dev *dev)
770 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
771 struct e1000_adapter *adapter =
772 E1000_DEV_PRIVATE(dev->data->dev_private);
775 adapter->stopped = 1;
776 em_dev_free_queues(dev);
777 e1000_phy_hw_reset(hw);
778 em_release_manageability(hw);
779 em_hw_control_release(hw);
783 em_get_rx_buffer_size(struct e1000_hw *hw)
785 uint32_t rx_buf_size;
787 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
791 /*********************************************************************
793 * Initialize the hardware
795 **********************************************************************/
797 em_hardware_init(struct e1000_hw *hw)
799 uint32_t rx_buf_size;
802 /* Issue a global reset */
805 /* Let the firmware know the OS is in control */
806 em_hw_control_acquire(hw);
809 * These parameters control the automatic generation (Tx) and
810 * response (Rx) to Ethernet PAUSE frames.
811 * - High water mark should allow for at least two standard size (1518)
812 * frames to be received after sending an XOFF.
813 * - Low water mark works best when it is very near the high water mark.
814 * This allows the receiver to restart by sending XON when it has
815 * drained a bit. Here we use an arbitrary value of 1500 which will
816 * restart after one full frame is pulled from the buffer. There
817 * could be several smaller frames in the buffer and if so they will
818 * not trigger the XON until their total number reduces the buffer
820 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
822 rx_buf_size = em_get_rx_buffer_size(hw);
824 hw->fc.high_water = rx_buf_size -
825 PMD_ROUNDUP(RTE_ETHER_MAX_LEN * 2, 1024);
826 hw->fc.low_water = hw->fc.high_water - 1500;
828 if (hw->mac.type == e1000_80003es2lan)
829 hw->fc.pause_time = UINT16_MAX;
831 hw->fc.pause_time = EM_FC_PAUSE_TIME;
835 /* Set Flow control, use the tunable location if sane */
836 if (em_fc_setting <= e1000_fc_full)
837 hw->fc.requested_mode = em_fc_setting;
839 hw->fc.requested_mode = e1000_fc_none;
841 /* Workaround: no TX flow ctrl for PCH */
842 if (hw->mac.type == e1000_pchlan)
843 hw->fc.requested_mode = e1000_fc_rx_pause;
845 /* Override - settings for PCH2LAN, ya its magic :) */
846 if (hw->mac.type == e1000_pch2lan) {
847 hw->fc.high_water = 0x5C20;
848 hw->fc.low_water = 0x5048;
849 hw->fc.pause_time = 0x0650;
850 hw->fc.refresh_time = 0x0400;
851 } else if (hw->mac.type == e1000_pch_lpt ||
852 hw->mac.type == e1000_pch_spt ||
853 hw->mac.type == e1000_pch_cnp) {
854 hw->fc.requested_mode = e1000_fc_full;
857 diag = e1000_init_hw(hw);
860 e1000_check_for_link(hw);
864 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
866 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
868 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
869 struct e1000_hw_stats *stats =
870 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
873 if(hw->phy.media_type == e1000_media_type_copper ||
874 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
875 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
876 stats->sec += E1000_READ_REG(hw, E1000_SEC);
879 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
880 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
881 stats->scc += E1000_READ_REG(hw, E1000_SCC);
882 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
884 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
885 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
886 stats->colc += E1000_READ_REG(hw, E1000_COLC);
887 stats->dc += E1000_READ_REG(hw, E1000_DC);
888 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
889 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
890 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
893 * For watchdog management we need to know if we have been
894 * paused during the last interval, so capture that here.
896 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
897 stats->xoffrxc += pause_frames;
898 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
899 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
900 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
901 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
902 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
903 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
904 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
905 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
906 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
907 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
908 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
909 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
912 * For the 64-bit byte counters the low dword must be read first.
913 * Both registers clear on the read of the high dword.
916 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
917 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
918 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
919 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
921 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
922 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
923 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
924 stats->roc += E1000_READ_REG(hw, E1000_ROC);
925 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
927 stats->tor += E1000_READ_REG(hw, E1000_TORH);
928 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
930 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
931 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
932 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
933 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
934 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
935 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
936 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
937 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
938 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
939 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
941 /* Interrupt Counts */
943 if (hw->mac.type >= e1000_82571) {
944 stats->iac += E1000_READ_REG(hw, E1000_IAC);
945 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
946 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
947 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
948 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
949 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
950 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
951 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
952 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
955 if (hw->mac.type >= e1000_82543) {
956 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
957 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
958 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
959 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
960 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
961 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
964 if (rte_stats == NULL)
968 rte_stats->imissed = stats->mpc;
969 rte_stats->ierrors = stats->crcerrs +
970 stats->rlec + stats->ruc + stats->roc +
971 stats->rxerrc + stats->algnerrc + stats->cexterr;
974 rte_stats->oerrors = stats->ecol + stats->latecol;
976 rte_stats->ipackets = stats->gprc;
977 rte_stats->opackets = stats->gptc;
978 rte_stats->ibytes = stats->gorc;
979 rte_stats->obytes = stats->gotc;
984 eth_em_stats_reset(struct rte_eth_dev *dev)
986 struct e1000_hw_stats *hw_stats =
987 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
989 /* HW registers are cleared on read */
990 eth_em_stats_get(dev, NULL);
992 /* Reset software totals */
993 memset(hw_stats, 0, sizeof(*hw_stats));
997 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
999 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1000 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1001 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1003 em_rxq_intr_enable(hw);
1004 rte_intr_enable(intr_handle);
1010 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1012 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1014 em_rxq_intr_disable(hw);
1020 em_get_max_pktlen(struct rte_eth_dev *dev)
1022 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024 switch (hw->mac.type) {
1028 case e1000_ich10lan:
1034 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1039 /* Adapters that do not support jumbo frames */
1041 return RTE_ETHER_MAX_LEN;
1043 return MAX_JUMBO_FRAME_SIZE;
1048 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1050 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1053 dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1054 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1057 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1058 * Unfortunatelly, all these nics have just one TX context.
1059 * So we have few choises for TX:
1060 * - Use just one TX queue.
1061 * - Allow cksum offload only for one TX queue.
1062 * - Don't allow TX cksum offload at all.
1063 * For now, option #1 was chosen.
1064 * To use second RX queue we have to use extended RX descriptor
1065 * (Multiple Receive Queues are mutually exclusive with UDP
1066 * fragmentation and are not supported when a legacy receive
1067 * descriptor format is used).
1068 * Which means separate RX routinies - as legacy nics (82540, 82545)
1069 * don't support extended RXD.
1070 * To avoid it we support just one RX queue for now (no RSS).
1073 dev_info->max_rx_queues = 1;
1074 dev_info->max_tx_queues = 1;
1076 dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1077 dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1078 dev_info->rx_queue_offload_capa;
1079 dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1080 dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1081 dev_info->tx_queue_offload_capa;
1083 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1084 .nb_max = E1000_MAX_RING_DESC,
1085 .nb_min = E1000_MIN_RING_DESC,
1086 .nb_align = EM_RXD_ALIGN,
1089 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1090 .nb_max = E1000_MAX_RING_DESC,
1091 .nb_min = E1000_MIN_RING_DESC,
1092 .nb_align = EM_TXD_ALIGN,
1093 .nb_seg_max = EM_TX_MAX_SEG,
1094 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1097 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1098 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1101 /* Preferred queue parameters */
1102 dev_info->default_rxportconf.nb_queues = 1;
1103 dev_info->default_txportconf.nb_queues = 1;
1104 dev_info->default_txportconf.ring_size = 256;
1105 dev_info->default_rxportconf.ring_size = 256;
1108 /* return 0 means link status changed, -1 means not changed */
1110 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1112 struct e1000_hw *hw =
1113 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114 struct rte_eth_link link;
1115 int link_check, count;
1118 hw->mac.get_link_status = 1;
1120 /* possible wait-to-complete in up to 9 seconds */
1121 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1122 /* Read the real link status */
1123 switch (hw->phy.media_type) {
1124 case e1000_media_type_copper:
1125 /* Do the work to read phy */
1126 e1000_check_for_link(hw);
1127 link_check = !hw->mac.get_link_status;
1130 case e1000_media_type_fiber:
1131 e1000_check_for_link(hw);
1132 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1136 case e1000_media_type_internal_serdes:
1137 e1000_check_for_link(hw);
1138 link_check = hw->mac.serdes_has_link;
1144 if (link_check || wait_to_complete == 0)
1146 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1148 memset(&link, 0, sizeof(link));
1150 /* Now we check if a transition has happened */
1151 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1152 uint16_t duplex, speed;
1153 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1154 link.link_duplex = (duplex == FULL_DUPLEX) ?
1155 ETH_LINK_FULL_DUPLEX :
1156 ETH_LINK_HALF_DUPLEX;
1157 link.link_speed = speed;
1158 link.link_status = ETH_LINK_UP;
1159 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1160 ETH_LINK_SPEED_FIXED);
1161 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1162 link.link_speed = ETH_SPEED_NUM_NONE;
1163 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1164 link.link_status = ETH_LINK_DOWN;
1165 link.link_autoneg = ETH_LINK_FIXED;
1168 return rte_eth_linkstatus_set(dev, &link);
1172 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1173 * For ASF and Pass Through versions of f/w this means
1174 * that the driver is loaded. For AMT version type f/w
1175 * this means that the network i/f is open.
1178 em_hw_control_acquire(struct e1000_hw *hw)
1180 uint32_t ctrl_ext, swsm;
1182 /* Let firmware know the driver has taken over */
1183 if (hw->mac.type == e1000_82573) {
1184 swsm = E1000_READ_REG(hw, E1000_SWSM);
1185 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1188 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1189 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1190 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1195 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1196 * For ASF and Pass Through versions of f/w this means that the
1197 * driver is no longer loaded. For AMT versions of the
1198 * f/w this means that the network i/f is closed.
1201 em_hw_control_release(struct e1000_hw *hw)
1203 uint32_t ctrl_ext, swsm;
1205 /* Let firmware taken over control of h/w */
1206 if (hw->mac.type == e1000_82573) {
1207 swsm = E1000_READ_REG(hw, E1000_SWSM);
1208 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1210 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1211 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1212 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1217 * Bit of a misnomer, what this really means is
1218 * to enable OS management of the system... aka
1219 * to disable special hardware management features.
1222 em_init_manageability(struct e1000_hw *hw)
1224 if (e1000_enable_mng_pass_thru(hw)) {
1225 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1226 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1228 /* disable hardware interception of ARP */
1229 manc &= ~(E1000_MANC_ARP_EN);
1231 /* enable receiving management packets to the host */
1232 manc |= E1000_MANC_EN_MNG2HOST;
1233 manc2h |= 1 << 5; /* Mng Port 623 */
1234 manc2h |= 1 << 6; /* Mng Port 664 */
1235 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1236 E1000_WRITE_REG(hw, E1000_MANC, manc);
1241 * Give control back to hardware management
1242 * controller if there is one.
1245 em_release_manageability(struct e1000_hw *hw)
1249 if (e1000_enable_mng_pass_thru(hw)) {
1250 manc = E1000_READ_REG(hw, E1000_MANC);
1252 /* re-enable hardware interception of ARP */
1253 manc |= E1000_MANC_ARP_EN;
1254 manc &= ~E1000_MANC_EN_MNG2HOST;
1256 E1000_WRITE_REG(hw, E1000_MANC, manc);
1261 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1263 struct e1000_hw *hw =
1264 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1267 rctl = E1000_READ_REG(hw, E1000_RCTL);
1268 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1269 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1273 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1275 struct e1000_hw *hw =
1276 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1279 rctl = E1000_READ_REG(hw, E1000_RCTL);
1280 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1281 if (dev->data->all_multicast == 1)
1282 rctl |= E1000_RCTL_MPE;
1284 rctl &= (~E1000_RCTL_MPE);
1285 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1289 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1291 struct e1000_hw *hw =
1292 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1295 rctl = E1000_READ_REG(hw, E1000_RCTL);
1296 rctl |= E1000_RCTL_MPE;
1297 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1301 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1303 struct e1000_hw *hw =
1304 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307 if (dev->data->promiscuous == 1)
1308 return; /* must remain in all_multicast mode */
1309 rctl = E1000_READ_REG(hw, E1000_RCTL);
1310 rctl &= (~E1000_RCTL_MPE);
1311 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1315 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1317 struct e1000_hw *hw =
1318 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1319 struct e1000_vfta * shadow_vfta =
1320 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1325 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1326 E1000_VFTA_ENTRY_MASK);
1327 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1328 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1333 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1335 /* update local VFTA copy */
1336 shadow_vfta->vfta[vid_idx] = vfta;
1342 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1344 struct e1000_hw *hw =
1345 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348 /* Filter Table Disable */
1349 reg = E1000_READ_REG(hw, E1000_RCTL);
1350 reg &= ~E1000_RCTL_CFIEN;
1351 reg &= ~E1000_RCTL_VFE;
1352 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1356 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1358 struct e1000_hw *hw =
1359 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1360 struct e1000_vfta * shadow_vfta =
1361 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1365 /* Filter Table Enable, CFI not used for packet acceptance */
1366 reg = E1000_READ_REG(hw, E1000_RCTL);
1367 reg &= ~E1000_RCTL_CFIEN;
1368 reg |= E1000_RCTL_VFE;
1369 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1371 /* restore vfta from local copy */
1372 for (i = 0; i < IGB_VFTA_SIZE; i++)
1373 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1377 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1379 struct e1000_hw *hw =
1380 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1383 /* VLAN Mode Disable */
1384 reg = E1000_READ_REG(hw, E1000_CTRL);
1385 reg &= ~E1000_CTRL_VME;
1386 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1391 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1393 struct e1000_hw *hw =
1394 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397 /* VLAN Mode Enable */
1398 reg = E1000_READ_REG(hw, E1000_CTRL);
1399 reg |= E1000_CTRL_VME;
1400 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1404 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1406 struct rte_eth_rxmode *rxmode;
1408 rxmode = &dev->data->dev_conf.rxmode;
1409 if(mask & ETH_VLAN_STRIP_MASK){
1410 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1411 em_vlan_hw_strip_enable(dev);
1413 em_vlan_hw_strip_disable(dev);
1416 if(mask & ETH_VLAN_FILTER_MASK){
1417 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1418 em_vlan_hw_filter_enable(dev);
1420 em_vlan_hw_filter_disable(dev);
1427 * It enables the interrupt mask and then enable the interrupt.
1430 * Pointer to struct rte_eth_dev.
1433 * - On success, zero.
1434 * - On failure, a negative value.
1437 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1440 struct e1000_hw *hw =
1441 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1443 /* clear interrupt */
1444 E1000_READ_REG(hw, E1000_ICR);
1445 regval = E1000_READ_REG(hw, E1000_IMS);
1446 E1000_WRITE_REG(hw, E1000_IMS,
1447 regval | E1000_ICR_LSC | E1000_ICR_OTHER);
1452 * It clears the interrupt causes and enables the interrupt.
1453 * It will be called once only during nic initialized.
1456 * Pointer to struct rte_eth_dev.
1459 * - On success, zero.
1460 * - On failure, a negative value.
1463 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1465 struct e1000_hw *hw =
1466 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1468 E1000_READ_REG(hw, E1000_ICR);
1469 em_rxq_intr_enable(hw);
1474 * It enable receive packet interrupt.
1476 * Pointer to struct e1000_hw
1481 em_rxq_intr_enable(struct e1000_hw *hw)
1483 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1484 E1000_WRITE_FLUSH(hw);
1488 * It disabled lsc interrupt.
1490 * Pointer to struct e1000_hw
1495 em_lsc_intr_disable(struct e1000_hw *hw)
1497 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC | E1000_IMS_OTHER);
1498 E1000_WRITE_FLUSH(hw);
1502 * It disabled receive packet interrupt.
1504 * Pointer to struct e1000_hw
1509 em_rxq_intr_disable(struct e1000_hw *hw)
1511 E1000_READ_REG(hw, E1000_ICR);
1512 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1513 E1000_WRITE_FLUSH(hw);
1517 * It reads ICR and gets interrupt causes, check it and set a bit flag
1518 * to update link status.
1521 * Pointer to struct rte_eth_dev.
1524 * - On success, zero.
1525 * - On failure, a negative value.
1528 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1531 struct e1000_hw *hw =
1532 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533 struct e1000_interrupt *intr =
1534 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1536 /* read-on-clear nic registers here */
1537 icr = E1000_READ_REG(hw, E1000_ICR);
1538 if (icr & E1000_ICR_LSC) {
1539 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1546 * It executes link_update after knowing an interrupt is prsent.
1549 * Pointer to struct rte_eth_dev.
1552 * - On success, zero.
1553 * - On failure, a negative value.
1556 eth_em_interrupt_action(struct rte_eth_dev *dev,
1557 struct rte_intr_handle *intr_handle)
1559 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1560 struct e1000_hw *hw =
1561 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1562 struct e1000_interrupt *intr =
1563 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1564 struct rte_eth_link link;
1567 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1570 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1571 rte_intr_enable(intr_handle);
1573 /* set get_link_status to check register later */
1574 hw->mac.get_link_status = 1;
1575 ret = eth_em_link_update(dev, 0);
1577 /* check if link has changed */
1581 rte_eth_linkstatus_get(dev, &link);
1583 if (link.link_status) {
1584 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1585 dev->data->port_id, link.link_speed,
1586 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1587 "full-duplex" : "half-duplex");
1589 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1591 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1592 pci_dev->addr.domain, pci_dev->addr.bus,
1593 pci_dev->addr.devid, pci_dev->addr.function);
1599 * Interrupt handler which shall be registered at first.
1602 * Pointer to interrupt handle.
1604 * The address of parameter (struct rte_eth_dev *) regsitered before.
1610 eth_em_interrupt_handler(void *param)
1612 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1614 eth_em_interrupt_get_status(dev);
1615 eth_em_interrupt_action(dev, dev->intr_handle);
1616 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1620 eth_em_led_on(struct rte_eth_dev *dev)
1622 struct e1000_hw *hw;
1624 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1629 eth_em_led_off(struct rte_eth_dev *dev)
1631 struct e1000_hw *hw;
1633 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1638 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1640 struct e1000_hw *hw;
1645 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646 fc_conf->pause_time = hw->fc.pause_time;
1647 fc_conf->high_water = hw->fc.high_water;
1648 fc_conf->low_water = hw->fc.low_water;
1649 fc_conf->send_xon = hw->fc.send_xon;
1650 fc_conf->autoneg = hw->mac.autoneg;
1653 * Return rx_pause and tx_pause status according to actual setting of
1654 * the TFCE and RFCE bits in the CTRL register.
1656 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1657 if (ctrl & E1000_CTRL_TFCE)
1662 if (ctrl & E1000_CTRL_RFCE)
1667 if (rx_pause && tx_pause)
1668 fc_conf->mode = RTE_FC_FULL;
1670 fc_conf->mode = RTE_FC_RX_PAUSE;
1672 fc_conf->mode = RTE_FC_TX_PAUSE;
1674 fc_conf->mode = RTE_FC_NONE;
1680 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1682 struct e1000_hw *hw;
1684 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1690 uint32_t rx_buf_size;
1691 uint32_t max_high_water;
1694 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695 if (fc_conf->autoneg != hw->mac.autoneg)
1697 rx_buf_size = em_get_rx_buffer_size(hw);
1698 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1700 /* At least reserve one Ethernet frame for watermark */
1701 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
1702 if ((fc_conf->high_water > max_high_water) ||
1703 (fc_conf->high_water < fc_conf->low_water)) {
1704 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1705 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1709 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1710 hw->fc.pause_time = fc_conf->pause_time;
1711 hw->fc.high_water = fc_conf->high_water;
1712 hw->fc.low_water = fc_conf->low_water;
1713 hw->fc.send_xon = fc_conf->send_xon;
1715 err = e1000_setup_link_generic(hw);
1716 if (err == E1000_SUCCESS) {
1718 /* check if we want to forward MAC frames - driver doesn't have native
1719 * capability to do that, so we'll write the registers ourselves */
1721 rctl = E1000_READ_REG(hw, E1000_RCTL);
1723 /* set or clear MFLCN.PMCF bit depending on configuration */
1724 if (fc_conf->mac_ctrl_frame_fwd != 0)
1725 rctl |= E1000_RCTL_PMCF;
1727 rctl &= ~E1000_RCTL_PMCF;
1729 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1730 E1000_WRITE_FLUSH(hw);
1735 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1740 eth_em_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1741 uint32_t index, __rte_unused uint32_t pool)
1743 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1745 return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1749 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1751 uint8_t addr[RTE_ETHER_ADDR_LEN];
1752 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754 memset(addr, 0, sizeof(addr));
1756 e1000_rar_set(hw, addr, index);
1760 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1761 struct rte_ether_addr *addr)
1763 eth_em_rar_clear(dev, 0);
1765 return eth_em_rar_set(dev, (void *)addr, 0, 0);
1769 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1771 struct rte_eth_dev_info dev_info;
1772 struct e1000_hw *hw;
1773 uint32_t frame_size;
1776 eth_em_infos_get(dev, &dev_info);
1777 frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1780 /* check that mtu is within the allowed range */
1781 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
1784 /* refuse mtu that requires the support of scattered packets when this
1785 * feature has not been enabled before. */
1786 if (!dev->data->scattered_rx &&
1787 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1790 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1791 rctl = E1000_READ_REG(hw, E1000_RCTL);
1793 /* switch to jumbo mode if needed */
1794 if (frame_size > RTE_ETHER_MAX_LEN) {
1795 dev->data->dev_conf.rxmode.offloads |=
1796 DEV_RX_OFFLOAD_JUMBO_FRAME;
1797 rctl |= E1000_RCTL_LPE;
1799 dev->data->dev_conf.rxmode.offloads &=
1800 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1801 rctl &= ~E1000_RCTL_LPE;
1803 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1805 /* update max frame size */
1806 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1811 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1812 struct rte_ether_addr *mc_addr_set,
1813 uint32_t nb_mc_addr)
1815 struct e1000_hw *hw;
1817 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1822 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1823 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1824 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1826 /* see e1000_logs.c */
1827 RTE_INIT(igb_init_log)
1829 e1000_igb_init_log();