4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
59 #define EM_EIAC 0x000DC
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
86 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
89 static int em_hw_init(struct e1000_hw *hw);
90 static int em_hardware_init(struct e1000_hw *hw);
91 static void em_hw_control_acquire(struct e1000_hw *hw);
92 static void em_hw_control_release(struct e1000_hw *hw);
93 static void em_init_manageability(struct e1000_hw *hw);
94 static void em_release_manageability(struct e1000_hw *hw);
96 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
98 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
99 uint16_t vlan_id, int on);
100 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
101 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
102 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
107 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
108 uint16_t vlan_id, int on);
110 static int eth_em_led_on(struct rte_eth_dev *dev);
111 static int eth_em_led_off(struct rte_eth_dev *dev);
113 static void em_intr_disable(struct e1000_hw *hw);
114 static int em_get_rx_buffer_size(struct e1000_hw *hw);
115 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
116 uint32_t index, uint32_t pool);
117 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
119 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
120 struct ether_addr *mc_addr_set,
121 uint32_t nb_mc_addr);
123 #define EM_FC_PAUSE_TIME 0x0680
124 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
125 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
127 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
130 * The set of PCI devices this driver supports
132 static const struct rte_pci_id pci_id_em_map[] = {
134 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
135 #include "rte_pci_dev_ids.h"
140 static const struct eth_dev_ops eth_em_ops = {
141 .dev_configure = eth_em_configure,
142 .dev_start = eth_em_start,
143 .dev_stop = eth_em_stop,
144 .dev_close = eth_em_close,
145 .promiscuous_enable = eth_em_promiscuous_enable,
146 .promiscuous_disable = eth_em_promiscuous_disable,
147 .allmulticast_enable = eth_em_allmulticast_enable,
148 .allmulticast_disable = eth_em_allmulticast_disable,
149 .link_update = eth_em_link_update,
150 .stats_get = eth_em_stats_get,
151 .stats_reset = eth_em_stats_reset,
152 .dev_infos_get = eth_em_infos_get,
153 .mtu_set = eth_em_mtu_set,
154 .vlan_filter_set = eth_em_vlan_filter_set,
155 .vlan_offload_set = eth_em_vlan_offload_set,
156 .rx_queue_setup = eth_em_rx_queue_setup,
157 .rx_queue_release = eth_em_rx_queue_release,
158 .rx_queue_count = eth_em_rx_queue_count,
159 .rx_descriptor_done = eth_em_rx_descriptor_done,
160 .tx_queue_setup = eth_em_tx_queue_setup,
161 .tx_queue_release = eth_em_tx_queue_release,
162 .dev_led_on = eth_em_led_on,
163 .dev_led_off = eth_em_led_off,
164 .flow_ctrl_get = eth_em_flow_ctrl_get,
165 .flow_ctrl_set = eth_em_flow_ctrl_set,
166 .mac_addr_add = eth_em_rar_set,
167 .mac_addr_remove = eth_em_rar_clear,
168 .set_mc_addr_list = eth_em_set_mc_addr_list,
172 * Atomically reads the link status information from global
173 * structure rte_eth_dev.
176 * - Pointer to the structure rte_eth_dev to read from.
177 * - Pointer to the buffer to be saved with the link status.
180 * - On success, zero.
181 * - On failure, negative value.
184 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
185 struct rte_eth_link *link)
187 struct rte_eth_link *dst = link;
188 struct rte_eth_link *src = &(dev->data->dev_link);
190 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
191 *(uint64_t *)src) == 0)
198 * Atomically writes the link status information into global
199 * structure rte_eth_dev.
202 * - Pointer to the structure rte_eth_dev to read from.
203 * - Pointer to the buffer to be saved with the link status.
206 * - On success, zero.
207 * - On failure, negative value.
210 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
211 struct rte_eth_link *link)
213 struct rte_eth_link *dst = &(dev->data->dev_link);
214 struct rte_eth_link *src = link;
216 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
217 *(uint64_t *)src) == 0)
224 eth_em_dev_init(struct rte_eth_dev *eth_dev)
226 struct rte_pci_device *pci_dev;
227 struct e1000_adapter *adapter =
228 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
229 struct e1000_hw *hw =
230 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
231 struct e1000_vfta * shadow_vfta =
232 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
234 pci_dev = eth_dev->pci_dev;
235 eth_dev->dev_ops = ð_em_ops;
236 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
237 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
239 /* for secondary processes, we don't initialise any further as primary
240 * has already done this work. Only check we don't need a different
242 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
243 if (eth_dev->data->scattered_rx)
244 eth_dev->rx_pkt_burst =
245 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
249 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
250 hw->device_id = pci_dev->id.device_id;
251 adapter->stopped = 0;
253 /* For ICH8 support we'll need to map the flash memory BAR */
255 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
256 em_hw_init(hw) != 0) {
257 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
259 eth_dev->data->port_id, pci_dev->id.vendor_id,
260 pci_dev->id.device_id);
264 /* Allocate memory for storing MAC addresses */
265 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
266 hw->mac.rar_entry_count, 0);
267 if (eth_dev->data->mac_addrs == NULL) {
268 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
269 "store MAC addresses",
270 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
274 /* Copy the permanent MAC address */
275 ether_addr_copy((struct ether_addr *) hw->mac.addr,
276 eth_dev->data->mac_addrs);
278 /* initialize the vfta */
279 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
281 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
282 eth_dev->data->port_id, pci_dev->id.vendor_id,
283 pci_dev->id.device_id);
285 rte_intr_callback_register(&(pci_dev->intr_handle),
286 eth_em_interrupt_handler, (void *)eth_dev);
292 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
294 struct rte_pci_device *pci_dev;
295 struct e1000_adapter *adapter =
296 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
298 PMD_INIT_FUNC_TRACE();
300 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
303 pci_dev = eth_dev->pci_dev;
305 if (adapter->stopped == 0)
306 eth_em_close(eth_dev);
308 eth_dev->dev_ops = NULL;
309 eth_dev->rx_pkt_burst = NULL;
310 eth_dev->tx_pkt_burst = NULL;
312 rte_free(eth_dev->data->mac_addrs);
313 eth_dev->data->mac_addrs = NULL;
315 /* disable uio intr before callback unregister */
316 rte_intr_disable(&(pci_dev->intr_handle));
317 rte_intr_callback_unregister(&(pci_dev->intr_handle),
318 eth_em_interrupt_handler, (void *)eth_dev);
323 static struct eth_driver rte_em_pmd = {
325 .name = "rte_em_pmd",
326 .id_table = pci_id_em_map,
327 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
328 RTE_PCI_DRV_DETACHABLE,
330 .eth_dev_init = eth_em_dev_init,
331 .eth_dev_uninit = eth_em_dev_uninit,
332 .dev_private_size = sizeof(struct e1000_adapter),
336 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
338 rte_eth_driver_register(&rte_em_pmd);
343 em_hw_init(struct e1000_hw *hw)
347 diag = hw->mac.ops.init_params(hw);
349 PMD_INIT_LOG(ERR, "MAC Initialization Error");
352 diag = hw->nvm.ops.init_params(hw);
354 PMD_INIT_LOG(ERR, "NVM Initialization Error");
357 diag = hw->phy.ops.init_params(hw);
359 PMD_INIT_LOG(ERR, "PHY Initialization Error");
362 (void) e1000_get_bus_info(hw);
365 hw->phy.autoneg_wait_to_complete = 0;
366 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
368 e1000_init_script_state_82541(hw, TRUE);
369 e1000_set_tbi_compatibility_82543(hw, TRUE);
372 if (hw->phy.media_type == e1000_media_type_copper) {
373 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
374 hw->phy.disable_polarity_correction = 0;
375 hw->phy.ms_type = e1000_ms_hw_default;
379 * Start from a known state, this is important in reading the nvm
384 /* Make sure we have a good EEPROM before we read from it */
385 if (e1000_validate_nvm_checksum(hw) < 0) {
387 * Some PCI-E parts fail the first check due to
388 * the link being in sleep state, call it again,
389 * if it fails a second time its a real issue.
391 diag = e1000_validate_nvm_checksum(hw);
393 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
398 /* Read the permanent MAC address out of the EEPROM */
399 diag = e1000_read_mac_addr(hw);
401 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
405 /* Now initialize the hardware */
406 diag = em_hardware_init(hw);
408 PMD_INIT_LOG(ERR, "Hardware initialization failed");
412 hw->mac.get_link_status = 1;
414 /* Indicate SOL/IDER usage */
415 diag = e1000_check_reset_block(hw);
417 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
423 em_hw_control_release(hw);
428 eth_em_configure(struct rte_eth_dev *dev)
430 struct e1000_interrupt *intr =
431 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
433 PMD_INIT_FUNC_TRACE();
434 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
435 PMD_INIT_FUNC_TRACE();
441 em_set_pba(struct e1000_hw *hw)
446 * Packet Buffer Allocation (PBA)
447 * Writing PBA sets the receive portion of the buffer
448 * the remainder is used for the transmit buffer.
449 * Devices before the 82547 had a Packet Buffer of 64K.
450 * After the 82547 the buffer was reduced to 40K.
452 switch (hw->mac.type) {
454 case e1000_82547_rev_2:
455 /* 82547: Total Packet Buffer is 40K */
456 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
460 case e1000_80003es2lan:
461 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
463 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
464 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
468 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
482 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
485 E1000_WRITE_REG(hw, E1000_PBA, pba);
489 eth_em_start(struct rte_eth_dev *dev)
491 struct e1000_adapter *adapter =
492 E1000_DEV_PRIVATE(dev->data->dev_private);
493 struct e1000_hw *hw =
494 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
497 PMD_INIT_FUNC_TRACE();
501 e1000_power_up_phy(hw);
503 /* Set default PBA value */
506 /* Put the address into the Receive Address Array */
507 e1000_rar_set(hw, hw->mac.addr, 0);
510 * With the 82571 adapter, RAR[0] may be overwritten
511 * when the other port is reset, we make a duplicate
512 * in RAR[14] for that eventuality, this assures
513 * the interface continues to function.
515 if (hw->mac.type == e1000_82571) {
516 e1000_set_laa_state_82571(hw, TRUE);
517 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
520 /* Initialize the hardware */
521 if (em_hardware_init(hw)) {
522 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
526 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
528 /* Configure for OS presence */
529 em_init_manageability(hw);
533 ret = eth_em_rx_init(dev);
535 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
536 em_dev_clear_queues(dev);
540 e1000_clear_hw_cntrs_base_generic(hw);
542 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
543 ETH_VLAN_EXTEND_MASK;
544 eth_em_vlan_offload_set(dev, mask);
546 /* Set Interrupt Throttling Rate to maximum allowed value. */
547 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
549 /* Setup link speed and duplex */
550 switch (dev->data->dev_conf.link_speed) {
551 case ETH_LINK_SPEED_AUTONEG:
552 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
553 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
554 else if (dev->data->dev_conf.link_duplex ==
555 ETH_LINK_HALF_DUPLEX)
556 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
557 else if (dev->data->dev_conf.link_duplex ==
558 ETH_LINK_FULL_DUPLEX)
559 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
561 goto error_invalid_config;
563 case ETH_LINK_SPEED_10:
564 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
565 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
566 else if (dev->data->dev_conf.link_duplex ==
567 ETH_LINK_HALF_DUPLEX)
568 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
569 else if (dev->data->dev_conf.link_duplex ==
570 ETH_LINK_FULL_DUPLEX)
571 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
573 goto error_invalid_config;
575 case ETH_LINK_SPEED_100:
576 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
577 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
578 else if (dev->data->dev_conf.link_duplex ==
579 ETH_LINK_HALF_DUPLEX)
580 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
581 else if (dev->data->dev_conf.link_duplex ==
582 ETH_LINK_FULL_DUPLEX)
583 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
585 goto error_invalid_config;
587 case ETH_LINK_SPEED_1000:
588 if ((dev->data->dev_conf.link_duplex ==
589 ETH_LINK_AUTONEG_DUPLEX) ||
590 (dev->data->dev_conf.link_duplex ==
591 ETH_LINK_FULL_DUPLEX))
592 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
594 goto error_invalid_config;
596 case ETH_LINK_SPEED_10000:
598 goto error_invalid_config;
600 e1000_setup_link(hw);
602 /* check if lsc interrupt feature is enabled */
603 if (dev->data->dev_conf.intr_conf.lsc != 0) {
604 ret = eth_em_interrupt_setup(dev);
606 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
607 em_dev_clear_queues(dev);
612 adapter->stopped = 0;
614 PMD_INIT_LOG(DEBUG, "<<");
618 error_invalid_config:
619 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
620 dev->data->dev_conf.link_speed,
621 dev->data->dev_conf.link_duplex, dev->data->port_id);
622 em_dev_clear_queues(dev);
626 /*********************************************************************
628 * This routine disables all traffic on the adapter by issuing a
629 * global reset on the MAC.
631 **********************************************************************/
633 eth_em_stop(struct rte_eth_dev *dev)
635 struct rte_eth_link link;
636 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
640 if (hw->mac.type >= e1000_82544)
641 E1000_WRITE_REG(hw, E1000_WUC, 0);
643 /* Power down the phy. Needed to make the link go down */
644 e1000_power_down_phy(hw);
646 em_dev_clear_queues(dev);
648 /* clear the recorded link status */
649 memset(&link, 0, sizeof(link));
650 rte_em_dev_atomic_write_link_status(dev, &link);
654 eth_em_close(struct rte_eth_dev *dev)
656 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
657 struct e1000_adapter *adapter =
658 E1000_DEV_PRIVATE(dev->data->dev_private);
661 adapter->stopped = 1;
662 e1000_phy_hw_reset(hw);
663 em_release_manageability(hw);
664 em_hw_control_release(hw);
668 em_get_rx_buffer_size(struct e1000_hw *hw)
670 uint32_t rx_buf_size;
672 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
676 /*********************************************************************
678 * Initialize the hardware
680 **********************************************************************/
682 em_hardware_init(struct e1000_hw *hw)
684 uint32_t rx_buf_size;
687 /* Issue a global reset */
690 /* Let the firmware know the OS is in control */
691 em_hw_control_acquire(hw);
694 * These parameters control the automatic generation (Tx) and
695 * response (Rx) to Ethernet PAUSE frames.
696 * - High water mark should allow for at least two standard size (1518)
697 * frames to be received after sending an XOFF.
698 * - Low water mark works best when it is very near the high water mark.
699 * This allows the receiver to restart by sending XON when it has
700 * drained a bit. Here we use an arbitrary value of 1500 which will
701 * restart after one full frame is pulled from the buffer. There
702 * could be several smaller frames in the buffer and if so they will
703 * not trigger the XON until their total number reduces the buffer
705 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
707 rx_buf_size = em_get_rx_buffer_size(hw);
709 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
710 hw->fc.low_water = hw->fc.high_water - 1500;
712 if (hw->mac.type == e1000_80003es2lan)
713 hw->fc.pause_time = UINT16_MAX;
715 hw->fc.pause_time = EM_FC_PAUSE_TIME;
719 /* Set Flow control, use the tunable location if sane */
720 if (em_fc_setting <= e1000_fc_full)
721 hw->fc.requested_mode = em_fc_setting;
723 hw->fc.requested_mode = e1000_fc_none;
725 /* Workaround: no TX flow ctrl for PCH */
726 if (hw->mac.type == e1000_pchlan)
727 hw->fc.requested_mode = e1000_fc_rx_pause;
729 /* Override - settings for PCH2LAN, ya its magic :) */
730 if (hw->mac.type == e1000_pch2lan) {
731 hw->fc.high_water = 0x5C20;
732 hw->fc.low_water = 0x5048;
733 hw->fc.pause_time = 0x0650;
734 hw->fc.refresh_time = 0x0400;
737 diag = e1000_init_hw(hw);
740 e1000_check_for_link(hw);
744 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
746 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
748 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
749 struct e1000_hw_stats *stats =
750 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
753 if(hw->phy.media_type == e1000_media_type_copper ||
754 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
755 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
756 stats->sec += E1000_READ_REG(hw, E1000_SEC);
759 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
760 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
761 stats->scc += E1000_READ_REG(hw, E1000_SCC);
762 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
764 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
765 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
766 stats->colc += E1000_READ_REG(hw, E1000_COLC);
767 stats->dc += E1000_READ_REG(hw, E1000_DC);
768 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
769 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
770 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
773 * For watchdog management we need to know if we have been
774 * paused during the last interval, so capture that here.
776 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
777 stats->xoffrxc += pause_frames;
778 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
779 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
780 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
781 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
782 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
783 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
784 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
785 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
786 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
787 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
788 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
789 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
792 * For the 64-bit byte counters the low dword must be read first.
793 * Both registers clear on the read of the high dword.
796 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
797 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
798 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
799 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
801 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
802 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
803 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
804 stats->roc += E1000_READ_REG(hw, E1000_ROC);
805 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
807 stats->tor += E1000_READ_REG(hw, E1000_TORH);
808 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
810 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
811 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
812 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
813 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
814 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
815 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
816 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
817 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
818 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
819 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
821 /* Interrupt Counts */
823 if (hw->mac.type >= e1000_82571) {
824 stats->iac += E1000_READ_REG(hw, E1000_IAC);
825 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
826 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
827 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
828 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
829 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
830 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
831 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
832 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
835 if (hw->mac.type >= e1000_82543) {
836 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
837 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
838 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
839 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
840 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
841 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
844 if (rte_stats == NULL)
848 rte_stats->ibadcrc = stats->crcerrs;
849 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
850 rte_stats->imissed = stats->mpc;
851 rte_stats->ierrors = rte_stats->ibadcrc +
854 stats->rxerrc + stats->algnerrc + stats->cexterr;
857 rte_stats->oerrors = stats->ecol + stats->latecol;
859 rte_stats->ipackets = stats->gprc;
860 rte_stats->opackets = stats->gptc;
861 rte_stats->ibytes = stats->gorc;
862 rte_stats->obytes = stats->gotc;
864 /* XON/XOFF pause frames stats registers */
865 rte_stats->tx_pause_xon = stats->xontxc;
866 rte_stats->rx_pause_xon = stats->xonrxc;
867 rte_stats->tx_pause_xoff = stats->xofftxc;
868 rte_stats->rx_pause_xoff = stats->xoffrxc;
872 eth_em_stats_reset(struct rte_eth_dev *dev)
874 struct e1000_hw_stats *hw_stats =
875 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
877 /* HW registers are cleared on read */
878 eth_em_stats_get(dev, NULL);
880 /* Reset software totals */
881 memset(hw_stats, 0, sizeof(*hw_stats));
885 em_get_max_pktlen(const struct e1000_hw *hw)
887 switch (hw->mac.type) {
894 case e1000_80003es2lan: /* 9K Jumbo Frame size */
898 /* Adapters that do not support jumbo frames */
901 return (ETHER_MAX_LEN);
903 return (MAX_JUMBO_FRAME_SIZE);
908 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
910 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
912 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
913 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
914 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
917 * Starting with 631xESB hw supports 2 TX/RX queues per port.
918 * Unfortunatelly, all these nics have just one TX context.
919 * So we have few choises for TX:
920 * - Use just one TX queue.
921 * - Allow cksum offload only for one TX queue.
922 * - Don't allow TX cksum offload at all.
923 * For now, option #1 was chosen.
924 * To use second RX queue we have to use extended RX descriptor
925 * (Multiple Receive Queues are mutually exclusive with UDP
926 * fragmentation and are not supported when a legacy receive
927 * descriptor format is used).
928 * Which means separate RX routinies - as legacy nics (82540, 82545)
929 * don't support extended RXD.
930 * To avoid it we support just one RX queue for now (no RSS).
933 dev_info->max_rx_queues = 1;
934 dev_info->max_tx_queues = 1;
937 /* return 0 means link status changed, -1 means not changed */
939 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
941 struct e1000_hw *hw =
942 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
943 struct rte_eth_link link, old;
944 int link_check, count;
947 hw->mac.get_link_status = 1;
949 /* possible wait-to-complete in up to 9 seconds */
950 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
951 /* Read the real link status */
952 switch (hw->phy.media_type) {
953 case e1000_media_type_copper:
954 /* Do the work to read phy */
955 e1000_check_for_link(hw);
956 link_check = !hw->mac.get_link_status;
959 case e1000_media_type_fiber:
960 e1000_check_for_link(hw);
961 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
965 case e1000_media_type_internal_serdes:
966 e1000_check_for_link(hw);
967 link_check = hw->mac.serdes_has_link;
973 if (link_check || wait_to_complete == 0)
975 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
977 memset(&link, 0, sizeof(link));
978 rte_em_dev_atomic_read_link_status(dev, &link);
981 /* Now we check if a transition has happened */
982 if (link_check && (link.link_status == 0)) {
983 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
985 link.link_status = 1;
986 } else if (!link_check && (link.link_status == 1)) {
988 link.link_duplex = 0;
989 link.link_status = 0;
991 rte_em_dev_atomic_write_link_status(dev, &link);
994 if (old.link_status == link.link_status)
1002 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1003 * For ASF and Pass Through versions of f/w this means
1004 * that the driver is loaded. For AMT version type f/w
1005 * this means that the network i/f is open.
1008 em_hw_control_acquire(struct e1000_hw *hw)
1010 uint32_t ctrl_ext, swsm;
1012 /* Let firmware know the driver has taken over */
1013 if (hw->mac.type == e1000_82573) {
1014 swsm = E1000_READ_REG(hw, E1000_SWSM);
1015 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1018 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1019 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1020 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1025 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1026 * For ASF and Pass Through versions of f/w this means that the
1027 * driver is no longer loaded. For AMT versions of the
1028 * f/w this means that the network i/f is closed.
1031 em_hw_control_release(struct e1000_hw *hw)
1033 uint32_t ctrl_ext, swsm;
1035 /* Let firmware taken over control of h/w */
1036 if (hw->mac.type == e1000_82573) {
1037 swsm = E1000_READ_REG(hw, E1000_SWSM);
1038 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1040 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1041 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1042 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1047 * Bit of a misnomer, what this really means is
1048 * to enable OS management of the system... aka
1049 * to disable special hardware management features.
1052 em_init_manageability(struct e1000_hw *hw)
1054 if (e1000_enable_mng_pass_thru(hw)) {
1055 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1056 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1058 /* disable hardware interception of ARP */
1059 manc &= ~(E1000_MANC_ARP_EN);
1061 /* enable receiving management packets to the host */
1062 manc |= E1000_MANC_EN_MNG2HOST;
1063 manc2h |= 1 << 5; /* Mng Port 623 */
1064 manc2h |= 1 << 6; /* Mng Port 664 */
1065 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1066 E1000_WRITE_REG(hw, E1000_MANC, manc);
1071 * Give control back to hardware management
1072 * controller if there is one.
1075 em_release_manageability(struct e1000_hw *hw)
1079 if (e1000_enable_mng_pass_thru(hw)) {
1080 manc = E1000_READ_REG(hw, E1000_MANC);
1082 /* re-enable hardware interception of ARP */
1083 manc |= E1000_MANC_ARP_EN;
1084 manc &= ~E1000_MANC_EN_MNG2HOST;
1086 E1000_WRITE_REG(hw, E1000_MANC, manc);
1091 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1093 struct e1000_hw *hw =
1094 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1097 rctl = E1000_READ_REG(hw, E1000_RCTL);
1098 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1099 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1103 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1105 struct e1000_hw *hw =
1106 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1109 rctl = E1000_READ_REG(hw, E1000_RCTL);
1110 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1111 if (dev->data->all_multicast == 1)
1112 rctl |= E1000_RCTL_MPE;
1114 rctl &= (~E1000_RCTL_MPE);
1115 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1119 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1121 struct e1000_hw *hw =
1122 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1125 rctl = E1000_READ_REG(hw, E1000_RCTL);
1126 rctl |= E1000_RCTL_MPE;
1127 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1131 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1133 struct e1000_hw *hw =
1134 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1137 if (dev->data->promiscuous == 1)
1138 return; /* must remain in all_multicast mode */
1139 rctl = E1000_READ_REG(hw, E1000_RCTL);
1140 rctl &= (~E1000_RCTL_MPE);
1141 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1145 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1147 struct e1000_hw *hw =
1148 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1149 struct e1000_vfta * shadow_vfta =
1150 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1155 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1156 E1000_VFTA_ENTRY_MASK);
1157 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1158 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1163 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1165 /* update local VFTA copy */
1166 shadow_vfta->vfta[vid_idx] = vfta;
1172 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1174 struct e1000_hw *hw =
1175 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178 /* Filter Table Disable */
1179 reg = E1000_READ_REG(hw, E1000_RCTL);
1180 reg &= ~E1000_RCTL_CFIEN;
1181 reg &= ~E1000_RCTL_VFE;
1182 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1186 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1188 struct e1000_hw *hw =
1189 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1190 struct e1000_vfta * shadow_vfta =
1191 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1195 /* Filter Table Enable, CFI not used for packet acceptance */
1196 reg = E1000_READ_REG(hw, E1000_RCTL);
1197 reg &= ~E1000_RCTL_CFIEN;
1198 reg |= E1000_RCTL_VFE;
1199 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1201 /* restore vfta from local copy */
1202 for (i = 0; i < IGB_VFTA_SIZE; i++)
1203 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1207 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1209 struct e1000_hw *hw =
1210 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1213 /* VLAN Mode Disable */
1214 reg = E1000_READ_REG(hw, E1000_CTRL);
1215 reg &= ~E1000_CTRL_VME;
1216 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1221 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1223 struct e1000_hw *hw =
1224 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1227 /* VLAN Mode Enable */
1228 reg = E1000_READ_REG(hw, E1000_CTRL);
1229 reg |= E1000_CTRL_VME;
1230 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1234 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1236 if(mask & ETH_VLAN_STRIP_MASK){
1237 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1238 em_vlan_hw_strip_enable(dev);
1240 em_vlan_hw_strip_disable(dev);
1243 if(mask & ETH_VLAN_FILTER_MASK){
1244 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1245 em_vlan_hw_filter_enable(dev);
1247 em_vlan_hw_filter_disable(dev);
1252 em_intr_disable(struct e1000_hw *hw)
1254 E1000_WRITE_REG(hw, E1000_IMC, ~0);
1258 * It enables the interrupt mask and then enable the interrupt.
1261 * Pointer to struct rte_eth_dev.
1264 * - On success, zero.
1265 * - On failure, a negative value.
1268 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1270 struct e1000_hw *hw =
1271 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273 E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1274 rte_intr_enable(&(dev->pci_dev->intr_handle));
1279 * It reads ICR and gets interrupt causes, check it and set a bit flag
1280 * to update link status.
1283 * Pointer to struct rte_eth_dev.
1286 * - On success, zero.
1287 * - On failure, a negative value.
1290 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1293 struct e1000_hw *hw =
1294 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1295 struct e1000_interrupt *intr =
1296 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1298 /* read-on-clear nic registers here */
1299 icr = E1000_READ_REG(hw, E1000_ICR);
1300 if (icr & E1000_ICR_LSC) {
1301 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1308 * It executes link_update after knowing an interrupt is prsent.
1311 * Pointer to struct rte_eth_dev.
1314 * - On success, zero.
1315 * - On failure, a negative value.
1318 eth_em_interrupt_action(struct rte_eth_dev *dev)
1320 struct e1000_hw *hw =
1321 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1322 struct e1000_interrupt *intr =
1323 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1324 uint32_t tctl, rctl;
1325 struct rte_eth_link link;
1328 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1331 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1332 rte_intr_enable(&(dev->pci_dev->intr_handle));
1334 /* set get_link_status to check register later */
1335 hw->mac.get_link_status = 1;
1336 ret = eth_em_link_update(dev, 0);
1338 /* check if link has changed */
1342 memset(&link, 0, sizeof(link));
1343 rte_em_dev_atomic_read_link_status(dev, &link);
1344 if (link.link_status) {
1345 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1346 dev->data->port_id, (unsigned)link.link_speed,
1347 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1348 "full-duplex" : "half-duplex");
1350 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1352 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1353 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1354 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1355 tctl = E1000_READ_REG(hw, E1000_TCTL);
1356 rctl = E1000_READ_REG(hw, E1000_RCTL);
1357 if (link.link_status) {
1359 tctl |= E1000_TCTL_EN;
1360 rctl |= E1000_RCTL_EN;
1363 tctl &= ~E1000_TCTL_EN;
1364 rctl &= ~E1000_RCTL_EN;
1366 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1367 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1368 E1000_WRITE_FLUSH(hw);
1374 * Interrupt handler which shall be registered at first.
1377 * Pointer to interrupt handle.
1379 * The address of parameter (struct rte_eth_dev *) regsitered before.
1385 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1388 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1390 eth_em_interrupt_get_status(dev);
1391 eth_em_interrupt_action(dev);
1392 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1396 eth_em_led_on(struct rte_eth_dev *dev)
1398 struct e1000_hw *hw;
1400 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1401 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1405 eth_em_led_off(struct rte_eth_dev *dev)
1407 struct e1000_hw *hw;
1409 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1410 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1414 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1416 struct e1000_hw *hw;
1421 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422 fc_conf->pause_time = hw->fc.pause_time;
1423 fc_conf->high_water = hw->fc.high_water;
1424 fc_conf->low_water = hw->fc.low_water;
1425 fc_conf->send_xon = hw->fc.send_xon;
1426 fc_conf->autoneg = hw->mac.autoneg;
1429 * Return rx_pause and tx_pause status according to actual setting of
1430 * the TFCE and RFCE bits in the CTRL register.
1432 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1433 if (ctrl & E1000_CTRL_TFCE)
1438 if (ctrl & E1000_CTRL_RFCE)
1443 if (rx_pause && tx_pause)
1444 fc_conf->mode = RTE_FC_FULL;
1446 fc_conf->mode = RTE_FC_RX_PAUSE;
1448 fc_conf->mode = RTE_FC_TX_PAUSE;
1450 fc_conf->mode = RTE_FC_NONE;
1456 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1458 struct e1000_hw *hw;
1460 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1466 uint32_t rx_buf_size;
1467 uint32_t max_high_water;
1470 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1471 if (fc_conf->autoneg != hw->mac.autoneg)
1473 rx_buf_size = em_get_rx_buffer_size(hw);
1474 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1476 /* At least reserve one Ethernet frame for watermark */
1477 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1478 if ((fc_conf->high_water > max_high_water) ||
1479 (fc_conf->high_water < fc_conf->low_water)) {
1480 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1481 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1485 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1486 hw->fc.pause_time = fc_conf->pause_time;
1487 hw->fc.high_water = fc_conf->high_water;
1488 hw->fc.low_water = fc_conf->low_water;
1489 hw->fc.send_xon = fc_conf->send_xon;
1491 err = e1000_setup_link_generic(hw);
1492 if (err == E1000_SUCCESS) {
1494 /* check if we want to forward MAC frames - driver doesn't have native
1495 * capability to do that, so we'll write the registers ourselves */
1497 rctl = E1000_READ_REG(hw, E1000_RCTL);
1499 /* set or clear MFLCN.PMCF bit depending on configuration */
1500 if (fc_conf->mac_ctrl_frame_fwd != 0)
1501 rctl |= E1000_RCTL_PMCF;
1503 rctl &= ~E1000_RCTL_PMCF;
1505 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1506 E1000_WRITE_FLUSH(hw);
1511 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1516 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1517 uint32_t index, __rte_unused uint32_t pool)
1519 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1525 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1527 uint8_t addr[ETHER_ADDR_LEN];
1528 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1530 memset(addr, 0, sizeof(addr));
1532 e1000_rar_set(hw, addr, index);
1536 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1538 struct rte_eth_dev_info dev_info;
1539 struct e1000_hw *hw;
1540 uint32_t frame_size;
1543 eth_em_infos_get(dev, &dev_info);
1544 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1546 /* check that mtu is within the allowed range */
1547 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1550 /* refuse mtu that requires the support of scattered packets when this
1551 * feature has not been enabled before. */
1552 if (!dev->data->scattered_rx &&
1553 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1556 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557 rctl = E1000_READ_REG(hw, E1000_RCTL);
1559 /* switch to jumbo mode if needed */
1560 if (frame_size > ETHER_MAX_LEN) {
1561 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1562 rctl |= E1000_RCTL_LPE;
1564 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1565 rctl &= ~E1000_RCTL_LPE;
1567 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1569 /* update max frame size */
1570 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1575 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1576 struct ether_addr *mc_addr_set,
1577 uint32_t nb_mc_addr)
1579 struct e1000_hw *hw;
1581 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1586 struct rte_driver em_pmd_drv = {
1588 .init = rte_em_pmd_init,
1591 PMD_REGISTER_DRIVER(em_pmd_drv);