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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
59 #define EM_EIAC 0x000DC
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
86 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
89 static int em_hw_init(struct e1000_hw *hw);
90 static int em_hardware_init(struct e1000_hw *hw);
91 static void em_hw_control_acquire(struct e1000_hw *hw);
92 static void em_hw_control_release(struct e1000_hw *hw);
93 static void em_init_manageability(struct e1000_hw *hw);
94 static void em_release_manageability(struct e1000_hw *hw);
96 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
98 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
99 uint16_t vlan_id, int on);
100 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
101 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
102 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
107 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
108 uint16_t vlan_id, int on);
110 static void em_lsc_intr_disable(struct e1000_hw *hw);
111 static void em_rxq_intr_disable(struct e1000_hw *hw);
112 static int eth_em_led_on(struct rte_eth_dev *dev);
113 static int eth_em_led_off(struct rte_eth_dev *dev);
115 static int em_get_rx_buffer_size(struct e1000_hw *hw);
116 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
117 uint32_t index, uint32_t pool);
118 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
120 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
121 struct ether_addr *mc_addr_set,
122 uint32_t nb_mc_addr);
124 #define EM_FC_PAUSE_TIME 0x0680
125 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
126 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
128 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
131 * The set of PCI devices this driver supports
133 static const struct rte_pci_id pci_id_em_map[] = {
135 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
136 #include "rte_pci_dev_ids.h"
141 static const struct eth_dev_ops eth_em_ops = {
142 .dev_configure = eth_em_configure,
143 .dev_start = eth_em_start,
144 .dev_stop = eth_em_stop,
145 .dev_close = eth_em_close,
146 .promiscuous_enable = eth_em_promiscuous_enable,
147 .promiscuous_disable = eth_em_promiscuous_disable,
148 .allmulticast_enable = eth_em_allmulticast_enable,
149 .allmulticast_disable = eth_em_allmulticast_disable,
150 .link_update = eth_em_link_update,
151 .stats_get = eth_em_stats_get,
152 .stats_reset = eth_em_stats_reset,
153 .dev_infos_get = eth_em_infos_get,
154 .mtu_set = eth_em_mtu_set,
155 .vlan_filter_set = eth_em_vlan_filter_set,
156 .vlan_offload_set = eth_em_vlan_offload_set,
157 .rx_queue_setup = eth_em_rx_queue_setup,
158 .rx_queue_release = eth_em_rx_queue_release,
159 .rx_queue_count = eth_em_rx_queue_count,
160 .rx_descriptor_done = eth_em_rx_descriptor_done,
161 .tx_queue_setup = eth_em_tx_queue_setup,
162 .tx_queue_release = eth_em_tx_queue_release,
163 .dev_led_on = eth_em_led_on,
164 .dev_led_off = eth_em_led_off,
165 .flow_ctrl_get = eth_em_flow_ctrl_get,
166 .flow_ctrl_set = eth_em_flow_ctrl_set,
167 .mac_addr_add = eth_em_rar_set,
168 .mac_addr_remove = eth_em_rar_clear,
169 .set_mc_addr_list = eth_em_set_mc_addr_list,
173 * Atomically reads the link status information from global
174 * structure rte_eth_dev.
177 * - Pointer to the structure rte_eth_dev to read from.
178 * - Pointer to the buffer to be saved with the link status.
181 * - On success, zero.
182 * - On failure, negative value.
185 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
186 struct rte_eth_link *link)
188 struct rte_eth_link *dst = link;
189 struct rte_eth_link *src = &(dev->data->dev_link);
191 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
192 *(uint64_t *)src) == 0)
199 * Atomically writes the link status information into global
200 * structure rte_eth_dev.
203 * - Pointer to the structure rte_eth_dev to read from.
204 * - Pointer to the buffer to be saved with the link status.
207 * - On success, zero.
208 * - On failure, negative value.
211 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
212 struct rte_eth_link *link)
214 struct rte_eth_link *dst = &(dev->data->dev_link);
215 struct rte_eth_link *src = link;
217 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
218 *(uint64_t *)src) == 0)
225 eth_em_dev_init(struct rte_eth_dev *eth_dev)
227 struct rte_pci_device *pci_dev;
228 struct e1000_adapter *adapter =
229 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
230 struct e1000_hw *hw =
231 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
232 struct e1000_vfta * shadow_vfta =
233 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
235 pci_dev = eth_dev->pci_dev;
236 eth_dev->dev_ops = ð_em_ops;
237 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
238 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
240 /* for secondary processes, we don't initialise any further as primary
241 * has already done this work. Only check we don't need a different
243 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
244 if (eth_dev->data->scattered_rx)
245 eth_dev->rx_pkt_burst =
246 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
250 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
251 hw->device_id = pci_dev->id.device_id;
252 adapter->stopped = 0;
254 /* For ICH8 support we'll need to map the flash memory BAR */
256 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
257 em_hw_init(hw) != 0) {
258 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
260 eth_dev->data->port_id, pci_dev->id.vendor_id,
261 pci_dev->id.device_id);
265 /* Allocate memory for storing MAC addresses */
266 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
267 hw->mac.rar_entry_count, 0);
268 if (eth_dev->data->mac_addrs == NULL) {
269 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
270 "store MAC addresses",
271 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
275 /* Copy the permanent MAC address */
276 ether_addr_copy((struct ether_addr *) hw->mac.addr,
277 eth_dev->data->mac_addrs);
279 /* initialize the vfta */
280 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
282 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
283 eth_dev->data->port_id, pci_dev->id.vendor_id,
284 pci_dev->id.device_id);
286 rte_intr_callback_register(&(pci_dev->intr_handle),
287 eth_em_interrupt_handler, (void *)eth_dev);
293 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
295 struct rte_pci_device *pci_dev;
296 struct e1000_adapter *adapter =
297 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
299 PMD_INIT_FUNC_TRACE();
301 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
304 pci_dev = eth_dev->pci_dev;
306 if (adapter->stopped == 0)
307 eth_em_close(eth_dev);
309 eth_dev->dev_ops = NULL;
310 eth_dev->rx_pkt_burst = NULL;
311 eth_dev->tx_pkt_burst = NULL;
313 rte_free(eth_dev->data->mac_addrs);
314 eth_dev->data->mac_addrs = NULL;
316 /* disable uio intr before callback unregister */
317 rte_intr_disable(&(pci_dev->intr_handle));
318 rte_intr_callback_unregister(&(pci_dev->intr_handle),
319 eth_em_interrupt_handler, (void *)eth_dev);
324 static struct eth_driver rte_em_pmd = {
326 .name = "rte_em_pmd",
327 .id_table = pci_id_em_map,
328 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
329 RTE_PCI_DRV_DETACHABLE,
331 .eth_dev_init = eth_em_dev_init,
332 .eth_dev_uninit = eth_em_dev_uninit,
333 .dev_private_size = sizeof(struct e1000_adapter),
337 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
339 rte_eth_driver_register(&rte_em_pmd);
344 em_hw_init(struct e1000_hw *hw)
348 diag = hw->mac.ops.init_params(hw);
350 PMD_INIT_LOG(ERR, "MAC Initialization Error");
353 diag = hw->nvm.ops.init_params(hw);
355 PMD_INIT_LOG(ERR, "NVM Initialization Error");
358 diag = hw->phy.ops.init_params(hw);
360 PMD_INIT_LOG(ERR, "PHY Initialization Error");
363 (void) e1000_get_bus_info(hw);
366 hw->phy.autoneg_wait_to_complete = 0;
367 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
369 e1000_init_script_state_82541(hw, TRUE);
370 e1000_set_tbi_compatibility_82543(hw, TRUE);
373 if (hw->phy.media_type == e1000_media_type_copper) {
374 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
375 hw->phy.disable_polarity_correction = 0;
376 hw->phy.ms_type = e1000_ms_hw_default;
380 * Start from a known state, this is important in reading the nvm
385 /* Make sure we have a good EEPROM before we read from it */
386 if (e1000_validate_nvm_checksum(hw) < 0) {
388 * Some PCI-E parts fail the first check due to
389 * the link being in sleep state, call it again,
390 * if it fails a second time its a real issue.
392 diag = e1000_validate_nvm_checksum(hw);
394 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
399 /* Read the permanent MAC address out of the EEPROM */
400 diag = e1000_read_mac_addr(hw);
402 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
406 /* Now initialize the hardware */
407 diag = em_hardware_init(hw);
409 PMD_INIT_LOG(ERR, "Hardware initialization failed");
413 hw->mac.get_link_status = 1;
415 /* Indicate SOL/IDER usage */
416 diag = e1000_check_reset_block(hw);
418 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
424 em_hw_control_release(hw);
429 eth_em_configure(struct rte_eth_dev *dev)
431 struct e1000_interrupt *intr =
432 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
434 PMD_INIT_FUNC_TRACE();
435 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
436 PMD_INIT_FUNC_TRACE();
442 em_set_pba(struct e1000_hw *hw)
447 * Packet Buffer Allocation (PBA)
448 * Writing PBA sets the receive portion of the buffer
449 * the remainder is used for the transmit buffer.
450 * Devices before the 82547 had a Packet Buffer of 64K.
451 * After the 82547 the buffer was reduced to 40K.
453 switch (hw->mac.type) {
455 case e1000_82547_rev_2:
456 /* 82547: Total Packet Buffer is 40K */
457 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
461 case e1000_80003es2lan:
462 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
464 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
465 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
469 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
483 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
486 E1000_WRITE_REG(hw, E1000_PBA, pba);
490 eth_em_start(struct rte_eth_dev *dev)
492 struct e1000_adapter *adapter =
493 E1000_DEV_PRIVATE(dev->data->dev_private);
494 struct e1000_hw *hw =
495 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
498 PMD_INIT_FUNC_TRACE();
502 e1000_power_up_phy(hw);
504 /* Set default PBA value */
507 /* Put the address into the Receive Address Array */
508 e1000_rar_set(hw, hw->mac.addr, 0);
511 * With the 82571 adapter, RAR[0] may be overwritten
512 * when the other port is reset, we make a duplicate
513 * in RAR[14] for that eventuality, this assures
514 * the interface continues to function.
516 if (hw->mac.type == e1000_82571) {
517 e1000_set_laa_state_82571(hw, TRUE);
518 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
521 /* Initialize the hardware */
522 if (em_hardware_init(hw)) {
523 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
527 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
529 /* Configure for OS presence */
530 em_init_manageability(hw);
534 ret = eth_em_rx_init(dev);
536 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
537 em_dev_clear_queues(dev);
541 e1000_clear_hw_cntrs_base_generic(hw);
543 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
544 ETH_VLAN_EXTEND_MASK;
545 eth_em_vlan_offload_set(dev, mask);
547 /* Set Interrupt Throttling Rate to maximum allowed value. */
548 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
550 /* Setup link speed and duplex */
551 switch (dev->data->dev_conf.link_speed) {
552 case ETH_LINK_SPEED_AUTONEG:
553 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
554 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
555 else if (dev->data->dev_conf.link_duplex ==
556 ETH_LINK_HALF_DUPLEX)
557 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
558 else if (dev->data->dev_conf.link_duplex ==
559 ETH_LINK_FULL_DUPLEX)
560 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
562 goto error_invalid_config;
564 case ETH_LINK_SPEED_10:
565 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
566 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
567 else if (dev->data->dev_conf.link_duplex ==
568 ETH_LINK_HALF_DUPLEX)
569 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
570 else if (dev->data->dev_conf.link_duplex ==
571 ETH_LINK_FULL_DUPLEX)
572 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
574 goto error_invalid_config;
576 case ETH_LINK_SPEED_100:
577 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
578 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
579 else if (dev->data->dev_conf.link_duplex ==
580 ETH_LINK_HALF_DUPLEX)
581 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
582 else if (dev->data->dev_conf.link_duplex ==
583 ETH_LINK_FULL_DUPLEX)
584 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
586 goto error_invalid_config;
588 case ETH_LINK_SPEED_1000:
589 if ((dev->data->dev_conf.link_duplex ==
590 ETH_LINK_AUTONEG_DUPLEX) ||
591 (dev->data->dev_conf.link_duplex ==
592 ETH_LINK_FULL_DUPLEX))
593 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
595 goto error_invalid_config;
597 case ETH_LINK_SPEED_10000:
599 goto error_invalid_config;
601 e1000_setup_link(hw);
603 /* check if lsc interrupt feature is enabled */
604 if (dev->data->dev_conf.intr_conf.lsc != 0) {
605 ret = eth_em_interrupt_setup(dev);
607 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
608 em_dev_clear_queues(dev);
613 adapter->stopped = 0;
615 PMD_INIT_LOG(DEBUG, "<<");
619 error_invalid_config:
620 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
621 dev->data->dev_conf.link_speed,
622 dev->data->dev_conf.link_duplex, dev->data->port_id);
623 em_dev_clear_queues(dev);
627 /*********************************************************************
629 * This routine disables all traffic on the adapter by issuing a
630 * global reset on the MAC.
632 **********************************************************************/
634 eth_em_stop(struct rte_eth_dev *dev)
636 struct rte_eth_link link;
637 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
639 em_rxq_intr_disable(hw);
640 em_lsc_intr_disable(hw);
643 if (hw->mac.type >= e1000_82544)
644 E1000_WRITE_REG(hw, E1000_WUC, 0);
646 /* Power down the phy. Needed to make the link go down */
647 e1000_power_down_phy(hw);
649 em_dev_clear_queues(dev);
651 /* clear the recorded link status */
652 memset(&link, 0, sizeof(link));
653 rte_em_dev_atomic_write_link_status(dev, &link);
657 eth_em_close(struct rte_eth_dev *dev)
659 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
660 struct e1000_adapter *adapter =
661 E1000_DEV_PRIVATE(dev->data->dev_private);
664 adapter->stopped = 1;
665 em_dev_free_queues(dev);
666 e1000_phy_hw_reset(hw);
667 em_release_manageability(hw);
668 em_hw_control_release(hw);
672 em_get_rx_buffer_size(struct e1000_hw *hw)
674 uint32_t rx_buf_size;
676 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
680 /*********************************************************************
682 * Initialize the hardware
684 **********************************************************************/
686 em_hardware_init(struct e1000_hw *hw)
688 uint32_t rx_buf_size;
691 /* Issue a global reset */
694 /* Let the firmware know the OS is in control */
695 em_hw_control_acquire(hw);
698 * These parameters control the automatic generation (Tx) and
699 * response (Rx) to Ethernet PAUSE frames.
700 * - High water mark should allow for at least two standard size (1518)
701 * frames to be received after sending an XOFF.
702 * - Low water mark works best when it is very near the high water mark.
703 * This allows the receiver to restart by sending XON when it has
704 * drained a bit. Here we use an arbitrary value of 1500 which will
705 * restart after one full frame is pulled from the buffer. There
706 * could be several smaller frames in the buffer and if so they will
707 * not trigger the XON until their total number reduces the buffer
709 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
711 rx_buf_size = em_get_rx_buffer_size(hw);
713 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
714 hw->fc.low_water = hw->fc.high_water - 1500;
716 if (hw->mac.type == e1000_80003es2lan)
717 hw->fc.pause_time = UINT16_MAX;
719 hw->fc.pause_time = EM_FC_PAUSE_TIME;
723 /* Set Flow control, use the tunable location if sane */
724 if (em_fc_setting <= e1000_fc_full)
725 hw->fc.requested_mode = em_fc_setting;
727 hw->fc.requested_mode = e1000_fc_none;
729 /* Workaround: no TX flow ctrl for PCH */
730 if (hw->mac.type == e1000_pchlan)
731 hw->fc.requested_mode = e1000_fc_rx_pause;
733 /* Override - settings for PCH2LAN, ya its magic :) */
734 if (hw->mac.type == e1000_pch2lan) {
735 hw->fc.high_water = 0x5C20;
736 hw->fc.low_water = 0x5048;
737 hw->fc.pause_time = 0x0650;
738 hw->fc.refresh_time = 0x0400;
741 diag = e1000_init_hw(hw);
744 e1000_check_for_link(hw);
748 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
750 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
752 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
753 struct e1000_hw_stats *stats =
754 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
757 if(hw->phy.media_type == e1000_media_type_copper ||
758 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
759 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
760 stats->sec += E1000_READ_REG(hw, E1000_SEC);
763 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
764 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
765 stats->scc += E1000_READ_REG(hw, E1000_SCC);
766 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
768 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
769 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
770 stats->colc += E1000_READ_REG(hw, E1000_COLC);
771 stats->dc += E1000_READ_REG(hw, E1000_DC);
772 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
773 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
774 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
777 * For watchdog management we need to know if we have been
778 * paused during the last interval, so capture that here.
780 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
781 stats->xoffrxc += pause_frames;
782 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
783 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
784 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
785 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
786 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
787 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
788 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
789 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
790 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
791 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
792 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
793 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
796 * For the 64-bit byte counters the low dword must be read first.
797 * Both registers clear on the read of the high dword.
800 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
801 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
802 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
803 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
805 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
806 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
807 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
808 stats->roc += E1000_READ_REG(hw, E1000_ROC);
809 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
811 stats->tor += E1000_READ_REG(hw, E1000_TORH);
812 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
814 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
815 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
816 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
817 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
818 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
819 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
820 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
821 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
822 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
823 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
825 /* Interrupt Counts */
827 if (hw->mac.type >= e1000_82571) {
828 stats->iac += E1000_READ_REG(hw, E1000_IAC);
829 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
830 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
831 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
832 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
833 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
834 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
835 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
836 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
839 if (hw->mac.type >= e1000_82543) {
840 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
841 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
842 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
843 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
844 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
845 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
848 if (rte_stats == NULL)
852 rte_stats->ibadcrc = stats->crcerrs;
853 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
854 rte_stats->imissed = stats->mpc;
855 rte_stats->ierrors = rte_stats->ibadcrc +
858 stats->rxerrc + stats->algnerrc + stats->cexterr;
861 rte_stats->oerrors = stats->ecol + stats->latecol;
863 rte_stats->ipackets = stats->gprc;
864 rte_stats->opackets = stats->gptc;
865 rte_stats->ibytes = stats->gorc;
866 rte_stats->obytes = stats->gotc;
868 /* XON/XOFF pause frames stats registers */
869 rte_stats->tx_pause_xon = stats->xontxc;
870 rte_stats->rx_pause_xon = stats->xonrxc;
871 rte_stats->tx_pause_xoff = stats->xofftxc;
872 rte_stats->rx_pause_xoff = stats->xoffrxc;
876 eth_em_stats_reset(struct rte_eth_dev *dev)
878 struct e1000_hw_stats *hw_stats =
879 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
881 /* HW registers are cleared on read */
882 eth_em_stats_get(dev, NULL);
884 /* Reset software totals */
885 memset(hw_stats, 0, sizeof(*hw_stats));
889 em_get_max_pktlen(const struct e1000_hw *hw)
891 switch (hw->mac.type) {
898 case e1000_80003es2lan: /* 9K Jumbo Frame size */
903 /* Adapters that do not support jumbo frames */
905 return (ETHER_MAX_LEN);
907 return (MAX_JUMBO_FRAME_SIZE);
912 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
914 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
916 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
917 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
918 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
921 * Starting with 631xESB hw supports 2 TX/RX queues per port.
922 * Unfortunatelly, all these nics have just one TX context.
923 * So we have few choises for TX:
924 * - Use just one TX queue.
925 * - Allow cksum offload only for one TX queue.
926 * - Don't allow TX cksum offload at all.
927 * For now, option #1 was chosen.
928 * To use second RX queue we have to use extended RX descriptor
929 * (Multiple Receive Queues are mutually exclusive with UDP
930 * fragmentation and are not supported when a legacy receive
931 * descriptor format is used).
932 * Which means separate RX routinies - as legacy nics (82540, 82545)
933 * don't support extended RXD.
934 * To avoid it we support just one RX queue for now (no RSS).
937 dev_info->max_rx_queues = 1;
938 dev_info->max_tx_queues = 1;
941 /* return 0 means link status changed, -1 means not changed */
943 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
945 struct e1000_hw *hw =
946 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
947 struct rte_eth_link link, old;
948 int link_check, count;
951 hw->mac.get_link_status = 1;
953 /* possible wait-to-complete in up to 9 seconds */
954 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
955 /* Read the real link status */
956 switch (hw->phy.media_type) {
957 case e1000_media_type_copper:
958 /* Do the work to read phy */
959 e1000_check_for_link(hw);
960 link_check = !hw->mac.get_link_status;
963 case e1000_media_type_fiber:
964 e1000_check_for_link(hw);
965 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
969 case e1000_media_type_internal_serdes:
970 e1000_check_for_link(hw);
971 link_check = hw->mac.serdes_has_link;
977 if (link_check || wait_to_complete == 0)
979 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
981 memset(&link, 0, sizeof(link));
982 rte_em_dev_atomic_read_link_status(dev, &link);
985 /* Now we check if a transition has happened */
986 if (link_check && (link.link_status == 0)) {
987 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
989 link.link_status = 1;
990 } else if (!link_check && (link.link_status == 1)) {
992 link.link_duplex = 0;
993 link.link_status = 0;
995 rte_em_dev_atomic_write_link_status(dev, &link);
998 if (old.link_status == link.link_status)
1006 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1007 * For ASF and Pass Through versions of f/w this means
1008 * that the driver is loaded. For AMT version type f/w
1009 * this means that the network i/f is open.
1012 em_hw_control_acquire(struct e1000_hw *hw)
1014 uint32_t ctrl_ext, swsm;
1016 /* Let firmware know the driver has taken over */
1017 if (hw->mac.type == e1000_82573) {
1018 swsm = E1000_READ_REG(hw, E1000_SWSM);
1019 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1022 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1023 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1024 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1029 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1030 * For ASF and Pass Through versions of f/w this means that the
1031 * driver is no longer loaded. For AMT versions of the
1032 * f/w this means that the network i/f is closed.
1035 em_hw_control_release(struct e1000_hw *hw)
1037 uint32_t ctrl_ext, swsm;
1039 /* Let firmware taken over control of h/w */
1040 if (hw->mac.type == e1000_82573) {
1041 swsm = E1000_READ_REG(hw, E1000_SWSM);
1042 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1044 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1045 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1046 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1051 * Bit of a misnomer, what this really means is
1052 * to enable OS management of the system... aka
1053 * to disable special hardware management features.
1056 em_init_manageability(struct e1000_hw *hw)
1058 if (e1000_enable_mng_pass_thru(hw)) {
1059 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1060 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1062 /* disable hardware interception of ARP */
1063 manc &= ~(E1000_MANC_ARP_EN);
1065 /* enable receiving management packets to the host */
1066 manc |= E1000_MANC_EN_MNG2HOST;
1067 manc2h |= 1 << 5; /* Mng Port 623 */
1068 manc2h |= 1 << 6; /* Mng Port 664 */
1069 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1070 E1000_WRITE_REG(hw, E1000_MANC, manc);
1075 * Give control back to hardware management
1076 * controller if there is one.
1079 em_release_manageability(struct e1000_hw *hw)
1083 if (e1000_enable_mng_pass_thru(hw)) {
1084 manc = E1000_READ_REG(hw, E1000_MANC);
1086 /* re-enable hardware interception of ARP */
1087 manc |= E1000_MANC_ARP_EN;
1088 manc &= ~E1000_MANC_EN_MNG2HOST;
1090 E1000_WRITE_REG(hw, E1000_MANC, manc);
1095 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1097 struct e1000_hw *hw =
1098 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101 rctl = E1000_READ_REG(hw, E1000_RCTL);
1102 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1103 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1107 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1109 struct e1000_hw *hw =
1110 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1113 rctl = E1000_READ_REG(hw, E1000_RCTL);
1114 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1115 if (dev->data->all_multicast == 1)
1116 rctl |= E1000_RCTL_MPE;
1118 rctl &= (~E1000_RCTL_MPE);
1119 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1123 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1125 struct e1000_hw *hw =
1126 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1129 rctl = E1000_READ_REG(hw, E1000_RCTL);
1130 rctl |= E1000_RCTL_MPE;
1131 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1135 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1137 struct e1000_hw *hw =
1138 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1141 if (dev->data->promiscuous == 1)
1142 return; /* must remain in all_multicast mode */
1143 rctl = E1000_READ_REG(hw, E1000_RCTL);
1144 rctl &= (~E1000_RCTL_MPE);
1145 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1149 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1151 struct e1000_hw *hw =
1152 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1153 struct e1000_vfta * shadow_vfta =
1154 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1159 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1160 E1000_VFTA_ENTRY_MASK);
1161 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1162 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1167 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1169 /* update local VFTA copy */
1170 shadow_vfta->vfta[vid_idx] = vfta;
1176 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1178 struct e1000_hw *hw =
1179 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1182 /* Filter Table Disable */
1183 reg = E1000_READ_REG(hw, E1000_RCTL);
1184 reg &= ~E1000_RCTL_CFIEN;
1185 reg &= ~E1000_RCTL_VFE;
1186 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1190 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1192 struct e1000_hw *hw =
1193 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1194 struct e1000_vfta * shadow_vfta =
1195 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1199 /* Filter Table Enable, CFI not used for packet acceptance */
1200 reg = E1000_READ_REG(hw, E1000_RCTL);
1201 reg &= ~E1000_RCTL_CFIEN;
1202 reg |= E1000_RCTL_VFE;
1203 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1205 /* restore vfta from local copy */
1206 for (i = 0; i < IGB_VFTA_SIZE; i++)
1207 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1211 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1213 struct e1000_hw *hw =
1214 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217 /* VLAN Mode Disable */
1218 reg = E1000_READ_REG(hw, E1000_CTRL);
1219 reg &= ~E1000_CTRL_VME;
1220 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1225 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1227 struct e1000_hw *hw =
1228 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231 /* VLAN Mode Enable */
1232 reg = E1000_READ_REG(hw, E1000_CTRL);
1233 reg |= E1000_CTRL_VME;
1234 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1238 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1240 if(mask & ETH_VLAN_STRIP_MASK){
1241 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1242 em_vlan_hw_strip_enable(dev);
1244 em_vlan_hw_strip_disable(dev);
1247 if(mask & ETH_VLAN_FILTER_MASK){
1248 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1249 em_vlan_hw_filter_enable(dev);
1251 em_vlan_hw_filter_disable(dev);
1256 * It enables the interrupt mask and then enable the interrupt.
1259 * Pointer to struct rte_eth_dev.
1262 * - On success, zero.
1263 * - On failure, a negative value.
1266 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1269 struct e1000_hw *hw =
1270 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1272 /* clear interrupt */
1273 E1000_READ_REG(hw, E1000_ICR);
1274 regval = E1000_READ_REG(hw, E1000_IMS);
1275 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1280 * It disabled lsc interrupt.
1282 * Pointer to struct e1000_hw
1287 em_lsc_intr_disable(struct e1000_hw *hw)
1289 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1290 E1000_WRITE_FLUSH(hw);
1294 * It disabled receive packet interrupt.
1296 * Pointer to struct e1000_hw
1301 em_rxq_intr_disable(struct e1000_hw *hw)
1303 E1000_READ_REG(hw, E1000_ICR);
1304 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1305 E1000_WRITE_FLUSH(hw);
1309 * It reads ICR and gets interrupt causes, check it and set a bit flag
1310 * to update link status.
1313 * Pointer to struct rte_eth_dev.
1316 * - On success, zero.
1317 * - On failure, a negative value.
1320 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1323 struct e1000_hw *hw =
1324 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1325 struct e1000_interrupt *intr =
1326 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1328 /* read-on-clear nic registers here */
1329 icr = E1000_READ_REG(hw, E1000_ICR);
1330 if (icr & E1000_ICR_LSC) {
1331 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1338 * It executes link_update after knowing an interrupt is prsent.
1341 * Pointer to struct rte_eth_dev.
1344 * - On success, zero.
1345 * - On failure, a negative value.
1348 eth_em_interrupt_action(struct rte_eth_dev *dev)
1350 struct e1000_hw *hw =
1351 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352 struct e1000_interrupt *intr =
1353 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1354 uint32_t tctl, rctl;
1355 struct rte_eth_link link;
1358 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1361 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1362 rte_intr_enable(&(dev->pci_dev->intr_handle));
1364 /* set get_link_status to check register later */
1365 hw->mac.get_link_status = 1;
1366 ret = eth_em_link_update(dev, 0);
1368 /* check if link has changed */
1372 memset(&link, 0, sizeof(link));
1373 rte_em_dev_atomic_read_link_status(dev, &link);
1374 if (link.link_status) {
1375 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1376 dev->data->port_id, (unsigned)link.link_speed,
1377 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1378 "full-duplex" : "half-duplex");
1380 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1382 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1383 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1384 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1386 tctl = E1000_READ_REG(hw, E1000_TCTL);
1387 rctl = E1000_READ_REG(hw, E1000_RCTL);
1388 if (link.link_status) {
1390 tctl |= E1000_TCTL_EN;
1391 rctl |= E1000_RCTL_EN;
1394 tctl &= ~E1000_TCTL_EN;
1395 rctl &= ~E1000_RCTL_EN;
1397 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1398 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1399 E1000_WRITE_FLUSH(hw);
1405 * Interrupt handler which shall be registered at first.
1408 * Pointer to interrupt handle.
1410 * The address of parameter (struct rte_eth_dev *) regsitered before.
1416 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1419 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1421 eth_em_interrupt_get_status(dev);
1422 eth_em_interrupt_action(dev);
1423 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1427 eth_em_led_on(struct rte_eth_dev *dev)
1429 struct e1000_hw *hw;
1431 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1432 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1436 eth_em_led_off(struct rte_eth_dev *dev)
1438 struct e1000_hw *hw;
1440 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1441 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1445 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1447 struct e1000_hw *hw;
1452 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453 fc_conf->pause_time = hw->fc.pause_time;
1454 fc_conf->high_water = hw->fc.high_water;
1455 fc_conf->low_water = hw->fc.low_water;
1456 fc_conf->send_xon = hw->fc.send_xon;
1457 fc_conf->autoneg = hw->mac.autoneg;
1460 * Return rx_pause and tx_pause status according to actual setting of
1461 * the TFCE and RFCE bits in the CTRL register.
1463 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1464 if (ctrl & E1000_CTRL_TFCE)
1469 if (ctrl & E1000_CTRL_RFCE)
1474 if (rx_pause && tx_pause)
1475 fc_conf->mode = RTE_FC_FULL;
1477 fc_conf->mode = RTE_FC_RX_PAUSE;
1479 fc_conf->mode = RTE_FC_TX_PAUSE;
1481 fc_conf->mode = RTE_FC_NONE;
1487 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1489 struct e1000_hw *hw;
1491 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1497 uint32_t rx_buf_size;
1498 uint32_t max_high_water;
1501 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1502 if (fc_conf->autoneg != hw->mac.autoneg)
1504 rx_buf_size = em_get_rx_buffer_size(hw);
1505 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1507 /* At least reserve one Ethernet frame for watermark */
1508 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1509 if ((fc_conf->high_water > max_high_water) ||
1510 (fc_conf->high_water < fc_conf->low_water)) {
1511 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1512 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1516 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1517 hw->fc.pause_time = fc_conf->pause_time;
1518 hw->fc.high_water = fc_conf->high_water;
1519 hw->fc.low_water = fc_conf->low_water;
1520 hw->fc.send_xon = fc_conf->send_xon;
1522 err = e1000_setup_link_generic(hw);
1523 if (err == E1000_SUCCESS) {
1525 /* check if we want to forward MAC frames - driver doesn't have native
1526 * capability to do that, so we'll write the registers ourselves */
1528 rctl = E1000_READ_REG(hw, E1000_RCTL);
1530 /* set or clear MFLCN.PMCF bit depending on configuration */
1531 if (fc_conf->mac_ctrl_frame_fwd != 0)
1532 rctl |= E1000_RCTL_PMCF;
1534 rctl &= ~E1000_RCTL_PMCF;
1536 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1537 E1000_WRITE_FLUSH(hw);
1542 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1547 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1548 uint32_t index, __rte_unused uint32_t pool)
1550 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1552 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1556 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1558 uint8_t addr[ETHER_ADDR_LEN];
1559 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561 memset(addr, 0, sizeof(addr));
1563 e1000_rar_set(hw, addr, index);
1567 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1569 struct rte_eth_dev_info dev_info;
1570 struct e1000_hw *hw;
1571 uint32_t frame_size;
1574 eth_em_infos_get(dev, &dev_info);
1575 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1577 /* check that mtu is within the allowed range */
1578 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1581 /* refuse mtu that requires the support of scattered packets when this
1582 * feature has not been enabled before. */
1583 if (!dev->data->scattered_rx &&
1584 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1587 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588 rctl = E1000_READ_REG(hw, E1000_RCTL);
1590 /* switch to jumbo mode if needed */
1591 if (frame_size > ETHER_MAX_LEN) {
1592 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1593 rctl |= E1000_RCTL_LPE;
1595 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1596 rctl &= ~E1000_RCTL_LPE;
1598 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1600 /* update max frame size */
1601 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1606 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1607 struct ether_addr *mc_addr_set,
1608 uint32_t nb_mc_addr)
1610 struct e1000_hw *hw;
1612 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1617 struct rte_driver em_pmd_drv = {
1619 .init = rte_em_pmd_init,
1622 PMD_REGISTER_DRIVER(em_pmd_drv);