net/e1000: fix MAC type checking
[dpdk.git] / drivers / net / e1000 / em_ethdev.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2016 Intel Corporation
3  */
4
5 #include <sys/queue.h>
6 #include <stdio.h>
7 #include <errno.h>
8 #include <stdint.h>
9 #include <stdarg.h>
10
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
14 #include <rte_debug.h>
15 #include <rte_pci.h>
16 #include <rte_bus_pci.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_ethdev_pci.h>
20 #include <rte_memory.h>
21 #include <rte_eal.h>
22 #include <rte_malloc.h>
23 #include <rte_dev.h>
24
25 #include "e1000_logs.h"
26 #include "base/e1000_api.h"
27 #include "e1000_ethdev.h"
28
29 #define EM_EIAC                 0x000DC
30
31 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
32
33
34 static int eth_em_configure(struct rte_eth_dev *dev);
35 static int eth_em_start(struct rte_eth_dev *dev);
36 static void eth_em_stop(struct rte_eth_dev *dev);
37 static void eth_em_close(struct rte_eth_dev *dev);
38 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
39 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
40 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
41 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
42 static int eth_em_link_update(struct rte_eth_dev *dev,
43                                 int wait_to_complete);
44 static int eth_em_stats_get(struct rte_eth_dev *dev,
45                                 struct rte_eth_stats *rte_stats);
46 static void eth_em_stats_reset(struct rte_eth_dev *dev);
47 static void eth_em_infos_get(struct rte_eth_dev *dev,
48                                 struct rte_eth_dev_info *dev_info);
49 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
50                                 struct rte_eth_fc_conf *fc_conf);
51 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
52                                 struct rte_eth_fc_conf *fc_conf);
53 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
54 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
55 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
56 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
57                                    struct rte_intr_handle *handle);
58 static void eth_em_interrupt_handler(void *param);
59
60 static int em_hw_init(struct e1000_hw *hw);
61 static int em_hardware_init(struct e1000_hw *hw);
62 static void em_hw_control_acquire(struct e1000_hw *hw);
63 static void em_hw_control_release(struct e1000_hw *hw);
64 static void em_init_manageability(struct e1000_hw *hw);
65 static void em_release_manageability(struct e1000_hw *hw);
66
67 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
68
69 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
70                 uint16_t vlan_id, int on);
71 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
72 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
73 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
74 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
75 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
76
77 /*
78 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
79                                         uint16_t vlan_id, int on);
80 */
81
82 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
83 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
84 static void em_lsc_intr_disable(struct e1000_hw *hw);
85 static void em_rxq_intr_enable(struct e1000_hw *hw);
86 static void em_rxq_intr_disable(struct e1000_hw *hw);
87
88 static int eth_em_led_on(struct rte_eth_dev *dev);
89 static int eth_em_led_off(struct rte_eth_dev *dev);
90
91 static int em_get_rx_buffer_size(struct e1000_hw *hw);
92 static int eth_em_rar_set(struct rte_eth_dev *dev,
93                         struct rte_ether_addr *mac_addr,
94                         uint32_t index, uint32_t pool);
95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
96 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
97                                          struct rte_ether_addr *addr);
98
99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
100                                    struct rte_ether_addr *mc_addr_set,
101                                    uint32_t nb_mc_addr);
102
103 #define EM_FC_PAUSE_TIME 0x0680
104 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
106
107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
108
109 /*
110  * The set of PCI devices this driver supports
111  */
112 static const struct rte_pci_id pci_id_em_map[] = {
113         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
114         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
158         { .vendor_id = 0, /* sentinel */ },
159 };
160
161 static const struct eth_dev_ops eth_em_ops = {
162         .dev_configure        = eth_em_configure,
163         .dev_start            = eth_em_start,
164         .dev_stop             = eth_em_stop,
165         .dev_close            = eth_em_close,
166         .promiscuous_enable   = eth_em_promiscuous_enable,
167         .promiscuous_disable  = eth_em_promiscuous_disable,
168         .allmulticast_enable  = eth_em_allmulticast_enable,
169         .allmulticast_disable = eth_em_allmulticast_disable,
170         .link_update          = eth_em_link_update,
171         .stats_get            = eth_em_stats_get,
172         .stats_reset          = eth_em_stats_reset,
173         .dev_infos_get        = eth_em_infos_get,
174         .mtu_set              = eth_em_mtu_set,
175         .vlan_filter_set      = eth_em_vlan_filter_set,
176         .vlan_offload_set     = eth_em_vlan_offload_set,
177         .rx_queue_setup       = eth_em_rx_queue_setup,
178         .rx_queue_release     = eth_em_rx_queue_release,
179         .rx_queue_count       = eth_em_rx_queue_count,
180         .rx_descriptor_done   = eth_em_rx_descriptor_done,
181         .rx_descriptor_status = eth_em_rx_descriptor_status,
182         .tx_descriptor_status = eth_em_tx_descriptor_status,
183         .tx_queue_setup       = eth_em_tx_queue_setup,
184         .tx_queue_release     = eth_em_tx_queue_release,
185         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
186         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
187         .dev_led_on           = eth_em_led_on,
188         .dev_led_off          = eth_em_led_off,
189         .flow_ctrl_get        = eth_em_flow_ctrl_get,
190         .flow_ctrl_set        = eth_em_flow_ctrl_set,
191         .mac_addr_set         = eth_em_default_mac_addr_set,
192         .mac_addr_add         = eth_em_rar_set,
193         .mac_addr_remove      = eth_em_rar_clear,
194         .set_mc_addr_list     = eth_em_set_mc_addr_list,
195         .rxq_info_get         = em_rxq_info_get,
196         .txq_info_get         = em_txq_info_get,
197 };
198
199
200 /**
201  *  eth_em_dev_is_ich8 - Check for ICH8 device
202  *  @hw: pointer to the HW structure
203  *
204  *  return TRUE for ICH8, otherwise FALSE
205  **/
206 static bool
207 eth_em_dev_is_ich8(struct e1000_hw *hw)
208 {
209         DEBUGFUNC("eth_em_dev_is_ich8");
210
211         switch (hw->device_id) {
212         case E1000_DEV_ID_PCH2_LV_LM:
213         case E1000_DEV_ID_PCH_LPT_I217_LM:
214         case E1000_DEV_ID_PCH_LPT_I217_V:
215         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
216         case E1000_DEV_ID_PCH_LPTLP_I218_V:
217         case E1000_DEV_ID_PCH_I218_V2:
218         case E1000_DEV_ID_PCH_I218_LM2:
219         case E1000_DEV_ID_PCH_I218_V3:
220         case E1000_DEV_ID_PCH_I218_LM3:
221         case E1000_DEV_ID_PCH_SPT_I219_LM:
222         case E1000_DEV_ID_PCH_SPT_I219_V:
223         case E1000_DEV_ID_PCH_SPT_I219_LM2:
224         case E1000_DEV_ID_PCH_SPT_I219_V2:
225         case E1000_DEV_ID_PCH_LBG_I219_LM3:
226         case E1000_DEV_ID_PCH_SPT_I219_LM4:
227         case E1000_DEV_ID_PCH_SPT_I219_V4:
228         case E1000_DEV_ID_PCH_SPT_I219_LM5:
229         case E1000_DEV_ID_PCH_SPT_I219_V5:
230         case E1000_DEV_ID_PCH_CNP_I219_LM6:
231         case E1000_DEV_ID_PCH_CNP_I219_V6:
232         case E1000_DEV_ID_PCH_CNP_I219_LM7:
233         case E1000_DEV_ID_PCH_CNP_I219_V7:
234                 return 1;
235         default:
236                 return 0;
237         }
238 }
239
240 static int
241 eth_em_dev_init(struct rte_eth_dev *eth_dev)
242 {
243         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
244         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
245         struct e1000_adapter *adapter =
246                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
247         struct e1000_hw *hw =
248                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
249         struct e1000_vfta * shadow_vfta =
250                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
251
252         eth_dev->dev_ops = &eth_em_ops;
253         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
254         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
255         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
256
257         /* for secondary processes, we don't initialise any further as primary
258          * has already done this work. Only check we don't need a different
259          * RX function */
260         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
261                 if (eth_dev->data->scattered_rx)
262                         eth_dev->rx_pkt_burst =
263                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
264                 return 0;
265         }
266
267         rte_eth_copy_pci_info(eth_dev, pci_dev);
268
269         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
270         hw->device_id = pci_dev->id.device_id;
271         adapter->stopped = 0;
272
273         /* For ICH8 support we'll need to map the flash memory BAR */
274         if (eth_em_dev_is_ich8(hw))
275                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
276
277         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
278                         em_hw_init(hw) != 0) {
279                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
280                         "failed to init HW",
281                         eth_dev->data->port_id, pci_dev->id.vendor_id,
282                         pci_dev->id.device_id);
283                 return -ENODEV;
284         }
285
286         /* Allocate memory for storing MAC addresses */
287         eth_dev->data->mac_addrs = rte_zmalloc("e1000", RTE_ETHER_ADDR_LEN *
288                         hw->mac.rar_entry_count, 0);
289         if (eth_dev->data->mac_addrs == NULL) {
290                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
291                         "store MAC addresses",
292                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
293                 return -ENOMEM;
294         }
295
296         /* Copy the permanent MAC address */
297         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
298                 eth_dev->data->mac_addrs);
299
300         /* initialize the vfta */
301         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
302
303         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
304                      eth_dev->data->port_id, pci_dev->id.vendor_id,
305                      pci_dev->id.device_id);
306
307         rte_intr_callback_register(intr_handle,
308                                    eth_em_interrupt_handler, eth_dev);
309
310         return 0;
311 }
312
313 static int
314 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
315 {
316         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
317         struct e1000_adapter *adapter =
318                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
319         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
320
321         PMD_INIT_FUNC_TRACE();
322
323         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
324                 return -EPERM;
325
326         if (adapter->stopped == 0)
327                 eth_em_close(eth_dev);
328
329         eth_dev->dev_ops = NULL;
330         eth_dev->rx_pkt_burst = NULL;
331         eth_dev->tx_pkt_burst = NULL;
332
333         /* disable uio intr before callback unregister */
334         rte_intr_disable(intr_handle);
335         rte_intr_callback_unregister(intr_handle,
336                                      eth_em_interrupt_handler, eth_dev);
337
338         return 0;
339 }
340
341 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
342         struct rte_pci_device *pci_dev)
343 {
344         return rte_eth_dev_pci_generic_probe(pci_dev,
345                 sizeof(struct e1000_adapter), eth_em_dev_init);
346 }
347
348 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
349 {
350         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
351 }
352
353 static struct rte_pci_driver rte_em_pmd = {
354         .id_table = pci_id_em_map,
355         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
356         .probe = eth_em_pci_probe,
357         .remove = eth_em_pci_remove,
358 };
359
360 static int
361 em_hw_init(struct e1000_hw *hw)
362 {
363         int diag;
364
365         diag = hw->mac.ops.init_params(hw);
366         if (diag != 0) {
367                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
368                 return diag;
369         }
370         diag = hw->nvm.ops.init_params(hw);
371         if (diag != 0) {
372                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
373                 return diag;
374         }
375         diag = hw->phy.ops.init_params(hw);
376         if (diag != 0) {
377                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
378                 return diag;
379         }
380         (void) e1000_get_bus_info(hw);
381
382         hw->mac.autoneg = 1;
383         hw->phy.autoneg_wait_to_complete = 0;
384         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
385
386         e1000_init_script_state_82541(hw, TRUE);
387         e1000_set_tbi_compatibility_82543(hw, TRUE);
388
389         /* Copper options */
390         if (hw->phy.media_type == e1000_media_type_copper) {
391                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
392                 hw->phy.disable_polarity_correction = 0;
393                 hw->phy.ms_type = e1000_ms_hw_default;
394         }
395
396         /*
397          * Start from a known state, this is important in reading the nvm
398          * and mac from that.
399          */
400         e1000_reset_hw(hw);
401
402         /* Make sure we have a good EEPROM before we read from it */
403         if (e1000_validate_nvm_checksum(hw) < 0) {
404                 /*
405                  * Some PCI-E parts fail the first check due to
406                  * the link being in sleep state, call it again,
407                  * if it fails a second time its a real issue.
408                  */
409                 diag = e1000_validate_nvm_checksum(hw);
410                 if (diag < 0) {
411                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
412                         goto error;
413                 }
414         }
415
416         /* Read the permanent MAC address out of the EEPROM */
417         diag = e1000_read_mac_addr(hw);
418         if (diag != 0) {
419                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
420                 goto error;
421         }
422
423         /* Now initialize the hardware */
424         diag = em_hardware_init(hw);
425         if (diag != 0) {
426                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
427                 goto error;
428         }
429
430         hw->mac.get_link_status = 1;
431
432         /* Indicate SOL/IDER usage */
433         diag = e1000_check_reset_block(hw);
434         if (diag < 0) {
435                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
436                         "SOL/IDER session");
437         }
438         return 0;
439
440 error:
441         em_hw_control_release(hw);
442         return diag;
443 }
444
445 static int
446 eth_em_configure(struct rte_eth_dev *dev)
447 {
448         struct e1000_interrupt *intr =
449                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
450
451         PMD_INIT_FUNC_TRACE();
452         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
453
454         PMD_INIT_FUNC_TRACE();
455
456         return 0;
457 }
458
459 static void
460 em_set_pba(struct e1000_hw *hw)
461 {
462         uint32_t pba;
463
464         /*
465          * Packet Buffer Allocation (PBA)
466          * Writing PBA sets the receive portion of the buffer
467          * the remainder is used for the transmit buffer.
468          * Devices before the 82547 had a Packet Buffer of 64K.
469          * After the 82547 the buffer was reduced to 40K.
470          */
471         switch (hw->mac.type) {
472                 case e1000_82547:
473                 case e1000_82547_rev_2:
474                 /* 82547: Total Packet Buffer is 40K */
475                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
476                         break;
477                 case e1000_82571:
478                 case e1000_82572:
479                 case e1000_80003es2lan:
480                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
481                         break;
482                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
483                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
484                         break;
485                 case e1000_82574:
486                 case e1000_82583:
487                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
488                         break;
489                 case e1000_ich8lan:
490                         pba = E1000_PBA_8K;
491                         break;
492                 case e1000_ich9lan:
493                 case e1000_ich10lan:
494                         pba = E1000_PBA_10K;
495                         break;
496                 case e1000_pchlan:
497                 case e1000_pch2lan:
498                 case e1000_pch_lpt:
499                 case e1000_pch_spt:
500                 case e1000_pch_cnp:
501                         pba = E1000_PBA_26K;
502                         break;
503                 default:
504                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
505         }
506
507         E1000_WRITE_REG(hw, E1000_PBA, pba);
508 }
509
510 static void
511 eth_em_rxtx_control(struct rte_eth_dev *dev,
512                     bool enable)
513 {
514         struct e1000_hw *hw =
515                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
516         uint32_t tctl, rctl;
517
518         tctl = E1000_READ_REG(hw, E1000_TCTL);
519         rctl = E1000_READ_REG(hw, E1000_RCTL);
520         if (enable) {
521                 /* enable Tx/Rx */
522                 tctl |= E1000_TCTL_EN;
523                 rctl |= E1000_RCTL_EN;
524         } else {
525                 /* disable Tx/Rx */
526                 tctl &= ~E1000_TCTL_EN;
527                 rctl &= ~E1000_RCTL_EN;
528         }
529         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
530         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
531         E1000_WRITE_FLUSH(hw);
532 }
533
534 static int
535 eth_em_start(struct rte_eth_dev *dev)
536 {
537         struct e1000_adapter *adapter =
538                 E1000_DEV_PRIVATE(dev->data->dev_private);
539         struct e1000_hw *hw =
540                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
541         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
543         int ret, mask;
544         uint32_t intr_vector = 0;
545         uint32_t *speeds;
546         int num_speeds;
547         bool autoneg;
548
549         PMD_INIT_FUNC_TRACE();
550
551         eth_em_stop(dev);
552
553         e1000_power_up_phy(hw);
554
555         /* Set default PBA value */
556         em_set_pba(hw);
557
558         /* Put the address into the Receive Address Array */
559         e1000_rar_set(hw, hw->mac.addr, 0);
560
561         /*
562          * With the 82571 adapter, RAR[0] may be overwritten
563          * when the other port is reset, we make a duplicate
564          * in RAR[14] for that eventuality, this assures
565          * the interface continues to function.
566          */
567         if (hw->mac.type == e1000_82571) {
568                 e1000_set_laa_state_82571(hw, TRUE);
569                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
570         }
571
572         /* Initialize the hardware */
573         if (em_hardware_init(hw)) {
574                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
575                 return -EIO;
576         }
577
578         E1000_WRITE_REG(hw, E1000_VET, RTE_ETHER_TYPE_VLAN);
579
580         /* Configure for OS presence */
581         em_init_manageability(hw);
582
583         if (dev->data->dev_conf.intr_conf.rxq != 0) {
584                 intr_vector = dev->data->nb_rx_queues;
585                 if (rte_intr_efd_enable(intr_handle, intr_vector))
586                         return -1;
587         }
588
589         if (rte_intr_dp_is_en(intr_handle)) {
590                 intr_handle->intr_vec =
591                         rte_zmalloc("intr_vec",
592                                         dev->data->nb_rx_queues * sizeof(int), 0);
593                 if (intr_handle->intr_vec == NULL) {
594                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
595                                                 " intr_vec", dev->data->nb_rx_queues);
596                         return -ENOMEM;
597                 }
598
599                 /* enable rx interrupt */
600                 em_rxq_intr_enable(hw);
601         }
602
603         eth_em_tx_init(dev);
604
605         ret = eth_em_rx_init(dev);
606         if (ret) {
607                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
608                 em_dev_clear_queues(dev);
609                 return ret;
610         }
611
612         e1000_clear_hw_cntrs_base_generic(hw);
613
614         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
615                         ETH_VLAN_EXTEND_MASK;
616         ret = eth_em_vlan_offload_set(dev, mask);
617         if (ret) {
618                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
619                 em_dev_clear_queues(dev);
620                 return ret;
621         }
622
623         /* Set Interrupt Throttling Rate to maximum allowed value. */
624         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
625
626         /* Setup link speed and duplex */
627         speeds = &dev->data->dev_conf.link_speeds;
628         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
629                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
630                 hw->mac.autoneg = 1;
631         } else {
632                 num_speeds = 0;
633                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
634
635                 /* Reset */
636                 hw->phy.autoneg_advertised = 0;
637
638                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
639                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
640                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
641                         num_speeds = -1;
642                         goto error_invalid_config;
643                 }
644                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
645                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
646                         num_speeds++;
647                 }
648                 if (*speeds & ETH_LINK_SPEED_10M) {
649                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
650                         num_speeds++;
651                 }
652                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
653                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
654                         num_speeds++;
655                 }
656                 if (*speeds & ETH_LINK_SPEED_100M) {
657                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
658                         num_speeds++;
659                 }
660                 if (*speeds & ETH_LINK_SPEED_1G) {
661                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
662                         num_speeds++;
663                 }
664                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
665                         goto error_invalid_config;
666
667                 /* Set/reset the mac.autoneg based on the link speed,
668                  * fixed or not
669                  */
670                 if (!autoneg) {
671                         hw->mac.autoneg = 0;
672                         hw->mac.forced_speed_duplex =
673                                         hw->phy.autoneg_advertised;
674                 } else {
675                         hw->mac.autoneg = 1;
676                 }
677         }
678
679         e1000_setup_link(hw);
680
681         if (rte_intr_allow_others(intr_handle)) {
682                 /* check if lsc interrupt is enabled */
683                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
684                         ret = eth_em_interrupt_setup(dev);
685                         if (ret) {
686                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
687                                 em_dev_clear_queues(dev);
688                                 return ret;
689                         }
690                 }
691         } else {
692                 rte_intr_callback_unregister(intr_handle,
693                                                 eth_em_interrupt_handler,
694                                                 (void *)dev);
695                 if (dev->data->dev_conf.intr_conf.lsc != 0)
696                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
697                                      " no intr multiplexn");
698         }
699         /* check if rxq interrupt is enabled */
700         if (dev->data->dev_conf.intr_conf.rxq != 0)
701                 eth_em_rxq_interrupt_setup(dev);
702
703         rte_intr_enable(intr_handle);
704
705         adapter->stopped = 0;
706
707         eth_em_rxtx_control(dev, true);
708         eth_em_link_update(dev, 0);
709
710         PMD_INIT_LOG(DEBUG, "<<");
711
712         return 0;
713
714 error_invalid_config:
715         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
716                      dev->data->dev_conf.link_speeds, dev->data->port_id);
717         em_dev_clear_queues(dev);
718         return -EINVAL;
719 }
720
721 /*********************************************************************
722  *
723  *  This routine disables all traffic on the adapter by issuing a
724  *  global reset on the MAC.
725  *
726  **********************************************************************/
727 static void
728 eth_em_stop(struct rte_eth_dev *dev)
729 {
730         struct rte_eth_link link;
731         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
732         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
733         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
734
735         eth_em_rxtx_control(dev, false);
736         em_rxq_intr_disable(hw);
737         em_lsc_intr_disable(hw);
738
739         e1000_reset_hw(hw);
740
741         /* Flush desc rings for i219 */
742         if (hw->mac.type == e1000_pch_spt || hw->mac.type == e1000_pch_cnp)
743                 em_flush_desc_rings(dev);
744
745         if (hw->mac.type >= e1000_82544)
746                 E1000_WRITE_REG(hw, E1000_WUC, 0);
747
748         /* Power down the phy. Needed to make the link go down */
749         e1000_power_down_phy(hw);
750
751         em_dev_clear_queues(dev);
752
753         /* clear the recorded link status */
754         memset(&link, 0, sizeof(link));
755         rte_eth_linkstatus_set(dev, &link);
756
757         if (!rte_intr_allow_others(intr_handle))
758                 /* resume to the default handler */
759                 rte_intr_callback_register(intr_handle,
760                                            eth_em_interrupt_handler,
761                                            (void *)dev);
762
763         /* Clean datapath event and queue/vec mapping */
764         rte_intr_efd_disable(intr_handle);
765         if (intr_handle->intr_vec != NULL) {
766                 rte_free(intr_handle->intr_vec);
767                 intr_handle->intr_vec = NULL;
768         }
769 }
770
771 static void
772 eth_em_close(struct rte_eth_dev *dev)
773 {
774         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
775         struct e1000_adapter *adapter =
776                 E1000_DEV_PRIVATE(dev->data->dev_private);
777
778         eth_em_stop(dev);
779         adapter->stopped = 1;
780         em_dev_free_queues(dev);
781         e1000_phy_hw_reset(hw);
782         em_release_manageability(hw);
783         em_hw_control_release(hw);
784 }
785
786 static int
787 em_get_rx_buffer_size(struct e1000_hw *hw)
788 {
789         uint32_t rx_buf_size;
790
791         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
792         return rx_buf_size;
793 }
794
795 /*********************************************************************
796  *
797  *  Initialize the hardware
798  *
799  **********************************************************************/
800 static int
801 em_hardware_init(struct e1000_hw *hw)
802 {
803         uint32_t rx_buf_size;
804         int diag;
805
806         /* Issue a global reset */
807         e1000_reset_hw(hw);
808
809         /* Let the firmware know the OS is in control */
810         em_hw_control_acquire(hw);
811
812         /*
813          * These parameters control the automatic generation (Tx) and
814          * response (Rx) to Ethernet PAUSE frames.
815          * - High water mark should allow for at least two standard size (1518)
816          *   frames to be received after sending an XOFF.
817          * - Low water mark works best when it is very near the high water mark.
818          *   This allows the receiver to restart by sending XON when it has
819          *   drained a bit. Here we use an arbitrary value of 1500 which will
820          *   restart after one full frame is pulled from the buffer. There
821          *   could be several smaller frames in the buffer and if so they will
822          *   not trigger the XON until their total number reduces the buffer
823          *   by 1500.
824          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
825          */
826         rx_buf_size = em_get_rx_buffer_size(hw);
827
828         hw->fc.high_water = rx_buf_size -
829                 PMD_ROUNDUP(RTE_ETHER_MAX_LEN * 2, 1024);
830         hw->fc.low_water = hw->fc.high_water - 1500;
831
832         if (hw->mac.type == e1000_80003es2lan)
833                 hw->fc.pause_time = UINT16_MAX;
834         else
835                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
836
837         hw->fc.send_xon = 1;
838
839         /* Set Flow control, use the tunable location if sane */
840         if (em_fc_setting <= e1000_fc_full)
841                 hw->fc.requested_mode = em_fc_setting;
842         else
843                 hw->fc.requested_mode = e1000_fc_none;
844
845         /* Workaround: no TX flow ctrl for PCH */
846         if (hw->mac.type == e1000_pchlan)
847                 hw->fc.requested_mode = e1000_fc_rx_pause;
848
849         /* Override - settings for PCH2LAN, ya its magic :) */
850         if (hw->mac.type == e1000_pch2lan) {
851                 hw->fc.high_water = 0x5C20;
852                 hw->fc.low_water = 0x5048;
853                 hw->fc.pause_time = 0x0650;
854                 hw->fc.refresh_time = 0x0400;
855         } else if (hw->mac.type == e1000_pch_lpt ||
856                    hw->mac.type == e1000_pch_spt ||
857                    hw->mac.type == e1000_pch_cnp) {
858                 hw->fc.requested_mode = e1000_fc_full;
859         }
860
861         diag = e1000_init_hw(hw);
862         if (diag < 0)
863                 return diag;
864         e1000_check_for_link(hw);
865         return 0;
866 }
867
868 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
869 static int
870 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
871 {
872         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
873         struct e1000_hw_stats *stats =
874                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
875         int pause_frames;
876
877         if(hw->phy.media_type == e1000_media_type_copper ||
878                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
879                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
880                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
881         }
882
883         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
884         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
885         stats->scc += E1000_READ_REG(hw, E1000_SCC);
886         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
887
888         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
889         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
890         stats->colc += E1000_READ_REG(hw, E1000_COLC);
891         stats->dc += E1000_READ_REG(hw, E1000_DC);
892         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
893         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
894         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
895
896         /*
897          * For watchdog management we need to know if we have been
898          * paused during the last interval, so capture that here.
899          */
900         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
901         stats->xoffrxc += pause_frames;
902         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
903         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
904         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
905         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
906         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
907         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
908         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
909         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
910         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
911         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
912         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
913         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
914
915         /*
916          * For the 64-bit byte counters the low dword must be read first.
917          * Both registers clear on the read of the high dword.
918          */
919
920         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
921         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
922         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
923         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
924
925         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
926         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
927         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
928         stats->roc += E1000_READ_REG(hw, E1000_ROC);
929         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
930
931         stats->tor += E1000_READ_REG(hw, E1000_TORH);
932         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
933
934         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
935         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
936         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
937         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
938         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
939         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
940         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
941         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
942         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
943         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
944
945         /* Interrupt Counts */
946
947         if (hw->mac.type >= e1000_82571) {
948                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
949                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
950                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
951                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
952                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
953                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
954                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
955                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
956                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
957         }
958
959         if (hw->mac.type >= e1000_82543) {
960                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
961                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
962                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
963                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
964                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
965                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
966         }
967
968         if (rte_stats == NULL)
969                 return -EINVAL;
970
971         /* Rx Errors */
972         rte_stats->imissed = stats->mpc;
973         rte_stats->ierrors = stats->crcerrs +
974                              stats->rlec + stats->ruc + stats->roc +
975                              stats->rxerrc + stats->algnerrc + stats->cexterr;
976
977         /* Tx Errors */
978         rte_stats->oerrors = stats->ecol + stats->latecol;
979
980         rte_stats->ipackets = stats->gprc;
981         rte_stats->opackets = stats->gptc;
982         rte_stats->ibytes   = stats->gorc;
983         rte_stats->obytes   = stats->gotc;
984         return 0;
985 }
986
987 static void
988 eth_em_stats_reset(struct rte_eth_dev *dev)
989 {
990         struct e1000_hw_stats *hw_stats =
991                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
992
993         /* HW registers are cleared on read */
994         eth_em_stats_get(dev, NULL);
995
996         /* Reset software totals */
997         memset(hw_stats, 0, sizeof(*hw_stats));
998 }
999
1000 static int
1001 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1002 {
1003         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1004         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1006
1007         em_rxq_intr_enable(hw);
1008         rte_intr_ack(intr_handle);
1009
1010         return 0;
1011 }
1012
1013 static int
1014 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1015 {
1016         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017
1018         em_rxq_intr_disable(hw);
1019
1020         return 0;
1021 }
1022
1023 uint32_t
1024 em_get_max_pktlen(struct rte_eth_dev *dev)
1025 {
1026         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027
1028         switch (hw->mac.type) {
1029         case e1000_82571:
1030         case e1000_82572:
1031         case e1000_ich9lan:
1032         case e1000_ich10lan:
1033         case e1000_pch2lan:
1034         case e1000_pch_lpt:
1035         case e1000_pch_spt:
1036         case e1000_pch_cnp:
1037         case e1000_82574:
1038         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1039         case e1000_82583:
1040                 return 0x2412;
1041         case e1000_pchlan:
1042                 return 0x1000;
1043         /* Adapters that do not support jumbo frames */
1044         case e1000_ich8lan:
1045                 return RTE_ETHER_MAX_LEN;
1046         default:
1047                 return MAX_JUMBO_FRAME_SIZE;
1048         }
1049 }
1050
1051 static void
1052 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1053 {
1054         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1055
1056         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1057         dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1058         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1059
1060         /*
1061          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1062          * Unfortunatelly, all these nics have just one TX context.
1063          * So we have few choises for TX:
1064          * - Use just one TX queue.
1065          * - Allow cksum offload only for one TX queue.
1066          * - Don't allow TX cksum offload at all.
1067          * For now, option #1 was chosen.
1068          * To use second RX queue we have to use extended RX descriptor
1069          * (Multiple Receive Queues are mutually exclusive with UDP
1070          * fragmentation and are not supported when a legacy receive
1071          * descriptor format is used).
1072          * Which means separate RX routinies - as legacy nics (82540, 82545)
1073          * don't support extended RXD.
1074          * To avoid it we support just one RX queue for now (no RSS).
1075          */
1076
1077         dev_info->max_rx_queues = 1;
1078         dev_info->max_tx_queues = 1;
1079
1080         dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1081         dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1082                                     dev_info->rx_queue_offload_capa;
1083         dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1084         dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1085                                     dev_info->tx_queue_offload_capa;
1086
1087         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1088                 .nb_max = E1000_MAX_RING_DESC,
1089                 .nb_min = E1000_MIN_RING_DESC,
1090                 .nb_align = EM_RXD_ALIGN,
1091         };
1092
1093         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1094                 .nb_max = E1000_MAX_RING_DESC,
1095                 .nb_min = E1000_MIN_RING_DESC,
1096                 .nb_align = EM_TXD_ALIGN,
1097                 .nb_seg_max = EM_TX_MAX_SEG,
1098                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1099         };
1100
1101         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1102                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1103                         ETH_LINK_SPEED_1G;
1104
1105         /* Preferred queue parameters */
1106         dev_info->default_rxportconf.nb_queues = 1;
1107         dev_info->default_txportconf.nb_queues = 1;
1108         dev_info->default_txportconf.ring_size = 256;
1109         dev_info->default_rxportconf.ring_size = 256;
1110 }
1111
1112 /* return 0 means link status changed, -1 means not changed */
1113 static int
1114 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1115 {
1116         struct e1000_hw *hw =
1117                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1118         struct rte_eth_link link;
1119         int link_check, count;
1120
1121         link_check = 0;
1122         hw->mac.get_link_status = 1;
1123
1124         /* possible wait-to-complete in up to 9 seconds */
1125         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1126                 /* Read the real link status */
1127                 switch (hw->phy.media_type) {
1128                 case e1000_media_type_copper:
1129                         /* Do the work to read phy */
1130                         e1000_check_for_link(hw);
1131                         link_check = !hw->mac.get_link_status;
1132                         break;
1133
1134                 case e1000_media_type_fiber:
1135                         e1000_check_for_link(hw);
1136                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1137                                         E1000_STATUS_LU);
1138                         break;
1139
1140                 case e1000_media_type_internal_serdes:
1141                         e1000_check_for_link(hw);
1142                         link_check = hw->mac.serdes_has_link;
1143                         break;
1144
1145                 default:
1146                         break;
1147                 }
1148                 if (link_check || wait_to_complete == 0)
1149                         break;
1150                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1151         }
1152         memset(&link, 0, sizeof(link));
1153
1154         /* Now we check if a transition has happened */
1155         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1156                 uint16_t duplex, speed;
1157                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1158                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1159                                 ETH_LINK_FULL_DUPLEX :
1160                                 ETH_LINK_HALF_DUPLEX;
1161                 link.link_speed = speed;
1162                 link.link_status = ETH_LINK_UP;
1163                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1164                                 ETH_LINK_SPEED_FIXED);
1165         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1166                 link.link_speed = ETH_SPEED_NUM_NONE;
1167                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1168                 link.link_status = ETH_LINK_DOWN;
1169                 link.link_autoneg = ETH_LINK_FIXED;
1170         }
1171
1172         return rte_eth_linkstatus_set(dev, &link);
1173 }
1174
1175 /*
1176  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1177  * For ASF and Pass Through versions of f/w this means
1178  * that the driver is loaded. For AMT version type f/w
1179  * this means that the network i/f is open.
1180  */
1181 static void
1182 em_hw_control_acquire(struct e1000_hw *hw)
1183 {
1184         uint32_t ctrl_ext, swsm;
1185
1186         /* Let firmware know the driver has taken over */
1187         if (hw->mac.type == e1000_82573) {
1188                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1189                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1190
1191         } else {
1192                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1193                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1194                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1195         }
1196 }
1197
1198 /*
1199  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1200  * For ASF and Pass Through versions of f/w this means that the
1201  * driver is no longer loaded. For AMT versions of the
1202  * f/w this means that the network i/f is closed.
1203  */
1204 static void
1205 em_hw_control_release(struct e1000_hw *hw)
1206 {
1207         uint32_t ctrl_ext, swsm;
1208
1209         /* Let firmware taken over control of h/w */
1210         if (hw->mac.type == e1000_82573) {
1211                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1212                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1213         } else {
1214                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1215                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1216                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1217         }
1218 }
1219
1220 /*
1221  * Bit of a misnomer, what this really means is
1222  * to enable OS management of the system... aka
1223  * to disable special hardware management features.
1224  */
1225 static void
1226 em_init_manageability(struct e1000_hw *hw)
1227 {
1228         if (e1000_enable_mng_pass_thru(hw)) {
1229                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1230                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1231
1232                 /* disable hardware interception of ARP */
1233                 manc &= ~(E1000_MANC_ARP_EN);
1234
1235                 /* enable receiving management packets to the host */
1236                 manc |= E1000_MANC_EN_MNG2HOST;
1237                 manc2h |= 1 << 5;  /* Mng Port 623 */
1238                 manc2h |= 1 << 6;  /* Mng Port 664 */
1239                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1240                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1241         }
1242 }
1243
1244 /*
1245  * Give control back to hardware management
1246  * controller if there is one.
1247  */
1248 static void
1249 em_release_manageability(struct e1000_hw *hw)
1250 {
1251         uint32_t manc;
1252
1253         if (e1000_enable_mng_pass_thru(hw)) {
1254                 manc = E1000_READ_REG(hw, E1000_MANC);
1255
1256                 /* re-enable hardware interception of ARP */
1257                 manc |= E1000_MANC_ARP_EN;
1258                 manc &= ~E1000_MANC_EN_MNG2HOST;
1259
1260                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1261         }
1262 }
1263
1264 static void
1265 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1266 {
1267         struct e1000_hw *hw =
1268                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1269         uint32_t rctl;
1270
1271         rctl = E1000_READ_REG(hw, E1000_RCTL);
1272         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1273         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1274 }
1275
1276 static void
1277 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1278 {
1279         struct e1000_hw *hw =
1280                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1281         uint32_t rctl;
1282
1283         rctl = E1000_READ_REG(hw, E1000_RCTL);
1284         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1285         if (dev->data->all_multicast == 1)
1286                 rctl |= E1000_RCTL_MPE;
1287         else
1288                 rctl &= (~E1000_RCTL_MPE);
1289         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1290 }
1291
1292 static void
1293 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1294 {
1295         struct e1000_hw *hw =
1296                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1297         uint32_t rctl;
1298
1299         rctl = E1000_READ_REG(hw, E1000_RCTL);
1300         rctl |= E1000_RCTL_MPE;
1301         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1302 }
1303
1304 static void
1305 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1306 {
1307         struct e1000_hw *hw =
1308                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309         uint32_t rctl;
1310
1311         if (dev->data->promiscuous == 1)
1312                 return; /* must remain in all_multicast mode */
1313         rctl = E1000_READ_REG(hw, E1000_RCTL);
1314         rctl &= (~E1000_RCTL_MPE);
1315         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1316 }
1317
1318 static int
1319 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1320 {
1321         struct e1000_hw *hw =
1322                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1323         struct e1000_vfta * shadow_vfta =
1324                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1325         uint32_t vfta;
1326         uint32_t vid_idx;
1327         uint32_t vid_bit;
1328
1329         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1330                               E1000_VFTA_ENTRY_MASK);
1331         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1332         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1333         if (on)
1334                 vfta |= vid_bit;
1335         else
1336                 vfta &= ~vid_bit;
1337         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1338
1339         /* update local VFTA copy */
1340         shadow_vfta->vfta[vid_idx] = vfta;
1341
1342         return 0;
1343 }
1344
1345 static void
1346 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1347 {
1348         struct e1000_hw *hw =
1349                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1350         uint32_t reg;
1351
1352         /* Filter Table Disable */
1353         reg = E1000_READ_REG(hw, E1000_RCTL);
1354         reg &= ~E1000_RCTL_CFIEN;
1355         reg &= ~E1000_RCTL_VFE;
1356         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1357 }
1358
1359 static void
1360 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1361 {
1362         struct e1000_hw *hw =
1363                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364         struct e1000_vfta * shadow_vfta =
1365                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1366         uint32_t reg;
1367         int i;
1368
1369         /* Filter Table Enable, CFI not used for packet acceptance */
1370         reg = E1000_READ_REG(hw, E1000_RCTL);
1371         reg &= ~E1000_RCTL_CFIEN;
1372         reg |= E1000_RCTL_VFE;
1373         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1374
1375         /* restore vfta from local copy */
1376         for (i = 0; i < IGB_VFTA_SIZE; i++)
1377                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1378 }
1379
1380 static void
1381 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1382 {
1383         struct e1000_hw *hw =
1384                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1385         uint32_t reg;
1386
1387         /* VLAN Mode Disable */
1388         reg = E1000_READ_REG(hw, E1000_CTRL);
1389         reg &= ~E1000_CTRL_VME;
1390         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1391
1392 }
1393
1394 static void
1395 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1396 {
1397         struct e1000_hw *hw =
1398                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1399         uint32_t reg;
1400
1401         /* VLAN Mode Enable */
1402         reg = E1000_READ_REG(hw, E1000_CTRL);
1403         reg |= E1000_CTRL_VME;
1404         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1405 }
1406
1407 static int
1408 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1409 {
1410         struct rte_eth_rxmode *rxmode;
1411
1412         rxmode = &dev->data->dev_conf.rxmode;
1413         if(mask & ETH_VLAN_STRIP_MASK){
1414                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1415                         em_vlan_hw_strip_enable(dev);
1416                 else
1417                         em_vlan_hw_strip_disable(dev);
1418         }
1419
1420         if(mask & ETH_VLAN_FILTER_MASK){
1421                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1422                         em_vlan_hw_filter_enable(dev);
1423                 else
1424                         em_vlan_hw_filter_disable(dev);
1425         }
1426
1427         return 0;
1428 }
1429
1430 /*
1431  * It enables the interrupt mask and then enable the interrupt.
1432  *
1433  * @param dev
1434  *  Pointer to struct rte_eth_dev.
1435  *
1436  * @return
1437  *  - On success, zero.
1438  *  - On failure, a negative value.
1439  */
1440 static int
1441 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1442 {
1443         uint32_t regval;
1444         struct e1000_hw *hw =
1445                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1446
1447         /* clear interrupt */
1448         E1000_READ_REG(hw, E1000_ICR);
1449         regval = E1000_READ_REG(hw, E1000_IMS);
1450         E1000_WRITE_REG(hw, E1000_IMS,
1451                         regval | E1000_ICR_LSC | E1000_ICR_OTHER);
1452         return 0;
1453 }
1454
1455 /*
1456  * It clears the interrupt causes and enables the interrupt.
1457  * It will be called once only during nic initialized.
1458  *
1459  * @param dev
1460  *  Pointer to struct rte_eth_dev.
1461  *
1462  * @return
1463  *  - On success, zero.
1464  *  - On failure, a negative value.
1465  */
1466 static int
1467 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1468 {
1469         struct e1000_hw *hw =
1470         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1471
1472         E1000_READ_REG(hw, E1000_ICR);
1473         em_rxq_intr_enable(hw);
1474         return 0;
1475 }
1476
1477 /*
1478  * It enable receive packet interrupt.
1479  * @param hw
1480  * Pointer to struct e1000_hw
1481  *
1482  * @return
1483  */
1484 static void
1485 em_rxq_intr_enable(struct e1000_hw *hw)
1486 {
1487         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1488         E1000_WRITE_FLUSH(hw);
1489 }
1490
1491 /*
1492  * It disabled lsc interrupt.
1493  * @param hw
1494  * Pointer to struct e1000_hw
1495  *
1496  * @return
1497  */
1498 static void
1499 em_lsc_intr_disable(struct e1000_hw *hw)
1500 {
1501         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC | E1000_IMS_OTHER);
1502         E1000_WRITE_FLUSH(hw);
1503 }
1504
1505 /*
1506  * It disabled receive packet interrupt.
1507  * @param hw
1508  * Pointer to struct e1000_hw
1509  *
1510  * @return
1511  */
1512 static void
1513 em_rxq_intr_disable(struct e1000_hw *hw)
1514 {
1515         E1000_READ_REG(hw, E1000_ICR);
1516         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1517         E1000_WRITE_FLUSH(hw);
1518 }
1519
1520 /*
1521  * It reads ICR and gets interrupt causes, check it and set a bit flag
1522  * to update link status.
1523  *
1524  * @param dev
1525  *  Pointer to struct rte_eth_dev.
1526  *
1527  * @return
1528  *  - On success, zero.
1529  *  - On failure, a negative value.
1530  */
1531 static int
1532 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1533 {
1534         uint32_t icr;
1535         struct e1000_hw *hw =
1536                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         struct e1000_interrupt *intr =
1538                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1539
1540         /* read-on-clear nic registers here */
1541         icr = E1000_READ_REG(hw, E1000_ICR);
1542         if (icr & E1000_ICR_LSC) {
1543                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1544         }
1545
1546         return 0;
1547 }
1548
1549 /*
1550  * It executes link_update after knowing an interrupt is prsent.
1551  *
1552  * @param dev
1553  *  Pointer to struct rte_eth_dev.
1554  *
1555  * @return
1556  *  - On success, zero.
1557  *  - On failure, a negative value.
1558  */
1559 static int
1560 eth_em_interrupt_action(struct rte_eth_dev *dev,
1561                         struct rte_intr_handle *intr_handle)
1562 {
1563         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1564         struct e1000_hw *hw =
1565                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566         struct e1000_interrupt *intr =
1567                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1568         struct rte_eth_link link;
1569         int ret;
1570
1571         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1572                 return -1;
1573
1574         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1575         rte_intr_ack(intr_handle);
1576
1577         /* set get_link_status to check register later */
1578         hw->mac.get_link_status = 1;
1579         ret = eth_em_link_update(dev, 0);
1580
1581         /* check if link has changed */
1582         if (ret < 0)
1583                 return 0;
1584
1585         rte_eth_linkstatus_get(dev, &link);
1586
1587         if (link.link_status) {
1588                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1589                              dev->data->port_id, link.link_speed,
1590                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1591                              "full-duplex" : "half-duplex");
1592         } else {
1593                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1594         }
1595         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1596                      pci_dev->addr.domain, pci_dev->addr.bus,
1597                      pci_dev->addr.devid, pci_dev->addr.function);
1598
1599         return 0;
1600 }
1601
1602 /**
1603  * Interrupt handler which shall be registered at first.
1604  *
1605  * @param handle
1606  *  Pointer to interrupt handle.
1607  * @param param
1608  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1609  *
1610  * @return
1611  *  void
1612  */
1613 static void
1614 eth_em_interrupt_handler(void *param)
1615 {
1616         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1617
1618         eth_em_interrupt_get_status(dev);
1619         eth_em_interrupt_action(dev, dev->intr_handle);
1620         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1621 }
1622
1623 static int
1624 eth_em_led_on(struct rte_eth_dev *dev)
1625 {
1626         struct e1000_hw *hw;
1627
1628         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1629         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1630 }
1631
1632 static int
1633 eth_em_led_off(struct rte_eth_dev *dev)
1634 {
1635         struct e1000_hw *hw;
1636
1637         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1639 }
1640
1641 static int
1642 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1643 {
1644         struct e1000_hw *hw;
1645         uint32_t ctrl;
1646         int tx_pause;
1647         int rx_pause;
1648
1649         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         fc_conf->pause_time = hw->fc.pause_time;
1651         fc_conf->high_water = hw->fc.high_water;
1652         fc_conf->low_water = hw->fc.low_water;
1653         fc_conf->send_xon = hw->fc.send_xon;
1654         fc_conf->autoneg = hw->mac.autoneg;
1655
1656         /*
1657          * Return rx_pause and tx_pause status according to actual setting of
1658          * the TFCE and RFCE bits in the CTRL register.
1659          */
1660         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1661         if (ctrl & E1000_CTRL_TFCE)
1662                 tx_pause = 1;
1663         else
1664                 tx_pause = 0;
1665
1666         if (ctrl & E1000_CTRL_RFCE)
1667                 rx_pause = 1;
1668         else
1669                 rx_pause = 0;
1670
1671         if (rx_pause && tx_pause)
1672                 fc_conf->mode = RTE_FC_FULL;
1673         else if (rx_pause)
1674                 fc_conf->mode = RTE_FC_RX_PAUSE;
1675         else if (tx_pause)
1676                 fc_conf->mode = RTE_FC_TX_PAUSE;
1677         else
1678                 fc_conf->mode = RTE_FC_NONE;
1679
1680         return 0;
1681 }
1682
1683 static int
1684 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1685 {
1686         struct e1000_hw *hw;
1687         int err;
1688         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1689                 e1000_fc_none,
1690                 e1000_fc_rx_pause,
1691                 e1000_fc_tx_pause,
1692                 e1000_fc_full
1693         };
1694         uint32_t rx_buf_size;
1695         uint32_t max_high_water;
1696         uint32_t rctl;
1697
1698         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699         if (fc_conf->autoneg != hw->mac.autoneg)
1700                 return -ENOTSUP;
1701         rx_buf_size = em_get_rx_buffer_size(hw);
1702         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1703
1704         /* At least reserve one Ethernet frame for watermark */
1705         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
1706         if ((fc_conf->high_water > max_high_water) ||
1707             (fc_conf->high_water < fc_conf->low_water)) {
1708                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1709                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1710                 return -EINVAL;
1711         }
1712
1713         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1714         hw->fc.pause_time     = fc_conf->pause_time;
1715         hw->fc.high_water     = fc_conf->high_water;
1716         hw->fc.low_water      = fc_conf->low_water;
1717         hw->fc.send_xon       = fc_conf->send_xon;
1718
1719         err = e1000_setup_link_generic(hw);
1720         if (err == E1000_SUCCESS) {
1721
1722                 /* check if we want to forward MAC frames - driver doesn't have native
1723                  * capability to do that, so we'll write the registers ourselves */
1724
1725                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1726
1727                 /* set or clear MFLCN.PMCF bit depending on configuration */
1728                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1729                         rctl |= E1000_RCTL_PMCF;
1730                 else
1731                         rctl &= ~E1000_RCTL_PMCF;
1732
1733                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1734                 E1000_WRITE_FLUSH(hw);
1735
1736                 return 0;
1737         }
1738
1739         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1740         return -EIO;
1741 }
1742
1743 static int
1744 eth_em_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1745                 uint32_t index, __rte_unused uint32_t pool)
1746 {
1747         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748
1749         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1750 }
1751
1752 static void
1753 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1754 {
1755         uint8_t addr[RTE_ETHER_ADDR_LEN];
1756         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757
1758         memset(addr, 0, sizeof(addr));
1759
1760         e1000_rar_set(hw, addr, index);
1761 }
1762
1763 static int
1764 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1765                             struct rte_ether_addr *addr)
1766 {
1767         eth_em_rar_clear(dev, 0);
1768
1769         return eth_em_rar_set(dev, (void *)addr, 0, 0);
1770 }
1771
1772 static int
1773 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1774 {
1775         struct rte_eth_dev_info dev_info;
1776         struct e1000_hw *hw;
1777         uint32_t frame_size;
1778         uint32_t rctl;
1779
1780         eth_em_infos_get(dev, &dev_info);
1781         frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1782                 VLAN_TAG_SIZE;
1783
1784         /* check that mtu is within the allowed range */
1785         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
1786                 return -EINVAL;
1787
1788         /* refuse mtu that requires the support of scattered packets when this
1789          * feature has not been enabled before. */
1790         if (!dev->data->scattered_rx &&
1791             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1792                 return -EINVAL;
1793
1794         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795         rctl = E1000_READ_REG(hw, E1000_RCTL);
1796
1797         /* switch to jumbo mode if needed */
1798         if (frame_size > RTE_ETHER_MAX_LEN) {
1799                 dev->data->dev_conf.rxmode.offloads |=
1800                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1801                 rctl |= E1000_RCTL_LPE;
1802         } else {
1803                 dev->data->dev_conf.rxmode.offloads &=
1804                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1805                 rctl &= ~E1000_RCTL_LPE;
1806         }
1807         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1808
1809         /* update max frame size */
1810         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1811         return 0;
1812 }
1813
1814 static int
1815 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1816                         struct rte_ether_addr *mc_addr_set,
1817                         uint32_t nb_mc_addr)
1818 {
1819         struct e1000_hw *hw;
1820
1821         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1823         return 0;
1824 }
1825
1826 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1827 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1828 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1829
1830 /* see e1000_logs.c */
1831 RTE_INIT(igb_init_log)
1832 {
1833         e1000_igb_init_log();
1834 }