4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_bus_pci.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_ethdev_pci.h>
50 #include <rte_memory.h>
51 #include <rte_memzone.h>
53 #include <rte_atomic.h>
54 #include <rte_malloc.h>
57 #include "e1000_logs.h"
58 #include "base/e1000_api.h"
59 #include "e1000_ethdev.h"
61 #define EM_EIAC 0x000DC
63 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
66 static int eth_em_configure(struct rte_eth_dev *dev);
67 static int eth_em_start(struct rte_eth_dev *dev);
68 static void eth_em_stop(struct rte_eth_dev *dev);
69 static void eth_em_close(struct rte_eth_dev *dev);
70 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
71 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
72 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
73 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
74 static int eth_em_link_update(struct rte_eth_dev *dev,
75 int wait_to_complete);
76 static int eth_em_stats_get(struct rte_eth_dev *dev,
77 struct rte_eth_stats *rte_stats);
78 static void eth_em_stats_reset(struct rte_eth_dev *dev);
79 static void eth_em_infos_get(struct rte_eth_dev *dev,
80 struct rte_eth_dev_info *dev_info);
81 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
84 struct rte_eth_fc_conf *fc_conf);
85 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
86 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
87 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
88 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
89 struct rte_intr_handle *handle);
90 static void eth_em_interrupt_handler(void *param);
92 static int em_hw_init(struct e1000_hw *hw);
93 static int em_hardware_init(struct e1000_hw *hw);
94 static void em_hw_control_acquire(struct e1000_hw *hw);
95 static void em_hw_control_release(struct e1000_hw *hw);
96 static void em_init_manageability(struct e1000_hw *hw);
97 static void em_release_manageability(struct e1000_hw *hw);
99 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
101 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
102 uint16_t vlan_id, int on);
103 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
104 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
106 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
107 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
110 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
111 uint16_t vlan_id, int on);
114 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
115 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
116 static void em_lsc_intr_disable(struct e1000_hw *hw);
117 static void em_rxq_intr_enable(struct e1000_hw *hw);
118 static void em_rxq_intr_disable(struct e1000_hw *hw);
120 static int eth_em_led_on(struct rte_eth_dev *dev);
121 static int eth_em_led_off(struct rte_eth_dev *dev);
123 static int em_get_rx_buffer_size(struct e1000_hw *hw);
124 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
125 uint32_t index, uint32_t pool);
126 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
128 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
129 struct ether_addr *mc_addr_set,
130 uint32_t nb_mc_addr);
132 #define EM_FC_PAUSE_TIME 0x0680
133 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
134 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
136 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
139 * The set of PCI devices this driver supports
141 static const struct rte_pci_id pci_id_em_map[] = {
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
160 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
161 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
162 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
163 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
164 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
165 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
166 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
167 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
168 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
169 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
170 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
171 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
172 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
173 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
174 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
175 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
176 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
177 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
178 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
179 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
180 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
181 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
182 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
183 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
184 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
185 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
186 { .vendor_id = 0, /* sentinel */ },
189 static const struct eth_dev_ops eth_em_ops = {
190 .dev_configure = eth_em_configure,
191 .dev_start = eth_em_start,
192 .dev_stop = eth_em_stop,
193 .dev_close = eth_em_close,
194 .promiscuous_enable = eth_em_promiscuous_enable,
195 .promiscuous_disable = eth_em_promiscuous_disable,
196 .allmulticast_enable = eth_em_allmulticast_enable,
197 .allmulticast_disable = eth_em_allmulticast_disable,
198 .link_update = eth_em_link_update,
199 .stats_get = eth_em_stats_get,
200 .stats_reset = eth_em_stats_reset,
201 .dev_infos_get = eth_em_infos_get,
202 .mtu_set = eth_em_mtu_set,
203 .vlan_filter_set = eth_em_vlan_filter_set,
204 .vlan_offload_set = eth_em_vlan_offload_set,
205 .rx_queue_setup = eth_em_rx_queue_setup,
206 .rx_queue_release = eth_em_rx_queue_release,
207 .rx_queue_count = eth_em_rx_queue_count,
208 .rx_descriptor_done = eth_em_rx_descriptor_done,
209 .rx_descriptor_status = eth_em_rx_descriptor_status,
210 .tx_descriptor_status = eth_em_tx_descriptor_status,
211 .tx_queue_setup = eth_em_tx_queue_setup,
212 .tx_queue_release = eth_em_tx_queue_release,
213 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
214 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
215 .dev_led_on = eth_em_led_on,
216 .dev_led_off = eth_em_led_off,
217 .flow_ctrl_get = eth_em_flow_ctrl_get,
218 .flow_ctrl_set = eth_em_flow_ctrl_set,
219 .mac_addr_add = eth_em_rar_set,
220 .mac_addr_remove = eth_em_rar_clear,
221 .set_mc_addr_list = eth_em_set_mc_addr_list,
222 .rxq_info_get = em_rxq_info_get,
223 .txq_info_get = em_txq_info_get,
227 * Atomically reads the link status information from global
228 * structure rte_eth_dev.
231 * - Pointer to the structure rte_eth_dev to read from.
232 * - Pointer to the buffer to be saved with the link status.
235 * - On success, zero.
236 * - On failure, negative value.
239 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
240 struct rte_eth_link *link)
242 struct rte_eth_link *dst = link;
243 struct rte_eth_link *src = &(dev->data->dev_link);
245 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
246 *(uint64_t *)src) == 0)
253 * Atomically writes the link status information into global
254 * structure rte_eth_dev.
257 * - Pointer to the structure rte_eth_dev to read from.
258 * - Pointer to the buffer to be saved with the link status.
261 * - On success, zero.
262 * - On failure, negative value.
265 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
266 struct rte_eth_link *link)
268 struct rte_eth_link *dst = &(dev->data->dev_link);
269 struct rte_eth_link *src = link;
271 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
272 *(uint64_t *)src) == 0)
279 * eth_em_dev_is_ich8 - Check for ICH8 device
280 * @hw: pointer to the HW structure
282 * return TRUE for ICH8, otherwise FALSE
285 eth_em_dev_is_ich8(struct e1000_hw *hw)
287 DEBUGFUNC("eth_em_dev_is_ich8");
289 switch (hw->device_id) {
290 case E1000_DEV_ID_PCH_LPT_I217_LM:
291 case E1000_DEV_ID_PCH_LPT_I217_V:
292 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
293 case E1000_DEV_ID_PCH_LPTLP_I218_V:
294 case E1000_DEV_ID_PCH_I218_V2:
295 case E1000_DEV_ID_PCH_I218_LM2:
296 case E1000_DEV_ID_PCH_I218_V3:
297 case E1000_DEV_ID_PCH_I218_LM3:
298 case E1000_DEV_ID_PCH_SPT_I219_LM:
299 case E1000_DEV_ID_PCH_SPT_I219_V:
300 case E1000_DEV_ID_PCH_SPT_I219_LM2:
301 case E1000_DEV_ID_PCH_SPT_I219_V2:
302 case E1000_DEV_ID_PCH_LBG_I219_LM3:
303 case E1000_DEV_ID_PCH_SPT_I219_LM4:
304 case E1000_DEV_ID_PCH_SPT_I219_V4:
305 case E1000_DEV_ID_PCH_SPT_I219_LM5:
306 case E1000_DEV_ID_PCH_SPT_I219_V5:
307 case E1000_DEV_ID_PCH_CNP_I219_LM6:
308 case E1000_DEV_ID_PCH_CNP_I219_V6:
309 case E1000_DEV_ID_PCH_CNP_I219_LM7:
310 case E1000_DEV_ID_PCH_CNP_I219_V7:
318 eth_em_dev_init(struct rte_eth_dev *eth_dev)
320 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
321 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
322 struct e1000_adapter *adapter =
323 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
324 struct e1000_hw *hw =
325 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
326 struct e1000_vfta * shadow_vfta =
327 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
329 eth_dev->dev_ops = ð_em_ops;
330 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
331 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
332 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
334 /* for secondary processes, we don't initialise any further as primary
335 * has already done this work. Only check we don't need a different
337 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
338 if (eth_dev->data->scattered_rx)
339 eth_dev->rx_pkt_burst =
340 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
344 rte_eth_copy_pci_info(eth_dev, pci_dev);
346 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
347 hw->device_id = pci_dev->id.device_id;
348 adapter->stopped = 0;
350 /* For ICH8 support we'll need to map the flash memory BAR */
351 if (eth_em_dev_is_ich8(hw))
352 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
354 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
355 em_hw_init(hw) != 0) {
356 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
358 eth_dev->data->port_id, pci_dev->id.vendor_id,
359 pci_dev->id.device_id);
363 /* Allocate memory for storing MAC addresses */
364 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
365 hw->mac.rar_entry_count, 0);
366 if (eth_dev->data->mac_addrs == NULL) {
367 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
368 "store MAC addresses",
369 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
373 /* Copy the permanent MAC address */
374 ether_addr_copy((struct ether_addr *) hw->mac.addr,
375 eth_dev->data->mac_addrs);
377 /* initialize the vfta */
378 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
380 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
381 eth_dev->data->port_id, pci_dev->id.vendor_id,
382 pci_dev->id.device_id);
384 rte_intr_callback_register(intr_handle,
385 eth_em_interrupt_handler, eth_dev);
391 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
393 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
394 struct e1000_adapter *adapter =
395 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
396 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
398 PMD_INIT_FUNC_TRACE();
400 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
403 if (adapter->stopped == 0)
404 eth_em_close(eth_dev);
406 eth_dev->dev_ops = NULL;
407 eth_dev->rx_pkt_burst = NULL;
408 eth_dev->tx_pkt_burst = NULL;
410 rte_free(eth_dev->data->mac_addrs);
411 eth_dev->data->mac_addrs = NULL;
413 /* disable uio intr before callback unregister */
414 rte_intr_disable(intr_handle);
415 rte_intr_callback_unregister(intr_handle,
416 eth_em_interrupt_handler, eth_dev);
421 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
422 struct rte_pci_device *pci_dev)
424 return rte_eth_dev_pci_generic_probe(pci_dev,
425 sizeof(struct e1000_adapter), eth_em_dev_init);
428 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
430 return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
433 static struct rte_pci_driver rte_em_pmd = {
434 .id_table = pci_id_em_map,
435 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
436 RTE_PCI_DRV_IOVA_AS_VA,
437 .probe = eth_em_pci_probe,
438 .remove = eth_em_pci_remove,
442 em_hw_init(struct e1000_hw *hw)
446 diag = hw->mac.ops.init_params(hw);
448 PMD_INIT_LOG(ERR, "MAC Initialization Error");
451 diag = hw->nvm.ops.init_params(hw);
453 PMD_INIT_LOG(ERR, "NVM Initialization Error");
456 diag = hw->phy.ops.init_params(hw);
458 PMD_INIT_LOG(ERR, "PHY Initialization Error");
461 (void) e1000_get_bus_info(hw);
464 hw->phy.autoneg_wait_to_complete = 0;
465 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
467 e1000_init_script_state_82541(hw, TRUE);
468 e1000_set_tbi_compatibility_82543(hw, TRUE);
471 if (hw->phy.media_type == e1000_media_type_copper) {
472 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
473 hw->phy.disable_polarity_correction = 0;
474 hw->phy.ms_type = e1000_ms_hw_default;
478 * Start from a known state, this is important in reading the nvm
483 /* Make sure we have a good EEPROM before we read from it */
484 if (e1000_validate_nvm_checksum(hw) < 0) {
486 * Some PCI-E parts fail the first check due to
487 * the link being in sleep state, call it again,
488 * if it fails a second time its a real issue.
490 diag = e1000_validate_nvm_checksum(hw);
492 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
497 /* Read the permanent MAC address out of the EEPROM */
498 diag = e1000_read_mac_addr(hw);
500 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
504 /* Now initialize the hardware */
505 diag = em_hardware_init(hw);
507 PMD_INIT_LOG(ERR, "Hardware initialization failed");
511 hw->mac.get_link_status = 1;
513 /* Indicate SOL/IDER usage */
514 diag = e1000_check_reset_block(hw);
516 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
522 em_hw_control_release(hw);
527 eth_em_configure(struct rte_eth_dev *dev)
529 struct e1000_interrupt *intr =
530 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
532 PMD_INIT_FUNC_TRACE();
533 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
534 PMD_INIT_FUNC_TRACE();
540 em_set_pba(struct e1000_hw *hw)
545 * Packet Buffer Allocation (PBA)
546 * Writing PBA sets the receive portion of the buffer
547 * the remainder is used for the transmit buffer.
548 * Devices before the 82547 had a Packet Buffer of 64K.
549 * After the 82547 the buffer was reduced to 40K.
551 switch (hw->mac.type) {
553 case e1000_82547_rev_2:
554 /* 82547: Total Packet Buffer is 40K */
555 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
559 case e1000_80003es2lan:
560 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
562 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
563 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
567 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
584 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
587 E1000_WRITE_REG(hw, E1000_PBA, pba);
591 eth_em_start(struct rte_eth_dev *dev)
593 struct e1000_adapter *adapter =
594 E1000_DEV_PRIVATE(dev->data->dev_private);
595 struct e1000_hw *hw =
596 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
597 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
598 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
600 uint32_t intr_vector = 0;
605 PMD_INIT_FUNC_TRACE();
609 e1000_power_up_phy(hw);
611 /* Set default PBA value */
614 /* Put the address into the Receive Address Array */
615 e1000_rar_set(hw, hw->mac.addr, 0);
618 * With the 82571 adapter, RAR[0] may be overwritten
619 * when the other port is reset, we make a duplicate
620 * in RAR[14] for that eventuality, this assures
621 * the interface continues to function.
623 if (hw->mac.type == e1000_82571) {
624 e1000_set_laa_state_82571(hw, TRUE);
625 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
628 /* Initialize the hardware */
629 if (em_hardware_init(hw)) {
630 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
634 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
636 /* Configure for OS presence */
637 em_init_manageability(hw);
639 if (dev->data->dev_conf.intr_conf.rxq != 0) {
640 intr_vector = dev->data->nb_rx_queues;
641 if (rte_intr_efd_enable(intr_handle, intr_vector))
645 if (rte_intr_dp_is_en(intr_handle)) {
646 intr_handle->intr_vec =
647 rte_zmalloc("intr_vec",
648 dev->data->nb_rx_queues * sizeof(int), 0);
649 if (intr_handle->intr_vec == NULL) {
650 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
651 " intr_vec", dev->data->nb_rx_queues);
655 /* enable rx interrupt */
656 em_rxq_intr_enable(hw);
661 ret = eth_em_rx_init(dev);
663 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
664 em_dev_clear_queues(dev);
668 e1000_clear_hw_cntrs_base_generic(hw);
670 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
671 ETH_VLAN_EXTEND_MASK;
672 ret = eth_em_vlan_offload_set(dev, mask);
674 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
675 em_dev_clear_queues(dev);
679 /* Set Interrupt Throttling Rate to maximum allowed value. */
680 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
682 /* Setup link speed and duplex */
683 speeds = &dev->data->dev_conf.link_speeds;
684 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
685 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
689 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
692 hw->phy.autoneg_advertised = 0;
694 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
695 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
696 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
698 goto error_invalid_config;
700 if (*speeds & ETH_LINK_SPEED_10M_HD) {
701 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
704 if (*speeds & ETH_LINK_SPEED_10M) {
705 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
708 if (*speeds & ETH_LINK_SPEED_100M_HD) {
709 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
712 if (*speeds & ETH_LINK_SPEED_100M) {
713 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
716 if (*speeds & ETH_LINK_SPEED_1G) {
717 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
720 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
721 goto error_invalid_config;
723 /* Set/reset the mac.autoneg based on the link speed,
728 hw->mac.forced_speed_duplex =
729 hw->phy.autoneg_advertised;
735 e1000_setup_link(hw);
737 if (rte_intr_allow_others(intr_handle)) {
738 /* check if lsc interrupt is enabled */
739 if (dev->data->dev_conf.intr_conf.lsc != 0) {
740 ret = eth_em_interrupt_setup(dev);
742 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
743 em_dev_clear_queues(dev);
748 rte_intr_callback_unregister(intr_handle,
749 eth_em_interrupt_handler,
751 if (dev->data->dev_conf.intr_conf.lsc != 0)
752 PMD_INIT_LOG(INFO, "lsc won't enable because of"
753 " no intr multiplexn");
755 /* check if rxq interrupt is enabled */
756 if (dev->data->dev_conf.intr_conf.rxq != 0)
757 eth_em_rxq_interrupt_setup(dev);
759 rte_intr_enable(intr_handle);
761 adapter->stopped = 0;
763 PMD_INIT_LOG(DEBUG, "<<");
767 error_invalid_config:
768 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
769 dev->data->dev_conf.link_speeds, dev->data->port_id);
770 em_dev_clear_queues(dev);
774 /*********************************************************************
776 * This routine disables all traffic on the adapter by issuing a
777 * global reset on the MAC.
779 **********************************************************************/
781 eth_em_stop(struct rte_eth_dev *dev)
783 struct rte_eth_link link;
784 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
785 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
786 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
788 em_rxq_intr_disable(hw);
789 em_lsc_intr_disable(hw);
792 if (hw->mac.type >= e1000_82544)
793 E1000_WRITE_REG(hw, E1000_WUC, 0);
795 /* Power down the phy. Needed to make the link go down */
796 e1000_power_down_phy(hw);
798 em_dev_clear_queues(dev);
800 /* clear the recorded link status */
801 memset(&link, 0, sizeof(link));
802 rte_em_dev_atomic_write_link_status(dev, &link);
804 if (!rte_intr_allow_others(intr_handle))
805 /* resume to the default handler */
806 rte_intr_callback_register(intr_handle,
807 eth_em_interrupt_handler,
810 /* Clean datapath event and queue/vec mapping */
811 rte_intr_efd_disable(intr_handle);
812 if (intr_handle->intr_vec != NULL) {
813 rte_free(intr_handle->intr_vec);
814 intr_handle->intr_vec = NULL;
819 eth_em_close(struct rte_eth_dev *dev)
821 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
822 struct e1000_adapter *adapter =
823 E1000_DEV_PRIVATE(dev->data->dev_private);
826 adapter->stopped = 1;
827 em_dev_free_queues(dev);
828 e1000_phy_hw_reset(hw);
829 em_release_manageability(hw);
830 em_hw_control_release(hw);
834 em_get_rx_buffer_size(struct e1000_hw *hw)
836 uint32_t rx_buf_size;
838 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
842 /*********************************************************************
844 * Initialize the hardware
846 **********************************************************************/
848 em_hardware_init(struct e1000_hw *hw)
850 uint32_t rx_buf_size;
853 /* Issue a global reset */
856 /* Let the firmware know the OS is in control */
857 em_hw_control_acquire(hw);
860 * These parameters control the automatic generation (Tx) and
861 * response (Rx) to Ethernet PAUSE frames.
862 * - High water mark should allow for at least two standard size (1518)
863 * frames to be received after sending an XOFF.
864 * - Low water mark works best when it is very near the high water mark.
865 * This allows the receiver to restart by sending XON when it has
866 * drained a bit. Here we use an arbitrary value of 1500 which will
867 * restart after one full frame is pulled from the buffer. There
868 * could be several smaller frames in the buffer and if so they will
869 * not trigger the XON until their total number reduces the buffer
871 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
873 rx_buf_size = em_get_rx_buffer_size(hw);
875 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
876 hw->fc.low_water = hw->fc.high_water - 1500;
878 if (hw->mac.type == e1000_80003es2lan)
879 hw->fc.pause_time = UINT16_MAX;
881 hw->fc.pause_time = EM_FC_PAUSE_TIME;
885 /* Set Flow control, use the tunable location if sane */
886 if (em_fc_setting <= e1000_fc_full)
887 hw->fc.requested_mode = em_fc_setting;
889 hw->fc.requested_mode = e1000_fc_none;
891 /* Workaround: no TX flow ctrl for PCH */
892 if (hw->mac.type == e1000_pchlan)
893 hw->fc.requested_mode = e1000_fc_rx_pause;
895 /* Override - settings for PCH2LAN, ya its magic :) */
896 if (hw->mac.type == e1000_pch2lan) {
897 hw->fc.high_water = 0x5C20;
898 hw->fc.low_water = 0x5048;
899 hw->fc.pause_time = 0x0650;
900 hw->fc.refresh_time = 0x0400;
901 } else if (hw->mac.type == e1000_pch_lpt ||
902 hw->mac.type == e1000_pch_spt ||
903 hw->mac.type == e1000_pch_cnp) {
904 hw->fc.requested_mode = e1000_fc_full;
907 diag = e1000_init_hw(hw);
910 e1000_check_for_link(hw);
914 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
916 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
918 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
919 struct e1000_hw_stats *stats =
920 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
923 if(hw->phy.media_type == e1000_media_type_copper ||
924 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
925 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
926 stats->sec += E1000_READ_REG(hw, E1000_SEC);
929 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
930 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
931 stats->scc += E1000_READ_REG(hw, E1000_SCC);
932 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
934 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
935 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
936 stats->colc += E1000_READ_REG(hw, E1000_COLC);
937 stats->dc += E1000_READ_REG(hw, E1000_DC);
938 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
939 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
940 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
943 * For watchdog management we need to know if we have been
944 * paused during the last interval, so capture that here.
946 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
947 stats->xoffrxc += pause_frames;
948 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
949 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
950 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
951 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
952 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
953 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
954 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
955 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
956 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
957 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
958 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
959 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
962 * For the 64-bit byte counters the low dword must be read first.
963 * Both registers clear on the read of the high dword.
966 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
967 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
968 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
969 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
971 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
972 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
973 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
974 stats->roc += E1000_READ_REG(hw, E1000_ROC);
975 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
977 stats->tor += E1000_READ_REG(hw, E1000_TORH);
978 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
980 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
981 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
982 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
983 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
984 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
985 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
986 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
987 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
988 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
989 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
991 /* Interrupt Counts */
993 if (hw->mac.type >= e1000_82571) {
994 stats->iac += E1000_READ_REG(hw, E1000_IAC);
995 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
996 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
997 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
998 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
999 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1000 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1001 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1002 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1005 if (hw->mac.type >= e1000_82543) {
1006 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1007 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1008 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1009 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1010 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1011 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1014 if (rte_stats == NULL)
1018 rte_stats->imissed = stats->mpc;
1019 rte_stats->ierrors = stats->crcerrs +
1020 stats->rlec + stats->ruc + stats->roc +
1021 stats->rxerrc + stats->algnerrc + stats->cexterr;
1024 rte_stats->oerrors = stats->ecol + stats->latecol;
1026 rte_stats->ipackets = stats->gprc;
1027 rte_stats->opackets = stats->gptc;
1028 rte_stats->ibytes = stats->gorc;
1029 rte_stats->obytes = stats->gotc;
1034 eth_em_stats_reset(struct rte_eth_dev *dev)
1036 struct e1000_hw_stats *hw_stats =
1037 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1039 /* HW registers are cleared on read */
1040 eth_em_stats_get(dev, NULL);
1042 /* Reset software totals */
1043 memset(hw_stats, 0, sizeof(*hw_stats));
1047 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1049 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1051 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1053 em_rxq_intr_enable(hw);
1054 rte_intr_enable(intr_handle);
1060 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1062 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1064 em_rxq_intr_disable(hw);
1070 em_get_max_pktlen(const struct e1000_hw *hw)
1072 switch (hw->mac.type) {
1076 case e1000_ich10lan:
1082 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1087 /* Adapters that do not support jumbo frames */
1089 return ETHER_MAX_LEN;
1091 return MAX_JUMBO_FRAME_SIZE;
1096 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1098 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1100 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1101 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1102 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1103 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1104 dev_info->rx_offload_capa =
1105 DEV_RX_OFFLOAD_VLAN_STRIP |
1106 DEV_RX_OFFLOAD_IPV4_CKSUM |
1107 DEV_RX_OFFLOAD_UDP_CKSUM |
1108 DEV_RX_OFFLOAD_TCP_CKSUM;
1109 dev_info->tx_offload_capa =
1110 DEV_TX_OFFLOAD_VLAN_INSERT |
1111 DEV_TX_OFFLOAD_IPV4_CKSUM |
1112 DEV_TX_OFFLOAD_UDP_CKSUM |
1113 DEV_TX_OFFLOAD_TCP_CKSUM;
1116 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1117 * Unfortunatelly, all these nics have just one TX context.
1118 * So we have few choises for TX:
1119 * - Use just one TX queue.
1120 * - Allow cksum offload only for one TX queue.
1121 * - Don't allow TX cksum offload at all.
1122 * For now, option #1 was chosen.
1123 * To use second RX queue we have to use extended RX descriptor
1124 * (Multiple Receive Queues are mutually exclusive with UDP
1125 * fragmentation and are not supported when a legacy receive
1126 * descriptor format is used).
1127 * Which means separate RX routinies - as legacy nics (82540, 82545)
1128 * don't support extended RXD.
1129 * To avoid it we support just one RX queue for now (no RSS).
1132 dev_info->max_rx_queues = 1;
1133 dev_info->max_tx_queues = 1;
1135 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1136 .nb_max = E1000_MAX_RING_DESC,
1137 .nb_min = E1000_MIN_RING_DESC,
1138 .nb_align = EM_RXD_ALIGN,
1141 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1142 .nb_max = E1000_MAX_RING_DESC,
1143 .nb_min = E1000_MIN_RING_DESC,
1144 .nb_align = EM_TXD_ALIGN,
1145 .nb_seg_max = EM_TX_MAX_SEG,
1146 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1149 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1150 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1154 /* return 0 means link status changed, -1 means not changed */
1156 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1158 struct e1000_hw *hw =
1159 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1160 struct rte_eth_link link, old;
1161 int link_check, count;
1164 hw->mac.get_link_status = 1;
1166 /* possible wait-to-complete in up to 9 seconds */
1167 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1168 /* Read the real link status */
1169 switch (hw->phy.media_type) {
1170 case e1000_media_type_copper:
1171 /* Do the work to read phy */
1172 e1000_check_for_link(hw);
1173 link_check = !hw->mac.get_link_status;
1176 case e1000_media_type_fiber:
1177 e1000_check_for_link(hw);
1178 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1182 case e1000_media_type_internal_serdes:
1183 e1000_check_for_link(hw);
1184 link_check = hw->mac.serdes_has_link;
1190 if (link_check || wait_to_complete == 0)
1192 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1194 memset(&link, 0, sizeof(link));
1195 rte_em_dev_atomic_read_link_status(dev, &link);
1198 /* Now we check if a transition has happened */
1199 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1200 uint16_t duplex, speed;
1201 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1202 link.link_duplex = (duplex == FULL_DUPLEX) ?
1203 ETH_LINK_FULL_DUPLEX :
1204 ETH_LINK_HALF_DUPLEX;
1205 link.link_speed = speed;
1206 link.link_status = ETH_LINK_UP;
1207 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1208 ETH_LINK_SPEED_FIXED);
1209 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1210 link.link_speed = 0;
1211 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1212 link.link_status = ETH_LINK_DOWN;
1213 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1215 rte_em_dev_atomic_write_link_status(dev, &link);
1218 if (old.link_status == link.link_status)
1226 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1227 * For ASF and Pass Through versions of f/w this means
1228 * that the driver is loaded. For AMT version type f/w
1229 * this means that the network i/f is open.
1232 em_hw_control_acquire(struct e1000_hw *hw)
1234 uint32_t ctrl_ext, swsm;
1236 /* Let firmware know the driver has taken over */
1237 if (hw->mac.type == e1000_82573) {
1238 swsm = E1000_READ_REG(hw, E1000_SWSM);
1239 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1242 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1243 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1244 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1249 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1250 * For ASF and Pass Through versions of f/w this means that the
1251 * driver is no longer loaded. For AMT versions of the
1252 * f/w this means that the network i/f is closed.
1255 em_hw_control_release(struct e1000_hw *hw)
1257 uint32_t ctrl_ext, swsm;
1259 /* Let firmware taken over control of h/w */
1260 if (hw->mac.type == e1000_82573) {
1261 swsm = E1000_READ_REG(hw, E1000_SWSM);
1262 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1264 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1265 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1266 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1271 * Bit of a misnomer, what this really means is
1272 * to enable OS management of the system... aka
1273 * to disable special hardware management features.
1276 em_init_manageability(struct e1000_hw *hw)
1278 if (e1000_enable_mng_pass_thru(hw)) {
1279 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1280 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1282 /* disable hardware interception of ARP */
1283 manc &= ~(E1000_MANC_ARP_EN);
1285 /* enable receiving management packets to the host */
1286 manc |= E1000_MANC_EN_MNG2HOST;
1287 manc2h |= 1 << 5; /* Mng Port 623 */
1288 manc2h |= 1 << 6; /* Mng Port 664 */
1289 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1290 E1000_WRITE_REG(hw, E1000_MANC, manc);
1295 * Give control back to hardware management
1296 * controller if there is one.
1299 em_release_manageability(struct e1000_hw *hw)
1303 if (e1000_enable_mng_pass_thru(hw)) {
1304 manc = E1000_READ_REG(hw, E1000_MANC);
1306 /* re-enable hardware interception of ARP */
1307 manc |= E1000_MANC_ARP_EN;
1308 manc &= ~E1000_MANC_EN_MNG2HOST;
1310 E1000_WRITE_REG(hw, E1000_MANC, manc);
1315 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1317 struct e1000_hw *hw =
1318 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1321 rctl = E1000_READ_REG(hw, E1000_RCTL);
1322 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1323 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1327 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1329 struct e1000_hw *hw =
1330 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1333 rctl = E1000_READ_REG(hw, E1000_RCTL);
1334 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1335 if (dev->data->all_multicast == 1)
1336 rctl |= E1000_RCTL_MPE;
1338 rctl &= (~E1000_RCTL_MPE);
1339 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1343 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1345 struct e1000_hw *hw =
1346 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349 rctl = E1000_READ_REG(hw, E1000_RCTL);
1350 rctl |= E1000_RCTL_MPE;
1351 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1355 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1357 struct e1000_hw *hw =
1358 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1361 if (dev->data->promiscuous == 1)
1362 return; /* must remain in all_multicast mode */
1363 rctl = E1000_READ_REG(hw, E1000_RCTL);
1364 rctl &= (~E1000_RCTL_MPE);
1365 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1369 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1371 struct e1000_hw *hw =
1372 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373 struct e1000_vfta * shadow_vfta =
1374 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1379 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1380 E1000_VFTA_ENTRY_MASK);
1381 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1382 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1387 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1389 /* update local VFTA copy */
1390 shadow_vfta->vfta[vid_idx] = vfta;
1396 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1398 struct e1000_hw *hw =
1399 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1402 /* Filter Table Disable */
1403 reg = E1000_READ_REG(hw, E1000_RCTL);
1404 reg &= ~E1000_RCTL_CFIEN;
1405 reg &= ~E1000_RCTL_VFE;
1406 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1410 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1412 struct e1000_hw *hw =
1413 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414 struct e1000_vfta * shadow_vfta =
1415 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1419 /* Filter Table Enable, CFI not used for packet acceptance */
1420 reg = E1000_READ_REG(hw, E1000_RCTL);
1421 reg &= ~E1000_RCTL_CFIEN;
1422 reg |= E1000_RCTL_VFE;
1423 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1425 /* restore vfta from local copy */
1426 for (i = 0; i < IGB_VFTA_SIZE; i++)
1427 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1431 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1433 struct e1000_hw *hw =
1434 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437 /* VLAN Mode Disable */
1438 reg = E1000_READ_REG(hw, E1000_CTRL);
1439 reg &= ~E1000_CTRL_VME;
1440 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1445 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1447 struct e1000_hw *hw =
1448 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1451 /* VLAN Mode Enable */
1452 reg = E1000_READ_REG(hw, E1000_CTRL);
1453 reg |= E1000_CTRL_VME;
1454 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1458 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1460 if(mask & ETH_VLAN_STRIP_MASK){
1461 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1462 em_vlan_hw_strip_enable(dev);
1464 em_vlan_hw_strip_disable(dev);
1467 if(mask & ETH_VLAN_FILTER_MASK){
1468 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1469 em_vlan_hw_filter_enable(dev);
1471 em_vlan_hw_filter_disable(dev);
1478 * It enables the interrupt mask and then enable the interrupt.
1481 * Pointer to struct rte_eth_dev.
1484 * - On success, zero.
1485 * - On failure, a negative value.
1488 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1491 struct e1000_hw *hw =
1492 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1494 /* clear interrupt */
1495 E1000_READ_REG(hw, E1000_ICR);
1496 regval = E1000_READ_REG(hw, E1000_IMS);
1497 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1502 * It clears the interrupt causes and enables the interrupt.
1503 * It will be called once only during nic initialized.
1506 * Pointer to struct rte_eth_dev.
1509 * - On success, zero.
1510 * - On failure, a negative value.
1513 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1515 struct e1000_hw *hw =
1516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518 E1000_READ_REG(hw, E1000_ICR);
1519 em_rxq_intr_enable(hw);
1524 * It enable receive packet interrupt.
1526 * Pointer to struct e1000_hw
1531 em_rxq_intr_enable(struct e1000_hw *hw)
1533 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1534 E1000_WRITE_FLUSH(hw);
1538 * It disabled lsc interrupt.
1540 * Pointer to struct e1000_hw
1545 em_lsc_intr_disable(struct e1000_hw *hw)
1547 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1548 E1000_WRITE_FLUSH(hw);
1552 * It disabled receive packet interrupt.
1554 * Pointer to struct e1000_hw
1559 em_rxq_intr_disable(struct e1000_hw *hw)
1561 E1000_READ_REG(hw, E1000_ICR);
1562 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1563 E1000_WRITE_FLUSH(hw);
1567 * It reads ICR and gets interrupt causes, check it and set a bit flag
1568 * to update link status.
1571 * Pointer to struct rte_eth_dev.
1574 * - On success, zero.
1575 * - On failure, a negative value.
1578 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1581 struct e1000_hw *hw =
1582 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583 struct e1000_interrupt *intr =
1584 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1586 /* read-on-clear nic registers here */
1587 icr = E1000_READ_REG(hw, E1000_ICR);
1588 if (icr & E1000_ICR_LSC) {
1589 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1596 * It executes link_update after knowing an interrupt is prsent.
1599 * Pointer to struct rte_eth_dev.
1602 * - On success, zero.
1603 * - On failure, a negative value.
1606 eth_em_interrupt_action(struct rte_eth_dev *dev,
1607 struct rte_intr_handle *intr_handle)
1609 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1610 struct e1000_hw *hw =
1611 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612 struct e1000_interrupt *intr =
1613 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1614 uint32_t tctl, rctl;
1615 struct rte_eth_link link;
1618 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1621 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1622 rte_intr_enable(intr_handle);
1624 /* set get_link_status to check register later */
1625 hw->mac.get_link_status = 1;
1626 ret = eth_em_link_update(dev, 0);
1628 /* check if link has changed */
1632 memset(&link, 0, sizeof(link));
1633 rte_em_dev_atomic_read_link_status(dev, &link);
1634 if (link.link_status) {
1635 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1636 dev->data->port_id, link.link_speed,
1637 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1638 "full-duplex" : "half-duplex");
1640 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1642 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1643 pci_dev->addr.domain, pci_dev->addr.bus,
1644 pci_dev->addr.devid, pci_dev->addr.function);
1646 tctl = E1000_READ_REG(hw, E1000_TCTL);
1647 rctl = E1000_READ_REG(hw, E1000_RCTL);
1648 if (link.link_status) {
1650 tctl |= E1000_TCTL_EN;
1651 rctl |= E1000_RCTL_EN;
1654 tctl &= ~E1000_TCTL_EN;
1655 rctl &= ~E1000_RCTL_EN;
1657 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1658 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1659 E1000_WRITE_FLUSH(hw);
1665 * Interrupt handler which shall be registered at first.
1668 * Pointer to interrupt handle.
1670 * The address of parameter (struct rte_eth_dev *) regsitered before.
1676 eth_em_interrupt_handler(void *param)
1678 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1680 eth_em_interrupt_get_status(dev);
1681 eth_em_interrupt_action(dev, dev->intr_handle);
1682 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1686 eth_em_led_on(struct rte_eth_dev *dev)
1688 struct e1000_hw *hw;
1690 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1695 eth_em_led_off(struct rte_eth_dev *dev)
1697 struct e1000_hw *hw;
1699 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1704 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1706 struct e1000_hw *hw;
1711 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712 fc_conf->pause_time = hw->fc.pause_time;
1713 fc_conf->high_water = hw->fc.high_water;
1714 fc_conf->low_water = hw->fc.low_water;
1715 fc_conf->send_xon = hw->fc.send_xon;
1716 fc_conf->autoneg = hw->mac.autoneg;
1719 * Return rx_pause and tx_pause status according to actual setting of
1720 * the TFCE and RFCE bits in the CTRL register.
1722 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1723 if (ctrl & E1000_CTRL_TFCE)
1728 if (ctrl & E1000_CTRL_RFCE)
1733 if (rx_pause && tx_pause)
1734 fc_conf->mode = RTE_FC_FULL;
1736 fc_conf->mode = RTE_FC_RX_PAUSE;
1738 fc_conf->mode = RTE_FC_TX_PAUSE;
1740 fc_conf->mode = RTE_FC_NONE;
1746 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1748 struct e1000_hw *hw;
1750 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1756 uint32_t rx_buf_size;
1757 uint32_t max_high_water;
1760 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1761 if (fc_conf->autoneg != hw->mac.autoneg)
1763 rx_buf_size = em_get_rx_buffer_size(hw);
1764 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1766 /* At least reserve one Ethernet frame for watermark */
1767 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1768 if ((fc_conf->high_water > max_high_water) ||
1769 (fc_conf->high_water < fc_conf->low_water)) {
1770 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1771 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1775 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1776 hw->fc.pause_time = fc_conf->pause_time;
1777 hw->fc.high_water = fc_conf->high_water;
1778 hw->fc.low_water = fc_conf->low_water;
1779 hw->fc.send_xon = fc_conf->send_xon;
1781 err = e1000_setup_link_generic(hw);
1782 if (err == E1000_SUCCESS) {
1784 /* check if we want to forward MAC frames - driver doesn't have native
1785 * capability to do that, so we'll write the registers ourselves */
1787 rctl = E1000_READ_REG(hw, E1000_RCTL);
1789 /* set or clear MFLCN.PMCF bit depending on configuration */
1790 if (fc_conf->mac_ctrl_frame_fwd != 0)
1791 rctl |= E1000_RCTL_PMCF;
1793 rctl &= ~E1000_RCTL_PMCF;
1795 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1796 E1000_WRITE_FLUSH(hw);
1801 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1806 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1807 uint32_t index, __rte_unused uint32_t pool)
1809 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1811 return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1815 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1817 uint8_t addr[ETHER_ADDR_LEN];
1818 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820 memset(addr, 0, sizeof(addr));
1822 e1000_rar_set(hw, addr, index);
1826 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1828 struct rte_eth_dev_info dev_info;
1829 struct e1000_hw *hw;
1830 uint32_t frame_size;
1833 eth_em_infos_get(dev, &dev_info);
1834 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1836 /* check that mtu is within the allowed range */
1837 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1840 /* refuse mtu that requires the support of scattered packets when this
1841 * feature has not been enabled before. */
1842 if (!dev->data->scattered_rx &&
1843 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1846 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847 rctl = E1000_READ_REG(hw, E1000_RCTL);
1849 /* switch to jumbo mode if needed */
1850 if (frame_size > ETHER_MAX_LEN) {
1851 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1852 rctl |= E1000_RCTL_LPE;
1854 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1855 rctl &= ~E1000_RCTL_LPE;
1857 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1859 /* update max frame size */
1860 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1865 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1866 struct ether_addr *mc_addr_set,
1867 uint32_t nb_mc_addr)
1869 struct e1000_hw *hw;
1871 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1876 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1877 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1878 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");