4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "base/e1000_api.h"
58 #include "e1000_ethdev.h"
62 * Default values for port configuration
64 #define IGB_DEFAULT_RX_FREE_THRESH 32
66 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
67 #define IGB_DEFAULT_RX_HTHRESH 8
68 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
70 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
71 #define IGB_DEFAULT_TX_HTHRESH 1
72 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
74 #define IGB_HKEY_MAX_INDEX 10
76 /* Bit shift and mask */
77 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
78 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
79 #define IGB_8_BIT_WIDTH CHAR_BIT
80 #define IGB_8_BIT_MASK UINT8_MAX
82 /* Additional timesync values. */
83 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
84 #define E1000_ETQF_FILTER_1588 3
85 #define IGB_82576_TSYNC_SHIFT 16
86 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
87 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
90 #define E1000_VTIVAR_MISC 0x01740
91 #define E1000_VTIVAR_MISC_MASK 0xFF
92 #define E1000_VTIVAR_VALID 0x80
93 #define E1000_VTIVAR_MISC_MAILBOX 0
94 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
96 /* External VLAN Enable bit mask */
97 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
99 /* External VLAN Ether Type bit mask and shift */
100 #define E1000_VET_VET_EXT 0xFFFF0000
101 #define E1000_VET_VET_EXT_SHIFT 16
103 static int eth_igb_configure(struct rte_eth_dev *dev);
104 static int eth_igb_start(struct rte_eth_dev *dev);
105 static void eth_igb_stop(struct rte_eth_dev *dev);
106 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
107 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
108 static void eth_igb_close(struct rte_eth_dev *dev);
109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
113 static int eth_igb_link_update(struct rte_eth_dev *dev,
114 int wait_to_complete);
115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
116 struct rte_eth_stats *rte_stats);
117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
118 struct rte_eth_xstat *xstats, unsigned n);
119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
121 uint64_t *values, unsigned int n);
122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
123 struct rte_eth_xstat_name *xstats_names,
125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
126 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
131 char *fw_version, size_t fw_size);
132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
133 struct rte_eth_dev_info *dev_info);
134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
136 struct rte_eth_dev_info *dev_info);
137 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
138 struct rte_eth_fc_conf *fc_conf);
139 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
140 struct rte_eth_fc_conf *fc_conf);
141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
145 struct rte_intr_handle *handle);
146 static void eth_igb_interrupt_handler(void *param);
147 static int igb_hardware_init(struct e1000_hw *hw);
148 static void igb_hw_control_acquire(struct e1000_hw *hw);
149 static void igb_hw_control_release(struct e1000_hw *hw);
150 static void igb_init_manageability(struct e1000_hw *hw);
151 static void igb_release_manageability(struct e1000_hw *hw);
153 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
156 uint16_t vlan_id, int on);
157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
158 enum rte_vlan_type vlan_type,
160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
169 static int eth_igb_led_on(struct rte_eth_dev *dev);
170 static int eth_igb_led_off(struct rte_eth_dev *dev);
172 static void igb_intr_disable(struct e1000_hw *hw);
173 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
175 struct ether_addr *mac_addr,
176 uint32_t index, uint32_t pool);
177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
179 struct ether_addr *addr);
181 static void igbvf_intr_disable(struct e1000_hw *hw);
182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
183 static int igbvf_dev_start(struct rte_eth_dev *dev);
184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
185 static void igbvf_dev_close(struct rte_eth_dev *dev);
186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
190 static int eth_igbvf_link_update(struct e1000_hw *hw);
191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
192 struct rte_eth_stats *rte_stats);
193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
194 struct rte_eth_xstat *xstats, unsigned n);
195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
196 struct rte_eth_xstat_name *xstats_names,
198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
200 uint16_t vlan_id, int on);
201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
204 struct ether_addr *addr);
205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
206 static int igbvf_get_regs(struct rte_eth_dev *dev,
207 struct rte_dev_reg_info *regs);
209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
216 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
217 struct rte_eth_syn_filter *filter);
218 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
219 enum rte_filter_op filter_op,
221 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
222 struct rte_eth_ntuple_filter *ntuple_filter);
223 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
224 struct rte_eth_ntuple_filter *ntuple_filter);
225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
226 struct rte_eth_flex_filter *filter);
227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
228 enum rte_filter_op filter_op,
230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
231 struct rte_eth_ntuple_filter *ntuple_filter);
232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
233 struct rte_eth_ntuple_filter *ntuple_filter);
234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
235 struct rte_eth_ntuple_filter *filter);
236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
237 enum rte_filter_op filter_op,
239 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
240 enum rte_filter_op filter_op,
242 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
243 struct rte_eth_ethertype_filter *filter);
244 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
245 enum rte_filter_type filter_type,
246 enum rte_filter_op filter_op,
248 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
249 static int eth_igb_get_regs(struct rte_eth_dev *dev,
250 struct rte_dev_reg_info *regs);
251 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
252 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
253 struct rte_dev_eeprom_info *eeprom);
254 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
255 struct rte_dev_eeprom_info *eeprom);
256 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
257 struct ether_addr *mc_addr_set,
258 uint32_t nb_mc_addr);
259 static int igb_timesync_enable(struct rte_eth_dev *dev);
260 static int igb_timesync_disable(struct rte_eth_dev *dev);
261 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
262 struct timespec *timestamp,
264 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
265 struct timespec *timestamp);
266 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
267 static int igb_timesync_read_time(struct rte_eth_dev *dev,
268 struct timespec *timestamp);
269 static int igb_timesync_write_time(struct rte_eth_dev *dev,
270 const struct timespec *timestamp);
271 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
273 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
275 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
276 uint8_t queue, uint8_t msix_vector);
277 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
278 uint8_t index, uint8_t offset);
279 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
280 static void eth_igbvf_interrupt_handler(void *param);
281 static void igbvf_mbx_process(struct rte_eth_dev *dev);
282 static int igb_filter_restore(struct rte_eth_dev *dev);
285 * Define VF Stats MACRO for Non "cleared on read" register
287 #define UPDATE_VF_STAT(reg, last, cur) \
289 u32 latest = E1000_READ_REG(hw, reg); \
290 cur += (latest - last) & UINT_MAX; \
294 #define IGB_FC_PAUSE_TIME 0x0680
295 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
296 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
298 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
300 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
303 * The set of PCI devices this driver supports
305 static const struct rte_pci_id pci_id_igb_map[] = {
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
335 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
336 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
337 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
338 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
339 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
340 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
341 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
342 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
343 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
344 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
345 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
346 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
347 { .vendor_id = 0, /* sentinel */ },
351 * The set of PCI devices this driver supports (for 82576&I350 VF)
353 static const struct rte_pci_id pci_id_igbvf_map[] = {
354 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
355 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
356 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
357 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
358 { .vendor_id = 0, /* sentinel */ },
361 static const struct rte_eth_desc_lim rx_desc_lim = {
362 .nb_max = E1000_MAX_RING_DESC,
363 .nb_min = E1000_MIN_RING_DESC,
364 .nb_align = IGB_RXD_ALIGN,
367 static const struct rte_eth_desc_lim tx_desc_lim = {
368 .nb_max = E1000_MAX_RING_DESC,
369 .nb_min = E1000_MIN_RING_DESC,
370 .nb_align = IGB_RXD_ALIGN,
371 .nb_seg_max = IGB_TX_MAX_SEG,
372 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
375 static const struct eth_dev_ops eth_igb_ops = {
376 .dev_configure = eth_igb_configure,
377 .dev_start = eth_igb_start,
378 .dev_stop = eth_igb_stop,
379 .dev_set_link_up = eth_igb_dev_set_link_up,
380 .dev_set_link_down = eth_igb_dev_set_link_down,
381 .dev_close = eth_igb_close,
382 .promiscuous_enable = eth_igb_promiscuous_enable,
383 .promiscuous_disable = eth_igb_promiscuous_disable,
384 .allmulticast_enable = eth_igb_allmulticast_enable,
385 .allmulticast_disable = eth_igb_allmulticast_disable,
386 .link_update = eth_igb_link_update,
387 .stats_get = eth_igb_stats_get,
388 .xstats_get = eth_igb_xstats_get,
389 .xstats_get_by_id = eth_igb_xstats_get_by_id,
390 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
391 .xstats_get_names = eth_igb_xstats_get_names,
392 .stats_reset = eth_igb_stats_reset,
393 .xstats_reset = eth_igb_xstats_reset,
394 .fw_version_get = eth_igb_fw_version_get,
395 .dev_infos_get = eth_igb_infos_get,
396 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
397 .mtu_set = eth_igb_mtu_set,
398 .vlan_filter_set = eth_igb_vlan_filter_set,
399 .vlan_tpid_set = eth_igb_vlan_tpid_set,
400 .vlan_offload_set = eth_igb_vlan_offload_set,
401 .rx_queue_setup = eth_igb_rx_queue_setup,
402 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
403 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
404 .rx_queue_release = eth_igb_rx_queue_release,
405 .rx_queue_count = eth_igb_rx_queue_count,
406 .rx_descriptor_done = eth_igb_rx_descriptor_done,
407 .rx_descriptor_status = eth_igb_rx_descriptor_status,
408 .tx_descriptor_status = eth_igb_tx_descriptor_status,
409 .tx_queue_setup = eth_igb_tx_queue_setup,
410 .tx_queue_release = eth_igb_tx_queue_release,
411 .tx_done_cleanup = eth_igb_tx_done_cleanup,
412 .dev_led_on = eth_igb_led_on,
413 .dev_led_off = eth_igb_led_off,
414 .flow_ctrl_get = eth_igb_flow_ctrl_get,
415 .flow_ctrl_set = eth_igb_flow_ctrl_set,
416 .mac_addr_add = eth_igb_rar_set,
417 .mac_addr_remove = eth_igb_rar_clear,
418 .mac_addr_set = eth_igb_default_mac_addr_set,
419 .reta_update = eth_igb_rss_reta_update,
420 .reta_query = eth_igb_rss_reta_query,
421 .rss_hash_update = eth_igb_rss_hash_update,
422 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
423 .filter_ctrl = eth_igb_filter_ctrl,
424 .set_mc_addr_list = eth_igb_set_mc_addr_list,
425 .rxq_info_get = igb_rxq_info_get,
426 .txq_info_get = igb_txq_info_get,
427 .timesync_enable = igb_timesync_enable,
428 .timesync_disable = igb_timesync_disable,
429 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
430 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
431 .get_reg = eth_igb_get_regs,
432 .get_eeprom_length = eth_igb_get_eeprom_length,
433 .get_eeprom = eth_igb_get_eeprom,
434 .set_eeprom = eth_igb_set_eeprom,
435 .timesync_adjust_time = igb_timesync_adjust_time,
436 .timesync_read_time = igb_timesync_read_time,
437 .timesync_write_time = igb_timesync_write_time,
441 * dev_ops for virtual function, bare necessities for basic vf
442 * operation have been implemented
444 static const struct eth_dev_ops igbvf_eth_dev_ops = {
445 .dev_configure = igbvf_dev_configure,
446 .dev_start = igbvf_dev_start,
447 .dev_stop = igbvf_dev_stop,
448 .dev_close = igbvf_dev_close,
449 .promiscuous_enable = igbvf_promiscuous_enable,
450 .promiscuous_disable = igbvf_promiscuous_disable,
451 .allmulticast_enable = igbvf_allmulticast_enable,
452 .allmulticast_disable = igbvf_allmulticast_disable,
453 .link_update = eth_igb_link_update,
454 .stats_get = eth_igbvf_stats_get,
455 .xstats_get = eth_igbvf_xstats_get,
456 .xstats_get_names = eth_igbvf_xstats_get_names,
457 .stats_reset = eth_igbvf_stats_reset,
458 .xstats_reset = eth_igbvf_stats_reset,
459 .vlan_filter_set = igbvf_vlan_filter_set,
460 .dev_infos_get = eth_igbvf_infos_get,
461 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
462 .rx_queue_setup = eth_igb_rx_queue_setup,
463 .rx_queue_release = eth_igb_rx_queue_release,
464 .tx_queue_setup = eth_igb_tx_queue_setup,
465 .tx_queue_release = eth_igb_tx_queue_release,
466 .set_mc_addr_list = eth_igb_set_mc_addr_list,
467 .rxq_info_get = igb_rxq_info_get,
468 .txq_info_get = igb_txq_info_get,
469 .mac_addr_set = igbvf_default_mac_addr_set,
470 .get_reg = igbvf_get_regs,
473 /* store statistics names and its offset in stats structure */
474 struct rte_igb_xstats_name_off {
475 char name[RTE_ETH_XSTATS_NAME_SIZE];
479 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
480 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
481 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
482 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
483 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
484 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
485 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
486 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
488 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
489 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
490 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
491 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
492 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
493 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
494 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
495 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
496 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
497 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
498 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
500 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
501 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
502 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
503 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
504 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
506 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
508 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
509 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
510 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
511 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
512 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
513 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
514 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
515 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
516 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
517 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
518 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
519 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
520 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
521 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
522 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
523 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
524 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
525 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
527 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
529 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
530 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
531 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
532 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
533 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
534 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
535 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
537 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
540 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
541 sizeof(rte_igb_stats_strings[0]))
543 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
544 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
545 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
546 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
547 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
548 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
551 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
552 sizeof(rte_igbvf_stats_strings[0]))
555 * Atomically reads the link status information from global
556 * structure rte_eth_dev.
559 * - Pointer to the structure rte_eth_dev to read from.
560 * - Pointer to the buffer to be saved with the link status.
563 * - On success, zero.
564 * - On failure, negative value.
567 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
568 struct rte_eth_link *link)
570 struct rte_eth_link *dst = link;
571 struct rte_eth_link *src = &(dev->data->dev_link);
573 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
574 *(uint64_t *)src) == 0)
581 * Atomically writes the link status information into global
582 * structure rte_eth_dev.
585 * - Pointer to the structure rte_eth_dev to read from.
586 * - Pointer to the buffer to be saved with the link status.
589 * - On success, zero.
590 * - On failure, negative value.
593 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
594 struct rte_eth_link *link)
596 struct rte_eth_link *dst = &(dev->data->dev_link);
597 struct rte_eth_link *src = link;
599 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
600 *(uint64_t *)src) == 0)
607 igb_intr_enable(struct rte_eth_dev *dev)
609 struct e1000_interrupt *intr =
610 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
611 struct e1000_hw *hw =
612 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
614 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
615 E1000_WRITE_FLUSH(hw);
619 igb_intr_disable(struct e1000_hw *hw)
621 E1000_WRITE_REG(hw, E1000_IMC, ~0);
622 E1000_WRITE_FLUSH(hw);
626 igbvf_intr_enable(struct rte_eth_dev *dev)
628 struct e1000_hw *hw =
629 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
631 /* only for mailbox */
632 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
633 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
634 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
635 E1000_WRITE_FLUSH(hw);
638 /* only for mailbox now. If RX/TX needed, should extend this function. */
640 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
645 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
646 tmp |= E1000_VTIVAR_VALID;
647 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
651 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
653 struct e1000_hw *hw =
654 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
656 /* Configure VF other cause ivar */
657 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
660 static inline int32_t
661 igb_pf_reset_hw(struct e1000_hw *hw)
666 status = e1000_reset_hw(hw);
668 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
669 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
670 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
671 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
672 E1000_WRITE_FLUSH(hw);
678 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
680 struct e1000_hw *hw =
681 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
684 hw->vendor_id = pci_dev->id.vendor_id;
685 hw->device_id = pci_dev->id.device_id;
686 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
687 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
689 e1000_set_mac_type(hw);
691 /* need to check if it is a vf device below */
695 igb_reset_swfw_lock(struct e1000_hw *hw)
700 * Do mac ops initialization manually here, since we will need
701 * some function pointers set by this call.
703 ret_val = e1000_init_mac_params(hw);
708 * SMBI lock should not fail in this early stage. If this is the case,
709 * it is due to an improper exit of the application.
710 * So force the release of the faulty lock.
712 if (e1000_get_hw_semaphore_generic(hw) < 0) {
713 PMD_DRV_LOG(DEBUG, "SMBI lock released");
715 e1000_put_hw_semaphore_generic(hw);
717 if (hw->mac.ops.acquire_swfw_sync != NULL) {
721 * Phy lock should not fail in this early stage. If this is the case,
722 * it is due to an improper exit of the application.
723 * So force the release of the faulty lock.
725 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
726 if (hw->bus.func > E1000_FUNC_1)
728 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
729 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
732 hw->mac.ops.release_swfw_sync(hw, mask);
735 * This one is more tricky since it is common to all ports; but
736 * swfw_sync retries last long enough (1s) to be almost sure that if
737 * lock can not be taken it is due to an improper lock of the
740 mask = E1000_SWFW_EEP_SM;
741 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
742 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
744 hw->mac.ops.release_swfw_sync(hw, mask);
747 return E1000_SUCCESS;
750 /* Remove all ntuple filters of the device */
751 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
753 struct e1000_filter_info *filter_info =
754 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
755 struct e1000_5tuple_filter *p_5tuple;
756 struct e1000_2tuple_filter *p_2tuple;
758 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
759 TAILQ_REMOVE(&filter_info->fivetuple_list,
763 filter_info->fivetuple_mask = 0;
764 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
765 TAILQ_REMOVE(&filter_info->twotuple_list,
769 filter_info->twotuple_mask = 0;
774 /* Remove all flex filters of the device */
775 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
777 struct e1000_filter_info *filter_info =
778 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
779 struct e1000_flex_filter *p_flex;
781 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
782 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
785 filter_info->flex_mask = 0;
791 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
794 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
795 struct e1000_hw *hw =
796 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
797 struct e1000_vfta * shadow_vfta =
798 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
799 struct e1000_filter_info *filter_info =
800 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
801 struct e1000_adapter *adapter =
802 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
806 eth_dev->dev_ops = ð_igb_ops;
807 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
808 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
809 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
811 /* for secondary processes, we don't initialise any further as primary
812 * has already done this work. Only check we don't need a different
814 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
815 if (eth_dev->data->scattered_rx)
816 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
820 rte_eth_copy_pci_info(eth_dev, pci_dev);
821 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
823 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
825 igb_identify_hardware(eth_dev, pci_dev);
826 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
831 e1000_get_bus_info(hw);
833 /* Reset any pending lock */
834 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
839 /* Finish initialization */
840 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
846 hw->phy.autoneg_wait_to_complete = 0;
847 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
850 if (hw->phy.media_type == e1000_media_type_copper) {
851 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
852 hw->phy.disable_polarity_correction = 0;
853 hw->phy.ms_type = e1000_ms_hw_default;
857 * Start from a known state, this is important in reading the nvm
862 /* Make sure we have a good EEPROM before we read from it */
863 if (e1000_validate_nvm_checksum(hw) < 0) {
865 * Some PCI-E parts fail the first check due to
866 * the link being in sleep state, call it again,
867 * if it fails a second time its a real issue.
869 if (e1000_validate_nvm_checksum(hw) < 0) {
870 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
876 /* Read the permanent MAC address out of the EEPROM */
877 if (e1000_read_mac_addr(hw) != 0) {
878 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
883 /* Allocate memory for storing MAC addresses */
884 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
885 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
886 if (eth_dev->data->mac_addrs == NULL) {
887 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
888 "store MAC addresses",
889 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
894 /* Copy the permanent MAC address */
895 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
897 /* initialize the vfta */
898 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
900 /* Now initialize the hardware */
901 if (igb_hardware_init(hw) != 0) {
902 PMD_INIT_LOG(ERR, "Hardware initialization failed");
903 rte_free(eth_dev->data->mac_addrs);
904 eth_dev->data->mac_addrs = NULL;
908 hw->mac.get_link_status = 1;
909 adapter->stopped = 0;
911 /* Indicate SOL/IDER usage */
912 if (e1000_check_reset_block(hw) < 0) {
913 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
917 /* initialize PF if max_vfs not zero */
918 igb_pf_host_init(eth_dev);
920 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
921 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
922 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
923 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
924 E1000_WRITE_FLUSH(hw);
926 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
927 eth_dev->data->port_id, pci_dev->id.vendor_id,
928 pci_dev->id.device_id);
930 rte_intr_callback_register(&pci_dev->intr_handle,
931 eth_igb_interrupt_handler,
934 /* enable uio/vfio intr/eventfd mapping */
935 rte_intr_enable(&pci_dev->intr_handle);
937 /* enable support intr */
938 igb_intr_enable(eth_dev);
940 /* initialize filter info */
941 memset(filter_info, 0,
942 sizeof(struct e1000_filter_info));
944 TAILQ_INIT(&filter_info->flex_list);
945 TAILQ_INIT(&filter_info->twotuple_list);
946 TAILQ_INIT(&filter_info->fivetuple_list);
948 TAILQ_INIT(&igb_filter_ntuple_list);
949 TAILQ_INIT(&igb_filter_ethertype_list);
950 TAILQ_INIT(&igb_filter_syn_list);
951 TAILQ_INIT(&igb_filter_flex_list);
952 TAILQ_INIT(&igb_flow_list);
957 igb_hw_control_release(hw);
963 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
965 struct rte_pci_device *pci_dev;
966 struct rte_intr_handle *intr_handle;
968 struct e1000_adapter *adapter =
969 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
970 struct e1000_filter_info *filter_info =
971 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
973 PMD_INIT_FUNC_TRACE();
975 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
978 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
979 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
980 intr_handle = &pci_dev->intr_handle;
982 if (adapter->stopped == 0)
983 eth_igb_close(eth_dev);
985 eth_dev->dev_ops = NULL;
986 eth_dev->rx_pkt_burst = NULL;
987 eth_dev->tx_pkt_burst = NULL;
989 /* Reset any pending lock */
990 igb_reset_swfw_lock(hw);
992 rte_free(eth_dev->data->mac_addrs);
993 eth_dev->data->mac_addrs = NULL;
995 /* uninitialize PF if max_vfs not zero */
996 igb_pf_host_uninit(eth_dev);
998 /* disable uio intr before callback unregister */
999 rte_intr_disable(intr_handle);
1000 rte_intr_callback_unregister(intr_handle,
1001 eth_igb_interrupt_handler, eth_dev);
1003 /* clear the SYN filter info */
1004 filter_info->syn_info = 0;
1006 /* clear the ethertype filters info */
1007 filter_info->ethertype_mask = 0;
1008 memset(filter_info->ethertype_filters, 0,
1009 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1011 /* remove all ntuple filters of the device */
1012 igb_ntuple_filter_uninit(eth_dev);
1014 /* remove all flex filters of the device */
1015 igb_flex_filter_uninit(eth_dev);
1017 /* clear all the filters list */
1018 igb_filterlist_flush(eth_dev);
1024 * Virtual Function device init
1027 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1029 struct rte_pci_device *pci_dev;
1030 struct rte_intr_handle *intr_handle;
1031 struct e1000_adapter *adapter =
1032 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1033 struct e1000_hw *hw =
1034 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1036 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1038 PMD_INIT_FUNC_TRACE();
1040 eth_dev->dev_ops = &igbvf_eth_dev_ops;
1041 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
1042 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
1043 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
1045 /* for secondary processes, we don't initialise any further as primary
1046 * has already done this work. Only check we don't need a different
1048 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1049 if (eth_dev->data->scattered_rx)
1050 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
1054 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1055 rte_eth_copy_pci_info(eth_dev, pci_dev);
1056 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1058 hw->device_id = pci_dev->id.device_id;
1059 hw->vendor_id = pci_dev->id.vendor_id;
1060 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1061 adapter->stopped = 0;
1063 /* Initialize the shared code (base driver) */
1064 diag = e1000_setup_init_funcs(hw, TRUE);
1066 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1071 /* init_mailbox_params */
1072 hw->mbx.ops.init_params(hw);
1074 /* Disable the interrupts for VF */
1075 igbvf_intr_disable(hw);
1077 diag = hw->mac.ops.reset_hw(hw);
1079 /* Allocate memory for storing MAC addresses */
1080 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1081 hw->mac.rar_entry_count, 0);
1082 if (eth_dev->data->mac_addrs == NULL) {
1084 "Failed to allocate %d bytes needed to store MAC "
1086 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1090 /* Generate a random MAC address, if none was assigned by PF. */
1091 if (is_zero_ether_addr(perm_addr)) {
1092 eth_random_addr(perm_addr->addr_bytes);
1093 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1094 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1095 "%02x:%02x:%02x:%02x:%02x:%02x",
1096 perm_addr->addr_bytes[0],
1097 perm_addr->addr_bytes[1],
1098 perm_addr->addr_bytes[2],
1099 perm_addr->addr_bytes[3],
1100 perm_addr->addr_bytes[4],
1101 perm_addr->addr_bytes[5]);
1104 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1106 rte_free(eth_dev->data->mac_addrs);
1107 eth_dev->data->mac_addrs = NULL;
1110 /* Copy the permanent MAC address */
1111 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1112 ð_dev->data->mac_addrs[0]);
1114 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1116 eth_dev->data->port_id, pci_dev->id.vendor_id,
1117 pci_dev->id.device_id, "igb_mac_82576_vf");
1119 intr_handle = &pci_dev->intr_handle;
1120 rte_intr_callback_register(intr_handle,
1121 eth_igbvf_interrupt_handler, eth_dev);
1127 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1129 struct e1000_adapter *adapter =
1130 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1131 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1133 PMD_INIT_FUNC_TRACE();
1135 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1138 if (adapter->stopped == 0)
1139 igbvf_dev_close(eth_dev);
1141 eth_dev->dev_ops = NULL;
1142 eth_dev->rx_pkt_burst = NULL;
1143 eth_dev->tx_pkt_burst = NULL;
1145 rte_free(eth_dev->data->mac_addrs);
1146 eth_dev->data->mac_addrs = NULL;
1148 /* disable uio intr before callback unregister */
1149 rte_intr_disable(&pci_dev->intr_handle);
1150 rte_intr_callback_unregister(&pci_dev->intr_handle,
1151 eth_igbvf_interrupt_handler,
1157 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1158 struct rte_pci_device *pci_dev)
1160 return rte_eth_dev_pci_generic_probe(pci_dev,
1161 sizeof(struct e1000_adapter), eth_igb_dev_init);
1164 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1166 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1169 static struct rte_pci_driver rte_igb_pmd = {
1170 .id_table = pci_id_igb_map,
1171 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1172 .probe = eth_igb_pci_probe,
1173 .remove = eth_igb_pci_remove,
1177 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1178 struct rte_pci_device *pci_dev)
1180 return rte_eth_dev_pci_generic_probe(pci_dev,
1181 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1184 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1186 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1190 * virtual function driver struct
1192 static struct rte_pci_driver rte_igbvf_pmd = {
1193 .id_table = pci_id_igbvf_map,
1194 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1195 .probe = eth_igbvf_pci_probe,
1196 .remove = eth_igbvf_pci_remove,
1200 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1202 struct e1000_hw *hw =
1203 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1205 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1206 rctl |= E1000_RCTL_VFE;
1207 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1211 igb_check_mq_mode(struct rte_eth_dev *dev)
1213 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1214 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1215 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1216 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1218 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1219 tx_mq_mode == ETH_MQ_TX_DCB ||
1220 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1221 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1224 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1225 /* Check multi-queue mode.
1226 * To no break software we accept ETH_MQ_RX_NONE as this might
1227 * be used to turn off VLAN filter.
1230 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1231 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1232 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1233 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1235 /* Only support one queue on VFs.
1236 * RSS together with SRIOV is not supported.
1238 PMD_INIT_LOG(ERR, "SRIOV is active,"
1239 " wrong mq_mode rx %d.",
1243 /* TX mode is not used here, so mode might be ignored.*/
1244 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1245 /* SRIOV only works in VMDq enable mode */
1246 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1247 " TX mode %d is not supported. "
1248 " Driver will behave as %d mode.",
1249 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1252 /* check valid queue number */
1253 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1254 PMD_INIT_LOG(ERR, "SRIOV is active,"
1255 " only support one queue on VFs.");
1259 /* To no break software that set invalid mode, only display
1260 * warning if invalid mode is used.
1262 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1263 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1264 rx_mq_mode != ETH_MQ_RX_RSS) {
1265 /* RSS together with VMDq not supported*/
1266 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1271 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1272 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1273 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1274 " Due to txmode is meaningless in this"
1275 " driver, just ignore.",
1283 eth_igb_configure(struct rte_eth_dev *dev)
1285 struct e1000_interrupt *intr =
1286 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1289 PMD_INIT_FUNC_TRACE();
1291 /* multipe queue mode checking */
1292 ret = igb_check_mq_mode(dev);
1294 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1299 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1300 PMD_INIT_FUNC_TRACE();
1306 eth_igb_start(struct rte_eth_dev *dev)
1308 struct e1000_hw *hw =
1309 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310 struct e1000_adapter *adapter =
1311 E1000_DEV_PRIVATE(dev->data->dev_private);
1312 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1313 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1315 uint32_t intr_vector = 0;
1321 PMD_INIT_FUNC_TRACE();
1323 /* disable uio/vfio intr/eventfd mapping */
1324 rte_intr_disable(intr_handle);
1326 /* Power up the phy. Needed to make the link go Up */
1327 eth_igb_dev_set_link_up(dev);
1330 * Packet Buffer Allocation (PBA)
1331 * Writing PBA sets the receive portion of the buffer
1332 * the remainder is used for the transmit buffer.
1334 if (hw->mac.type == e1000_82575) {
1337 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1338 E1000_WRITE_REG(hw, E1000_PBA, pba);
1341 /* Put the address into the Receive Address Array */
1342 e1000_rar_set(hw, hw->mac.addr, 0);
1344 /* Initialize the hardware */
1345 if (igb_hardware_init(hw)) {
1346 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1349 adapter->stopped = 0;
1351 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1353 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1354 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1355 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1356 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1357 E1000_WRITE_FLUSH(hw);
1359 /* configure PF module if SRIOV enabled */
1360 igb_pf_host_configure(dev);
1362 /* check and configure queue intr-vector mapping */
1363 if ((rte_intr_cap_multiple(intr_handle) ||
1364 !RTE_ETH_DEV_SRIOV(dev).active) &&
1365 dev->data->dev_conf.intr_conf.rxq != 0) {
1366 intr_vector = dev->data->nb_rx_queues;
1367 if (rte_intr_efd_enable(intr_handle, intr_vector))
1371 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1372 intr_handle->intr_vec =
1373 rte_zmalloc("intr_vec",
1374 dev->data->nb_rx_queues * sizeof(int), 0);
1375 if (intr_handle->intr_vec == NULL) {
1376 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1377 " intr_vec", dev->data->nb_rx_queues);
1382 /* confiugre msix for rx interrupt */
1383 eth_igb_configure_msix_intr(dev);
1385 /* Configure for OS presence */
1386 igb_init_manageability(hw);
1388 eth_igb_tx_init(dev);
1390 /* This can fail when allocating mbufs for descriptor rings */
1391 ret = eth_igb_rx_init(dev);
1393 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1394 igb_dev_clear_queues(dev);
1398 e1000_clear_hw_cntrs_base_generic(hw);
1401 * VLAN Offload Settings
1403 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1404 ETH_VLAN_EXTEND_MASK;
1405 eth_igb_vlan_offload_set(dev, mask);
1407 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1408 /* Enable VLAN filter since VMDq always use VLAN filter */
1409 igb_vmdq_vlan_hw_filter_enable(dev);
1412 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1413 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1414 (hw->mac.type == e1000_i211)) {
1415 /* Configure EITR with the maximum possible value (0xFFFF) */
1416 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1419 /* Setup link speed and duplex */
1420 speeds = &dev->data->dev_conf.link_speeds;
1421 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1422 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1423 hw->mac.autoneg = 1;
1426 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1429 hw->phy.autoneg_advertised = 0;
1431 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1432 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1433 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1435 goto error_invalid_config;
1437 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1438 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1441 if (*speeds & ETH_LINK_SPEED_10M) {
1442 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1445 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1446 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1449 if (*speeds & ETH_LINK_SPEED_100M) {
1450 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1453 if (*speeds & ETH_LINK_SPEED_1G) {
1454 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1457 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1458 goto error_invalid_config;
1460 /* Set/reset the mac.autoneg based on the link speed,
1464 hw->mac.autoneg = 0;
1465 hw->mac.forced_speed_duplex =
1466 hw->phy.autoneg_advertised;
1468 hw->mac.autoneg = 1;
1472 e1000_setup_link(hw);
1474 if (rte_intr_allow_others(intr_handle)) {
1475 /* check if lsc interrupt is enabled */
1476 if (dev->data->dev_conf.intr_conf.lsc != 0)
1477 eth_igb_lsc_interrupt_setup(dev, TRUE);
1479 eth_igb_lsc_interrupt_setup(dev, FALSE);
1481 rte_intr_callback_unregister(intr_handle,
1482 eth_igb_interrupt_handler,
1484 if (dev->data->dev_conf.intr_conf.lsc != 0)
1485 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1486 " no intr multiplex");
1489 /* check if rxq interrupt is enabled */
1490 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1491 rte_intr_dp_is_en(intr_handle))
1492 eth_igb_rxq_interrupt_setup(dev);
1494 /* enable uio/vfio intr/eventfd mapping */
1495 rte_intr_enable(intr_handle);
1497 /* resume enabled intr since hw reset */
1498 igb_intr_enable(dev);
1500 /* restore all types filter */
1501 igb_filter_restore(dev);
1503 PMD_INIT_LOG(DEBUG, "<<");
1507 error_invalid_config:
1508 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1509 dev->data->dev_conf.link_speeds, dev->data->port_id);
1510 igb_dev_clear_queues(dev);
1514 /*********************************************************************
1516 * This routine disables all traffic on the adapter by issuing a
1517 * global reset on the MAC.
1519 **********************************************************************/
1521 eth_igb_stop(struct rte_eth_dev *dev)
1523 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1525 struct rte_eth_link link;
1526 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1528 igb_intr_disable(hw);
1530 /* disable intr eventfd mapping */
1531 rte_intr_disable(intr_handle);
1533 igb_pf_reset_hw(hw);
1534 E1000_WRITE_REG(hw, E1000_WUC, 0);
1536 /* Set bit for Go Link disconnect */
1537 if (hw->mac.type >= e1000_82580) {
1540 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1541 phpm_reg |= E1000_82580_PM_GO_LINKD;
1542 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1545 /* Power down the phy. Needed to make the link go Down */
1546 eth_igb_dev_set_link_down(dev);
1548 igb_dev_clear_queues(dev);
1550 /* clear the recorded link status */
1551 memset(&link, 0, sizeof(link));
1552 rte_igb_dev_atomic_write_link_status(dev, &link);
1554 if (!rte_intr_allow_others(intr_handle))
1555 /* resume to the default handler */
1556 rte_intr_callback_register(intr_handle,
1557 eth_igb_interrupt_handler,
1560 /* Clean datapath event and queue/vec mapping */
1561 rte_intr_efd_disable(intr_handle);
1562 if (intr_handle->intr_vec != NULL) {
1563 rte_free(intr_handle->intr_vec);
1564 intr_handle->intr_vec = NULL;
1569 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1571 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1573 if (hw->phy.media_type == e1000_media_type_copper)
1574 e1000_power_up_phy(hw);
1576 e1000_power_up_fiber_serdes_link(hw);
1582 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1584 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586 if (hw->phy.media_type == e1000_media_type_copper)
1587 e1000_power_down_phy(hw);
1589 e1000_shutdown_fiber_serdes_link(hw);
1595 eth_igb_close(struct rte_eth_dev *dev)
1597 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598 struct e1000_adapter *adapter =
1599 E1000_DEV_PRIVATE(dev->data->dev_private);
1600 struct rte_eth_link link;
1601 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1602 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1605 adapter->stopped = 1;
1607 e1000_phy_hw_reset(hw);
1608 igb_release_manageability(hw);
1609 igb_hw_control_release(hw);
1611 /* Clear bit for Go Link disconnect */
1612 if (hw->mac.type >= e1000_82580) {
1615 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1616 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1617 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1620 igb_dev_free_queues(dev);
1622 if (intr_handle->intr_vec) {
1623 rte_free(intr_handle->intr_vec);
1624 intr_handle->intr_vec = NULL;
1627 memset(&link, 0, sizeof(link));
1628 rte_igb_dev_atomic_write_link_status(dev, &link);
1632 igb_get_rx_buffer_size(struct e1000_hw *hw)
1634 uint32_t rx_buf_size;
1635 if (hw->mac.type == e1000_82576) {
1636 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1637 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1638 /* PBS needs to be translated according to a lookup table */
1639 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1640 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1641 rx_buf_size = (rx_buf_size << 10);
1642 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1643 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1645 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1651 /*********************************************************************
1653 * Initialize the hardware
1655 **********************************************************************/
1657 igb_hardware_init(struct e1000_hw *hw)
1659 uint32_t rx_buf_size;
1662 /* Let the firmware know the OS is in control */
1663 igb_hw_control_acquire(hw);
1666 * These parameters control the automatic generation (Tx) and
1667 * response (Rx) to Ethernet PAUSE frames.
1668 * - High water mark should allow for at least two standard size (1518)
1669 * frames to be received after sending an XOFF.
1670 * - Low water mark works best when it is very near the high water mark.
1671 * This allows the receiver to restart by sending XON when it has
1672 * drained a bit. Here we use an arbitrary value of 1500 which will
1673 * restart after one full frame is pulled from the buffer. There
1674 * could be several smaller frames in the buffer and if so they will
1675 * not trigger the XON until their total number reduces the buffer
1677 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1679 rx_buf_size = igb_get_rx_buffer_size(hw);
1681 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1682 hw->fc.low_water = hw->fc.high_water - 1500;
1683 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1684 hw->fc.send_xon = 1;
1686 /* Set Flow control, use the tunable location if sane */
1687 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1688 hw->fc.requested_mode = igb_fc_setting;
1690 hw->fc.requested_mode = e1000_fc_none;
1692 /* Issue a global reset */
1693 igb_pf_reset_hw(hw);
1694 E1000_WRITE_REG(hw, E1000_WUC, 0);
1696 diag = e1000_init_hw(hw);
1700 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1701 e1000_get_phy_info(hw);
1702 e1000_check_for_link(hw);
1707 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1709 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1713 uint64_t old_gprc = stats->gprc;
1714 uint64_t old_gptc = stats->gptc;
1715 uint64_t old_tpr = stats->tpr;
1716 uint64_t old_tpt = stats->tpt;
1717 uint64_t old_rpthc = stats->rpthc;
1718 uint64_t old_hgptc = stats->hgptc;
1720 if(hw->phy.media_type == e1000_media_type_copper ||
1721 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1723 E1000_READ_REG(hw,E1000_SYMERRS);
1724 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1727 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1728 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1729 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1730 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1732 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1733 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1734 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1735 stats->dc += E1000_READ_REG(hw, E1000_DC);
1736 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1737 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1738 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1740 ** For watchdog management we need to know if we have been
1741 ** paused during the last interval, so capture that here.
1743 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1744 stats->xoffrxc += pause_frames;
1745 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1746 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1747 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1748 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1749 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1750 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1751 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1752 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1753 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1754 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1755 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1756 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1758 /* For the 64-bit byte counters the low dword must be read first. */
1759 /* Both registers clear on the read of the high dword */
1761 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1762 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1763 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1764 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1765 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1766 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1767 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1769 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1770 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1771 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1772 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1773 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1775 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1776 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1778 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1779 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1780 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1781 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1782 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1783 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1785 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1786 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1787 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1788 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1789 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1790 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1791 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1792 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1794 /* Interrupt Counts */
1796 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1797 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1798 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1799 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1800 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1801 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1802 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1803 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1804 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1806 /* Host to Card Statistics */
1808 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1809 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1810 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1811 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1812 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1813 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1814 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1815 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1816 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1817 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1818 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1819 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1820 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1821 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1822 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1823 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1825 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1826 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1827 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1828 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1829 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1830 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1834 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1836 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837 struct e1000_hw_stats *stats =
1838 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1840 igb_read_stats_registers(hw, stats);
1842 if (rte_stats == NULL)
1846 rte_stats->imissed = stats->mpc;
1847 rte_stats->ierrors = stats->crcerrs +
1848 stats->rlec + stats->ruc + stats->roc +
1849 stats->rxerrc + stats->algnerrc + stats->cexterr;
1852 rte_stats->oerrors = stats->ecol + stats->latecol;
1854 rte_stats->ipackets = stats->gprc;
1855 rte_stats->opackets = stats->gptc;
1856 rte_stats->ibytes = stats->gorc;
1857 rte_stats->obytes = stats->gotc;
1861 eth_igb_stats_reset(struct rte_eth_dev *dev)
1863 struct e1000_hw_stats *hw_stats =
1864 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1866 /* HW registers are cleared on read */
1867 eth_igb_stats_get(dev, NULL);
1869 /* Reset software totals */
1870 memset(hw_stats, 0, sizeof(*hw_stats));
1874 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1876 struct e1000_hw_stats *stats =
1877 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1879 /* HW registers are cleared on read */
1880 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1882 /* Reset software totals */
1883 memset(stats, 0, sizeof(*stats));
1886 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1887 struct rte_eth_xstat_name *xstats_names,
1888 __rte_unused unsigned int size)
1892 if (xstats_names == NULL)
1893 return IGB_NB_XSTATS;
1895 /* Note: limit checked in rte_eth_xstats_names() */
1897 for (i = 0; i < IGB_NB_XSTATS; i++) {
1898 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1899 "%s", rte_igb_stats_strings[i].name);
1902 return IGB_NB_XSTATS;
1905 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1906 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1912 if (xstats_names == NULL)
1913 return IGB_NB_XSTATS;
1915 for (i = 0; i < IGB_NB_XSTATS; i++)
1916 snprintf(xstats_names[i].name,
1917 sizeof(xstats_names[i].name),
1918 "%s", rte_igb_stats_strings[i].name);
1920 return IGB_NB_XSTATS;
1923 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1925 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1928 for (i = 0; i < limit; i++) {
1929 if (ids[i] >= IGB_NB_XSTATS) {
1930 PMD_INIT_LOG(ERR, "id value isn't valid");
1933 strcpy(xstats_names[i].name,
1934 xstats_names_copy[ids[i]].name);
1941 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1944 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945 struct e1000_hw_stats *hw_stats =
1946 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1949 if (n < IGB_NB_XSTATS)
1950 return IGB_NB_XSTATS;
1952 igb_read_stats_registers(hw, hw_stats);
1954 /* If this is a reset xstats is NULL, and we have cleared the
1955 * registers by reading them.
1960 /* Extended stats */
1961 for (i = 0; i < IGB_NB_XSTATS; i++) {
1963 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1964 rte_igb_stats_strings[i].offset);
1967 return IGB_NB_XSTATS;
1971 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1972 uint64_t *values, unsigned int n)
1977 struct e1000_hw *hw =
1978 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979 struct e1000_hw_stats *hw_stats =
1980 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1982 if (n < IGB_NB_XSTATS)
1983 return IGB_NB_XSTATS;
1985 igb_read_stats_registers(hw, hw_stats);
1987 /* If this is a reset xstats is NULL, and we have cleared the
1988 * registers by reading them.
1993 /* Extended stats */
1994 for (i = 0; i < IGB_NB_XSTATS; i++)
1995 values[i] = *(uint64_t *)(((char *)hw_stats) +
1996 rte_igb_stats_strings[i].offset);
1998 return IGB_NB_XSTATS;
2001 uint64_t values_copy[IGB_NB_XSTATS];
2003 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2006 for (i = 0; i < n; i++) {
2007 if (ids[i] >= IGB_NB_XSTATS) {
2008 PMD_INIT_LOG(ERR, "id value isn't valid");
2011 values[i] = values_copy[ids[i]];
2018 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2020 /* Good Rx packets, include VF loopback */
2021 UPDATE_VF_STAT(E1000_VFGPRC,
2022 hw_stats->last_gprc, hw_stats->gprc);
2024 /* Good Rx octets, include VF loopback */
2025 UPDATE_VF_STAT(E1000_VFGORC,
2026 hw_stats->last_gorc, hw_stats->gorc);
2028 /* Good Tx packets, include VF loopback */
2029 UPDATE_VF_STAT(E1000_VFGPTC,
2030 hw_stats->last_gptc, hw_stats->gptc);
2032 /* Good Tx octets, include VF loopback */
2033 UPDATE_VF_STAT(E1000_VFGOTC,
2034 hw_stats->last_gotc, hw_stats->gotc);
2036 /* Rx Multicst packets */
2037 UPDATE_VF_STAT(E1000_VFMPRC,
2038 hw_stats->last_mprc, hw_stats->mprc);
2040 /* Good Rx loopback packets */
2041 UPDATE_VF_STAT(E1000_VFGPRLBC,
2042 hw_stats->last_gprlbc, hw_stats->gprlbc);
2044 /* Good Rx loopback octets */
2045 UPDATE_VF_STAT(E1000_VFGORLBC,
2046 hw_stats->last_gorlbc, hw_stats->gorlbc);
2048 /* Good Tx loopback packets */
2049 UPDATE_VF_STAT(E1000_VFGPTLBC,
2050 hw_stats->last_gptlbc, hw_stats->gptlbc);
2052 /* Good Tx loopback octets */
2053 UPDATE_VF_STAT(E1000_VFGOTLBC,
2054 hw_stats->last_gotlbc, hw_stats->gotlbc);
2057 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2058 struct rte_eth_xstat_name *xstats_names,
2059 __rte_unused unsigned limit)
2063 if (xstats_names != NULL)
2064 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2065 snprintf(xstats_names[i].name,
2066 sizeof(xstats_names[i].name), "%s",
2067 rte_igbvf_stats_strings[i].name);
2069 return IGBVF_NB_XSTATS;
2073 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2076 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2078 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2081 if (n < IGBVF_NB_XSTATS)
2082 return IGBVF_NB_XSTATS;
2084 igbvf_read_stats_registers(hw, hw_stats);
2089 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2091 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2092 rte_igbvf_stats_strings[i].offset);
2095 return IGBVF_NB_XSTATS;
2099 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2101 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2103 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2105 igbvf_read_stats_registers(hw, hw_stats);
2107 if (rte_stats == NULL)
2110 rte_stats->ipackets = hw_stats->gprc;
2111 rte_stats->ibytes = hw_stats->gorc;
2112 rte_stats->opackets = hw_stats->gptc;
2113 rte_stats->obytes = hw_stats->gotc;
2117 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2119 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2120 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2122 /* Sync HW register to the last stats */
2123 eth_igbvf_stats_get(dev, NULL);
2125 /* reset HW current stats*/
2126 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2127 offsetof(struct e1000_vf_stats, gprc));
2131 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2134 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135 struct e1000_fw_version fw;
2138 e1000_get_fw_version(hw, &fw);
2140 switch (hw->mac.type) {
2143 if (!(e1000_get_flash_presence_i210(hw))) {
2144 ret = snprintf(fw_version, fw_size,
2146 fw.invm_major, fw.invm_minor,
2152 /* if option rom is valid, display its version too */
2154 ret = snprintf(fw_version, fw_size,
2155 "%d.%d, 0x%08x, %d.%d.%d",
2156 fw.eep_major, fw.eep_minor, fw.etrack_id,
2157 fw.or_major, fw.or_build, fw.or_patch);
2160 if (fw.etrack_id != 0X0000) {
2161 ret = snprintf(fw_version, fw_size,
2163 fw.eep_major, fw.eep_minor,
2166 ret = snprintf(fw_version, fw_size,
2168 fw.eep_major, fw.eep_minor,
2175 ret += 1; /* add the size of '\0' */
2176 if (fw_size < (u32)ret)
2183 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2185 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2188 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2189 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2190 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2191 dev_info->rx_offload_capa =
2192 DEV_RX_OFFLOAD_VLAN_STRIP |
2193 DEV_RX_OFFLOAD_IPV4_CKSUM |
2194 DEV_RX_OFFLOAD_UDP_CKSUM |
2195 DEV_RX_OFFLOAD_TCP_CKSUM;
2196 dev_info->tx_offload_capa =
2197 DEV_TX_OFFLOAD_VLAN_INSERT |
2198 DEV_TX_OFFLOAD_IPV4_CKSUM |
2199 DEV_TX_OFFLOAD_UDP_CKSUM |
2200 DEV_TX_OFFLOAD_TCP_CKSUM |
2201 DEV_TX_OFFLOAD_SCTP_CKSUM |
2202 DEV_TX_OFFLOAD_TCP_TSO;
2204 switch (hw->mac.type) {
2206 dev_info->max_rx_queues = 4;
2207 dev_info->max_tx_queues = 4;
2208 dev_info->max_vmdq_pools = 0;
2212 dev_info->max_rx_queues = 16;
2213 dev_info->max_tx_queues = 16;
2214 dev_info->max_vmdq_pools = ETH_8_POOLS;
2215 dev_info->vmdq_queue_num = 16;
2219 dev_info->max_rx_queues = 8;
2220 dev_info->max_tx_queues = 8;
2221 dev_info->max_vmdq_pools = ETH_8_POOLS;
2222 dev_info->vmdq_queue_num = 8;
2226 dev_info->max_rx_queues = 8;
2227 dev_info->max_tx_queues = 8;
2228 dev_info->max_vmdq_pools = ETH_8_POOLS;
2229 dev_info->vmdq_queue_num = 8;
2233 dev_info->max_rx_queues = 8;
2234 dev_info->max_tx_queues = 8;
2238 dev_info->max_rx_queues = 4;
2239 dev_info->max_tx_queues = 4;
2240 dev_info->max_vmdq_pools = 0;
2244 dev_info->max_rx_queues = 2;
2245 dev_info->max_tx_queues = 2;
2246 dev_info->max_vmdq_pools = 0;
2250 /* Should not happen */
2253 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2254 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2255 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2257 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2259 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2260 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2261 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2263 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2267 dev_info->default_txconf = (struct rte_eth_txconf) {
2269 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2270 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2271 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2276 dev_info->rx_desc_lim = rx_desc_lim;
2277 dev_info->tx_desc_lim = tx_desc_lim;
2279 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2280 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2284 static const uint32_t *
2285 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2287 static const uint32_t ptypes[] = {
2288 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2291 RTE_PTYPE_L3_IPV4_EXT,
2293 RTE_PTYPE_L3_IPV6_EXT,
2297 RTE_PTYPE_TUNNEL_IP,
2298 RTE_PTYPE_INNER_L3_IPV6,
2299 RTE_PTYPE_INNER_L3_IPV6_EXT,
2300 RTE_PTYPE_INNER_L4_TCP,
2301 RTE_PTYPE_INNER_L4_UDP,
2305 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2306 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2312 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2314 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2317 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2318 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2319 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2320 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2321 DEV_RX_OFFLOAD_IPV4_CKSUM |
2322 DEV_RX_OFFLOAD_UDP_CKSUM |
2323 DEV_RX_OFFLOAD_TCP_CKSUM;
2324 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2325 DEV_TX_OFFLOAD_IPV4_CKSUM |
2326 DEV_TX_OFFLOAD_UDP_CKSUM |
2327 DEV_TX_OFFLOAD_TCP_CKSUM |
2328 DEV_TX_OFFLOAD_SCTP_CKSUM |
2329 DEV_TX_OFFLOAD_TCP_TSO;
2330 switch (hw->mac.type) {
2332 dev_info->max_rx_queues = 2;
2333 dev_info->max_tx_queues = 2;
2335 case e1000_vfadapt_i350:
2336 dev_info->max_rx_queues = 1;
2337 dev_info->max_tx_queues = 1;
2340 /* Should not happen */
2344 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2346 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2347 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2348 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2350 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2354 dev_info->default_txconf = (struct rte_eth_txconf) {
2356 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2357 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2358 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2363 dev_info->rx_desc_lim = rx_desc_lim;
2364 dev_info->tx_desc_lim = tx_desc_lim;
2367 /* return 0 means link status changed, -1 means not changed */
2369 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2371 struct e1000_hw *hw =
2372 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373 struct rte_eth_link link, old;
2374 int link_check, count;
2377 hw->mac.get_link_status = 1;
2379 /* possible wait-to-complete in up to 9 seconds */
2380 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2381 /* Read the real link status */
2382 switch (hw->phy.media_type) {
2383 case e1000_media_type_copper:
2384 /* Do the work to read phy */
2385 e1000_check_for_link(hw);
2386 link_check = !hw->mac.get_link_status;
2389 case e1000_media_type_fiber:
2390 e1000_check_for_link(hw);
2391 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2395 case e1000_media_type_internal_serdes:
2396 e1000_check_for_link(hw);
2397 link_check = hw->mac.serdes_has_link;
2400 /* VF device is type_unknown */
2401 case e1000_media_type_unknown:
2402 eth_igbvf_link_update(hw);
2403 link_check = !hw->mac.get_link_status;
2409 if (link_check || wait_to_complete == 0)
2411 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2413 memset(&link, 0, sizeof(link));
2414 rte_igb_dev_atomic_read_link_status(dev, &link);
2417 /* Now we check if a transition has happened */
2419 uint16_t duplex, speed;
2420 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2421 link.link_duplex = (duplex == FULL_DUPLEX) ?
2422 ETH_LINK_FULL_DUPLEX :
2423 ETH_LINK_HALF_DUPLEX;
2424 link.link_speed = speed;
2425 link.link_status = ETH_LINK_UP;
2426 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2427 ETH_LINK_SPEED_FIXED);
2428 } else if (!link_check) {
2429 link.link_speed = 0;
2430 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2431 link.link_status = ETH_LINK_DOWN;
2432 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2434 rte_igb_dev_atomic_write_link_status(dev, &link);
2437 if (old.link_status == link.link_status)
2445 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2446 * For ASF and Pass Through versions of f/w this means
2447 * that the driver is loaded.
2450 igb_hw_control_acquire(struct e1000_hw *hw)
2454 /* Let firmware know the driver has taken over */
2455 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2456 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2460 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2461 * For ASF and Pass Through versions of f/w this means that the
2462 * driver is no longer loaded.
2465 igb_hw_control_release(struct e1000_hw *hw)
2469 /* Let firmware taken over control of h/w */
2470 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2471 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2472 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2476 * Bit of a misnomer, what this really means is
2477 * to enable OS management of the system... aka
2478 * to disable special hardware management features.
2481 igb_init_manageability(struct e1000_hw *hw)
2483 if (e1000_enable_mng_pass_thru(hw)) {
2484 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2485 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2487 /* disable hardware interception of ARP */
2488 manc &= ~(E1000_MANC_ARP_EN);
2490 /* enable receiving management packets to the host */
2491 manc |= E1000_MANC_EN_MNG2HOST;
2492 manc2h |= 1 << 5; /* Mng Port 623 */
2493 manc2h |= 1 << 6; /* Mng Port 664 */
2494 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2495 E1000_WRITE_REG(hw, E1000_MANC, manc);
2500 igb_release_manageability(struct e1000_hw *hw)
2502 if (e1000_enable_mng_pass_thru(hw)) {
2503 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2505 manc |= E1000_MANC_ARP_EN;
2506 manc &= ~E1000_MANC_EN_MNG2HOST;
2508 E1000_WRITE_REG(hw, E1000_MANC, manc);
2513 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2515 struct e1000_hw *hw =
2516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519 rctl = E1000_READ_REG(hw, E1000_RCTL);
2520 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2521 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2525 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2527 struct e1000_hw *hw =
2528 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531 rctl = E1000_READ_REG(hw, E1000_RCTL);
2532 rctl &= (~E1000_RCTL_UPE);
2533 if (dev->data->all_multicast == 1)
2534 rctl |= E1000_RCTL_MPE;
2536 rctl &= (~E1000_RCTL_MPE);
2537 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2541 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2543 struct e1000_hw *hw =
2544 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547 rctl = E1000_READ_REG(hw, E1000_RCTL);
2548 rctl |= E1000_RCTL_MPE;
2549 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2553 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2555 struct e1000_hw *hw =
2556 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2559 if (dev->data->promiscuous == 1)
2560 return; /* must remain in all_multicast mode */
2561 rctl = E1000_READ_REG(hw, E1000_RCTL);
2562 rctl &= (~E1000_RCTL_MPE);
2563 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2567 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2569 struct e1000_hw *hw =
2570 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2571 struct e1000_vfta * shadow_vfta =
2572 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2577 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2578 E1000_VFTA_ENTRY_MASK);
2579 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2580 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2585 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2587 /* update local VFTA copy */
2588 shadow_vfta->vfta[vid_idx] = vfta;
2594 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2595 enum rte_vlan_type vlan_type,
2598 struct e1000_hw *hw =
2599 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2602 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2603 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2605 /* only outer TPID of double VLAN can be configured*/
2606 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2607 reg = E1000_READ_REG(hw, E1000_VET);
2608 reg = (reg & (~E1000_VET_VET_EXT)) |
2609 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2610 E1000_WRITE_REG(hw, E1000_VET, reg);
2615 /* all other TPID values are read-only*/
2616 PMD_DRV_LOG(ERR, "Not supported");
2622 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2624 struct e1000_hw *hw =
2625 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628 /* Filter Table Disable */
2629 reg = E1000_READ_REG(hw, E1000_RCTL);
2630 reg &= ~E1000_RCTL_CFIEN;
2631 reg &= ~E1000_RCTL_VFE;
2632 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2636 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2638 struct e1000_hw *hw =
2639 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640 struct e1000_vfta * shadow_vfta =
2641 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2645 /* Filter Table Enable, CFI not used for packet acceptance */
2646 reg = E1000_READ_REG(hw, E1000_RCTL);
2647 reg &= ~E1000_RCTL_CFIEN;
2648 reg |= E1000_RCTL_VFE;
2649 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2651 /* restore VFTA table */
2652 for (i = 0; i < IGB_VFTA_SIZE; i++)
2653 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2657 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2659 struct e1000_hw *hw =
2660 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2663 /* VLAN Mode Disable */
2664 reg = E1000_READ_REG(hw, E1000_CTRL);
2665 reg &= ~E1000_CTRL_VME;
2666 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2670 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2672 struct e1000_hw *hw =
2673 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2676 /* VLAN Mode Enable */
2677 reg = E1000_READ_REG(hw, E1000_CTRL);
2678 reg |= E1000_CTRL_VME;
2679 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2683 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2685 struct e1000_hw *hw =
2686 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689 /* CTRL_EXT: Extended VLAN */
2690 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2691 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2692 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2694 /* Update maximum packet length */
2695 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2696 E1000_WRITE_REG(hw, E1000_RLPML,
2697 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2702 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2704 struct e1000_hw *hw =
2705 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708 /* CTRL_EXT: Extended VLAN */
2709 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2710 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2711 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2713 /* Update maximum packet length */
2714 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2715 E1000_WRITE_REG(hw, E1000_RLPML,
2716 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2721 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2723 if(mask & ETH_VLAN_STRIP_MASK){
2724 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2725 igb_vlan_hw_strip_enable(dev);
2727 igb_vlan_hw_strip_disable(dev);
2730 if(mask & ETH_VLAN_FILTER_MASK){
2731 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2732 igb_vlan_hw_filter_enable(dev);
2734 igb_vlan_hw_filter_disable(dev);
2737 if(mask & ETH_VLAN_EXTEND_MASK){
2738 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2739 igb_vlan_hw_extend_enable(dev);
2741 igb_vlan_hw_extend_disable(dev);
2747 * It enables the interrupt mask and then enable the interrupt.
2750 * Pointer to struct rte_eth_dev.
2755 * - On success, zero.
2756 * - On failure, a negative value.
2759 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2761 struct e1000_interrupt *intr =
2762 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2765 intr->mask |= E1000_ICR_LSC;
2767 intr->mask &= ~E1000_ICR_LSC;
2772 /* It clears the interrupt causes and enables the interrupt.
2773 * It will be called once only during nic initialized.
2776 * Pointer to struct rte_eth_dev.
2779 * - On success, zero.
2780 * - On failure, a negative value.
2782 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2784 uint32_t mask, regval;
2785 struct e1000_hw *hw =
2786 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2787 struct rte_eth_dev_info dev_info;
2789 memset(&dev_info, 0, sizeof(dev_info));
2790 eth_igb_infos_get(dev, &dev_info);
2792 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2793 regval = E1000_READ_REG(hw, E1000_EIMS);
2794 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2800 * It reads ICR and gets interrupt causes, check it and set a bit flag
2801 * to update link status.
2804 * Pointer to struct rte_eth_dev.
2807 * - On success, zero.
2808 * - On failure, a negative value.
2811 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2814 struct e1000_hw *hw =
2815 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2816 struct e1000_interrupt *intr =
2817 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2819 igb_intr_disable(hw);
2821 /* read-on-clear nic registers here */
2822 icr = E1000_READ_REG(hw, E1000_ICR);
2825 if (icr & E1000_ICR_LSC) {
2826 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2829 if (icr & E1000_ICR_VMMB)
2830 intr->flags |= E1000_FLAG_MAILBOX;
2836 * It executes link_update after knowing an interrupt is prsent.
2839 * Pointer to struct rte_eth_dev.
2842 * - On success, zero.
2843 * - On failure, a negative value.
2846 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2847 struct rte_intr_handle *intr_handle)
2849 struct e1000_hw *hw =
2850 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2851 struct e1000_interrupt *intr =
2852 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2853 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2854 uint32_t tctl, rctl;
2855 struct rte_eth_link link;
2858 if (intr->flags & E1000_FLAG_MAILBOX) {
2859 igb_pf_mbx_process(dev);
2860 intr->flags &= ~E1000_FLAG_MAILBOX;
2863 igb_intr_enable(dev);
2864 rte_intr_enable(intr_handle);
2866 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2867 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2869 /* set get_link_status to check register later */
2870 hw->mac.get_link_status = 1;
2871 ret = eth_igb_link_update(dev, 0);
2873 /* check if link has changed */
2877 memset(&link, 0, sizeof(link));
2878 rte_igb_dev_atomic_read_link_status(dev, &link);
2879 if (link.link_status) {
2881 " Port %d: Link Up - speed %u Mbps - %s",
2883 (unsigned)link.link_speed,
2884 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2885 "full-duplex" : "half-duplex");
2887 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2888 dev->data->port_id);
2891 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2892 pci_dev->addr.domain,
2894 pci_dev->addr.devid,
2895 pci_dev->addr.function);
2896 tctl = E1000_READ_REG(hw, E1000_TCTL);
2897 rctl = E1000_READ_REG(hw, E1000_RCTL);
2898 if (link.link_status) {
2900 tctl |= E1000_TCTL_EN;
2901 rctl |= E1000_RCTL_EN;
2904 tctl &= ~E1000_TCTL_EN;
2905 rctl &= ~E1000_RCTL_EN;
2907 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2908 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2909 E1000_WRITE_FLUSH(hw);
2910 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2918 * Interrupt handler which shall be registered at first.
2921 * Pointer to interrupt handle.
2923 * The address of parameter (struct rte_eth_dev *) regsitered before.
2929 eth_igb_interrupt_handler(void *param)
2931 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2933 eth_igb_interrupt_get_status(dev);
2934 eth_igb_interrupt_action(dev, dev->intr_handle);
2938 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2941 struct e1000_hw *hw =
2942 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943 struct e1000_interrupt *intr =
2944 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2946 igbvf_intr_disable(hw);
2948 /* read-on-clear nic registers here */
2949 eicr = E1000_READ_REG(hw, E1000_EICR);
2952 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2953 intr->flags |= E1000_FLAG_MAILBOX;
2958 void igbvf_mbx_process(struct rte_eth_dev *dev)
2960 struct e1000_hw *hw =
2961 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962 struct e1000_mbx_info *mbx = &hw->mbx;
2965 if (mbx->ops.read(hw, &in_msg, 1, 0))
2968 /* PF reset VF event */
2969 if (in_msg == E1000_PF_CONTROL_MSG)
2970 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2975 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2977 struct e1000_interrupt *intr =
2978 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2980 if (intr->flags & E1000_FLAG_MAILBOX) {
2981 igbvf_mbx_process(dev);
2982 intr->flags &= ~E1000_FLAG_MAILBOX;
2985 igbvf_intr_enable(dev);
2986 rte_intr_enable(intr_handle);
2992 eth_igbvf_interrupt_handler(void *param)
2994 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2996 eth_igbvf_interrupt_get_status(dev);
2997 eth_igbvf_interrupt_action(dev, dev->intr_handle);
3001 eth_igb_led_on(struct rte_eth_dev *dev)
3003 struct e1000_hw *hw;
3005 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3006 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3010 eth_igb_led_off(struct rte_eth_dev *dev)
3012 struct e1000_hw *hw;
3014 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3019 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3021 struct e1000_hw *hw;
3026 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027 fc_conf->pause_time = hw->fc.pause_time;
3028 fc_conf->high_water = hw->fc.high_water;
3029 fc_conf->low_water = hw->fc.low_water;
3030 fc_conf->send_xon = hw->fc.send_xon;
3031 fc_conf->autoneg = hw->mac.autoneg;
3034 * Return rx_pause and tx_pause status according to actual setting of
3035 * the TFCE and RFCE bits in the CTRL register.
3037 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3038 if (ctrl & E1000_CTRL_TFCE)
3043 if (ctrl & E1000_CTRL_RFCE)
3048 if (rx_pause && tx_pause)
3049 fc_conf->mode = RTE_FC_FULL;
3051 fc_conf->mode = RTE_FC_RX_PAUSE;
3053 fc_conf->mode = RTE_FC_TX_PAUSE;
3055 fc_conf->mode = RTE_FC_NONE;
3061 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3063 struct e1000_hw *hw;
3065 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3071 uint32_t rx_buf_size;
3072 uint32_t max_high_water;
3075 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076 if (fc_conf->autoneg != hw->mac.autoneg)
3078 rx_buf_size = igb_get_rx_buffer_size(hw);
3079 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3081 /* At least reserve one Ethernet frame for watermark */
3082 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3083 if ((fc_conf->high_water > max_high_water) ||
3084 (fc_conf->high_water < fc_conf->low_water)) {
3085 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3086 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3090 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3091 hw->fc.pause_time = fc_conf->pause_time;
3092 hw->fc.high_water = fc_conf->high_water;
3093 hw->fc.low_water = fc_conf->low_water;
3094 hw->fc.send_xon = fc_conf->send_xon;
3096 err = e1000_setup_link_generic(hw);
3097 if (err == E1000_SUCCESS) {
3099 /* check if we want to forward MAC frames - driver doesn't have native
3100 * capability to do that, so we'll write the registers ourselves */
3102 rctl = E1000_READ_REG(hw, E1000_RCTL);
3104 /* set or clear MFLCN.PMCF bit depending on configuration */
3105 if (fc_conf->mac_ctrl_frame_fwd != 0)
3106 rctl |= E1000_RCTL_PMCF;
3108 rctl &= ~E1000_RCTL_PMCF;
3110 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3111 E1000_WRITE_FLUSH(hw);
3116 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3120 #define E1000_RAH_POOLSEL_SHIFT (18)
3122 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3123 uint32_t index, uint32_t pool)
3125 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3128 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3129 rah = E1000_READ_REG(hw, E1000_RAH(index));
3130 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3131 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3136 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3138 uint8_t addr[ETHER_ADDR_LEN];
3139 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3141 memset(addr, 0, sizeof(addr));
3143 e1000_rar_set(hw, addr, index);
3147 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3148 struct ether_addr *addr)
3150 eth_igb_rar_clear(dev, 0);
3152 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3155 * Virtual Function operations
3158 igbvf_intr_disable(struct e1000_hw *hw)
3160 PMD_INIT_FUNC_TRACE();
3162 /* Clear interrupt mask to stop from interrupts being generated */
3163 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3165 E1000_WRITE_FLUSH(hw);
3169 igbvf_stop_adapter(struct rte_eth_dev *dev)
3173 struct rte_eth_dev_info dev_info;
3174 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176 memset(&dev_info, 0, sizeof(dev_info));
3177 eth_igbvf_infos_get(dev, &dev_info);
3179 /* Clear interrupt mask to stop from interrupts being generated */
3180 igbvf_intr_disable(hw);
3182 /* Clear any pending interrupts, flush previous writes */
3183 E1000_READ_REG(hw, E1000_EICR);
3185 /* Disable the transmit unit. Each queue must be disabled. */
3186 for (i = 0; i < dev_info.max_tx_queues; i++)
3187 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3189 /* Disable the receive unit by stopping each queue */
3190 for (i = 0; i < dev_info.max_rx_queues; i++) {
3191 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3192 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3193 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3194 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3198 /* flush all queues disables */
3199 E1000_WRITE_FLUSH(hw);
3203 static int eth_igbvf_link_update(struct e1000_hw *hw)
3205 struct e1000_mbx_info *mbx = &hw->mbx;
3206 struct e1000_mac_info *mac = &hw->mac;
3207 int ret_val = E1000_SUCCESS;
3209 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3212 * We only want to run this if there has been a rst asserted.
3213 * in this case that could mean a link change, device reset,
3214 * or a virtual function reset
3217 /* If we were hit with a reset or timeout drop the link */
3218 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3219 mac->get_link_status = TRUE;
3221 if (!mac->get_link_status)
3224 /* if link status is down no point in checking to see if pf is up */
3225 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3228 /* if we passed all the tests above then the link is up and we no
3229 * longer need to check for link */
3230 mac->get_link_status = FALSE;
3238 igbvf_dev_configure(struct rte_eth_dev *dev)
3240 struct rte_eth_conf* conf = &dev->data->dev_conf;
3242 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3243 dev->data->port_id);
3246 * VF has no ability to enable/disable HW CRC
3247 * Keep the persistent behavior the same as Host PF
3249 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3250 if (!conf->rxmode.hw_strip_crc) {
3251 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3252 conf->rxmode.hw_strip_crc = 1;
3255 if (conf->rxmode.hw_strip_crc) {
3256 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3257 conf->rxmode.hw_strip_crc = 0;
3265 igbvf_dev_start(struct rte_eth_dev *dev)
3267 struct e1000_hw *hw =
3268 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269 struct e1000_adapter *adapter =
3270 E1000_DEV_PRIVATE(dev->data->dev_private);
3271 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3272 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3274 uint32_t intr_vector = 0;
3276 PMD_INIT_FUNC_TRACE();
3278 hw->mac.ops.reset_hw(hw);
3279 adapter->stopped = 0;
3282 igbvf_set_vfta_all(dev,1);
3284 eth_igbvf_tx_init(dev);
3286 /* This can fail when allocating mbufs for descriptor rings */
3287 ret = eth_igbvf_rx_init(dev);
3289 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3290 igb_dev_clear_queues(dev);
3294 /* check and configure queue intr-vector mapping */
3295 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3296 intr_vector = dev->data->nb_rx_queues;
3297 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3302 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3303 intr_handle->intr_vec =
3304 rte_zmalloc("intr_vec",
3305 dev->data->nb_rx_queues * sizeof(int), 0);
3306 if (!intr_handle->intr_vec) {
3307 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3308 " intr_vec", dev->data->nb_rx_queues);
3313 eth_igbvf_configure_msix_intr(dev);
3315 /* enable uio/vfio intr/eventfd mapping */
3316 rte_intr_enable(intr_handle);
3318 /* resume enabled intr since hw reset */
3319 igbvf_intr_enable(dev);
3325 igbvf_dev_stop(struct rte_eth_dev *dev)
3327 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3328 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3330 PMD_INIT_FUNC_TRACE();
3332 igbvf_stop_adapter(dev);
3335 * Clear what we set, but we still keep shadow_vfta to
3336 * restore after device starts
3338 igbvf_set_vfta_all(dev,0);
3340 igb_dev_clear_queues(dev);
3342 /* disable intr eventfd mapping */
3343 rte_intr_disable(intr_handle);
3345 /* Clean datapath event and queue/vec mapping */
3346 rte_intr_efd_disable(intr_handle);
3347 if (intr_handle->intr_vec) {
3348 rte_free(intr_handle->intr_vec);
3349 intr_handle->intr_vec = NULL;
3354 igbvf_dev_close(struct rte_eth_dev *dev)
3356 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3357 struct e1000_adapter *adapter =
3358 E1000_DEV_PRIVATE(dev->data->dev_private);
3359 struct ether_addr addr;
3361 PMD_INIT_FUNC_TRACE();
3365 igbvf_dev_stop(dev);
3366 adapter->stopped = 1;
3367 igb_dev_free_queues(dev);
3370 * reprogram the RAR with a zero mac address,
3371 * to ensure that the VF traffic goes to the PF
3372 * after stop, close and detach of the VF.
3375 memset(&addr, 0, sizeof(addr));
3376 igbvf_default_mac_addr_set(dev, &addr);
3380 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3382 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3384 /* Set both unicast and multicast promisc */
3385 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3389 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3391 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3393 /* If in allmulticast mode leave multicast promisc */
3394 if (dev->data->all_multicast == 1)
3395 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3397 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3401 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3403 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405 /* In promiscuous mode multicast promisc already set */
3406 if (dev->data->promiscuous == 0)
3407 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3411 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3413 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3415 /* In promiscuous mode leave multicast promisc enabled */
3416 if (dev->data->promiscuous == 0)
3417 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3420 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3422 struct e1000_mbx_info *mbx = &hw->mbx;
3426 /* After set vlan, vlan strip will also be enabled in igb driver*/
3427 msgbuf[0] = E1000_VF_SET_VLAN;
3429 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3431 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3433 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3437 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3441 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3442 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3449 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3451 struct e1000_hw *hw =
3452 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3453 struct e1000_vfta * shadow_vfta =
3454 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3455 int i = 0, j = 0, vfta = 0, mask = 1;
3457 for (i = 0; i < IGB_VFTA_SIZE; i++){
3458 vfta = shadow_vfta->vfta[i];
3461 for (j = 0; j < 32; j++){
3464 (uint16_t)((i<<5)+j), on);
3473 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3475 struct e1000_hw *hw =
3476 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3477 struct e1000_vfta * shadow_vfta =
3478 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3479 uint32_t vid_idx = 0;
3480 uint32_t vid_bit = 0;
3483 PMD_INIT_FUNC_TRACE();
3485 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3486 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3488 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3491 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3492 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3494 /*Save what we set and retore it after device reset*/
3496 shadow_vfta->vfta[vid_idx] |= vid_bit;
3498 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3504 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3506 struct e1000_hw *hw =
3507 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3509 /* index is not used by rar_set() */
3510 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3515 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3516 struct rte_eth_rss_reta_entry64 *reta_conf,
3521 uint16_t idx, shift;
3522 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3524 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3525 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3526 "(%d) doesn't match the number hardware can supported "
3527 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3531 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3532 idx = i / RTE_RETA_GROUP_SIZE;
3533 shift = i % RTE_RETA_GROUP_SIZE;
3534 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3538 if (mask == IGB_4_BIT_MASK)
3541 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3542 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3543 if (mask & (0x1 << j))
3544 reta |= reta_conf[idx].reta[shift + j] <<
3547 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3549 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3556 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3557 struct rte_eth_rss_reta_entry64 *reta_conf,
3562 uint16_t idx, shift;
3563 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3566 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3567 "(%d) doesn't match the number hardware can supported "
3568 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3572 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3573 idx = i / RTE_RETA_GROUP_SIZE;
3574 shift = i % RTE_RETA_GROUP_SIZE;
3575 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3579 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3580 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3581 if (mask & (0x1 << j))
3582 reta_conf[idx].reta[shift + j] =
3583 ((reta >> (CHAR_BIT * j)) &
3592 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3593 struct rte_eth_syn_filter *filter,
3596 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3597 struct e1000_filter_info *filter_info =
3598 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3599 uint32_t synqf, rfctl;
3601 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3604 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3607 if (synqf & E1000_SYN_FILTER_ENABLE)
3610 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3611 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3613 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3614 if (filter->hig_pri)
3615 rfctl |= E1000_RFCTL_SYNQFP;
3617 rfctl &= ~E1000_RFCTL_SYNQFP;
3619 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3621 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3626 filter_info->syn_info = synqf;
3627 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3628 E1000_WRITE_FLUSH(hw);
3633 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3634 struct rte_eth_syn_filter *filter)
3636 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3637 uint32_t synqf, rfctl;
3639 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3640 if (synqf & E1000_SYN_FILTER_ENABLE) {
3641 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3642 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3643 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3644 E1000_SYN_FILTER_QUEUE_SHIFT);
3652 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3653 enum rte_filter_op filter_op,
3656 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3659 MAC_TYPE_FILTER_SUP(hw->mac.type);
3661 if (filter_op == RTE_ETH_FILTER_NOP)
3665 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3670 switch (filter_op) {
3671 case RTE_ETH_FILTER_ADD:
3672 ret = eth_igb_syn_filter_set(dev,
3673 (struct rte_eth_syn_filter *)arg,
3676 case RTE_ETH_FILTER_DELETE:
3677 ret = eth_igb_syn_filter_set(dev,
3678 (struct rte_eth_syn_filter *)arg,
3681 case RTE_ETH_FILTER_GET:
3682 ret = eth_igb_syn_filter_get(dev,
3683 (struct rte_eth_syn_filter *)arg);
3686 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3694 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3696 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3697 struct e1000_2tuple_filter_info *filter_info)
3699 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3701 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3702 return -EINVAL; /* filter index is out of range. */
3703 if (filter->tcp_flags > TCP_FLAG_ALL)
3704 return -EINVAL; /* flags is invalid. */
3706 switch (filter->dst_port_mask) {
3708 filter_info->dst_port_mask = 0;
3709 filter_info->dst_port = filter->dst_port;
3712 filter_info->dst_port_mask = 1;
3715 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3719 switch (filter->proto_mask) {
3721 filter_info->proto_mask = 0;
3722 filter_info->proto = filter->proto;
3725 filter_info->proto_mask = 1;
3728 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3732 filter_info->priority = (uint8_t)filter->priority;
3733 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3734 filter_info->tcp_flags = filter->tcp_flags;
3736 filter_info->tcp_flags = 0;
3741 static inline struct e1000_2tuple_filter *
3742 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3743 struct e1000_2tuple_filter_info *key)
3745 struct e1000_2tuple_filter *it;
3747 TAILQ_FOREACH(it, filter_list, entries) {
3748 if (memcmp(key, &it->filter_info,
3749 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3756 /* inject a igb 2tuple filter to HW */
3758 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3759 struct e1000_2tuple_filter *filter)
3761 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3762 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3763 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3767 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3768 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3769 imir |= E1000_IMIR_PORT_BP;
3771 imir &= ~E1000_IMIR_PORT_BP;
3773 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3775 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3776 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3777 ttqf |= (uint32_t)(filter->filter_info.proto &
3778 E1000_TTQF_PROTOCOL_MASK);
3779 if (filter->filter_info.proto_mask == 0)
3780 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3782 /* tcp flags bits setting. */
3783 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3784 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3785 imir_ext |= E1000_IMIREXT_CTRL_URG;
3786 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3787 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3788 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3789 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3790 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3791 imir_ext |= E1000_IMIREXT_CTRL_RST;
3792 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3793 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3794 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3795 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3797 imir_ext |= E1000_IMIREXT_CTRL_BP;
3799 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3800 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3801 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3805 * igb_add_2tuple_filter - add a 2tuple filter
3808 * dev: Pointer to struct rte_eth_dev.
3809 * ntuple_filter: ponter to the filter that will be added.
3812 * - On success, zero.
3813 * - On failure, a negative value.
3816 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3817 struct rte_eth_ntuple_filter *ntuple_filter)
3819 struct e1000_filter_info *filter_info =
3820 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3821 struct e1000_2tuple_filter *filter;
3824 filter = rte_zmalloc("e1000_2tuple_filter",
3825 sizeof(struct e1000_2tuple_filter), 0);
3829 ret = ntuple_filter_to_2tuple(ntuple_filter,
3830 &filter->filter_info);
3835 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3836 &filter->filter_info) != NULL) {
3837 PMD_DRV_LOG(ERR, "filter exists.");
3841 filter->queue = ntuple_filter->queue;
3844 * look for an unused 2tuple filter index,
3845 * and insert the filter to list.
3847 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3848 if (!(filter_info->twotuple_mask & (1 << i))) {
3849 filter_info->twotuple_mask |= 1 << i;
3851 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3857 if (i >= E1000_MAX_TTQF_FILTERS) {
3858 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3863 igb_inject_2uple_filter(dev, filter);
3868 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3869 struct e1000_2tuple_filter *filter)
3871 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3872 struct e1000_filter_info *filter_info =
3873 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3875 filter_info->twotuple_mask &= ~(1 << filter->index);
3876 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3879 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3880 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3881 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3886 * igb_remove_2tuple_filter - remove a 2tuple filter
3889 * dev: Pointer to struct rte_eth_dev.
3890 * ntuple_filter: ponter to the filter that will be removed.
3893 * - On success, zero.
3894 * - On failure, a negative value.
3897 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3898 struct rte_eth_ntuple_filter *ntuple_filter)
3900 struct e1000_filter_info *filter_info =
3901 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3902 struct e1000_2tuple_filter_info filter_2tuple;
3903 struct e1000_2tuple_filter *filter;
3906 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3907 ret = ntuple_filter_to_2tuple(ntuple_filter,
3912 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3914 if (filter == NULL) {
3915 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3919 igb_delete_2tuple_filter(dev, filter);
3924 /* inject a igb flex filter to HW */
3926 igb_inject_flex_filter(struct rte_eth_dev *dev,
3927 struct e1000_flex_filter *filter)
3929 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3930 uint32_t wufc, queueing;
3934 wufc = E1000_READ_REG(hw, E1000_WUFC);
3935 if (filter->index < E1000_MAX_FHFT)
3936 reg_off = E1000_FHFT(filter->index);
3938 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3940 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3941 (E1000_WUFC_FLX0 << filter->index));
3942 queueing = filter->filter_info.len |
3943 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3944 (filter->filter_info.priority <<
3945 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3946 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3949 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3950 E1000_WRITE_REG(hw, reg_off,
3951 filter->filter_info.dwords[j]);
3952 reg_off += sizeof(uint32_t);
3953 E1000_WRITE_REG(hw, reg_off,
3954 filter->filter_info.dwords[++j]);
3955 reg_off += sizeof(uint32_t);
3956 E1000_WRITE_REG(hw, reg_off,
3957 (uint32_t)filter->filter_info.mask[i]);
3958 reg_off += sizeof(uint32_t) * 2;
3963 static inline struct e1000_flex_filter *
3964 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3965 struct e1000_flex_filter_info *key)
3967 struct e1000_flex_filter *it;
3969 TAILQ_FOREACH(it, filter_list, entries) {
3970 if (memcmp(key, &it->filter_info,
3971 sizeof(struct e1000_flex_filter_info)) == 0)
3978 /* remove a flex byte filter
3980 * dev: Pointer to struct rte_eth_dev.
3981 * filter: the pointer of the filter will be removed.
3984 igb_remove_flex_filter(struct rte_eth_dev *dev,
3985 struct e1000_flex_filter *filter)
3987 struct e1000_filter_info *filter_info =
3988 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3989 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993 wufc = E1000_READ_REG(hw, E1000_WUFC);
3994 if (filter->index < E1000_MAX_FHFT)
3995 reg_off = E1000_FHFT(filter->index);
3997 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3999 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4000 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4002 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4003 (~(E1000_WUFC_FLX0 << filter->index)));
4005 filter_info->flex_mask &= ~(1 << filter->index);
4006 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4011 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4012 struct rte_eth_flex_filter *filter,
4015 struct e1000_filter_info *filter_info =
4016 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4017 struct e1000_flex_filter *flex_filter, *it;
4021 flex_filter = rte_zmalloc("e1000_flex_filter",
4022 sizeof(struct e1000_flex_filter), 0);
4023 if (flex_filter == NULL)
4026 flex_filter->filter_info.len = filter->len;
4027 flex_filter->filter_info.priority = filter->priority;
4028 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4029 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4031 /* reverse bits in flex filter's mask*/
4032 for (shift = 0; shift < CHAR_BIT; shift++) {
4033 if (filter->mask[i] & (0x01 << shift))
4034 mask |= (0x80 >> shift);
4036 flex_filter->filter_info.mask[i] = mask;
4039 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4040 &flex_filter->filter_info);
4041 if (it == NULL && !add) {
4042 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4043 rte_free(flex_filter);
4046 if (it != NULL && add) {
4047 PMD_DRV_LOG(ERR, "filter exists.");
4048 rte_free(flex_filter);
4053 flex_filter->queue = filter->queue;
4055 * look for an unused flex filter index
4056 * and insert the filter into the list.
4058 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4059 if (!(filter_info->flex_mask & (1 << i))) {
4060 filter_info->flex_mask |= 1 << i;
4061 flex_filter->index = i;
4062 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4068 if (i >= E1000_MAX_FLEX_FILTERS) {
4069 PMD_DRV_LOG(ERR, "flex filters are full.");
4070 rte_free(flex_filter);
4074 igb_inject_flex_filter(dev, flex_filter);
4077 igb_remove_flex_filter(dev, it);
4078 rte_free(flex_filter);
4085 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4086 struct rte_eth_flex_filter *filter)
4088 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4089 struct e1000_filter_info *filter_info =
4090 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4091 struct e1000_flex_filter flex_filter, *it;
4092 uint32_t wufc, queueing, wufc_en = 0;
4094 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4095 flex_filter.filter_info.len = filter->len;
4096 flex_filter.filter_info.priority = filter->priority;
4097 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4098 memcpy(flex_filter.filter_info.mask, filter->mask,
4099 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4101 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4102 &flex_filter.filter_info);
4104 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4108 wufc = E1000_READ_REG(hw, E1000_WUFC);
4109 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4111 if ((wufc & wufc_en) == wufc_en) {
4112 uint32_t reg_off = 0;
4113 if (it->index < E1000_MAX_FHFT)
4114 reg_off = E1000_FHFT(it->index);
4116 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4118 queueing = E1000_READ_REG(hw,
4119 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4120 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4121 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4122 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4123 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4124 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4131 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4132 enum rte_filter_op filter_op,
4135 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4136 struct rte_eth_flex_filter *filter;
4139 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4141 if (filter_op == RTE_ETH_FILTER_NOP)
4145 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4150 filter = (struct rte_eth_flex_filter *)arg;
4151 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4152 || filter->len % sizeof(uint64_t) != 0) {
4153 PMD_DRV_LOG(ERR, "filter's length is out of range");
4156 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4157 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4161 switch (filter_op) {
4162 case RTE_ETH_FILTER_ADD:
4163 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4165 case RTE_ETH_FILTER_DELETE:
4166 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4168 case RTE_ETH_FILTER_GET:
4169 ret = eth_igb_get_flex_filter(dev, filter);
4172 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4180 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4182 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4183 struct e1000_5tuple_filter_info *filter_info)
4185 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4187 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4188 return -EINVAL; /* filter index is out of range. */
4189 if (filter->tcp_flags > TCP_FLAG_ALL)
4190 return -EINVAL; /* flags is invalid. */
4192 switch (filter->dst_ip_mask) {
4194 filter_info->dst_ip_mask = 0;
4195 filter_info->dst_ip = filter->dst_ip;
4198 filter_info->dst_ip_mask = 1;
4201 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4205 switch (filter->src_ip_mask) {
4207 filter_info->src_ip_mask = 0;
4208 filter_info->src_ip = filter->src_ip;
4211 filter_info->src_ip_mask = 1;
4214 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4218 switch (filter->dst_port_mask) {
4220 filter_info->dst_port_mask = 0;
4221 filter_info->dst_port = filter->dst_port;
4224 filter_info->dst_port_mask = 1;
4227 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4231 switch (filter->src_port_mask) {
4233 filter_info->src_port_mask = 0;
4234 filter_info->src_port = filter->src_port;
4237 filter_info->src_port_mask = 1;
4240 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4244 switch (filter->proto_mask) {
4246 filter_info->proto_mask = 0;
4247 filter_info->proto = filter->proto;
4250 filter_info->proto_mask = 1;
4253 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4257 filter_info->priority = (uint8_t)filter->priority;
4258 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4259 filter_info->tcp_flags = filter->tcp_flags;
4261 filter_info->tcp_flags = 0;
4266 static inline struct e1000_5tuple_filter *
4267 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4268 struct e1000_5tuple_filter_info *key)
4270 struct e1000_5tuple_filter *it;
4272 TAILQ_FOREACH(it, filter_list, entries) {
4273 if (memcmp(key, &it->filter_info,
4274 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4281 /* inject a igb 5-tuple filter to HW */
4283 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4284 struct e1000_5tuple_filter *filter)
4286 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4287 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4288 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4292 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4293 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4294 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4295 if (filter->filter_info.dst_ip_mask == 0)
4296 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4297 if (filter->filter_info.src_port_mask == 0)
4298 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4299 if (filter->filter_info.proto_mask == 0)
4300 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4301 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4302 E1000_FTQF_QUEUE_MASK;
4303 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4304 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4305 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4306 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4308 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4309 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4311 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4312 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4313 imir |= E1000_IMIR_PORT_BP;
4315 imir &= ~E1000_IMIR_PORT_BP;
4316 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4318 /* tcp flags bits setting. */
4319 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4320 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4321 imir_ext |= E1000_IMIREXT_CTRL_URG;
4322 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4323 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4324 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4325 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4326 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4327 imir_ext |= E1000_IMIREXT_CTRL_RST;
4328 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4329 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4330 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4331 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4333 imir_ext |= E1000_IMIREXT_CTRL_BP;
4335 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4336 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4340 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4343 * dev: Pointer to struct rte_eth_dev.
4344 * ntuple_filter: ponter to the filter that will be added.
4347 * - On success, zero.
4348 * - On failure, a negative value.
4351 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4352 struct rte_eth_ntuple_filter *ntuple_filter)
4354 struct e1000_filter_info *filter_info =
4355 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4356 struct e1000_5tuple_filter *filter;
4360 filter = rte_zmalloc("e1000_5tuple_filter",
4361 sizeof(struct e1000_5tuple_filter), 0);
4365 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4366 &filter->filter_info);
4372 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4373 &filter->filter_info) != NULL) {
4374 PMD_DRV_LOG(ERR, "filter exists.");
4378 filter->queue = ntuple_filter->queue;
4381 * look for an unused 5tuple filter index,
4382 * and insert the filter to list.
4384 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4385 if (!(filter_info->fivetuple_mask & (1 << i))) {
4386 filter_info->fivetuple_mask |= 1 << i;
4388 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4394 if (i >= E1000_MAX_FTQF_FILTERS) {
4395 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4400 igb_inject_5tuple_filter_82576(dev, filter);
4405 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4406 struct e1000_5tuple_filter *filter)
4408 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4409 struct e1000_filter_info *filter_info =
4410 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4412 filter_info->fivetuple_mask &= ~(1 << filter->index);
4413 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4416 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4417 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4418 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4419 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4420 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4421 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4422 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4427 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4430 * dev: Pointer to struct rte_eth_dev.
4431 * ntuple_filter: ponter to the filter that will be removed.
4434 * - On success, zero.
4435 * - On failure, a negative value.
4438 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4439 struct rte_eth_ntuple_filter *ntuple_filter)
4441 struct e1000_filter_info *filter_info =
4442 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4443 struct e1000_5tuple_filter_info filter_5tuple;
4444 struct e1000_5tuple_filter *filter;
4447 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4448 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4453 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4455 if (filter == NULL) {
4456 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4460 igb_delete_5tuple_filter_82576(dev, filter);
4466 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4469 struct e1000_hw *hw;
4470 struct rte_eth_dev_info dev_info;
4471 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4474 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4476 #ifdef RTE_LIBRTE_82571_SUPPORT
4477 /* XXX: not bigger than max_rx_pktlen */
4478 if (hw->mac.type == e1000_82571)
4481 eth_igb_infos_get(dev, &dev_info);
4483 /* check that mtu is within the allowed range */
4484 if ((mtu < ETHER_MIN_MTU) ||
4485 (frame_size > dev_info.max_rx_pktlen))
4488 /* refuse mtu that requires the support of scattered packets when this
4489 * feature has not been enabled before. */
4490 if (!dev->data->scattered_rx &&
4491 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4494 rctl = E1000_READ_REG(hw, E1000_RCTL);
4496 /* switch to jumbo mode if needed */
4497 if (frame_size > ETHER_MAX_LEN) {
4498 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4499 rctl |= E1000_RCTL_LPE;
4501 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4502 rctl &= ~E1000_RCTL_LPE;
4504 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4506 /* update max frame size */
4507 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4509 E1000_WRITE_REG(hw, E1000_RLPML,
4510 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4516 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4519 * dev: Pointer to struct rte_eth_dev.
4520 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4521 * add: if true, add filter, if false, remove filter
4524 * - On success, zero.
4525 * - On failure, a negative value.
4528 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4529 struct rte_eth_ntuple_filter *ntuple_filter,
4532 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4535 switch (ntuple_filter->flags) {
4536 case RTE_5TUPLE_FLAGS:
4537 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4538 if (hw->mac.type != e1000_82576)
4541 ret = igb_add_5tuple_filter_82576(dev,
4544 ret = igb_remove_5tuple_filter_82576(dev,
4547 case RTE_2TUPLE_FLAGS:
4548 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4549 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4550 hw->mac.type != e1000_i210 &&
4551 hw->mac.type != e1000_i211)
4554 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4556 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4567 * igb_get_ntuple_filter - get a ntuple filter
4570 * dev: Pointer to struct rte_eth_dev.
4571 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4574 * - On success, zero.
4575 * - On failure, a negative value.
4578 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4579 struct rte_eth_ntuple_filter *ntuple_filter)
4581 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4582 struct e1000_filter_info *filter_info =
4583 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4584 struct e1000_5tuple_filter_info filter_5tuple;
4585 struct e1000_2tuple_filter_info filter_2tuple;
4586 struct e1000_5tuple_filter *p_5tuple_filter;
4587 struct e1000_2tuple_filter *p_2tuple_filter;
4590 switch (ntuple_filter->flags) {
4591 case RTE_5TUPLE_FLAGS:
4592 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4593 if (hw->mac.type != e1000_82576)
4595 memset(&filter_5tuple,
4597 sizeof(struct e1000_5tuple_filter_info));
4598 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4602 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4603 &filter_info->fivetuple_list,
4605 if (p_5tuple_filter == NULL) {
4606 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4609 ntuple_filter->queue = p_5tuple_filter->queue;
4611 case RTE_2TUPLE_FLAGS:
4612 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4613 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4615 memset(&filter_2tuple,
4617 sizeof(struct e1000_2tuple_filter_info));
4618 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4621 p_2tuple_filter = igb_2tuple_filter_lookup(
4622 &filter_info->twotuple_list,
4624 if (p_2tuple_filter == NULL) {
4625 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4628 ntuple_filter->queue = p_2tuple_filter->queue;
4639 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4640 * @dev: pointer to rte_eth_dev structure
4641 * @filter_op:operation will be taken.
4642 * @arg: a pointer to specific structure corresponding to the filter_op
4645 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4646 enum rte_filter_op filter_op,
4649 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4652 MAC_TYPE_FILTER_SUP(hw->mac.type);
4654 if (filter_op == RTE_ETH_FILTER_NOP)
4658 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4663 switch (filter_op) {
4664 case RTE_ETH_FILTER_ADD:
4665 ret = igb_add_del_ntuple_filter(dev,
4666 (struct rte_eth_ntuple_filter *)arg,
4669 case RTE_ETH_FILTER_DELETE:
4670 ret = igb_add_del_ntuple_filter(dev,
4671 (struct rte_eth_ntuple_filter *)arg,
4674 case RTE_ETH_FILTER_GET:
4675 ret = igb_get_ntuple_filter(dev,
4676 (struct rte_eth_ntuple_filter *)arg);
4679 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4687 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4692 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4693 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4694 (filter_info->ethertype_mask & (1 << i)))
4701 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4702 uint16_t ethertype, uint32_t etqf)
4706 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4707 if (!(filter_info->ethertype_mask & (1 << i))) {
4708 filter_info->ethertype_mask |= 1 << i;
4709 filter_info->ethertype_filters[i].ethertype = ethertype;
4710 filter_info->ethertype_filters[i].etqf = etqf;
4718 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4721 if (idx >= E1000_MAX_ETQF_FILTERS)
4723 filter_info->ethertype_mask &= ~(1 << idx);
4724 filter_info->ethertype_filters[idx].ethertype = 0;
4725 filter_info->ethertype_filters[idx].etqf = 0;
4731 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4732 struct rte_eth_ethertype_filter *filter,
4735 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4736 struct e1000_filter_info *filter_info =
4737 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4741 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4742 filter->ether_type == ETHER_TYPE_IPv6) {
4743 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4744 " ethertype filter.", filter->ether_type);
4748 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4749 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4752 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4753 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4757 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4758 if (ret >= 0 && add) {
4759 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4760 filter->ether_type);
4763 if (ret < 0 && !add) {
4764 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4765 filter->ether_type);
4770 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4771 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4772 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4773 ret = igb_ethertype_filter_insert(filter_info,
4774 filter->ether_type, etqf);
4776 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4780 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4784 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4785 E1000_WRITE_FLUSH(hw);
4791 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4792 struct rte_eth_ethertype_filter *filter)
4794 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4795 struct e1000_filter_info *filter_info =
4796 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4800 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4802 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4803 filter->ether_type);
4807 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4808 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4809 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4811 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4812 E1000_ETQF_QUEUE_SHIFT;
4820 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4821 * @dev: pointer to rte_eth_dev structure
4822 * @filter_op:operation will be taken.
4823 * @arg: a pointer to specific structure corresponding to the filter_op
4826 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4827 enum rte_filter_op filter_op,
4830 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4833 MAC_TYPE_FILTER_SUP(hw->mac.type);
4835 if (filter_op == RTE_ETH_FILTER_NOP)
4839 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4844 switch (filter_op) {
4845 case RTE_ETH_FILTER_ADD:
4846 ret = igb_add_del_ethertype_filter(dev,
4847 (struct rte_eth_ethertype_filter *)arg,
4850 case RTE_ETH_FILTER_DELETE:
4851 ret = igb_add_del_ethertype_filter(dev,
4852 (struct rte_eth_ethertype_filter *)arg,
4855 case RTE_ETH_FILTER_GET:
4856 ret = igb_get_ethertype_filter(dev,
4857 (struct rte_eth_ethertype_filter *)arg);
4860 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4868 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4869 enum rte_filter_type filter_type,
4870 enum rte_filter_op filter_op,
4875 switch (filter_type) {
4876 case RTE_ETH_FILTER_NTUPLE:
4877 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4879 case RTE_ETH_FILTER_ETHERTYPE:
4880 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4882 case RTE_ETH_FILTER_SYN:
4883 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4885 case RTE_ETH_FILTER_FLEXIBLE:
4886 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4888 case RTE_ETH_FILTER_GENERIC:
4889 if (filter_op != RTE_ETH_FILTER_GET)
4891 *(const void **)arg = &igb_flow_ops;
4894 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4903 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4904 struct ether_addr *mc_addr_set,
4905 uint32_t nb_mc_addr)
4907 struct e1000_hw *hw;
4909 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4910 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4915 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4917 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918 uint64_t systime_cycles;
4920 switch (hw->mac.type) {
4924 * Need to read System Time Residue Register to be able
4925 * to read the other two registers.
4927 E1000_READ_REG(hw, E1000_SYSTIMR);
4928 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4929 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4930 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4937 * Need to read System Time Residue Register to be able
4938 * to read the other two registers.
4940 E1000_READ_REG(hw, E1000_SYSTIMR);
4941 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4942 /* Only the 8 LSB are valid. */
4943 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4947 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4948 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4953 return systime_cycles;
4957 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4959 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4960 uint64_t rx_tstamp_cycles;
4962 switch (hw->mac.type) {
4965 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4966 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4967 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4973 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4974 /* Only the 8 LSB are valid. */
4975 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4979 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4980 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4985 return rx_tstamp_cycles;
4989 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4991 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992 uint64_t tx_tstamp_cycles;
4994 switch (hw->mac.type) {
4997 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4998 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4999 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5005 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5006 /* Only the 8 LSB are valid. */
5007 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5011 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5012 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5017 return tx_tstamp_cycles;
5021 igb_start_timecounters(struct rte_eth_dev *dev)
5023 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5024 struct e1000_adapter *adapter =
5025 (struct e1000_adapter *)dev->data->dev_private;
5026 uint32_t incval = 1;
5028 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5030 switch (hw->mac.type) {
5034 /* 32 LSB bits + 8 MSB bits = 40 bits */
5035 mask = (1ULL << 40) - 1;
5040 * Start incrementing the register
5041 * used to timestamp PTP packets.
5043 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5046 incval = E1000_INCVALUE_82576;
5047 shift = IGB_82576_TSYNC_SHIFT;
5048 E1000_WRITE_REG(hw, E1000_TIMINCA,
5049 E1000_INCPERIOD_82576 | incval);
5056 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5057 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5058 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5060 adapter->systime_tc.cc_mask = mask;
5061 adapter->systime_tc.cc_shift = shift;
5062 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5064 adapter->rx_tstamp_tc.cc_mask = mask;
5065 adapter->rx_tstamp_tc.cc_shift = shift;
5066 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5068 adapter->tx_tstamp_tc.cc_mask = mask;
5069 adapter->tx_tstamp_tc.cc_shift = shift;
5070 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5074 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5076 struct e1000_adapter *adapter =
5077 (struct e1000_adapter *)dev->data->dev_private;
5079 adapter->systime_tc.nsec += delta;
5080 adapter->rx_tstamp_tc.nsec += delta;
5081 adapter->tx_tstamp_tc.nsec += delta;
5087 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5090 struct e1000_adapter *adapter =
5091 (struct e1000_adapter *)dev->data->dev_private;
5093 ns = rte_timespec_to_ns(ts);
5095 /* Set the timecounters to a new value. */
5096 adapter->systime_tc.nsec = ns;
5097 adapter->rx_tstamp_tc.nsec = ns;
5098 adapter->tx_tstamp_tc.nsec = ns;
5104 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5106 uint64_t ns, systime_cycles;
5107 struct e1000_adapter *adapter =
5108 (struct e1000_adapter *)dev->data->dev_private;
5110 systime_cycles = igb_read_systime_cyclecounter(dev);
5111 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5112 *ts = rte_ns_to_timespec(ns);
5118 igb_timesync_enable(struct rte_eth_dev *dev)
5120 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5124 /* Stop the timesync system time. */
5125 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5126 /* Reset the timesync system time value. */
5127 switch (hw->mac.type) {
5133 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5136 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5137 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5140 /* Not supported. */
5144 /* Enable system time for it isn't on by default. */
5145 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5146 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5147 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5149 igb_start_timecounters(dev);
5151 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5152 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5154 E1000_ETQF_FILTER_ENABLE |
5157 /* Enable timestamping of received PTP packets. */
5158 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5159 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5160 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5162 /* Enable Timestamping of transmitted PTP packets. */
5163 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5164 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5165 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5171 igb_timesync_disable(struct rte_eth_dev *dev)
5173 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5176 /* Disable timestamping of transmitted PTP packets. */
5177 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5178 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5179 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5181 /* Disable timestamping of received PTP packets. */
5182 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5183 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5184 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5186 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5187 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5189 /* Stop incrementating the System Time registers. */
5190 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5196 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5197 struct timespec *timestamp,
5198 uint32_t flags __rte_unused)
5200 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201 struct e1000_adapter *adapter =
5202 (struct e1000_adapter *)dev->data->dev_private;
5203 uint32_t tsync_rxctl;
5204 uint64_t rx_tstamp_cycles;
5207 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5208 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5211 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5212 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5213 *timestamp = rte_ns_to_timespec(ns);
5219 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5220 struct timespec *timestamp)
5222 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223 struct e1000_adapter *adapter =
5224 (struct e1000_adapter *)dev->data->dev_private;
5225 uint32_t tsync_txctl;
5226 uint64_t tx_tstamp_cycles;
5229 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5230 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5233 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5234 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5235 *timestamp = rte_ns_to_timespec(ns);
5241 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5245 const struct reg_info *reg_group;
5247 while ((reg_group = igb_regs[g_ind++]))
5248 count += igb_reg_group_count(reg_group);
5254 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5258 const struct reg_info *reg_group;
5260 while ((reg_group = igbvf_regs[g_ind++]))
5261 count += igb_reg_group_count(reg_group);
5267 eth_igb_get_regs(struct rte_eth_dev *dev,
5268 struct rte_dev_reg_info *regs)
5270 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5271 uint32_t *data = regs->data;
5274 const struct reg_info *reg_group;
5277 regs->length = eth_igb_get_reg_length(dev);
5278 regs->width = sizeof(uint32_t);
5282 /* Support only full register dump */
5283 if ((regs->length == 0) ||
5284 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5285 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5287 while ((reg_group = igb_regs[g_ind++]))
5288 count += igb_read_regs_group(dev, &data[count],
5297 igbvf_get_regs(struct rte_eth_dev *dev,
5298 struct rte_dev_reg_info *regs)
5300 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5301 uint32_t *data = regs->data;
5304 const struct reg_info *reg_group;
5307 regs->length = igbvf_get_reg_length(dev);
5308 regs->width = sizeof(uint32_t);
5312 /* Support only full register dump */
5313 if ((regs->length == 0) ||
5314 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5315 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5317 while ((reg_group = igbvf_regs[g_ind++]))
5318 count += igb_read_regs_group(dev, &data[count],
5327 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5329 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5331 /* Return unit is byte count */
5332 return hw->nvm.word_size * 2;
5336 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5337 struct rte_dev_eeprom_info *in_eeprom)
5339 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5340 struct e1000_nvm_info *nvm = &hw->nvm;
5341 uint16_t *data = in_eeprom->data;
5344 first = in_eeprom->offset >> 1;
5345 length = in_eeprom->length >> 1;
5346 if ((first >= hw->nvm.word_size) ||
5347 ((first + length) >= hw->nvm.word_size))
5350 in_eeprom->magic = hw->vendor_id |
5351 ((uint32_t)hw->device_id << 16);
5353 if ((nvm->ops.read) == NULL)
5356 return nvm->ops.read(hw, first, length, data);
5360 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5361 struct rte_dev_eeprom_info *in_eeprom)
5363 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5364 struct e1000_nvm_info *nvm = &hw->nvm;
5365 uint16_t *data = in_eeprom->data;
5368 first = in_eeprom->offset >> 1;
5369 length = in_eeprom->length >> 1;
5370 if ((first >= hw->nvm.word_size) ||
5371 ((first + length) >= hw->nvm.word_size))
5374 in_eeprom->magic = (uint32_t)hw->vendor_id |
5375 ((uint32_t)hw->device_id << 16);
5377 if ((nvm->ops.write) == NULL)
5379 return nvm->ops.write(hw, first, length, data);
5383 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5385 struct e1000_hw *hw =
5386 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5387 uint32_t mask = 1 << queue_id;
5389 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5390 E1000_WRITE_FLUSH(hw);
5396 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5398 struct e1000_hw *hw =
5399 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5400 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5401 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5402 uint32_t mask = 1 << queue_id;
5405 regval = E1000_READ_REG(hw, E1000_EIMS);
5406 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5407 E1000_WRITE_FLUSH(hw);
5409 rte_intr_enable(intr_handle);
5415 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5416 uint8_t index, uint8_t offset)
5418 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5421 val &= ~((uint32_t)0xFF << offset);
5423 /* write vector and valid bit */
5424 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5426 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5430 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5431 uint8_t queue, uint8_t msix_vector)
5435 if (hw->mac.type == e1000_82575) {
5437 tmp = E1000_EICR_RX_QUEUE0 << queue;
5438 else if (direction == 1)
5439 tmp = E1000_EICR_TX_QUEUE0 << queue;
5440 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5441 } else if (hw->mac.type == e1000_82576) {
5442 if ((direction == 0) || (direction == 1))
5443 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5444 ((queue & 0x8) << 1) +
5446 } else if ((hw->mac.type == e1000_82580) ||
5447 (hw->mac.type == e1000_i350) ||
5448 (hw->mac.type == e1000_i354) ||
5449 (hw->mac.type == e1000_i210) ||
5450 (hw->mac.type == e1000_i211)) {
5451 if ((direction == 0) || (direction == 1))
5452 eth_igb_write_ivar(hw, msix_vector,
5454 ((queue & 0x1) << 4) +
5459 /* Sets up the hardware to generate MSI-X interrupts properly
5461 * board private structure
5464 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5467 uint32_t tmpval, regval, intr_mask;
5468 struct e1000_hw *hw =
5469 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5470 uint32_t vec = E1000_MISC_VEC_ID;
5471 uint32_t base = E1000_MISC_VEC_ID;
5472 uint32_t misc_shift = 0;
5473 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5474 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5476 /* won't configure msix register if no mapping is done
5477 * between intr vector and event fd
5479 if (!rte_intr_dp_is_en(intr_handle))
5482 if (rte_intr_allow_others(intr_handle)) {
5483 vec = base = E1000_RX_VEC_START;
5487 /* set interrupt vector for other causes */
5488 if (hw->mac.type == e1000_82575) {
5489 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5490 /* enable MSI-X PBA support */
5491 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5493 /* Auto-Mask interrupts upon ICR read */
5494 tmpval |= E1000_CTRL_EXT_EIAME;
5495 tmpval |= E1000_CTRL_EXT_IRCA;
5497 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5499 /* enable msix_other interrupt */
5500 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5501 regval = E1000_READ_REG(hw, E1000_EIAC);
5502 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5503 regval = E1000_READ_REG(hw, E1000_EIAM);
5504 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5505 } else if ((hw->mac.type == e1000_82576) ||
5506 (hw->mac.type == e1000_82580) ||
5507 (hw->mac.type == e1000_i350) ||
5508 (hw->mac.type == e1000_i354) ||
5509 (hw->mac.type == e1000_i210) ||
5510 (hw->mac.type == e1000_i211)) {
5511 /* turn on MSI-X capability first */
5512 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5513 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5515 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5517 regval = E1000_READ_REG(hw, E1000_EIAC);
5518 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5520 /* enable msix_other interrupt */
5521 regval = E1000_READ_REG(hw, E1000_EIMS);
5522 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5523 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5524 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5527 /* use EIAM to auto-mask when MSI-X interrupt
5528 * is asserted, this saves a register write for every interrupt
5530 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5532 regval = E1000_READ_REG(hw, E1000_EIAM);
5533 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5535 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5536 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5537 intr_handle->intr_vec[queue_id] = vec;
5538 if (vec < base + intr_handle->nb_efd - 1)
5542 E1000_WRITE_FLUSH(hw);
5545 /* restore n-tuple filter */
5547 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5549 struct e1000_filter_info *filter_info =
5550 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5551 struct e1000_5tuple_filter *p_5tuple;
5552 struct e1000_2tuple_filter *p_2tuple;
5554 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5555 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5558 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5559 igb_inject_2uple_filter(dev, p_2tuple);
5563 /* restore SYN filter */
5565 igb_syn_filter_restore(struct rte_eth_dev *dev)
5567 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5568 struct e1000_filter_info *filter_info =
5569 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5572 synqf = filter_info->syn_info;
5574 if (synqf & E1000_SYN_FILTER_ENABLE) {
5575 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5576 E1000_WRITE_FLUSH(hw);
5580 /* restore ethernet type filter */
5582 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5584 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5585 struct e1000_filter_info *filter_info =
5586 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5589 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5590 if (filter_info->ethertype_mask & (1 << i)) {
5591 E1000_WRITE_REG(hw, E1000_ETQF(i),
5592 filter_info->ethertype_filters[i].etqf);
5593 E1000_WRITE_FLUSH(hw);
5598 /* restore flex byte filter */
5600 igb_flex_filter_restore(struct rte_eth_dev *dev)
5602 struct e1000_filter_info *filter_info =
5603 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5604 struct e1000_flex_filter *flex_filter;
5606 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5607 igb_inject_flex_filter(dev, flex_filter);
5611 /* restore all types filter */
5613 igb_filter_restore(struct rte_eth_dev *dev)
5615 igb_ntuple_filter_restore(dev);
5616 igb_ethertype_filter_restore(dev);
5617 igb_syn_filter_restore(dev);
5618 igb_flex_filter_restore(dev);
5623 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5624 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5625 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5626 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5627 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5628 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");