drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_bus_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_ethdev_pci.h>
  50 #include <rte_memory.h>
  51 #include <rte_memzone.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55 #include <rte_dev.h>
  56
  57 #include "e1000_logs.h"
  58 #include "base/e1000_api.h"
  59 #include "e1000_ethdev.h"
  60 #include "igb_regs.h"
  61
  62 /*
  63  * Default values for port configuration
  64  */
  65 #define IGB_DEFAULT_RX_FREE_THRESH  32
  66
  67 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  68 #define IGB_DEFAULT_RX_HTHRESH      8
  69 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  70
  71 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  72 #define IGB_DEFAULT_TX_HTHRESH      1
  73 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  74
  75 #define IGB_HKEY_MAX_INDEX 10
  76
  77 /* Bit shift and mask */
  78 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  79 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  80 #define IGB_8_BIT_WIDTH  CHAR_BIT
  81 #define IGB_8_BIT_MASK   UINT8_MAX
  82
  83 /* Additional timesync values. */
  84 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  85 #define E1000_ETQF_FILTER_1588       3
  86 #define IGB_82576_TSYNC_SHIFT        16
  87 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  88 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  89 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  90
  91 #define E1000_VTIVAR_MISC                0x01740
  92 #define E1000_VTIVAR_MISC_MASK           0xFF
  93 #define E1000_VTIVAR_VALID               0x80
  94 #define E1000_VTIVAR_MISC_MAILBOX        0
  95 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  96
  97 /* External VLAN Enable bit mask */
  98 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  99
 100 /* External VLAN Ether Type bit mask and shift */
 101 #define E1000_VET_VET_EXT            0xFFFF0000
 102 #define E1000_VET_VET_EXT_SHIFT      16
 103
 104 static int  eth_igb_configure(struct rte_eth_dev *dev);
 105 static int  eth_igb_start(struct rte_eth_dev *dev);
 106 static void eth_igb_stop(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 108 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 109 static void eth_igb_close(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 113 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 114 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 115                                 int wait_to_complete);
 116 static int eth_igb_stats_get(struct rte_eth_dev *dev,
 117                                 struct rte_eth_stats *rte_stats);
 118 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 119                               struct rte_eth_xstat *xstats, unsigned n);
 120 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 121                 const uint64_t *ids,
 122                 uint64_t *values, unsigned int n);
 123 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 124                                     struct rte_eth_xstat_name *xstats_names,
 125                                     unsigned int size);
 126 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 127                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 128                 unsigned int limit);
 129 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 130 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 131 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 132                                    char *fw_version, size_t fw_size);
 133 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 134                               struct rte_eth_dev_info *dev_info);
 135 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 136 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 137                                 struct rte_eth_dev_info *dev_info);
 138 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 139                                 struct rte_eth_fc_conf *fc_conf);
 140 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 141                                 struct rte_eth_fc_conf *fc_conf);
 142 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 143 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 145 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 146                                     struct rte_intr_handle *handle);
 147 static void eth_igb_interrupt_handler(void *param);
 148 static int  igb_hardware_init(struct e1000_hw *hw);
 149 static void igb_hw_control_acquire(struct e1000_hw *hw);
 150 static void igb_hw_control_release(struct e1000_hw *hw);
 151 static void igb_init_manageability(struct e1000_hw *hw);
 152 static void igb_release_manageability(struct e1000_hw *hw);
 153
 154 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 155
 156 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 157                 uint16_t vlan_id, int on);
 158 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 159                                  enum rte_vlan_type vlan_type,
 160                                  uint16_t tpid_id);
 161 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 162
 163 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 168 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 169
 170 static int eth_igb_led_on(struct rte_eth_dev *dev);
 171 static int eth_igb_led_off(struct rte_eth_dev *dev);
 172
 173 static void igb_intr_disable(struct e1000_hw *hw);
 174 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 175 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 176                            struct ether_addr *mac_addr,
 177                            uint32_t index, uint32_t pool);
 178 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 179 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 180                 struct ether_addr *addr);
 181
 182 static void igbvf_intr_disable(struct e1000_hw *hw);
 183 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 184 static int igbvf_dev_start(struct rte_eth_dev *dev);
 185 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 186 static void igbvf_dev_close(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 188 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 190 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 191 static int eth_igbvf_link_update(struct e1000_hw *hw);
 192 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 193                                 struct rte_eth_stats *rte_stats);
 194 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 195                                 struct rte_eth_xstat *xstats, unsigned n);
 196 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 197                                       struct rte_eth_xstat_name *xstats_names,
 198                                       unsigned limit);
 199 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 200 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 201                 uint16_t vlan_id, int on);
 202 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 203 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 204 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 205                 struct ether_addr *addr);
 206 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 207 static int igbvf_get_regs(struct rte_eth_dev *dev,
 208                 struct rte_dev_reg_info *regs);
 209
 210 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 211                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 212                                    uint16_t reta_size);
 213 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 214                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 215                                   uint16_t reta_size);
 216
 217 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 218                         struct rte_eth_syn_filter *filter);
 219 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 220                         enum rte_filter_op filter_op,
 221                         void *arg);
 222 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_ntuple_filter *ntuple_filter);
 224 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ntuple_filter *ntuple_filter);
 226 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 227                         struct rte_eth_flex_filter *filter);
 228 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 229                         enum rte_filter_op filter_op,
 230                         void *arg);
 231 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 232                         struct rte_eth_ntuple_filter *ntuple_filter);
 233 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 234                         struct rte_eth_ntuple_filter *ntuple_filter);
 235 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 236                         struct rte_eth_ntuple_filter *filter);
 237 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 238                                 enum rte_filter_op filter_op,
 239                                 void *arg);
 240 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 241                                 enum rte_filter_op filter_op,
 242                                 void *arg);
 243 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 244                         struct rte_eth_ethertype_filter *filter);
 245 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 246                      enum rte_filter_type filter_type,
 247                      enum rte_filter_op filter_op,
 248                      void *arg);
 249 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 250 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 251                 struct rte_dev_reg_info *regs);
 252 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 253 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 254                 struct rte_dev_eeprom_info *eeprom);
 255 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 256                 struct rte_dev_eeprom_info *eeprom);
 257 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 258                                     struct ether_addr *mc_addr_set,
 259                                     uint32_t nb_mc_addr);
 260 static int igb_timesync_enable(struct rte_eth_dev *dev);
 261 static int igb_timesync_disable(struct rte_eth_dev *dev);
 262 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 263                                           struct timespec *timestamp,
 264                                           uint32_t flags);
 265 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 266                                           struct timespec *timestamp);
 267 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 268 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 269                                   struct timespec *timestamp);
 270 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 271                                    const struct timespec *timestamp);
 272 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 273                                         uint16_t queue_id);
 274 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 275                                          uint16_t queue_id);
 276 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 277                                        uint8_t queue, uint8_t msix_vector);
 278 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 279                                uint8_t index, uint8_t offset);
 280 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 281 static void eth_igbvf_interrupt_handler(void *param);
 282 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 283 static int igb_filter_restore(struct rte_eth_dev *dev);
 284
 285 /*
 286  * Define VF Stats MACRO for Non "cleared on read" register
 287  */
 288 #define UPDATE_VF_STAT(reg, last, cur)            \
 289 {                                                 \
 290         u32 latest = E1000_READ_REG(hw, reg);     \
 291         cur += (latest - last) & UINT_MAX;        \
 292         last = latest;                            \
 293 }
 294
 295 #define IGB_FC_PAUSE_TIME 0x0680
 296 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 297 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 298
 299 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 300
 301 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 302
 303 /*
 304  * The set of PCI devices this driver supports
 305  */
 306 static const struct rte_pci_id pci_id_igb_map[] = {
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 315
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 319
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 326
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 348         { .vendor_id = 0, /* sentinel */ },
 349 };
 350
 351 /*
 352  * The set of PCI devices this driver supports (for 82576&I350 VF)
 353  */
 354 static const struct rte_pci_id pci_id_igbvf_map[] = {
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 359         { .vendor_id = 0, /* sentinel */ },
 360 };
 361
 362 static const struct rte_eth_desc_lim rx_desc_lim = {
 363         .nb_max = E1000_MAX_RING_DESC,
 364         .nb_min = E1000_MIN_RING_DESC,
 365         .nb_align = IGB_RXD_ALIGN,
 366 };
 367
 368 static const struct rte_eth_desc_lim tx_desc_lim = {
 369         .nb_max = E1000_MAX_RING_DESC,
 370         .nb_min = E1000_MIN_RING_DESC,
 371         .nb_align = IGB_RXD_ALIGN,
 372         .nb_seg_max = IGB_TX_MAX_SEG,
 373         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 374 };
 375
 376 static const struct eth_dev_ops eth_igb_ops = {
 377         .dev_configure        = eth_igb_configure,
 378         .dev_start            = eth_igb_start,
 379         .dev_stop             = eth_igb_stop,
 380         .dev_set_link_up      = eth_igb_dev_set_link_up,
 381         .dev_set_link_down    = eth_igb_dev_set_link_down,
 382         .dev_close            = eth_igb_close,
 383         .promiscuous_enable   = eth_igb_promiscuous_enable,
 384         .promiscuous_disable  = eth_igb_promiscuous_disable,
 385         .allmulticast_enable  = eth_igb_allmulticast_enable,
 386         .allmulticast_disable = eth_igb_allmulticast_disable,
 387         .link_update          = eth_igb_link_update,
 388         .stats_get            = eth_igb_stats_get,
 389         .xstats_get           = eth_igb_xstats_get,
 390         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 391         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 392         .xstats_get_names     = eth_igb_xstats_get_names,
 393         .stats_reset          = eth_igb_stats_reset,
 394         .xstats_reset         = eth_igb_xstats_reset,
 395         .fw_version_get       = eth_igb_fw_version_get,
 396         .dev_infos_get        = eth_igb_infos_get,
 397         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 398         .mtu_set              = eth_igb_mtu_set,
 399         .vlan_filter_set      = eth_igb_vlan_filter_set,
 400         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 401         .vlan_offload_set     = eth_igb_vlan_offload_set,
 402         .rx_queue_setup       = eth_igb_rx_queue_setup,
 403         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 404         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 405         .rx_queue_release     = eth_igb_rx_queue_release,
 406         .rx_queue_count       = eth_igb_rx_queue_count,
 407         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 408         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 409         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 410         .tx_queue_setup       = eth_igb_tx_queue_setup,
 411         .tx_queue_release     = eth_igb_tx_queue_release,
 412         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 413         .dev_led_on           = eth_igb_led_on,
 414         .dev_led_off          = eth_igb_led_off,
 415         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 416         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 417         .mac_addr_add         = eth_igb_rar_set,
 418         .mac_addr_remove      = eth_igb_rar_clear,
 419         .mac_addr_set         = eth_igb_default_mac_addr_set,
 420         .reta_update          = eth_igb_rss_reta_update,
 421         .reta_query           = eth_igb_rss_reta_query,
 422         .rss_hash_update      = eth_igb_rss_hash_update,
 423         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 424         .filter_ctrl          = eth_igb_filter_ctrl,
 425         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 426         .rxq_info_get         = igb_rxq_info_get,
 427         .txq_info_get         = igb_txq_info_get,
 428         .timesync_enable      = igb_timesync_enable,
 429         .timesync_disable     = igb_timesync_disable,
 430         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 431         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 432         .get_reg              = eth_igb_get_regs,
 433         .get_eeprom_length    = eth_igb_get_eeprom_length,
 434         .get_eeprom           = eth_igb_get_eeprom,
 435         .set_eeprom           = eth_igb_set_eeprom,
 436         .timesync_adjust_time = igb_timesync_adjust_time,
 437         .timesync_read_time   = igb_timesync_read_time,
 438         .timesync_write_time  = igb_timesync_write_time,
 439 };
 440
 441 /*
 442  * dev_ops for virtual function, bare necessities for basic vf
 443  * operation have been implemented
 444  */
 445 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 446         .dev_configure        = igbvf_dev_configure,
 447         .dev_start            = igbvf_dev_start,
 448         .dev_stop             = igbvf_dev_stop,
 449         .dev_close            = igbvf_dev_close,
 450         .promiscuous_enable   = igbvf_promiscuous_enable,
 451         .promiscuous_disable  = igbvf_promiscuous_disable,
 452         .allmulticast_enable  = igbvf_allmulticast_enable,
 453         .allmulticast_disable = igbvf_allmulticast_disable,
 454         .link_update          = eth_igb_link_update,
 455         .stats_get            = eth_igbvf_stats_get,
 456         .xstats_get           = eth_igbvf_xstats_get,
 457         .xstats_get_names     = eth_igbvf_xstats_get_names,
 458         .stats_reset          = eth_igbvf_stats_reset,
 459         .xstats_reset         = eth_igbvf_stats_reset,
 460         .vlan_filter_set      = igbvf_vlan_filter_set,
 461         .dev_infos_get        = eth_igbvf_infos_get,
 462         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 463         .rx_queue_setup       = eth_igb_rx_queue_setup,
 464         .rx_queue_release     = eth_igb_rx_queue_release,
 465         .tx_queue_setup       = eth_igb_tx_queue_setup,
 466         .tx_queue_release     = eth_igb_tx_queue_release,
 467         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 468         .rxq_info_get         = igb_rxq_info_get,
 469         .txq_info_get         = igb_txq_info_get,
 470         .mac_addr_set         = igbvf_default_mac_addr_set,
 471         .get_reg              = igbvf_get_regs,
 472 };
 473
 474 /* store statistics names and its offset in stats structure */
 475 struct rte_igb_xstats_name_off {
 476         char name[RTE_ETH_XSTATS_NAME_SIZE];
 477         unsigned offset;
 478 };
 479
 480 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 481         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 482         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 483         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 484         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 485         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 486         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 487         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 488                 ecol)},
 489         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 490         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 491         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 492         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 493         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 494         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 495         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 496         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 497         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 498         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 499         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 500                 fcruc)},
 501         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 502         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 503         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 504         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 505         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 506                 prc1023)},
 507         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 508                 prc1522)},
 509         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 510         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 511         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 512         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 513         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 514         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 515         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 516         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 517         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 518         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 519         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 520         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 521         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 522         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 523         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 524         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 525         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 526         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 527                 ptc1023)},
 528         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 529                 ptc1522)},
 530         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 531         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 532         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 533         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 534         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 535         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 536         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 537
 538         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 539 };
 540
 541 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 542                 sizeof(rte_igb_stats_strings[0]))
 543
 544 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 545         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 546         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 547         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 548         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 549         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 550 };
 551
 552 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 553                 sizeof(rte_igbvf_stats_strings[0]))
 554
 555 /**
 556  * Atomically reads the link status information from global
 557  * structure rte_eth_dev.
 558  *
 559  * @param dev
 560  *   - Pointer to the structure rte_eth_dev to read from.
 561  *   - Pointer to the buffer to be saved with the link status.
 562  *
 563  * @return
 564  *   - On success, zero.
 565  *   - On failure, negative value.
 566  */
 567 static inline int
 568 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 569                                 struct rte_eth_link *link)
 570 {
 571         struct rte_eth_link *dst = link;
 572         struct rte_eth_link *src = &(dev->data->dev_link);
 573
 574         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 575                                         *(uint64_t *)src) == 0)
 576                 return -1;
 577
 578         return 0;
 579 }
 580
 581 /**
 582  * Atomically writes the link status information into global
 583  * structure rte_eth_dev.
 584  *
 585  * @param dev
 586  *   - Pointer to the structure rte_eth_dev to read from.
 587  *   - Pointer to the buffer to be saved with the link status.
 588  *
 589  * @return
 590  *   - On success, zero.
 591  *   - On failure, negative value.
 592  */
 593 static inline int
 594 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 595                                 struct rte_eth_link *link)
 596 {
 597         struct rte_eth_link *dst = &(dev->data->dev_link);
 598         struct rte_eth_link *src = link;
 599
 600         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 601                                         *(uint64_t *)src) == 0)
 602                 return -1;
 603
 604         return 0;
 605 }
 606
 607 static inline void
 608 igb_intr_enable(struct rte_eth_dev *dev)
 609 {
 610         struct e1000_interrupt *intr =
 611                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 612         struct e1000_hw *hw =
 613                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 614
 615         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 616         E1000_WRITE_FLUSH(hw);
 617 }
 618
 619 static void
 620 igb_intr_disable(struct e1000_hw *hw)
 621 {
 622         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 623         E1000_WRITE_FLUSH(hw);
 624 }
 625
 626 static inline void
 627 igbvf_intr_enable(struct rte_eth_dev *dev)
 628 {
 629         struct e1000_hw *hw =
 630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632         /* only for mailbox */
 633         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 634         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 635         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 636         E1000_WRITE_FLUSH(hw);
 637 }
 638
 639 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 640 static void
 641 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 642 {
 643         uint32_t tmp = 0;
 644
 645         /* mailbox */
 646         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 647         tmp |= E1000_VTIVAR_VALID;
 648         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 649 }
 650
 651 static void
 652 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 653 {
 654         struct e1000_hw *hw =
 655                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 656
 657         /* Configure VF other cause ivar */
 658         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 659 }
 660
 661 static inline int32_t
 662 igb_pf_reset_hw(struct e1000_hw *hw)
 663 {
 664         uint32_t ctrl_ext;
 665         int32_t status;
 666
 667         status = e1000_reset_hw(hw);
 668
 669         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 670         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 671         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 672         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 673         E1000_WRITE_FLUSH(hw);
 674
 675         return status;
 676 }
 677
 678 static void
 679 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 680 {
 681         struct e1000_hw *hw =
 682                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 683
 684
 685         hw->vendor_id = pci_dev->id.vendor_id;
 686         hw->device_id = pci_dev->id.device_id;
 687         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 688         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 689
 690         e1000_set_mac_type(hw);
 691
 692         /* need to check if it is a vf device below */
 693 }
 694
 695 static int
 696 igb_reset_swfw_lock(struct e1000_hw *hw)
 697 {
 698         int ret_val;
 699
 700         /*
 701          * Do mac ops initialization manually here, since we will need
 702          * some function pointers set by this call.
 703          */
 704         ret_val = e1000_init_mac_params(hw);
 705         if (ret_val)
 706                 return ret_val;
 707
 708         /*
 709          * SMBI lock should not fail in this early stage. If this is the case,
 710          * it is due to an improper exit of the application.
 711          * So force the release of the faulty lock.
 712          */
 713         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 714                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 715         }
 716         e1000_put_hw_semaphore_generic(hw);
 717
 718         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 719                 uint16_t mask;
 720
 721                 /*
 722                  * Phy lock should not fail in this early stage. If this is the case,
 723                  * it is due to an improper exit of the application.
 724                  * So force the release of the faulty lock.
 725                  */
 726                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 727                 if (hw->bus.func > E1000_FUNC_1)
 728                         mask <<= 2;
 729                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 730                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 731                                     hw->bus.func);
 732                 }
 733                 hw->mac.ops.release_swfw_sync(hw, mask);
 734
 735                 /*
 736                  * This one is more tricky since it is common to all ports; but
 737                  * swfw_sync retries last long enough (1s) to be almost sure that if
 738                  * lock can not be taken it is due to an improper lock of the
 739                  * semaphore.
 740                  */
 741                 mask = E1000_SWFW_EEP_SM;
 742                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 743                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 744                 }
 745                 hw->mac.ops.release_swfw_sync(hw, mask);
 746         }
 747
 748         return E1000_SUCCESS;
 749 }
 750
 751 /* Remove all ntuple filters of the device */
 752 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 753 {
 754         struct e1000_filter_info *filter_info =
 755                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 756         struct e1000_5tuple_filter *p_5tuple;
 757         struct e1000_2tuple_filter *p_2tuple;
 758
 759         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 760                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 761                         p_5tuple, entries);
 762                         rte_free(p_5tuple);
 763         }
 764         filter_info->fivetuple_mask = 0;
 765         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 766                 TAILQ_REMOVE(&filter_info->twotuple_list,
 767                         p_2tuple, entries);
 768                         rte_free(p_2tuple);
 769         }
 770         filter_info->twotuple_mask = 0;
 771
 772         return 0;
 773 }
 774
 775 /* Remove all flex filters of the device */
 776 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 777 {
 778         struct e1000_filter_info *filter_info =
 779                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 780         struct e1000_flex_filter *p_flex;
 781
 782         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 783                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 784                 rte_free(p_flex);
 785         }
 786         filter_info->flex_mask = 0;
 787
 788         return 0;
 789 }
 790
 791 static int
 792 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 793 {
 794         int error = 0;
 795         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 796         struct e1000_hw *hw =
 797                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 798         struct e1000_vfta * shadow_vfta =
 799                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 800         struct e1000_filter_info *filter_info =
 801                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 802         struct e1000_adapter *adapter =
 803                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 804
 805         uint32_t ctrl_ext;
 806
 807         eth_dev->dev_ops = &eth_igb_ops;
 808         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 809         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 810         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 811
 812         /* for secondary processes, we don't initialise any further as primary
 813          * has already done this work. Only check we don't need a different
 814          * RX function */
 815         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 816                 if (eth_dev->data->scattered_rx)
 817                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 818                 return 0;
 819         }
 820
 821         rte_eth_copy_pci_info(eth_dev, pci_dev);
 822
 823         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 824
 825         igb_identify_hardware(eth_dev, pci_dev);
 826         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 827                 error = -EIO;
 828                 goto err_late;
 829         }
 830
 831         e1000_get_bus_info(hw);
 832
 833         /* Reset any pending lock */
 834         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 835                 error = -EIO;
 836                 goto err_late;
 837         }
 838
 839         /* Finish initialization */
 840         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 841                 error = -EIO;
 842                 goto err_late;
 843         }
 844
 845         hw->mac.autoneg = 1;
 846         hw->phy.autoneg_wait_to_complete = 0;
 847         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 848
 849         /* Copper options */
 850         if (hw->phy.media_type == e1000_media_type_copper) {
 851                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 852                 hw->phy.disable_polarity_correction = 0;
 853                 hw->phy.ms_type = e1000_ms_hw_default;
 854         }
 855
 856         /*
 857          * Start from a known state, this is important in reading the nvm
 858          * and mac from that.
 859          */
 860         igb_pf_reset_hw(hw);
 861
 862         /* Make sure we have a good EEPROM before we read from it */
 863         if (e1000_validate_nvm_checksum(hw) < 0) {
 864                 /*
 865                  * Some PCI-E parts fail the first check due to
 866                  * the link being in sleep state, call it again,
 867                  * if it fails a second time its a real issue.
 868                  */
 869                 if (e1000_validate_nvm_checksum(hw) < 0) {
 870                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 871                         error = -EIO;
 872                         goto err_late;
 873                 }
 874         }
 875
 876         /* Read the permanent MAC address out of the EEPROM */
 877         if (e1000_read_mac_addr(hw) != 0) {
 878                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 879                 error = -EIO;
 880                 goto err_late;
 881         }
 882
 883         /* Allocate memory for storing MAC addresses */
 884         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 885                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 886         if (eth_dev->data->mac_addrs == NULL) {
 887                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 888                                                 "store MAC addresses",
 889                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 890                 error = -ENOMEM;
 891                 goto err_late;
 892         }
 893
 894         /* Copy the permanent MAC address */
 895         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 896
 897         /* initialize the vfta */
 898         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 899
 900         /* Now initialize the hardware */
 901         if (igb_hardware_init(hw) != 0) {
 902                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 903                 rte_free(eth_dev->data->mac_addrs);
 904                 eth_dev->data->mac_addrs = NULL;
 905                 error = -ENODEV;
 906                 goto err_late;
 907         }
 908         hw->mac.get_link_status = 1;
 909         adapter->stopped = 0;
 910
 911         /* Indicate SOL/IDER usage */
 912         if (e1000_check_reset_block(hw) < 0) {
 913                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 914                                         "SOL/IDER session");
 915         }
 916
 917         /* initialize PF if max_vfs not zero */
 918         igb_pf_host_init(eth_dev);
 919
 920         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 921         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 922         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 923         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 924         E1000_WRITE_FLUSH(hw);
 925
 926         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 927                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 928                      pci_dev->id.device_id);
 929
 930         rte_intr_callback_register(&pci_dev->intr_handle,
 931                                    eth_igb_interrupt_handler,
 932                                    (void *)eth_dev);
 933
 934         /* enable uio/vfio intr/eventfd mapping */
 935         rte_intr_enable(&pci_dev->intr_handle);
 936
 937         /* enable support intr */
 938         igb_intr_enable(eth_dev);
 939
 940         /* initialize filter info */
 941         memset(filter_info, 0,
 942                sizeof(struct e1000_filter_info));
 943
 944         TAILQ_INIT(&filter_info->flex_list);
 945         TAILQ_INIT(&filter_info->twotuple_list);
 946         TAILQ_INIT(&filter_info->fivetuple_list);
 947
 948         TAILQ_INIT(&igb_filter_ntuple_list);
 949         TAILQ_INIT(&igb_filter_ethertype_list);
 950         TAILQ_INIT(&igb_filter_syn_list);
 951         TAILQ_INIT(&igb_filter_flex_list);
 952         TAILQ_INIT(&igb_flow_list);
 953
 954         return 0;
 955
 956 err_late:
 957         igb_hw_control_release(hw);
 958
 959         return error;
 960 }
 961
 962 static int
 963 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 964 {
 965         struct rte_pci_device *pci_dev;
 966         struct rte_intr_handle *intr_handle;
 967         struct e1000_hw *hw;
 968         struct e1000_adapter *adapter =
 969                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 970         struct e1000_filter_info *filter_info =
 971                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 972
 973         PMD_INIT_FUNC_TRACE();
 974
 975         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 976                 return -EPERM;
 977
 978         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 979         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 980         intr_handle = &pci_dev->intr_handle;
 981
 982         if (adapter->stopped == 0)
 983                 eth_igb_close(eth_dev);
 984
 985         eth_dev->dev_ops = NULL;
 986         eth_dev->rx_pkt_burst = NULL;
 987         eth_dev->tx_pkt_burst = NULL;
 988
 989         /* Reset any pending lock */
 990         igb_reset_swfw_lock(hw);
 991
 992         rte_free(eth_dev->data->mac_addrs);
 993         eth_dev->data->mac_addrs = NULL;
 994
 995         /* uninitialize PF if max_vfs not zero */
 996         igb_pf_host_uninit(eth_dev);
 997
 998         /* disable uio intr before callback unregister */
 999         rte_intr_disable(intr_handle);
1000         rte_intr_callback_unregister(intr_handle,
1001                                      eth_igb_interrupt_handler, eth_dev);
1002
1003         /* clear the SYN filter info */
1004         filter_info->syn_info = 0;
1005
1006         /* clear the ethertype filters info */
1007         filter_info->ethertype_mask = 0;
1008         memset(filter_info->ethertype_filters, 0,
1009                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1010
1011         /* remove all ntuple filters of the device */
1012         igb_ntuple_filter_uninit(eth_dev);
1013
1014         /* remove all flex filters of the device */
1015         igb_flex_filter_uninit(eth_dev);
1016
1017         /* clear all the filters list */
1018         igb_filterlist_flush(eth_dev);
1019
1020         return 0;
1021 }
1022
1023 /*
1024  * Virtual Function device init
1025  */
1026 static int
1027 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1028 {
1029         struct rte_pci_device *pci_dev;
1030         struct rte_intr_handle *intr_handle;
1031         struct e1000_adapter *adapter =
1032                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1033         struct e1000_hw *hw =
1034                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1035         int diag;
1036         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1037
1038         PMD_INIT_FUNC_TRACE();
1039
1040         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1041         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1042         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1043         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1044
1045         /* for secondary processes, we don't initialise any further as primary
1046          * has already done this work. Only check we don't need a different
1047          * RX function */
1048         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1049                 if (eth_dev->data->scattered_rx)
1050                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1051                 return 0;
1052         }
1053
1054         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1055         rte_eth_copy_pci_info(eth_dev, pci_dev);
1056
1057         hw->device_id = pci_dev->id.device_id;
1058         hw->vendor_id = pci_dev->id.vendor_id;
1059         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1060         adapter->stopped = 0;
1061
1062         /* Initialize the shared code (base driver) */
1063         diag = e1000_setup_init_funcs(hw, TRUE);
1064         if (diag != 0) {
1065                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1066                         diag);
1067                 return -EIO;
1068         }
1069
1070         /* init_mailbox_params */
1071         hw->mbx.ops.init_params(hw);
1072
1073         /* Disable the interrupts for VF */
1074         igbvf_intr_disable(hw);
1075
1076         diag = hw->mac.ops.reset_hw(hw);
1077
1078         /* Allocate memory for storing MAC addresses */
1079         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1080                 hw->mac.rar_entry_count, 0);
1081         if (eth_dev->data->mac_addrs == NULL) {
1082                 PMD_INIT_LOG(ERR,
1083                         "Failed to allocate %d bytes needed to store MAC "
1084                         "addresses",
1085                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1086                 return -ENOMEM;
1087         }
1088
1089         /* Generate a random MAC address, if none was assigned by PF. */
1090         if (is_zero_ether_addr(perm_addr)) {
1091                 eth_random_addr(perm_addr->addr_bytes);
1092                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1093                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1094                              "%02x:%02x:%02x:%02x:%02x:%02x",
1095                              perm_addr->addr_bytes[0],
1096                              perm_addr->addr_bytes[1],
1097                              perm_addr->addr_bytes[2],
1098                              perm_addr->addr_bytes[3],
1099                              perm_addr->addr_bytes[4],
1100                              perm_addr->addr_bytes[5]);
1101         }
1102
1103         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1104         if (diag) {
1105                 rte_free(eth_dev->data->mac_addrs);
1106                 eth_dev->data->mac_addrs = NULL;
1107                 return diag;
1108         }
1109         /* Copy the permanent MAC address */
1110         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1111                         &eth_dev->data->mac_addrs[0]);
1112
1113         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1114                      "mac.type=%s",
1115                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1116                      pci_dev->id.device_id, "igb_mac_82576_vf");
1117
1118         intr_handle = &pci_dev->intr_handle;
1119         rte_intr_callback_register(intr_handle,
1120                                    eth_igbvf_interrupt_handler, eth_dev);
1121
1122         return 0;
1123 }
1124
1125 static int
1126 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1127 {
1128         struct e1000_adapter *adapter =
1129                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1130         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1131
1132         PMD_INIT_FUNC_TRACE();
1133
1134         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1135                 return -EPERM;
1136
1137         if (adapter->stopped == 0)
1138                 igbvf_dev_close(eth_dev);
1139
1140         eth_dev->dev_ops = NULL;
1141         eth_dev->rx_pkt_burst = NULL;
1142         eth_dev->tx_pkt_burst = NULL;
1143
1144         rte_free(eth_dev->data->mac_addrs);
1145         eth_dev->data->mac_addrs = NULL;
1146
1147         /* disable uio intr before callback unregister */
1148         rte_intr_disable(&pci_dev->intr_handle);
1149         rte_intr_callback_unregister(&pci_dev->intr_handle,
1150                                      eth_igbvf_interrupt_handler,
1151                                      (void *)eth_dev);
1152
1153         return 0;
1154 }
1155
1156 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1157         struct rte_pci_device *pci_dev)
1158 {
1159         return rte_eth_dev_pci_generic_probe(pci_dev,
1160                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1161 }
1162
1163 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1164 {
1165         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1166 }
1167
1168 static struct rte_pci_driver rte_igb_pmd = {
1169         .id_table = pci_id_igb_map,
1170         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1171                      RTE_PCI_DRV_IOVA_AS_VA,
1172         .probe = eth_igb_pci_probe,
1173         .remove = eth_igb_pci_remove,
1174 };
1175
1176
1177 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1178         struct rte_pci_device *pci_dev)
1179 {
1180         return rte_eth_dev_pci_generic_probe(pci_dev,
1181                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1182 }
1183
1184 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1185 {
1186         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1187 }
1188
1189 /*
1190  * virtual function driver struct
1191  */
1192 static struct rte_pci_driver rte_igbvf_pmd = {
1193         .id_table = pci_id_igbvf_map,
1194         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1195         .probe = eth_igbvf_pci_probe,
1196         .remove = eth_igbvf_pci_remove,
1197 };
1198
1199 static void
1200 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1201 {
1202         struct e1000_hw *hw =
1203                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1205         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1206         rctl |= E1000_RCTL_VFE;
1207         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1208 }
1209
1210 static int
1211 igb_check_mq_mode(struct rte_eth_dev *dev)
1212 {
1213         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1214         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1215         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1216         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1217
1218         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1219             tx_mq_mode == ETH_MQ_TX_DCB ||
1220             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1221                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1222                 return -EINVAL;
1223         }
1224         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1225                 /* Check multi-queue mode.
1226                  * To no break software we accept ETH_MQ_RX_NONE as this might
1227                  * be used to turn off VLAN filter.
1228                  */
1229
1230                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1231                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1232                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1233                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1234                 } else {
1235                         /* Only support one queue on VFs.
1236                          * RSS together with SRIOV is not supported.
1237                          */
1238                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1239                                         " wrong mq_mode rx %d.",
1240                                         rx_mq_mode);
1241                         return -EINVAL;
1242                 }
1243                 /* TX mode is not used here, so mode might be ignored.*/
1244                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1245                         /* SRIOV only works in VMDq enable mode */
1246                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1247                                         " TX mode %d is not supported. "
1248                                         " Driver will behave as %d mode.",
1249                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1250                 }
1251
1252                 /* check valid queue number */
1253                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1254                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1255                                         " only support one queue on VFs.");
1256                         return -EINVAL;
1257                 }
1258         } else {
1259                 /* To no break software that set invalid mode, only display
1260                  * warning if invalid mode is used.
1261                  */
1262                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1263                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1264                     rx_mq_mode != ETH_MQ_RX_RSS) {
1265                         /* RSS together with VMDq not supported*/
1266                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1267                                      rx_mq_mode);
1268                         return -EINVAL;
1269                 }
1270
1271                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1272                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1273                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1274                                         " Due to txmode is meaningless in this"
1275                                         " driver, just ignore.",
1276                                         tx_mq_mode);
1277                 }
1278         }
1279         return 0;
1280 }
1281
1282 static int
1283 eth_igb_configure(struct rte_eth_dev *dev)
1284 {
1285         struct e1000_interrupt *intr =
1286                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1287         int ret;
1288
1289         PMD_INIT_FUNC_TRACE();
1290
1291         /* multipe queue mode checking */
1292         ret  = igb_check_mq_mode(dev);
1293         if (ret != 0) {
1294                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1295                             ret);
1296                 return ret;
1297         }
1298
1299         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1300         PMD_INIT_FUNC_TRACE();
1301
1302         return 0;
1303 }
1304
1305 static int
1306 eth_igb_start(struct rte_eth_dev *dev)
1307 {
1308         struct e1000_hw *hw =
1309                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310         struct e1000_adapter *adapter =
1311                 E1000_DEV_PRIVATE(dev->data->dev_private);
1312         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1313         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1314         int ret, mask;
1315         uint32_t intr_vector = 0;
1316         uint32_t ctrl_ext;
1317         uint32_t *speeds;
1318         int num_speeds;
1319         bool autoneg;
1320
1321         PMD_INIT_FUNC_TRACE();
1322
1323         /* disable uio/vfio intr/eventfd mapping */
1324         rte_intr_disable(intr_handle);
1325
1326         /* Power up the phy. Needed to make the link go Up */
1327         eth_igb_dev_set_link_up(dev);
1328
1329         /*
1330          * Packet Buffer Allocation (PBA)
1331          * Writing PBA sets the receive portion of the buffer
1332          * the remainder is used for the transmit buffer.
1333          */
1334         if (hw->mac.type == e1000_82575) {
1335                 uint32_t pba;
1336
1337                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1338                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1339         }
1340
1341         /* Put the address into the Receive Address Array */
1342         e1000_rar_set(hw, hw->mac.addr, 0);
1343
1344         /* Initialize the hardware */
1345         if (igb_hardware_init(hw)) {
1346                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1347                 return -EIO;
1348         }
1349         adapter->stopped = 0;
1350
1351         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1352
1353         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1354         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1355         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1356         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1357         E1000_WRITE_FLUSH(hw);
1358
1359         /* configure PF module if SRIOV enabled */
1360         igb_pf_host_configure(dev);
1361
1362         /* check and configure queue intr-vector mapping */
1363         if ((rte_intr_cap_multiple(intr_handle) ||
1364              !RTE_ETH_DEV_SRIOV(dev).active) &&
1365             dev->data->dev_conf.intr_conf.rxq != 0) {
1366                 intr_vector = dev->data->nb_rx_queues;
1367                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1368                         return -1;
1369         }
1370
1371         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1372                 intr_handle->intr_vec =
1373                         rte_zmalloc("intr_vec",
1374                                     dev->data->nb_rx_queues * sizeof(int), 0);
1375                 if (intr_handle->intr_vec == NULL) {
1376                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1377                                      " intr_vec", dev->data->nb_rx_queues);
1378                         return -ENOMEM;
1379                 }
1380         }
1381
1382         /* confiugre msix for rx interrupt */
1383         eth_igb_configure_msix_intr(dev);
1384
1385         /* Configure for OS presence */
1386         igb_init_manageability(hw);
1387
1388         eth_igb_tx_init(dev);
1389
1390         /* This can fail when allocating mbufs for descriptor rings */
1391         ret = eth_igb_rx_init(dev);
1392         if (ret) {
1393                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1394                 igb_dev_clear_queues(dev);
1395                 return ret;
1396         }
1397
1398         e1000_clear_hw_cntrs_base_generic(hw);
1399
1400         /*
1401          * VLAN Offload Settings
1402          */
1403         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1404                         ETH_VLAN_EXTEND_MASK;
1405         ret = eth_igb_vlan_offload_set(dev, mask);
1406         if (ret) {
1407                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1408                 igb_dev_clear_queues(dev);
1409                 return ret;
1410         }
1411
1412         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1413                 /* Enable VLAN filter since VMDq always use VLAN filter */
1414                 igb_vmdq_vlan_hw_filter_enable(dev);
1415         }
1416
1417         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1418                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1419                 (hw->mac.type == e1000_i211)) {
1420                 /* Configure EITR with the maximum possible value (0xFFFF) */
1421                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1422         }
1423
1424         /* Setup link speed and duplex */
1425         speeds = &dev->data->dev_conf.link_speeds;
1426         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1427                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1428                 hw->mac.autoneg = 1;
1429         } else {
1430                 num_speeds = 0;
1431                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1432
1433                 /* Reset */
1434                 hw->phy.autoneg_advertised = 0;
1435
1436                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1437                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1438                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1439                         num_speeds = -1;
1440                         goto error_invalid_config;
1441                 }
1442                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1443                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1444                         num_speeds++;
1445                 }
1446                 if (*speeds & ETH_LINK_SPEED_10M) {
1447                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1448                         num_speeds++;
1449                 }
1450                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1451                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1452                         num_speeds++;
1453                 }
1454                 if (*speeds & ETH_LINK_SPEED_100M) {
1455                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1456                         num_speeds++;
1457                 }
1458                 if (*speeds & ETH_LINK_SPEED_1G) {
1459                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1460                         num_speeds++;
1461                 }
1462                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1463                         goto error_invalid_config;
1464
1465                 /* Set/reset the mac.autoneg based on the link speed,
1466                  * fixed or not
1467                  */
1468                 if (!autoneg) {
1469                         hw->mac.autoneg = 0;
1470                         hw->mac.forced_speed_duplex =
1471                                         hw->phy.autoneg_advertised;
1472                 } else {
1473                         hw->mac.autoneg = 1;
1474                 }
1475         }
1476
1477         e1000_setup_link(hw);
1478
1479         if (rte_intr_allow_others(intr_handle)) {
1480                 /* check if lsc interrupt is enabled */
1481                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1482                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1483                 else
1484                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1485         } else {
1486                 rte_intr_callback_unregister(intr_handle,
1487                                              eth_igb_interrupt_handler,
1488                                              (void *)dev);
1489                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1490                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1491                                      " no intr multiplex");
1492         }
1493
1494         /* check if rxq interrupt is enabled */
1495         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1496             rte_intr_dp_is_en(intr_handle))
1497                 eth_igb_rxq_interrupt_setup(dev);
1498
1499         /* enable uio/vfio intr/eventfd mapping */
1500         rte_intr_enable(intr_handle);
1501
1502         /* resume enabled intr since hw reset */
1503         igb_intr_enable(dev);
1504
1505         /* restore all types filter */
1506         igb_filter_restore(dev);
1507
1508         PMD_INIT_LOG(DEBUG, "<<");
1509
1510         return 0;
1511
1512 error_invalid_config:
1513         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1514                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1515         igb_dev_clear_queues(dev);
1516         return -EINVAL;
1517 }
1518
1519 /*********************************************************************
1520  *
1521  *  This routine disables all traffic on the adapter by issuing a
1522  *  global reset on the MAC.
1523  *
1524  **********************************************************************/
1525 static void
1526 eth_igb_stop(struct rte_eth_dev *dev)
1527 {
1528         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1529         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1530         struct rte_eth_link link;
1531         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1532
1533         igb_intr_disable(hw);
1534
1535         /* disable intr eventfd mapping */
1536         rte_intr_disable(intr_handle);
1537
1538         igb_pf_reset_hw(hw);
1539         E1000_WRITE_REG(hw, E1000_WUC, 0);
1540
1541         /* Set bit for Go Link disconnect */
1542         if (hw->mac.type >= e1000_82580) {
1543                 uint32_t phpm_reg;
1544
1545                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1546                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1547                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1548         }
1549
1550         /* Power down the phy. Needed to make the link go Down */
1551         eth_igb_dev_set_link_down(dev);
1552
1553         igb_dev_clear_queues(dev);
1554
1555         /* clear the recorded link status */
1556         memset(&link, 0, sizeof(link));
1557         rte_igb_dev_atomic_write_link_status(dev, &link);
1558
1559         if (!rte_intr_allow_others(intr_handle))
1560                 /* resume to the default handler */
1561                 rte_intr_callback_register(intr_handle,
1562                                            eth_igb_interrupt_handler,
1563                                            (void *)dev);
1564
1565         /* Clean datapath event and queue/vec mapping */
1566         rte_intr_efd_disable(intr_handle);
1567         if (intr_handle->intr_vec != NULL) {
1568                 rte_free(intr_handle->intr_vec);
1569                 intr_handle->intr_vec = NULL;
1570         }
1571 }
1572
1573 static int
1574 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1575 {
1576         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577
1578         if (hw->phy.media_type == e1000_media_type_copper)
1579                 e1000_power_up_phy(hw);
1580         else
1581                 e1000_power_up_fiber_serdes_link(hw);
1582
1583         return 0;
1584 }
1585
1586 static int
1587 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1588 {
1589         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1590
1591         if (hw->phy.media_type == e1000_media_type_copper)
1592                 e1000_power_down_phy(hw);
1593         else
1594                 e1000_shutdown_fiber_serdes_link(hw);
1595
1596         return 0;
1597 }
1598
1599 static void
1600 eth_igb_close(struct rte_eth_dev *dev)
1601 {
1602         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1603         struct e1000_adapter *adapter =
1604                 E1000_DEV_PRIVATE(dev->data->dev_private);
1605         struct rte_eth_link link;
1606         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1607         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1608
1609         eth_igb_stop(dev);
1610         adapter->stopped = 1;
1611
1612         e1000_phy_hw_reset(hw);
1613         igb_release_manageability(hw);
1614         igb_hw_control_release(hw);
1615
1616         /* Clear bit for Go Link disconnect */
1617         if (hw->mac.type >= e1000_82580) {
1618                 uint32_t phpm_reg;
1619
1620                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1621                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1622                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1623         }
1624
1625         igb_dev_free_queues(dev);
1626
1627         if (intr_handle->intr_vec) {
1628                 rte_free(intr_handle->intr_vec);
1629                 intr_handle->intr_vec = NULL;
1630         }
1631
1632         memset(&link, 0, sizeof(link));
1633         rte_igb_dev_atomic_write_link_status(dev, &link);
1634 }
1635
1636 static int
1637 igb_get_rx_buffer_size(struct e1000_hw *hw)
1638 {
1639         uint32_t rx_buf_size;
1640         if (hw->mac.type == e1000_82576) {
1641                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1642         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1643                 /* PBS needs to be translated according to a lookup table */
1644                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1645                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1646                 rx_buf_size = (rx_buf_size << 10);
1647         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1648                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1649         } else {
1650                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1651         }
1652
1653         return rx_buf_size;
1654 }
1655
1656 /*********************************************************************
1657  *
1658  *  Initialize the hardware
1659  *
1660  **********************************************************************/
1661 static int
1662 igb_hardware_init(struct e1000_hw *hw)
1663 {
1664         uint32_t rx_buf_size;
1665         int diag;
1666
1667         /* Let the firmware know the OS is in control */
1668         igb_hw_control_acquire(hw);
1669
1670         /*
1671          * These parameters control the automatic generation (Tx) and
1672          * response (Rx) to Ethernet PAUSE frames.
1673          * - High water mark should allow for at least two standard size (1518)
1674          *   frames to be received after sending an XOFF.
1675          * - Low water mark works best when it is very near the high water mark.
1676          *   This allows the receiver to restart by sending XON when it has
1677          *   drained a bit. Here we use an arbitrary value of 1500 which will
1678          *   restart after one full frame is pulled from the buffer. There
1679          *   could be several smaller frames in the buffer and if so they will
1680          *   not trigger the XON until their total number reduces the buffer
1681          *   by 1500.
1682          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1683          */
1684         rx_buf_size = igb_get_rx_buffer_size(hw);
1685
1686         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1687         hw->fc.low_water = hw->fc.high_water - 1500;
1688         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1689         hw->fc.send_xon = 1;
1690
1691         /* Set Flow control, use the tunable location if sane */
1692         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1693                 hw->fc.requested_mode = igb_fc_setting;
1694         else
1695                 hw->fc.requested_mode = e1000_fc_none;
1696
1697         /* Issue a global reset */
1698         igb_pf_reset_hw(hw);
1699         E1000_WRITE_REG(hw, E1000_WUC, 0);
1700
1701         diag = e1000_init_hw(hw);
1702         if (diag < 0)
1703                 return diag;
1704
1705         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1706         e1000_get_phy_info(hw);
1707         e1000_check_for_link(hw);
1708
1709         return 0;
1710 }
1711
1712 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1713 static void
1714 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1715 {
1716         int pause_frames;
1717
1718         uint64_t old_gprc  = stats->gprc;
1719         uint64_t old_gptc  = stats->gptc;
1720         uint64_t old_tpr   = stats->tpr;
1721         uint64_t old_tpt   = stats->tpt;
1722         uint64_t old_rpthc = stats->rpthc;
1723         uint64_t old_hgptc = stats->hgptc;
1724
1725         if(hw->phy.media_type == e1000_media_type_copper ||
1726             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1727                 stats->symerrs +=
1728                     E1000_READ_REG(hw,E1000_SYMERRS);
1729                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1730         }
1731
1732         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1733         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1734         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1735         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1736
1737         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1738         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1739         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1740         stats->dc += E1000_READ_REG(hw, E1000_DC);
1741         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1742         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1743         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1744         /*
1745         ** For watchdog management we need to know if we have been
1746         ** paused during the last interval, so capture that here.
1747         */
1748         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1749         stats->xoffrxc += pause_frames;
1750         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1751         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1752         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1753         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1754         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1755         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1756         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1757         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1758         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1759         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1760         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1761         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1762
1763         /* For the 64-bit byte counters the low dword must be read first. */
1764         /* Both registers clear on the read of the high dword */
1765
1766         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1767         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1768         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1769         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1770         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1771         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1772         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1773
1774         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1775         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1776         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1777         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1778         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1779
1780         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1781         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1782
1783         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1784         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1785         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1786         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1787         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1788         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1789
1790         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1791         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1792         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1793         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1794         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1795         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1796         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1797         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1798
1799         /* Interrupt Counts */
1800
1801         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1802         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1803         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1804         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1805         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1806         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1807         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1808         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1809         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1810
1811         /* Host to Card Statistics */
1812
1813         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1814         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1815         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1816         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1817         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1818         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1819         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1820         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1821         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1822         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1823         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1824         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1825         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1826         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1827         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1828         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1829
1830         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1831         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1832         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1833         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1834         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1835         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1836 }
1837
1838 static int
1839 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1840 {
1841         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         struct e1000_hw_stats *stats =
1843                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1844
1845         igb_read_stats_registers(hw, stats);
1846
1847         if (rte_stats == NULL)
1848                 return -EINVAL;
1849
1850         /* Rx Errors */
1851         rte_stats->imissed = stats->mpc;
1852         rte_stats->ierrors = stats->crcerrs +
1853                              stats->rlec + stats->ruc + stats->roc +
1854                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1855
1856         /* Tx Errors */
1857         rte_stats->oerrors = stats->ecol + stats->latecol;
1858
1859         rte_stats->ipackets = stats->gprc;
1860         rte_stats->opackets = stats->gptc;
1861         rte_stats->ibytes   = stats->gorc;
1862         rte_stats->obytes   = stats->gotc;
1863         return 0;
1864 }
1865
1866 static void
1867 eth_igb_stats_reset(struct rte_eth_dev *dev)
1868 {
1869         struct e1000_hw_stats *hw_stats =
1870                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1871
1872         /* HW registers are cleared on read */
1873         eth_igb_stats_get(dev, NULL);
1874
1875         /* Reset software totals */
1876         memset(hw_stats, 0, sizeof(*hw_stats));
1877 }
1878
1879 static void
1880 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1881 {
1882         struct e1000_hw_stats *stats =
1883                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1884
1885         /* HW registers are cleared on read */
1886         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1887
1888         /* Reset software totals */
1889         memset(stats, 0, sizeof(*stats));
1890 }
1891
1892 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1893         struct rte_eth_xstat_name *xstats_names,
1894         __rte_unused unsigned int size)
1895 {
1896         unsigned i;
1897
1898         if (xstats_names == NULL)
1899                 return IGB_NB_XSTATS;
1900
1901         /* Note: limit checked in rte_eth_xstats_names() */
1902
1903         for (i = 0; i < IGB_NB_XSTATS; i++) {
1904                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1905                          "%s", rte_igb_stats_strings[i].name);
1906         }
1907
1908         return IGB_NB_XSTATS;
1909 }
1910
1911 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1912                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1913                 unsigned int limit)
1914 {
1915         unsigned int i;
1916
1917         if (!ids) {
1918                 if (xstats_names == NULL)
1919                         return IGB_NB_XSTATS;
1920
1921                 for (i = 0; i < IGB_NB_XSTATS; i++)
1922                         snprintf(xstats_names[i].name,
1923                                         sizeof(xstats_names[i].name),
1924                                         "%s", rte_igb_stats_strings[i].name);
1925
1926                 return IGB_NB_XSTATS;
1927
1928         } else {
1929                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1930
1931                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1932                                 IGB_NB_XSTATS);
1933
1934                 for (i = 0; i < limit; i++) {
1935                         if (ids[i] >= IGB_NB_XSTATS) {
1936                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1937                                 return -1;
1938                         }
1939                         strcpy(xstats_names[i].name,
1940                                         xstats_names_copy[ids[i]].name);
1941                 }
1942                 return limit;
1943         }
1944 }
1945
1946 static int
1947 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1948                    unsigned n)
1949 {
1950         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         struct e1000_hw_stats *hw_stats =
1952                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1953         unsigned i;
1954
1955         if (n < IGB_NB_XSTATS)
1956                 return IGB_NB_XSTATS;
1957
1958         igb_read_stats_registers(hw, hw_stats);
1959
1960         /* If this is a reset xstats is NULL, and we have cleared the
1961          * registers by reading them.
1962          */
1963         if (!xstats)
1964                 return 0;
1965
1966         /* Extended stats */
1967         for (i = 0; i < IGB_NB_XSTATS; i++) {
1968                 xstats[i].id = i;
1969                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1970                         rte_igb_stats_strings[i].offset);
1971         }
1972
1973         return IGB_NB_XSTATS;
1974 }
1975
1976 static int
1977 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1978                 uint64_t *values, unsigned int n)
1979 {
1980         unsigned int i;
1981
1982         if (!ids) {
1983                 struct e1000_hw *hw =
1984                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985                 struct e1000_hw_stats *hw_stats =
1986                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1987
1988                 if (n < IGB_NB_XSTATS)
1989                         return IGB_NB_XSTATS;
1990
1991                 igb_read_stats_registers(hw, hw_stats);
1992
1993                 /* If this is a reset xstats is NULL, and we have cleared the
1994                  * registers by reading them.
1995                  */
1996                 if (!values)
1997                         return 0;
1998
1999                 /* Extended stats */
2000                 for (i = 0; i < IGB_NB_XSTATS; i++)
2001                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2002                                         rte_igb_stats_strings[i].offset);
2003
2004                 return IGB_NB_XSTATS;
2005
2006         } else {
2007                 uint64_t values_copy[IGB_NB_XSTATS];
2008
2009                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2010                                 IGB_NB_XSTATS);
2011
2012                 for (i = 0; i < n; i++) {
2013                         if (ids[i] >= IGB_NB_XSTATS) {
2014                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2015                                 return -1;
2016                         }
2017                         values[i] = values_copy[ids[i]];
2018                 }
2019                 return n;
2020         }
2021 }
2022
2023 static void
2024 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2025 {
2026         /* Good Rx packets, include VF loopback */
2027         UPDATE_VF_STAT(E1000_VFGPRC,
2028             hw_stats->last_gprc, hw_stats->gprc);
2029
2030         /* Good Rx octets, include VF loopback */
2031         UPDATE_VF_STAT(E1000_VFGORC,
2032             hw_stats->last_gorc, hw_stats->gorc);
2033
2034         /* Good Tx packets, include VF loopback */
2035         UPDATE_VF_STAT(E1000_VFGPTC,
2036             hw_stats->last_gptc, hw_stats->gptc);
2037
2038         /* Good Tx octets, include VF loopback */
2039         UPDATE_VF_STAT(E1000_VFGOTC,
2040             hw_stats->last_gotc, hw_stats->gotc);
2041
2042         /* Rx Multicst packets */
2043         UPDATE_VF_STAT(E1000_VFMPRC,
2044             hw_stats->last_mprc, hw_stats->mprc);
2045
2046         /* Good Rx loopback packets */
2047         UPDATE_VF_STAT(E1000_VFGPRLBC,
2048             hw_stats->last_gprlbc, hw_stats->gprlbc);
2049
2050         /* Good Rx loopback octets */
2051         UPDATE_VF_STAT(E1000_VFGORLBC,
2052             hw_stats->last_gorlbc, hw_stats->gorlbc);
2053
2054         /* Good Tx loopback packets */
2055         UPDATE_VF_STAT(E1000_VFGPTLBC,
2056             hw_stats->last_gptlbc, hw_stats->gptlbc);
2057
2058         /* Good Tx loopback octets */
2059         UPDATE_VF_STAT(E1000_VFGOTLBC,
2060             hw_stats->last_gotlbc, hw_stats->gotlbc);
2061 }
2062
2063 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2064                                      struct rte_eth_xstat_name *xstats_names,
2065                                      __rte_unused unsigned limit)
2066 {
2067         unsigned i;
2068
2069         if (xstats_names != NULL)
2070                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2071                         snprintf(xstats_names[i].name,
2072                                 sizeof(xstats_names[i].name), "%s",
2073                                 rte_igbvf_stats_strings[i].name);
2074                 }
2075         return IGBVF_NB_XSTATS;
2076 }
2077
2078 static int
2079 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2080                      unsigned n)
2081 {
2082         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2084                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2085         unsigned i;
2086
2087         if (n < IGBVF_NB_XSTATS)
2088                 return IGBVF_NB_XSTATS;
2089
2090         igbvf_read_stats_registers(hw, hw_stats);
2091
2092         if (!xstats)
2093                 return 0;
2094
2095         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2096                 xstats[i].id = i;
2097                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2098                         rte_igbvf_stats_strings[i].offset);
2099         }
2100
2101         return IGBVF_NB_XSTATS;
2102 }
2103
2104 static int
2105 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2106 {
2107         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2108         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2109                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2110
2111         igbvf_read_stats_registers(hw, hw_stats);
2112
2113         if (rte_stats == NULL)
2114                 return -EINVAL;
2115
2116         rte_stats->ipackets = hw_stats->gprc;
2117         rte_stats->ibytes = hw_stats->gorc;
2118         rte_stats->opackets = hw_stats->gptc;
2119         rte_stats->obytes = hw_stats->gotc;
2120         return 0;
2121 }
2122
2123 static void
2124 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2125 {
2126         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2127                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2128
2129         /* Sync HW register to the last stats */
2130         eth_igbvf_stats_get(dev, NULL);
2131
2132         /* reset HW current stats*/
2133         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2134                offsetof(struct e1000_vf_stats, gprc));
2135 }
2136
2137 static int
2138 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2139                        size_t fw_size)
2140 {
2141         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142         struct e1000_fw_version fw;
2143         int ret;
2144
2145         e1000_get_fw_version(hw, &fw);
2146
2147         switch (hw->mac.type) {
2148         case e1000_i210:
2149         case e1000_i211:
2150                 if (!(e1000_get_flash_presence_i210(hw))) {
2151                         ret = snprintf(fw_version, fw_size,
2152                                  "%2d.%2d-%d",
2153                                  fw.invm_major, fw.invm_minor,
2154                                  fw.invm_img_type);
2155                         break;
2156                 }
2157                 /* fall through */
2158         default:
2159                 /* if option rom is valid, display its version too */
2160                 if (fw.or_valid) {
2161                         ret = snprintf(fw_version, fw_size,
2162                                  "%d.%d, 0x%08x, %d.%d.%d",
2163                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2164                                  fw.or_major, fw.or_build, fw.or_patch);
2165                 /* no option rom */
2166                 } else {
2167                         if (fw.etrack_id != 0X0000) {
2168                                 ret = snprintf(fw_version, fw_size,
2169                                          "%d.%d, 0x%08x",
2170                                          fw.eep_major, fw.eep_minor,
2171                                          fw.etrack_id);
2172                         } else {
2173                                 ret = snprintf(fw_version, fw_size,
2174                                          "%d.%d.%d",
2175                                          fw.eep_major, fw.eep_minor,
2176                                          fw.eep_build);
2177                         }
2178                 }
2179                 break;
2180         }
2181
2182         ret += 1; /* add the size of '\0' */
2183         if (fw_size < (u32)ret)
2184                 return ret;
2185         else
2186                 return 0;
2187 }
2188
2189 static void
2190 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2191 {
2192         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193
2194         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2195         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2196         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2197         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2198         dev_info->rx_offload_capa =
2199                 DEV_RX_OFFLOAD_VLAN_STRIP |
2200                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2201                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2202                 DEV_RX_OFFLOAD_TCP_CKSUM;
2203         dev_info->tx_offload_capa =
2204                 DEV_TX_OFFLOAD_VLAN_INSERT |
2205                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2206                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2207                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2208                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2209                 DEV_TX_OFFLOAD_TCP_TSO;
2210
2211         switch (hw->mac.type) {
2212         case e1000_82575:
2213                 dev_info->max_rx_queues = 4;
2214                 dev_info->max_tx_queues = 4;
2215                 dev_info->max_vmdq_pools = 0;
2216                 break;
2217
2218         case e1000_82576:
2219                 dev_info->max_rx_queues = 16;
2220                 dev_info->max_tx_queues = 16;
2221                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2222                 dev_info->vmdq_queue_num = 16;
2223                 break;
2224
2225         case e1000_82580:
2226                 dev_info->max_rx_queues = 8;
2227                 dev_info->max_tx_queues = 8;
2228                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2229                 dev_info->vmdq_queue_num = 8;
2230                 break;
2231
2232         case e1000_i350:
2233                 dev_info->max_rx_queues = 8;
2234                 dev_info->max_tx_queues = 8;
2235                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2236                 dev_info->vmdq_queue_num = 8;
2237                 break;
2238
2239         case e1000_i354:
2240                 dev_info->max_rx_queues = 8;
2241                 dev_info->max_tx_queues = 8;
2242                 break;
2243
2244         case e1000_i210:
2245                 dev_info->max_rx_queues = 4;
2246                 dev_info->max_tx_queues = 4;
2247                 dev_info->max_vmdq_pools = 0;
2248                 break;
2249
2250         case e1000_i211:
2251                 dev_info->max_rx_queues = 2;
2252                 dev_info->max_tx_queues = 2;
2253                 dev_info->max_vmdq_pools = 0;
2254                 break;
2255
2256         default:
2257                 /* Should not happen */
2258                 break;
2259         }
2260         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2261         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2262         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2263
2264         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2265                 .rx_thresh = {
2266                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2267                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2268                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2269                 },
2270                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2271                 .rx_drop_en = 0,
2272         };
2273
2274         dev_info->default_txconf = (struct rte_eth_txconf) {
2275                 .tx_thresh = {
2276                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2277                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2278                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2279                 },
2280                 .txq_flags = 0,
2281         };
2282
2283         dev_info->rx_desc_lim = rx_desc_lim;
2284         dev_info->tx_desc_lim = tx_desc_lim;
2285
2286         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2287                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2288                         ETH_LINK_SPEED_1G;
2289 }
2290
2291 static const uint32_t *
2292 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2293 {
2294         static const uint32_t ptypes[] = {
2295                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2296                 RTE_PTYPE_L2_ETHER,
2297                 RTE_PTYPE_L3_IPV4,
2298                 RTE_PTYPE_L3_IPV4_EXT,
2299                 RTE_PTYPE_L3_IPV6,
2300                 RTE_PTYPE_L3_IPV6_EXT,
2301                 RTE_PTYPE_L4_TCP,
2302                 RTE_PTYPE_L4_UDP,
2303                 RTE_PTYPE_L4_SCTP,
2304                 RTE_PTYPE_TUNNEL_IP,
2305                 RTE_PTYPE_INNER_L3_IPV6,
2306                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2307                 RTE_PTYPE_INNER_L4_TCP,
2308                 RTE_PTYPE_INNER_L4_UDP,
2309                 RTE_PTYPE_UNKNOWN
2310         };
2311
2312         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2313             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2314                 return ptypes;
2315         return NULL;
2316 }
2317
2318 static void
2319 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2320 {
2321         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322
2323         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2324         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2325         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2326         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2327         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2328                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2329                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2330                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2331         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2332                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2333                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2334                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2335                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2336                                 DEV_TX_OFFLOAD_TCP_TSO;
2337         switch (hw->mac.type) {
2338         case e1000_vfadapt:
2339                 dev_info->max_rx_queues = 2;
2340                 dev_info->max_tx_queues = 2;
2341                 break;
2342         case e1000_vfadapt_i350:
2343                 dev_info->max_rx_queues = 1;
2344                 dev_info->max_tx_queues = 1;
2345                 break;
2346         default:
2347                 /* Should not happen */
2348                 break;
2349         }
2350
2351         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2352                 .rx_thresh = {
2353                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2354                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2355                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2356                 },
2357                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2358                 .rx_drop_en = 0,
2359         };
2360
2361         dev_info->default_txconf = (struct rte_eth_txconf) {
2362                 .tx_thresh = {
2363                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2364                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2365                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2366                 },
2367                 .txq_flags = 0,
2368         };
2369
2370         dev_info->rx_desc_lim = rx_desc_lim;
2371         dev_info->tx_desc_lim = tx_desc_lim;
2372 }
2373
2374 /* return 0 means link status changed, -1 means not changed */
2375 static int
2376 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2377 {
2378         struct e1000_hw *hw =
2379                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380         struct rte_eth_link link, old;
2381         int link_check, count;
2382
2383         link_check = 0;
2384         hw->mac.get_link_status = 1;
2385
2386         /* possible wait-to-complete in up to 9 seconds */
2387         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2388                 /* Read the real link status */
2389                 switch (hw->phy.media_type) {
2390                 case e1000_media_type_copper:
2391                         /* Do the work to read phy */
2392                         e1000_check_for_link(hw);
2393                         link_check = !hw->mac.get_link_status;
2394                         break;
2395
2396                 case e1000_media_type_fiber:
2397                         e1000_check_for_link(hw);
2398                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2399                                       E1000_STATUS_LU);
2400                         break;
2401
2402                 case e1000_media_type_internal_serdes:
2403                         e1000_check_for_link(hw);
2404                         link_check = hw->mac.serdes_has_link;
2405                         break;
2406
2407                 /* VF device is type_unknown */
2408                 case e1000_media_type_unknown:
2409                         eth_igbvf_link_update(hw);
2410                         link_check = !hw->mac.get_link_status;
2411                         break;
2412
2413                 default:
2414                         break;
2415                 }
2416                 if (link_check || wait_to_complete == 0)
2417                         break;
2418                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2419         }
2420         memset(&link, 0, sizeof(link));
2421         rte_igb_dev_atomic_read_link_status(dev, &link);
2422         old = link;
2423
2424         /* Now we check if a transition has happened */
2425         if (link_check) {
2426                 uint16_t duplex, speed;
2427                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2428                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2429                                 ETH_LINK_FULL_DUPLEX :
2430                                 ETH_LINK_HALF_DUPLEX;
2431                 link.link_speed = speed;
2432                 link.link_status = ETH_LINK_UP;
2433                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2434                                 ETH_LINK_SPEED_FIXED);
2435         } else if (!link_check) {
2436                 link.link_speed = 0;
2437                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2438                 link.link_status = ETH_LINK_DOWN;
2439                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2440         }
2441         rte_igb_dev_atomic_write_link_status(dev, &link);
2442
2443         /* not changed */
2444         if (old.link_status == link.link_status)
2445                 return -1;
2446
2447         /* changed */
2448         return 0;
2449 }
2450
2451 /*
2452  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2453  * For ASF and Pass Through versions of f/w this means
2454  * that the driver is loaded.
2455  */
2456 static void
2457 igb_hw_control_acquire(struct e1000_hw *hw)
2458 {
2459         uint32_t ctrl_ext;
2460
2461         /* Let firmware know the driver has taken over */
2462         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2463         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2464 }
2465
2466 /*
2467  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2468  * For ASF and Pass Through versions of f/w this means that the
2469  * driver is no longer loaded.
2470  */
2471 static void
2472 igb_hw_control_release(struct e1000_hw *hw)
2473 {
2474         uint32_t ctrl_ext;
2475
2476         /* Let firmware taken over control of h/w */
2477         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2478         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2479                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2480 }
2481
2482 /*
2483  * Bit of a misnomer, what this really means is
2484  * to enable OS management of the system... aka
2485  * to disable special hardware management features.
2486  */
2487 static void
2488 igb_init_manageability(struct e1000_hw *hw)
2489 {
2490         if (e1000_enable_mng_pass_thru(hw)) {
2491                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2492                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2493
2494                 /* disable hardware interception of ARP */
2495                 manc &= ~(E1000_MANC_ARP_EN);
2496
2497                 /* enable receiving management packets to the host */
2498                 manc |= E1000_MANC_EN_MNG2HOST;
2499                 manc2h |= 1 << 5;  /* Mng Port 623 */
2500                 manc2h |= 1 << 6;  /* Mng Port 664 */
2501                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2502                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2503         }
2504 }
2505
2506 static void
2507 igb_release_manageability(struct e1000_hw *hw)
2508 {
2509         if (e1000_enable_mng_pass_thru(hw)) {
2510                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2511
2512                 manc |= E1000_MANC_ARP_EN;
2513                 manc &= ~E1000_MANC_EN_MNG2HOST;
2514
2515                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2516         }
2517 }
2518
2519 static void
2520 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2521 {
2522         struct e1000_hw *hw =
2523                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524         uint32_t rctl;
2525
2526         rctl = E1000_READ_REG(hw, E1000_RCTL);
2527         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2528         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2529 }
2530
2531 static void
2532 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2533 {
2534         struct e1000_hw *hw =
2535                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536         uint32_t rctl;
2537
2538         rctl = E1000_READ_REG(hw, E1000_RCTL);
2539         rctl &= (~E1000_RCTL_UPE);
2540         if (dev->data->all_multicast == 1)
2541                 rctl |= E1000_RCTL_MPE;
2542         else
2543                 rctl &= (~E1000_RCTL_MPE);
2544         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2545 }
2546
2547 static void
2548 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2549 {
2550         struct e1000_hw *hw =
2551                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2552         uint32_t rctl;
2553
2554         rctl = E1000_READ_REG(hw, E1000_RCTL);
2555         rctl |= E1000_RCTL_MPE;
2556         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2557 }
2558
2559 static void
2560 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2561 {
2562         struct e1000_hw *hw =
2563                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2564         uint32_t rctl;
2565
2566         if (dev->data->promiscuous == 1)
2567                 return; /* must remain in all_multicast mode */
2568         rctl = E1000_READ_REG(hw, E1000_RCTL);
2569         rctl &= (~E1000_RCTL_MPE);
2570         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2571 }
2572
2573 static int
2574 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2575 {
2576         struct e1000_hw *hw =
2577                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578         struct e1000_vfta * shadow_vfta =
2579                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2580         uint32_t vfta;
2581         uint32_t vid_idx;
2582         uint32_t vid_bit;
2583
2584         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2585                               E1000_VFTA_ENTRY_MASK);
2586         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2587         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2588         if (on)
2589                 vfta |= vid_bit;
2590         else
2591                 vfta &= ~vid_bit;
2592         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2593
2594         /* update local VFTA copy */
2595         shadow_vfta->vfta[vid_idx] = vfta;
2596
2597         return 0;
2598 }
2599
2600 static int
2601 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2602                       enum rte_vlan_type vlan_type,
2603                       uint16_t tpid)
2604 {
2605         struct e1000_hw *hw =
2606                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2607         uint32_t reg, qinq;
2608
2609         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2610         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2611
2612         /* only outer TPID of double VLAN can be configured*/
2613         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2614                 reg = E1000_READ_REG(hw, E1000_VET);
2615                 reg = (reg & (~E1000_VET_VET_EXT)) |
2616                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2617                 E1000_WRITE_REG(hw, E1000_VET, reg);
2618
2619                 return 0;
2620         }
2621
2622         /* all other TPID values are read-only*/
2623         PMD_DRV_LOG(ERR, "Not supported");
2624
2625         return -ENOTSUP;
2626 }
2627
2628 static void
2629 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2630 {
2631         struct e1000_hw *hw =
2632                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2633         uint32_t reg;
2634
2635         /* Filter Table Disable */
2636         reg = E1000_READ_REG(hw, E1000_RCTL);
2637         reg &= ~E1000_RCTL_CFIEN;
2638         reg &= ~E1000_RCTL_VFE;
2639         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2640 }
2641
2642 static void
2643 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2644 {
2645         struct e1000_hw *hw =
2646                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         struct e1000_vfta * shadow_vfta =
2648                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2649         uint32_t reg;
2650         int i;
2651
2652         /* Filter Table Enable, CFI not used for packet acceptance */
2653         reg = E1000_READ_REG(hw, E1000_RCTL);
2654         reg &= ~E1000_RCTL_CFIEN;
2655         reg |= E1000_RCTL_VFE;
2656         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2657
2658         /* restore VFTA table */
2659         for (i = 0; i < IGB_VFTA_SIZE; i++)
2660                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2661 }
2662
2663 static void
2664 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2665 {
2666         struct e1000_hw *hw =
2667                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668         uint32_t reg;
2669
2670         /* VLAN Mode Disable */
2671         reg = E1000_READ_REG(hw, E1000_CTRL);
2672         reg &= ~E1000_CTRL_VME;
2673         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2674 }
2675
2676 static void
2677 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2678 {
2679         struct e1000_hw *hw =
2680                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681         uint32_t reg;
2682
2683         /* VLAN Mode Enable */
2684         reg = E1000_READ_REG(hw, E1000_CTRL);
2685         reg |= E1000_CTRL_VME;
2686         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2687 }
2688
2689 static void
2690 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2691 {
2692         struct e1000_hw *hw =
2693                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2694         uint32_t reg;
2695
2696         /* CTRL_EXT: Extended VLAN */
2697         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2698         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2699         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2700
2701         /* Update maximum packet length */
2702         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2703                 E1000_WRITE_REG(hw, E1000_RLPML,
2704                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2705                                                 VLAN_TAG_SIZE);
2706 }
2707
2708 static void
2709 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2710 {
2711         struct e1000_hw *hw =
2712                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713         uint32_t reg;
2714
2715         /* CTRL_EXT: Extended VLAN */
2716         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2717         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2718         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2719
2720         /* Update maximum packet length */
2721         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2722                 E1000_WRITE_REG(hw, E1000_RLPML,
2723                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2724                                                 2 * VLAN_TAG_SIZE);
2725 }
2726
2727 static int
2728 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2729 {
2730         if(mask & ETH_VLAN_STRIP_MASK){
2731                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2732                         igb_vlan_hw_strip_enable(dev);
2733                 else
2734                         igb_vlan_hw_strip_disable(dev);
2735         }
2736
2737         if(mask & ETH_VLAN_FILTER_MASK){
2738                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2739                         igb_vlan_hw_filter_enable(dev);
2740                 else
2741                         igb_vlan_hw_filter_disable(dev);
2742         }
2743
2744         if(mask & ETH_VLAN_EXTEND_MASK){
2745                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2746                         igb_vlan_hw_extend_enable(dev);
2747                 else
2748                         igb_vlan_hw_extend_disable(dev);
2749         }
2750
2751         return 0;
2752 }
2753
2754
2755 /**
2756  * It enables the interrupt mask and then enable the interrupt.
2757  *
2758  * @param dev
2759  *  Pointer to struct rte_eth_dev.
2760  * @param on
2761  *  Enable or Disable
2762  *
2763  * @return
2764  *  - On success, zero.
2765  *  - On failure, a negative value.
2766  */
2767 static int
2768 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2769 {
2770         struct e1000_interrupt *intr =
2771                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2772
2773         if (on)
2774                 intr->mask |= E1000_ICR_LSC;
2775         else
2776                 intr->mask &= ~E1000_ICR_LSC;
2777
2778         return 0;
2779 }
2780
2781 /* It clears the interrupt causes and enables the interrupt.
2782  * It will be called once only during nic initialized.
2783  *
2784  * @param dev
2785  *  Pointer to struct rte_eth_dev.
2786  *
2787  * @return
2788  *  - On success, zero.
2789  *  - On failure, a negative value.
2790  */
2791 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2792 {
2793         uint32_t mask, regval;
2794         struct e1000_hw *hw =
2795                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796         struct rte_eth_dev_info dev_info;
2797
2798         memset(&dev_info, 0, sizeof(dev_info));
2799         eth_igb_infos_get(dev, &dev_info);
2800
2801         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2802         regval = E1000_READ_REG(hw, E1000_EIMS);
2803         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2804
2805         return 0;
2806 }
2807
2808 /*
2809  * It reads ICR and gets interrupt causes, check it and set a bit flag
2810  * to update link status.
2811  *
2812  * @param dev
2813  *  Pointer to struct rte_eth_dev.
2814  *
2815  * @return
2816  *  - On success, zero.
2817  *  - On failure, a negative value.
2818  */
2819 static int
2820 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2821 {
2822         uint32_t icr;
2823         struct e1000_hw *hw =
2824                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2825         struct e1000_interrupt *intr =
2826                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2827
2828         igb_intr_disable(hw);
2829
2830         /* read-on-clear nic registers here */
2831         icr = E1000_READ_REG(hw, E1000_ICR);
2832
2833         intr->flags = 0;
2834         if (icr & E1000_ICR_LSC) {
2835                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2836         }
2837
2838         if (icr & E1000_ICR_VMMB)
2839                 intr->flags |= E1000_FLAG_MAILBOX;
2840
2841         return 0;
2842 }
2843
2844 /*
2845  * It executes link_update after knowing an interrupt is prsent.
2846  *
2847  * @param dev
2848  *  Pointer to struct rte_eth_dev.
2849  *
2850  * @return
2851  *  - On success, zero.
2852  *  - On failure, a negative value.
2853  */
2854 static int
2855 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2856                          struct rte_intr_handle *intr_handle)
2857 {
2858         struct e1000_hw *hw =
2859                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2860         struct e1000_interrupt *intr =
2861                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2862         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2863         uint32_t tctl, rctl;
2864         struct rte_eth_link link;
2865         int ret;
2866
2867         if (intr->flags & E1000_FLAG_MAILBOX) {
2868                 igb_pf_mbx_process(dev);
2869                 intr->flags &= ~E1000_FLAG_MAILBOX;
2870         }
2871
2872         igb_intr_enable(dev);
2873         rte_intr_enable(intr_handle);
2874
2875         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2876                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2877
2878                 /* set get_link_status to check register later */
2879                 hw->mac.get_link_status = 1;
2880                 ret = eth_igb_link_update(dev, 0);
2881
2882                 /* check if link has changed */
2883                 if (ret < 0)
2884                         return 0;
2885
2886                 memset(&link, 0, sizeof(link));
2887                 rte_igb_dev_atomic_read_link_status(dev, &link);
2888                 if (link.link_status) {
2889                         PMD_INIT_LOG(INFO,
2890                                      " Port %d: Link Up - speed %u Mbps - %s",
2891                                      dev->data->port_id,
2892                                      (unsigned)link.link_speed,
2893                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2894                                      "full-duplex" : "half-duplex");
2895                 } else {
2896                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2897                                      dev->data->port_id);
2898                 }
2899
2900                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2901                              pci_dev->addr.domain,
2902                              pci_dev->addr.bus,
2903                              pci_dev->addr.devid,
2904                              pci_dev->addr.function);
2905                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2906                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2907                 if (link.link_status) {
2908                         /* enable Tx/Rx */
2909                         tctl |= E1000_TCTL_EN;
2910                         rctl |= E1000_RCTL_EN;
2911                 } else {
2912                         /* disable Tx/Rx */
2913                         tctl &= ~E1000_TCTL_EN;
2914                         rctl &= ~E1000_RCTL_EN;
2915                 }
2916                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2917                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2918                 E1000_WRITE_FLUSH(hw);
2919                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2920                                               NULL, NULL);
2921         }
2922
2923         return 0;
2924 }
2925
2926 /**
2927  * Interrupt handler which shall be registered at first.
2928  *
2929  * @param handle
2930  *  Pointer to interrupt handle.
2931  * @param param
2932  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2933  *
2934  * @return
2935  *  void
2936  */
2937 static void
2938 eth_igb_interrupt_handler(void *param)
2939 {
2940         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2941
2942         eth_igb_interrupt_get_status(dev);
2943         eth_igb_interrupt_action(dev, dev->intr_handle);
2944 }
2945
2946 static int
2947 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2948 {
2949         uint32_t eicr;
2950         struct e1000_hw *hw =
2951                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         struct e1000_interrupt *intr =
2953                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2954
2955         igbvf_intr_disable(hw);
2956
2957         /* read-on-clear nic registers here */
2958         eicr = E1000_READ_REG(hw, E1000_EICR);
2959         intr->flags = 0;
2960
2961         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2962                 intr->flags |= E1000_FLAG_MAILBOX;
2963
2964         return 0;
2965 }
2966
2967 void igbvf_mbx_process(struct rte_eth_dev *dev)
2968 {
2969         struct e1000_hw *hw =
2970                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         struct e1000_mbx_info *mbx = &hw->mbx;
2972         u32 in_msg = 0;
2973
2974         if (mbx->ops.read(hw, &in_msg, 1, 0))
2975                 return;
2976
2977         /* PF reset VF event */
2978         if (in_msg == E1000_PF_CONTROL_MSG)
2979                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2980                                               NULL, NULL);
2981 }
2982
2983 static int
2984 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2985 {
2986         struct e1000_interrupt *intr =
2987                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2988
2989         if (intr->flags & E1000_FLAG_MAILBOX) {
2990                 igbvf_mbx_process(dev);
2991                 intr->flags &= ~E1000_FLAG_MAILBOX;
2992         }
2993
2994         igbvf_intr_enable(dev);
2995         rte_intr_enable(intr_handle);
2996
2997         return 0;
2998 }
2999
3000 static void
3001 eth_igbvf_interrupt_handler(void *param)
3002 {
3003         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3004
3005         eth_igbvf_interrupt_get_status(dev);
3006         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3007 }
3008
3009 static int
3010 eth_igb_led_on(struct rte_eth_dev *dev)
3011 {
3012         struct e1000_hw *hw;
3013
3014         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3016 }
3017
3018 static int
3019 eth_igb_led_off(struct rte_eth_dev *dev)
3020 {
3021         struct e1000_hw *hw;
3022
3023         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3024         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3025 }
3026
3027 static int
3028 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3029 {
3030         struct e1000_hw *hw;
3031         uint32_t ctrl;
3032         int tx_pause;
3033         int rx_pause;
3034
3035         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3036         fc_conf->pause_time = hw->fc.pause_time;
3037         fc_conf->high_water = hw->fc.high_water;
3038         fc_conf->low_water = hw->fc.low_water;
3039         fc_conf->send_xon = hw->fc.send_xon;
3040         fc_conf->autoneg = hw->mac.autoneg;
3041
3042         /*
3043          * Return rx_pause and tx_pause status according to actual setting of
3044          * the TFCE and RFCE bits in the CTRL register.
3045          */
3046         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3047         if (ctrl & E1000_CTRL_TFCE)
3048                 tx_pause = 1;
3049         else
3050                 tx_pause = 0;
3051
3052         if (ctrl & E1000_CTRL_RFCE)
3053                 rx_pause = 1;
3054         else
3055                 rx_pause = 0;
3056
3057         if (rx_pause && tx_pause)
3058                 fc_conf->mode = RTE_FC_FULL;
3059         else if (rx_pause)
3060                 fc_conf->mode = RTE_FC_RX_PAUSE;
3061         else if (tx_pause)
3062                 fc_conf->mode = RTE_FC_TX_PAUSE;
3063         else
3064                 fc_conf->mode = RTE_FC_NONE;
3065
3066         return 0;
3067 }
3068
3069 static int
3070 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3071 {
3072         struct e1000_hw *hw;
3073         int err;
3074         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3075                 e1000_fc_none,
3076                 e1000_fc_rx_pause,
3077                 e1000_fc_tx_pause,
3078                 e1000_fc_full
3079         };
3080         uint32_t rx_buf_size;
3081         uint32_t max_high_water;
3082         uint32_t rctl;
3083
3084         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3085         if (fc_conf->autoneg != hw->mac.autoneg)
3086                 return -ENOTSUP;
3087         rx_buf_size = igb_get_rx_buffer_size(hw);
3088         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3089
3090         /* At least reserve one Ethernet frame for watermark */
3091         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3092         if ((fc_conf->high_water > max_high_water) ||
3093             (fc_conf->high_water < fc_conf->low_water)) {
3094                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3095                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3096                 return -EINVAL;
3097         }
3098
3099         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3100         hw->fc.pause_time     = fc_conf->pause_time;
3101         hw->fc.high_water     = fc_conf->high_water;
3102         hw->fc.low_water      = fc_conf->low_water;
3103         hw->fc.send_xon       = fc_conf->send_xon;
3104
3105         err = e1000_setup_link_generic(hw);
3106         if (err == E1000_SUCCESS) {
3107
3108                 /* check if we want to forward MAC frames - driver doesn't have native
3109                  * capability to do that, so we'll write the registers ourselves */
3110
3111                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3112
3113                 /* set or clear MFLCN.PMCF bit depending on configuration */
3114                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3115                         rctl |= E1000_RCTL_PMCF;
3116                 else
3117                         rctl &= ~E1000_RCTL_PMCF;
3118
3119                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3120                 E1000_WRITE_FLUSH(hw);
3121
3122                 return 0;
3123         }
3124
3125         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3126         return -EIO;
3127 }
3128
3129 #define E1000_RAH_POOLSEL_SHIFT      (18)
3130 static int
3131 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3132                 uint32_t index, uint32_t pool)
3133 {
3134         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135         uint32_t rah;
3136
3137         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3138         rah = E1000_READ_REG(hw, E1000_RAH(index));
3139         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3140         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3141         return 0;
3142 }
3143
3144 static void
3145 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3146 {
3147         uint8_t addr[ETHER_ADDR_LEN];
3148         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149
3150         memset(addr, 0, sizeof(addr));
3151
3152         e1000_rar_set(hw, addr, index);
3153 }
3154
3155 static void
3156 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3157                                 struct ether_addr *addr)
3158 {
3159         eth_igb_rar_clear(dev, 0);
3160
3161         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3162 }
3163 /*
3164  * Virtual Function operations
3165  */
3166 static void
3167 igbvf_intr_disable(struct e1000_hw *hw)
3168 {
3169         PMD_INIT_FUNC_TRACE();
3170
3171         /* Clear interrupt mask to stop from interrupts being generated */
3172         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3173
3174         E1000_WRITE_FLUSH(hw);
3175 }
3176
3177 static void
3178 igbvf_stop_adapter(struct rte_eth_dev *dev)
3179 {
3180         u32 reg_val;
3181         u16 i;
3182         struct rte_eth_dev_info dev_info;
3183         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184
3185         memset(&dev_info, 0, sizeof(dev_info));
3186         eth_igbvf_infos_get(dev, &dev_info);
3187
3188         /* Clear interrupt mask to stop from interrupts being generated */
3189         igbvf_intr_disable(hw);
3190
3191         /* Clear any pending interrupts, flush previous writes */
3192         E1000_READ_REG(hw, E1000_EICR);
3193
3194         /* Disable the transmit unit.  Each queue must be disabled. */
3195         for (i = 0; i < dev_info.max_tx_queues; i++)
3196                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3197
3198         /* Disable the receive unit by stopping each queue */
3199         for (i = 0; i < dev_info.max_rx_queues; i++) {
3200                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3201                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3202                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3203                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3204                         ;
3205         }
3206
3207         /* flush all queues disables */
3208         E1000_WRITE_FLUSH(hw);
3209         msec_delay(2);
3210 }
3211
3212 static int eth_igbvf_link_update(struct e1000_hw *hw)
3213 {
3214         struct e1000_mbx_info *mbx = &hw->mbx;
3215         struct e1000_mac_info *mac = &hw->mac;
3216         int ret_val = E1000_SUCCESS;
3217
3218         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3219
3220         /*
3221          * We only want to run this if there has been a rst asserted.
3222          * in this case that could mean a link change, device reset,
3223          * or a virtual function reset
3224          */
3225
3226         /* If we were hit with a reset or timeout drop the link */
3227         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3228                 mac->get_link_status = TRUE;
3229
3230         if (!mac->get_link_status)
3231                 goto out;
3232
3233         /* if link status is down no point in checking to see if pf is up */
3234         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3235                 goto out;
3236
3237         /* if we passed all the tests above then the link is up and we no
3238          * longer need to check for link */
3239         mac->get_link_status = FALSE;
3240
3241 out:
3242         return ret_val;
3243 }
3244
3245
3246 static int
3247 igbvf_dev_configure(struct rte_eth_dev *dev)
3248 {
3249         struct rte_eth_conf* conf = &dev->data->dev_conf;
3250
3251         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3252                      dev->data->port_id);
3253
3254         /*
3255          * VF has no ability to enable/disable HW CRC
3256          * Keep the persistent behavior the same as Host PF
3257          */
3258 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3259         if (!conf->rxmode.hw_strip_crc) {
3260                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3261                 conf->rxmode.hw_strip_crc = 1;
3262         }
3263 #else
3264         if (conf->rxmode.hw_strip_crc) {
3265                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3266                 conf->rxmode.hw_strip_crc = 0;
3267         }
3268 #endif
3269
3270         return 0;
3271 }
3272
3273 static int
3274 igbvf_dev_start(struct rte_eth_dev *dev)
3275 {
3276         struct e1000_hw *hw =
3277                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3278         struct e1000_adapter *adapter =
3279                 E1000_DEV_PRIVATE(dev->data->dev_private);
3280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3281         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3282         int ret;
3283         uint32_t intr_vector = 0;
3284
3285         PMD_INIT_FUNC_TRACE();
3286
3287         hw->mac.ops.reset_hw(hw);
3288         adapter->stopped = 0;
3289
3290         /* Set all vfta */
3291         igbvf_set_vfta_all(dev,1);
3292
3293         eth_igbvf_tx_init(dev);
3294
3295         /* This can fail when allocating mbufs for descriptor rings */
3296         ret = eth_igbvf_rx_init(dev);
3297         if (ret) {
3298                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3299                 igb_dev_clear_queues(dev);
3300                 return ret;
3301         }
3302
3303         /* check and configure queue intr-vector mapping */
3304         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3305                 intr_vector = dev->data->nb_rx_queues;
3306                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3307                 if (ret)
3308                         return ret;
3309         }
3310
3311         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3312                 intr_handle->intr_vec =
3313                         rte_zmalloc("intr_vec",
3314                                     dev->data->nb_rx_queues * sizeof(int), 0);
3315                 if (!intr_handle->intr_vec) {
3316                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3317                                      " intr_vec", dev->data->nb_rx_queues);
3318                         return -ENOMEM;
3319                 }
3320         }
3321
3322         eth_igbvf_configure_msix_intr(dev);
3323
3324         /* enable uio/vfio intr/eventfd mapping */
3325         rte_intr_enable(intr_handle);
3326
3327         /* resume enabled intr since hw reset */
3328         igbvf_intr_enable(dev);
3329
3330         return 0;
3331 }
3332
3333 static void
3334 igbvf_dev_stop(struct rte_eth_dev *dev)
3335 {
3336         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3337         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3338
3339         PMD_INIT_FUNC_TRACE();
3340
3341         igbvf_stop_adapter(dev);
3342
3343         /*
3344           * Clear what we set, but we still keep shadow_vfta to
3345           * restore after device starts
3346           */
3347         igbvf_set_vfta_all(dev,0);
3348
3349         igb_dev_clear_queues(dev);
3350
3351         /* disable intr eventfd mapping */
3352         rte_intr_disable(intr_handle);
3353
3354         /* Clean datapath event and queue/vec mapping */
3355         rte_intr_efd_disable(intr_handle);
3356         if (intr_handle->intr_vec) {
3357                 rte_free(intr_handle->intr_vec);
3358                 intr_handle->intr_vec = NULL;
3359         }
3360 }
3361
3362 static void
3363 igbvf_dev_close(struct rte_eth_dev *dev)
3364 {
3365         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3366         struct e1000_adapter *adapter =
3367                 E1000_DEV_PRIVATE(dev->data->dev_private);
3368         struct ether_addr addr;
3369
3370         PMD_INIT_FUNC_TRACE();
3371
3372         e1000_reset_hw(hw);
3373
3374         igbvf_dev_stop(dev);
3375         adapter->stopped = 1;
3376         igb_dev_free_queues(dev);
3377
3378         /**
3379          * reprogram the RAR with a zero mac address,
3380          * to ensure that the VF traffic goes to the PF
3381          * after stop, close and detach of the VF.
3382          **/
3383
3384         memset(&addr, 0, sizeof(addr));
3385         igbvf_default_mac_addr_set(dev, &addr);
3386 }
3387
3388 static void
3389 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3390 {
3391         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3392
3393         /* Set both unicast and multicast promisc */
3394         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3395 }
3396
3397 static void
3398 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3399 {
3400         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401
3402         /* If in allmulticast mode leave multicast promisc */
3403         if (dev->data->all_multicast == 1)
3404                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3405         else
3406                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3407 }
3408
3409 static void
3410 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3411 {
3412         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3413
3414         /* In promiscuous mode multicast promisc already set */
3415         if (dev->data->promiscuous == 0)
3416                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3417 }
3418
3419 static void
3420 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3421 {
3422         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3423
3424         /* In promiscuous mode leave multicast promisc enabled */
3425         if (dev->data->promiscuous == 0)
3426                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3427 }
3428
3429 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3430 {
3431         struct e1000_mbx_info *mbx = &hw->mbx;
3432         uint32_t msgbuf[2];
3433         s32 err;
3434
3435         /* After set vlan, vlan strip will also be enabled in igb driver*/
3436         msgbuf[0] = E1000_VF_SET_VLAN;
3437         msgbuf[1] = vid;
3438         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3439         if (on)
3440                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3441
3442         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3443         if (err)
3444                 goto mbx_err;
3445
3446         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3447         if (err)
3448                 goto mbx_err;
3449
3450         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3451         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3452                 err = -EINVAL;
3453
3454 mbx_err:
3455         return err;
3456 }
3457
3458 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3459 {
3460         struct e1000_hw *hw =
3461                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462         struct e1000_vfta * shadow_vfta =
3463                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3464         int i = 0, j = 0, vfta = 0, mask = 1;
3465
3466         for (i = 0; i < IGB_VFTA_SIZE; i++){
3467                 vfta = shadow_vfta->vfta[i];
3468                 if(vfta){
3469                         mask = 1;
3470                         for (j = 0; j < 32; j++){
3471                                 if(vfta & mask)
3472                                         igbvf_set_vfta(hw,
3473                                                 (uint16_t)((i<<5)+j), on);
3474                                 mask<<=1;
3475                         }
3476                 }
3477         }
3478
3479 }
3480
3481 static int
3482 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3483 {
3484         struct e1000_hw *hw =
3485                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486         struct e1000_vfta * shadow_vfta =
3487                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3488         uint32_t vid_idx = 0;
3489         uint32_t vid_bit = 0;
3490         int ret = 0;
3491
3492         PMD_INIT_FUNC_TRACE();
3493
3494         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3495         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3496         if(ret){
3497                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3498                 return ret;
3499         }
3500         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3501         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3502
3503         /*Save what we set and retore it after device reset*/
3504         if (on)
3505                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3506         else
3507                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3508
3509         return 0;
3510 }
3511
3512 static void
3513 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3514 {
3515         struct e1000_hw *hw =
3516                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517
3518         /* index is not used by rar_set() */
3519         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3520 }
3521
3522
3523 static int
3524 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3525                         struct rte_eth_rss_reta_entry64 *reta_conf,
3526                         uint16_t reta_size)
3527 {
3528         uint8_t i, j, mask;
3529         uint32_t reta, r;
3530         uint16_t idx, shift;
3531         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532
3533         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3534                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3535                         "(%d) doesn't match the number hardware can supported "
3536                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3537                 return -EINVAL;
3538         }
3539
3540         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3541                 idx = i / RTE_RETA_GROUP_SIZE;
3542                 shift = i % RTE_RETA_GROUP_SIZE;
3543                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3544                                                 IGB_4_BIT_MASK);
3545                 if (!mask)
3546                         continue;
3547                 if (mask == IGB_4_BIT_MASK)
3548                         r = 0;
3549                 else
3550                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3551                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3552                         if (mask & (0x1 << j))
3553                                 reta |= reta_conf[idx].reta[shift + j] <<
3554                                                         (CHAR_BIT * j);
3555                         else
3556                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3557                 }
3558                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3559         }
3560
3561         return 0;
3562 }
3563
3564 static int
3565 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3566                        struct rte_eth_rss_reta_entry64 *reta_conf,
3567                        uint16_t reta_size)
3568 {
3569         uint8_t i, j, mask;
3570         uint32_t reta;
3571         uint16_t idx, shift;
3572         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3573
3574         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3575                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3576                         "(%d) doesn't match the number hardware can supported "
3577                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3578                 return -EINVAL;
3579         }
3580
3581         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3582                 idx = i / RTE_RETA_GROUP_SIZE;
3583                 shift = i % RTE_RETA_GROUP_SIZE;
3584                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3585                                                 IGB_4_BIT_MASK);
3586                 if (!mask)
3587                         continue;
3588                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3589                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3590                         if (mask & (0x1 << j))
3591                                 reta_conf[idx].reta[shift + j] =
3592                                         ((reta >> (CHAR_BIT * j)) &
3593                                                 IGB_8_BIT_MASK);
3594                 }
3595         }
3596
3597         return 0;
3598 }
3599
3600 int
3601 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3602                         struct rte_eth_syn_filter *filter,
3603                         bool add)
3604 {
3605         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3606         struct e1000_filter_info *filter_info =
3607                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3608         uint32_t synqf, rfctl;
3609
3610         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3611                 return -EINVAL;
3612
3613         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3614
3615         if (add) {
3616                 if (synqf & E1000_SYN_FILTER_ENABLE)
3617                         return -EINVAL;
3618
3619                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3620                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3621
3622                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3623                 if (filter->hig_pri)
3624                         rfctl |= E1000_RFCTL_SYNQFP;
3625                 else
3626                         rfctl &= ~E1000_RFCTL_SYNQFP;
3627
3628                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3629         } else {
3630                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3631                         return -ENOENT;
3632                 synqf = 0;
3633         }
3634
3635         filter_info->syn_info = synqf;
3636         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3637         E1000_WRITE_FLUSH(hw);
3638         return 0;
3639 }
3640
3641 static int
3642 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3643                         struct rte_eth_syn_filter *filter)
3644 {
3645         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3646         uint32_t synqf, rfctl;
3647
3648         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3649         if (synqf & E1000_SYN_FILTER_ENABLE) {
3650                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3651                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3652                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3653                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3654                 return 0;
3655         }
3656
3657         return -ENOENT;
3658 }
3659
3660 static int
3661 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3662                         enum rte_filter_op filter_op,
3663                         void *arg)
3664 {
3665         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3666         int ret;
3667
3668         MAC_TYPE_FILTER_SUP(hw->mac.type);
3669
3670         if (filter_op == RTE_ETH_FILTER_NOP)
3671                 return 0;
3672
3673         if (arg == NULL) {
3674                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3675                             filter_op);
3676                 return -EINVAL;
3677         }
3678
3679         switch (filter_op) {
3680         case RTE_ETH_FILTER_ADD:
3681                 ret = eth_igb_syn_filter_set(dev,
3682                                 (struct rte_eth_syn_filter *)arg,
3683                                 TRUE);
3684                 break;
3685         case RTE_ETH_FILTER_DELETE:
3686                 ret = eth_igb_syn_filter_set(dev,
3687                                 (struct rte_eth_syn_filter *)arg,
3688                                 FALSE);
3689                 break;
3690         case RTE_ETH_FILTER_GET:
3691                 ret = eth_igb_syn_filter_get(dev,
3692                                 (struct rte_eth_syn_filter *)arg);
3693                 break;
3694         default:
3695                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3696                 ret = -EINVAL;
3697                 break;
3698         }
3699
3700         return ret;
3701 }
3702
3703 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3704 static inline int
3705 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3706                         struct e1000_2tuple_filter_info *filter_info)
3707 {
3708         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3709                 return -EINVAL;
3710         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3711                 return -EINVAL;  /* filter index is out of range. */
3712         if (filter->tcp_flags > TCP_FLAG_ALL)
3713                 return -EINVAL;  /* flags is invalid. */
3714
3715         switch (filter->dst_port_mask) {
3716         case UINT16_MAX:
3717                 filter_info->dst_port_mask = 0;
3718                 filter_info->dst_port = filter->dst_port;
3719                 break;
3720         case 0:
3721                 filter_info->dst_port_mask = 1;
3722                 break;
3723         default:
3724                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3725                 return -EINVAL;
3726         }
3727
3728         switch (filter->proto_mask) {
3729         case UINT8_MAX:
3730                 filter_info->proto_mask = 0;
3731                 filter_info->proto = filter->proto;
3732                 break;
3733         case 0:
3734                 filter_info->proto_mask = 1;
3735                 break;
3736         default:
3737                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3738                 return -EINVAL;
3739         }
3740
3741         filter_info->priority = (uint8_t)filter->priority;
3742         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3743                 filter_info->tcp_flags = filter->tcp_flags;
3744         else
3745                 filter_info->tcp_flags = 0;
3746
3747         return 0;
3748 }
3749
3750 static inline struct e1000_2tuple_filter *
3751 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3752                         struct e1000_2tuple_filter_info *key)
3753 {
3754         struct e1000_2tuple_filter *it;
3755
3756         TAILQ_FOREACH(it, filter_list, entries) {
3757                 if (memcmp(key, &it->filter_info,
3758                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3759                         return it;
3760                 }
3761         }
3762         return NULL;
3763 }
3764
3765 /* inject a igb 2tuple filter to HW */
3766 static inline void
3767 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3768                            struct e1000_2tuple_filter *filter)
3769 {
3770         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3771         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3772         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3773         int i;
3774
3775         i = filter->index;
3776         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3777         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3778                 imir |= E1000_IMIR_PORT_BP;
3779         else
3780                 imir &= ~E1000_IMIR_PORT_BP;
3781
3782         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3783
3784         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3785         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3786         ttqf |= (uint32_t)(filter->filter_info.proto &
3787                                                 E1000_TTQF_PROTOCOL_MASK);
3788         if (filter->filter_info.proto_mask == 0)
3789                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3790
3791         /* tcp flags bits setting. */
3792         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3793                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3794                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3795                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3796                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3797                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3798                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3799                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3800                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3801                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3802                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3803                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3804                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3805         } else {
3806                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3807         }
3808         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3809         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3810         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3811 }
3812
3813 /*
3814  * igb_add_2tuple_filter - add a 2tuple filter
3815  *
3816  * @param
3817  * dev: Pointer to struct rte_eth_dev.
3818  * ntuple_filter: ponter to the filter that will be added.
3819  *
3820  * @return
3821  *    - On success, zero.
3822  *    - On failure, a negative value.
3823  */
3824 static int
3825 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3826                         struct rte_eth_ntuple_filter *ntuple_filter)
3827 {
3828         struct e1000_filter_info *filter_info =
3829                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3830         struct e1000_2tuple_filter *filter;
3831         int i, ret;
3832
3833         filter = rte_zmalloc("e1000_2tuple_filter",
3834                         sizeof(struct e1000_2tuple_filter), 0);
3835         if (filter == NULL)
3836                 return -ENOMEM;
3837
3838         ret = ntuple_filter_to_2tuple(ntuple_filter,
3839                                       &filter->filter_info);
3840         if (ret < 0) {
3841                 rte_free(filter);
3842                 return ret;
3843         }
3844         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3845                                          &filter->filter_info) != NULL) {
3846                 PMD_DRV_LOG(ERR, "filter exists.");
3847                 rte_free(filter);
3848                 return -EEXIST;
3849         }
3850         filter->queue = ntuple_filter->queue;
3851
3852         /*
3853          * look for an unused 2tuple filter index,
3854          * and insert the filter to list.
3855          */
3856         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3857                 if (!(filter_info->twotuple_mask & (1 << i))) {
3858                         filter_info->twotuple_mask |= 1 << i;
3859                         filter->index = i;
3860                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3861                                           filter,
3862                                           entries);
3863                         break;
3864                 }
3865         }
3866         if (i >= E1000_MAX_TTQF_FILTERS) {
3867                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3868                 rte_free(filter);
3869                 return -ENOSYS;
3870         }
3871
3872         igb_inject_2uple_filter(dev, filter);
3873         return 0;
3874 }
3875
3876 int
3877 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3878                         struct e1000_2tuple_filter *filter)
3879 {
3880         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3881         struct e1000_filter_info *filter_info =
3882                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3883
3884         filter_info->twotuple_mask &= ~(1 << filter->index);
3885         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3886         rte_free(filter);
3887
3888         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3889         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3890         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3891         return 0;
3892 }
3893
3894 /*
3895  * igb_remove_2tuple_filter - remove a 2tuple filter
3896  *
3897  * @param
3898  * dev: Pointer to struct rte_eth_dev.
3899  * ntuple_filter: ponter to the filter that will be removed.
3900  *
3901  * @return
3902  *    - On success, zero.
3903  *    - On failure, a negative value.
3904  */
3905 static int
3906 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3907                         struct rte_eth_ntuple_filter *ntuple_filter)
3908 {
3909         struct e1000_filter_info *filter_info =
3910                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3911         struct e1000_2tuple_filter_info filter_2tuple;
3912         struct e1000_2tuple_filter *filter;
3913         int ret;
3914
3915         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3916         ret = ntuple_filter_to_2tuple(ntuple_filter,
3917                                       &filter_2tuple);
3918         if (ret < 0)
3919                 return ret;
3920
3921         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3922                                          &filter_2tuple);
3923         if (filter == NULL) {
3924                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3925                 return -ENOENT;
3926         }
3927
3928         igb_delete_2tuple_filter(dev, filter);
3929
3930         return 0;
3931 }
3932
3933 /* inject a igb flex filter to HW */
3934 static inline void
3935 igb_inject_flex_filter(struct rte_eth_dev *dev,
3936                            struct e1000_flex_filter *filter)
3937 {
3938         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939         uint32_t wufc, queueing;
3940         uint32_t reg_off;
3941         uint8_t i, j = 0;
3942
3943         wufc = E1000_READ_REG(hw, E1000_WUFC);
3944         if (filter->index < E1000_MAX_FHFT)
3945                 reg_off = E1000_FHFT(filter->index);
3946         else
3947                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3948
3949         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3950                         (E1000_WUFC_FLX0 << filter->index));
3951         queueing = filter->filter_info.len |
3952                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3953                 (filter->filter_info.priority <<
3954                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3955         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3956                         queueing);
3957
3958         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3959                 E1000_WRITE_REG(hw, reg_off,
3960                                 filter->filter_info.dwords[j]);
3961                 reg_off += sizeof(uint32_t);
3962                 E1000_WRITE_REG(hw, reg_off,
3963                                 filter->filter_info.dwords[++j]);
3964                 reg_off += sizeof(uint32_t);
3965                 E1000_WRITE_REG(hw, reg_off,
3966                         (uint32_t)filter->filter_info.mask[i]);
3967                 reg_off += sizeof(uint32_t) * 2;
3968                 ++j;
3969         }
3970 }
3971
3972 static inline struct e1000_flex_filter *
3973 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3974                         struct e1000_flex_filter_info *key)
3975 {
3976         struct e1000_flex_filter *it;
3977
3978         TAILQ_FOREACH(it, filter_list, entries) {
3979                 if (memcmp(key, &it->filter_info,
3980                         sizeof(struct e1000_flex_filter_info)) == 0)
3981                         return it;
3982         }
3983
3984         return NULL;
3985 }
3986
3987 /* remove a flex byte filter
3988  * @param
3989  * dev: Pointer to struct rte_eth_dev.
3990  * filter: the pointer of the filter will be removed.
3991  */
3992 void
3993 igb_remove_flex_filter(struct rte_eth_dev *dev,
3994                         struct e1000_flex_filter *filter)
3995 {
3996         struct e1000_filter_info *filter_info =
3997                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3998         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999         uint32_t wufc, i;
4000         uint32_t reg_off;
4001
4002         wufc = E1000_READ_REG(hw, E1000_WUFC);
4003         if (filter->index < E1000_MAX_FHFT)
4004                 reg_off = E1000_FHFT(filter->index);
4005         else
4006                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4007
4008         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4009                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4010
4011         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4012                 (~(E1000_WUFC_FLX0 << filter->index)));
4013
4014         filter_info->flex_mask &= ~(1 << filter->index);
4015         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4016         rte_free(filter);
4017 }
4018
4019 int
4020 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4021                         struct rte_eth_flex_filter *filter,
4022                         bool add)
4023 {
4024         struct e1000_filter_info *filter_info =
4025                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4026         struct e1000_flex_filter *flex_filter, *it;
4027         uint32_t mask;
4028         uint8_t shift, i;
4029
4030         flex_filter = rte_zmalloc("e1000_flex_filter",
4031                         sizeof(struct e1000_flex_filter), 0);
4032         if (flex_filter == NULL)
4033                 return -ENOMEM;
4034
4035         flex_filter->filter_info.len = filter->len;
4036         flex_filter->filter_info.priority = filter->priority;
4037         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4038         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4039                 mask = 0;
4040                 /* reverse bits in flex filter's mask*/
4041                 for (shift = 0; shift < CHAR_BIT; shift++) {
4042                         if (filter->mask[i] & (0x01 << shift))
4043                                 mask |= (0x80 >> shift);
4044                 }
4045                 flex_filter->filter_info.mask[i] = mask;
4046         }
4047
4048         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4049                                 &flex_filter->filter_info);
4050         if (it == NULL && !add) {
4051                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4052                 rte_free(flex_filter);
4053                 return -ENOENT;
4054         }
4055         if (it != NULL && add) {
4056                 PMD_DRV_LOG(ERR, "filter exists.");
4057                 rte_free(flex_filter);
4058                 return -EEXIST;
4059         }
4060
4061         if (add) {
4062                 flex_filter->queue = filter->queue;
4063                 /*
4064                  * look for an unused flex filter index
4065                  * and insert the filter into the list.
4066                  */
4067                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4068                         if (!(filter_info->flex_mask & (1 << i))) {
4069                                 filter_info->flex_mask |= 1 << i;
4070                                 flex_filter->index = i;
4071                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4072                                         flex_filter,
4073                                         entries);
4074                                 break;
4075                         }
4076                 }
4077                 if (i >= E1000_MAX_FLEX_FILTERS) {
4078                         PMD_DRV_LOG(ERR, "flex filters are full.");
4079                         rte_free(flex_filter);
4080                         return -ENOSYS;
4081                 }
4082
4083                 igb_inject_flex_filter(dev, flex_filter);
4084
4085         } else {
4086                 igb_remove_flex_filter(dev, it);
4087                 rte_free(flex_filter);
4088         }
4089
4090         return 0;
4091 }
4092
4093 static int
4094 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4095                         struct rte_eth_flex_filter *filter)
4096 {
4097         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4098         struct e1000_filter_info *filter_info =
4099                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4100         struct e1000_flex_filter flex_filter, *it;
4101         uint32_t wufc, queueing, wufc_en = 0;
4102
4103         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4104         flex_filter.filter_info.len = filter->len;
4105         flex_filter.filter_info.priority = filter->priority;
4106         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4107         memcpy(flex_filter.filter_info.mask, filter->mask,
4108                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4109
4110         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4111                                 &flex_filter.filter_info);
4112         if (it == NULL) {
4113                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4114                 return -ENOENT;
4115         }
4116
4117         wufc = E1000_READ_REG(hw, E1000_WUFC);
4118         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4119
4120         if ((wufc & wufc_en) == wufc_en) {
4121                 uint32_t reg_off = 0;
4122                 if (it->index < E1000_MAX_FHFT)
4123                         reg_off = E1000_FHFT(it->index);
4124                 else
4125                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4126
4127                 queueing = E1000_READ_REG(hw,
4128                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4129                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4130                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4131                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4132                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4133                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4134                 return 0;
4135         }
4136         return -ENOENT;
4137 }
4138
4139 static int
4140 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4141                         enum rte_filter_op filter_op,
4142                         void *arg)
4143 {
4144         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4145         struct rte_eth_flex_filter *filter;
4146         int ret = 0;
4147
4148         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4149
4150         if (filter_op == RTE_ETH_FILTER_NOP)
4151                 return ret;
4152
4153         if (arg == NULL) {
4154                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4155                             filter_op);
4156                 return -EINVAL;
4157         }
4158
4159         filter = (struct rte_eth_flex_filter *)arg;
4160         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4161             || filter->len % sizeof(uint64_t) != 0) {
4162                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4163                 return -EINVAL;
4164         }
4165         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4166                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4167                 return -EINVAL;
4168         }
4169
4170         switch (filter_op) {
4171         case RTE_ETH_FILTER_ADD:
4172                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4173                 break;
4174         case RTE_ETH_FILTER_DELETE:
4175                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4176                 break;
4177         case RTE_ETH_FILTER_GET:
4178                 ret = eth_igb_get_flex_filter(dev, filter);
4179                 break;
4180         default:
4181                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4182                 ret = -EINVAL;
4183                 break;
4184         }
4185
4186         return ret;
4187 }
4188
4189 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4190 static inline int
4191 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4192                         struct e1000_5tuple_filter_info *filter_info)
4193 {
4194         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4195                 return -EINVAL;
4196         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4197                 return -EINVAL;  /* filter index is out of range. */
4198         if (filter->tcp_flags > TCP_FLAG_ALL)
4199                 return -EINVAL;  /* flags is invalid. */
4200
4201         switch (filter->dst_ip_mask) {
4202         case UINT32_MAX:
4203                 filter_info->dst_ip_mask = 0;
4204                 filter_info->dst_ip = filter->dst_ip;
4205                 break;
4206         case 0:
4207                 filter_info->dst_ip_mask = 1;
4208                 break;
4209         default:
4210                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4211                 return -EINVAL;
4212         }
4213
4214         switch (filter->src_ip_mask) {
4215         case UINT32_MAX:
4216                 filter_info->src_ip_mask = 0;
4217                 filter_info->src_ip = filter->src_ip;
4218                 break;
4219         case 0:
4220                 filter_info->src_ip_mask = 1;
4221                 break;
4222         default:
4223                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4224                 return -EINVAL;
4225         }
4226
4227         switch (filter->dst_port_mask) {
4228         case UINT16_MAX:
4229                 filter_info->dst_port_mask = 0;
4230                 filter_info->dst_port = filter->dst_port;
4231                 break;
4232         case 0:
4233                 filter_info->dst_port_mask = 1;
4234                 break;
4235         default:
4236                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4237                 return -EINVAL;
4238         }
4239
4240         switch (filter->src_port_mask) {
4241         case UINT16_MAX:
4242                 filter_info->src_port_mask = 0;
4243                 filter_info->src_port = filter->src_port;
4244                 break;
4245         case 0:
4246                 filter_info->src_port_mask = 1;
4247                 break;
4248         default:
4249                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4250                 return -EINVAL;
4251         }
4252
4253         switch (filter->proto_mask) {
4254         case UINT8_MAX:
4255                 filter_info->proto_mask = 0;
4256                 filter_info->proto = filter->proto;
4257                 break;
4258         case 0:
4259                 filter_info->proto_mask = 1;
4260                 break;
4261         default:
4262                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4263                 return -EINVAL;
4264         }
4265
4266         filter_info->priority = (uint8_t)filter->priority;
4267         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4268                 filter_info->tcp_flags = filter->tcp_flags;
4269         else
4270                 filter_info->tcp_flags = 0;
4271
4272         return 0;
4273 }
4274
4275 static inline struct e1000_5tuple_filter *
4276 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4277                         struct e1000_5tuple_filter_info *key)
4278 {
4279         struct e1000_5tuple_filter *it;
4280
4281         TAILQ_FOREACH(it, filter_list, entries) {
4282                 if (memcmp(key, &it->filter_info,
4283                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4284                         return it;
4285                 }
4286         }
4287         return NULL;
4288 }
4289
4290 /* inject a igb 5-tuple filter to HW */
4291 static inline void
4292 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4293                            struct e1000_5tuple_filter *filter)
4294 {
4295         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4296         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4297         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4298         uint8_t i;
4299
4300         i = filter->index;
4301         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4302         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4303                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4304         if (filter->filter_info.dst_ip_mask == 0)
4305                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4306         if (filter->filter_info.src_port_mask == 0)
4307                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4308         if (filter->filter_info.proto_mask == 0)
4309                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4310         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4311                 E1000_FTQF_QUEUE_MASK;
4312         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4313         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4314         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4315         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4316
4317         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4318         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4319
4320         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4321         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4322                 imir |= E1000_IMIR_PORT_BP;
4323         else
4324                 imir &= ~E1000_IMIR_PORT_BP;
4325         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4326
4327         /* tcp flags bits setting. */
4328         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4329                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4330                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4331                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4332                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4333                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4334                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4335                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4336                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4337                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4338                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4339                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4340                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4341         } else {
4342                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4343         }
4344         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4345         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4346 }
4347
4348 /*
4349  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4350  *
4351  * @param
4352  * dev: Pointer to struct rte_eth_dev.
4353  * ntuple_filter: ponter to the filter that will be added.
4354  *
4355  * @return
4356  *    - On success, zero.
4357  *    - On failure, a negative value.
4358  */
4359 static int
4360 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4361                         struct rte_eth_ntuple_filter *ntuple_filter)
4362 {
4363         struct e1000_filter_info *filter_info =
4364                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4365         struct e1000_5tuple_filter *filter;
4366         uint8_t i;
4367         int ret;
4368
4369         filter = rte_zmalloc("e1000_5tuple_filter",
4370                         sizeof(struct e1000_5tuple_filter), 0);
4371         if (filter == NULL)
4372                 return -ENOMEM;
4373
4374         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4375                                             &filter->filter_info);
4376         if (ret < 0) {
4377                 rte_free(filter);
4378                 return ret;
4379         }
4380
4381         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4382                                          &filter->filter_info) != NULL) {
4383                 PMD_DRV_LOG(ERR, "filter exists.");
4384                 rte_free(filter);
4385                 return -EEXIST;
4386         }
4387         filter->queue = ntuple_filter->queue;
4388
4389         /*
4390          * look for an unused 5tuple filter index,
4391          * and insert the filter to list.
4392          */
4393         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4394                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4395                         filter_info->fivetuple_mask |= 1 << i;
4396                         filter->index = i;
4397                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4398                                           filter,
4399                                           entries);
4400                         break;
4401                 }
4402         }
4403         if (i >= E1000_MAX_FTQF_FILTERS) {
4404                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4405                 rte_free(filter);
4406                 return -ENOSYS;
4407         }
4408
4409         igb_inject_5tuple_filter_82576(dev, filter);
4410         return 0;
4411 }
4412
4413 int
4414 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4415                                 struct e1000_5tuple_filter *filter)
4416 {
4417         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418         struct e1000_filter_info *filter_info =
4419                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4420
4421         filter_info->fivetuple_mask &= ~(1 << filter->index);
4422         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4423         rte_free(filter);
4424
4425         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4426                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4427         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4428         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4429         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4430         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4431         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4432         return 0;
4433 }
4434
4435 /*
4436  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4437  *
4438  * @param
4439  * dev: Pointer to struct rte_eth_dev.
4440  * ntuple_filter: ponter to the filter that will be removed.
4441  *
4442  * @return
4443  *    - On success, zero.
4444  *    - On failure, a negative value.
4445  */
4446 static int
4447 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4448                                 struct rte_eth_ntuple_filter *ntuple_filter)
4449 {
4450         struct e1000_filter_info *filter_info =
4451                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4452         struct e1000_5tuple_filter_info filter_5tuple;
4453         struct e1000_5tuple_filter *filter;
4454         int ret;
4455
4456         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4457         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4458                                             &filter_5tuple);
4459         if (ret < 0)
4460                 return ret;
4461
4462         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4463                                          &filter_5tuple);
4464         if (filter == NULL) {
4465                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4466                 return -ENOENT;
4467         }
4468
4469         igb_delete_5tuple_filter_82576(dev, filter);
4470
4471         return 0;
4472 }
4473
4474 static int
4475 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4476 {
4477         uint32_t rctl;
4478         struct e1000_hw *hw;
4479         struct rte_eth_dev_info dev_info;
4480         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4481                                      VLAN_TAG_SIZE);
4482
4483         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484
4485 #ifdef RTE_LIBRTE_82571_SUPPORT
4486         /* XXX: not bigger than max_rx_pktlen */
4487         if (hw->mac.type == e1000_82571)
4488                 return -ENOTSUP;
4489 #endif
4490         eth_igb_infos_get(dev, &dev_info);
4491
4492         /* check that mtu is within the allowed range */
4493         if ((mtu < ETHER_MIN_MTU) ||
4494             (frame_size > dev_info.max_rx_pktlen))
4495                 return -EINVAL;
4496
4497         /* refuse mtu that requires the support of scattered packets when this
4498          * feature has not been enabled before. */
4499         if (!dev->data->scattered_rx &&
4500             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4501                 return -EINVAL;
4502
4503         rctl = E1000_READ_REG(hw, E1000_RCTL);
4504
4505         /* switch to jumbo mode if needed */
4506         if (frame_size > ETHER_MAX_LEN) {
4507                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4508                 rctl |= E1000_RCTL_LPE;
4509         } else {
4510                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4511                 rctl &= ~E1000_RCTL_LPE;
4512         }
4513         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4514
4515         /* update max frame size */
4516         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4517
4518         E1000_WRITE_REG(hw, E1000_RLPML,
4519                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4520
4521         return 0;
4522 }
4523
4524 /*
4525  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4526  *
4527  * @param
4528  * dev: Pointer to struct rte_eth_dev.
4529  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4530  * add: if true, add filter, if false, remove filter
4531  *
4532  * @return
4533  *    - On success, zero.
4534  *    - On failure, a negative value.
4535  */
4536 int
4537 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4538                         struct rte_eth_ntuple_filter *ntuple_filter,
4539                         bool add)
4540 {
4541         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4542         int ret;
4543
4544         switch (ntuple_filter->flags) {
4545         case RTE_5TUPLE_FLAGS:
4546         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4547                 if (hw->mac.type != e1000_82576)
4548                         return -ENOTSUP;
4549                 if (add)
4550                         ret = igb_add_5tuple_filter_82576(dev,
4551                                                           ntuple_filter);
4552                 else
4553                         ret = igb_remove_5tuple_filter_82576(dev,
4554                                                              ntuple_filter);
4555                 break;
4556         case RTE_2TUPLE_FLAGS:
4557         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4558                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4559                         hw->mac.type != e1000_i210 &&
4560                         hw->mac.type != e1000_i211)
4561                         return -ENOTSUP;
4562                 if (add)
4563                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4564                 else
4565                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4566                 break;
4567         default:
4568                 ret = -EINVAL;
4569                 break;
4570         }
4571
4572         return ret;
4573 }
4574
4575 /*
4576  * igb_get_ntuple_filter - get a ntuple filter
4577  *
4578  * @param
4579  * dev: Pointer to struct rte_eth_dev.
4580  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4581  *
4582  * @return
4583  *    - On success, zero.
4584  *    - On failure, a negative value.
4585  */
4586 static int
4587 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4588                         struct rte_eth_ntuple_filter *ntuple_filter)
4589 {
4590         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4591         struct e1000_filter_info *filter_info =
4592                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4593         struct e1000_5tuple_filter_info filter_5tuple;
4594         struct e1000_2tuple_filter_info filter_2tuple;
4595         struct e1000_5tuple_filter *p_5tuple_filter;
4596         struct e1000_2tuple_filter *p_2tuple_filter;
4597         int ret;
4598
4599         switch (ntuple_filter->flags) {
4600         case RTE_5TUPLE_FLAGS:
4601         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4602                 if (hw->mac.type != e1000_82576)
4603                         return -ENOTSUP;
4604                 memset(&filter_5tuple,
4605                         0,
4606                         sizeof(struct e1000_5tuple_filter_info));
4607                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4608                                                     &filter_5tuple);
4609                 if (ret < 0)
4610                         return ret;
4611                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4612                                         &filter_info->fivetuple_list,
4613                                         &filter_5tuple);
4614                 if (p_5tuple_filter == NULL) {
4615                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4616                         return -ENOENT;
4617                 }
4618                 ntuple_filter->queue = p_5tuple_filter->queue;
4619                 break;
4620         case RTE_2TUPLE_FLAGS:
4621         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4622                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4623                         return -ENOTSUP;
4624                 memset(&filter_2tuple,
4625                         0,
4626                         sizeof(struct e1000_2tuple_filter_info));
4627                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4628                 if (ret < 0)
4629                         return ret;
4630                 p_2tuple_filter = igb_2tuple_filter_lookup(
4631                                         &filter_info->twotuple_list,
4632                                         &filter_2tuple);
4633                 if (p_2tuple_filter == NULL) {
4634                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4635                         return -ENOENT;
4636                 }
4637                 ntuple_filter->queue = p_2tuple_filter->queue;
4638                 break;
4639         default:
4640                 ret = -EINVAL;
4641                 break;
4642         }
4643
4644         return 0;
4645 }
4646
4647 /*
4648  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4649  * @dev: pointer to rte_eth_dev structure
4650  * @filter_op:operation will be taken.
4651  * @arg: a pointer to specific structure corresponding to the filter_op
4652  */
4653 static int
4654 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4655                                 enum rte_filter_op filter_op,
4656                                 void *arg)
4657 {
4658         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4659         int ret;
4660
4661         MAC_TYPE_FILTER_SUP(hw->mac.type);
4662
4663         if (filter_op == RTE_ETH_FILTER_NOP)
4664                 return 0;
4665
4666         if (arg == NULL) {
4667                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4668                             filter_op);
4669                 return -EINVAL;
4670         }
4671
4672         switch (filter_op) {
4673         case RTE_ETH_FILTER_ADD:
4674                 ret = igb_add_del_ntuple_filter(dev,
4675                         (struct rte_eth_ntuple_filter *)arg,
4676                         TRUE);
4677                 break;
4678         case RTE_ETH_FILTER_DELETE:
4679                 ret = igb_add_del_ntuple_filter(dev,
4680                         (struct rte_eth_ntuple_filter *)arg,
4681                         FALSE);
4682                 break;
4683         case RTE_ETH_FILTER_GET:
4684                 ret = igb_get_ntuple_filter(dev,
4685                         (struct rte_eth_ntuple_filter *)arg);
4686                 break;
4687         default:
4688                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4689                 ret = -EINVAL;
4690                 break;
4691         }
4692         return ret;
4693 }
4694
4695 static inline int
4696 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4697                         uint16_t ethertype)
4698 {
4699         int i;
4700
4701         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4702                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4703                     (filter_info->ethertype_mask & (1 << i)))
4704                         return i;
4705         }
4706         return -1;
4707 }
4708
4709 static inline int
4710 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4711                         uint16_t ethertype, uint32_t etqf)
4712 {
4713         int i;
4714
4715         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4716                 if (!(filter_info->ethertype_mask & (1 << i))) {
4717                         filter_info->ethertype_mask |= 1 << i;
4718                         filter_info->ethertype_filters[i].ethertype = ethertype;
4719                         filter_info->ethertype_filters[i].etqf = etqf;
4720                         return i;
4721                 }
4722         }
4723         return -1;
4724 }
4725
4726 int
4727 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4728                         uint8_t idx)
4729 {
4730         if (idx >= E1000_MAX_ETQF_FILTERS)
4731                 return -1;
4732         filter_info->ethertype_mask &= ~(1 << idx);
4733         filter_info->ethertype_filters[idx].ethertype = 0;
4734         filter_info->ethertype_filters[idx].etqf = 0;
4735         return idx;
4736 }
4737
4738
4739 int
4740 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4741                         struct rte_eth_ethertype_filter *filter,
4742                         bool add)
4743 {
4744         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4745         struct e1000_filter_info *filter_info =
4746                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4747         uint32_t etqf = 0;
4748         int ret;
4749
4750         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4751                 filter->ether_type == ETHER_TYPE_IPv6) {
4752                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4753                         " ethertype filter.", filter->ether_type);
4754                 return -EINVAL;
4755         }
4756
4757         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4758                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4759                 return -EINVAL;
4760         }
4761         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4762                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4763                 return -EINVAL;
4764         }
4765
4766         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4767         if (ret >= 0 && add) {
4768                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4769                             filter->ether_type);
4770                 return -EEXIST;
4771         }
4772         if (ret < 0 && !add) {
4773                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4774                             filter->ether_type);
4775                 return -ENOENT;
4776         }
4777
4778         if (add) {
4779                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4780                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4781                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4782                 ret = igb_ethertype_filter_insert(filter_info,
4783                                 filter->ether_type, etqf);
4784                 if (ret < 0) {
4785                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4786                         return -ENOSYS;
4787                 }
4788         } else {
4789                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4790                 if (ret < 0)
4791                         return -ENOSYS;
4792         }
4793         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4794         E1000_WRITE_FLUSH(hw);
4795
4796         return 0;
4797 }
4798
4799 static int
4800 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4801                         struct rte_eth_ethertype_filter *filter)
4802 {
4803         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804         struct e1000_filter_info *filter_info =
4805                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4806         uint32_t etqf;
4807         int ret;
4808
4809         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4810         if (ret < 0) {
4811                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4812                             filter->ether_type);
4813                 return -ENOENT;
4814         }
4815
4816         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4817         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4818                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4819                 filter->flags = 0;
4820                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4821                                 E1000_ETQF_QUEUE_SHIFT;
4822                 return 0;
4823         }
4824
4825         return -ENOENT;
4826 }
4827
4828 /*
4829  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4830  * @dev: pointer to rte_eth_dev structure
4831  * @filter_op:operation will be taken.
4832  * @arg: a pointer to specific structure corresponding to the filter_op
4833  */
4834 static int
4835 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4836                                 enum rte_filter_op filter_op,
4837                                 void *arg)
4838 {
4839         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840         int ret;
4841
4842         MAC_TYPE_FILTER_SUP(hw->mac.type);
4843
4844         if (filter_op == RTE_ETH_FILTER_NOP)
4845                 return 0;
4846
4847         if (arg == NULL) {
4848                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4849                             filter_op);
4850                 return -EINVAL;
4851         }
4852
4853         switch (filter_op) {
4854         case RTE_ETH_FILTER_ADD:
4855                 ret = igb_add_del_ethertype_filter(dev,
4856                         (struct rte_eth_ethertype_filter *)arg,
4857                         TRUE);
4858                 break;
4859         case RTE_ETH_FILTER_DELETE:
4860                 ret = igb_add_del_ethertype_filter(dev,
4861                         (struct rte_eth_ethertype_filter *)arg,
4862                         FALSE);
4863                 break;
4864         case RTE_ETH_FILTER_GET:
4865                 ret = igb_get_ethertype_filter(dev,
4866                         (struct rte_eth_ethertype_filter *)arg);
4867                 break;
4868         default:
4869                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4870                 ret = -EINVAL;
4871                 break;
4872         }
4873         return ret;
4874 }
4875
4876 static int
4877 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4878                      enum rte_filter_type filter_type,
4879                      enum rte_filter_op filter_op,
4880                      void *arg)
4881 {
4882         int ret = 0;
4883
4884         switch (filter_type) {
4885         case RTE_ETH_FILTER_NTUPLE:
4886                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4887                 break;
4888         case RTE_ETH_FILTER_ETHERTYPE:
4889                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4890                 break;
4891         case RTE_ETH_FILTER_SYN:
4892                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4893                 break;
4894         case RTE_ETH_FILTER_FLEXIBLE:
4895                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4896                 break;
4897         case RTE_ETH_FILTER_GENERIC:
4898                 if (filter_op != RTE_ETH_FILTER_GET)
4899                         return -EINVAL;
4900                 *(const void **)arg = &igb_flow_ops;
4901                 break;
4902         default:
4903                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4904                                                         filter_type);
4905                 break;
4906         }
4907
4908         return ret;
4909 }
4910
4911 static int
4912 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4913                          struct ether_addr *mc_addr_set,
4914                          uint32_t nb_mc_addr)
4915 {
4916         struct e1000_hw *hw;
4917
4918         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4919         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4920         return 0;
4921 }
4922
4923 static uint64_t
4924 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4925 {
4926         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4927         uint64_t systime_cycles;
4928
4929         switch (hw->mac.type) {
4930         case e1000_i210:
4931         case e1000_i211:
4932                 /*
4933                  * Need to read System Time Residue Register to be able
4934                  * to read the other two registers.
4935                  */
4936                 E1000_READ_REG(hw, E1000_SYSTIMR);
4937                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4938                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4939                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4940                                 * NSEC_PER_SEC;
4941                 break;
4942         case e1000_82580:
4943         case e1000_i350:
4944         case e1000_i354:
4945                 /*
4946                  * Need to read System Time Residue Register to be able
4947                  * to read the other two registers.
4948                  */
4949                 E1000_READ_REG(hw, E1000_SYSTIMR);
4950                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4951                 /* Only the 8 LSB are valid. */
4952                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4953                                 & 0xff) << 32;
4954                 break;
4955         default:
4956                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4957                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4958                                 << 32;
4959                 break;
4960         }
4961
4962         return systime_cycles;
4963 }
4964
4965 static uint64_t
4966 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4967 {
4968         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969         uint64_t rx_tstamp_cycles;
4970
4971         switch (hw->mac.type) {
4972         case e1000_i210:
4973         case e1000_i211:
4974                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4975                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4976                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4977                                 * NSEC_PER_SEC;
4978                 break;
4979         case e1000_82580:
4980         case e1000_i350:
4981         case e1000_i354:
4982                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4983                 /* Only the 8 LSB are valid. */
4984                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4985                                 & 0xff) << 32;
4986                 break;
4987         default:
4988                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4989                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4990                                 << 32;
4991                 break;
4992         }
4993
4994         return rx_tstamp_cycles;
4995 }
4996
4997 static uint64_t
4998 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4999 {
5000         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5001         uint64_t tx_tstamp_cycles;
5002
5003         switch (hw->mac.type) {
5004         case e1000_i210:
5005         case e1000_i211:
5006                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5007                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5008                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5009                                 * NSEC_PER_SEC;
5010                 break;
5011         case e1000_82580:
5012         case e1000_i350:
5013         case e1000_i354:
5014                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5015                 /* Only the 8 LSB are valid. */
5016                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5017                                 & 0xff) << 32;
5018                 break;
5019         default:
5020                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5021                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5022                                 << 32;
5023                 break;
5024         }
5025
5026         return tx_tstamp_cycles;
5027 }
5028
5029 static void
5030 igb_start_timecounters(struct rte_eth_dev *dev)
5031 {
5032         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5033         struct e1000_adapter *adapter =
5034                 (struct e1000_adapter *)dev->data->dev_private;
5035         uint32_t incval = 1;
5036         uint32_t shift = 0;
5037         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5038
5039         switch (hw->mac.type) {
5040         case e1000_82580:
5041         case e1000_i350:
5042         case e1000_i354:
5043                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5044                 mask = (1ULL << 40) - 1;
5045                 /* fall-through */
5046         case e1000_i210:
5047         case e1000_i211:
5048                 /*
5049                  * Start incrementing the register
5050                  * used to timestamp PTP packets.
5051                  */
5052                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5053                 break;
5054         case e1000_82576:
5055                 incval = E1000_INCVALUE_82576;
5056                 shift = IGB_82576_TSYNC_SHIFT;
5057                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5058                                 E1000_INCPERIOD_82576 | incval);
5059                 break;
5060         default:
5061                 /* Not supported */
5062                 return;
5063         }
5064
5065         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5066         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5067         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5068
5069         adapter->systime_tc.cc_mask = mask;
5070         adapter->systime_tc.cc_shift = shift;
5071         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5072
5073         adapter->rx_tstamp_tc.cc_mask = mask;
5074         adapter->rx_tstamp_tc.cc_shift = shift;
5075         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5076
5077         adapter->tx_tstamp_tc.cc_mask = mask;
5078         adapter->tx_tstamp_tc.cc_shift = shift;
5079         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5080 }
5081
5082 static int
5083 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5084 {
5085         struct e1000_adapter *adapter =
5086                         (struct e1000_adapter *)dev->data->dev_private;
5087
5088         adapter->systime_tc.nsec += delta;
5089         adapter->rx_tstamp_tc.nsec += delta;
5090         adapter->tx_tstamp_tc.nsec += delta;
5091
5092         return 0;
5093 }
5094
5095 static int
5096 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5097 {
5098         uint64_t ns;
5099         struct e1000_adapter *adapter =
5100                         (struct e1000_adapter *)dev->data->dev_private;
5101
5102         ns = rte_timespec_to_ns(ts);
5103
5104         /* Set the timecounters to a new value. */
5105         adapter->systime_tc.nsec = ns;
5106         adapter->rx_tstamp_tc.nsec = ns;
5107         adapter->tx_tstamp_tc.nsec = ns;
5108
5109         return 0;
5110 }
5111
5112 static int
5113 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5114 {
5115         uint64_t ns, systime_cycles;
5116         struct e1000_adapter *adapter =
5117                         (struct e1000_adapter *)dev->data->dev_private;
5118
5119         systime_cycles = igb_read_systime_cyclecounter(dev);
5120         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5121         *ts = rte_ns_to_timespec(ns);
5122
5123         return 0;
5124 }
5125
5126 static int
5127 igb_timesync_enable(struct rte_eth_dev *dev)
5128 {
5129         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5130         uint32_t tsync_ctl;
5131         uint32_t tsauxc;
5132
5133         /* Stop the timesync system time. */
5134         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5135         /* Reset the timesync system time value. */
5136         switch (hw->mac.type) {
5137         case e1000_82580:
5138         case e1000_i350:
5139         case e1000_i354:
5140         case e1000_i210:
5141         case e1000_i211:
5142                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5143                 /* fall-through */
5144         case e1000_82576:
5145                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5146                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5147                 break;
5148         default:
5149                 /* Not supported. */
5150                 return -ENOTSUP;
5151         }
5152
5153         /* Enable system time for it isn't on by default. */
5154         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5155         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5156         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5157
5158         igb_start_timecounters(dev);
5159
5160         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5161         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5162                         (ETHER_TYPE_1588 |
5163                          E1000_ETQF_FILTER_ENABLE |
5164                          E1000_ETQF_1588));
5165
5166         /* Enable timestamping of received PTP packets. */
5167         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5168         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5169         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5170
5171         /* Enable Timestamping of transmitted PTP packets. */
5172         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5173         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5174         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5175
5176         return 0;
5177 }
5178
5179 static int
5180 igb_timesync_disable(struct rte_eth_dev *dev)
5181 {
5182         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5183         uint32_t tsync_ctl;
5184
5185         /* Disable timestamping of transmitted PTP packets. */
5186         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5187         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5188         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5189
5190         /* Disable timestamping of received PTP packets. */
5191         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5192         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5193         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5194
5195         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5196         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5197
5198         /* Stop incrementating the System Time registers. */
5199         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5200
5201         return 0;
5202 }
5203
5204 static int
5205 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5206                                struct timespec *timestamp,
5207                                uint32_t flags __rte_unused)
5208 {
5209         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5210         struct e1000_adapter *adapter =
5211                         (struct e1000_adapter *)dev->data->dev_private;
5212         uint32_t tsync_rxctl;
5213         uint64_t rx_tstamp_cycles;
5214         uint64_t ns;
5215
5216         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5217         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5218                 return -EINVAL;
5219
5220         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5221         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5222         *timestamp = rte_ns_to_timespec(ns);
5223
5224         return  0;
5225 }
5226
5227 static int
5228 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5229                                struct timespec *timestamp)
5230 {
5231         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5232         struct e1000_adapter *adapter =
5233                         (struct e1000_adapter *)dev->data->dev_private;
5234         uint32_t tsync_txctl;
5235         uint64_t tx_tstamp_cycles;
5236         uint64_t ns;
5237
5238         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5239         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5240                 return -EINVAL;
5241
5242         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5243         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5244         *timestamp = rte_ns_to_timespec(ns);
5245
5246         return  0;
5247 }
5248
5249 static int
5250 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5251 {
5252         int count = 0;
5253         int g_ind = 0;
5254         const struct reg_info *reg_group;
5255
5256         while ((reg_group = igb_regs[g_ind++]))
5257                 count += igb_reg_group_count(reg_group);
5258
5259         return count;
5260 }
5261
5262 static int
5263 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5264 {
5265         int count = 0;
5266         int g_ind = 0;
5267         const struct reg_info *reg_group;
5268
5269         while ((reg_group = igbvf_regs[g_ind++]))
5270                 count += igb_reg_group_count(reg_group);
5271
5272         return count;
5273 }
5274
5275 static int
5276 eth_igb_get_regs(struct rte_eth_dev *dev,
5277         struct rte_dev_reg_info *regs)
5278 {
5279         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5280         uint32_t *data = regs->data;
5281         int g_ind = 0;
5282         int count = 0;
5283         const struct reg_info *reg_group;
5284
5285         if (data == NULL) {
5286                 regs->length = eth_igb_get_reg_length(dev);
5287                 regs->width = sizeof(uint32_t);
5288                 return 0;
5289         }
5290
5291         /* Support only full register dump */
5292         if ((regs->length == 0) ||
5293             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5294                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5295                         hw->device_id;
5296                 while ((reg_group = igb_regs[g_ind++]))
5297                         count += igb_read_regs_group(dev, &data[count],
5298                                                         reg_group);
5299                 return 0;
5300         }
5301
5302         return -ENOTSUP;
5303 }
5304
5305 static int
5306 igbvf_get_regs(struct rte_eth_dev *dev,
5307         struct rte_dev_reg_info *regs)
5308 {
5309         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5310         uint32_t *data = regs->data;
5311         int g_ind = 0;
5312         int count = 0;
5313         const struct reg_info *reg_group;
5314
5315         if (data == NULL) {
5316                 regs->length = igbvf_get_reg_length(dev);
5317                 regs->width = sizeof(uint32_t);
5318                 return 0;
5319         }
5320
5321         /* Support only full register dump */
5322         if ((regs->length == 0) ||
5323             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5324                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5325                         hw->device_id;
5326                 while ((reg_group = igbvf_regs[g_ind++]))
5327                         count += igb_read_regs_group(dev, &data[count],
5328                                                         reg_group);
5329                 return 0;
5330         }
5331
5332         return -ENOTSUP;
5333 }
5334
5335 static int
5336 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5337 {
5338         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5339
5340         /* Return unit is byte count */
5341         return hw->nvm.word_size * 2;
5342 }
5343
5344 static int
5345 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5346         struct rte_dev_eeprom_info *in_eeprom)
5347 {
5348         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5349         struct e1000_nvm_info *nvm = &hw->nvm;
5350         uint16_t *data = in_eeprom->data;
5351         int first, length;
5352
5353         first = in_eeprom->offset >> 1;
5354         length = in_eeprom->length >> 1;
5355         if ((first >= hw->nvm.word_size) ||
5356             ((first + length) >= hw->nvm.word_size))
5357                 return -EINVAL;
5358
5359         in_eeprom->magic = hw->vendor_id |
5360                 ((uint32_t)hw->device_id << 16);
5361
5362         if ((nvm->ops.read) == NULL)
5363                 return -ENOTSUP;
5364
5365         return nvm->ops.read(hw, first, length, data);
5366 }
5367
5368 static int
5369 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5370         struct rte_dev_eeprom_info *in_eeprom)
5371 {
5372         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5373         struct e1000_nvm_info *nvm = &hw->nvm;
5374         uint16_t *data = in_eeprom->data;
5375         int first, length;
5376
5377         first = in_eeprom->offset >> 1;
5378         length = in_eeprom->length >> 1;
5379         if ((first >= hw->nvm.word_size) ||
5380             ((first + length) >= hw->nvm.word_size))
5381                 return -EINVAL;
5382
5383         in_eeprom->magic = (uint32_t)hw->vendor_id |
5384                 ((uint32_t)hw->device_id << 16);
5385
5386         if ((nvm->ops.write) == NULL)
5387                 return -ENOTSUP;
5388         return nvm->ops.write(hw,  first, length, data);
5389 }
5390
5391 static int
5392 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5393 {
5394         struct e1000_hw *hw =
5395                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5396         uint32_t mask = 1 << queue_id;
5397
5398         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5399         E1000_WRITE_FLUSH(hw);
5400
5401         return 0;
5402 }
5403
5404 static int
5405 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5406 {
5407         struct e1000_hw *hw =
5408                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5409         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5410         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5411         uint32_t mask = 1 << queue_id;
5412         uint32_t regval;
5413
5414         regval = E1000_READ_REG(hw, E1000_EIMS);
5415         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5416         E1000_WRITE_FLUSH(hw);
5417
5418         rte_intr_enable(intr_handle);
5419
5420         return 0;
5421 }
5422
5423 static void
5424 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5425                    uint8_t index, uint8_t offset)
5426 {
5427         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5428
5429         /* clear bits */
5430         val &= ~((uint32_t)0xFF << offset);
5431
5432         /* write vector and valid bit */
5433         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5434
5435         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5436 }
5437
5438 static void
5439 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5440                            uint8_t queue, uint8_t msix_vector)
5441 {
5442         uint32_t tmp = 0;
5443
5444         if (hw->mac.type == e1000_82575) {
5445                 if (direction == 0)
5446                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5447                 else if (direction == 1)
5448                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5449                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5450         } else if (hw->mac.type == e1000_82576) {
5451                 if ((direction == 0) || (direction == 1))
5452                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5453                                            ((queue & 0x8) << 1) +
5454                                            8 * direction);
5455         } else if ((hw->mac.type == e1000_82580) ||
5456                         (hw->mac.type == e1000_i350) ||
5457                         (hw->mac.type == e1000_i354) ||
5458                         (hw->mac.type == e1000_i210) ||
5459                         (hw->mac.type == e1000_i211)) {
5460                 if ((direction == 0) || (direction == 1))
5461                         eth_igb_write_ivar(hw, msix_vector,
5462                                            queue >> 1,
5463                                            ((queue & 0x1) << 4) +
5464                                            8 * direction);
5465         }
5466 }
5467
5468 /* Sets up the hardware to generate MSI-X interrupts properly
5469  * @hw
5470  *  board private structure
5471  */
5472 static void
5473 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5474 {
5475         int queue_id;
5476         uint32_t tmpval, regval, intr_mask;
5477         struct e1000_hw *hw =
5478                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5479         uint32_t vec = E1000_MISC_VEC_ID;
5480         uint32_t base = E1000_MISC_VEC_ID;
5481         uint32_t misc_shift = 0;
5482         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5483         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5484
5485         /* won't configure msix register if no mapping is done
5486          * between intr vector and event fd
5487          */
5488         if (!rte_intr_dp_is_en(intr_handle))
5489                 return;
5490
5491         if (rte_intr_allow_others(intr_handle)) {
5492                 vec = base = E1000_RX_VEC_START;
5493                 misc_shift = 1;
5494         }
5495
5496         /* set interrupt vector for other causes */
5497         if (hw->mac.type == e1000_82575) {
5498                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5499                 /* enable MSI-X PBA support */
5500                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5501
5502                 /* Auto-Mask interrupts upon ICR read */
5503                 tmpval |= E1000_CTRL_EXT_EIAME;
5504                 tmpval |= E1000_CTRL_EXT_IRCA;
5505
5506                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5507
5508                 /* enable msix_other interrupt */
5509                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5510                 regval = E1000_READ_REG(hw, E1000_EIAC);
5511                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5512                 regval = E1000_READ_REG(hw, E1000_EIAM);
5513                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5514         } else if ((hw->mac.type == e1000_82576) ||
5515                         (hw->mac.type == e1000_82580) ||
5516                         (hw->mac.type == e1000_i350) ||
5517                         (hw->mac.type == e1000_i354) ||
5518                         (hw->mac.type == e1000_i210) ||
5519                         (hw->mac.type == e1000_i211)) {
5520                 /* turn on MSI-X capability first */
5521                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5522                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5523                                         E1000_GPIE_NSICR);
5524                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5525                         misc_shift;
5526                 regval = E1000_READ_REG(hw, E1000_EIAC);
5527                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5528
5529                 /* enable msix_other interrupt */
5530                 regval = E1000_READ_REG(hw, E1000_EIMS);
5531                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5532                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5533                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5534         }
5535
5536         /* use EIAM to auto-mask when MSI-X interrupt
5537          * is asserted, this saves a register write for every interrupt
5538          */
5539         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5540                 misc_shift;
5541         regval = E1000_READ_REG(hw, E1000_EIAM);
5542         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5543
5544         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5545                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5546                 intr_handle->intr_vec[queue_id] = vec;
5547                 if (vec < base + intr_handle->nb_efd - 1)
5548                         vec++;
5549         }
5550
5551         E1000_WRITE_FLUSH(hw);
5552 }
5553
5554 /* restore n-tuple filter */
5555 static inline void
5556 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5557 {
5558         struct e1000_filter_info *filter_info =
5559                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5560         struct e1000_5tuple_filter *p_5tuple;
5561         struct e1000_2tuple_filter *p_2tuple;
5562
5563         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5564                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5565         }
5566
5567         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5568                 igb_inject_2uple_filter(dev, p_2tuple);
5569         }
5570 }
5571
5572 /* restore SYN filter */
5573 static inline void
5574 igb_syn_filter_restore(struct rte_eth_dev *dev)
5575 {
5576         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5577         struct e1000_filter_info *filter_info =
5578                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5579         uint32_t synqf;
5580
5581         synqf = filter_info->syn_info;
5582
5583         if (synqf & E1000_SYN_FILTER_ENABLE) {
5584                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5585                 E1000_WRITE_FLUSH(hw);
5586         }
5587 }
5588
5589 /* restore ethernet type filter */
5590 static inline void
5591 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5592 {
5593         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5594         struct e1000_filter_info *filter_info =
5595                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5596         int i;
5597
5598         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5599                 if (filter_info->ethertype_mask & (1 << i)) {
5600                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5601                                 filter_info->ethertype_filters[i].etqf);
5602                         E1000_WRITE_FLUSH(hw);
5603                 }
5604         }
5605 }
5606
5607 /* restore flex byte filter */
5608 static inline void
5609 igb_flex_filter_restore(struct rte_eth_dev *dev)
5610 {
5611         struct e1000_filter_info *filter_info =
5612                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5613         struct e1000_flex_filter *flex_filter;
5614
5615         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5616                 igb_inject_flex_filter(dev, flex_filter);
5617         }
5618 }
5619
5620 /* restore all types filter */
5621 static int
5622 igb_filter_restore(struct rte_eth_dev *dev)
5623 {
5624         igb_ntuple_filter_restore(dev);
5625         igb_ethertype_filter_restore(dev);
5626         igb_syn_filter_restore(dev);
5627         igb_flex_filter_restore(dev);
5628
5629         return 0;
5630 }
5631
5632 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5633 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5634 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5635 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5636 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5637 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");