1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static int eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static int eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
158 static int igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
190 struct rte_eth_ntuple_filter *ntuple_filter);
191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
194 struct rte_eth_ntuple_filter *ntuple_filter);
195 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
196 struct rte_eth_ntuple_filter *ntuple_filter);
197 static int eth_igb_flow_ops_get(struct rte_eth_dev *dev,
198 const struct rte_flow_ops **ops);
199 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
200 static int eth_igb_get_regs(struct rte_eth_dev *dev,
201 struct rte_dev_reg_info *regs);
202 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
203 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
204 struct rte_dev_eeprom_info *eeprom);
205 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
206 struct rte_dev_eeprom_info *eeprom);
207 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
208 struct rte_eth_dev_module_info *modinfo);
209 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
210 struct rte_dev_eeprom_info *info);
211 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
212 struct rte_ether_addr *mc_addr_set,
213 uint32_t nb_mc_addr);
214 static int igb_timesync_enable(struct rte_eth_dev *dev);
215 static int igb_timesync_disable(struct rte_eth_dev *dev);
216 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
217 struct timespec *timestamp,
219 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
220 struct timespec *timestamp);
221 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
222 static int igb_timesync_read_time(struct rte_eth_dev *dev,
223 struct timespec *timestamp);
224 static int igb_timesync_write_time(struct rte_eth_dev *dev,
225 const struct timespec *timestamp);
226 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
228 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
230 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
231 uint8_t queue, uint8_t msix_vector);
232 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
233 uint8_t index, uint8_t offset);
234 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
235 static void eth_igbvf_interrupt_handler(void *param);
236 static void igbvf_mbx_process(struct rte_eth_dev *dev);
237 static int igb_filter_restore(struct rte_eth_dev *dev);
240 * Define VF Stats MACRO for Non "cleared on read" register
242 #define UPDATE_VF_STAT(reg, last, cur) \
244 u32 latest = E1000_READ_REG(hw, reg); \
245 cur += (latest - last) & UINT_MAX; \
249 #define IGB_FC_PAUSE_TIME 0x0680
250 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
251 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
253 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
255 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
258 * The set of PCI devices this driver supports
260 static const struct rte_pci_id pci_id_igb_map[] = {
261 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
262 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
263 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
264 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
265 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
266 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
267 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
268 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
270 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
271 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
272 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
274 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
275 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
276 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
302 { .vendor_id = 0, /* sentinel */ },
306 * The set of PCI devices this driver supports (for 82576&I350 VF)
308 static const struct rte_pci_id pci_id_igbvf_map[] = {
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
313 { .vendor_id = 0, /* sentinel */ },
316 static const struct rte_eth_desc_lim rx_desc_lim = {
317 .nb_max = E1000_MAX_RING_DESC,
318 .nb_min = E1000_MIN_RING_DESC,
319 .nb_align = IGB_RXD_ALIGN,
322 static const struct rte_eth_desc_lim tx_desc_lim = {
323 .nb_max = E1000_MAX_RING_DESC,
324 .nb_min = E1000_MIN_RING_DESC,
325 .nb_align = IGB_RXD_ALIGN,
326 .nb_seg_max = IGB_TX_MAX_SEG,
327 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
330 static const struct eth_dev_ops eth_igb_ops = {
331 .dev_configure = eth_igb_configure,
332 .dev_start = eth_igb_start,
333 .dev_stop = eth_igb_stop,
334 .dev_set_link_up = eth_igb_dev_set_link_up,
335 .dev_set_link_down = eth_igb_dev_set_link_down,
336 .dev_close = eth_igb_close,
337 .dev_reset = eth_igb_reset,
338 .promiscuous_enable = eth_igb_promiscuous_enable,
339 .promiscuous_disable = eth_igb_promiscuous_disable,
340 .allmulticast_enable = eth_igb_allmulticast_enable,
341 .allmulticast_disable = eth_igb_allmulticast_disable,
342 .link_update = eth_igb_link_update,
343 .stats_get = eth_igb_stats_get,
344 .xstats_get = eth_igb_xstats_get,
345 .xstats_get_by_id = eth_igb_xstats_get_by_id,
346 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
347 .xstats_get_names = eth_igb_xstats_get_names,
348 .stats_reset = eth_igb_stats_reset,
349 .xstats_reset = eth_igb_xstats_reset,
350 .fw_version_get = eth_igb_fw_version_get,
351 .dev_infos_get = eth_igb_infos_get,
352 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
353 .mtu_set = eth_igb_mtu_set,
354 .vlan_filter_set = eth_igb_vlan_filter_set,
355 .vlan_tpid_set = eth_igb_vlan_tpid_set,
356 .vlan_offload_set = eth_igb_vlan_offload_set,
357 .rx_queue_setup = eth_igb_rx_queue_setup,
358 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
359 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
360 .rx_queue_release = eth_igb_rx_queue_release,
361 .tx_queue_setup = eth_igb_tx_queue_setup,
362 .tx_queue_release = eth_igb_tx_queue_release,
363 .tx_done_cleanup = eth_igb_tx_done_cleanup,
364 .dev_led_on = eth_igb_led_on,
365 .dev_led_off = eth_igb_led_off,
366 .flow_ctrl_get = eth_igb_flow_ctrl_get,
367 .flow_ctrl_set = eth_igb_flow_ctrl_set,
368 .mac_addr_add = eth_igb_rar_set,
369 .mac_addr_remove = eth_igb_rar_clear,
370 .mac_addr_set = eth_igb_default_mac_addr_set,
371 .reta_update = eth_igb_rss_reta_update,
372 .reta_query = eth_igb_rss_reta_query,
373 .rss_hash_update = eth_igb_rss_hash_update,
374 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
375 .flow_ops_get = eth_igb_flow_ops_get,
376 .set_mc_addr_list = eth_igb_set_mc_addr_list,
377 .rxq_info_get = igb_rxq_info_get,
378 .txq_info_get = igb_txq_info_get,
379 .timesync_enable = igb_timesync_enable,
380 .timesync_disable = igb_timesync_disable,
381 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
382 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
383 .get_reg = eth_igb_get_regs,
384 .get_eeprom_length = eth_igb_get_eeprom_length,
385 .get_eeprom = eth_igb_get_eeprom,
386 .set_eeprom = eth_igb_set_eeprom,
387 .get_module_info = eth_igb_get_module_info,
388 .get_module_eeprom = eth_igb_get_module_eeprom,
389 .timesync_adjust_time = igb_timesync_adjust_time,
390 .timesync_read_time = igb_timesync_read_time,
391 .timesync_write_time = igb_timesync_write_time,
395 * dev_ops for virtual function, bare necessities for basic vf
396 * operation have been implemented
398 static const struct eth_dev_ops igbvf_eth_dev_ops = {
399 .dev_configure = igbvf_dev_configure,
400 .dev_start = igbvf_dev_start,
401 .dev_stop = igbvf_dev_stop,
402 .dev_close = igbvf_dev_close,
403 .promiscuous_enable = igbvf_promiscuous_enable,
404 .promiscuous_disable = igbvf_promiscuous_disable,
405 .allmulticast_enable = igbvf_allmulticast_enable,
406 .allmulticast_disable = igbvf_allmulticast_disable,
407 .link_update = eth_igb_link_update,
408 .stats_get = eth_igbvf_stats_get,
409 .xstats_get = eth_igbvf_xstats_get,
410 .xstats_get_names = eth_igbvf_xstats_get_names,
411 .stats_reset = eth_igbvf_stats_reset,
412 .xstats_reset = eth_igbvf_stats_reset,
413 .vlan_filter_set = igbvf_vlan_filter_set,
414 .dev_infos_get = eth_igbvf_infos_get,
415 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
416 .rx_queue_setup = eth_igb_rx_queue_setup,
417 .rx_queue_release = eth_igb_rx_queue_release,
418 .tx_queue_setup = eth_igb_tx_queue_setup,
419 .tx_queue_release = eth_igb_tx_queue_release,
420 .tx_done_cleanup = eth_igb_tx_done_cleanup,
421 .set_mc_addr_list = eth_igb_set_mc_addr_list,
422 .rxq_info_get = igb_rxq_info_get,
423 .txq_info_get = igb_txq_info_get,
424 .mac_addr_set = igbvf_default_mac_addr_set,
425 .get_reg = igbvf_get_regs,
428 /* store statistics names and its offset in stats structure */
429 struct rte_igb_xstats_name_off {
430 char name[RTE_ETH_XSTATS_NAME_SIZE];
434 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
435 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
436 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
437 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
438 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
439 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
440 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
441 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
443 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
444 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
445 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
446 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
447 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
448 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
449 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
450 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
451 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
452 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
453 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
455 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
456 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
457 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
458 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
459 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
461 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
463 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
464 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
465 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
466 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
467 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
468 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
469 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
470 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
471 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
472 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
473 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
474 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
475 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
476 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
477 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
478 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
479 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
480 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
482 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
484 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
485 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
486 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
487 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
488 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
489 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
490 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
492 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
495 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
496 sizeof(rte_igb_stats_strings[0]))
498 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
499 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
500 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
501 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
502 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
503 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
506 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
507 sizeof(rte_igbvf_stats_strings[0]))
511 igb_intr_enable(struct rte_eth_dev *dev)
513 struct e1000_interrupt *intr =
514 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
515 struct e1000_hw *hw =
516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
517 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
518 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
520 if (rte_intr_allow_others(intr_handle) &&
521 dev->data->dev_conf.intr_conf.lsc != 0) {
522 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
525 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
526 E1000_WRITE_FLUSH(hw);
530 igb_intr_disable(struct rte_eth_dev *dev)
532 struct e1000_hw *hw =
533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
535 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
537 if (rte_intr_allow_others(intr_handle) &&
538 dev->data->dev_conf.intr_conf.lsc != 0) {
539 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
542 E1000_WRITE_REG(hw, E1000_IMC, ~0);
543 E1000_WRITE_FLUSH(hw);
547 igbvf_intr_enable(struct rte_eth_dev *dev)
549 struct e1000_hw *hw =
550 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 /* only for mailbox */
553 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
554 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
555 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
556 E1000_WRITE_FLUSH(hw);
559 /* only for mailbox now. If RX/TX needed, should extend this function. */
561 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
566 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
567 tmp |= E1000_VTIVAR_VALID;
568 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
572 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
574 struct e1000_hw *hw =
575 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
577 /* Configure VF other cause ivar */
578 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
581 static inline int32_t
582 igb_pf_reset_hw(struct e1000_hw *hw)
587 status = e1000_reset_hw(hw);
589 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
590 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
591 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
592 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
593 E1000_WRITE_FLUSH(hw);
599 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
601 struct e1000_hw *hw =
602 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 hw->vendor_id = pci_dev->id.vendor_id;
606 hw->device_id = pci_dev->id.device_id;
607 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
608 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
610 e1000_set_mac_type(hw);
612 /* need to check if it is a vf device below */
616 igb_reset_swfw_lock(struct e1000_hw *hw)
621 * Do mac ops initialization manually here, since we will need
622 * some function pointers set by this call.
624 ret_val = e1000_init_mac_params(hw);
629 * SMBI lock should not fail in this early stage. If this is the case,
630 * it is due to an improper exit of the application.
631 * So force the release of the faulty lock.
633 if (e1000_get_hw_semaphore_generic(hw) < 0) {
634 PMD_DRV_LOG(DEBUG, "SMBI lock released");
636 e1000_put_hw_semaphore_generic(hw);
638 if (hw->mac.ops.acquire_swfw_sync != NULL) {
642 * Phy lock should not fail in this early stage. If this is the case,
643 * it is due to an improper exit of the application.
644 * So force the release of the faulty lock.
646 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
647 if (hw->bus.func > E1000_FUNC_1)
649 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
650 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
653 hw->mac.ops.release_swfw_sync(hw, mask);
656 * This one is more tricky since it is common to all ports; but
657 * swfw_sync retries last long enough (1s) to be almost sure that if
658 * lock can not be taken it is due to an improper lock of the
661 mask = E1000_SWFW_EEP_SM;
662 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
663 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
665 hw->mac.ops.release_swfw_sync(hw, mask);
668 return E1000_SUCCESS;
671 /* Remove all ntuple filters of the device */
672 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
674 struct e1000_filter_info *filter_info =
675 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
676 struct e1000_5tuple_filter *p_5tuple;
677 struct e1000_2tuple_filter *p_2tuple;
679 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
680 TAILQ_REMOVE(&filter_info->fivetuple_list,
684 filter_info->fivetuple_mask = 0;
685 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
686 TAILQ_REMOVE(&filter_info->twotuple_list,
690 filter_info->twotuple_mask = 0;
695 /* Remove all flex filters of the device */
696 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
698 struct e1000_filter_info *filter_info =
699 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
700 struct e1000_flex_filter *p_flex;
702 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
703 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
706 filter_info->flex_mask = 0;
712 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
716 struct e1000_hw *hw =
717 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
718 struct e1000_vfta * shadow_vfta =
719 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
720 struct e1000_filter_info *filter_info =
721 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
722 struct e1000_adapter *adapter =
723 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
727 eth_dev->dev_ops = ð_igb_ops;
728 eth_dev->rx_queue_count = eth_igb_rx_queue_count;
729 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
730 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
731 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
732 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
733 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
734 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
736 /* for secondary processes, we don't initialise any further as primary
737 * has already done this work. Only check we don't need a different
739 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
740 if (eth_dev->data->scattered_rx)
741 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
745 rte_eth_copy_pci_info(eth_dev, pci_dev);
746 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
748 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
750 igb_identify_hardware(eth_dev, pci_dev);
751 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
756 e1000_get_bus_info(hw);
758 /* Reset any pending lock */
759 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
764 /* Finish initialization */
765 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
771 hw->phy.autoneg_wait_to_complete = 0;
772 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
775 if (hw->phy.media_type == e1000_media_type_copper) {
776 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
777 hw->phy.disable_polarity_correction = 0;
778 hw->phy.ms_type = e1000_ms_hw_default;
782 * Start from a known state, this is important in reading the nvm
787 /* Make sure we have a good EEPROM before we read from it */
788 if (e1000_validate_nvm_checksum(hw) < 0) {
790 * Some PCI-E parts fail the first check due to
791 * the link being in sleep state, call it again,
792 * if it fails a second time its a real issue.
794 if (e1000_validate_nvm_checksum(hw) < 0) {
795 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
801 /* Read the permanent MAC address out of the EEPROM */
802 if (e1000_read_mac_addr(hw) != 0) {
803 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
808 /* Allocate memory for storing MAC addresses */
809 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
810 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
811 if (eth_dev->data->mac_addrs == NULL) {
812 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
813 "store MAC addresses",
814 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
819 /* Copy the permanent MAC address */
820 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
821 ð_dev->data->mac_addrs[0]);
823 /* initialize the vfta */
824 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
826 /* Now initialize the hardware */
827 if (igb_hardware_init(hw) != 0) {
828 PMD_INIT_LOG(ERR, "Hardware initialization failed");
829 rte_free(eth_dev->data->mac_addrs);
830 eth_dev->data->mac_addrs = NULL;
834 hw->mac.get_link_status = 1;
835 adapter->stopped = 0;
837 /* Indicate SOL/IDER usage */
838 if (e1000_check_reset_block(hw) < 0) {
839 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
843 /* initialize PF if max_vfs not zero */
844 igb_pf_host_init(eth_dev);
846 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
847 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
848 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
849 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
850 E1000_WRITE_FLUSH(hw);
852 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
853 eth_dev->data->port_id, pci_dev->id.vendor_id,
854 pci_dev->id.device_id);
856 rte_intr_callback_register(&pci_dev->intr_handle,
857 eth_igb_interrupt_handler,
860 /* enable uio/vfio intr/eventfd mapping */
861 rte_intr_enable(&pci_dev->intr_handle);
863 /* enable support intr */
864 igb_intr_enable(eth_dev);
866 eth_igb_dev_set_link_down(eth_dev);
868 /* initialize filter info */
869 memset(filter_info, 0,
870 sizeof(struct e1000_filter_info));
872 TAILQ_INIT(&filter_info->flex_list);
873 TAILQ_INIT(&filter_info->twotuple_list);
874 TAILQ_INIT(&filter_info->fivetuple_list);
876 TAILQ_INIT(&igb_filter_ntuple_list);
877 TAILQ_INIT(&igb_filter_ethertype_list);
878 TAILQ_INIT(&igb_filter_syn_list);
879 TAILQ_INIT(&igb_filter_flex_list);
880 TAILQ_INIT(&igb_filter_rss_list);
881 TAILQ_INIT(&igb_flow_list);
886 igb_hw_control_release(hw);
892 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
894 PMD_INIT_FUNC_TRACE();
896 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
899 eth_igb_close(eth_dev);
905 * Virtual Function device init
908 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
910 struct rte_pci_device *pci_dev;
911 struct rte_intr_handle *intr_handle;
912 struct e1000_adapter *adapter =
913 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
914 struct e1000_hw *hw =
915 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
917 struct rte_ether_addr *perm_addr =
918 (struct rte_ether_addr *)hw->mac.perm_addr;
920 PMD_INIT_FUNC_TRACE();
922 eth_dev->dev_ops = &igbvf_eth_dev_ops;
923 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
924 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
925 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
926 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
927 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
928 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
930 /* for secondary processes, we don't initialise any further as primary
931 * has already done this work. Only check we don't need a different
933 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
934 if (eth_dev->data->scattered_rx)
935 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
939 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
940 rte_eth_copy_pci_info(eth_dev, pci_dev);
941 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
943 hw->device_id = pci_dev->id.device_id;
944 hw->vendor_id = pci_dev->id.vendor_id;
945 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
946 adapter->stopped = 0;
948 /* Initialize the shared code (base driver) */
949 diag = e1000_setup_init_funcs(hw, TRUE);
951 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
956 /* init_mailbox_params */
957 hw->mbx.ops.init_params(hw);
959 /* Disable the interrupts for VF */
960 igbvf_intr_disable(hw);
962 diag = hw->mac.ops.reset_hw(hw);
964 /* Allocate memory for storing MAC addresses */
965 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
966 hw->mac.rar_entry_count, 0);
967 if (eth_dev->data->mac_addrs == NULL) {
969 "Failed to allocate %d bytes needed to store MAC "
971 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
975 /* Generate a random MAC address, if none was assigned by PF. */
976 if (rte_is_zero_ether_addr(perm_addr)) {
977 rte_eth_random_addr(perm_addr->addr_bytes);
978 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
979 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
980 "%02x:%02x:%02x:%02x:%02x:%02x",
981 perm_addr->addr_bytes[0],
982 perm_addr->addr_bytes[1],
983 perm_addr->addr_bytes[2],
984 perm_addr->addr_bytes[3],
985 perm_addr->addr_bytes[4],
986 perm_addr->addr_bytes[5]);
989 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
991 rte_free(eth_dev->data->mac_addrs);
992 eth_dev->data->mac_addrs = NULL;
995 /* Copy the permanent MAC address */
996 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
997 ð_dev->data->mac_addrs[0]);
999 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1001 eth_dev->data->port_id, pci_dev->id.vendor_id,
1002 pci_dev->id.device_id, "igb_mac_82576_vf");
1004 intr_handle = &pci_dev->intr_handle;
1005 rte_intr_callback_register(intr_handle,
1006 eth_igbvf_interrupt_handler, eth_dev);
1012 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1014 PMD_INIT_FUNC_TRACE();
1016 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1019 igbvf_dev_close(eth_dev);
1024 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1025 struct rte_pci_device *pci_dev)
1027 return rte_eth_dev_pci_generic_probe(pci_dev,
1028 sizeof(struct e1000_adapter), eth_igb_dev_init);
1031 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1033 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1036 static struct rte_pci_driver rte_igb_pmd = {
1037 .id_table = pci_id_igb_map,
1038 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1039 .probe = eth_igb_pci_probe,
1040 .remove = eth_igb_pci_remove,
1044 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1045 struct rte_pci_device *pci_dev)
1047 return rte_eth_dev_pci_generic_probe(pci_dev,
1048 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1051 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1053 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1057 * virtual function driver struct
1059 static struct rte_pci_driver rte_igbvf_pmd = {
1060 .id_table = pci_id_igbvf_map,
1061 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1062 .probe = eth_igbvf_pci_probe,
1063 .remove = eth_igbvf_pci_remove,
1067 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1069 struct e1000_hw *hw =
1070 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1071 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1072 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1073 rctl |= E1000_RCTL_VFE;
1074 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1078 igb_check_mq_mode(struct rte_eth_dev *dev)
1080 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1081 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1082 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1083 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1085 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1086 tx_mq_mode == ETH_MQ_TX_DCB ||
1087 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1088 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1091 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1092 /* Check multi-queue mode.
1093 * To no break software we accept ETH_MQ_RX_NONE as this might
1094 * be used to turn off VLAN filter.
1097 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1098 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1099 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1100 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1102 /* Only support one queue on VFs.
1103 * RSS together with SRIOV is not supported.
1105 PMD_INIT_LOG(ERR, "SRIOV is active,"
1106 " wrong mq_mode rx %d.",
1110 /* TX mode is not used here, so mode might be ignored.*/
1111 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1112 /* SRIOV only works in VMDq enable mode */
1113 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1114 " TX mode %d is not supported. "
1115 " Driver will behave as %d mode.",
1116 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1119 /* check valid queue number */
1120 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1121 PMD_INIT_LOG(ERR, "SRIOV is active,"
1122 " only support one queue on VFs.");
1126 /* To no break software that set invalid mode, only display
1127 * warning if invalid mode is used.
1129 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1130 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1131 rx_mq_mode != ETH_MQ_RX_RSS) {
1132 /* RSS together with VMDq not supported*/
1133 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1138 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1139 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1140 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1141 " Due to txmode is meaningless in this"
1142 " driver, just ignore.",
1150 eth_igb_configure(struct rte_eth_dev *dev)
1152 struct e1000_interrupt *intr =
1153 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1156 PMD_INIT_FUNC_TRACE();
1158 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1159 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1161 /* multipe queue mode checking */
1162 ret = igb_check_mq_mode(dev);
1164 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1169 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1170 PMD_INIT_FUNC_TRACE();
1176 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1179 struct e1000_hw *hw =
1180 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181 uint32_t tctl, rctl;
1183 tctl = E1000_READ_REG(hw, E1000_TCTL);
1184 rctl = E1000_READ_REG(hw, E1000_RCTL);
1188 tctl |= E1000_TCTL_EN;
1189 rctl |= E1000_RCTL_EN;
1192 tctl &= ~E1000_TCTL_EN;
1193 rctl &= ~E1000_RCTL_EN;
1195 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1196 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1197 E1000_WRITE_FLUSH(hw);
1201 eth_igb_start(struct rte_eth_dev *dev)
1203 struct e1000_hw *hw =
1204 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205 struct e1000_adapter *adapter =
1206 E1000_DEV_PRIVATE(dev->data->dev_private);
1207 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1208 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1210 uint32_t intr_vector = 0;
1216 PMD_INIT_FUNC_TRACE();
1218 /* disable uio/vfio intr/eventfd mapping */
1219 rte_intr_disable(intr_handle);
1221 /* Power up the phy. Needed to make the link go Up */
1222 eth_igb_dev_set_link_up(dev);
1225 * Packet Buffer Allocation (PBA)
1226 * Writing PBA sets the receive portion of the buffer
1227 * the remainder is used for the transmit buffer.
1229 if (hw->mac.type == e1000_82575) {
1232 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1233 E1000_WRITE_REG(hw, E1000_PBA, pba);
1236 /* Put the address into the Receive Address Array */
1237 e1000_rar_set(hw, hw->mac.addr, 0);
1239 /* Initialize the hardware */
1240 if (igb_hardware_init(hw)) {
1241 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1244 adapter->stopped = 0;
1246 E1000_WRITE_REG(hw, E1000_VET,
1247 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1249 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1250 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1251 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1252 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1253 E1000_WRITE_FLUSH(hw);
1255 /* configure PF module if SRIOV enabled */
1256 igb_pf_host_configure(dev);
1258 /* check and configure queue intr-vector mapping */
1259 if ((rte_intr_cap_multiple(intr_handle) ||
1260 !RTE_ETH_DEV_SRIOV(dev).active) &&
1261 dev->data->dev_conf.intr_conf.rxq != 0) {
1262 intr_vector = dev->data->nb_rx_queues;
1263 if (rte_intr_efd_enable(intr_handle, intr_vector))
1267 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1268 intr_handle->intr_vec =
1269 rte_zmalloc("intr_vec",
1270 dev->data->nb_rx_queues * sizeof(int), 0);
1271 if (intr_handle->intr_vec == NULL) {
1272 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1273 " intr_vec", dev->data->nb_rx_queues);
1278 /* confiugre msix for rx interrupt */
1279 eth_igb_configure_msix_intr(dev);
1281 /* Configure for OS presence */
1282 igb_init_manageability(hw);
1284 eth_igb_tx_init(dev);
1286 /* This can fail when allocating mbufs for descriptor rings */
1287 ret = eth_igb_rx_init(dev);
1289 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1290 igb_dev_clear_queues(dev);
1294 e1000_clear_hw_cntrs_base_generic(hw);
1297 * VLAN Offload Settings
1299 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1300 ETH_VLAN_EXTEND_MASK;
1301 ret = eth_igb_vlan_offload_set(dev, mask);
1303 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1304 igb_dev_clear_queues(dev);
1308 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1309 /* Enable VLAN filter since VMDq always use VLAN filter */
1310 igb_vmdq_vlan_hw_filter_enable(dev);
1313 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1314 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1315 (hw->mac.type == e1000_i211)) {
1316 /* Configure EITR with the maximum possible value (0xFFFF) */
1317 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1320 /* Setup link speed and duplex */
1321 speeds = &dev->data->dev_conf.link_speeds;
1322 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1323 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1324 hw->mac.autoneg = 1;
1327 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1330 hw->phy.autoneg_advertised = 0;
1332 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1333 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1334 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1336 goto error_invalid_config;
1338 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1339 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1342 if (*speeds & ETH_LINK_SPEED_10M) {
1343 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1346 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1347 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1350 if (*speeds & ETH_LINK_SPEED_100M) {
1351 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1354 if (*speeds & ETH_LINK_SPEED_1G) {
1355 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1358 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1359 goto error_invalid_config;
1361 /* Set/reset the mac.autoneg based on the link speed,
1365 hw->mac.autoneg = 0;
1366 hw->mac.forced_speed_duplex =
1367 hw->phy.autoneg_advertised;
1369 hw->mac.autoneg = 1;
1373 e1000_setup_link(hw);
1375 if (rte_intr_allow_others(intr_handle)) {
1376 /* check if lsc interrupt is enabled */
1377 if (dev->data->dev_conf.intr_conf.lsc != 0)
1378 eth_igb_lsc_interrupt_setup(dev, TRUE);
1380 eth_igb_lsc_interrupt_setup(dev, FALSE);
1382 rte_intr_callback_unregister(intr_handle,
1383 eth_igb_interrupt_handler,
1385 if (dev->data->dev_conf.intr_conf.lsc != 0)
1386 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1387 " no intr multiplex");
1390 /* check if rxq interrupt is enabled */
1391 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1392 rte_intr_dp_is_en(intr_handle))
1393 eth_igb_rxq_interrupt_setup(dev);
1395 /* enable uio/vfio intr/eventfd mapping */
1396 rte_intr_enable(intr_handle);
1398 /* resume enabled intr since hw reset */
1399 igb_intr_enable(dev);
1401 /* restore all types filter */
1402 igb_filter_restore(dev);
1404 eth_igb_rxtx_control(dev, true);
1405 eth_igb_link_update(dev, 0);
1407 PMD_INIT_LOG(DEBUG, "<<");
1411 error_invalid_config:
1412 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1413 dev->data->dev_conf.link_speeds, dev->data->port_id);
1414 igb_dev_clear_queues(dev);
1418 /*********************************************************************
1420 * This routine disables all traffic on the adapter by issuing a
1421 * global reset on the MAC.
1423 **********************************************************************/
1425 eth_igb_stop(struct rte_eth_dev *dev)
1427 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1429 struct rte_eth_link link;
1430 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1431 struct e1000_adapter *adapter =
1432 E1000_DEV_PRIVATE(dev->data->dev_private);
1434 if (adapter->stopped)
1437 eth_igb_rxtx_control(dev, false);
1439 igb_intr_disable(dev);
1441 /* disable intr eventfd mapping */
1442 rte_intr_disable(intr_handle);
1444 igb_pf_reset_hw(hw);
1445 E1000_WRITE_REG(hw, E1000_WUC, 0);
1447 /* Set bit for Go Link disconnect if PHY reset is not blocked */
1448 if (hw->mac.type >= e1000_82580 &&
1449 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1452 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1453 phpm_reg |= E1000_82580_PM_GO_LINKD;
1454 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1457 /* Power down the phy. Needed to make the link go Down */
1458 eth_igb_dev_set_link_down(dev);
1460 igb_dev_clear_queues(dev);
1462 /* clear the recorded link status */
1463 memset(&link, 0, sizeof(link));
1464 rte_eth_linkstatus_set(dev, &link);
1466 if (!rte_intr_allow_others(intr_handle))
1467 /* resume to the default handler */
1468 rte_intr_callback_register(intr_handle,
1469 eth_igb_interrupt_handler,
1472 /* Clean datapath event and queue/vec mapping */
1473 rte_intr_efd_disable(intr_handle);
1474 if (intr_handle->intr_vec != NULL) {
1475 rte_free(intr_handle->intr_vec);
1476 intr_handle->intr_vec = NULL;
1479 adapter->stopped = true;
1480 dev->data->dev_started = 0;
1486 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1488 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490 if (hw->phy.media_type == e1000_media_type_copper)
1491 e1000_power_up_phy(hw);
1493 e1000_power_up_fiber_serdes_link(hw);
1499 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1501 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503 if (hw->phy.media_type == e1000_media_type_copper)
1504 e1000_power_down_phy(hw);
1506 e1000_shutdown_fiber_serdes_link(hw);
1512 eth_igb_close(struct rte_eth_dev *dev)
1514 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515 struct rte_eth_link link;
1516 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1517 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1518 struct e1000_filter_info *filter_info =
1519 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1522 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1525 ret = eth_igb_stop(dev);
1527 e1000_phy_hw_reset(hw);
1528 igb_release_manageability(hw);
1529 igb_hw_control_release(hw);
1531 /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1532 if (hw->mac.type >= e1000_82580 &&
1533 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1536 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1537 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1538 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1541 igb_dev_free_queues(dev);
1543 if (intr_handle->intr_vec) {
1544 rte_free(intr_handle->intr_vec);
1545 intr_handle->intr_vec = NULL;
1548 memset(&link, 0, sizeof(link));
1549 rte_eth_linkstatus_set(dev, &link);
1551 /* Reset any pending lock */
1552 igb_reset_swfw_lock(hw);
1554 /* uninitialize PF if max_vfs not zero */
1555 igb_pf_host_uninit(dev);
1557 rte_intr_callback_unregister(intr_handle,
1558 eth_igb_interrupt_handler, dev);
1560 /* clear the SYN filter info */
1561 filter_info->syn_info = 0;
1563 /* clear the ethertype filters info */
1564 filter_info->ethertype_mask = 0;
1565 memset(filter_info->ethertype_filters, 0,
1566 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1568 /* clear the rss filter info */
1569 memset(&filter_info->rss_info, 0,
1570 sizeof(struct igb_rte_flow_rss_conf));
1572 /* remove all ntuple filters of the device */
1573 igb_ntuple_filter_uninit(dev);
1575 /* remove all flex filters of the device */
1576 igb_flex_filter_uninit(dev);
1578 /* clear all the filters list */
1579 igb_filterlist_flush(dev);
1588 eth_igb_reset(struct rte_eth_dev *dev)
1592 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1593 * its VF to make them align with it. The detailed notification
1594 * mechanism is PMD specific and is currently not implemented.
1595 * To avoid unexpected behavior in VF, currently reset of PF with
1596 * SR-IOV activation is not supported. It might be supported later.
1598 if (dev->data->sriov.active)
1601 ret = eth_igb_dev_uninit(dev);
1605 ret = eth_igb_dev_init(dev);
1612 igb_get_rx_buffer_size(struct e1000_hw *hw)
1614 uint32_t rx_buf_size;
1615 if (hw->mac.type == e1000_82576) {
1616 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1617 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1618 /* PBS needs to be translated according to a lookup table */
1619 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1620 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1621 rx_buf_size = (rx_buf_size << 10);
1622 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1623 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1625 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1631 /*********************************************************************
1633 * Initialize the hardware
1635 **********************************************************************/
1637 igb_hardware_init(struct e1000_hw *hw)
1639 uint32_t rx_buf_size;
1642 /* Let the firmware know the OS is in control */
1643 igb_hw_control_acquire(hw);
1646 * These parameters control the automatic generation (Tx) and
1647 * response (Rx) to Ethernet PAUSE frames.
1648 * - High water mark should allow for at least two standard size (1518)
1649 * frames to be received after sending an XOFF.
1650 * - Low water mark works best when it is very near the high water mark.
1651 * This allows the receiver to restart by sending XON when it has
1652 * drained a bit. Here we use an arbitrary value of 1500 which will
1653 * restart after one full frame is pulled from the buffer. There
1654 * could be several smaller frames in the buffer and if so they will
1655 * not trigger the XON until their total number reduces the buffer
1657 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1659 rx_buf_size = igb_get_rx_buffer_size(hw);
1661 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1662 hw->fc.low_water = hw->fc.high_water - 1500;
1663 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1664 hw->fc.send_xon = 1;
1666 /* Set Flow control, use the tunable location if sane */
1667 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1668 hw->fc.requested_mode = igb_fc_setting;
1670 hw->fc.requested_mode = e1000_fc_none;
1672 /* Issue a global reset */
1673 igb_pf_reset_hw(hw);
1674 E1000_WRITE_REG(hw, E1000_WUC, 0);
1676 diag = e1000_init_hw(hw);
1680 E1000_WRITE_REG(hw, E1000_VET,
1681 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1682 e1000_get_phy_info(hw);
1683 e1000_check_for_link(hw);
1688 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1690 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1694 uint64_t old_gprc = stats->gprc;
1695 uint64_t old_gptc = stats->gptc;
1696 uint64_t old_tpr = stats->tpr;
1697 uint64_t old_tpt = stats->tpt;
1698 uint64_t old_rpthc = stats->rpthc;
1699 uint64_t old_hgptc = stats->hgptc;
1701 if(hw->phy.media_type == e1000_media_type_copper ||
1702 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1704 E1000_READ_REG(hw,E1000_SYMERRS);
1705 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1708 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1709 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1710 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1711 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1713 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1714 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1715 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1716 stats->dc += E1000_READ_REG(hw, E1000_DC);
1717 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1718 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1719 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1721 ** For watchdog management we need to know if we have been
1722 ** paused during the last interval, so capture that here.
1724 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1725 stats->xoffrxc += pause_frames;
1726 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1727 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1728 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1729 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1730 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1731 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1732 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1733 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1734 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1735 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1736 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1737 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1739 /* For the 64-bit byte counters the low dword must be read first. */
1740 /* Both registers clear on the read of the high dword */
1742 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1743 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1744 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1745 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1746 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1747 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1748 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1750 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1751 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1752 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1753 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1754 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1756 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1757 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1759 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1760 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1761 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1762 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1763 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1764 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1766 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1767 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1768 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1769 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1770 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1771 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1772 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1773 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1775 /* Interrupt Counts */
1777 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1778 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1779 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1780 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1781 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1782 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1783 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1784 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1785 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1787 /* Host to Card Statistics */
1789 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1790 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1791 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1792 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1793 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1794 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1795 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1796 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1797 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1798 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1799 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1800 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1801 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1802 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1803 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1804 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1806 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1807 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1808 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1809 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1810 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1811 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1815 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1817 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818 struct e1000_hw_stats *stats =
1819 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1821 igb_read_stats_registers(hw, stats);
1823 if (rte_stats == NULL)
1827 rte_stats->imissed = stats->mpc;
1828 rte_stats->ierrors = stats->crcerrs + stats->rlec +
1829 stats->rxerrc + stats->algnerrc + stats->cexterr;
1832 rte_stats->oerrors = stats->ecol + stats->latecol;
1834 rte_stats->ipackets = stats->gprc;
1835 rte_stats->opackets = stats->gptc;
1836 rte_stats->ibytes = stats->gorc;
1837 rte_stats->obytes = stats->gotc;
1842 eth_igb_stats_reset(struct rte_eth_dev *dev)
1844 struct e1000_hw_stats *hw_stats =
1845 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1847 /* HW registers are cleared on read */
1848 eth_igb_stats_get(dev, NULL);
1850 /* Reset software totals */
1851 memset(hw_stats, 0, sizeof(*hw_stats));
1857 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1859 struct e1000_hw_stats *stats =
1860 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1862 /* HW registers are cleared on read */
1863 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1865 /* Reset software totals */
1866 memset(stats, 0, sizeof(*stats));
1871 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1872 struct rte_eth_xstat_name *xstats_names,
1873 __rte_unused unsigned int size)
1877 if (xstats_names == NULL)
1878 return IGB_NB_XSTATS;
1880 /* Note: limit checked in rte_eth_xstats_names() */
1882 for (i = 0; i < IGB_NB_XSTATS; i++) {
1883 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1884 sizeof(xstats_names[i].name));
1887 return IGB_NB_XSTATS;
1890 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1891 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1897 if (xstats_names == NULL)
1898 return IGB_NB_XSTATS;
1900 for (i = 0; i < IGB_NB_XSTATS; i++)
1901 strlcpy(xstats_names[i].name,
1902 rte_igb_stats_strings[i].name,
1903 sizeof(xstats_names[i].name));
1905 return IGB_NB_XSTATS;
1908 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1910 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1913 for (i = 0; i < limit; i++) {
1914 if (ids[i] >= IGB_NB_XSTATS) {
1915 PMD_INIT_LOG(ERR, "id value isn't valid");
1918 strcpy(xstats_names[i].name,
1919 xstats_names_copy[ids[i]].name);
1926 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1929 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930 struct e1000_hw_stats *hw_stats =
1931 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1934 if (n < IGB_NB_XSTATS)
1935 return IGB_NB_XSTATS;
1937 igb_read_stats_registers(hw, hw_stats);
1939 /* If this is a reset xstats is NULL, and we have cleared the
1940 * registers by reading them.
1945 /* Extended stats */
1946 for (i = 0; i < IGB_NB_XSTATS; i++) {
1948 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1949 rte_igb_stats_strings[i].offset);
1952 return IGB_NB_XSTATS;
1956 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1957 uint64_t *values, unsigned int n)
1962 struct e1000_hw *hw =
1963 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964 struct e1000_hw_stats *hw_stats =
1965 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1967 if (n < IGB_NB_XSTATS)
1968 return IGB_NB_XSTATS;
1970 igb_read_stats_registers(hw, hw_stats);
1972 /* If this is a reset xstats is NULL, and we have cleared the
1973 * registers by reading them.
1978 /* Extended stats */
1979 for (i = 0; i < IGB_NB_XSTATS; i++)
1980 values[i] = *(uint64_t *)(((char *)hw_stats) +
1981 rte_igb_stats_strings[i].offset);
1983 return IGB_NB_XSTATS;
1986 uint64_t values_copy[IGB_NB_XSTATS];
1988 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1991 for (i = 0; i < n; i++) {
1992 if (ids[i] >= IGB_NB_XSTATS) {
1993 PMD_INIT_LOG(ERR, "id value isn't valid");
1996 values[i] = values_copy[ids[i]];
2003 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2005 /* Good Rx packets, include VF loopback */
2006 UPDATE_VF_STAT(E1000_VFGPRC,
2007 hw_stats->last_gprc, hw_stats->gprc);
2009 /* Good Rx octets, include VF loopback */
2010 UPDATE_VF_STAT(E1000_VFGORC,
2011 hw_stats->last_gorc, hw_stats->gorc);
2013 /* Good Tx packets, include VF loopback */
2014 UPDATE_VF_STAT(E1000_VFGPTC,
2015 hw_stats->last_gptc, hw_stats->gptc);
2017 /* Good Tx octets, include VF loopback */
2018 UPDATE_VF_STAT(E1000_VFGOTC,
2019 hw_stats->last_gotc, hw_stats->gotc);
2021 /* Rx Multicst packets */
2022 UPDATE_VF_STAT(E1000_VFMPRC,
2023 hw_stats->last_mprc, hw_stats->mprc);
2025 /* Good Rx loopback packets */
2026 UPDATE_VF_STAT(E1000_VFGPRLBC,
2027 hw_stats->last_gprlbc, hw_stats->gprlbc);
2029 /* Good Rx loopback octets */
2030 UPDATE_VF_STAT(E1000_VFGORLBC,
2031 hw_stats->last_gorlbc, hw_stats->gorlbc);
2033 /* Good Tx loopback packets */
2034 UPDATE_VF_STAT(E1000_VFGPTLBC,
2035 hw_stats->last_gptlbc, hw_stats->gptlbc);
2037 /* Good Tx loopback octets */
2038 UPDATE_VF_STAT(E1000_VFGOTLBC,
2039 hw_stats->last_gotlbc, hw_stats->gotlbc);
2042 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2043 struct rte_eth_xstat_name *xstats_names,
2044 __rte_unused unsigned limit)
2048 if (xstats_names != NULL)
2049 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2050 strlcpy(xstats_names[i].name,
2051 rte_igbvf_stats_strings[i].name,
2052 sizeof(xstats_names[i].name));
2054 return IGBVF_NB_XSTATS;
2058 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2061 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2063 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2066 if (n < IGBVF_NB_XSTATS)
2067 return IGBVF_NB_XSTATS;
2069 igbvf_read_stats_registers(hw, hw_stats);
2074 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2076 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2077 rte_igbvf_stats_strings[i].offset);
2080 return IGBVF_NB_XSTATS;
2084 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2086 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2088 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2090 igbvf_read_stats_registers(hw, hw_stats);
2092 if (rte_stats == NULL)
2095 rte_stats->ipackets = hw_stats->gprc;
2096 rte_stats->ibytes = hw_stats->gorc;
2097 rte_stats->opackets = hw_stats->gptc;
2098 rte_stats->obytes = hw_stats->gotc;
2103 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2105 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2106 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2108 /* Sync HW register to the last stats */
2109 eth_igbvf_stats_get(dev, NULL);
2111 /* reset HW current stats*/
2112 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2113 offsetof(struct e1000_vf_stats, gprc));
2119 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2122 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123 struct e1000_fw_version fw;
2126 e1000_get_fw_version(hw, &fw);
2128 switch (hw->mac.type) {
2131 if (!(e1000_get_flash_presence_i210(hw))) {
2132 ret = snprintf(fw_version, fw_size,
2134 fw.invm_major, fw.invm_minor,
2140 /* if option rom is valid, display its version too */
2142 ret = snprintf(fw_version, fw_size,
2143 "%d.%d, 0x%08x, %d.%d.%d",
2144 fw.eep_major, fw.eep_minor, fw.etrack_id,
2145 fw.or_major, fw.or_build, fw.or_patch);
2148 if (fw.etrack_id != 0X0000) {
2149 ret = snprintf(fw_version, fw_size,
2151 fw.eep_major, fw.eep_minor,
2154 ret = snprintf(fw_version, fw_size,
2156 fw.eep_major, fw.eep_minor,
2165 ret += 1; /* add the size of '\0' */
2166 if (fw_size < (size_t)ret)
2173 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2175 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2178 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2179 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2180 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2181 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2182 dev_info->rx_queue_offload_capa;
2183 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2184 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2185 dev_info->tx_queue_offload_capa;
2187 switch (hw->mac.type) {
2189 dev_info->max_rx_queues = 4;
2190 dev_info->max_tx_queues = 4;
2191 dev_info->max_vmdq_pools = 0;
2195 dev_info->max_rx_queues = 16;
2196 dev_info->max_tx_queues = 16;
2197 dev_info->max_vmdq_pools = ETH_8_POOLS;
2198 dev_info->vmdq_queue_num = 16;
2202 dev_info->max_rx_queues = 8;
2203 dev_info->max_tx_queues = 8;
2204 dev_info->max_vmdq_pools = ETH_8_POOLS;
2205 dev_info->vmdq_queue_num = 8;
2209 dev_info->max_rx_queues = 8;
2210 dev_info->max_tx_queues = 8;
2211 dev_info->max_vmdq_pools = ETH_8_POOLS;
2212 dev_info->vmdq_queue_num = 8;
2216 dev_info->max_rx_queues = 8;
2217 dev_info->max_tx_queues = 8;
2221 dev_info->max_rx_queues = 4;
2222 dev_info->max_tx_queues = 4;
2223 dev_info->max_vmdq_pools = 0;
2227 dev_info->max_rx_queues = 2;
2228 dev_info->max_tx_queues = 2;
2229 dev_info->max_vmdq_pools = 0;
2233 /* Should not happen */
2236 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2237 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2238 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2240 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2242 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2243 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2244 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2246 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2251 dev_info->default_txconf = (struct rte_eth_txconf) {
2253 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2254 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2255 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2260 dev_info->rx_desc_lim = rx_desc_lim;
2261 dev_info->tx_desc_lim = tx_desc_lim;
2263 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2264 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2267 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2268 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2273 static const uint32_t *
2274 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2276 static const uint32_t ptypes[] = {
2277 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2280 RTE_PTYPE_L3_IPV4_EXT,
2282 RTE_PTYPE_L3_IPV6_EXT,
2286 RTE_PTYPE_TUNNEL_IP,
2287 RTE_PTYPE_INNER_L3_IPV6,
2288 RTE_PTYPE_INNER_L3_IPV6_EXT,
2289 RTE_PTYPE_INNER_L4_TCP,
2290 RTE_PTYPE_INNER_L4_UDP,
2294 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2295 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2301 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2303 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2305 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2306 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2307 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2308 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2309 DEV_TX_OFFLOAD_IPV4_CKSUM |
2310 DEV_TX_OFFLOAD_UDP_CKSUM |
2311 DEV_TX_OFFLOAD_TCP_CKSUM |
2312 DEV_TX_OFFLOAD_SCTP_CKSUM |
2313 DEV_TX_OFFLOAD_TCP_TSO;
2314 switch (hw->mac.type) {
2316 dev_info->max_rx_queues = 2;
2317 dev_info->max_tx_queues = 2;
2319 case e1000_vfadapt_i350:
2320 dev_info->max_rx_queues = 1;
2321 dev_info->max_tx_queues = 1;
2324 /* Should not happen */
2328 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2329 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2330 dev_info->rx_queue_offload_capa;
2331 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2332 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2333 dev_info->tx_queue_offload_capa;
2335 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2337 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2338 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2339 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2341 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2346 dev_info->default_txconf = (struct rte_eth_txconf) {
2348 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2349 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2350 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2355 dev_info->rx_desc_lim = rx_desc_lim;
2356 dev_info->tx_desc_lim = tx_desc_lim;
2361 /* return 0 means link status changed, -1 means not changed */
2363 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2365 struct e1000_hw *hw =
2366 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2367 struct rte_eth_link link;
2368 int link_check, count;
2371 hw->mac.get_link_status = 1;
2373 /* possible wait-to-complete in up to 9 seconds */
2374 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2375 /* Read the real link status */
2376 switch (hw->phy.media_type) {
2377 case e1000_media_type_copper:
2378 /* Do the work to read phy */
2379 e1000_check_for_link(hw);
2380 link_check = !hw->mac.get_link_status;
2383 case e1000_media_type_fiber:
2384 e1000_check_for_link(hw);
2385 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2389 case e1000_media_type_internal_serdes:
2390 e1000_check_for_link(hw);
2391 link_check = hw->mac.serdes_has_link;
2394 /* VF device is type_unknown */
2395 case e1000_media_type_unknown:
2396 eth_igbvf_link_update(hw);
2397 link_check = !hw->mac.get_link_status;
2403 if (link_check || wait_to_complete == 0)
2405 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2407 memset(&link, 0, sizeof(link));
2409 /* Now we check if a transition has happened */
2411 uint16_t duplex, speed;
2412 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2413 link.link_duplex = (duplex == FULL_DUPLEX) ?
2414 ETH_LINK_FULL_DUPLEX :
2415 ETH_LINK_HALF_DUPLEX;
2416 link.link_speed = speed;
2417 link.link_status = ETH_LINK_UP;
2418 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2419 ETH_LINK_SPEED_FIXED);
2420 } else if (!link_check) {
2421 link.link_speed = 0;
2422 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2423 link.link_status = ETH_LINK_DOWN;
2424 link.link_autoneg = ETH_LINK_FIXED;
2427 return rte_eth_linkstatus_set(dev, &link);
2431 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2432 * For ASF and Pass Through versions of f/w this means
2433 * that the driver is loaded.
2436 igb_hw_control_acquire(struct e1000_hw *hw)
2440 /* Let firmware know the driver has taken over */
2441 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2442 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2446 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2447 * For ASF and Pass Through versions of f/w this means that the
2448 * driver is no longer loaded.
2451 igb_hw_control_release(struct e1000_hw *hw)
2455 /* Let firmware taken over control of h/w */
2456 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2457 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2458 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2462 * Bit of a misnomer, what this really means is
2463 * to enable OS management of the system... aka
2464 * to disable special hardware management features.
2467 igb_init_manageability(struct e1000_hw *hw)
2469 if (e1000_enable_mng_pass_thru(hw)) {
2470 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2471 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2473 /* disable hardware interception of ARP */
2474 manc &= ~(E1000_MANC_ARP_EN);
2476 /* enable receiving management packets to the host */
2477 manc |= E1000_MANC_EN_MNG2HOST;
2478 manc2h |= 1 << 5; /* Mng Port 623 */
2479 manc2h |= 1 << 6; /* Mng Port 664 */
2480 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2481 E1000_WRITE_REG(hw, E1000_MANC, manc);
2486 igb_release_manageability(struct e1000_hw *hw)
2488 if (e1000_enable_mng_pass_thru(hw)) {
2489 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2491 manc |= E1000_MANC_ARP_EN;
2492 manc &= ~E1000_MANC_EN_MNG2HOST;
2494 E1000_WRITE_REG(hw, E1000_MANC, manc);
2499 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2501 struct e1000_hw *hw =
2502 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2505 rctl = E1000_READ_REG(hw, E1000_RCTL);
2506 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2507 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2513 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2515 struct e1000_hw *hw =
2516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519 rctl = E1000_READ_REG(hw, E1000_RCTL);
2520 rctl &= (~E1000_RCTL_UPE);
2521 if (dev->data->all_multicast == 1)
2522 rctl |= E1000_RCTL_MPE;
2524 rctl &= (~E1000_RCTL_MPE);
2525 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2531 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2533 struct e1000_hw *hw =
2534 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537 rctl = E1000_READ_REG(hw, E1000_RCTL);
2538 rctl |= E1000_RCTL_MPE;
2539 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2545 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2547 struct e1000_hw *hw =
2548 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2551 if (dev->data->promiscuous == 1)
2552 return 0; /* must remain in all_multicast mode */
2553 rctl = E1000_READ_REG(hw, E1000_RCTL);
2554 rctl &= (~E1000_RCTL_MPE);
2555 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2561 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2563 struct e1000_hw *hw =
2564 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565 struct e1000_vfta * shadow_vfta =
2566 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2571 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2572 E1000_VFTA_ENTRY_MASK);
2573 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2574 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2579 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2581 /* update local VFTA copy */
2582 shadow_vfta->vfta[vid_idx] = vfta;
2588 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2589 enum rte_vlan_type vlan_type,
2592 struct e1000_hw *hw =
2593 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2596 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2597 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2599 /* only outer TPID of double VLAN can be configured*/
2600 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2601 reg = E1000_READ_REG(hw, E1000_VET);
2602 reg = (reg & (~E1000_VET_VET_EXT)) |
2603 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2604 E1000_WRITE_REG(hw, E1000_VET, reg);
2609 /* all other TPID values are read-only*/
2610 PMD_DRV_LOG(ERR, "Not supported");
2616 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2618 struct e1000_hw *hw =
2619 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2622 /* Filter Table Disable */
2623 reg = E1000_READ_REG(hw, E1000_RCTL);
2624 reg &= ~E1000_RCTL_CFIEN;
2625 reg &= ~E1000_RCTL_VFE;
2626 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2630 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2632 struct e1000_hw *hw =
2633 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2634 struct e1000_vfta * shadow_vfta =
2635 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2639 /* Filter Table Enable, CFI not used for packet acceptance */
2640 reg = E1000_READ_REG(hw, E1000_RCTL);
2641 reg &= ~E1000_RCTL_CFIEN;
2642 reg |= E1000_RCTL_VFE;
2643 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2645 /* restore VFTA table */
2646 for (i = 0; i < IGB_VFTA_SIZE; i++)
2647 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2651 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2653 struct e1000_hw *hw =
2654 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657 /* VLAN Mode Disable */
2658 reg = E1000_READ_REG(hw, E1000_CTRL);
2659 reg &= ~E1000_CTRL_VME;
2660 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2664 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2666 struct e1000_hw *hw =
2667 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2670 /* VLAN Mode Enable */
2671 reg = E1000_READ_REG(hw, E1000_CTRL);
2672 reg |= E1000_CTRL_VME;
2673 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2677 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2679 struct e1000_hw *hw =
2680 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2683 /* CTRL_EXT: Extended VLAN */
2684 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2685 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2686 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2688 /* Update maximum packet length */
2689 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2690 E1000_WRITE_REG(hw, E1000_RLPML,
2691 dev->data->dev_conf.rxmode.max_rx_pkt_len);
2695 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2697 struct e1000_hw *hw =
2698 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2701 /* CTRL_EXT: Extended VLAN */
2702 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2703 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2704 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2706 /* Update maximum packet length */
2707 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2708 E1000_WRITE_REG(hw, E1000_RLPML,
2709 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2714 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2716 struct rte_eth_rxmode *rxmode;
2718 rxmode = &dev->data->dev_conf.rxmode;
2719 if(mask & ETH_VLAN_STRIP_MASK){
2720 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2721 igb_vlan_hw_strip_enable(dev);
2723 igb_vlan_hw_strip_disable(dev);
2726 if(mask & ETH_VLAN_FILTER_MASK){
2727 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2728 igb_vlan_hw_filter_enable(dev);
2730 igb_vlan_hw_filter_disable(dev);
2733 if(mask & ETH_VLAN_EXTEND_MASK){
2734 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2735 igb_vlan_hw_extend_enable(dev);
2737 igb_vlan_hw_extend_disable(dev);
2745 * It enables the interrupt mask and then enable the interrupt.
2748 * Pointer to struct rte_eth_dev.
2753 * - On success, zero.
2754 * - On failure, a negative value.
2757 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2759 struct e1000_interrupt *intr =
2760 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2763 intr->mask |= E1000_ICR_LSC;
2765 intr->mask &= ~E1000_ICR_LSC;
2770 /* It clears the interrupt causes and enables the interrupt.
2771 * It will be called once only during nic initialized.
2774 * Pointer to struct rte_eth_dev.
2777 * - On success, zero.
2778 * - On failure, a negative value.
2780 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2782 uint32_t mask, regval;
2784 struct e1000_hw *hw =
2785 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2787 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2788 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2789 struct rte_eth_dev_info dev_info;
2791 memset(&dev_info, 0, sizeof(dev_info));
2792 ret = eth_igb_infos_get(dev, &dev_info);
2796 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2797 regval = E1000_READ_REG(hw, E1000_EIMS);
2798 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2804 * It reads ICR and gets interrupt causes, check it and set a bit flag
2805 * to update link status.
2808 * Pointer to struct rte_eth_dev.
2811 * - On success, zero.
2812 * - On failure, a negative value.
2815 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2818 struct e1000_hw *hw =
2819 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820 struct e1000_interrupt *intr =
2821 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2823 igb_intr_disable(dev);
2825 /* read-on-clear nic registers here */
2826 icr = E1000_READ_REG(hw, E1000_ICR);
2829 if (icr & E1000_ICR_LSC) {
2830 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2833 if (icr & E1000_ICR_VMMB)
2834 intr->flags |= E1000_FLAG_MAILBOX;
2840 * It executes link_update after knowing an interrupt is prsent.
2843 * Pointer to struct rte_eth_dev.
2846 * - On success, zero.
2847 * - On failure, a negative value.
2850 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2851 struct rte_intr_handle *intr_handle)
2853 struct e1000_hw *hw =
2854 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855 struct e1000_interrupt *intr =
2856 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2857 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2858 struct rte_eth_link link;
2861 if (intr->flags & E1000_FLAG_MAILBOX) {
2862 igb_pf_mbx_process(dev);
2863 intr->flags &= ~E1000_FLAG_MAILBOX;
2866 igb_intr_enable(dev);
2867 rte_intr_ack(intr_handle);
2869 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2870 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2872 /* set get_link_status to check register later */
2873 hw->mac.get_link_status = 1;
2874 ret = eth_igb_link_update(dev, 0);
2876 /* check if link has changed */
2880 rte_eth_linkstatus_get(dev, &link);
2881 if (link.link_status) {
2883 " Port %d: Link Up - speed %u Mbps - %s",
2885 (unsigned)link.link_speed,
2886 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2887 "full-duplex" : "half-duplex");
2889 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2890 dev->data->port_id);
2893 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2894 pci_dev->addr.domain,
2896 pci_dev->addr.devid,
2897 pci_dev->addr.function);
2898 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2905 * Interrupt handler which shall be registered at first.
2908 * Pointer to interrupt handle.
2910 * The address of parameter (struct rte_eth_dev *) regsitered before.
2916 eth_igb_interrupt_handler(void *param)
2918 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2920 eth_igb_interrupt_get_status(dev);
2921 eth_igb_interrupt_action(dev, dev->intr_handle);
2925 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2928 struct e1000_hw *hw =
2929 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2930 struct e1000_interrupt *intr =
2931 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2933 igbvf_intr_disable(hw);
2935 /* read-on-clear nic registers here */
2936 eicr = E1000_READ_REG(hw, E1000_EICR);
2939 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2940 intr->flags |= E1000_FLAG_MAILBOX;
2945 void igbvf_mbx_process(struct rte_eth_dev *dev)
2947 struct e1000_hw *hw =
2948 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949 struct e1000_mbx_info *mbx = &hw->mbx;
2952 /* peek the message first */
2953 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2955 /* PF reset VF event */
2956 if (in_msg == E1000_PF_CONTROL_MSG) {
2957 /* dummy mbx read to ack pf */
2958 if (mbx->ops.read(hw, &in_msg, 1, 0))
2960 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2966 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2968 struct e1000_interrupt *intr =
2969 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2971 if (intr->flags & E1000_FLAG_MAILBOX) {
2972 igbvf_mbx_process(dev);
2973 intr->flags &= ~E1000_FLAG_MAILBOX;
2976 igbvf_intr_enable(dev);
2977 rte_intr_ack(intr_handle);
2983 eth_igbvf_interrupt_handler(void *param)
2985 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2987 eth_igbvf_interrupt_get_status(dev);
2988 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2992 eth_igb_led_on(struct rte_eth_dev *dev)
2994 struct e1000_hw *hw;
2996 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2997 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3001 eth_igb_led_off(struct rte_eth_dev *dev)
3003 struct e1000_hw *hw;
3005 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3006 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3010 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3012 struct e1000_hw *hw;
3017 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018 fc_conf->pause_time = hw->fc.pause_time;
3019 fc_conf->high_water = hw->fc.high_water;
3020 fc_conf->low_water = hw->fc.low_water;
3021 fc_conf->send_xon = hw->fc.send_xon;
3022 fc_conf->autoneg = hw->mac.autoneg;
3025 * Return rx_pause and tx_pause status according to actual setting of
3026 * the TFCE and RFCE bits in the CTRL register.
3028 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3029 if (ctrl & E1000_CTRL_TFCE)
3034 if (ctrl & E1000_CTRL_RFCE)
3039 if (rx_pause && tx_pause)
3040 fc_conf->mode = RTE_FC_FULL;
3042 fc_conf->mode = RTE_FC_RX_PAUSE;
3044 fc_conf->mode = RTE_FC_TX_PAUSE;
3046 fc_conf->mode = RTE_FC_NONE;
3052 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3054 struct e1000_hw *hw;
3056 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3062 uint32_t rx_buf_size;
3063 uint32_t max_high_water;
3067 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068 if (fc_conf->autoneg != hw->mac.autoneg)
3070 rx_buf_size = igb_get_rx_buffer_size(hw);
3071 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3073 /* At least reserve one Ethernet frame for watermark */
3074 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3075 if ((fc_conf->high_water > max_high_water) ||
3076 (fc_conf->high_water < fc_conf->low_water)) {
3077 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3078 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3082 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3083 hw->fc.pause_time = fc_conf->pause_time;
3084 hw->fc.high_water = fc_conf->high_water;
3085 hw->fc.low_water = fc_conf->low_water;
3086 hw->fc.send_xon = fc_conf->send_xon;
3088 err = e1000_setup_link_generic(hw);
3089 if (err == E1000_SUCCESS) {
3091 /* check if we want to forward MAC frames - driver doesn't have native
3092 * capability to do that, so we'll write the registers ourselves */
3094 rctl = E1000_READ_REG(hw, E1000_RCTL);
3096 /* set or clear MFLCN.PMCF bit depending on configuration */
3097 if (fc_conf->mac_ctrl_frame_fwd != 0)
3098 rctl |= E1000_RCTL_PMCF;
3100 rctl &= ~E1000_RCTL_PMCF;
3102 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3105 * check if we want to change flow control mode - driver doesn't have native
3106 * capability to do that, so we'll write the registers ourselves
3108 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3111 * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits depending
3114 switch (fc_conf->mode) {
3116 ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE;
3118 case RTE_FC_RX_PAUSE:
3119 ctrl |= E1000_CTRL_RFCE;
3120 ctrl &= ~E1000_CTRL_TFCE;
3122 case RTE_FC_TX_PAUSE:
3123 ctrl |= E1000_CTRL_TFCE;
3124 ctrl &= ~E1000_CTRL_RFCE;
3127 ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE;
3130 PMD_INIT_LOG(ERR, "invalid flow control mode");
3134 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3136 E1000_WRITE_FLUSH(hw);
3141 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3145 #define E1000_RAH_POOLSEL_SHIFT (18)
3147 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3148 uint32_t index, uint32_t pool)
3150 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3154 rah = E1000_READ_REG(hw, E1000_RAH(index));
3155 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3156 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3161 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3163 uint8_t addr[RTE_ETHER_ADDR_LEN];
3164 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3166 memset(addr, 0, sizeof(addr));
3168 e1000_rar_set(hw, addr, index);
3172 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3173 struct rte_ether_addr *addr)
3175 eth_igb_rar_clear(dev, 0);
3176 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3181 * Virtual Function operations
3184 igbvf_intr_disable(struct e1000_hw *hw)
3186 PMD_INIT_FUNC_TRACE();
3188 /* Clear interrupt mask to stop from interrupts being generated */
3189 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3191 E1000_WRITE_FLUSH(hw);
3195 igbvf_stop_adapter(struct rte_eth_dev *dev)
3199 struct rte_eth_dev_info dev_info;
3200 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3203 memset(&dev_info, 0, sizeof(dev_info));
3204 ret = eth_igbvf_infos_get(dev, &dev_info);
3208 /* Clear interrupt mask to stop from interrupts being generated */
3209 igbvf_intr_disable(hw);
3211 /* Clear any pending interrupts, flush previous writes */
3212 E1000_READ_REG(hw, E1000_EICR);
3214 /* Disable the transmit unit. Each queue must be disabled. */
3215 for (i = 0; i < dev_info.max_tx_queues; i++)
3216 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3218 /* Disable the receive unit by stopping each queue */
3219 for (i = 0; i < dev_info.max_rx_queues; i++) {
3220 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3221 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3222 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3223 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3227 /* flush all queues disables */
3228 E1000_WRITE_FLUSH(hw);
3232 static int eth_igbvf_link_update(struct e1000_hw *hw)
3234 struct e1000_mbx_info *mbx = &hw->mbx;
3235 struct e1000_mac_info *mac = &hw->mac;
3236 int ret_val = E1000_SUCCESS;
3238 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3241 * We only want to run this if there has been a rst asserted.
3242 * in this case that could mean a link change, device reset,
3243 * or a virtual function reset
3246 /* If we were hit with a reset or timeout drop the link */
3247 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3248 mac->get_link_status = TRUE;
3250 if (!mac->get_link_status)
3253 /* if link status is down no point in checking to see if pf is up */
3254 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3257 /* if we passed all the tests above then the link is up and we no
3258 * longer need to check for link */
3259 mac->get_link_status = FALSE;
3267 igbvf_dev_configure(struct rte_eth_dev *dev)
3269 struct rte_eth_conf* conf = &dev->data->dev_conf;
3271 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3272 dev->data->port_id);
3274 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3275 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3278 * VF has no ability to enable/disable HW CRC
3279 * Keep the persistent behavior the same as Host PF
3281 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3282 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3283 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3284 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3287 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3288 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3289 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3297 igbvf_dev_start(struct rte_eth_dev *dev)
3299 struct e1000_hw *hw =
3300 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3301 struct e1000_adapter *adapter =
3302 E1000_DEV_PRIVATE(dev->data->dev_private);
3303 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3304 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3306 uint32_t intr_vector = 0;
3308 PMD_INIT_FUNC_TRACE();
3310 hw->mac.ops.reset_hw(hw);
3311 adapter->stopped = 0;
3314 igbvf_set_vfta_all(dev,1);
3316 eth_igbvf_tx_init(dev);
3318 /* This can fail when allocating mbufs for descriptor rings */
3319 ret = eth_igbvf_rx_init(dev);
3321 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3322 igb_dev_clear_queues(dev);
3326 /* check and configure queue intr-vector mapping */
3327 if (rte_intr_cap_multiple(intr_handle) &&
3328 dev->data->dev_conf.intr_conf.rxq) {
3329 intr_vector = dev->data->nb_rx_queues;
3330 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3335 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3336 intr_handle->intr_vec =
3337 rte_zmalloc("intr_vec",
3338 dev->data->nb_rx_queues * sizeof(int), 0);
3339 if (!intr_handle->intr_vec) {
3340 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3341 " intr_vec", dev->data->nb_rx_queues);
3346 eth_igbvf_configure_msix_intr(dev);
3348 /* enable uio/vfio intr/eventfd mapping */
3349 rte_intr_enable(intr_handle);
3351 /* resume enabled intr since hw reset */
3352 igbvf_intr_enable(dev);
3358 igbvf_dev_stop(struct rte_eth_dev *dev)
3360 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3361 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3362 struct e1000_adapter *adapter =
3363 E1000_DEV_PRIVATE(dev->data->dev_private);
3365 if (adapter->stopped)
3368 PMD_INIT_FUNC_TRACE();
3370 igbvf_stop_adapter(dev);
3373 * Clear what we set, but we still keep shadow_vfta to
3374 * restore after device starts
3376 igbvf_set_vfta_all(dev,0);
3378 igb_dev_clear_queues(dev);
3380 /* disable intr eventfd mapping */
3381 rte_intr_disable(intr_handle);
3383 /* Clean datapath event and queue/vec mapping */
3384 rte_intr_efd_disable(intr_handle);
3385 if (intr_handle->intr_vec) {
3386 rte_free(intr_handle->intr_vec);
3387 intr_handle->intr_vec = NULL;
3390 adapter->stopped = true;
3391 dev->data->dev_started = 0;
3397 igbvf_dev_close(struct rte_eth_dev *dev)
3399 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3400 struct rte_ether_addr addr;
3401 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3404 PMD_INIT_FUNC_TRACE();
3406 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3411 ret = igbvf_dev_stop(dev);
3415 igb_dev_free_queues(dev);
3418 * reprogram the RAR with a zero mac address,
3419 * to ensure that the VF traffic goes to the PF
3420 * after stop, close and detach of the VF.
3423 memset(&addr, 0, sizeof(addr));
3424 igbvf_default_mac_addr_set(dev, &addr);
3426 rte_intr_callback_unregister(&pci_dev->intr_handle,
3427 eth_igbvf_interrupt_handler,
3434 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3436 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438 /* Set both unicast and multicast promisc */
3439 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3445 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3447 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3449 /* If in allmulticast mode leave multicast promisc */
3450 if (dev->data->all_multicast == 1)
3451 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3453 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3459 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3461 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3463 /* In promiscuous mode multicast promisc already set */
3464 if (dev->data->promiscuous == 0)
3465 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3471 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3473 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3475 /* In promiscuous mode leave multicast promisc enabled */
3476 if (dev->data->promiscuous == 0)
3477 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3482 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3484 struct e1000_mbx_info *mbx = &hw->mbx;
3488 /* After set vlan, vlan strip will also be enabled in igb driver*/
3489 msgbuf[0] = E1000_VF_SET_VLAN;
3491 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3493 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3495 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3499 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3503 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3504 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3511 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3513 struct e1000_hw *hw =
3514 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515 struct e1000_vfta * shadow_vfta =
3516 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3517 int i = 0, j = 0, vfta = 0, mask = 1;
3519 for (i = 0; i < IGB_VFTA_SIZE; i++){
3520 vfta = shadow_vfta->vfta[i];
3523 for (j = 0; j < 32; j++){
3526 (uint16_t)((i<<5)+j), on);
3535 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3537 struct e1000_hw *hw =
3538 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539 struct e1000_vfta * shadow_vfta =
3540 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3541 uint32_t vid_idx = 0;
3542 uint32_t vid_bit = 0;
3545 PMD_INIT_FUNC_TRACE();
3547 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3548 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3550 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3553 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3554 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3556 /*Save what we set and retore it after device reset*/
3558 shadow_vfta->vfta[vid_idx] |= vid_bit;
3560 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3566 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3568 struct e1000_hw *hw =
3569 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3571 /* index is not used by rar_set() */
3572 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3578 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3579 struct rte_eth_rss_reta_entry64 *reta_conf,
3584 uint16_t idx, shift;
3585 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3588 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3589 "(%d) doesn't match the number hardware can supported "
3590 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3594 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3595 idx = i / RTE_RETA_GROUP_SIZE;
3596 shift = i % RTE_RETA_GROUP_SIZE;
3597 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3601 if (mask == IGB_4_BIT_MASK)
3604 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3605 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3606 if (mask & (0x1 << j))
3607 reta |= reta_conf[idx].reta[shift + j] <<
3610 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3612 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3619 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3620 struct rte_eth_rss_reta_entry64 *reta_conf,
3625 uint16_t idx, shift;
3626 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3628 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3629 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3630 "(%d) doesn't match the number hardware can supported "
3631 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3635 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3636 idx = i / RTE_RETA_GROUP_SIZE;
3637 shift = i % RTE_RETA_GROUP_SIZE;
3638 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3642 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3643 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3644 if (mask & (0x1 << j))
3645 reta_conf[idx].reta[shift + j] =
3646 ((reta >> (CHAR_BIT * j)) &
3655 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3656 struct rte_eth_syn_filter *filter,
3659 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3660 struct e1000_filter_info *filter_info =
3661 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3662 uint32_t synqf, rfctl;
3664 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3667 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3670 if (synqf & E1000_SYN_FILTER_ENABLE)
3673 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3674 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3676 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3677 if (filter->hig_pri)
3678 rfctl |= E1000_RFCTL_SYNQFP;
3680 rfctl &= ~E1000_RFCTL_SYNQFP;
3682 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3684 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3689 filter_info->syn_info = synqf;
3690 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3691 E1000_WRITE_FLUSH(hw);
3695 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3697 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3698 struct e1000_2tuple_filter_info *filter_info)
3700 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3702 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3703 return -EINVAL; /* filter index is out of range. */
3704 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3705 return -EINVAL; /* flags is invalid. */
3707 switch (filter->dst_port_mask) {
3709 filter_info->dst_port_mask = 0;
3710 filter_info->dst_port = filter->dst_port;
3713 filter_info->dst_port_mask = 1;
3716 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3720 switch (filter->proto_mask) {
3722 filter_info->proto_mask = 0;
3723 filter_info->proto = filter->proto;
3726 filter_info->proto_mask = 1;
3729 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3733 filter_info->priority = (uint8_t)filter->priority;
3734 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3735 filter_info->tcp_flags = filter->tcp_flags;
3737 filter_info->tcp_flags = 0;
3742 static inline struct e1000_2tuple_filter *
3743 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3744 struct e1000_2tuple_filter_info *key)
3746 struct e1000_2tuple_filter *it;
3748 TAILQ_FOREACH(it, filter_list, entries) {
3749 if (memcmp(key, &it->filter_info,
3750 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3757 /* inject a igb 2tuple filter to HW */
3759 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3760 struct e1000_2tuple_filter *filter)
3762 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3763 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3764 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3768 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3769 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3770 imir |= E1000_IMIR_PORT_BP;
3772 imir &= ~E1000_IMIR_PORT_BP;
3774 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3776 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3777 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3778 ttqf |= (uint32_t)(filter->filter_info.proto &
3779 E1000_TTQF_PROTOCOL_MASK);
3780 if (filter->filter_info.proto_mask == 0)
3781 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3783 /* tcp flags bits setting. */
3784 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3785 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3786 imir_ext |= E1000_IMIREXT_CTRL_URG;
3787 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3788 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3789 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3790 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3791 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3792 imir_ext |= E1000_IMIREXT_CTRL_RST;
3793 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3794 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3795 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3796 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3798 imir_ext |= E1000_IMIREXT_CTRL_BP;
3800 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3801 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3802 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3806 * igb_add_2tuple_filter - add a 2tuple filter
3809 * dev: Pointer to struct rte_eth_dev.
3810 * ntuple_filter: ponter to the filter that will be added.
3813 * - On success, zero.
3814 * - On failure, a negative value.
3817 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3818 struct rte_eth_ntuple_filter *ntuple_filter)
3820 struct e1000_filter_info *filter_info =
3821 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3822 struct e1000_2tuple_filter *filter;
3825 filter = rte_zmalloc("e1000_2tuple_filter",
3826 sizeof(struct e1000_2tuple_filter), 0);
3830 ret = ntuple_filter_to_2tuple(ntuple_filter,
3831 &filter->filter_info);
3836 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3837 &filter->filter_info) != NULL) {
3838 PMD_DRV_LOG(ERR, "filter exists.");
3842 filter->queue = ntuple_filter->queue;
3845 * look for an unused 2tuple filter index,
3846 * and insert the filter to list.
3848 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3849 if (!(filter_info->twotuple_mask & (1 << i))) {
3850 filter_info->twotuple_mask |= 1 << i;
3852 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3858 if (i >= E1000_MAX_TTQF_FILTERS) {
3859 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3864 igb_inject_2uple_filter(dev, filter);
3869 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3870 struct e1000_2tuple_filter *filter)
3872 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873 struct e1000_filter_info *filter_info =
3874 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3876 filter_info->twotuple_mask &= ~(1 << filter->index);
3877 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3880 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3881 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3882 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3887 * igb_remove_2tuple_filter - remove a 2tuple filter
3890 * dev: Pointer to struct rte_eth_dev.
3891 * ntuple_filter: ponter to the filter that will be removed.
3894 * - On success, zero.
3895 * - On failure, a negative value.
3898 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3899 struct rte_eth_ntuple_filter *ntuple_filter)
3901 struct e1000_filter_info *filter_info =
3902 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3903 struct e1000_2tuple_filter_info filter_2tuple;
3904 struct e1000_2tuple_filter *filter;
3907 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3908 ret = ntuple_filter_to_2tuple(ntuple_filter,
3913 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3915 if (filter == NULL) {
3916 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3920 igb_delete_2tuple_filter(dev, filter);
3925 /* inject a igb flex filter to HW */
3927 igb_inject_flex_filter(struct rte_eth_dev *dev,
3928 struct e1000_flex_filter *filter)
3930 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3931 uint32_t wufc, queueing;
3935 wufc = E1000_READ_REG(hw, E1000_WUFC);
3936 if (filter->index < E1000_MAX_FHFT)
3937 reg_off = E1000_FHFT(filter->index);
3939 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3941 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3942 (E1000_WUFC_FLX0 << filter->index));
3943 queueing = filter->filter_info.len |
3944 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3945 (filter->filter_info.priority <<
3946 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3947 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3950 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3951 E1000_WRITE_REG(hw, reg_off,
3952 filter->filter_info.dwords[j]);
3953 reg_off += sizeof(uint32_t);
3954 E1000_WRITE_REG(hw, reg_off,
3955 filter->filter_info.dwords[++j]);
3956 reg_off += sizeof(uint32_t);
3957 E1000_WRITE_REG(hw, reg_off,
3958 (uint32_t)filter->filter_info.mask[i]);
3959 reg_off += sizeof(uint32_t) * 2;
3964 static inline struct e1000_flex_filter *
3965 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3966 struct e1000_flex_filter_info *key)
3968 struct e1000_flex_filter *it;
3970 TAILQ_FOREACH(it, filter_list, entries) {
3971 if (memcmp(key, &it->filter_info,
3972 sizeof(struct e1000_flex_filter_info)) == 0)
3979 /* remove a flex byte filter
3981 * dev: Pointer to struct rte_eth_dev.
3982 * filter: the pointer of the filter will be removed.
3985 igb_remove_flex_filter(struct rte_eth_dev *dev,
3986 struct e1000_flex_filter *filter)
3988 struct e1000_filter_info *filter_info =
3989 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3990 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3994 wufc = E1000_READ_REG(hw, E1000_WUFC);
3995 if (filter->index < E1000_MAX_FHFT)
3996 reg_off = E1000_FHFT(filter->index);
3998 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4000 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4001 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4003 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4004 (~(E1000_WUFC_FLX0 << filter->index)));
4006 filter_info->flex_mask &= ~(1 << filter->index);
4007 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4012 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4013 struct igb_flex_filter *filter,
4016 struct e1000_filter_info *filter_info =
4017 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4018 struct e1000_flex_filter *flex_filter, *it;
4022 flex_filter = rte_zmalloc("e1000_flex_filter",
4023 sizeof(struct e1000_flex_filter), 0);
4024 if (flex_filter == NULL)
4027 flex_filter->filter_info.len = filter->len;
4028 flex_filter->filter_info.priority = filter->priority;
4029 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4030 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4032 /* reverse bits in flex filter's mask*/
4033 for (shift = 0; shift < CHAR_BIT; shift++) {
4034 if (filter->mask[i] & (0x01 << shift))
4035 mask |= (0x80 >> shift);
4037 flex_filter->filter_info.mask[i] = mask;
4040 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4041 &flex_filter->filter_info);
4042 if (it == NULL && !add) {
4043 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4044 rte_free(flex_filter);
4047 if (it != NULL && add) {
4048 PMD_DRV_LOG(ERR, "filter exists.");
4049 rte_free(flex_filter);
4054 flex_filter->queue = filter->queue;
4056 * look for an unused flex filter index
4057 * and insert the filter into the list.
4059 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4060 if (!(filter_info->flex_mask & (1 << i))) {
4061 filter_info->flex_mask |= 1 << i;
4062 flex_filter->index = i;
4063 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4069 if (i >= E1000_MAX_FLEX_FILTERS) {
4070 PMD_DRV_LOG(ERR, "flex filters are full.");
4071 rte_free(flex_filter);
4075 igb_inject_flex_filter(dev, flex_filter);
4078 igb_remove_flex_filter(dev, it);
4079 rte_free(flex_filter);
4085 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4087 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4088 struct e1000_5tuple_filter_info *filter_info)
4090 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4092 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4093 return -EINVAL; /* filter index is out of range. */
4094 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4095 return -EINVAL; /* flags is invalid. */
4097 switch (filter->dst_ip_mask) {
4099 filter_info->dst_ip_mask = 0;
4100 filter_info->dst_ip = filter->dst_ip;
4103 filter_info->dst_ip_mask = 1;
4106 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4110 switch (filter->src_ip_mask) {
4112 filter_info->src_ip_mask = 0;
4113 filter_info->src_ip = filter->src_ip;
4116 filter_info->src_ip_mask = 1;
4119 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4123 switch (filter->dst_port_mask) {
4125 filter_info->dst_port_mask = 0;
4126 filter_info->dst_port = filter->dst_port;
4129 filter_info->dst_port_mask = 1;
4132 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4136 switch (filter->src_port_mask) {
4138 filter_info->src_port_mask = 0;
4139 filter_info->src_port = filter->src_port;
4142 filter_info->src_port_mask = 1;
4145 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4149 switch (filter->proto_mask) {
4151 filter_info->proto_mask = 0;
4152 filter_info->proto = filter->proto;
4155 filter_info->proto_mask = 1;
4158 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4162 filter_info->priority = (uint8_t)filter->priority;
4163 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4164 filter_info->tcp_flags = filter->tcp_flags;
4166 filter_info->tcp_flags = 0;
4171 static inline struct e1000_5tuple_filter *
4172 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4173 struct e1000_5tuple_filter_info *key)
4175 struct e1000_5tuple_filter *it;
4177 TAILQ_FOREACH(it, filter_list, entries) {
4178 if (memcmp(key, &it->filter_info,
4179 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4186 /* inject a igb 5-tuple filter to HW */
4188 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4189 struct e1000_5tuple_filter *filter)
4191 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4192 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4193 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4197 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4198 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4199 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4200 if (filter->filter_info.dst_ip_mask == 0)
4201 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4202 if (filter->filter_info.src_port_mask == 0)
4203 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4204 if (filter->filter_info.proto_mask == 0)
4205 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4206 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4207 E1000_FTQF_QUEUE_MASK;
4208 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4209 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4210 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4211 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4213 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4214 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4216 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4217 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4218 imir |= E1000_IMIR_PORT_BP;
4220 imir &= ~E1000_IMIR_PORT_BP;
4221 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4223 /* tcp flags bits setting. */
4224 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4225 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4226 imir_ext |= E1000_IMIREXT_CTRL_URG;
4227 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4228 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4229 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4230 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4231 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4232 imir_ext |= E1000_IMIREXT_CTRL_RST;
4233 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4234 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4235 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4236 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4238 imir_ext |= E1000_IMIREXT_CTRL_BP;
4240 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4241 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4245 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4248 * dev: Pointer to struct rte_eth_dev.
4249 * ntuple_filter: ponter to the filter that will be added.
4252 * - On success, zero.
4253 * - On failure, a negative value.
4256 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4257 struct rte_eth_ntuple_filter *ntuple_filter)
4259 struct e1000_filter_info *filter_info =
4260 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4261 struct e1000_5tuple_filter *filter;
4265 filter = rte_zmalloc("e1000_5tuple_filter",
4266 sizeof(struct e1000_5tuple_filter), 0);
4270 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4271 &filter->filter_info);
4277 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4278 &filter->filter_info) != NULL) {
4279 PMD_DRV_LOG(ERR, "filter exists.");
4283 filter->queue = ntuple_filter->queue;
4286 * look for an unused 5tuple filter index,
4287 * and insert the filter to list.
4289 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4290 if (!(filter_info->fivetuple_mask & (1 << i))) {
4291 filter_info->fivetuple_mask |= 1 << i;
4293 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4299 if (i >= E1000_MAX_FTQF_FILTERS) {
4300 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4305 igb_inject_5tuple_filter_82576(dev, filter);
4310 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4311 struct e1000_5tuple_filter *filter)
4313 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4314 struct e1000_filter_info *filter_info =
4315 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4317 filter_info->fivetuple_mask &= ~(1 << filter->index);
4318 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4321 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4322 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4323 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4324 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4325 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4326 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4327 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4332 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4335 * dev: Pointer to struct rte_eth_dev.
4336 * ntuple_filter: ponter to the filter that will be removed.
4339 * - On success, zero.
4340 * - On failure, a negative value.
4343 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4344 struct rte_eth_ntuple_filter *ntuple_filter)
4346 struct e1000_filter_info *filter_info =
4347 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4348 struct e1000_5tuple_filter_info filter_5tuple;
4349 struct e1000_5tuple_filter *filter;
4352 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4353 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4358 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4360 if (filter == NULL) {
4361 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4365 igb_delete_5tuple_filter_82576(dev, filter);
4371 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4374 struct e1000_hw *hw;
4375 struct rte_eth_dev_info dev_info;
4376 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4379 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4381 #ifdef RTE_LIBRTE_82571_SUPPORT
4382 /* XXX: not bigger than max_rx_pktlen */
4383 if (hw->mac.type == e1000_82571)
4386 ret = eth_igb_infos_get(dev, &dev_info);
4390 /* check that mtu is within the allowed range */
4391 if (mtu < RTE_ETHER_MIN_MTU ||
4392 frame_size > dev_info.max_rx_pktlen)
4396 * If device is started, refuse mtu that requires the support of
4397 * scattered packets when this feature has not been enabled before.
4399 if (dev->data->dev_started && !dev->data->scattered_rx &&
4400 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
4401 PMD_INIT_LOG(ERR, "Stop port first.");
4405 rctl = E1000_READ_REG(hw, E1000_RCTL);
4407 /* switch to jumbo mode if needed */
4408 if (frame_size > E1000_ETH_MAX_LEN) {
4409 dev->data->dev_conf.rxmode.offloads |=
4410 DEV_RX_OFFLOAD_JUMBO_FRAME;
4411 rctl |= E1000_RCTL_LPE;
4413 dev->data->dev_conf.rxmode.offloads &=
4414 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4415 rctl &= ~E1000_RCTL_LPE;
4417 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4419 /* update max frame size */
4420 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4422 E1000_WRITE_REG(hw, E1000_RLPML,
4423 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4429 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4432 * dev: Pointer to struct rte_eth_dev.
4433 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4434 * add: if true, add filter, if false, remove filter
4437 * - On success, zero.
4438 * - On failure, a negative value.
4441 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4442 struct rte_eth_ntuple_filter *ntuple_filter,
4445 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4448 switch (ntuple_filter->flags) {
4449 case RTE_5TUPLE_FLAGS:
4450 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4451 if (hw->mac.type != e1000_82576)
4454 ret = igb_add_5tuple_filter_82576(dev,
4457 ret = igb_remove_5tuple_filter_82576(dev,
4460 case RTE_2TUPLE_FLAGS:
4461 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4462 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4463 hw->mac.type != e1000_i210 &&
4464 hw->mac.type != e1000_i211)
4467 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4469 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4480 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4485 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4486 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4487 (filter_info->ethertype_mask & (1 << i)))
4494 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4495 uint16_t ethertype, uint32_t etqf)
4499 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4500 if (!(filter_info->ethertype_mask & (1 << i))) {
4501 filter_info->ethertype_mask |= 1 << i;
4502 filter_info->ethertype_filters[i].ethertype = ethertype;
4503 filter_info->ethertype_filters[i].etqf = etqf;
4511 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4514 if (idx >= E1000_MAX_ETQF_FILTERS)
4516 filter_info->ethertype_mask &= ~(1 << idx);
4517 filter_info->ethertype_filters[idx].ethertype = 0;
4518 filter_info->ethertype_filters[idx].etqf = 0;
4524 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4525 struct rte_eth_ethertype_filter *filter,
4528 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4529 struct e1000_filter_info *filter_info =
4530 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4534 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4535 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4536 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4537 " ethertype filter.", filter->ether_type);
4541 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4542 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4545 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4546 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4550 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4551 if (ret >= 0 && add) {
4552 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4553 filter->ether_type);
4556 if (ret < 0 && !add) {
4557 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4558 filter->ether_type);
4563 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4564 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4565 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4566 ret = igb_ethertype_filter_insert(filter_info,
4567 filter->ether_type, etqf);
4569 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4573 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4577 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4578 E1000_WRITE_FLUSH(hw);
4584 eth_igb_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
4585 const struct rte_flow_ops **ops)
4587 *ops = &igb_flow_ops;
4592 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4593 struct rte_ether_addr *mc_addr_set,
4594 uint32_t nb_mc_addr)
4596 struct e1000_hw *hw;
4598 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4599 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4604 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4606 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4607 uint64_t systime_cycles;
4609 switch (hw->mac.type) {
4613 * Need to read System Time Residue Register to be able
4614 * to read the other two registers.
4616 E1000_READ_REG(hw, E1000_SYSTIMR);
4617 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4618 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4619 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4626 * Need to read System Time Residue Register to be able
4627 * to read the other two registers.
4629 E1000_READ_REG(hw, E1000_SYSTIMR);
4630 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4631 /* Only the 8 LSB are valid. */
4632 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4636 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4637 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4642 return systime_cycles;
4646 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4648 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4649 uint64_t rx_tstamp_cycles;
4651 switch (hw->mac.type) {
4654 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4655 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4656 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4662 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4663 /* Only the 8 LSB are valid. */
4664 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4668 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4669 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4674 return rx_tstamp_cycles;
4678 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4680 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4681 uint64_t tx_tstamp_cycles;
4683 switch (hw->mac.type) {
4686 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4687 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4688 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4694 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4695 /* Only the 8 LSB are valid. */
4696 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4700 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4701 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4706 return tx_tstamp_cycles;
4710 igb_start_timecounters(struct rte_eth_dev *dev)
4712 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4713 struct e1000_adapter *adapter = dev->data->dev_private;
4714 uint32_t incval = 1;
4716 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4718 switch (hw->mac.type) {
4722 /* 32 LSB bits + 8 MSB bits = 40 bits */
4723 mask = (1ULL << 40) - 1;
4728 * Start incrementing the register
4729 * used to timestamp PTP packets.
4731 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4734 incval = E1000_INCVALUE_82576;
4735 shift = IGB_82576_TSYNC_SHIFT;
4736 E1000_WRITE_REG(hw, E1000_TIMINCA,
4737 E1000_INCPERIOD_82576 | incval);
4744 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4745 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4746 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4748 adapter->systime_tc.cc_mask = mask;
4749 adapter->systime_tc.cc_shift = shift;
4750 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4752 adapter->rx_tstamp_tc.cc_mask = mask;
4753 adapter->rx_tstamp_tc.cc_shift = shift;
4754 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4756 adapter->tx_tstamp_tc.cc_mask = mask;
4757 adapter->tx_tstamp_tc.cc_shift = shift;
4758 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4762 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4764 struct e1000_adapter *adapter = dev->data->dev_private;
4766 adapter->systime_tc.nsec += delta;
4767 adapter->rx_tstamp_tc.nsec += delta;
4768 adapter->tx_tstamp_tc.nsec += delta;
4774 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4777 struct e1000_adapter *adapter = dev->data->dev_private;
4779 ns = rte_timespec_to_ns(ts);
4781 /* Set the timecounters to a new value. */
4782 adapter->systime_tc.nsec = ns;
4783 adapter->rx_tstamp_tc.nsec = ns;
4784 adapter->tx_tstamp_tc.nsec = ns;
4790 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4792 uint64_t ns, systime_cycles;
4793 struct e1000_adapter *adapter = dev->data->dev_private;
4795 systime_cycles = igb_read_systime_cyclecounter(dev);
4796 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4797 *ts = rte_ns_to_timespec(ns);
4803 igb_timesync_enable(struct rte_eth_dev *dev)
4805 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4809 /* Stop the timesync system time. */
4810 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4811 /* Reset the timesync system time value. */
4812 switch (hw->mac.type) {
4818 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4821 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4822 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4825 /* Not supported. */
4829 /* Enable system time for it isn't on by default. */
4830 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4831 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4832 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4834 igb_start_timecounters(dev);
4836 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4837 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4838 (RTE_ETHER_TYPE_1588 |
4839 E1000_ETQF_FILTER_ENABLE |
4842 /* Enable timestamping of received PTP packets. */
4843 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4844 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4845 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4847 /* Enable Timestamping of transmitted PTP packets. */
4848 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4849 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4850 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4856 igb_timesync_disable(struct rte_eth_dev *dev)
4858 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4861 /* Disable timestamping of transmitted PTP packets. */
4862 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4863 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4864 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4866 /* Disable timestamping of received PTP packets. */
4867 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4868 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4869 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4871 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4872 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4874 /* Stop incrementating the System Time registers. */
4875 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4881 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4882 struct timespec *timestamp,
4883 uint32_t flags __rte_unused)
4885 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886 struct e1000_adapter *adapter = dev->data->dev_private;
4887 uint32_t tsync_rxctl;
4888 uint64_t rx_tstamp_cycles;
4891 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4892 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4895 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4896 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4897 *timestamp = rte_ns_to_timespec(ns);
4903 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4904 struct timespec *timestamp)
4906 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907 struct e1000_adapter *adapter = dev->data->dev_private;
4908 uint32_t tsync_txctl;
4909 uint64_t tx_tstamp_cycles;
4912 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4913 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4916 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4917 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4918 *timestamp = rte_ns_to_timespec(ns);
4924 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4928 const struct reg_info *reg_group;
4930 while ((reg_group = igb_regs[g_ind++]))
4931 count += igb_reg_group_count(reg_group);
4937 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4941 const struct reg_info *reg_group;
4943 while ((reg_group = igbvf_regs[g_ind++]))
4944 count += igb_reg_group_count(reg_group);
4950 eth_igb_get_regs(struct rte_eth_dev *dev,
4951 struct rte_dev_reg_info *regs)
4953 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4954 uint32_t *data = regs->data;
4957 const struct reg_info *reg_group;
4960 regs->length = eth_igb_get_reg_length(dev);
4961 regs->width = sizeof(uint32_t);
4965 /* Support only full register dump */
4966 if ((regs->length == 0) ||
4967 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4968 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4970 while ((reg_group = igb_regs[g_ind++]))
4971 count += igb_read_regs_group(dev, &data[count],
4980 igbvf_get_regs(struct rte_eth_dev *dev,
4981 struct rte_dev_reg_info *regs)
4983 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4984 uint32_t *data = regs->data;
4987 const struct reg_info *reg_group;
4990 regs->length = igbvf_get_reg_length(dev);
4991 regs->width = sizeof(uint32_t);
4995 /* Support only full register dump */
4996 if ((regs->length == 0) ||
4997 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4998 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5000 while ((reg_group = igbvf_regs[g_ind++]))
5001 count += igb_read_regs_group(dev, &data[count],
5010 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5012 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5014 /* Return unit is byte count */
5015 return hw->nvm.word_size * 2;
5019 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5020 struct rte_dev_eeprom_info *in_eeprom)
5022 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5023 struct e1000_nvm_info *nvm = &hw->nvm;
5024 uint16_t *data = in_eeprom->data;
5027 first = in_eeprom->offset >> 1;
5028 length = in_eeprom->length >> 1;
5029 if ((first >= hw->nvm.word_size) ||
5030 ((first + length) >= hw->nvm.word_size))
5033 in_eeprom->magic = hw->vendor_id |
5034 ((uint32_t)hw->device_id << 16);
5036 if ((nvm->ops.read) == NULL)
5039 return nvm->ops.read(hw, first, length, data);
5043 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5044 struct rte_dev_eeprom_info *in_eeprom)
5046 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5047 struct e1000_nvm_info *nvm = &hw->nvm;
5048 uint16_t *data = in_eeprom->data;
5051 first = in_eeprom->offset >> 1;
5052 length = in_eeprom->length >> 1;
5053 if ((first >= hw->nvm.word_size) ||
5054 ((first + length) >= hw->nvm.word_size))
5057 in_eeprom->magic = (uint32_t)hw->vendor_id |
5058 ((uint32_t)hw->device_id << 16);
5060 if ((nvm->ops.write) == NULL)
5062 return nvm->ops.write(hw, first, length, data);
5066 eth_igb_get_module_info(struct rte_eth_dev *dev,
5067 struct rte_eth_dev_module_info *modinfo)
5069 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071 uint32_t status = 0;
5072 uint16_t sff8472_rev, addr_mode;
5073 bool page_swap = false;
5075 if (hw->phy.media_type == e1000_media_type_copper ||
5076 hw->phy.media_type == e1000_media_type_unknown)
5079 /* Check whether we support SFF-8472 or not */
5080 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5084 /* addressing mode is not supported */
5085 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5089 /* addressing mode is not supported */
5090 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5092 "Address change required to access page 0xA2, "
5093 "but not supported. Please report the module "
5094 "type to the driver maintainers.\n");
5098 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5099 /* We have an SFP, but it does not support SFF-8472 */
5100 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5101 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5103 /* We have an SFP which supports a revision of SFF-8472 */
5104 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5105 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5112 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5113 struct rte_dev_eeprom_info *info)
5115 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5117 uint32_t status = 0;
5118 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5119 u16 first_word, last_word;
5122 first_word = info->offset >> 1;
5123 last_word = (info->offset + info->length - 1) >> 1;
5125 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5126 for (i = 0; i < last_word - first_word + 1; i++) {
5127 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5130 /* Error occurred while reading module */
5134 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5137 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5143 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5145 struct e1000_hw *hw =
5146 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5148 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5149 uint32_t vec = E1000_MISC_VEC_ID;
5151 if (rte_intr_allow_others(intr_handle))
5152 vec = E1000_RX_VEC_START;
5154 uint32_t mask = 1 << (queue_id + vec);
5156 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5157 E1000_WRITE_FLUSH(hw);
5163 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5165 struct e1000_hw *hw =
5166 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5168 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5169 uint32_t vec = E1000_MISC_VEC_ID;
5171 if (rte_intr_allow_others(intr_handle))
5172 vec = E1000_RX_VEC_START;
5174 uint32_t mask = 1 << (queue_id + vec);
5177 regval = E1000_READ_REG(hw, E1000_EIMS);
5178 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5179 E1000_WRITE_FLUSH(hw);
5181 rte_intr_ack(intr_handle);
5187 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5188 uint8_t index, uint8_t offset)
5190 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5193 val &= ~((uint32_t)0xFF << offset);
5195 /* write vector and valid bit */
5196 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5198 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5202 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5203 uint8_t queue, uint8_t msix_vector)
5207 if (hw->mac.type == e1000_82575) {
5209 tmp = E1000_EICR_RX_QUEUE0 << queue;
5210 else if (direction == 1)
5211 tmp = E1000_EICR_TX_QUEUE0 << queue;
5212 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5213 } else if (hw->mac.type == e1000_82576) {
5214 if ((direction == 0) || (direction == 1))
5215 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5216 ((queue & 0x8) << 1) +
5218 } else if ((hw->mac.type == e1000_82580) ||
5219 (hw->mac.type == e1000_i350) ||
5220 (hw->mac.type == e1000_i354) ||
5221 (hw->mac.type == e1000_i210) ||
5222 (hw->mac.type == e1000_i211)) {
5223 if ((direction == 0) || (direction == 1))
5224 eth_igb_write_ivar(hw, msix_vector,
5226 ((queue & 0x1) << 4) +
5231 /* Sets up the hardware to generate MSI-X interrupts properly
5233 * board private structure
5236 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5239 uint32_t tmpval, regval, intr_mask;
5240 struct e1000_hw *hw =
5241 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5242 uint32_t vec = E1000_MISC_VEC_ID;
5243 uint32_t base = E1000_MISC_VEC_ID;
5244 uint32_t misc_shift = 0;
5245 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5246 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5248 /* won't configure msix register if no mapping is done
5249 * between intr vector and event fd
5251 if (!rte_intr_dp_is_en(intr_handle))
5254 if (rte_intr_allow_others(intr_handle)) {
5255 vec = base = E1000_RX_VEC_START;
5259 /* set interrupt vector for other causes */
5260 if (hw->mac.type == e1000_82575) {
5261 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5262 /* enable MSI-X PBA support */
5263 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5265 /* Auto-Mask interrupts upon ICR read */
5266 tmpval |= E1000_CTRL_EXT_EIAME;
5267 tmpval |= E1000_CTRL_EXT_IRCA;
5269 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5271 /* enable msix_other interrupt */
5272 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5273 regval = E1000_READ_REG(hw, E1000_EIAC);
5274 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5275 regval = E1000_READ_REG(hw, E1000_EIAM);
5276 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5277 } else if ((hw->mac.type == e1000_82576) ||
5278 (hw->mac.type == e1000_82580) ||
5279 (hw->mac.type == e1000_i350) ||
5280 (hw->mac.type == e1000_i354) ||
5281 (hw->mac.type == e1000_i210) ||
5282 (hw->mac.type == e1000_i211)) {
5283 /* turn on MSI-X capability first */
5284 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5285 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5287 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5290 if (dev->data->dev_conf.intr_conf.lsc != 0)
5291 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5293 regval = E1000_READ_REG(hw, E1000_EIAC);
5294 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5296 /* enable msix_other interrupt */
5297 regval = E1000_READ_REG(hw, E1000_EIMS);
5298 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5299 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5300 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5303 /* use EIAM to auto-mask when MSI-X interrupt
5304 * is asserted, this saves a register write for every interrupt
5306 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5309 if (dev->data->dev_conf.intr_conf.lsc != 0)
5310 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5312 regval = E1000_READ_REG(hw, E1000_EIAM);
5313 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5315 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5316 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5317 intr_handle->intr_vec[queue_id] = vec;
5318 if (vec < base + intr_handle->nb_efd - 1)
5322 E1000_WRITE_FLUSH(hw);
5325 /* restore n-tuple filter */
5327 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5329 struct e1000_filter_info *filter_info =
5330 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5331 struct e1000_5tuple_filter *p_5tuple;
5332 struct e1000_2tuple_filter *p_2tuple;
5334 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5335 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5338 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5339 igb_inject_2uple_filter(dev, p_2tuple);
5343 /* restore SYN filter */
5345 igb_syn_filter_restore(struct rte_eth_dev *dev)
5347 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5348 struct e1000_filter_info *filter_info =
5349 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5352 synqf = filter_info->syn_info;
5354 if (synqf & E1000_SYN_FILTER_ENABLE) {
5355 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5356 E1000_WRITE_FLUSH(hw);
5360 /* restore ethernet type filter */
5362 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5364 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5365 struct e1000_filter_info *filter_info =
5366 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5369 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5370 if (filter_info->ethertype_mask & (1 << i)) {
5371 E1000_WRITE_REG(hw, E1000_ETQF(i),
5372 filter_info->ethertype_filters[i].etqf);
5373 E1000_WRITE_FLUSH(hw);
5378 /* restore flex byte filter */
5380 igb_flex_filter_restore(struct rte_eth_dev *dev)
5382 struct e1000_filter_info *filter_info =
5383 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5384 struct e1000_flex_filter *flex_filter;
5386 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5387 igb_inject_flex_filter(dev, flex_filter);
5391 /* restore rss filter */
5393 igb_rss_filter_restore(struct rte_eth_dev *dev)
5395 struct e1000_filter_info *filter_info =
5396 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5398 if (filter_info->rss_info.conf.queue_num)
5399 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5402 /* restore all types filter */
5404 igb_filter_restore(struct rte_eth_dev *dev)
5406 igb_ntuple_filter_restore(dev);
5407 igb_ethertype_filter_restore(dev);
5408 igb_syn_filter_restore(dev);
5409 igb_flex_filter_restore(dev);
5410 igb_rss_filter_restore(dev);
5415 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5416 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5417 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5418 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5419 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5420 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");