1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
15 #include <rte_debug.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memory.h>
23 #include <rte_malloc.h>
26 #include "e1000_logs.h"
27 #include "base/e1000_api.h"
28 #include "e1000_ethdev.h"
32 * Default values for port configuration
34 #define IGB_DEFAULT_RX_FREE_THRESH 32
36 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
37 #define IGB_DEFAULT_RX_HTHRESH 8
38 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
40 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
41 #define IGB_DEFAULT_TX_HTHRESH 1
42 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
44 /* Bit shift and mask */
45 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
46 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
47 #define IGB_8_BIT_WIDTH CHAR_BIT
48 #define IGB_8_BIT_MASK UINT8_MAX
50 /* Additional timesync values. */
51 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
52 #define E1000_ETQF_FILTER_1588 3
53 #define IGB_82576_TSYNC_SHIFT 16
54 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
55 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
56 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
58 #define E1000_VTIVAR_MISC 0x01740
59 #define E1000_VTIVAR_MISC_MASK 0xFF
60 #define E1000_VTIVAR_VALID 0x80
61 #define E1000_VTIVAR_MISC_MAILBOX 0
62 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
64 /* External VLAN Enable bit mask */
65 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
67 /* External VLAN Ether Type bit mask and shift */
68 #define E1000_VET_VET_EXT 0xFFFF0000
69 #define E1000_VET_VET_EXT_SHIFT 16
71 static int eth_igb_configure(struct rte_eth_dev *dev);
72 static int eth_igb_start(struct rte_eth_dev *dev);
73 static void eth_igb_stop(struct rte_eth_dev *dev);
74 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
75 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
76 static void eth_igb_close(struct rte_eth_dev *dev);
77 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
78 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
79 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
80 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
81 static int eth_igb_link_update(struct rte_eth_dev *dev,
82 int wait_to_complete);
83 static int eth_igb_stats_get(struct rte_eth_dev *dev,
84 struct rte_eth_stats *rte_stats);
85 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
86 struct rte_eth_xstat *xstats, unsigned n);
87 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
89 uint64_t *values, unsigned int n);
90 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
91 struct rte_eth_xstat_name *xstats_names,
93 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
94 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
96 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
97 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
98 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
99 char *fw_version, size_t fw_size);
100 static void eth_igb_infos_get(struct rte_eth_dev *dev,
101 struct rte_eth_dev_info *dev_info);
102 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
103 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
104 struct rte_eth_dev_info *dev_info);
105 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
106 struct rte_eth_fc_conf *fc_conf);
107 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
108 struct rte_eth_fc_conf *fc_conf);
109 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
110 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
111 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
112 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
113 struct rte_intr_handle *handle);
114 static void eth_igb_interrupt_handler(void *param);
115 static int igb_hardware_init(struct e1000_hw *hw);
116 static void igb_hw_control_acquire(struct e1000_hw *hw);
117 static void igb_hw_control_release(struct e1000_hw *hw);
118 static void igb_init_manageability(struct e1000_hw *hw);
119 static void igb_release_manageability(struct e1000_hw *hw);
121 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
123 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
124 uint16_t vlan_id, int on);
125 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
126 enum rte_vlan_type vlan_type,
128 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
130 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
131 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
132 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
133 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
134 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
135 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
137 static int eth_igb_led_on(struct rte_eth_dev *dev);
138 static int eth_igb_led_off(struct rte_eth_dev *dev);
140 static void igb_intr_disable(struct e1000_hw *hw);
141 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
142 static int eth_igb_rar_set(struct rte_eth_dev *dev,
143 struct ether_addr *mac_addr,
144 uint32_t index, uint32_t pool);
145 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
146 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
147 struct ether_addr *addr);
149 static void igbvf_intr_disable(struct e1000_hw *hw);
150 static int igbvf_dev_configure(struct rte_eth_dev *dev);
151 static int igbvf_dev_start(struct rte_eth_dev *dev);
152 static void igbvf_dev_stop(struct rte_eth_dev *dev);
153 static void igbvf_dev_close(struct rte_eth_dev *dev);
154 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
155 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
156 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
157 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
158 static int eth_igbvf_link_update(struct e1000_hw *hw);
159 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
160 struct rte_eth_stats *rte_stats);
161 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
162 struct rte_eth_xstat *xstats, unsigned n);
163 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
164 struct rte_eth_xstat_name *xstats_names,
166 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
167 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
168 uint16_t vlan_id, int on);
169 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
170 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
171 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
172 struct ether_addr *addr);
173 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
174 static int igbvf_get_regs(struct rte_eth_dev *dev,
175 struct rte_dev_reg_info *regs);
177 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
178 struct rte_eth_rss_reta_entry64 *reta_conf,
180 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
181 struct rte_eth_rss_reta_entry64 *reta_conf,
184 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
185 struct rte_eth_syn_filter *filter);
186 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
187 enum rte_filter_op filter_op,
189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
190 struct rte_eth_ntuple_filter *ntuple_filter);
191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
194 struct rte_eth_flex_filter *filter);
195 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
196 enum rte_filter_op filter_op,
198 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
199 struct rte_eth_ntuple_filter *ntuple_filter);
200 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
201 struct rte_eth_ntuple_filter *ntuple_filter);
202 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
203 struct rte_eth_ntuple_filter *filter);
204 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
205 enum rte_filter_op filter_op,
207 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
208 enum rte_filter_op filter_op,
210 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
211 struct rte_eth_ethertype_filter *filter);
212 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
213 enum rte_filter_type filter_type,
214 enum rte_filter_op filter_op,
216 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
217 static int eth_igb_get_regs(struct rte_eth_dev *dev,
218 struct rte_dev_reg_info *regs);
219 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
220 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
221 struct rte_dev_eeprom_info *eeprom);
222 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
223 struct rte_dev_eeprom_info *eeprom);
224 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
225 struct rte_eth_dev_module_info *modinfo);
226 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
227 struct rte_dev_eeprom_info *info);
228 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
229 struct ether_addr *mc_addr_set,
230 uint32_t nb_mc_addr);
231 static int igb_timesync_enable(struct rte_eth_dev *dev);
232 static int igb_timesync_disable(struct rte_eth_dev *dev);
233 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
234 struct timespec *timestamp,
236 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
237 struct timespec *timestamp);
238 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
239 static int igb_timesync_read_time(struct rte_eth_dev *dev,
240 struct timespec *timestamp);
241 static int igb_timesync_write_time(struct rte_eth_dev *dev,
242 const struct timespec *timestamp);
243 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
245 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
247 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
248 uint8_t queue, uint8_t msix_vector);
249 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
250 uint8_t index, uint8_t offset);
251 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
252 static void eth_igbvf_interrupt_handler(void *param);
253 static void igbvf_mbx_process(struct rte_eth_dev *dev);
254 static int igb_filter_restore(struct rte_eth_dev *dev);
257 * Define VF Stats MACRO for Non "cleared on read" register
259 #define UPDATE_VF_STAT(reg, last, cur) \
261 u32 latest = E1000_READ_REG(hw, reg); \
262 cur += (latest - last) & UINT_MAX; \
266 #define IGB_FC_PAUSE_TIME 0x0680
267 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
268 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
270 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
272 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
275 * The set of PCI devices this driver supports
277 static const struct rte_pci_id pci_id_igb_map[] = {
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
280 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
302 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
319 { .vendor_id = 0, /* sentinel */ },
323 * The set of PCI devices this driver supports (for 82576&I350 VF)
325 static const struct rte_pci_id pci_id_igbvf_map[] = {
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
330 { .vendor_id = 0, /* sentinel */ },
333 static const struct rte_eth_desc_lim rx_desc_lim = {
334 .nb_max = E1000_MAX_RING_DESC,
335 .nb_min = E1000_MIN_RING_DESC,
336 .nb_align = IGB_RXD_ALIGN,
339 static const struct rte_eth_desc_lim tx_desc_lim = {
340 .nb_max = E1000_MAX_RING_DESC,
341 .nb_min = E1000_MIN_RING_DESC,
342 .nb_align = IGB_RXD_ALIGN,
343 .nb_seg_max = IGB_TX_MAX_SEG,
344 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
347 static const struct eth_dev_ops eth_igb_ops = {
348 .dev_configure = eth_igb_configure,
349 .dev_start = eth_igb_start,
350 .dev_stop = eth_igb_stop,
351 .dev_set_link_up = eth_igb_dev_set_link_up,
352 .dev_set_link_down = eth_igb_dev_set_link_down,
353 .dev_close = eth_igb_close,
354 .promiscuous_enable = eth_igb_promiscuous_enable,
355 .promiscuous_disable = eth_igb_promiscuous_disable,
356 .allmulticast_enable = eth_igb_allmulticast_enable,
357 .allmulticast_disable = eth_igb_allmulticast_disable,
358 .link_update = eth_igb_link_update,
359 .stats_get = eth_igb_stats_get,
360 .xstats_get = eth_igb_xstats_get,
361 .xstats_get_by_id = eth_igb_xstats_get_by_id,
362 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
363 .xstats_get_names = eth_igb_xstats_get_names,
364 .stats_reset = eth_igb_stats_reset,
365 .xstats_reset = eth_igb_xstats_reset,
366 .fw_version_get = eth_igb_fw_version_get,
367 .dev_infos_get = eth_igb_infos_get,
368 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
369 .mtu_set = eth_igb_mtu_set,
370 .vlan_filter_set = eth_igb_vlan_filter_set,
371 .vlan_tpid_set = eth_igb_vlan_tpid_set,
372 .vlan_offload_set = eth_igb_vlan_offload_set,
373 .rx_queue_setup = eth_igb_rx_queue_setup,
374 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
375 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
376 .rx_queue_release = eth_igb_rx_queue_release,
377 .rx_queue_count = eth_igb_rx_queue_count,
378 .rx_descriptor_done = eth_igb_rx_descriptor_done,
379 .rx_descriptor_status = eth_igb_rx_descriptor_status,
380 .tx_descriptor_status = eth_igb_tx_descriptor_status,
381 .tx_queue_setup = eth_igb_tx_queue_setup,
382 .tx_queue_release = eth_igb_tx_queue_release,
383 .tx_done_cleanup = eth_igb_tx_done_cleanup,
384 .dev_led_on = eth_igb_led_on,
385 .dev_led_off = eth_igb_led_off,
386 .flow_ctrl_get = eth_igb_flow_ctrl_get,
387 .flow_ctrl_set = eth_igb_flow_ctrl_set,
388 .mac_addr_add = eth_igb_rar_set,
389 .mac_addr_remove = eth_igb_rar_clear,
390 .mac_addr_set = eth_igb_default_mac_addr_set,
391 .reta_update = eth_igb_rss_reta_update,
392 .reta_query = eth_igb_rss_reta_query,
393 .rss_hash_update = eth_igb_rss_hash_update,
394 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
395 .filter_ctrl = eth_igb_filter_ctrl,
396 .set_mc_addr_list = eth_igb_set_mc_addr_list,
397 .rxq_info_get = igb_rxq_info_get,
398 .txq_info_get = igb_txq_info_get,
399 .timesync_enable = igb_timesync_enable,
400 .timesync_disable = igb_timesync_disable,
401 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
402 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
403 .get_reg = eth_igb_get_regs,
404 .get_eeprom_length = eth_igb_get_eeprom_length,
405 .get_eeprom = eth_igb_get_eeprom,
406 .set_eeprom = eth_igb_set_eeprom,
407 .get_module_info = eth_igb_get_module_info,
408 .get_module_eeprom = eth_igb_get_module_eeprom,
409 .timesync_adjust_time = igb_timesync_adjust_time,
410 .timesync_read_time = igb_timesync_read_time,
411 .timesync_write_time = igb_timesync_write_time,
415 * dev_ops for virtual function, bare necessities for basic vf
416 * operation have been implemented
418 static const struct eth_dev_ops igbvf_eth_dev_ops = {
419 .dev_configure = igbvf_dev_configure,
420 .dev_start = igbvf_dev_start,
421 .dev_stop = igbvf_dev_stop,
422 .dev_close = igbvf_dev_close,
423 .promiscuous_enable = igbvf_promiscuous_enable,
424 .promiscuous_disable = igbvf_promiscuous_disable,
425 .allmulticast_enable = igbvf_allmulticast_enable,
426 .allmulticast_disable = igbvf_allmulticast_disable,
427 .link_update = eth_igb_link_update,
428 .stats_get = eth_igbvf_stats_get,
429 .xstats_get = eth_igbvf_xstats_get,
430 .xstats_get_names = eth_igbvf_xstats_get_names,
431 .stats_reset = eth_igbvf_stats_reset,
432 .xstats_reset = eth_igbvf_stats_reset,
433 .vlan_filter_set = igbvf_vlan_filter_set,
434 .dev_infos_get = eth_igbvf_infos_get,
435 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
436 .rx_queue_setup = eth_igb_rx_queue_setup,
437 .rx_queue_release = eth_igb_rx_queue_release,
438 .tx_queue_setup = eth_igb_tx_queue_setup,
439 .tx_queue_release = eth_igb_tx_queue_release,
440 .set_mc_addr_list = eth_igb_set_mc_addr_list,
441 .rxq_info_get = igb_rxq_info_get,
442 .txq_info_get = igb_txq_info_get,
443 .mac_addr_set = igbvf_default_mac_addr_set,
444 .get_reg = igbvf_get_regs,
447 /* store statistics names and its offset in stats structure */
448 struct rte_igb_xstats_name_off {
449 char name[RTE_ETH_XSTATS_NAME_SIZE];
453 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
454 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
455 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
456 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
457 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
458 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
459 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
460 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
462 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
463 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
464 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
465 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
466 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
467 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
468 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
469 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
470 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
471 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
472 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
474 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
475 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
476 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
477 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
478 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
480 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
482 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
483 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
484 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
485 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
486 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
487 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
488 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
489 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
490 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
491 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
492 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
493 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
494 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
495 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
496 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
497 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
498 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
499 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
501 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
503 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
504 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
505 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
506 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
507 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
508 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
509 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
511 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
514 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
515 sizeof(rte_igb_stats_strings[0]))
517 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
518 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
519 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
520 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
521 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
522 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
525 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
526 sizeof(rte_igbvf_stats_strings[0]))
530 igb_intr_enable(struct rte_eth_dev *dev)
532 struct e1000_interrupt *intr =
533 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
534 struct e1000_hw *hw =
535 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
537 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
538 E1000_WRITE_FLUSH(hw);
542 igb_intr_disable(struct e1000_hw *hw)
544 E1000_WRITE_REG(hw, E1000_IMC, ~0);
545 E1000_WRITE_FLUSH(hw);
549 igbvf_intr_enable(struct rte_eth_dev *dev)
551 struct e1000_hw *hw =
552 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
554 /* only for mailbox */
555 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
556 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
557 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
558 E1000_WRITE_FLUSH(hw);
561 /* only for mailbox now. If RX/TX needed, should extend this function. */
563 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
568 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
569 tmp |= E1000_VTIVAR_VALID;
570 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
574 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
576 struct e1000_hw *hw =
577 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
579 /* Configure VF other cause ivar */
580 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
583 static inline int32_t
584 igb_pf_reset_hw(struct e1000_hw *hw)
589 status = e1000_reset_hw(hw);
591 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
592 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
593 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
594 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
595 E1000_WRITE_FLUSH(hw);
601 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
603 struct e1000_hw *hw =
604 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
607 hw->vendor_id = pci_dev->id.vendor_id;
608 hw->device_id = pci_dev->id.device_id;
609 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
610 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
612 e1000_set_mac_type(hw);
614 /* need to check if it is a vf device below */
618 igb_reset_swfw_lock(struct e1000_hw *hw)
623 * Do mac ops initialization manually here, since we will need
624 * some function pointers set by this call.
626 ret_val = e1000_init_mac_params(hw);
631 * SMBI lock should not fail in this early stage. If this is the case,
632 * it is due to an improper exit of the application.
633 * So force the release of the faulty lock.
635 if (e1000_get_hw_semaphore_generic(hw) < 0) {
636 PMD_DRV_LOG(DEBUG, "SMBI lock released");
638 e1000_put_hw_semaphore_generic(hw);
640 if (hw->mac.ops.acquire_swfw_sync != NULL) {
644 * Phy lock should not fail in this early stage. If this is the case,
645 * it is due to an improper exit of the application.
646 * So force the release of the faulty lock.
648 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
649 if (hw->bus.func > E1000_FUNC_1)
651 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
652 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
655 hw->mac.ops.release_swfw_sync(hw, mask);
658 * This one is more tricky since it is common to all ports; but
659 * swfw_sync retries last long enough (1s) to be almost sure that if
660 * lock can not be taken it is due to an improper lock of the
663 mask = E1000_SWFW_EEP_SM;
664 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
665 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
667 hw->mac.ops.release_swfw_sync(hw, mask);
670 return E1000_SUCCESS;
673 /* Remove all ntuple filters of the device */
674 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
676 struct e1000_filter_info *filter_info =
677 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
678 struct e1000_5tuple_filter *p_5tuple;
679 struct e1000_2tuple_filter *p_2tuple;
681 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
682 TAILQ_REMOVE(&filter_info->fivetuple_list,
686 filter_info->fivetuple_mask = 0;
687 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
688 TAILQ_REMOVE(&filter_info->twotuple_list,
692 filter_info->twotuple_mask = 0;
697 /* Remove all flex filters of the device */
698 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
700 struct e1000_filter_info *filter_info =
701 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
702 struct e1000_flex_filter *p_flex;
704 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
705 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
708 filter_info->flex_mask = 0;
714 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
717 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
718 struct e1000_hw *hw =
719 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
720 struct e1000_vfta * shadow_vfta =
721 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
722 struct e1000_filter_info *filter_info =
723 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
724 struct e1000_adapter *adapter =
725 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
729 eth_dev->dev_ops = ð_igb_ops;
730 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
731 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
732 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
734 /* for secondary processes, we don't initialise any further as primary
735 * has already done this work. Only check we don't need a different
737 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
738 if (eth_dev->data->scattered_rx)
739 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
743 rte_eth_copy_pci_info(eth_dev, pci_dev);
745 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
747 igb_identify_hardware(eth_dev, pci_dev);
748 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
753 e1000_get_bus_info(hw);
755 /* Reset any pending lock */
756 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
761 /* Finish initialization */
762 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
768 hw->phy.autoneg_wait_to_complete = 0;
769 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
772 if (hw->phy.media_type == e1000_media_type_copper) {
773 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
774 hw->phy.disable_polarity_correction = 0;
775 hw->phy.ms_type = e1000_ms_hw_default;
779 * Start from a known state, this is important in reading the nvm
784 /* Make sure we have a good EEPROM before we read from it */
785 if (e1000_validate_nvm_checksum(hw) < 0) {
787 * Some PCI-E parts fail the first check due to
788 * the link being in sleep state, call it again,
789 * if it fails a second time its a real issue.
791 if (e1000_validate_nvm_checksum(hw) < 0) {
792 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
798 /* Read the permanent MAC address out of the EEPROM */
799 if (e1000_read_mac_addr(hw) != 0) {
800 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
805 /* Allocate memory for storing MAC addresses */
806 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
807 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
808 if (eth_dev->data->mac_addrs == NULL) {
809 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
810 "store MAC addresses",
811 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
816 /* Copy the permanent MAC address */
817 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
819 /* initialize the vfta */
820 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
822 /* Now initialize the hardware */
823 if (igb_hardware_init(hw) != 0) {
824 PMD_INIT_LOG(ERR, "Hardware initialization failed");
825 rte_free(eth_dev->data->mac_addrs);
826 eth_dev->data->mac_addrs = NULL;
830 hw->mac.get_link_status = 1;
831 adapter->stopped = 0;
833 /* Indicate SOL/IDER usage */
834 if (e1000_check_reset_block(hw) < 0) {
835 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
839 /* initialize PF if max_vfs not zero */
840 igb_pf_host_init(eth_dev);
842 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
843 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
844 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
845 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
846 E1000_WRITE_FLUSH(hw);
848 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
849 eth_dev->data->port_id, pci_dev->id.vendor_id,
850 pci_dev->id.device_id);
852 rte_intr_callback_register(&pci_dev->intr_handle,
853 eth_igb_interrupt_handler,
856 /* enable uio/vfio intr/eventfd mapping */
857 rte_intr_enable(&pci_dev->intr_handle);
859 /* enable support intr */
860 igb_intr_enable(eth_dev);
862 /* initialize filter info */
863 memset(filter_info, 0,
864 sizeof(struct e1000_filter_info));
866 TAILQ_INIT(&filter_info->flex_list);
867 TAILQ_INIT(&filter_info->twotuple_list);
868 TAILQ_INIT(&filter_info->fivetuple_list);
870 TAILQ_INIT(&igb_filter_ntuple_list);
871 TAILQ_INIT(&igb_filter_ethertype_list);
872 TAILQ_INIT(&igb_filter_syn_list);
873 TAILQ_INIT(&igb_filter_flex_list);
874 TAILQ_INIT(&igb_filter_rss_list);
875 TAILQ_INIT(&igb_flow_list);
880 igb_hw_control_release(hw);
886 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
888 struct rte_pci_device *pci_dev;
889 struct rte_intr_handle *intr_handle;
891 struct e1000_adapter *adapter =
892 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
893 struct e1000_filter_info *filter_info =
894 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
896 PMD_INIT_FUNC_TRACE();
898 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
901 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
902 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
903 intr_handle = &pci_dev->intr_handle;
905 if (adapter->stopped == 0)
906 eth_igb_close(eth_dev);
908 eth_dev->dev_ops = NULL;
909 eth_dev->rx_pkt_burst = NULL;
910 eth_dev->tx_pkt_burst = NULL;
912 /* Reset any pending lock */
913 igb_reset_swfw_lock(hw);
915 rte_free(eth_dev->data->mac_addrs);
916 eth_dev->data->mac_addrs = NULL;
918 /* uninitialize PF if max_vfs not zero */
919 igb_pf_host_uninit(eth_dev);
921 /* disable uio intr before callback unregister */
922 rte_intr_disable(intr_handle);
923 rte_intr_callback_unregister(intr_handle,
924 eth_igb_interrupt_handler, eth_dev);
926 /* clear the SYN filter info */
927 filter_info->syn_info = 0;
929 /* clear the ethertype filters info */
930 filter_info->ethertype_mask = 0;
931 memset(filter_info->ethertype_filters, 0,
932 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
934 /* clear the rss filter info */
935 memset(&filter_info->rss_info, 0,
936 sizeof(struct igb_rte_flow_rss_conf));
938 /* remove all ntuple filters of the device */
939 igb_ntuple_filter_uninit(eth_dev);
941 /* remove all flex filters of the device */
942 igb_flex_filter_uninit(eth_dev);
944 /* clear all the filters list */
945 igb_filterlist_flush(eth_dev);
951 * Virtual Function device init
954 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
956 struct rte_pci_device *pci_dev;
957 struct rte_intr_handle *intr_handle;
958 struct e1000_adapter *adapter =
959 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
960 struct e1000_hw *hw =
961 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
963 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
965 PMD_INIT_FUNC_TRACE();
967 eth_dev->dev_ops = &igbvf_eth_dev_ops;
968 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
969 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
970 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
972 /* for secondary processes, we don't initialise any further as primary
973 * has already done this work. Only check we don't need a different
975 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
976 if (eth_dev->data->scattered_rx)
977 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
981 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
982 rte_eth_copy_pci_info(eth_dev, pci_dev);
984 hw->device_id = pci_dev->id.device_id;
985 hw->vendor_id = pci_dev->id.vendor_id;
986 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
987 adapter->stopped = 0;
989 /* Initialize the shared code (base driver) */
990 diag = e1000_setup_init_funcs(hw, TRUE);
992 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
997 /* init_mailbox_params */
998 hw->mbx.ops.init_params(hw);
1000 /* Disable the interrupts for VF */
1001 igbvf_intr_disable(hw);
1003 diag = hw->mac.ops.reset_hw(hw);
1005 /* Allocate memory for storing MAC addresses */
1006 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1007 hw->mac.rar_entry_count, 0);
1008 if (eth_dev->data->mac_addrs == NULL) {
1010 "Failed to allocate %d bytes needed to store MAC "
1012 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1016 /* Generate a random MAC address, if none was assigned by PF. */
1017 if (is_zero_ether_addr(perm_addr)) {
1018 eth_random_addr(perm_addr->addr_bytes);
1019 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1020 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1021 "%02x:%02x:%02x:%02x:%02x:%02x",
1022 perm_addr->addr_bytes[0],
1023 perm_addr->addr_bytes[1],
1024 perm_addr->addr_bytes[2],
1025 perm_addr->addr_bytes[3],
1026 perm_addr->addr_bytes[4],
1027 perm_addr->addr_bytes[5]);
1030 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1032 rte_free(eth_dev->data->mac_addrs);
1033 eth_dev->data->mac_addrs = NULL;
1036 /* Copy the permanent MAC address */
1037 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1038 ð_dev->data->mac_addrs[0]);
1040 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1042 eth_dev->data->port_id, pci_dev->id.vendor_id,
1043 pci_dev->id.device_id, "igb_mac_82576_vf");
1045 intr_handle = &pci_dev->intr_handle;
1046 rte_intr_callback_register(intr_handle,
1047 eth_igbvf_interrupt_handler, eth_dev);
1053 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1055 struct e1000_adapter *adapter =
1056 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1057 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1059 PMD_INIT_FUNC_TRACE();
1061 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1064 if (adapter->stopped == 0)
1065 igbvf_dev_close(eth_dev);
1067 eth_dev->dev_ops = NULL;
1068 eth_dev->rx_pkt_burst = NULL;
1069 eth_dev->tx_pkt_burst = NULL;
1071 rte_free(eth_dev->data->mac_addrs);
1072 eth_dev->data->mac_addrs = NULL;
1074 /* disable uio intr before callback unregister */
1075 rte_intr_disable(&pci_dev->intr_handle);
1076 rte_intr_callback_unregister(&pci_dev->intr_handle,
1077 eth_igbvf_interrupt_handler,
1083 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1084 struct rte_pci_device *pci_dev)
1086 return rte_eth_dev_pci_generic_probe(pci_dev,
1087 sizeof(struct e1000_adapter), eth_igb_dev_init);
1090 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1092 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1095 static struct rte_pci_driver rte_igb_pmd = {
1096 .id_table = pci_id_igb_map,
1097 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1098 RTE_PCI_DRV_IOVA_AS_VA,
1099 .probe = eth_igb_pci_probe,
1100 .remove = eth_igb_pci_remove,
1104 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1105 struct rte_pci_device *pci_dev)
1107 return rte_eth_dev_pci_generic_probe(pci_dev,
1108 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1111 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1113 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1117 * virtual function driver struct
1119 static struct rte_pci_driver rte_igbvf_pmd = {
1120 .id_table = pci_id_igbvf_map,
1121 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1122 .probe = eth_igbvf_pci_probe,
1123 .remove = eth_igbvf_pci_remove,
1127 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1129 struct e1000_hw *hw =
1130 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1131 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1132 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1133 rctl |= E1000_RCTL_VFE;
1134 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1138 igb_check_mq_mode(struct rte_eth_dev *dev)
1140 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1141 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1142 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1143 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1145 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1146 tx_mq_mode == ETH_MQ_TX_DCB ||
1147 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1148 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1151 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1152 /* Check multi-queue mode.
1153 * To no break software we accept ETH_MQ_RX_NONE as this might
1154 * be used to turn off VLAN filter.
1157 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1158 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1159 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1160 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1162 /* Only support one queue on VFs.
1163 * RSS together with SRIOV is not supported.
1165 PMD_INIT_LOG(ERR, "SRIOV is active,"
1166 " wrong mq_mode rx %d.",
1170 /* TX mode is not used here, so mode might be ignored.*/
1171 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1172 /* SRIOV only works in VMDq enable mode */
1173 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1174 " TX mode %d is not supported. "
1175 " Driver will behave as %d mode.",
1176 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1179 /* check valid queue number */
1180 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1181 PMD_INIT_LOG(ERR, "SRIOV is active,"
1182 " only support one queue on VFs.");
1186 /* To no break software that set invalid mode, only display
1187 * warning if invalid mode is used.
1189 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1190 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1191 rx_mq_mode != ETH_MQ_RX_RSS) {
1192 /* RSS together with VMDq not supported*/
1193 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1198 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1199 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1200 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1201 " Due to txmode is meaningless in this"
1202 " driver, just ignore.",
1210 eth_igb_configure(struct rte_eth_dev *dev)
1212 struct e1000_interrupt *intr =
1213 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1216 PMD_INIT_FUNC_TRACE();
1218 /* multipe queue mode checking */
1219 ret = igb_check_mq_mode(dev);
1221 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1226 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1227 PMD_INIT_FUNC_TRACE();
1233 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1236 struct e1000_hw *hw =
1237 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1238 uint32_t tctl, rctl;
1240 tctl = E1000_READ_REG(hw, E1000_TCTL);
1241 rctl = E1000_READ_REG(hw, E1000_RCTL);
1245 tctl |= E1000_TCTL_EN;
1246 rctl |= E1000_RCTL_EN;
1249 tctl &= ~E1000_TCTL_EN;
1250 rctl &= ~E1000_RCTL_EN;
1252 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1253 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1254 E1000_WRITE_FLUSH(hw);
1258 eth_igb_start(struct rte_eth_dev *dev)
1260 struct e1000_hw *hw =
1261 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1262 struct e1000_adapter *adapter =
1263 E1000_DEV_PRIVATE(dev->data->dev_private);
1264 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1265 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1267 uint32_t intr_vector = 0;
1273 PMD_INIT_FUNC_TRACE();
1275 /* disable uio/vfio intr/eventfd mapping */
1276 rte_intr_disable(intr_handle);
1278 /* Power up the phy. Needed to make the link go Up */
1279 eth_igb_dev_set_link_up(dev);
1282 * Packet Buffer Allocation (PBA)
1283 * Writing PBA sets the receive portion of the buffer
1284 * the remainder is used for the transmit buffer.
1286 if (hw->mac.type == e1000_82575) {
1289 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1290 E1000_WRITE_REG(hw, E1000_PBA, pba);
1293 /* Put the address into the Receive Address Array */
1294 e1000_rar_set(hw, hw->mac.addr, 0);
1296 /* Initialize the hardware */
1297 if (igb_hardware_init(hw)) {
1298 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1301 adapter->stopped = 0;
1303 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1305 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1306 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1307 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1308 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1309 E1000_WRITE_FLUSH(hw);
1311 /* configure PF module if SRIOV enabled */
1312 igb_pf_host_configure(dev);
1314 /* check and configure queue intr-vector mapping */
1315 if ((rte_intr_cap_multiple(intr_handle) ||
1316 !RTE_ETH_DEV_SRIOV(dev).active) &&
1317 dev->data->dev_conf.intr_conf.rxq != 0) {
1318 intr_vector = dev->data->nb_rx_queues;
1319 if (rte_intr_efd_enable(intr_handle, intr_vector))
1323 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1324 intr_handle->intr_vec =
1325 rte_zmalloc("intr_vec",
1326 dev->data->nb_rx_queues * sizeof(int), 0);
1327 if (intr_handle->intr_vec == NULL) {
1328 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1329 " intr_vec", dev->data->nb_rx_queues);
1334 /* confiugre msix for rx interrupt */
1335 eth_igb_configure_msix_intr(dev);
1337 /* Configure for OS presence */
1338 igb_init_manageability(hw);
1340 eth_igb_tx_init(dev);
1342 /* This can fail when allocating mbufs for descriptor rings */
1343 ret = eth_igb_rx_init(dev);
1345 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1346 igb_dev_clear_queues(dev);
1350 e1000_clear_hw_cntrs_base_generic(hw);
1353 * VLAN Offload Settings
1355 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1356 ETH_VLAN_EXTEND_MASK;
1357 ret = eth_igb_vlan_offload_set(dev, mask);
1359 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1360 igb_dev_clear_queues(dev);
1364 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1365 /* Enable VLAN filter since VMDq always use VLAN filter */
1366 igb_vmdq_vlan_hw_filter_enable(dev);
1369 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1370 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1371 (hw->mac.type == e1000_i211)) {
1372 /* Configure EITR with the maximum possible value (0xFFFF) */
1373 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1376 /* Setup link speed and duplex */
1377 speeds = &dev->data->dev_conf.link_speeds;
1378 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1379 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1380 hw->mac.autoneg = 1;
1383 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1386 hw->phy.autoneg_advertised = 0;
1388 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1389 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1390 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1392 goto error_invalid_config;
1394 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1395 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1398 if (*speeds & ETH_LINK_SPEED_10M) {
1399 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1402 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1403 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1406 if (*speeds & ETH_LINK_SPEED_100M) {
1407 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1410 if (*speeds & ETH_LINK_SPEED_1G) {
1411 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1414 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1415 goto error_invalid_config;
1417 /* Set/reset the mac.autoneg based on the link speed,
1421 hw->mac.autoneg = 0;
1422 hw->mac.forced_speed_duplex =
1423 hw->phy.autoneg_advertised;
1425 hw->mac.autoneg = 1;
1429 e1000_setup_link(hw);
1431 if (rte_intr_allow_others(intr_handle)) {
1432 /* check if lsc interrupt is enabled */
1433 if (dev->data->dev_conf.intr_conf.lsc != 0)
1434 eth_igb_lsc_interrupt_setup(dev, TRUE);
1436 eth_igb_lsc_interrupt_setup(dev, FALSE);
1438 rte_intr_callback_unregister(intr_handle,
1439 eth_igb_interrupt_handler,
1441 if (dev->data->dev_conf.intr_conf.lsc != 0)
1442 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1443 " no intr multiplex");
1446 /* check if rxq interrupt is enabled */
1447 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1448 rte_intr_dp_is_en(intr_handle))
1449 eth_igb_rxq_interrupt_setup(dev);
1451 /* enable uio/vfio intr/eventfd mapping */
1452 rte_intr_enable(intr_handle);
1454 /* resume enabled intr since hw reset */
1455 igb_intr_enable(dev);
1457 /* restore all types filter */
1458 igb_filter_restore(dev);
1460 eth_igb_rxtx_control(dev, true);
1461 eth_igb_link_update(dev, 0);
1463 PMD_INIT_LOG(DEBUG, "<<");
1467 error_invalid_config:
1468 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1469 dev->data->dev_conf.link_speeds, dev->data->port_id);
1470 igb_dev_clear_queues(dev);
1474 /*********************************************************************
1476 * This routine disables all traffic on the adapter by issuing a
1477 * global reset on the MAC.
1479 **********************************************************************/
1481 eth_igb_stop(struct rte_eth_dev *dev)
1483 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1485 struct rte_eth_link link;
1486 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1488 eth_igb_rxtx_control(dev, false);
1490 igb_intr_disable(hw);
1492 /* disable intr eventfd mapping */
1493 rte_intr_disable(intr_handle);
1495 igb_pf_reset_hw(hw);
1496 E1000_WRITE_REG(hw, E1000_WUC, 0);
1498 /* Set bit for Go Link disconnect */
1499 if (hw->mac.type >= e1000_82580) {
1502 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1503 phpm_reg |= E1000_82580_PM_GO_LINKD;
1504 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1507 /* Power down the phy. Needed to make the link go Down */
1508 eth_igb_dev_set_link_down(dev);
1510 igb_dev_clear_queues(dev);
1512 /* clear the recorded link status */
1513 memset(&link, 0, sizeof(link));
1514 rte_eth_linkstatus_set(dev, &link);
1516 if (!rte_intr_allow_others(intr_handle))
1517 /* resume to the default handler */
1518 rte_intr_callback_register(intr_handle,
1519 eth_igb_interrupt_handler,
1522 /* Clean datapath event and queue/vec mapping */
1523 rte_intr_efd_disable(intr_handle);
1524 if (intr_handle->intr_vec != NULL) {
1525 rte_free(intr_handle->intr_vec);
1526 intr_handle->intr_vec = NULL;
1531 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1533 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1535 if (hw->phy.media_type == e1000_media_type_copper)
1536 e1000_power_up_phy(hw);
1538 e1000_power_up_fiber_serdes_link(hw);
1544 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1546 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1548 if (hw->phy.media_type == e1000_media_type_copper)
1549 e1000_power_down_phy(hw);
1551 e1000_shutdown_fiber_serdes_link(hw);
1557 eth_igb_close(struct rte_eth_dev *dev)
1559 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560 struct e1000_adapter *adapter =
1561 E1000_DEV_PRIVATE(dev->data->dev_private);
1562 struct rte_eth_link link;
1563 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1564 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1567 adapter->stopped = 1;
1569 e1000_phy_hw_reset(hw);
1570 igb_release_manageability(hw);
1571 igb_hw_control_release(hw);
1573 /* Clear bit for Go Link disconnect */
1574 if (hw->mac.type >= e1000_82580) {
1577 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1578 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1579 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1582 igb_dev_free_queues(dev);
1584 if (intr_handle->intr_vec) {
1585 rte_free(intr_handle->intr_vec);
1586 intr_handle->intr_vec = NULL;
1589 memset(&link, 0, sizeof(link));
1590 rte_eth_linkstatus_set(dev, &link);
1594 igb_get_rx_buffer_size(struct e1000_hw *hw)
1596 uint32_t rx_buf_size;
1597 if (hw->mac.type == e1000_82576) {
1598 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1599 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1600 /* PBS needs to be translated according to a lookup table */
1601 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1602 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1603 rx_buf_size = (rx_buf_size << 10);
1604 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1605 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1607 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1613 /*********************************************************************
1615 * Initialize the hardware
1617 **********************************************************************/
1619 igb_hardware_init(struct e1000_hw *hw)
1621 uint32_t rx_buf_size;
1624 /* Let the firmware know the OS is in control */
1625 igb_hw_control_acquire(hw);
1628 * These parameters control the automatic generation (Tx) and
1629 * response (Rx) to Ethernet PAUSE frames.
1630 * - High water mark should allow for at least two standard size (1518)
1631 * frames to be received after sending an XOFF.
1632 * - Low water mark works best when it is very near the high water mark.
1633 * This allows the receiver to restart by sending XON when it has
1634 * drained a bit. Here we use an arbitrary value of 1500 which will
1635 * restart after one full frame is pulled from the buffer. There
1636 * could be several smaller frames in the buffer and if so they will
1637 * not trigger the XON until their total number reduces the buffer
1639 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1641 rx_buf_size = igb_get_rx_buffer_size(hw);
1643 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1644 hw->fc.low_water = hw->fc.high_water - 1500;
1645 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1646 hw->fc.send_xon = 1;
1648 /* Set Flow control, use the tunable location if sane */
1649 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1650 hw->fc.requested_mode = igb_fc_setting;
1652 hw->fc.requested_mode = e1000_fc_none;
1654 /* Issue a global reset */
1655 igb_pf_reset_hw(hw);
1656 E1000_WRITE_REG(hw, E1000_WUC, 0);
1658 diag = e1000_init_hw(hw);
1662 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1663 e1000_get_phy_info(hw);
1664 e1000_check_for_link(hw);
1669 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1671 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1675 uint64_t old_gprc = stats->gprc;
1676 uint64_t old_gptc = stats->gptc;
1677 uint64_t old_tpr = stats->tpr;
1678 uint64_t old_tpt = stats->tpt;
1679 uint64_t old_rpthc = stats->rpthc;
1680 uint64_t old_hgptc = stats->hgptc;
1682 if(hw->phy.media_type == e1000_media_type_copper ||
1683 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1685 E1000_READ_REG(hw,E1000_SYMERRS);
1686 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1689 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1690 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1691 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1692 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1694 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1695 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1696 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1697 stats->dc += E1000_READ_REG(hw, E1000_DC);
1698 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1699 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1700 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1702 ** For watchdog management we need to know if we have been
1703 ** paused during the last interval, so capture that here.
1705 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1706 stats->xoffrxc += pause_frames;
1707 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1708 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1709 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1710 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1711 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1712 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1713 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1714 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1715 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1716 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1717 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1718 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1720 /* For the 64-bit byte counters the low dword must be read first. */
1721 /* Both registers clear on the read of the high dword */
1723 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1724 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1725 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1726 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1727 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1728 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1729 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1731 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1732 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1733 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1734 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1735 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1737 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1738 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1740 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1741 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1742 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1743 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1744 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1745 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1747 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1748 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1749 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1750 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1751 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1752 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1753 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1754 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1756 /* Interrupt Counts */
1758 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1759 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1760 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1761 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1762 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1763 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1764 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1765 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1766 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1768 /* Host to Card Statistics */
1770 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1771 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1772 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1773 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1774 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1775 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1776 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1777 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1778 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1779 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1780 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1781 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1782 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1783 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1784 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1785 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1787 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1788 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1789 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1790 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1791 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1792 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1796 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1798 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1799 struct e1000_hw_stats *stats =
1800 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1802 igb_read_stats_registers(hw, stats);
1804 if (rte_stats == NULL)
1808 rte_stats->imissed = stats->mpc;
1809 rte_stats->ierrors = stats->crcerrs +
1810 stats->rlec + stats->ruc + stats->roc +
1811 stats->rxerrc + stats->algnerrc + stats->cexterr;
1814 rte_stats->oerrors = stats->ecol + stats->latecol;
1816 rte_stats->ipackets = stats->gprc;
1817 rte_stats->opackets = stats->gptc;
1818 rte_stats->ibytes = stats->gorc;
1819 rte_stats->obytes = stats->gotc;
1824 eth_igb_stats_reset(struct rte_eth_dev *dev)
1826 struct e1000_hw_stats *hw_stats =
1827 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1829 /* HW registers are cleared on read */
1830 eth_igb_stats_get(dev, NULL);
1832 /* Reset software totals */
1833 memset(hw_stats, 0, sizeof(*hw_stats));
1837 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1839 struct e1000_hw_stats *stats =
1840 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1842 /* HW registers are cleared on read */
1843 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1845 /* Reset software totals */
1846 memset(stats, 0, sizeof(*stats));
1849 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1850 struct rte_eth_xstat_name *xstats_names,
1851 __rte_unused unsigned int size)
1855 if (xstats_names == NULL)
1856 return IGB_NB_XSTATS;
1858 /* Note: limit checked in rte_eth_xstats_names() */
1860 for (i = 0; i < IGB_NB_XSTATS; i++) {
1861 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1862 "%s", rte_igb_stats_strings[i].name);
1865 return IGB_NB_XSTATS;
1868 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1869 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1875 if (xstats_names == NULL)
1876 return IGB_NB_XSTATS;
1878 for (i = 0; i < IGB_NB_XSTATS; i++)
1879 snprintf(xstats_names[i].name,
1880 sizeof(xstats_names[i].name),
1881 "%s", rte_igb_stats_strings[i].name);
1883 return IGB_NB_XSTATS;
1886 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1888 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1891 for (i = 0; i < limit; i++) {
1892 if (ids[i] >= IGB_NB_XSTATS) {
1893 PMD_INIT_LOG(ERR, "id value isn't valid");
1896 strcpy(xstats_names[i].name,
1897 xstats_names_copy[ids[i]].name);
1904 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1907 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908 struct e1000_hw_stats *hw_stats =
1909 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1912 if (n < IGB_NB_XSTATS)
1913 return IGB_NB_XSTATS;
1915 igb_read_stats_registers(hw, hw_stats);
1917 /* If this is a reset xstats is NULL, and we have cleared the
1918 * registers by reading them.
1923 /* Extended stats */
1924 for (i = 0; i < IGB_NB_XSTATS; i++) {
1926 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1927 rte_igb_stats_strings[i].offset);
1930 return IGB_NB_XSTATS;
1934 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1935 uint64_t *values, unsigned int n)
1940 struct e1000_hw *hw =
1941 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942 struct e1000_hw_stats *hw_stats =
1943 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1945 if (n < IGB_NB_XSTATS)
1946 return IGB_NB_XSTATS;
1948 igb_read_stats_registers(hw, hw_stats);
1950 /* If this is a reset xstats is NULL, and we have cleared the
1951 * registers by reading them.
1956 /* Extended stats */
1957 for (i = 0; i < IGB_NB_XSTATS; i++)
1958 values[i] = *(uint64_t *)(((char *)hw_stats) +
1959 rte_igb_stats_strings[i].offset);
1961 return IGB_NB_XSTATS;
1964 uint64_t values_copy[IGB_NB_XSTATS];
1966 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1969 for (i = 0; i < n; i++) {
1970 if (ids[i] >= IGB_NB_XSTATS) {
1971 PMD_INIT_LOG(ERR, "id value isn't valid");
1974 values[i] = values_copy[ids[i]];
1981 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1983 /* Good Rx packets, include VF loopback */
1984 UPDATE_VF_STAT(E1000_VFGPRC,
1985 hw_stats->last_gprc, hw_stats->gprc);
1987 /* Good Rx octets, include VF loopback */
1988 UPDATE_VF_STAT(E1000_VFGORC,
1989 hw_stats->last_gorc, hw_stats->gorc);
1991 /* Good Tx packets, include VF loopback */
1992 UPDATE_VF_STAT(E1000_VFGPTC,
1993 hw_stats->last_gptc, hw_stats->gptc);
1995 /* Good Tx octets, include VF loopback */
1996 UPDATE_VF_STAT(E1000_VFGOTC,
1997 hw_stats->last_gotc, hw_stats->gotc);
1999 /* Rx Multicst packets */
2000 UPDATE_VF_STAT(E1000_VFMPRC,
2001 hw_stats->last_mprc, hw_stats->mprc);
2003 /* Good Rx loopback packets */
2004 UPDATE_VF_STAT(E1000_VFGPRLBC,
2005 hw_stats->last_gprlbc, hw_stats->gprlbc);
2007 /* Good Rx loopback octets */
2008 UPDATE_VF_STAT(E1000_VFGORLBC,
2009 hw_stats->last_gorlbc, hw_stats->gorlbc);
2011 /* Good Tx loopback packets */
2012 UPDATE_VF_STAT(E1000_VFGPTLBC,
2013 hw_stats->last_gptlbc, hw_stats->gptlbc);
2015 /* Good Tx loopback octets */
2016 UPDATE_VF_STAT(E1000_VFGOTLBC,
2017 hw_stats->last_gotlbc, hw_stats->gotlbc);
2020 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2021 struct rte_eth_xstat_name *xstats_names,
2022 __rte_unused unsigned limit)
2026 if (xstats_names != NULL)
2027 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2028 snprintf(xstats_names[i].name,
2029 sizeof(xstats_names[i].name), "%s",
2030 rte_igbvf_stats_strings[i].name);
2032 return IGBVF_NB_XSTATS;
2036 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2039 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2040 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2041 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2044 if (n < IGBVF_NB_XSTATS)
2045 return IGBVF_NB_XSTATS;
2047 igbvf_read_stats_registers(hw, hw_stats);
2052 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2054 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2055 rte_igbvf_stats_strings[i].offset);
2058 return IGBVF_NB_XSTATS;
2062 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2064 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2066 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2068 igbvf_read_stats_registers(hw, hw_stats);
2070 if (rte_stats == NULL)
2073 rte_stats->ipackets = hw_stats->gprc;
2074 rte_stats->ibytes = hw_stats->gorc;
2075 rte_stats->opackets = hw_stats->gptc;
2076 rte_stats->obytes = hw_stats->gotc;
2081 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2083 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2084 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2086 /* Sync HW register to the last stats */
2087 eth_igbvf_stats_get(dev, NULL);
2089 /* reset HW current stats*/
2090 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2091 offsetof(struct e1000_vf_stats, gprc));
2095 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2098 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099 struct e1000_fw_version fw;
2102 e1000_get_fw_version(hw, &fw);
2104 switch (hw->mac.type) {
2107 if (!(e1000_get_flash_presence_i210(hw))) {
2108 ret = snprintf(fw_version, fw_size,
2110 fw.invm_major, fw.invm_minor,
2116 /* if option rom is valid, display its version too */
2118 ret = snprintf(fw_version, fw_size,
2119 "%d.%d, 0x%08x, %d.%d.%d",
2120 fw.eep_major, fw.eep_minor, fw.etrack_id,
2121 fw.or_major, fw.or_build, fw.or_patch);
2124 if (fw.etrack_id != 0X0000) {
2125 ret = snprintf(fw_version, fw_size,
2127 fw.eep_major, fw.eep_minor,
2130 ret = snprintf(fw_version, fw_size,
2132 fw.eep_major, fw.eep_minor,
2139 ret += 1; /* add the size of '\0' */
2140 if (fw_size < (u32)ret)
2147 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2149 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2152 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2153 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2154 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2155 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2156 dev_info->rx_queue_offload_capa;
2157 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2158 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2159 dev_info->tx_queue_offload_capa;
2161 switch (hw->mac.type) {
2163 dev_info->max_rx_queues = 4;
2164 dev_info->max_tx_queues = 4;
2165 dev_info->max_vmdq_pools = 0;
2169 dev_info->max_rx_queues = 16;
2170 dev_info->max_tx_queues = 16;
2171 dev_info->max_vmdq_pools = ETH_8_POOLS;
2172 dev_info->vmdq_queue_num = 16;
2176 dev_info->max_rx_queues = 8;
2177 dev_info->max_tx_queues = 8;
2178 dev_info->max_vmdq_pools = ETH_8_POOLS;
2179 dev_info->vmdq_queue_num = 8;
2183 dev_info->max_rx_queues = 8;
2184 dev_info->max_tx_queues = 8;
2185 dev_info->max_vmdq_pools = ETH_8_POOLS;
2186 dev_info->vmdq_queue_num = 8;
2190 dev_info->max_rx_queues = 8;
2191 dev_info->max_tx_queues = 8;
2195 dev_info->max_rx_queues = 4;
2196 dev_info->max_tx_queues = 4;
2197 dev_info->max_vmdq_pools = 0;
2201 dev_info->max_rx_queues = 2;
2202 dev_info->max_tx_queues = 2;
2203 dev_info->max_vmdq_pools = 0;
2207 /* Should not happen */
2210 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2211 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2212 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2214 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2216 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2217 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2218 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2220 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2225 dev_info->default_txconf = (struct rte_eth_txconf) {
2227 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2228 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2229 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2235 dev_info->rx_desc_lim = rx_desc_lim;
2236 dev_info->tx_desc_lim = tx_desc_lim;
2238 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2239 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2243 static const uint32_t *
2244 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2246 static const uint32_t ptypes[] = {
2247 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2250 RTE_PTYPE_L3_IPV4_EXT,
2252 RTE_PTYPE_L3_IPV6_EXT,
2256 RTE_PTYPE_TUNNEL_IP,
2257 RTE_PTYPE_INNER_L3_IPV6,
2258 RTE_PTYPE_INNER_L3_IPV6_EXT,
2259 RTE_PTYPE_INNER_L4_TCP,
2260 RTE_PTYPE_INNER_L4_UDP,
2264 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2265 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2271 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2273 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2276 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2277 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2278 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2279 DEV_TX_OFFLOAD_IPV4_CKSUM |
2280 DEV_TX_OFFLOAD_UDP_CKSUM |
2281 DEV_TX_OFFLOAD_TCP_CKSUM |
2282 DEV_TX_OFFLOAD_SCTP_CKSUM |
2283 DEV_TX_OFFLOAD_TCP_TSO;
2284 switch (hw->mac.type) {
2286 dev_info->max_rx_queues = 2;
2287 dev_info->max_tx_queues = 2;
2289 case e1000_vfadapt_i350:
2290 dev_info->max_rx_queues = 1;
2291 dev_info->max_tx_queues = 1;
2294 /* Should not happen */
2298 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2299 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2300 dev_info->rx_queue_offload_capa;
2301 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2302 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2303 dev_info->tx_queue_offload_capa;
2305 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2307 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2308 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2309 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2311 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2316 dev_info->default_txconf = (struct rte_eth_txconf) {
2318 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2319 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2320 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2326 dev_info->rx_desc_lim = rx_desc_lim;
2327 dev_info->tx_desc_lim = tx_desc_lim;
2330 /* return 0 means link status changed, -1 means not changed */
2332 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2334 struct e1000_hw *hw =
2335 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336 struct rte_eth_link link;
2337 int link_check, count;
2340 hw->mac.get_link_status = 1;
2342 /* possible wait-to-complete in up to 9 seconds */
2343 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2344 /* Read the real link status */
2345 switch (hw->phy.media_type) {
2346 case e1000_media_type_copper:
2347 /* Do the work to read phy */
2348 e1000_check_for_link(hw);
2349 link_check = !hw->mac.get_link_status;
2352 case e1000_media_type_fiber:
2353 e1000_check_for_link(hw);
2354 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2358 case e1000_media_type_internal_serdes:
2359 e1000_check_for_link(hw);
2360 link_check = hw->mac.serdes_has_link;
2363 /* VF device is type_unknown */
2364 case e1000_media_type_unknown:
2365 eth_igbvf_link_update(hw);
2366 link_check = !hw->mac.get_link_status;
2372 if (link_check || wait_to_complete == 0)
2374 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2376 memset(&link, 0, sizeof(link));
2378 /* Now we check if a transition has happened */
2380 uint16_t duplex, speed;
2381 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2382 link.link_duplex = (duplex == FULL_DUPLEX) ?
2383 ETH_LINK_FULL_DUPLEX :
2384 ETH_LINK_HALF_DUPLEX;
2385 link.link_speed = speed;
2386 link.link_status = ETH_LINK_UP;
2387 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2388 ETH_LINK_SPEED_FIXED);
2389 } else if (!link_check) {
2390 link.link_speed = 0;
2391 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2392 link.link_status = ETH_LINK_DOWN;
2393 link.link_autoneg = ETH_LINK_FIXED;
2396 return rte_eth_linkstatus_set(dev, &link);
2400 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2401 * For ASF and Pass Through versions of f/w this means
2402 * that the driver is loaded.
2405 igb_hw_control_acquire(struct e1000_hw *hw)
2409 /* Let firmware know the driver has taken over */
2410 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2411 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2415 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2416 * For ASF and Pass Through versions of f/w this means that the
2417 * driver is no longer loaded.
2420 igb_hw_control_release(struct e1000_hw *hw)
2424 /* Let firmware taken over control of h/w */
2425 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2426 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2427 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2431 * Bit of a misnomer, what this really means is
2432 * to enable OS management of the system... aka
2433 * to disable special hardware management features.
2436 igb_init_manageability(struct e1000_hw *hw)
2438 if (e1000_enable_mng_pass_thru(hw)) {
2439 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2440 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2442 /* disable hardware interception of ARP */
2443 manc &= ~(E1000_MANC_ARP_EN);
2445 /* enable receiving management packets to the host */
2446 manc |= E1000_MANC_EN_MNG2HOST;
2447 manc2h |= 1 << 5; /* Mng Port 623 */
2448 manc2h |= 1 << 6; /* Mng Port 664 */
2449 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2450 E1000_WRITE_REG(hw, E1000_MANC, manc);
2455 igb_release_manageability(struct e1000_hw *hw)
2457 if (e1000_enable_mng_pass_thru(hw)) {
2458 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2460 manc |= E1000_MANC_ARP_EN;
2461 manc &= ~E1000_MANC_EN_MNG2HOST;
2463 E1000_WRITE_REG(hw, E1000_MANC, manc);
2468 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2470 struct e1000_hw *hw =
2471 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2474 rctl = E1000_READ_REG(hw, E1000_RCTL);
2475 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2476 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2480 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2482 struct e1000_hw *hw =
2483 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486 rctl = E1000_READ_REG(hw, E1000_RCTL);
2487 rctl &= (~E1000_RCTL_UPE);
2488 if (dev->data->all_multicast == 1)
2489 rctl |= E1000_RCTL_MPE;
2491 rctl &= (~E1000_RCTL_MPE);
2492 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2496 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2498 struct e1000_hw *hw =
2499 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2502 rctl = E1000_READ_REG(hw, E1000_RCTL);
2503 rctl |= E1000_RCTL_MPE;
2504 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2508 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2510 struct e1000_hw *hw =
2511 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2514 if (dev->data->promiscuous == 1)
2515 return; /* must remain in all_multicast mode */
2516 rctl = E1000_READ_REG(hw, E1000_RCTL);
2517 rctl &= (~E1000_RCTL_MPE);
2518 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2522 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2524 struct e1000_hw *hw =
2525 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526 struct e1000_vfta * shadow_vfta =
2527 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2532 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2533 E1000_VFTA_ENTRY_MASK);
2534 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2535 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2540 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2542 /* update local VFTA copy */
2543 shadow_vfta->vfta[vid_idx] = vfta;
2549 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2550 enum rte_vlan_type vlan_type,
2553 struct e1000_hw *hw =
2554 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2557 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2558 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2560 /* only outer TPID of double VLAN can be configured*/
2561 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2562 reg = E1000_READ_REG(hw, E1000_VET);
2563 reg = (reg & (~E1000_VET_VET_EXT)) |
2564 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2565 E1000_WRITE_REG(hw, E1000_VET, reg);
2570 /* all other TPID values are read-only*/
2571 PMD_DRV_LOG(ERR, "Not supported");
2577 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2579 struct e1000_hw *hw =
2580 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2583 /* Filter Table Disable */
2584 reg = E1000_READ_REG(hw, E1000_RCTL);
2585 reg &= ~E1000_RCTL_CFIEN;
2586 reg &= ~E1000_RCTL_VFE;
2587 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2591 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2593 struct e1000_hw *hw =
2594 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2595 struct e1000_vfta * shadow_vfta =
2596 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2600 /* Filter Table Enable, CFI not used for packet acceptance */
2601 reg = E1000_READ_REG(hw, E1000_RCTL);
2602 reg &= ~E1000_RCTL_CFIEN;
2603 reg |= E1000_RCTL_VFE;
2604 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2606 /* restore VFTA table */
2607 for (i = 0; i < IGB_VFTA_SIZE; i++)
2608 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2612 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2614 struct e1000_hw *hw =
2615 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618 /* VLAN Mode Disable */
2619 reg = E1000_READ_REG(hw, E1000_CTRL);
2620 reg &= ~E1000_CTRL_VME;
2621 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2625 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2627 struct e1000_hw *hw =
2628 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631 /* VLAN Mode Enable */
2632 reg = E1000_READ_REG(hw, E1000_CTRL);
2633 reg |= E1000_CTRL_VME;
2634 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2638 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2640 struct e1000_hw *hw =
2641 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2644 /* CTRL_EXT: Extended VLAN */
2645 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2646 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2647 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2649 /* Update maximum packet length */
2650 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2651 E1000_WRITE_REG(hw, E1000_RLPML,
2652 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2657 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2659 struct e1000_hw *hw =
2660 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2663 /* CTRL_EXT: Extended VLAN */
2664 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2665 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2666 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2668 /* Update maximum packet length */
2669 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2670 E1000_WRITE_REG(hw, E1000_RLPML,
2671 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2676 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2678 struct rte_eth_rxmode *rxmode;
2680 rxmode = &dev->data->dev_conf.rxmode;
2681 if(mask & ETH_VLAN_STRIP_MASK){
2682 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2683 igb_vlan_hw_strip_enable(dev);
2685 igb_vlan_hw_strip_disable(dev);
2688 if(mask & ETH_VLAN_FILTER_MASK){
2689 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2690 igb_vlan_hw_filter_enable(dev);
2692 igb_vlan_hw_filter_disable(dev);
2695 if(mask & ETH_VLAN_EXTEND_MASK){
2696 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2697 igb_vlan_hw_extend_enable(dev);
2699 igb_vlan_hw_extend_disable(dev);
2707 * It enables the interrupt mask and then enable the interrupt.
2710 * Pointer to struct rte_eth_dev.
2715 * - On success, zero.
2716 * - On failure, a negative value.
2719 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2721 struct e1000_interrupt *intr =
2722 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2725 intr->mask |= E1000_ICR_LSC;
2727 intr->mask &= ~E1000_ICR_LSC;
2732 /* It clears the interrupt causes and enables the interrupt.
2733 * It will be called once only during nic initialized.
2736 * Pointer to struct rte_eth_dev.
2739 * - On success, zero.
2740 * - On failure, a negative value.
2742 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2744 uint32_t mask, regval;
2745 struct e1000_hw *hw =
2746 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2747 struct rte_eth_dev_info dev_info;
2749 memset(&dev_info, 0, sizeof(dev_info));
2750 eth_igb_infos_get(dev, &dev_info);
2752 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2753 regval = E1000_READ_REG(hw, E1000_EIMS);
2754 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2760 * It reads ICR and gets interrupt causes, check it and set a bit flag
2761 * to update link status.
2764 * Pointer to struct rte_eth_dev.
2767 * - On success, zero.
2768 * - On failure, a negative value.
2771 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2774 struct e1000_hw *hw =
2775 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2776 struct e1000_interrupt *intr =
2777 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2779 igb_intr_disable(hw);
2781 /* read-on-clear nic registers here */
2782 icr = E1000_READ_REG(hw, E1000_ICR);
2785 if (icr & E1000_ICR_LSC) {
2786 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2789 if (icr & E1000_ICR_VMMB)
2790 intr->flags |= E1000_FLAG_MAILBOX;
2796 * It executes link_update after knowing an interrupt is prsent.
2799 * Pointer to struct rte_eth_dev.
2802 * - On success, zero.
2803 * - On failure, a negative value.
2806 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2807 struct rte_intr_handle *intr_handle)
2809 struct e1000_hw *hw =
2810 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811 struct e1000_interrupt *intr =
2812 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2813 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2814 struct rte_eth_link link;
2817 if (intr->flags & E1000_FLAG_MAILBOX) {
2818 igb_pf_mbx_process(dev);
2819 intr->flags &= ~E1000_FLAG_MAILBOX;
2822 igb_intr_enable(dev);
2823 rte_intr_enable(intr_handle);
2825 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2826 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2828 /* set get_link_status to check register later */
2829 hw->mac.get_link_status = 1;
2830 ret = eth_igb_link_update(dev, 0);
2832 /* check if link has changed */
2836 rte_eth_linkstatus_get(dev, &link);
2837 if (link.link_status) {
2839 " Port %d: Link Up - speed %u Mbps - %s",
2841 (unsigned)link.link_speed,
2842 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2843 "full-duplex" : "half-duplex");
2845 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2846 dev->data->port_id);
2849 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2850 pci_dev->addr.domain,
2852 pci_dev->addr.devid,
2853 pci_dev->addr.function);
2854 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2862 * Interrupt handler which shall be registered at first.
2865 * Pointer to interrupt handle.
2867 * The address of parameter (struct rte_eth_dev *) regsitered before.
2873 eth_igb_interrupt_handler(void *param)
2875 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2877 eth_igb_interrupt_get_status(dev);
2878 eth_igb_interrupt_action(dev, dev->intr_handle);
2882 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2885 struct e1000_hw *hw =
2886 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2887 struct e1000_interrupt *intr =
2888 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2890 igbvf_intr_disable(hw);
2892 /* read-on-clear nic registers here */
2893 eicr = E1000_READ_REG(hw, E1000_EICR);
2896 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2897 intr->flags |= E1000_FLAG_MAILBOX;
2902 void igbvf_mbx_process(struct rte_eth_dev *dev)
2904 struct e1000_hw *hw =
2905 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2906 struct e1000_mbx_info *mbx = &hw->mbx;
2909 /* peek the message first */
2910 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2912 /* PF reset VF event */
2913 if (in_msg == E1000_PF_CONTROL_MSG) {
2914 /* dummy mbx read to ack pf */
2915 if (mbx->ops.read(hw, &in_msg, 1, 0))
2917 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2923 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2925 struct e1000_interrupt *intr =
2926 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2928 if (intr->flags & E1000_FLAG_MAILBOX) {
2929 igbvf_mbx_process(dev);
2930 intr->flags &= ~E1000_FLAG_MAILBOX;
2933 igbvf_intr_enable(dev);
2934 rte_intr_enable(intr_handle);
2940 eth_igbvf_interrupt_handler(void *param)
2942 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2944 eth_igbvf_interrupt_get_status(dev);
2945 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2949 eth_igb_led_on(struct rte_eth_dev *dev)
2951 struct e1000_hw *hw;
2953 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2954 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2958 eth_igb_led_off(struct rte_eth_dev *dev)
2960 struct e1000_hw *hw;
2962 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2963 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2967 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2969 struct e1000_hw *hw;
2974 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2975 fc_conf->pause_time = hw->fc.pause_time;
2976 fc_conf->high_water = hw->fc.high_water;
2977 fc_conf->low_water = hw->fc.low_water;
2978 fc_conf->send_xon = hw->fc.send_xon;
2979 fc_conf->autoneg = hw->mac.autoneg;
2982 * Return rx_pause and tx_pause status according to actual setting of
2983 * the TFCE and RFCE bits in the CTRL register.
2985 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2986 if (ctrl & E1000_CTRL_TFCE)
2991 if (ctrl & E1000_CTRL_RFCE)
2996 if (rx_pause && tx_pause)
2997 fc_conf->mode = RTE_FC_FULL;
2999 fc_conf->mode = RTE_FC_RX_PAUSE;
3001 fc_conf->mode = RTE_FC_TX_PAUSE;
3003 fc_conf->mode = RTE_FC_NONE;
3009 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3011 struct e1000_hw *hw;
3013 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3019 uint32_t rx_buf_size;
3020 uint32_t max_high_water;
3023 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3024 if (fc_conf->autoneg != hw->mac.autoneg)
3026 rx_buf_size = igb_get_rx_buffer_size(hw);
3027 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3029 /* At least reserve one Ethernet frame for watermark */
3030 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3031 if ((fc_conf->high_water > max_high_water) ||
3032 (fc_conf->high_water < fc_conf->low_water)) {
3033 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3034 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3038 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3039 hw->fc.pause_time = fc_conf->pause_time;
3040 hw->fc.high_water = fc_conf->high_water;
3041 hw->fc.low_water = fc_conf->low_water;
3042 hw->fc.send_xon = fc_conf->send_xon;
3044 err = e1000_setup_link_generic(hw);
3045 if (err == E1000_SUCCESS) {
3047 /* check if we want to forward MAC frames - driver doesn't have native
3048 * capability to do that, so we'll write the registers ourselves */
3050 rctl = E1000_READ_REG(hw, E1000_RCTL);
3052 /* set or clear MFLCN.PMCF bit depending on configuration */
3053 if (fc_conf->mac_ctrl_frame_fwd != 0)
3054 rctl |= E1000_RCTL_PMCF;
3056 rctl &= ~E1000_RCTL_PMCF;
3058 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3059 E1000_WRITE_FLUSH(hw);
3064 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3068 #define E1000_RAH_POOLSEL_SHIFT (18)
3070 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3071 uint32_t index, uint32_t pool)
3073 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3077 rah = E1000_READ_REG(hw, E1000_RAH(index));
3078 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3079 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3084 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3086 uint8_t addr[ETHER_ADDR_LEN];
3087 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3089 memset(addr, 0, sizeof(addr));
3091 e1000_rar_set(hw, addr, index);
3095 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3096 struct ether_addr *addr)
3098 eth_igb_rar_clear(dev, 0);
3099 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3104 * Virtual Function operations
3107 igbvf_intr_disable(struct e1000_hw *hw)
3109 PMD_INIT_FUNC_TRACE();
3111 /* Clear interrupt mask to stop from interrupts being generated */
3112 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3114 E1000_WRITE_FLUSH(hw);
3118 igbvf_stop_adapter(struct rte_eth_dev *dev)
3122 struct rte_eth_dev_info dev_info;
3123 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3125 memset(&dev_info, 0, sizeof(dev_info));
3126 eth_igbvf_infos_get(dev, &dev_info);
3128 /* Clear interrupt mask to stop from interrupts being generated */
3129 igbvf_intr_disable(hw);
3131 /* Clear any pending interrupts, flush previous writes */
3132 E1000_READ_REG(hw, E1000_EICR);
3134 /* Disable the transmit unit. Each queue must be disabled. */
3135 for (i = 0; i < dev_info.max_tx_queues; i++)
3136 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3138 /* Disable the receive unit by stopping each queue */
3139 for (i = 0; i < dev_info.max_rx_queues; i++) {
3140 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3141 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3142 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3143 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3147 /* flush all queues disables */
3148 E1000_WRITE_FLUSH(hw);
3152 static int eth_igbvf_link_update(struct e1000_hw *hw)
3154 struct e1000_mbx_info *mbx = &hw->mbx;
3155 struct e1000_mac_info *mac = &hw->mac;
3156 int ret_val = E1000_SUCCESS;
3158 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3161 * We only want to run this if there has been a rst asserted.
3162 * in this case that could mean a link change, device reset,
3163 * or a virtual function reset
3166 /* If we were hit with a reset or timeout drop the link */
3167 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3168 mac->get_link_status = TRUE;
3170 if (!mac->get_link_status)
3173 /* if link status is down no point in checking to see if pf is up */
3174 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3177 /* if we passed all the tests above then the link is up and we no
3178 * longer need to check for link */
3179 mac->get_link_status = FALSE;
3187 igbvf_dev_configure(struct rte_eth_dev *dev)
3189 struct rte_eth_conf* conf = &dev->data->dev_conf;
3191 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3192 dev->data->port_id);
3195 * VF has no ability to enable/disable HW CRC
3196 * Keep the persistent behavior the same as Host PF
3198 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3199 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
3200 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3201 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
3204 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
3205 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3206 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
3214 igbvf_dev_start(struct rte_eth_dev *dev)
3216 struct e1000_hw *hw =
3217 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3218 struct e1000_adapter *adapter =
3219 E1000_DEV_PRIVATE(dev->data->dev_private);
3220 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3221 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3223 uint32_t intr_vector = 0;
3225 PMD_INIT_FUNC_TRACE();
3227 hw->mac.ops.reset_hw(hw);
3228 adapter->stopped = 0;
3231 igbvf_set_vfta_all(dev,1);
3233 eth_igbvf_tx_init(dev);
3235 /* This can fail when allocating mbufs for descriptor rings */
3236 ret = eth_igbvf_rx_init(dev);
3238 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3239 igb_dev_clear_queues(dev);
3243 /* check and configure queue intr-vector mapping */
3244 if (rte_intr_cap_multiple(intr_handle) &&
3245 dev->data->dev_conf.intr_conf.rxq) {
3246 intr_vector = dev->data->nb_rx_queues;
3247 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3252 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3253 intr_handle->intr_vec =
3254 rte_zmalloc("intr_vec",
3255 dev->data->nb_rx_queues * sizeof(int), 0);
3256 if (!intr_handle->intr_vec) {
3257 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3258 " intr_vec", dev->data->nb_rx_queues);
3263 eth_igbvf_configure_msix_intr(dev);
3265 /* enable uio/vfio intr/eventfd mapping */
3266 rte_intr_enable(intr_handle);
3268 /* resume enabled intr since hw reset */
3269 igbvf_intr_enable(dev);
3275 igbvf_dev_stop(struct rte_eth_dev *dev)
3277 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3278 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3280 PMD_INIT_FUNC_TRACE();
3282 igbvf_stop_adapter(dev);
3285 * Clear what we set, but we still keep shadow_vfta to
3286 * restore after device starts
3288 igbvf_set_vfta_all(dev,0);
3290 igb_dev_clear_queues(dev);
3292 /* disable intr eventfd mapping */
3293 rte_intr_disable(intr_handle);
3295 /* Clean datapath event and queue/vec mapping */
3296 rte_intr_efd_disable(intr_handle);
3297 if (intr_handle->intr_vec) {
3298 rte_free(intr_handle->intr_vec);
3299 intr_handle->intr_vec = NULL;
3304 igbvf_dev_close(struct rte_eth_dev *dev)
3306 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307 struct e1000_adapter *adapter =
3308 E1000_DEV_PRIVATE(dev->data->dev_private);
3309 struct ether_addr addr;
3311 PMD_INIT_FUNC_TRACE();
3315 igbvf_dev_stop(dev);
3316 adapter->stopped = 1;
3317 igb_dev_free_queues(dev);
3320 * reprogram the RAR with a zero mac address,
3321 * to ensure that the VF traffic goes to the PF
3322 * after stop, close and detach of the VF.
3325 memset(&addr, 0, sizeof(addr));
3326 igbvf_default_mac_addr_set(dev, &addr);
3330 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3332 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3334 /* Set both unicast and multicast promisc */
3335 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3339 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3341 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3343 /* If in allmulticast mode leave multicast promisc */
3344 if (dev->data->all_multicast == 1)
3345 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3347 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3351 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3353 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3355 /* In promiscuous mode multicast promisc already set */
3356 if (dev->data->promiscuous == 0)
3357 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3361 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3363 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3365 /* In promiscuous mode leave multicast promisc enabled */
3366 if (dev->data->promiscuous == 0)
3367 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3370 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3372 struct e1000_mbx_info *mbx = &hw->mbx;
3376 /* After set vlan, vlan strip will also be enabled in igb driver*/
3377 msgbuf[0] = E1000_VF_SET_VLAN;
3379 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3381 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3383 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3387 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3391 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3392 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3399 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3401 struct e1000_hw *hw =
3402 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3403 struct e1000_vfta * shadow_vfta =
3404 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3405 int i = 0, j = 0, vfta = 0, mask = 1;
3407 for (i = 0; i < IGB_VFTA_SIZE; i++){
3408 vfta = shadow_vfta->vfta[i];
3411 for (j = 0; j < 32; j++){
3414 (uint16_t)((i<<5)+j), on);
3423 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3425 struct e1000_hw *hw =
3426 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3427 struct e1000_vfta * shadow_vfta =
3428 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3429 uint32_t vid_idx = 0;
3430 uint32_t vid_bit = 0;
3433 PMD_INIT_FUNC_TRACE();
3435 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3436 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3438 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3441 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3442 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3444 /*Save what we set and retore it after device reset*/
3446 shadow_vfta->vfta[vid_idx] |= vid_bit;
3448 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3454 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3456 struct e1000_hw *hw =
3457 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3459 /* index is not used by rar_set() */
3460 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3466 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3467 struct rte_eth_rss_reta_entry64 *reta_conf,
3472 uint16_t idx, shift;
3473 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3475 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3476 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3477 "(%d) doesn't match the number hardware can supported "
3478 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3482 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3483 idx = i / RTE_RETA_GROUP_SIZE;
3484 shift = i % RTE_RETA_GROUP_SIZE;
3485 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3489 if (mask == IGB_4_BIT_MASK)
3492 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3493 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3494 if (mask & (0x1 << j))
3495 reta |= reta_conf[idx].reta[shift + j] <<
3498 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3500 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3507 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3508 struct rte_eth_rss_reta_entry64 *reta_conf,
3513 uint16_t idx, shift;
3514 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3517 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3518 "(%d) doesn't match the number hardware can supported "
3519 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3523 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3524 idx = i / RTE_RETA_GROUP_SIZE;
3525 shift = i % RTE_RETA_GROUP_SIZE;
3526 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3530 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3531 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3532 if (mask & (0x1 << j))
3533 reta_conf[idx].reta[shift + j] =
3534 ((reta >> (CHAR_BIT * j)) &
3543 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3544 struct rte_eth_syn_filter *filter,
3547 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548 struct e1000_filter_info *filter_info =
3549 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3550 uint32_t synqf, rfctl;
3552 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3555 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3558 if (synqf & E1000_SYN_FILTER_ENABLE)
3561 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3562 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3564 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3565 if (filter->hig_pri)
3566 rfctl |= E1000_RFCTL_SYNQFP;
3568 rfctl &= ~E1000_RFCTL_SYNQFP;
3570 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3572 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3577 filter_info->syn_info = synqf;
3578 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3579 E1000_WRITE_FLUSH(hw);
3584 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3585 struct rte_eth_syn_filter *filter)
3587 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3588 uint32_t synqf, rfctl;
3590 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3591 if (synqf & E1000_SYN_FILTER_ENABLE) {
3592 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3593 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3594 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3595 E1000_SYN_FILTER_QUEUE_SHIFT);
3603 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3604 enum rte_filter_op filter_op,
3607 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3610 MAC_TYPE_FILTER_SUP(hw->mac.type);
3612 if (filter_op == RTE_ETH_FILTER_NOP)
3616 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3621 switch (filter_op) {
3622 case RTE_ETH_FILTER_ADD:
3623 ret = eth_igb_syn_filter_set(dev,
3624 (struct rte_eth_syn_filter *)arg,
3627 case RTE_ETH_FILTER_DELETE:
3628 ret = eth_igb_syn_filter_set(dev,
3629 (struct rte_eth_syn_filter *)arg,
3632 case RTE_ETH_FILTER_GET:
3633 ret = eth_igb_syn_filter_get(dev,
3634 (struct rte_eth_syn_filter *)arg);
3637 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3645 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3647 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3648 struct e1000_2tuple_filter_info *filter_info)
3650 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3652 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3653 return -EINVAL; /* filter index is out of range. */
3654 if (filter->tcp_flags > TCP_FLAG_ALL)
3655 return -EINVAL; /* flags is invalid. */
3657 switch (filter->dst_port_mask) {
3659 filter_info->dst_port_mask = 0;
3660 filter_info->dst_port = filter->dst_port;
3663 filter_info->dst_port_mask = 1;
3666 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3670 switch (filter->proto_mask) {
3672 filter_info->proto_mask = 0;
3673 filter_info->proto = filter->proto;
3676 filter_info->proto_mask = 1;
3679 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3683 filter_info->priority = (uint8_t)filter->priority;
3684 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3685 filter_info->tcp_flags = filter->tcp_flags;
3687 filter_info->tcp_flags = 0;
3692 static inline struct e1000_2tuple_filter *
3693 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3694 struct e1000_2tuple_filter_info *key)
3696 struct e1000_2tuple_filter *it;
3698 TAILQ_FOREACH(it, filter_list, entries) {
3699 if (memcmp(key, &it->filter_info,
3700 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3707 /* inject a igb 2tuple filter to HW */
3709 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3710 struct e1000_2tuple_filter *filter)
3712 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3713 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3714 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3718 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3719 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3720 imir |= E1000_IMIR_PORT_BP;
3722 imir &= ~E1000_IMIR_PORT_BP;
3724 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3726 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3727 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3728 ttqf |= (uint32_t)(filter->filter_info.proto &
3729 E1000_TTQF_PROTOCOL_MASK);
3730 if (filter->filter_info.proto_mask == 0)
3731 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3733 /* tcp flags bits setting. */
3734 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3735 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3736 imir_ext |= E1000_IMIREXT_CTRL_URG;
3737 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3738 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3739 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3740 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3741 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3742 imir_ext |= E1000_IMIREXT_CTRL_RST;
3743 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3744 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3745 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3746 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3748 imir_ext |= E1000_IMIREXT_CTRL_BP;
3750 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3751 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3752 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3756 * igb_add_2tuple_filter - add a 2tuple filter
3759 * dev: Pointer to struct rte_eth_dev.
3760 * ntuple_filter: ponter to the filter that will be added.
3763 * - On success, zero.
3764 * - On failure, a negative value.
3767 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3768 struct rte_eth_ntuple_filter *ntuple_filter)
3770 struct e1000_filter_info *filter_info =
3771 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3772 struct e1000_2tuple_filter *filter;
3775 filter = rte_zmalloc("e1000_2tuple_filter",
3776 sizeof(struct e1000_2tuple_filter), 0);
3780 ret = ntuple_filter_to_2tuple(ntuple_filter,
3781 &filter->filter_info);
3786 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3787 &filter->filter_info) != NULL) {
3788 PMD_DRV_LOG(ERR, "filter exists.");
3792 filter->queue = ntuple_filter->queue;
3795 * look for an unused 2tuple filter index,
3796 * and insert the filter to list.
3798 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3799 if (!(filter_info->twotuple_mask & (1 << i))) {
3800 filter_info->twotuple_mask |= 1 << i;
3802 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3808 if (i >= E1000_MAX_TTQF_FILTERS) {
3809 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3814 igb_inject_2uple_filter(dev, filter);
3819 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3820 struct e1000_2tuple_filter *filter)
3822 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3823 struct e1000_filter_info *filter_info =
3824 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3826 filter_info->twotuple_mask &= ~(1 << filter->index);
3827 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3830 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3831 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3832 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3837 * igb_remove_2tuple_filter - remove a 2tuple filter
3840 * dev: Pointer to struct rte_eth_dev.
3841 * ntuple_filter: ponter to the filter that will be removed.
3844 * - On success, zero.
3845 * - On failure, a negative value.
3848 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3849 struct rte_eth_ntuple_filter *ntuple_filter)
3851 struct e1000_filter_info *filter_info =
3852 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3853 struct e1000_2tuple_filter_info filter_2tuple;
3854 struct e1000_2tuple_filter *filter;
3857 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3858 ret = ntuple_filter_to_2tuple(ntuple_filter,
3863 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3865 if (filter == NULL) {
3866 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3870 igb_delete_2tuple_filter(dev, filter);
3875 /* inject a igb flex filter to HW */
3877 igb_inject_flex_filter(struct rte_eth_dev *dev,
3878 struct e1000_flex_filter *filter)
3880 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3881 uint32_t wufc, queueing;
3885 wufc = E1000_READ_REG(hw, E1000_WUFC);
3886 if (filter->index < E1000_MAX_FHFT)
3887 reg_off = E1000_FHFT(filter->index);
3889 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3891 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3892 (E1000_WUFC_FLX0 << filter->index));
3893 queueing = filter->filter_info.len |
3894 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3895 (filter->filter_info.priority <<
3896 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3897 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3900 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3901 E1000_WRITE_REG(hw, reg_off,
3902 filter->filter_info.dwords[j]);
3903 reg_off += sizeof(uint32_t);
3904 E1000_WRITE_REG(hw, reg_off,
3905 filter->filter_info.dwords[++j]);
3906 reg_off += sizeof(uint32_t);
3907 E1000_WRITE_REG(hw, reg_off,
3908 (uint32_t)filter->filter_info.mask[i]);
3909 reg_off += sizeof(uint32_t) * 2;
3914 static inline struct e1000_flex_filter *
3915 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3916 struct e1000_flex_filter_info *key)
3918 struct e1000_flex_filter *it;
3920 TAILQ_FOREACH(it, filter_list, entries) {
3921 if (memcmp(key, &it->filter_info,
3922 sizeof(struct e1000_flex_filter_info)) == 0)
3929 /* remove a flex byte filter
3931 * dev: Pointer to struct rte_eth_dev.
3932 * filter: the pointer of the filter will be removed.
3935 igb_remove_flex_filter(struct rte_eth_dev *dev,
3936 struct e1000_flex_filter *filter)
3938 struct e1000_filter_info *filter_info =
3939 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3940 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944 wufc = E1000_READ_REG(hw, E1000_WUFC);
3945 if (filter->index < E1000_MAX_FHFT)
3946 reg_off = E1000_FHFT(filter->index);
3948 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3950 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3951 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3953 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3954 (~(E1000_WUFC_FLX0 << filter->index)));
3956 filter_info->flex_mask &= ~(1 << filter->index);
3957 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3962 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3963 struct rte_eth_flex_filter *filter,
3966 struct e1000_filter_info *filter_info =
3967 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3968 struct e1000_flex_filter *flex_filter, *it;
3972 flex_filter = rte_zmalloc("e1000_flex_filter",
3973 sizeof(struct e1000_flex_filter), 0);
3974 if (flex_filter == NULL)
3977 flex_filter->filter_info.len = filter->len;
3978 flex_filter->filter_info.priority = filter->priority;
3979 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3980 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3982 /* reverse bits in flex filter's mask*/
3983 for (shift = 0; shift < CHAR_BIT; shift++) {
3984 if (filter->mask[i] & (0x01 << shift))
3985 mask |= (0x80 >> shift);
3987 flex_filter->filter_info.mask[i] = mask;
3990 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3991 &flex_filter->filter_info);
3992 if (it == NULL && !add) {
3993 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3994 rte_free(flex_filter);
3997 if (it != NULL && add) {
3998 PMD_DRV_LOG(ERR, "filter exists.");
3999 rte_free(flex_filter);
4004 flex_filter->queue = filter->queue;
4006 * look for an unused flex filter index
4007 * and insert the filter into the list.
4009 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4010 if (!(filter_info->flex_mask & (1 << i))) {
4011 filter_info->flex_mask |= 1 << i;
4012 flex_filter->index = i;
4013 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4019 if (i >= E1000_MAX_FLEX_FILTERS) {
4020 PMD_DRV_LOG(ERR, "flex filters are full.");
4021 rte_free(flex_filter);
4025 igb_inject_flex_filter(dev, flex_filter);
4028 igb_remove_flex_filter(dev, it);
4029 rte_free(flex_filter);
4036 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4037 struct rte_eth_flex_filter *filter)
4039 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4040 struct e1000_filter_info *filter_info =
4041 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4042 struct e1000_flex_filter flex_filter, *it;
4043 uint32_t wufc, queueing, wufc_en = 0;
4045 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4046 flex_filter.filter_info.len = filter->len;
4047 flex_filter.filter_info.priority = filter->priority;
4048 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4049 memcpy(flex_filter.filter_info.mask, filter->mask,
4050 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4052 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4053 &flex_filter.filter_info);
4055 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4059 wufc = E1000_READ_REG(hw, E1000_WUFC);
4060 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4062 if ((wufc & wufc_en) == wufc_en) {
4063 uint32_t reg_off = 0;
4064 if (it->index < E1000_MAX_FHFT)
4065 reg_off = E1000_FHFT(it->index);
4067 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4069 queueing = E1000_READ_REG(hw,
4070 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4071 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4072 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4073 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4074 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4075 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4082 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4083 enum rte_filter_op filter_op,
4086 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4087 struct rte_eth_flex_filter *filter;
4090 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4092 if (filter_op == RTE_ETH_FILTER_NOP)
4096 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4101 filter = (struct rte_eth_flex_filter *)arg;
4102 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4103 || filter->len % sizeof(uint64_t) != 0) {
4104 PMD_DRV_LOG(ERR, "filter's length is out of range");
4107 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4108 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4112 switch (filter_op) {
4113 case RTE_ETH_FILTER_ADD:
4114 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4116 case RTE_ETH_FILTER_DELETE:
4117 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4119 case RTE_ETH_FILTER_GET:
4120 ret = eth_igb_get_flex_filter(dev, filter);
4123 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4131 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4133 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4134 struct e1000_5tuple_filter_info *filter_info)
4136 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4138 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4139 return -EINVAL; /* filter index is out of range. */
4140 if (filter->tcp_flags > TCP_FLAG_ALL)
4141 return -EINVAL; /* flags is invalid. */
4143 switch (filter->dst_ip_mask) {
4145 filter_info->dst_ip_mask = 0;
4146 filter_info->dst_ip = filter->dst_ip;
4149 filter_info->dst_ip_mask = 1;
4152 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4156 switch (filter->src_ip_mask) {
4158 filter_info->src_ip_mask = 0;
4159 filter_info->src_ip = filter->src_ip;
4162 filter_info->src_ip_mask = 1;
4165 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4169 switch (filter->dst_port_mask) {
4171 filter_info->dst_port_mask = 0;
4172 filter_info->dst_port = filter->dst_port;
4175 filter_info->dst_port_mask = 1;
4178 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4182 switch (filter->src_port_mask) {
4184 filter_info->src_port_mask = 0;
4185 filter_info->src_port = filter->src_port;
4188 filter_info->src_port_mask = 1;
4191 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4195 switch (filter->proto_mask) {
4197 filter_info->proto_mask = 0;
4198 filter_info->proto = filter->proto;
4201 filter_info->proto_mask = 1;
4204 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4208 filter_info->priority = (uint8_t)filter->priority;
4209 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4210 filter_info->tcp_flags = filter->tcp_flags;
4212 filter_info->tcp_flags = 0;
4217 static inline struct e1000_5tuple_filter *
4218 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4219 struct e1000_5tuple_filter_info *key)
4221 struct e1000_5tuple_filter *it;
4223 TAILQ_FOREACH(it, filter_list, entries) {
4224 if (memcmp(key, &it->filter_info,
4225 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4232 /* inject a igb 5-tuple filter to HW */
4234 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4235 struct e1000_5tuple_filter *filter)
4237 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4238 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4239 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4243 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4244 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4245 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4246 if (filter->filter_info.dst_ip_mask == 0)
4247 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4248 if (filter->filter_info.src_port_mask == 0)
4249 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4250 if (filter->filter_info.proto_mask == 0)
4251 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4252 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4253 E1000_FTQF_QUEUE_MASK;
4254 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4255 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4256 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4257 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4259 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4260 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4262 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4263 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4264 imir |= E1000_IMIR_PORT_BP;
4266 imir &= ~E1000_IMIR_PORT_BP;
4267 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4269 /* tcp flags bits setting. */
4270 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4271 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4272 imir_ext |= E1000_IMIREXT_CTRL_URG;
4273 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4274 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4275 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4276 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4277 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4278 imir_ext |= E1000_IMIREXT_CTRL_RST;
4279 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4280 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4281 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4282 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4284 imir_ext |= E1000_IMIREXT_CTRL_BP;
4286 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4287 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4291 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4294 * dev: Pointer to struct rte_eth_dev.
4295 * ntuple_filter: ponter to the filter that will be added.
4298 * - On success, zero.
4299 * - On failure, a negative value.
4302 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4303 struct rte_eth_ntuple_filter *ntuple_filter)
4305 struct e1000_filter_info *filter_info =
4306 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4307 struct e1000_5tuple_filter *filter;
4311 filter = rte_zmalloc("e1000_5tuple_filter",
4312 sizeof(struct e1000_5tuple_filter), 0);
4316 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4317 &filter->filter_info);
4323 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4324 &filter->filter_info) != NULL) {
4325 PMD_DRV_LOG(ERR, "filter exists.");
4329 filter->queue = ntuple_filter->queue;
4332 * look for an unused 5tuple filter index,
4333 * and insert the filter to list.
4335 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4336 if (!(filter_info->fivetuple_mask & (1 << i))) {
4337 filter_info->fivetuple_mask |= 1 << i;
4339 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4345 if (i >= E1000_MAX_FTQF_FILTERS) {
4346 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4351 igb_inject_5tuple_filter_82576(dev, filter);
4356 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4357 struct e1000_5tuple_filter *filter)
4359 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360 struct e1000_filter_info *filter_info =
4361 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4363 filter_info->fivetuple_mask &= ~(1 << filter->index);
4364 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4367 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4368 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4369 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4370 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4371 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4372 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4373 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4378 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4381 * dev: Pointer to struct rte_eth_dev.
4382 * ntuple_filter: ponter to the filter that will be removed.
4385 * - On success, zero.
4386 * - On failure, a negative value.
4389 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4390 struct rte_eth_ntuple_filter *ntuple_filter)
4392 struct e1000_filter_info *filter_info =
4393 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4394 struct e1000_5tuple_filter_info filter_5tuple;
4395 struct e1000_5tuple_filter *filter;
4398 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4399 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4404 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4406 if (filter == NULL) {
4407 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4411 igb_delete_5tuple_filter_82576(dev, filter);
4417 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4420 struct e1000_hw *hw;
4421 struct rte_eth_dev_info dev_info;
4422 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4425 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4427 #ifdef RTE_LIBRTE_82571_SUPPORT
4428 /* XXX: not bigger than max_rx_pktlen */
4429 if (hw->mac.type == e1000_82571)
4432 eth_igb_infos_get(dev, &dev_info);
4434 /* check that mtu is within the allowed range */
4435 if ((mtu < ETHER_MIN_MTU) ||
4436 (frame_size > dev_info.max_rx_pktlen))
4439 /* refuse mtu that requires the support of scattered packets when this
4440 * feature has not been enabled before. */
4441 if (!dev->data->scattered_rx &&
4442 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4445 rctl = E1000_READ_REG(hw, E1000_RCTL);
4447 /* switch to jumbo mode if needed */
4448 if (frame_size > ETHER_MAX_LEN) {
4449 dev->data->dev_conf.rxmode.offloads |=
4450 DEV_RX_OFFLOAD_JUMBO_FRAME;
4451 rctl |= E1000_RCTL_LPE;
4453 dev->data->dev_conf.rxmode.offloads &=
4454 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4455 rctl &= ~E1000_RCTL_LPE;
4457 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4459 /* update max frame size */
4460 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4462 E1000_WRITE_REG(hw, E1000_RLPML,
4463 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4469 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4472 * dev: Pointer to struct rte_eth_dev.
4473 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4474 * add: if true, add filter, if false, remove filter
4477 * - On success, zero.
4478 * - On failure, a negative value.
4481 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4482 struct rte_eth_ntuple_filter *ntuple_filter,
4485 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4488 switch (ntuple_filter->flags) {
4489 case RTE_5TUPLE_FLAGS:
4490 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4491 if (hw->mac.type != e1000_82576)
4494 ret = igb_add_5tuple_filter_82576(dev,
4497 ret = igb_remove_5tuple_filter_82576(dev,
4500 case RTE_2TUPLE_FLAGS:
4501 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4502 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4503 hw->mac.type != e1000_i210 &&
4504 hw->mac.type != e1000_i211)
4507 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4509 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4520 * igb_get_ntuple_filter - get a ntuple filter
4523 * dev: Pointer to struct rte_eth_dev.
4524 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4527 * - On success, zero.
4528 * - On failure, a negative value.
4531 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4532 struct rte_eth_ntuple_filter *ntuple_filter)
4534 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4535 struct e1000_filter_info *filter_info =
4536 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4537 struct e1000_5tuple_filter_info filter_5tuple;
4538 struct e1000_2tuple_filter_info filter_2tuple;
4539 struct e1000_5tuple_filter *p_5tuple_filter;
4540 struct e1000_2tuple_filter *p_2tuple_filter;
4543 switch (ntuple_filter->flags) {
4544 case RTE_5TUPLE_FLAGS:
4545 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4546 if (hw->mac.type != e1000_82576)
4548 memset(&filter_5tuple,
4550 sizeof(struct e1000_5tuple_filter_info));
4551 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4555 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4556 &filter_info->fivetuple_list,
4558 if (p_5tuple_filter == NULL) {
4559 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4562 ntuple_filter->queue = p_5tuple_filter->queue;
4564 case RTE_2TUPLE_FLAGS:
4565 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4566 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4568 memset(&filter_2tuple,
4570 sizeof(struct e1000_2tuple_filter_info));
4571 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4574 p_2tuple_filter = igb_2tuple_filter_lookup(
4575 &filter_info->twotuple_list,
4577 if (p_2tuple_filter == NULL) {
4578 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4581 ntuple_filter->queue = p_2tuple_filter->queue;
4592 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4593 * @dev: pointer to rte_eth_dev structure
4594 * @filter_op:operation will be taken.
4595 * @arg: a pointer to specific structure corresponding to the filter_op
4598 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4599 enum rte_filter_op filter_op,
4602 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4605 MAC_TYPE_FILTER_SUP(hw->mac.type);
4607 if (filter_op == RTE_ETH_FILTER_NOP)
4611 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4616 switch (filter_op) {
4617 case RTE_ETH_FILTER_ADD:
4618 ret = igb_add_del_ntuple_filter(dev,
4619 (struct rte_eth_ntuple_filter *)arg,
4622 case RTE_ETH_FILTER_DELETE:
4623 ret = igb_add_del_ntuple_filter(dev,
4624 (struct rte_eth_ntuple_filter *)arg,
4627 case RTE_ETH_FILTER_GET:
4628 ret = igb_get_ntuple_filter(dev,
4629 (struct rte_eth_ntuple_filter *)arg);
4632 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4640 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4645 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4646 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4647 (filter_info->ethertype_mask & (1 << i)))
4654 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4655 uint16_t ethertype, uint32_t etqf)
4659 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4660 if (!(filter_info->ethertype_mask & (1 << i))) {
4661 filter_info->ethertype_mask |= 1 << i;
4662 filter_info->ethertype_filters[i].ethertype = ethertype;
4663 filter_info->ethertype_filters[i].etqf = etqf;
4671 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4674 if (idx >= E1000_MAX_ETQF_FILTERS)
4676 filter_info->ethertype_mask &= ~(1 << idx);
4677 filter_info->ethertype_filters[idx].ethertype = 0;
4678 filter_info->ethertype_filters[idx].etqf = 0;
4684 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4685 struct rte_eth_ethertype_filter *filter,
4688 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4689 struct e1000_filter_info *filter_info =
4690 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4694 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4695 filter->ether_type == ETHER_TYPE_IPv6) {
4696 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4697 " ethertype filter.", filter->ether_type);
4701 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4702 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4705 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4706 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4710 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4711 if (ret >= 0 && add) {
4712 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4713 filter->ether_type);
4716 if (ret < 0 && !add) {
4717 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4718 filter->ether_type);
4723 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4724 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4725 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4726 ret = igb_ethertype_filter_insert(filter_info,
4727 filter->ether_type, etqf);
4729 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4733 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4737 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4738 E1000_WRITE_FLUSH(hw);
4744 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4745 struct rte_eth_ethertype_filter *filter)
4747 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4748 struct e1000_filter_info *filter_info =
4749 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4753 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4755 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4756 filter->ether_type);
4760 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4761 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4762 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4764 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4765 E1000_ETQF_QUEUE_SHIFT;
4773 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4774 * @dev: pointer to rte_eth_dev structure
4775 * @filter_op:operation will be taken.
4776 * @arg: a pointer to specific structure corresponding to the filter_op
4779 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4780 enum rte_filter_op filter_op,
4783 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4786 MAC_TYPE_FILTER_SUP(hw->mac.type);
4788 if (filter_op == RTE_ETH_FILTER_NOP)
4792 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4797 switch (filter_op) {
4798 case RTE_ETH_FILTER_ADD:
4799 ret = igb_add_del_ethertype_filter(dev,
4800 (struct rte_eth_ethertype_filter *)arg,
4803 case RTE_ETH_FILTER_DELETE:
4804 ret = igb_add_del_ethertype_filter(dev,
4805 (struct rte_eth_ethertype_filter *)arg,
4808 case RTE_ETH_FILTER_GET:
4809 ret = igb_get_ethertype_filter(dev,
4810 (struct rte_eth_ethertype_filter *)arg);
4813 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4821 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4822 enum rte_filter_type filter_type,
4823 enum rte_filter_op filter_op,
4828 switch (filter_type) {
4829 case RTE_ETH_FILTER_NTUPLE:
4830 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4832 case RTE_ETH_FILTER_ETHERTYPE:
4833 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4835 case RTE_ETH_FILTER_SYN:
4836 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4838 case RTE_ETH_FILTER_FLEXIBLE:
4839 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4841 case RTE_ETH_FILTER_GENERIC:
4842 if (filter_op != RTE_ETH_FILTER_GET)
4844 *(const void **)arg = &igb_flow_ops;
4847 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4856 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4857 struct ether_addr *mc_addr_set,
4858 uint32_t nb_mc_addr)
4860 struct e1000_hw *hw;
4862 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4863 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4868 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4870 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4871 uint64_t systime_cycles;
4873 switch (hw->mac.type) {
4877 * Need to read System Time Residue Register to be able
4878 * to read the other two registers.
4880 E1000_READ_REG(hw, E1000_SYSTIMR);
4881 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4882 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4883 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4890 * Need to read System Time Residue Register to be able
4891 * to read the other two registers.
4893 E1000_READ_REG(hw, E1000_SYSTIMR);
4894 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4895 /* Only the 8 LSB are valid. */
4896 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4900 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4901 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4906 return systime_cycles;
4910 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4912 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4913 uint64_t rx_tstamp_cycles;
4915 switch (hw->mac.type) {
4918 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4919 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4920 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4926 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4927 /* Only the 8 LSB are valid. */
4928 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4932 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4933 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4938 return rx_tstamp_cycles;
4942 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4944 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4945 uint64_t tx_tstamp_cycles;
4947 switch (hw->mac.type) {
4950 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4951 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4952 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4958 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4959 /* Only the 8 LSB are valid. */
4960 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4964 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4965 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4970 return tx_tstamp_cycles;
4974 igb_start_timecounters(struct rte_eth_dev *dev)
4976 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4977 struct e1000_adapter *adapter =
4978 (struct e1000_adapter *)dev->data->dev_private;
4979 uint32_t incval = 1;
4981 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4983 switch (hw->mac.type) {
4987 /* 32 LSB bits + 8 MSB bits = 40 bits */
4988 mask = (1ULL << 40) - 1;
4993 * Start incrementing the register
4994 * used to timestamp PTP packets.
4996 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4999 incval = E1000_INCVALUE_82576;
5000 shift = IGB_82576_TSYNC_SHIFT;
5001 E1000_WRITE_REG(hw, E1000_TIMINCA,
5002 E1000_INCPERIOD_82576 | incval);
5009 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5010 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5011 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5013 adapter->systime_tc.cc_mask = mask;
5014 adapter->systime_tc.cc_shift = shift;
5015 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5017 adapter->rx_tstamp_tc.cc_mask = mask;
5018 adapter->rx_tstamp_tc.cc_shift = shift;
5019 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5021 adapter->tx_tstamp_tc.cc_mask = mask;
5022 adapter->tx_tstamp_tc.cc_shift = shift;
5023 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5027 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5029 struct e1000_adapter *adapter =
5030 (struct e1000_adapter *)dev->data->dev_private;
5032 adapter->systime_tc.nsec += delta;
5033 adapter->rx_tstamp_tc.nsec += delta;
5034 adapter->tx_tstamp_tc.nsec += delta;
5040 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5043 struct e1000_adapter *adapter =
5044 (struct e1000_adapter *)dev->data->dev_private;
5046 ns = rte_timespec_to_ns(ts);
5048 /* Set the timecounters to a new value. */
5049 adapter->systime_tc.nsec = ns;
5050 adapter->rx_tstamp_tc.nsec = ns;
5051 adapter->tx_tstamp_tc.nsec = ns;
5057 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5059 uint64_t ns, systime_cycles;
5060 struct e1000_adapter *adapter =
5061 (struct e1000_adapter *)dev->data->dev_private;
5063 systime_cycles = igb_read_systime_cyclecounter(dev);
5064 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5065 *ts = rte_ns_to_timespec(ns);
5071 igb_timesync_enable(struct rte_eth_dev *dev)
5073 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5077 /* Stop the timesync system time. */
5078 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5079 /* Reset the timesync system time value. */
5080 switch (hw->mac.type) {
5086 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5089 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5090 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5093 /* Not supported. */
5097 /* Enable system time for it isn't on by default. */
5098 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5099 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5100 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5102 igb_start_timecounters(dev);
5104 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5105 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5107 E1000_ETQF_FILTER_ENABLE |
5110 /* Enable timestamping of received PTP packets. */
5111 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5112 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5113 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5115 /* Enable Timestamping of transmitted PTP packets. */
5116 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5117 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5118 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5124 igb_timesync_disable(struct rte_eth_dev *dev)
5126 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5129 /* Disable timestamping of transmitted PTP packets. */
5130 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5131 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5132 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5134 /* Disable timestamping of received PTP packets. */
5135 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5136 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5137 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5139 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5140 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5142 /* Stop incrementating the System Time registers. */
5143 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5149 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5150 struct timespec *timestamp,
5151 uint32_t flags __rte_unused)
5153 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5154 struct e1000_adapter *adapter =
5155 (struct e1000_adapter *)dev->data->dev_private;
5156 uint32_t tsync_rxctl;
5157 uint64_t rx_tstamp_cycles;
5160 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5161 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5164 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5165 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5166 *timestamp = rte_ns_to_timespec(ns);
5172 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5173 struct timespec *timestamp)
5175 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5176 struct e1000_adapter *adapter =
5177 (struct e1000_adapter *)dev->data->dev_private;
5178 uint32_t tsync_txctl;
5179 uint64_t tx_tstamp_cycles;
5182 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5183 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5186 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5187 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5188 *timestamp = rte_ns_to_timespec(ns);
5194 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5198 const struct reg_info *reg_group;
5200 while ((reg_group = igb_regs[g_ind++]))
5201 count += igb_reg_group_count(reg_group);
5207 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5211 const struct reg_info *reg_group;
5213 while ((reg_group = igbvf_regs[g_ind++]))
5214 count += igb_reg_group_count(reg_group);
5220 eth_igb_get_regs(struct rte_eth_dev *dev,
5221 struct rte_dev_reg_info *regs)
5223 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5224 uint32_t *data = regs->data;
5227 const struct reg_info *reg_group;
5230 regs->length = eth_igb_get_reg_length(dev);
5231 regs->width = sizeof(uint32_t);
5235 /* Support only full register dump */
5236 if ((regs->length == 0) ||
5237 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5238 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5240 while ((reg_group = igb_regs[g_ind++]))
5241 count += igb_read_regs_group(dev, &data[count],
5250 igbvf_get_regs(struct rte_eth_dev *dev,
5251 struct rte_dev_reg_info *regs)
5253 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5254 uint32_t *data = regs->data;
5257 const struct reg_info *reg_group;
5260 regs->length = igbvf_get_reg_length(dev);
5261 regs->width = sizeof(uint32_t);
5265 /* Support only full register dump */
5266 if ((regs->length == 0) ||
5267 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5268 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5270 while ((reg_group = igbvf_regs[g_ind++]))
5271 count += igb_read_regs_group(dev, &data[count],
5280 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5282 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5284 /* Return unit is byte count */
5285 return hw->nvm.word_size * 2;
5289 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5290 struct rte_dev_eeprom_info *in_eeprom)
5292 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5293 struct e1000_nvm_info *nvm = &hw->nvm;
5294 uint16_t *data = in_eeprom->data;
5297 first = in_eeprom->offset >> 1;
5298 length = in_eeprom->length >> 1;
5299 if ((first >= hw->nvm.word_size) ||
5300 ((first + length) >= hw->nvm.word_size))
5303 in_eeprom->magic = hw->vendor_id |
5304 ((uint32_t)hw->device_id << 16);
5306 if ((nvm->ops.read) == NULL)
5309 return nvm->ops.read(hw, first, length, data);
5313 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5314 struct rte_dev_eeprom_info *in_eeprom)
5316 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5317 struct e1000_nvm_info *nvm = &hw->nvm;
5318 uint16_t *data = in_eeprom->data;
5321 first = in_eeprom->offset >> 1;
5322 length = in_eeprom->length >> 1;
5323 if ((first >= hw->nvm.word_size) ||
5324 ((first + length) >= hw->nvm.word_size))
5327 in_eeprom->magic = (uint32_t)hw->vendor_id |
5328 ((uint32_t)hw->device_id << 16);
5330 if ((nvm->ops.write) == NULL)
5332 return nvm->ops.write(hw, first, length, data);
5336 eth_igb_get_module_info(struct rte_eth_dev *dev,
5337 struct rte_eth_dev_module_info *modinfo)
5339 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5341 uint32_t status = 0;
5342 uint16_t sff8472_rev, addr_mode;
5343 bool page_swap = false;
5345 if (hw->phy.media_type == e1000_media_type_copper ||
5346 hw->phy.media_type == e1000_media_type_unknown)
5349 /* Check whether we support SFF-8472 or not */
5350 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5354 /* addressing mode is not supported */
5355 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5359 /* addressing mode is not supported */
5360 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5362 "Address change required to access page 0xA2, "
5363 "but not supported. Please report the module "
5364 "type to the driver maintainers.\n");
5368 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5369 /* We have an SFP, but it does not support SFF-8472 */
5370 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5371 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5373 /* We have an SFP which supports a revision of SFF-8472 */
5374 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5375 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5382 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5383 struct rte_dev_eeprom_info *info)
5385 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5387 uint32_t status = 0;
5388 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5389 u16 first_word, last_word;
5392 if (info->length == 0)
5395 first_word = info->offset >> 1;
5396 last_word = (info->offset + info->length - 1) >> 1;
5398 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5399 for (i = 0; i < last_word - first_word + 1; i++) {
5400 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5403 /* Error occurred while reading module */
5407 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5410 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5416 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5418 struct e1000_hw *hw =
5419 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5420 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5421 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5422 uint32_t vec = E1000_MISC_VEC_ID;
5424 if (rte_intr_allow_others(intr_handle))
5425 vec = E1000_RX_VEC_START;
5427 uint32_t mask = 1 << (queue_id + vec);
5429 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5430 E1000_WRITE_FLUSH(hw);
5436 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5438 struct e1000_hw *hw =
5439 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5440 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5441 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5442 uint32_t vec = E1000_MISC_VEC_ID;
5444 if (rte_intr_allow_others(intr_handle))
5445 vec = E1000_RX_VEC_START;
5447 uint32_t mask = 1 << (queue_id + vec);
5450 regval = E1000_READ_REG(hw, E1000_EIMS);
5451 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5452 E1000_WRITE_FLUSH(hw);
5454 rte_intr_enable(intr_handle);
5460 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5461 uint8_t index, uint8_t offset)
5463 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5466 val &= ~((uint32_t)0xFF << offset);
5468 /* write vector and valid bit */
5469 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5471 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5475 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5476 uint8_t queue, uint8_t msix_vector)
5480 if (hw->mac.type == e1000_82575) {
5482 tmp = E1000_EICR_RX_QUEUE0 << queue;
5483 else if (direction == 1)
5484 tmp = E1000_EICR_TX_QUEUE0 << queue;
5485 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5486 } else if (hw->mac.type == e1000_82576) {
5487 if ((direction == 0) || (direction == 1))
5488 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5489 ((queue & 0x8) << 1) +
5491 } else if ((hw->mac.type == e1000_82580) ||
5492 (hw->mac.type == e1000_i350) ||
5493 (hw->mac.type == e1000_i354) ||
5494 (hw->mac.type == e1000_i210) ||
5495 (hw->mac.type == e1000_i211)) {
5496 if ((direction == 0) || (direction == 1))
5497 eth_igb_write_ivar(hw, msix_vector,
5499 ((queue & 0x1) << 4) +
5504 /* Sets up the hardware to generate MSI-X interrupts properly
5506 * board private structure
5509 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5512 uint32_t tmpval, regval, intr_mask;
5513 struct e1000_hw *hw =
5514 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5515 uint32_t vec = E1000_MISC_VEC_ID;
5516 uint32_t base = E1000_MISC_VEC_ID;
5517 uint32_t misc_shift = 0;
5518 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5519 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5521 /* won't configure msix register if no mapping is done
5522 * between intr vector and event fd
5524 if (!rte_intr_dp_is_en(intr_handle))
5527 if (rte_intr_allow_others(intr_handle)) {
5528 vec = base = E1000_RX_VEC_START;
5532 /* set interrupt vector for other causes */
5533 if (hw->mac.type == e1000_82575) {
5534 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5535 /* enable MSI-X PBA support */
5536 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5538 /* Auto-Mask interrupts upon ICR read */
5539 tmpval |= E1000_CTRL_EXT_EIAME;
5540 tmpval |= E1000_CTRL_EXT_IRCA;
5542 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5544 /* enable msix_other interrupt */
5545 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5546 regval = E1000_READ_REG(hw, E1000_EIAC);
5547 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5548 regval = E1000_READ_REG(hw, E1000_EIAM);
5549 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5550 } else if ((hw->mac.type == e1000_82576) ||
5551 (hw->mac.type == e1000_82580) ||
5552 (hw->mac.type == e1000_i350) ||
5553 (hw->mac.type == e1000_i354) ||
5554 (hw->mac.type == e1000_i210) ||
5555 (hw->mac.type == e1000_i211)) {
5556 /* turn on MSI-X capability first */
5557 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5558 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5560 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5562 regval = E1000_READ_REG(hw, E1000_EIAC);
5563 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5565 /* enable msix_other interrupt */
5566 regval = E1000_READ_REG(hw, E1000_EIMS);
5567 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5568 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5569 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5572 /* use EIAM to auto-mask when MSI-X interrupt
5573 * is asserted, this saves a register write for every interrupt
5575 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5577 regval = E1000_READ_REG(hw, E1000_EIAM);
5578 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5580 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5581 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5582 intr_handle->intr_vec[queue_id] = vec;
5583 if (vec < base + intr_handle->nb_efd - 1)
5587 E1000_WRITE_FLUSH(hw);
5590 /* restore n-tuple filter */
5592 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5594 struct e1000_filter_info *filter_info =
5595 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5596 struct e1000_5tuple_filter *p_5tuple;
5597 struct e1000_2tuple_filter *p_2tuple;
5599 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5600 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5603 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5604 igb_inject_2uple_filter(dev, p_2tuple);
5608 /* restore SYN filter */
5610 igb_syn_filter_restore(struct rte_eth_dev *dev)
5612 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5613 struct e1000_filter_info *filter_info =
5614 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5617 synqf = filter_info->syn_info;
5619 if (synqf & E1000_SYN_FILTER_ENABLE) {
5620 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5621 E1000_WRITE_FLUSH(hw);
5625 /* restore ethernet type filter */
5627 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5629 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5630 struct e1000_filter_info *filter_info =
5631 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5634 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5635 if (filter_info->ethertype_mask & (1 << i)) {
5636 E1000_WRITE_REG(hw, E1000_ETQF(i),
5637 filter_info->ethertype_filters[i].etqf);
5638 E1000_WRITE_FLUSH(hw);
5643 /* restore flex byte filter */
5645 igb_flex_filter_restore(struct rte_eth_dev *dev)
5647 struct e1000_filter_info *filter_info =
5648 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5649 struct e1000_flex_filter *flex_filter;
5651 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5652 igb_inject_flex_filter(dev, flex_filter);
5656 /* restore rss filter */
5658 igb_rss_filter_restore(struct rte_eth_dev *dev)
5660 struct e1000_filter_info *filter_info =
5661 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5663 if (filter_info->rss_info.conf.queue_num)
5664 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5667 /* restore all types filter */
5669 igb_filter_restore(struct rte_eth_dev *dev)
5671 igb_ntuple_filter_restore(dev);
5672 igb_ethertype_filter_restore(dev);
5673 igb_syn_filter_restore(dev);
5674 igb_flex_filter_restore(dev);
5675 igb_rss_filter_restore(dev);
5680 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5681 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5682 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5683 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5684 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5685 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");