1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static void eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static void eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
158 static void igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
190 struct rte_eth_syn_filter *filter);
191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
192 enum rte_filter_op filter_op,
194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
197 struct rte_eth_ntuple_filter *ntuple_filter);
198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
199 struct rte_eth_flex_filter *filter);
200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
201 enum rte_filter_op filter_op,
203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
204 struct rte_eth_ntuple_filter *ntuple_filter);
205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
206 struct rte_eth_ntuple_filter *ntuple_filter);
207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
208 struct rte_eth_ntuple_filter *filter);
209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
210 enum rte_filter_op filter_op,
212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ethertype_filter *filter);
217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
218 enum rte_filter_type filter_type,
219 enum rte_filter_op filter_op,
221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
223 struct rte_dev_reg_info *regs);
224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
226 struct rte_dev_eeprom_info *eeprom);
227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
228 struct rte_dev_eeprom_info *eeprom);
229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
230 struct rte_eth_dev_module_info *modinfo);
231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
232 struct rte_dev_eeprom_info *info);
233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
234 struct rte_ether_addr *mc_addr_set,
235 uint32_t nb_mc_addr);
236 static int igb_timesync_enable(struct rte_eth_dev *dev);
237 static int igb_timesync_disable(struct rte_eth_dev *dev);
238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
239 struct timespec *timestamp,
241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
242 struct timespec *timestamp);
243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
245 struct timespec *timestamp);
246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
247 const struct timespec *timestamp);
248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
253 uint8_t queue, uint8_t msix_vector);
254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
255 uint8_t index, uint8_t offset);
256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
257 static void eth_igbvf_interrupt_handler(void *param);
258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
259 static int igb_filter_restore(struct rte_eth_dev *dev);
262 * Define VF Stats MACRO for Non "cleared on read" register
264 #define UPDATE_VF_STAT(reg, last, cur) \
266 u32 latest = E1000_READ_REG(hw, reg); \
267 cur += (latest - last) & UINT_MAX; \
271 #define IGB_FC_PAUSE_TIME 0x0680
272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
275 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
280 * The set of PCI devices this driver supports
282 static const struct rte_pci_id pci_id_igb_map[] = {
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
324 { .vendor_id = 0, /* sentinel */ },
328 * The set of PCI devices this driver supports (for 82576&I350 VF)
330 static const struct rte_pci_id pci_id_igbvf_map[] = {
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
335 { .vendor_id = 0, /* sentinel */ },
338 static const struct rte_eth_desc_lim rx_desc_lim = {
339 .nb_max = E1000_MAX_RING_DESC,
340 .nb_min = E1000_MIN_RING_DESC,
341 .nb_align = IGB_RXD_ALIGN,
344 static const struct rte_eth_desc_lim tx_desc_lim = {
345 .nb_max = E1000_MAX_RING_DESC,
346 .nb_min = E1000_MIN_RING_DESC,
347 .nb_align = IGB_RXD_ALIGN,
348 .nb_seg_max = IGB_TX_MAX_SEG,
349 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
352 static const struct eth_dev_ops eth_igb_ops = {
353 .dev_configure = eth_igb_configure,
354 .dev_start = eth_igb_start,
355 .dev_stop = eth_igb_stop,
356 .dev_set_link_up = eth_igb_dev_set_link_up,
357 .dev_set_link_down = eth_igb_dev_set_link_down,
358 .dev_close = eth_igb_close,
359 .dev_reset = eth_igb_reset,
360 .promiscuous_enable = eth_igb_promiscuous_enable,
361 .promiscuous_disable = eth_igb_promiscuous_disable,
362 .allmulticast_enable = eth_igb_allmulticast_enable,
363 .allmulticast_disable = eth_igb_allmulticast_disable,
364 .link_update = eth_igb_link_update,
365 .stats_get = eth_igb_stats_get,
366 .xstats_get = eth_igb_xstats_get,
367 .xstats_get_by_id = eth_igb_xstats_get_by_id,
368 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
369 .xstats_get_names = eth_igb_xstats_get_names,
370 .stats_reset = eth_igb_stats_reset,
371 .xstats_reset = eth_igb_xstats_reset,
372 .fw_version_get = eth_igb_fw_version_get,
373 .dev_infos_get = eth_igb_infos_get,
374 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
375 .mtu_set = eth_igb_mtu_set,
376 .vlan_filter_set = eth_igb_vlan_filter_set,
377 .vlan_tpid_set = eth_igb_vlan_tpid_set,
378 .vlan_offload_set = eth_igb_vlan_offload_set,
379 .rx_queue_setup = eth_igb_rx_queue_setup,
380 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
381 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
382 .rx_queue_release = eth_igb_rx_queue_release,
383 .rx_queue_count = eth_igb_rx_queue_count,
384 .rx_descriptor_done = eth_igb_rx_descriptor_done,
385 .rx_descriptor_status = eth_igb_rx_descriptor_status,
386 .tx_descriptor_status = eth_igb_tx_descriptor_status,
387 .tx_queue_setup = eth_igb_tx_queue_setup,
388 .tx_queue_release = eth_igb_tx_queue_release,
389 .tx_done_cleanup = eth_igb_tx_done_cleanup,
390 .dev_led_on = eth_igb_led_on,
391 .dev_led_off = eth_igb_led_off,
392 .flow_ctrl_get = eth_igb_flow_ctrl_get,
393 .flow_ctrl_set = eth_igb_flow_ctrl_set,
394 .mac_addr_add = eth_igb_rar_set,
395 .mac_addr_remove = eth_igb_rar_clear,
396 .mac_addr_set = eth_igb_default_mac_addr_set,
397 .reta_update = eth_igb_rss_reta_update,
398 .reta_query = eth_igb_rss_reta_query,
399 .rss_hash_update = eth_igb_rss_hash_update,
400 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
401 .filter_ctrl = eth_igb_filter_ctrl,
402 .set_mc_addr_list = eth_igb_set_mc_addr_list,
403 .rxq_info_get = igb_rxq_info_get,
404 .txq_info_get = igb_txq_info_get,
405 .timesync_enable = igb_timesync_enable,
406 .timesync_disable = igb_timesync_disable,
407 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
408 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
409 .get_reg = eth_igb_get_regs,
410 .get_eeprom_length = eth_igb_get_eeprom_length,
411 .get_eeprom = eth_igb_get_eeprom,
412 .set_eeprom = eth_igb_set_eeprom,
413 .get_module_info = eth_igb_get_module_info,
414 .get_module_eeprom = eth_igb_get_module_eeprom,
415 .timesync_adjust_time = igb_timesync_adjust_time,
416 .timesync_read_time = igb_timesync_read_time,
417 .timesync_write_time = igb_timesync_write_time,
421 * dev_ops for virtual function, bare necessities for basic vf
422 * operation have been implemented
424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
425 .dev_configure = igbvf_dev_configure,
426 .dev_start = igbvf_dev_start,
427 .dev_stop = igbvf_dev_stop,
428 .dev_close = igbvf_dev_close,
429 .promiscuous_enable = igbvf_promiscuous_enable,
430 .promiscuous_disable = igbvf_promiscuous_disable,
431 .allmulticast_enable = igbvf_allmulticast_enable,
432 .allmulticast_disable = igbvf_allmulticast_disable,
433 .link_update = eth_igb_link_update,
434 .stats_get = eth_igbvf_stats_get,
435 .xstats_get = eth_igbvf_xstats_get,
436 .xstats_get_names = eth_igbvf_xstats_get_names,
437 .stats_reset = eth_igbvf_stats_reset,
438 .xstats_reset = eth_igbvf_stats_reset,
439 .vlan_filter_set = igbvf_vlan_filter_set,
440 .dev_infos_get = eth_igbvf_infos_get,
441 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
442 .rx_queue_setup = eth_igb_rx_queue_setup,
443 .rx_queue_release = eth_igb_rx_queue_release,
444 .rx_descriptor_done = eth_igb_rx_descriptor_done,
445 .rx_descriptor_status = eth_igb_rx_descriptor_status,
446 .tx_descriptor_status = eth_igb_tx_descriptor_status,
447 .tx_queue_setup = eth_igb_tx_queue_setup,
448 .tx_queue_release = eth_igb_tx_queue_release,
449 .set_mc_addr_list = eth_igb_set_mc_addr_list,
450 .rxq_info_get = igb_rxq_info_get,
451 .txq_info_get = igb_txq_info_get,
452 .mac_addr_set = igbvf_default_mac_addr_set,
453 .get_reg = igbvf_get_regs,
456 /* store statistics names and its offset in stats structure */
457 struct rte_igb_xstats_name_off {
458 char name[RTE_ETH_XSTATS_NAME_SIZE];
462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
463 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
464 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
465 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
466 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
467 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
468 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
469 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
471 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
472 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
473 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
474 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
475 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
476 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
477 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
478 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
479 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
480 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
481 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
483 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
484 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
485 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
486 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
487 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
489 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
491 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
492 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
493 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
494 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
495 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
496 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
497 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
498 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
499 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
500 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
501 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
502 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
503 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
504 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
505 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
506 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
507 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
508 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
510 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
512 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
513 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
514 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
515 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
516 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
517 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
518 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
520 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
524 sizeof(rte_igb_stats_strings[0]))
526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
527 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
528 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
529 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
530 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
531 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
535 sizeof(rte_igbvf_stats_strings[0]))
539 igb_intr_enable(struct rte_eth_dev *dev)
541 struct e1000_interrupt *intr =
542 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
543 struct e1000_hw *hw =
544 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
545 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
546 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
548 if (rte_intr_allow_others(intr_handle) &&
549 dev->data->dev_conf.intr_conf.lsc != 0) {
550 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
553 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
554 E1000_WRITE_FLUSH(hw);
558 igb_intr_disable(struct rte_eth_dev *dev)
560 struct e1000_hw *hw =
561 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
565 if (rte_intr_allow_others(intr_handle) &&
566 dev->data->dev_conf.intr_conf.lsc != 0) {
567 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
570 E1000_WRITE_REG(hw, E1000_IMC, ~0);
571 E1000_WRITE_FLUSH(hw);
575 igbvf_intr_enable(struct rte_eth_dev *dev)
577 struct e1000_hw *hw =
578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
580 /* only for mailbox */
581 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
582 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
583 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
584 E1000_WRITE_FLUSH(hw);
587 /* only for mailbox now. If RX/TX needed, should extend this function. */
589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
594 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
595 tmp |= E1000_VTIVAR_VALID;
596 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
602 struct e1000_hw *hw =
603 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 /* Configure VF other cause ivar */
606 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
609 static inline int32_t
610 igb_pf_reset_hw(struct e1000_hw *hw)
615 status = e1000_reset_hw(hw);
617 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
618 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
619 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
620 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
621 E1000_WRITE_FLUSH(hw);
627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
629 struct e1000_hw *hw =
630 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 hw->vendor_id = pci_dev->id.vendor_id;
634 hw->device_id = pci_dev->id.device_id;
635 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
636 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
638 e1000_set_mac_type(hw);
640 /* need to check if it is a vf device below */
644 igb_reset_swfw_lock(struct e1000_hw *hw)
649 * Do mac ops initialization manually here, since we will need
650 * some function pointers set by this call.
652 ret_val = e1000_init_mac_params(hw);
657 * SMBI lock should not fail in this early stage. If this is the case,
658 * it is due to an improper exit of the application.
659 * So force the release of the faulty lock.
661 if (e1000_get_hw_semaphore_generic(hw) < 0) {
662 PMD_DRV_LOG(DEBUG, "SMBI lock released");
664 e1000_put_hw_semaphore_generic(hw);
666 if (hw->mac.ops.acquire_swfw_sync != NULL) {
670 * Phy lock should not fail in this early stage. If this is the case,
671 * it is due to an improper exit of the application.
672 * So force the release of the faulty lock.
674 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
675 if (hw->bus.func > E1000_FUNC_1)
677 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
678 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
681 hw->mac.ops.release_swfw_sync(hw, mask);
684 * This one is more tricky since it is common to all ports; but
685 * swfw_sync retries last long enough (1s) to be almost sure that if
686 * lock can not be taken it is due to an improper lock of the
689 mask = E1000_SWFW_EEP_SM;
690 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
691 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
693 hw->mac.ops.release_swfw_sync(hw, mask);
696 return E1000_SUCCESS;
699 /* Remove all ntuple filters of the device */
700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
702 struct e1000_filter_info *filter_info =
703 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
704 struct e1000_5tuple_filter *p_5tuple;
705 struct e1000_2tuple_filter *p_2tuple;
707 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
708 TAILQ_REMOVE(&filter_info->fivetuple_list,
712 filter_info->fivetuple_mask = 0;
713 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
714 TAILQ_REMOVE(&filter_info->twotuple_list,
718 filter_info->twotuple_mask = 0;
723 /* Remove all flex filters of the device */
724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
726 struct e1000_filter_info *filter_info =
727 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
728 struct e1000_flex_filter *p_flex;
730 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
731 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
734 filter_info->flex_mask = 0;
740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
743 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
744 struct e1000_hw *hw =
745 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
746 struct e1000_vfta * shadow_vfta =
747 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
748 struct e1000_filter_info *filter_info =
749 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
750 struct e1000_adapter *adapter =
751 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
755 eth_dev->dev_ops = ð_igb_ops;
756 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
757 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
758 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
760 /* for secondary processes, we don't initialise any further as primary
761 * has already done this work. Only check we don't need a different
763 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
764 if (eth_dev->data->scattered_rx)
765 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
769 rte_eth_copy_pci_info(eth_dev, pci_dev);
771 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
773 igb_identify_hardware(eth_dev, pci_dev);
774 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
779 e1000_get_bus_info(hw);
781 /* Reset any pending lock */
782 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
787 /* Finish initialization */
788 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
794 hw->phy.autoneg_wait_to_complete = 0;
795 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
798 if (hw->phy.media_type == e1000_media_type_copper) {
799 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
800 hw->phy.disable_polarity_correction = 0;
801 hw->phy.ms_type = e1000_ms_hw_default;
805 * Start from a known state, this is important in reading the nvm
810 /* Make sure we have a good EEPROM before we read from it */
811 if (e1000_validate_nvm_checksum(hw) < 0) {
813 * Some PCI-E parts fail the first check due to
814 * the link being in sleep state, call it again,
815 * if it fails a second time its a real issue.
817 if (e1000_validate_nvm_checksum(hw) < 0) {
818 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
824 /* Read the permanent MAC address out of the EEPROM */
825 if (e1000_read_mac_addr(hw) != 0) {
826 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
831 /* Allocate memory for storing MAC addresses */
832 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
833 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
834 if (eth_dev->data->mac_addrs == NULL) {
835 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
836 "store MAC addresses",
837 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
842 /* Copy the permanent MAC address */
843 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
844 ð_dev->data->mac_addrs[0]);
846 /* Pass the information to the rte_eth_dev_close() that it should also
847 * release the private port resources.
849 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
851 /* initialize the vfta */
852 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
854 /* Now initialize the hardware */
855 if (igb_hardware_init(hw) != 0) {
856 PMD_INIT_LOG(ERR, "Hardware initialization failed");
857 rte_free(eth_dev->data->mac_addrs);
858 eth_dev->data->mac_addrs = NULL;
862 hw->mac.get_link_status = 1;
863 adapter->stopped = 0;
865 /* Indicate SOL/IDER usage */
866 if (e1000_check_reset_block(hw) < 0) {
867 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
871 /* initialize PF if max_vfs not zero */
872 igb_pf_host_init(eth_dev);
874 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
875 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
876 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
877 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
878 E1000_WRITE_FLUSH(hw);
880 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
881 eth_dev->data->port_id, pci_dev->id.vendor_id,
882 pci_dev->id.device_id);
884 rte_intr_callback_register(&pci_dev->intr_handle,
885 eth_igb_interrupt_handler,
888 /* enable uio/vfio intr/eventfd mapping */
889 rte_intr_enable(&pci_dev->intr_handle);
891 /* enable support intr */
892 igb_intr_enable(eth_dev);
894 /* initialize filter info */
895 memset(filter_info, 0,
896 sizeof(struct e1000_filter_info));
898 TAILQ_INIT(&filter_info->flex_list);
899 TAILQ_INIT(&filter_info->twotuple_list);
900 TAILQ_INIT(&filter_info->fivetuple_list);
902 TAILQ_INIT(&igb_filter_ntuple_list);
903 TAILQ_INIT(&igb_filter_ethertype_list);
904 TAILQ_INIT(&igb_filter_syn_list);
905 TAILQ_INIT(&igb_filter_flex_list);
906 TAILQ_INIT(&igb_filter_rss_list);
907 TAILQ_INIT(&igb_flow_list);
912 igb_hw_control_release(hw);
918 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
920 PMD_INIT_FUNC_TRACE();
922 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
925 eth_igb_close(eth_dev);
931 * Virtual Function device init
934 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
936 struct rte_pci_device *pci_dev;
937 struct rte_intr_handle *intr_handle;
938 struct e1000_adapter *adapter =
939 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
940 struct e1000_hw *hw =
941 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
943 struct rte_ether_addr *perm_addr =
944 (struct rte_ether_addr *)hw->mac.perm_addr;
946 PMD_INIT_FUNC_TRACE();
948 eth_dev->dev_ops = &igbvf_eth_dev_ops;
949 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
950 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
951 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
953 /* for secondary processes, we don't initialise any further as primary
954 * has already done this work. Only check we don't need a different
956 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
957 if (eth_dev->data->scattered_rx)
958 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
962 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
963 rte_eth_copy_pci_info(eth_dev, pci_dev);
965 hw->device_id = pci_dev->id.device_id;
966 hw->vendor_id = pci_dev->id.vendor_id;
967 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
968 adapter->stopped = 0;
970 /* Initialize the shared code (base driver) */
971 diag = e1000_setup_init_funcs(hw, TRUE);
973 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
978 /* init_mailbox_params */
979 hw->mbx.ops.init_params(hw);
981 /* Disable the interrupts for VF */
982 igbvf_intr_disable(hw);
984 diag = hw->mac.ops.reset_hw(hw);
986 /* Allocate memory for storing MAC addresses */
987 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
988 hw->mac.rar_entry_count, 0);
989 if (eth_dev->data->mac_addrs == NULL) {
991 "Failed to allocate %d bytes needed to store MAC "
993 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
997 /* Pass the information to the rte_eth_dev_close() that it should also
998 * release the private port resources.
1000 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1002 /* Generate a random MAC address, if none was assigned by PF. */
1003 if (rte_is_zero_ether_addr(perm_addr)) {
1004 rte_eth_random_addr(perm_addr->addr_bytes);
1005 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1006 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1007 "%02x:%02x:%02x:%02x:%02x:%02x",
1008 perm_addr->addr_bytes[0],
1009 perm_addr->addr_bytes[1],
1010 perm_addr->addr_bytes[2],
1011 perm_addr->addr_bytes[3],
1012 perm_addr->addr_bytes[4],
1013 perm_addr->addr_bytes[5]);
1016 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1018 rte_free(eth_dev->data->mac_addrs);
1019 eth_dev->data->mac_addrs = NULL;
1022 /* Copy the permanent MAC address */
1023 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1024 ð_dev->data->mac_addrs[0]);
1026 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1028 eth_dev->data->port_id, pci_dev->id.vendor_id,
1029 pci_dev->id.device_id, "igb_mac_82576_vf");
1031 intr_handle = &pci_dev->intr_handle;
1032 rte_intr_callback_register(intr_handle,
1033 eth_igbvf_interrupt_handler, eth_dev);
1039 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1041 PMD_INIT_FUNC_TRACE();
1043 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1046 igbvf_dev_close(eth_dev);
1051 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1052 struct rte_pci_device *pci_dev)
1054 return rte_eth_dev_pci_generic_probe(pci_dev,
1055 sizeof(struct e1000_adapter), eth_igb_dev_init);
1058 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1060 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1063 static struct rte_pci_driver rte_igb_pmd = {
1064 .id_table = pci_id_igb_map,
1065 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1066 .probe = eth_igb_pci_probe,
1067 .remove = eth_igb_pci_remove,
1071 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1072 struct rte_pci_device *pci_dev)
1074 return rte_eth_dev_pci_generic_probe(pci_dev,
1075 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1078 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1080 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1084 * virtual function driver struct
1086 static struct rte_pci_driver rte_igbvf_pmd = {
1087 .id_table = pci_id_igbvf_map,
1088 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1089 .probe = eth_igbvf_pci_probe,
1090 .remove = eth_igbvf_pci_remove,
1094 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1096 struct e1000_hw *hw =
1097 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1099 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1100 rctl |= E1000_RCTL_VFE;
1101 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1105 igb_check_mq_mode(struct rte_eth_dev *dev)
1107 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1108 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1109 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1110 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1112 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1113 tx_mq_mode == ETH_MQ_TX_DCB ||
1114 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1115 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1118 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1119 /* Check multi-queue mode.
1120 * To no break software we accept ETH_MQ_RX_NONE as this might
1121 * be used to turn off VLAN filter.
1124 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1125 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1126 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1127 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1129 /* Only support one queue on VFs.
1130 * RSS together with SRIOV is not supported.
1132 PMD_INIT_LOG(ERR, "SRIOV is active,"
1133 " wrong mq_mode rx %d.",
1137 /* TX mode is not used here, so mode might be ignored.*/
1138 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1139 /* SRIOV only works in VMDq enable mode */
1140 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1141 " TX mode %d is not supported. "
1142 " Driver will behave as %d mode.",
1143 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1146 /* check valid queue number */
1147 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1148 PMD_INIT_LOG(ERR, "SRIOV is active,"
1149 " only support one queue on VFs.");
1153 /* To no break software that set invalid mode, only display
1154 * warning if invalid mode is used.
1156 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1157 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1158 rx_mq_mode != ETH_MQ_RX_RSS) {
1159 /* RSS together with VMDq not supported*/
1160 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1165 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1166 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1167 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1168 " Due to txmode is meaningless in this"
1169 " driver, just ignore.",
1177 eth_igb_configure(struct rte_eth_dev *dev)
1179 struct e1000_interrupt *intr =
1180 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1183 PMD_INIT_FUNC_TRACE();
1185 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1187 /* multipe queue mode checking */
1188 ret = igb_check_mq_mode(dev);
1190 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1195 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1196 PMD_INIT_FUNC_TRACE();
1202 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1205 struct e1000_hw *hw =
1206 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207 uint32_t tctl, rctl;
1209 tctl = E1000_READ_REG(hw, E1000_TCTL);
1210 rctl = E1000_READ_REG(hw, E1000_RCTL);
1214 tctl |= E1000_TCTL_EN;
1215 rctl |= E1000_RCTL_EN;
1218 tctl &= ~E1000_TCTL_EN;
1219 rctl &= ~E1000_RCTL_EN;
1221 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1222 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1223 E1000_WRITE_FLUSH(hw);
1227 eth_igb_start(struct rte_eth_dev *dev)
1229 struct e1000_hw *hw =
1230 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231 struct e1000_adapter *adapter =
1232 E1000_DEV_PRIVATE(dev->data->dev_private);
1233 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1234 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1236 uint32_t intr_vector = 0;
1242 PMD_INIT_FUNC_TRACE();
1244 /* disable uio/vfio intr/eventfd mapping */
1245 rte_intr_disable(intr_handle);
1247 /* Power up the phy. Needed to make the link go Up */
1248 eth_igb_dev_set_link_up(dev);
1251 * Packet Buffer Allocation (PBA)
1252 * Writing PBA sets the receive portion of the buffer
1253 * the remainder is used for the transmit buffer.
1255 if (hw->mac.type == e1000_82575) {
1258 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1259 E1000_WRITE_REG(hw, E1000_PBA, pba);
1262 /* Put the address into the Receive Address Array */
1263 e1000_rar_set(hw, hw->mac.addr, 0);
1265 /* Initialize the hardware */
1266 if (igb_hardware_init(hw)) {
1267 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1270 adapter->stopped = 0;
1272 E1000_WRITE_REG(hw, E1000_VET,
1273 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1275 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1276 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1277 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1278 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1279 E1000_WRITE_FLUSH(hw);
1281 /* configure PF module if SRIOV enabled */
1282 igb_pf_host_configure(dev);
1284 /* check and configure queue intr-vector mapping */
1285 if ((rte_intr_cap_multiple(intr_handle) ||
1286 !RTE_ETH_DEV_SRIOV(dev).active) &&
1287 dev->data->dev_conf.intr_conf.rxq != 0) {
1288 intr_vector = dev->data->nb_rx_queues;
1289 if (rte_intr_efd_enable(intr_handle, intr_vector))
1293 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1294 intr_handle->intr_vec =
1295 rte_zmalloc("intr_vec",
1296 dev->data->nb_rx_queues * sizeof(int), 0);
1297 if (intr_handle->intr_vec == NULL) {
1298 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1299 " intr_vec", dev->data->nb_rx_queues);
1304 /* confiugre msix for rx interrupt */
1305 eth_igb_configure_msix_intr(dev);
1307 /* Configure for OS presence */
1308 igb_init_manageability(hw);
1310 eth_igb_tx_init(dev);
1312 /* This can fail when allocating mbufs for descriptor rings */
1313 ret = eth_igb_rx_init(dev);
1315 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1316 igb_dev_clear_queues(dev);
1320 e1000_clear_hw_cntrs_base_generic(hw);
1323 * VLAN Offload Settings
1325 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1326 ETH_VLAN_EXTEND_MASK;
1327 ret = eth_igb_vlan_offload_set(dev, mask);
1329 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1330 igb_dev_clear_queues(dev);
1334 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1335 /* Enable VLAN filter since VMDq always use VLAN filter */
1336 igb_vmdq_vlan_hw_filter_enable(dev);
1339 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1340 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1341 (hw->mac.type == e1000_i211)) {
1342 /* Configure EITR with the maximum possible value (0xFFFF) */
1343 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1346 /* Setup link speed and duplex */
1347 speeds = &dev->data->dev_conf.link_speeds;
1348 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1349 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1350 hw->mac.autoneg = 1;
1353 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1356 hw->phy.autoneg_advertised = 0;
1358 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1359 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1360 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1362 goto error_invalid_config;
1364 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1365 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1368 if (*speeds & ETH_LINK_SPEED_10M) {
1369 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1372 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1373 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1376 if (*speeds & ETH_LINK_SPEED_100M) {
1377 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1380 if (*speeds & ETH_LINK_SPEED_1G) {
1381 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1384 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1385 goto error_invalid_config;
1387 /* Set/reset the mac.autoneg based on the link speed,
1391 hw->mac.autoneg = 0;
1392 hw->mac.forced_speed_duplex =
1393 hw->phy.autoneg_advertised;
1395 hw->mac.autoneg = 1;
1399 e1000_setup_link(hw);
1401 if (rte_intr_allow_others(intr_handle)) {
1402 /* check if lsc interrupt is enabled */
1403 if (dev->data->dev_conf.intr_conf.lsc != 0)
1404 eth_igb_lsc_interrupt_setup(dev, TRUE);
1406 eth_igb_lsc_interrupt_setup(dev, FALSE);
1408 rte_intr_callback_unregister(intr_handle,
1409 eth_igb_interrupt_handler,
1411 if (dev->data->dev_conf.intr_conf.lsc != 0)
1412 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1413 " no intr multiplex");
1416 /* check if rxq interrupt is enabled */
1417 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1418 rte_intr_dp_is_en(intr_handle))
1419 eth_igb_rxq_interrupt_setup(dev);
1421 /* enable uio/vfio intr/eventfd mapping */
1422 rte_intr_enable(intr_handle);
1424 /* resume enabled intr since hw reset */
1425 igb_intr_enable(dev);
1427 /* restore all types filter */
1428 igb_filter_restore(dev);
1430 eth_igb_rxtx_control(dev, true);
1431 eth_igb_link_update(dev, 0);
1433 PMD_INIT_LOG(DEBUG, "<<");
1437 error_invalid_config:
1438 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1439 dev->data->dev_conf.link_speeds, dev->data->port_id);
1440 igb_dev_clear_queues(dev);
1444 /*********************************************************************
1446 * This routine disables all traffic on the adapter by issuing a
1447 * global reset on the MAC.
1449 **********************************************************************/
1451 eth_igb_stop(struct rte_eth_dev *dev)
1453 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1455 struct rte_eth_link link;
1456 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1457 struct e1000_adapter *adapter =
1458 E1000_DEV_PRIVATE(dev->data->dev_private);
1460 if (adapter->stopped)
1463 eth_igb_rxtx_control(dev, false);
1465 igb_intr_disable(dev);
1467 /* disable intr eventfd mapping */
1468 rte_intr_disable(intr_handle);
1470 igb_pf_reset_hw(hw);
1471 E1000_WRITE_REG(hw, E1000_WUC, 0);
1473 /* Set bit for Go Link disconnect if PHY reset is not blocked */
1474 if (hw->mac.type >= e1000_82580 &&
1475 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1478 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1479 phpm_reg |= E1000_82580_PM_GO_LINKD;
1480 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1483 /* Power down the phy. Needed to make the link go Down */
1484 eth_igb_dev_set_link_down(dev);
1486 igb_dev_clear_queues(dev);
1488 /* clear the recorded link status */
1489 memset(&link, 0, sizeof(link));
1490 rte_eth_linkstatus_set(dev, &link);
1492 if (!rte_intr_allow_others(intr_handle))
1493 /* resume to the default handler */
1494 rte_intr_callback_register(intr_handle,
1495 eth_igb_interrupt_handler,
1498 /* Clean datapath event and queue/vec mapping */
1499 rte_intr_efd_disable(intr_handle);
1500 if (intr_handle->intr_vec != NULL) {
1501 rte_free(intr_handle->intr_vec);
1502 intr_handle->intr_vec = NULL;
1505 adapter->stopped = true;
1509 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1511 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1513 if (hw->phy.media_type == e1000_media_type_copper)
1514 e1000_power_up_phy(hw);
1516 e1000_power_up_fiber_serdes_link(hw);
1522 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1524 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1526 if (hw->phy.media_type == e1000_media_type_copper)
1527 e1000_power_down_phy(hw);
1529 e1000_shutdown_fiber_serdes_link(hw);
1535 eth_igb_close(struct rte_eth_dev *dev)
1537 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1538 struct rte_eth_link link;
1539 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1540 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1541 struct e1000_filter_info *filter_info =
1542 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1546 e1000_phy_hw_reset(hw);
1547 igb_release_manageability(hw);
1548 igb_hw_control_release(hw);
1550 /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1551 if (hw->mac.type >= e1000_82580 &&
1552 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1555 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1556 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1557 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1560 igb_dev_free_queues(dev);
1562 if (intr_handle->intr_vec) {
1563 rte_free(intr_handle->intr_vec);
1564 intr_handle->intr_vec = NULL;
1567 memset(&link, 0, sizeof(link));
1568 rte_eth_linkstatus_set(dev, &link);
1570 dev->dev_ops = NULL;
1571 dev->rx_pkt_burst = NULL;
1572 dev->tx_pkt_burst = NULL;
1574 /* Reset any pending lock */
1575 igb_reset_swfw_lock(hw);
1577 /* uninitialize PF if max_vfs not zero */
1578 igb_pf_host_uninit(dev);
1580 rte_intr_callback_unregister(intr_handle,
1581 eth_igb_interrupt_handler, dev);
1583 /* clear the SYN filter info */
1584 filter_info->syn_info = 0;
1586 /* clear the ethertype filters info */
1587 filter_info->ethertype_mask = 0;
1588 memset(filter_info->ethertype_filters, 0,
1589 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1591 /* clear the rss filter info */
1592 memset(&filter_info->rss_info, 0,
1593 sizeof(struct igb_rte_flow_rss_conf));
1595 /* remove all ntuple filters of the device */
1596 igb_ntuple_filter_uninit(dev);
1598 /* remove all flex filters of the device */
1599 igb_flex_filter_uninit(dev);
1601 /* clear all the filters list */
1602 igb_filterlist_flush(dev);
1609 eth_igb_reset(struct rte_eth_dev *dev)
1613 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1614 * its VF to make them align with it. The detailed notification
1615 * mechanism is PMD specific and is currently not implemented.
1616 * To avoid unexpected behavior in VF, currently reset of PF with
1617 * SR-IOV activation is not supported. It might be supported later.
1619 if (dev->data->sriov.active)
1622 ret = eth_igb_dev_uninit(dev);
1626 ret = eth_igb_dev_init(dev);
1633 igb_get_rx_buffer_size(struct e1000_hw *hw)
1635 uint32_t rx_buf_size;
1636 if (hw->mac.type == e1000_82576) {
1637 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1638 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1639 /* PBS needs to be translated according to a lookup table */
1640 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1641 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1642 rx_buf_size = (rx_buf_size << 10);
1643 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1644 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1646 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1652 /*********************************************************************
1654 * Initialize the hardware
1656 **********************************************************************/
1658 igb_hardware_init(struct e1000_hw *hw)
1660 uint32_t rx_buf_size;
1663 /* Let the firmware know the OS is in control */
1664 igb_hw_control_acquire(hw);
1667 * These parameters control the automatic generation (Tx) and
1668 * response (Rx) to Ethernet PAUSE frames.
1669 * - High water mark should allow for at least two standard size (1518)
1670 * frames to be received after sending an XOFF.
1671 * - Low water mark works best when it is very near the high water mark.
1672 * This allows the receiver to restart by sending XON when it has
1673 * drained a bit. Here we use an arbitrary value of 1500 which will
1674 * restart after one full frame is pulled from the buffer. There
1675 * could be several smaller frames in the buffer and if so they will
1676 * not trigger the XON until their total number reduces the buffer
1678 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1680 rx_buf_size = igb_get_rx_buffer_size(hw);
1682 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1683 hw->fc.low_water = hw->fc.high_water - 1500;
1684 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1685 hw->fc.send_xon = 1;
1687 /* Set Flow control, use the tunable location if sane */
1688 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1689 hw->fc.requested_mode = igb_fc_setting;
1691 hw->fc.requested_mode = e1000_fc_none;
1693 /* Issue a global reset */
1694 igb_pf_reset_hw(hw);
1695 E1000_WRITE_REG(hw, E1000_WUC, 0);
1697 diag = e1000_init_hw(hw);
1701 E1000_WRITE_REG(hw, E1000_VET,
1702 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1703 e1000_get_phy_info(hw);
1704 e1000_check_for_link(hw);
1709 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1711 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1715 uint64_t old_gprc = stats->gprc;
1716 uint64_t old_gptc = stats->gptc;
1717 uint64_t old_tpr = stats->tpr;
1718 uint64_t old_tpt = stats->tpt;
1719 uint64_t old_rpthc = stats->rpthc;
1720 uint64_t old_hgptc = stats->hgptc;
1722 if(hw->phy.media_type == e1000_media_type_copper ||
1723 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1725 E1000_READ_REG(hw,E1000_SYMERRS);
1726 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1729 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1730 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1731 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1732 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1734 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1735 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1736 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1737 stats->dc += E1000_READ_REG(hw, E1000_DC);
1738 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1739 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1740 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1742 ** For watchdog management we need to know if we have been
1743 ** paused during the last interval, so capture that here.
1745 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1746 stats->xoffrxc += pause_frames;
1747 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1748 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1749 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1750 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1751 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1752 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1753 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1754 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1755 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1756 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1757 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1758 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1760 /* For the 64-bit byte counters the low dword must be read first. */
1761 /* Both registers clear on the read of the high dword */
1763 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1764 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1765 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1766 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1767 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1768 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1769 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1771 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1772 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1773 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1774 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1775 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1777 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1778 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1780 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1781 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1782 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1783 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1784 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1785 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1787 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1788 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1789 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1790 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1791 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1792 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1793 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1794 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1796 /* Interrupt Counts */
1798 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1799 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1800 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1801 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1802 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1803 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1804 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1805 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1806 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1808 /* Host to Card Statistics */
1810 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1811 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1812 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1813 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1814 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1815 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1816 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1817 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1818 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1819 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1820 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1821 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1822 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1823 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1824 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1825 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1827 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1828 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1829 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1830 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1831 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1832 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1836 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1838 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839 struct e1000_hw_stats *stats =
1840 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1842 igb_read_stats_registers(hw, stats);
1844 if (rte_stats == NULL)
1848 rte_stats->imissed = stats->mpc;
1849 rte_stats->ierrors = stats->crcerrs +
1850 stats->rlec + stats->ruc + stats->roc +
1851 stats->rxerrc + stats->algnerrc + stats->cexterr;
1854 rte_stats->oerrors = stats->ecol + stats->latecol;
1856 rte_stats->ipackets = stats->gprc;
1857 rte_stats->opackets = stats->gptc;
1858 rte_stats->ibytes = stats->gorc;
1859 rte_stats->obytes = stats->gotc;
1864 eth_igb_stats_reset(struct rte_eth_dev *dev)
1866 struct e1000_hw_stats *hw_stats =
1867 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1869 /* HW registers are cleared on read */
1870 eth_igb_stats_get(dev, NULL);
1872 /* Reset software totals */
1873 memset(hw_stats, 0, sizeof(*hw_stats));
1879 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1881 struct e1000_hw_stats *stats =
1882 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1884 /* HW registers are cleared on read */
1885 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1887 /* Reset software totals */
1888 memset(stats, 0, sizeof(*stats));
1893 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1894 struct rte_eth_xstat_name *xstats_names,
1895 __rte_unused unsigned int size)
1899 if (xstats_names == NULL)
1900 return IGB_NB_XSTATS;
1902 /* Note: limit checked in rte_eth_xstats_names() */
1904 for (i = 0; i < IGB_NB_XSTATS; i++) {
1905 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1906 sizeof(xstats_names[i].name));
1909 return IGB_NB_XSTATS;
1912 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1913 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1919 if (xstats_names == NULL)
1920 return IGB_NB_XSTATS;
1922 for (i = 0; i < IGB_NB_XSTATS; i++)
1923 strlcpy(xstats_names[i].name,
1924 rte_igb_stats_strings[i].name,
1925 sizeof(xstats_names[i].name));
1927 return IGB_NB_XSTATS;
1930 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1932 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1935 for (i = 0; i < limit; i++) {
1936 if (ids[i] >= IGB_NB_XSTATS) {
1937 PMD_INIT_LOG(ERR, "id value isn't valid");
1940 strcpy(xstats_names[i].name,
1941 xstats_names_copy[ids[i]].name);
1948 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1951 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952 struct e1000_hw_stats *hw_stats =
1953 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1956 if (n < IGB_NB_XSTATS)
1957 return IGB_NB_XSTATS;
1959 igb_read_stats_registers(hw, hw_stats);
1961 /* If this is a reset xstats is NULL, and we have cleared the
1962 * registers by reading them.
1967 /* Extended stats */
1968 for (i = 0; i < IGB_NB_XSTATS; i++) {
1970 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1971 rte_igb_stats_strings[i].offset);
1974 return IGB_NB_XSTATS;
1978 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1979 uint64_t *values, unsigned int n)
1984 struct e1000_hw *hw =
1985 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986 struct e1000_hw_stats *hw_stats =
1987 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1989 if (n < IGB_NB_XSTATS)
1990 return IGB_NB_XSTATS;
1992 igb_read_stats_registers(hw, hw_stats);
1994 /* If this is a reset xstats is NULL, and we have cleared the
1995 * registers by reading them.
2000 /* Extended stats */
2001 for (i = 0; i < IGB_NB_XSTATS; i++)
2002 values[i] = *(uint64_t *)(((char *)hw_stats) +
2003 rte_igb_stats_strings[i].offset);
2005 return IGB_NB_XSTATS;
2008 uint64_t values_copy[IGB_NB_XSTATS];
2010 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2013 for (i = 0; i < n; i++) {
2014 if (ids[i] >= IGB_NB_XSTATS) {
2015 PMD_INIT_LOG(ERR, "id value isn't valid");
2018 values[i] = values_copy[ids[i]];
2025 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2027 /* Good Rx packets, include VF loopback */
2028 UPDATE_VF_STAT(E1000_VFGPRC,
2029 hw_stats->last_gprc, hw_stats->gprc);
2031 /* Good Rx octets, include VF loopback */
2032 UPDATE_VF_STAT(E1000_VFGORC,
2033 hw_stats->last_gorc, hw_stats->gorc);
2035 /* Good Tx packets, include VF loopback */
2036 UPDATE_VF_STAT(E1000_VFGPTC,
2037 hw_stats->last_gptc, hw_stats->gptc);
2039 /* Good Tx octets, include VF loopback */
2040 UPDATE_VF_STAT(E1000_VFGOTC,
2041 hw_stats->last_gotc, hw_stats->gotc);
2043 /* Rx Multicst packets */
2044 UPDATE_VF_STAT(E1000_VFMPRC,
2045 hw_stats->last_mprc, hw_stats->mprc);
2047 /* Good Rx loopback packets */
2048 UPDATE_VF_STAT(E1000_VFGPRLBC,
2049 hw_stats->last_gprlbc, hw_stats->gprlbc);
2051 /* Good Rx loopback octets */
2052 UPDATE_VF_STAT(E1000_VFGORLBC,
2053 hw_stats->last_gorlbc, hw_stats->gorlbc);
2055 /* Good Tx loopback packets */
2056 UPDATE_VF_STAT(E1000_VFGPTLBC,
2057 hw_stats->last_gptlbc, hw_stats->gptlbc);
2059 /* Good Tx loopback octets */
2060 UPDATE_VF_STAT(E1000_VFGOTLBC,
2061 hw_stats->last_gotlbc, hw_stats->gotlbc);
2064 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2065 struct rte_eth_xstat_name *xstats_names,
2066 __rte_unused unsigned limit)
2070 if (xstats_names != NULL)
2071 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2072 strlcpy(xstats_names[i].name,
2073 rte_igbvf_stats_strings[i].name,
2074 sizeof(xstats_names[i].name));
2076 return IGBVF_NB_XSTATS;
2080 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2083 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2085 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2088 if (n < IGBVF_NB_XSTATS)
2089 return IGBVF_NB_XSTATS;
2091 igbvf_read_stats_registers(hw, hw_stats);
2096 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2098 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2099 rte_igbvf_stats_strings[i].offset);
2102 return IGBVF_NB_XSTATS;
2106 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2108 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2110 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2112 igbvf_read_stats_registers(hw, hw_stats);
2114 if (rte_stats == NULL)
2117 rte_stats->ipackets = hw_stats->gprc;
2118 rte_stats->ibytes = hw_stats->gorc;
2119 rte_stats->opackets = hw_stats->gptc;
2120 rte_stats->obytes = hw_stats->gotc;
2125 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2127 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2128 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2130 /* Sync HW register to the last stats */
2131 eth_igbvf_stats_get(dev, NULL);
2133 /* reset HW current stats*/
2134 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2135 offsetof(struct e1000_vf_stats, gprc));
2141 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2144 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145 struct e1000_fw_version fw;
2148 e1000_get_fw_version(hw, &fw);
2150 switch (hw->mac.type) {
2153 if (!(e1000_get_flash_presence_i210(hw))) {
2154 ret = snprintf(fw_version, fw_size,
2156 fw.invm_major, fw.invm_minor,
2162 /* if option rom is valid, display its version too */
2164 ret = snprintf(fw_version, fw_size,
2165 "%d.%d, 0x%08x, %d.%d.%d",
2166 fw.eep_major, fw.eep_minor, fw.etrack_id,
2167 fw.or_major, fw.or_build, fw.or_patch);
2170 if (fw.etrack_id != 0X0000) {
2171 ret = snprintf(fw_version, fw_size,
2173 fw.eep_major, fw.eep_minor,
2176 ret = snprintf(fw_version, fw_size,
2178 fw.eep_major, fw.eep_minor,
2185 ret += 1; /* add the size of '\0' */
2186 if (fw_size < (u32)ret)
2193 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2195 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2197 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2198 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2199 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2200 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2201 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2202 dev_info->rx_queue_offload_capa;
2203 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2204 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2205 dev_info->tx_queue_offload_capa;
2207 switch (hw->mac.type) {
2209 dev_info->max_rx_queues = 4;
2210 dev_info->max_tx_queues = 4;
2211 dev_info->max_vmdq_pools = 0;
2215 dev_info->max_rx_queues = 16;
2216 dev_info->max_tx_queues = 16;
2217 dev_info->max_vmdq_pools = ETH_8_POOLS;
2218 dev_info->vmdq_queue_num = 16;
2222 dev_info->max_rx_queues = 8;
2223 dev_info->max_tx_queues = 8;
2224 dev_info->max_vmdq_pools = ETH_8_POOLS;
2225 dev_info->vmdq_queue_num = 8;
2229 dev_info->max_rx_queues = 8;
2230 dev_info->max_tx_queues = 8;
2231 dev_info->max_vmdq_pools = ETH_8_POOLS;
2232 dev_info->vmdq_queue_num = 8;
2236 dev_info->max_rx_queues = 8;
2237 dev_info->max_tx_queues = 8;
2241 dev_info->max_rx_queues = 4;
2242 dev_info->max_tx_queues = 4;
2243 dev_info->max_vmdq_pools = 0;
2247 dev_info->max_rx_queues = 2;
2248 dev_info->max_tx_queues = 2;
2249 dev_info->max_vmdq_pools = 0;
2253 /* Should not happen */
2256 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2257 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2258 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2260 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2262 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2263 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2264 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2266 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2271 dev_info->default_txconf = (struct rte_eth_txconf) {
2273 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2274 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2275 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2280 dev_info->rx_desc_lim = rx_desc_lim;
2281 dev_info->tx_desc_lim = tx_desc_lim;
2283 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2284 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2287 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2288 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2293 static const uint32_t *
2294 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2296 static const uint32_t ptypes[] = {
2297 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2300 RTE_PTYPE_L3_IPV4_EXT,
2302 RTE_PTYPE_L3_IPV6_EXT,
2306 RTE_PTYPE_TUNNEL_IP,
2307 RTE_PTYPE_INNER_L3_IPV6,
2308 RTE_PTYPE_INNER_L3_IPV6_EXT,
2309 RTE_PTYPE_INNER_L4_TCP,
2310 RTE_PTYPE_INNER_L4_UDP,
2314 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2315 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2321 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2323 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2325 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2326 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2327 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2328 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2329 DEV_TX_OFFLOAD_IPV4_CKSUM |
2330 DEV_TX_OFFLOAD_UDP_CKSUM |
2331 DEV_TX_OFFLOAD_TCP_CKSUM |
2332 DEV_TX_OFFLOAD_SCTP_CKSUM |
2333 DEV_TX_OFFLOAD_TCP_TSO;
2334 switch (hw->mac.type) {
2336 dev_info->max_rx_queues = 2;
2337 dev_info->max_tx_queues = 2;
2339 case e1000_vfadapt_i350:
2340 dev_info->max_rx_queues = 1;
2341 dev_info->max_tx_queues = 1;
2344 /* Should not happen */
2348 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2349 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2350 dev_info->rx_queue_offload_capa;
2351 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2352 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2353 dev_info->tx_queue_offload_capa;
2355 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2357 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2358 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2359 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2361 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2366 dev_info->default_txconf = (struct rte_eth_txconf) {
2368 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2369 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2370 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2375 dev_info->rx_desc_lim = rx_desc_lim;
2376 dev_info->tx_desc_lim = tx_desc_lim;
2381 /* return 0 means link status changed, -1 means not changed */
2383 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2385 struct e1000_hw *hw =
2386 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387 struct rte_eth_link link;
2388 int link_check, count;
2391 hw->mac.get_link_status = 1;
2393 /* possible wait-to-complete in up to 9 seconds */
2394 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2395 /* Read the real link status */
2396 switch (hw->phy.media_type) {
2397 case e1000_media_type_copper:
2398 /* Do the work to read phy */
2399 e1000_check_for_link(hw);
2400 link_check = !hw->mac.get_link_status;
2403 case e1000_media_type_fiber:
2404 e1000_check_for_link(hw);
2405 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2409 case e1000_media_type_internal_serdes:
2410 e1000_check_for_link(hw);
2411 link_check = hw->mac.serdes_has_link;
2414 /* VF device is type_unknown */
2415 case e1000_media_type_unknown:
2416 eth_igbvf_link_update(hw);
2417 link_check = !hw->mac.get_link_status;
2423 if (link_check || wait_to_complete == 0)
2425 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2427 memset(&link, 0, sizeof(link));
2429 /* Now we check if a transition has happened */
2431 uint16_t duplex, speed;
2432 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2433 link.link_duplex = (duplex == FULL_DUPLEX) ?
2434 ETH_LINK_FULL_DUPLEX :
2435 ETH_LINK_HALF_DUPLEX;
2436 link.link_speed = speed;
2437 link.link_status = ETH_LINK_UP;
2438 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2439 ETH_LINK_SPEED_FIXED);
2440 } else if (!link_check) {
2441 link.link_speed = 0;
2442 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2443 link.link_status = ETH_LINK_DOWN;
2444 link.link_autoneg = ETH_LINK_FIXED;
2447 return rte_eth_linkstatus_set(dev, &link);
2451 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2452 * For ASF and Pass Through versions of f/w this means
2453 * that the driver is loaded.
2456 igb_hw_control_acquire(struct e1000_hw *hw)
2460 /* Let firmware know the driver has taken over */
2461 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2462 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2466 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2467 * For ASF and Pass Through versions of f/w this means that the
2468 * driver is no longer loaded.
2471 igb_hw_control_release(struct e1000_hw *hw)
2475 /* Let firmware taken over control of h/w */
2476 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2477 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2478 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2482 * Bit of a misnomer, what this really means is
2483 * to enable OS management of the system... aka
2484 * to disable special hardware management features.
2487 igb_init_manageability(struct e1000_hw *hw)
2489 if (e1000_enable_mng_pass_thru(hw)) {
2490 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2491 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2493 /* disable hardware interception of ARP */
2494 manc &= ~(E1000_MANC_ARP_EN);
2496 /* enable receiving management packets to the host */
2497 manc |= E1000_MANC_EN_MNG2HOST;
2498 manc2h |= 1 << 5; /* Mng Port 623 */
2499 manc2h |= 1 << 6; /* Mng Port 664 */
2500 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2501 E1000_WRITE_REG(hw, E1000_MANC, manc);
2506 igb_release_manageability(struct e1000_hw *hw)
2508 if (e1000_enable_mng_pass_thru(hw)) {
2509 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2511 manc |= E1000_MANC_ARP_EN;
2512 manc &= ~E1000_MANC_EN_MNG2HOST;
2514 E1000_WRITE_REG(hw, E1000_MANC, manc);
2519 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2521 struct e1000_hw *hw =
2522 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2525 rctl = E1000_READ_REG(hw, E1000_RCTL);
2526 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2527 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2533 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2535 struct e1000_hw *hw =
2536 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539 rctl = E1000_READ_REG(hw, E1000_RCTL);
2540 rctl &= (~E1000_RCTL_UPE);
2541 if (dev->data->all_multicast == 1)
2542 rctl |= E1000_RCTL_MPE;
2544 rctl &= (~E1000_RCTL_MPE);
2545 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2551 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2553 struct e1000_hw *hw =
2554 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2557 rctl = E1000_READ_REG(hw, E1000_RCTL);
2558 rctl |= E1000_RCTL_MPE;
2559 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2565 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2567 struct e1000_hw *hw =
2568 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2571 if (dev->data->promiscuous == 1)
2572 return 0; /* must remain in all_multicast mode */
2573 rctl = E1000_READ_REG(hw, E1000_RCTL);
2574 rctl &= (~E1000_RCTL_MPE);
2575 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2581 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2583 struct e1000_hw *hw =
2584 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585 struct e1000_vfta * shadow_vfta =
2586 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2591 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2592 E1000_VFTA_ENTRY_MASK);
2593 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2594 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2599 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2601 /* update local VFTA copy */
2602 shadow_vfta->vfta[vid_idx] = vfta;
2608 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2609 enum rte_vlan_type vlan_type,
2612 struct e1000_hw *hw =
2613 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2617 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2619 /* only outer TPID of double VLAN can be configured*/
2620 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2621 reg = E1000_READ_REG(hw, E1000_VET);
2622 reg = (reg & (~E1000_VET_VET_EXT)) |
2623 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2624 E1000_WRITE_REG(hw, E1000_VET, reg);
2629 /* all other TPID values are read-only*/
2630 PMD_DRV_LOG(ERR, "Not supported");
2636 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2638 struct e1000_hw *hw =
2639 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642 /* Filter Table Disable */
2643 reg = E1000_READ_REG(hw, E1000_RCTL);
2644 reg &= ~E1000_RCTL_CFIEN;
2645 reg &= ~E1000_RCTL_VFE;
2646 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2650 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2652 struct e1000_hw *hw =
2653 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654 struct e1000_vfta * shadow_vfta =
2655 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2659 /* Filter Table Enable, CFI not used for packet acceptance */
2660 reg = E1000_READ_REG(hw, E1000_RCTL);
2661 reg &= ~E1000_RCTL_CFIEN;
2662 reg |= E1000_RCTL_VFE;
2663 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2665 /* restore VFTA table */
2666 for (i = 0; i < IGB_VFTA_SIZE; i++)
2667 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2671 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2673 struct e1000_hw *hw =
2674 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2677 /* VLAN Mode Disable */
2678 reg = E1000_READ_REG(hw, E1000_CTRL);
2679 reg &= ~E1000_CTRL_VME;
2680 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2684 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2686 struct e1000_hw *hw =
2687 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690 /* VLAN Mode Enable */
2691 reg = E1000_READ_REG(hw, E1000_CTRL);
2692 reg |= E1000_CTRL_VME;
2693 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2697 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2699 struct e1000_hw *hw =
2700 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2703 /* CTRL_EXT: Extended VLAN */
2704 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2705 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2706 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2708 /* Update maximum packet length */
2709 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2710 E1000_WRITE_REG(hw, E1000_RLPML,
2711 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2716 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2718 struct e1000_hw *hw =
2719 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2722 /* CTRL_EXT: Extended VLAN */
2723 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2724 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2725 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2727 /* Update maximum packet length */
2728 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2729 E1000_WRITE_REG(hw, E1000_RLPML,
2730 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2735 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2737 struct rte_eth_rxmode *rxmode;
2739 rxmode = &dev->data->dev_conf.rxmode;
2740 if(mask & ETH_VLAN_STRIP_MASK){
2741 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2742 igb_vlan_hw_strip_enable(dev);
2744 igb_vlan_hw_strip_disable(dev);
2747 if(mask & ETH_VLAN_FILTER_MASK){
2748 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2749 igb_vlan_hw_filter_enable(dev);
2751 igb_vlan_hw_filter_disable(dev);
2754 if(mask & ETH_VLAN_EXTEND_MASK){
2755 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2756 igb_vlan_hw_extend_enable(dev);
2758 igb_vlan_hw_extend_disable(dev);
2766 * It enables the interrupt mask and then enable the interrupt.
2769 * Pointer to struct rte_eth_dev.
2774 * - On success, zero.
2775 * - On failure, a negative value.
2778 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2780 struct e1000_interrupt *intr =
2781 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2784 intr->mask |= E1000_ICR_LSC;
2786 intr->mask &= ~E1000_ICR_LSC;
2791 /* It clears the interrupt causes and enables the interrupt.
2792 * It will be called once only during nic initialized.
2795 * Pointer to struct rte_eth_dev.
2798 * - On success, zero.
2799 * - On failure, a negative value.
2801 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2803 uint32_t mask, regval;
2805 struct e1000_hw *hw =
2806 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2808 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2809 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2810 struct rte_eth_dev_info dev_info;
2812 memset(&dev_info, 0, sizeof(dev_info));
2813 ret = eth_igb_infos_get(dev, &dev_info);
2817 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2818 regval = E1000_READ_REG(hw, E1000_EIMS);
2819 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2825 * It reads ICR and gets interrupt causes, check it and set a bit flag
2826 * to update link status.
2829 * Pointer to struct rte_eth_dev.
2832 * - On success, zero.
2833 * - On failure, a negative value.
2836 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2839 struct e1000_hw *hw =
2840 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841 struct e1000_interrupt *intr =
2842 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2844 igb_intr_disable(dev);
2846 /* read-on-clear nic registers here */
2847 icr = E1000_READ_REG(hw, E1000_ICR);
2850 if (icr & E1000_ICR_LSC) {
2851 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2854 if (icr & E1000_ICR_VMMB)
2855 intr->flags |= E1000_FLAG_MAILBOX;
2861 * It executes link_update after knowing an interrupt is prsent.
2864 * Pointer to struct rte_eth_dev.
2867 * - On success, zero.
2868 * - On failure, a negative value.
2871 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2872 struct rte_intr_handle *intr_handle)
2874 struct e1000_hw *hw =
2875 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 struct e1000_interrupt *intr =
2877 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2878 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2879 struct rte_eth_link link;
2882 if (intr->flags & E1000_FLAG_MAILBOX) {
2883 igb_pf_mbx_process(dev);
2884 intr->flags &= ~E1000_FLAG_MAILBOX;
2887 igb_intr_enable(dev);
2888 rte_intr_ack(intr_handle);
2890 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2891 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2893 /* set get_link_status to check register later */
2894 hw->mac.get_link_status = 1;
2895 ret = eth_igb_link_update(dev, 0);
2897 /* check if link has changed */
2901 rte_eth_linkstatus_get(dev, &link);
2902 if (link.link_status) {
2904 " Port %d: Link Up - speed %u Mbps - %s",
2906 (unsigned)link.link_speed,
2907 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2908 "full-duplex" : "half-duplex");
2910 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2911 dev->data->port_id);
2914 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2915 pci_dev->addr.domain,
2917 pci_dev->addr.devid,
2918 pci_dev->addr.function);
2919 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2927 * Interrupt handler which shall be registered at first.
2930 * Pointer to interrupt handle.
2932 * The address of parameter (struct rte_eth_dev *) regsitered before.
2938 eth_igb_interrupt_handler(void *param)
2940 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2942 eth_igb_interrupt_get_status(dev);
2943 eth_igb_interrupt_action(dev, dev->intr_handle);
2947 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2950 struct e1000_hw *hw =
2951 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952 struct e1000_interrupt *intr =
2953 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2955 igbvf_intr_disable(hw);
2957 /* read-on-clear nic registers here */
2958 eicr = E1000_READ_REG(hw, E1000_EICR);
2961 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2962 intr->flags |= E1000_FLAG_MAILBOX;
2967 void igbvf_mbx_process(struct rte_eth_dev *dev)
2969 struct e1000_hw *hw =
2970 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971 struct e1000_mbx_info *mbx = &hw->mbx;
2974 /* peek the message first */
2975 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2977 /* PF reset VF event */
2978 if (in_msg == E1000_PF_CONTROL_MSG) {
2979 /* dummy mbx read to ack pf */
2980 if (mbx->ops.read(hw, &in_msg, 1, 0))
2982 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2988 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2990 struct e1000_interrupt *intr =
2991 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2993 if (intr->flags & E1000_FLAG_MAILBOX) {
2994 igbvf_mbx_process(dev);
2995 intr->flags &= ~E1000_FLAG_MAILBOX;
2998 igbvf_intr_enable(dev);
2999 rte_intr_ack(intr_handle);
3005 eth_igbvf_interrupt_handler(void *param)
3007 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3009 eth_igbvf_interrupt_get_status(dev);
3010 eth_igbvf_interrupt_action(dev, dev->intr_handle);
3014 eth_igb_led_on(struct rte_eth_dev *dev)
3016 struct e1000_hw *hw;
3018 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3023 eth_igb_led_off(struct rte_eth_dev *dev)
3025 struct e1000_hw *hw;
3027 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3032 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3034 struct e1000_hw *hw;
3039 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3040 fc_conf->pause_time = hw->fc.pause_time;
3041 fc_conf->high_water = hw->fc.high_water;
3042 fc_conf->low_water = hw->fc.low_water;
3043 fc_conf->send_xon = hw->fc.send_xon;
3044 fc_conf->autoneg = hw->mac.autoneg;
3047 * Return rx_pause and tx_pause status according to actual setting of
3048 * the TFCE and RFCE bits in the CTRL register.
3050 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3051 if (ctrl & E1000_CTRL_TFCE)
3056 if (ctrl & E1000_CTRL_RFCE)
3061 if (rx_pause && tx_pause)
3062 fc_conf->mode = RTE_FC_FULL;
3064 fc_conf->mode = RTE_FC_RX_PAUSE;
3066 fc_conf->mode = RTE_FC_TX_PAUSE;
3068 fc_conf->mode = RTE_FC_NONE;
3074 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3076 struct e1000_hw *hw;
3078 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3084 uint32_t rx_buf_size;
3085 uint32_t max_high_water;
3088 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3089 if (fc_conf->autoneg != hw->mac.autoneg)
3091 rx_buf_size = igb_get_rx_buffer_size(hw);
3092 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3094 /* At least reserve one Ethernet frame for watermark */
3095 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3096 if ((fc_conf->high_water > max_high_water) ||
3097 (fc_conf->high_water < fc_conf->low_water)) {
3098 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3099 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3103 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3104 hw->fc.pause_time = fc_conf->pause_time;
3105 hw->fc.high_water = fc_conf->high_water;
3106 hw->fc.low_water = fc_conf->low_water;
3107 hw->fc.send_xon = fc_conf->send_xon;
3109 err = e1000_setup_link_generic(hw);
3110 if (err == E1000_SUCCESS) {
3112 /* check if we want to forward MAC frames - driver doesn't have native
3113 * capability to do that, so we'll write the registers ourselves */
3115 rctl = E1000_READ_REG(hw, E1000_RCTL);
3117 /* set or clear MFLCN.PMCF bit depending on configuration */
3118 if (fc_conf->mac_ctrl_frame_fwd != 0)
3119 rctl |= E1000_RCTL_PMCF;
3121 rctl &= ~E1000_RCTL_PMCF;
3123 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3124 E1000_WRITE_FLUSH(hw);
3129 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3133 #define E1000_RAH_POOLSEL_SHIFT (18)
3135 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3136 uint32_t index, uint32_t pool)
3138 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3141 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3142 rah = E1000_READ_REG(hw, E1000_RAH(index));
3143 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3144 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3149 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3151 uint8_t addr[RTE_ETHER_ADDR_LEN];
3152 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3154 memset(addr, 0, sizeof(addr));
3156 e1000_rar_set(hw, addr, index);
3160 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3161 struct rte_ether_addr *addr)
3163 eth_igb_rar_clear(dev, 0);
3164 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3169 * Virtual Function operations
3172 igbvf_intr_disable(struct e1000_hw *hw)
3174 PMD_INIT_FUNC_TRACE();
3176 /* Clear interrupt mask to stop from interrupts being generated */
3177 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3179 E1000_WRITE_FLUSH(hw);
3183 igbvf_stop_adapter(struct rte_eth_dev *dev)
3187 struct rte_eth_dev_info dev_info;
3188 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3191 memset(&dev_info, 0, sizeof(dev_info));
3192 ret = eth_igbvf_infos_get(dev, &dev_info);
3196 /* Clear interrupt mask to stop from interrupts being generated */
3197 igbvf_intr_disable(hw);
3199 /* Clear any pending interrupts, flush previous writes */
3200 E1000_READ_REG(hw, E1000_EICR);
3202 /* Disable the transmit unit. Each queue must be disabled. */
3203 for (i = 0; i < dev_info.max_tx_queues; i++)
3204 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3206 /* Disable the receive unit by stopping each queue */
3207 for (i = 0; i < dev_info.max_rx_queues; i++) {
3208 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3209 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3210 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3211 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3215 /* flush all queues disables */
3216 E1000_WRITE_FLUSH(hw);
3220 static int eth_igbvf_link_update(struct e1000_hw *hw)
3222 struct e1000_mbx_info *mbx = &hw->mbx;
3223 struct e1000_mac_info *mac = &hw->mac;
3224 int ret_val = E1000_SUCCESS;
3226 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3229 * We only want to run this if there has been a rst asserted.
3230 * in this case that could mean a link change, device reset,
3231 * or a virtual function reset
3234 /* If we were hit with a reset or timeout drop the link */
3235 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3236 mac->get_link_status = TRUE;
3238 if (!mac->get_link_status)
3241 /* if link status is down no point in checking to see if pf is up */
3242 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3245 /* if we passed all the tests above then the link is up and we no
3246 * longer need to check for link */
3247 mac->get_link_status = FALSE;
3255 igbvf_dev_configure(struct rte_eth_dev *dev)
3257 struct rte_eth_conf* conf = &dev->data->dev_conf;
3259 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3260 dev->data->port_id);
3262 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3265 * VF has no ability to enable/disable HW CRC
3266 * Keep the persistent behavior the same as Host PF
3268 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3269 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3270 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3271 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3274 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3275 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3276 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3284 igbvf_dev_start(struct rte_eth_dev *dev)
3286 struct e1000_hw *hw =
3287 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288 struct e1000_adapter *adapter =
3289 E1000_DEV_PRIVATE(dev->data->dev_private);
3290 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3291 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3293 uint32_t intr_vector = 0;
3295 PMD_INIT_FUNC_TRACE();
3297 hw->mac.ops.reset_hw(hw);
3298 adapter->stopped = 0;
3301 igbvf_set_vfta_all(dev,1);
3303 eth_igbvf_tx_init(dev);
3305 /* This can fail when allocating mbufs for descriptor rings */
3306 ret = eth_igbvf_rx_init(dev);
3308 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3309 igb_dev_clear_queues(dev);
3313 /* check and configure queue intr-vector mapping */
3314 if (rte_intr_cap_multiple(intr_handle) &&
3315 dev->data->dev_conf.intr_conf.rxq) {
3316 intr_vector = dev->data->nb_rx_queues;
3317 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3322 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3323 intr_handle->intr_vec =
3324 rte_zmalloc("intr_vec",
3325 dev->data->nb_rx_queues * sizeof(int), 0);
3326 if (!intr_handle->intr_vec) {
3327 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3328 " intr_vec", dev->data->nb_rx_queues);
3333 eth_igbvf_configure_msix_intr(dev);
3335 /* enable uio/vfio intr/eventfd mapping */
3336 rte_intr_enable(intr_handle);
3338 /* resume enabled intr since hw reset */
3339 igbvf_intr_enable(dev);
3345 igbvf_dev_stop(struct rte_eth_dev *dev)
3347 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3348 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3349 struct e1000_adapter *adapter =
3350 E1000_DEV_PRIVATE(dev->data->dev_private);
3352 if (adapter->stopped)
3355 PMD_INIT_FUNC_TRACE();
3357 igbvf_stop_adapter(dev);
3360 * Clear what we set, but we still keep shadow_vfta to
3361 * restore after device starts
3363 igbvf_set_vfta_all(dev,0);
3365 igb_dev_clear_queues(dev);
3367 /* disable intr eventfd mapping */
3368 rte_intr_disable(intr_handle);
3370 /* Clean datapath event and queue/vec mapping */
3371 rte_intr_efd_disable(intr_handle);
3372 if (intr_handle->intr_vec) {
3373 rte_free(intr_handle->intr_vec);
3374 intr_handle->intr_vec = NULL;
3377 adapter->stopped = true;
3381 igbvf_dev_close(struct rte_eth_dev *dev)
3383 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3384 struct rte_ether_addr addr;
3385 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3387 PMD_INIT_FUNC_TRACE();
3391 igbvf_dev_stop(dev);
3393 igb_dev_free_queues(dev);
3396 * reprogram the RAR with a zero mac address,
3397 * to ensure that the VF traffic goes to the PF
3398 * after stop, close and detach of the VF.
3401 memset(&addr, 0, sizeof(addr));
3402 igbvf_default_mac_addr_set(dev, &addr);
3404 dev->dev_ops = NULL;
3405 dev->rx_pkt_burst = NULL;
3406 dev->tx_pkt_burst = NULL;
3408 rte_intr_callback_unregister(&pci_dev->intr_handle,
3409 eth_igbvf_interrupt_handler,
3414 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3416 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3418 /* Set both unicast and multicast promisc */
3419 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3425 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3427 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3429 /* If in allmulticast mode leave multicast promisc */
3430 if (dev->data->all_multicast == 1)
3431 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3433 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3439 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3441 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3443 /* In promiscuous mode multicast promisc already set */
3444 if (dev->data->promiscuous == 0)
3445 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3451 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3453 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3455 /* In promiscuous mode leave multicast promisc enabled */
3456 if (dev->data->promiscuous == 0)
3457 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3462 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3464 struct e1000_mbx_info *mbx = &hw->mbx;
3468 /* After set vlan, vlan strip will also be enabled in igb driver*/
3469 msgbuf[0] = E1000_VF_SET_VLAN;
3471 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3473 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3475 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3479 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3483 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3484 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3491 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3493 struct e1000_hw *hw =
3494 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3495 struct e1000_vfta * shadow_vfta =
3496 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3497 int i = 0, j = 0, vfta = 0, mask = 1;
3499 for (i = 0; i < IGB_VFTA_SIZE; i++){
3500 vfta = shadow_vfta->vfta[i];
3503 for (j = 0; j < 32; j++){
3506 (uint16_t)((i<<5)+j), on);
3515 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3517 struct e1000_hw *hw =
3518 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519 struct e1000_vfta * shadow_vfta =
3520 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3521 uint32_t vid_idx = 0;
3522 uint32_t vid_bit = 0;
3525 PMD_INIT_FUNC_TRACE();
3527 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3528 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3530 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3533 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3534 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3536 /*Save what we set and retore it after device reset*/
3538 shadow_vfta->vfta[vid_idx] |= vid_bit;
3540 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3546 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3548 struct e1000_hw *hw =
3549 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3551 /* index is not used by rar_set() */
3552 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3558 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3559 struct rte_eth_rss_reta_entry64 *reta_conf,
3564 uint16_t idx, shift;
3565 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3567 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3568 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3569 "(%d) doesn't match the number hardware can supported "
3570 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3574 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3575 idx = i / RTE_RETA_GROUP_SIZE;
3576 shift = i % RTE_RETA_GROUP_SIZE;
3577 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3581 if (mask == IGB_4_BIT_MASK)
3584 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3585 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3586 if (mask & (0x1 << j))
3587 reta |= reta_conf[idx].reta[shift + j] <<
3590 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3592 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3599 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3600 struct rte_eth_rss_reta_entry64 *reta_conf,
3605 uint16_t idx, shift;
3606 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3609 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3610 "(%d) doesn't match the number hardware can supported "
3611 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3615 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3616 idx = i / RTE_RETA_GROUP_SIZE;
3617 shift = i % RTE_RETA_GROUP_SIZE;
3618 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3622 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3623 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3624 if (mask & (0x1 << j))
3625 reta_conf[idx].reta[shift + j] =
3626 ((reta >> (CHAR_BIT * j)) &
3635 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3636 struct rte_eth_syn_filter *filter,
3639 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640 struct e1000_filter_info *filter_info =
3641 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3642 uint32_t synqf, rfctl;
3644 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3647 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3650 if (synqf & E1000_SYN_FILTER_ENABLE)
3653 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3654 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3656 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3657 if (filter->hig_pri)
3658 rfctl |= E1000_RFCTL_SYNQFP;
3660 rfctl &= ~E1000_RFCTL_SYNQFP;
3662 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3664 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3669 filter_info->syn_info = synqf;
3670 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3671 E1000_WRITE_FLUSH(hw);
3676 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3677 struct rte_eth_syn_filter *filter)
3679 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3680 uint32_t synqf, rfctl;
3682 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3683 if (synqf & E1000_SYN_FILTER_ENABLE) {
3684 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3685 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3686 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3687 E1000_SYN_FILTER_QUEUE_SHIFT);
3695 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3696 enum rte_filter_op filter_op,
3699 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702 MAC_TYPE_FILTER_SUP(hw->mac.type);
3704 if (filter_op == RTE_ETH_FILTER_NOP)
3708 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3713 switch (filter_op) {
3714 case RTE_ETH_FILTER_ADD:
3715 ret = eth_igb_syn_filter_set(dev,
3716 (struct rte_eth_syn_filter *)arg,
3719 case RTE_ETH_FILTER_DELETE:
3720 ret = eth_igb_syn_filter_set(dev,
3721 (struct rte_eth_syn_filter *)arg,
3724 case RTE_ETH_FILTER_GET:
3725 ret = eth_igb_syn_filter_get(dev,
3726 (struct rte_eth_syn_filter *)arg);
3729 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3737 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3739 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3740 struct e1000_2tuple_filter_info *filter_info)
3742 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3744 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3745 return -EINVAL; /* filter index is out of range. */
3746 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3747 return -EINVAL; /* flags is invalid. */
3749 switch (filter->dst_port_mask) {
3751 filter_info->dst_port_mask = 0;
3752 filter_info->dst_port = filter->dst_port;
3755 filter_info->dst_port_mask = 1;
3758 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3762 switch (filter->proto_mask) {
3764 filter_info->proto_mask = 0;
3765 filter_info->proto = filter->proto;
3768 filter_info->proto_mask = 1;
3771 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3775 filter_info->priority = (uint8_t)filter->priority;
3776 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3777 filter_info->tcp_flags = filter->tcp_flags;
3779 filter_info->tcp_flags = 0;
3784 static inline struct e1000_2tuple_filter *
3785 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3786 struct e1000_2tuple_filter_info *key)
3788 struct e1000_2tuple_filter *it;
3790 TAILQ_FOREACH(it, filter_list, entries) {
3791 if (memcmp(key, &it->filter_info,
3792 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3799 /* inject a igb 2tuple filter to HW */
3801 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3802 struct e1000_2tuple_filter *filter)
3804 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3805 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3806 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3810 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3811 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3812 imir |= E1000_IMIR_PORT_BP;
3814 imir &= ~E1000_IMIR_PORT_BP;
3816 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3818 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3819 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3820 ttqf |= (uint32_t)(filter->filter_info.proto &
3821 E1000_TTQF_PROTOCOL_MASK);
3822 if (filter->filter_info.proto_mask == 0)
3823 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3825 /* tcp flags bits setting. */
3826 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3827 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3828 imir_ext |= E1000_IMIREXT_CTRL_URG;
3829 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3830 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3831 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3832 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3833 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3834 imir_ext |= E1000_IMIREXT_CTRL_RST;
3835 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3836 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3837 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3838 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3840 imir_ext |= E1000_IMIREXT_CTRL_BP;
3842 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3843 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3844 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3848 * igb_add_2tuple_filter - add a 2tuple filter
3851 * dev: Pointer to struct rte_eth_dev.
3852 * ntuple_filter: ponter to the filter that will be added.
3855 * - On success, zero.
3856 * - On failure, a negative value.
3859 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3860 struct rte_eth_ntuple_filter *ntuple_filter)
3862 struct e1000_filter_info *filter_info =
3863 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3864 struct e1000_2tuple_filter *filter;
3867 filter = rte_zmalloc("e1000_2tuple_filter",
3868 sizeof(struct e1000_2tuple_filter), 0);
3872 ret = ntuple_filter_to_2tuple(ntuple_filter,
3873 &filter->filter_info);
3878 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3879 &filter->filter_info) != NULL) {
3880 PMD_DRV_LOG(ERR, "filter exists.");
3884 filter->queue = ntuple_filter->queue;
3887 * look for an unused 2tuple filter index,
3888 * and insert the filter to list.
3890 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3891 if (!(filter_info->twotuple_mask & (1 << i))) {
3892 filter_info->twotuple_mask |= 1 << i;
3894 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3900 if (i >= E1000_MAX_TTQF_FILTERS) {
3901 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3906 igb_inject_2uple_filter(dev, filter);
3911 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3912 struct e1000_2tuple_filter *filter)
3914 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3915 struct e1000_filter_info *filter_info =
3916 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3918 filter_info->twotuple_mask &= ~(1 << filter->index);
3919 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3922 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3923 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3924 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3929 * igb_remove_2tuple_filter - remove a 2tuple filter
3932 * dev: Pointer to struct rte_eth_dev.
3933 * ntuple_filter: ponter to the filter that will be removed.
3936 * - On success, zero.
3937 * - On failure, a negative value.
3940 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3941 struct rte_eth_ntuple_filter *ntuple_filter)
3943 struct e1000_filter_info *filter_info =
3944 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3945 struct e1000_2tuple_filter_info filter_2tuple;
3946 struct e1000_2tuple_filter *filter;
3949 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3950 ret = ntuple_filter_to_2tuple(ntuple_filter,
3955 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3957 if (filter == NULL) {
3958 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3962 igb_delete_2tuple_filter(dev, filter);
3967 /* inject a igb flex filter to HW */
3969 igb_inject_flex_filter(struct rte_eth_dev *dev,
3970 struct e1000_flex_filter *filter)
3972 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3973 uint32_t wufc, queueing;
3977 wufc = E1000_READ_REG(hw, E1000_WUFC);
3978 if (filter->index < E1000_MAX_FHFT)
3979 reg_off = E1000_FHFT(filter->index);
3981 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3983 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3984 (E1000_WUFC_FLX0 << filter->index));
3985 queueing = filter->filter_info.len |
3986 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3987 (filter->filter_info.priority <<
3988 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3989 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3992 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3993 E1000_WRITE_REG(hw, reg_off,
3994 filter->filter_info.dwords[j]);
3995 reg_off += sizeof(uint32_t);
3996 E1000_WRITE_REG(hw, reg_off,
3997 filter->filter_info.dwords[++j]);
3998 reg_off += sizeof(uint32_t);
3999 E1000_WRITE_REG(hw, reg_off,
4000 (uint32_t)filter->filter_info.mask[i]);
4001 reg_off += sizeof(uint32_t) * 2;
4006 static inline struct e1000_flex_filter *
4007 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4008 struct e1000_flex_filter_info *key)
4010 struct e1000_flex_filter *it;
4012 TAILQ_FOREACH(it, filter_list, entries) {
4013 if (memcmp(key, &it->filter_info,
4014 sizeof(struct e1000_flex_filter_info)) == 0)
4021 /* remove a flex byte filter
4023 * dev: Pointer to struct rte_eth_dev.
4024 * filter: the pointer of the filter will be removed.
4027 igb_remove_flex_filter(struct rte_eth_dev *dev,
4028 struct e1000_flex_filter *filter)
4030 struct e1000_filter_info *filter_info =
4031 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4032 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4036 wufc = E1000_READ_REG(hw, E1000_WUFC);
4037 if (filter->index < E1000_MAX_FHFT)
4038 reg_off = E1000_FHFT(filter->index);
4040 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4042 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4043 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4045 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4046 (~(E1000_WUFC_FLX0 << filter->index)));
4048 filter_info->flex_mask &= ~(1 << filter->index);
4049 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4054 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4055 struct rte_eth_flex_filter *filter,
4058 struct e1000_filter_info *filter_info =
4059 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4060 struct e1000_flex_filter *flex_filter, *it;
4064 flex_filter = rte_zmalloc("e1000_flex_filter",
4065 sizeof(struct e1000_flex_filter), 0);
4066 if (flex_filter == NULL)
4069 flex_filter->filter_info.len = filter->len;
4070 flex_filter->filter_info.priority = filter->priority;
4071 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4072 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4074 /* reverse bits in flex filter's mask*/
4075 for (shift = 0; shift < CHAR_BIT; shift++) {
4076 if (filter->mask[i] & (0x01 << shift))
4077 mask |= (0x80 >> shift);
4079 flex_filter->filter_info.mask[i] = mask;
4082 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4083 &flex_filter->filter_info);
4084 if (it == NULL && !add) {
4085 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4086 rte_free(flex_filter);
4089 if (it != NULL && add) {
4090 PMD_DRV_LOG(ERR, "filter exists.");
4091 rte_free(flex_filter);
4096 flex_filter->queue = filter->queue;
4098 * look for an unused flex filter index
4099 * and insert the filter into the list.
4101 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4102 if (!(filter_info->flex_mask & (1 << i))) {
4103 filter_info->flex_mask |= 1 << i;
4104 flex_filter->index = i;
4105 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4111 if (i >= E1000_MAX_FLEX_FILTERS) {
4112 PMD_DRV_LOG(ERR, "flex filters are full.");
4113 rte_free(flex_filter);
4117 igb_inject_flex_filter(dev, flex_filter);
4120 igb_remove_flex_filter(dev, it);
4121 rte_free(flex_filter);
4128 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4129 struct rte_eth_flex_filter *filter)
4131 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4132 struct e1000_filter_info *filter_info =
4133 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4134 struct e1000_flex_filter flex_filter, *it;
4135 uint32_t wufc, queueing, wufc_en = 0;
4137 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4138 flex_filter.filter_info.len = filter->len;
4139 flex_filter.filter_info.priority = filter->priority;
4140 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4141 memcpy(flex_filter.filter_info.mask, filter->mask,
4142 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4144 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4145 &flex_filter.filter_info);
4147 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4151 wufc = E1000_READ_REG(hw, E1000_WUFC);
4152 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4154 if ((wufc & wufc_en) == wufc_en) {
4155 uint32_t reg_off = 0;
4156 if (it->index < E1000_MAX_FHFT)
4157 reg_off = E1000_FHFT(it->index);
4159 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4161 queueing = E1000_READ_REG(hw,
4162 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4163 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4164 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4165 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4166 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4167 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4174 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4175 enum rte_filter_op filter_op,
4178 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4179 struct rte_eth_flex_filter *filter;
4182 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4184 if (filter_op == RTE_ETH_FILTER_NOP)
4188 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4193 filter = (struct rte_eth_flex_filter *)arg;
4194 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4195 || filter->len % sizeof(uint64_t) != 0) {
4196 PMD_DRV_LOG(ERR, "filter's length is out of range");
4199 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4200 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4204 switch (filter_op) {
4205 case RTE_ETH_FILTER_ADD:
4206 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4208 case RTE_ETH_FILTER_DELETE:
4209 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4211 case RTE_ETH_FILTER_GET:
4212 ret = eth_igb_get_flex_filter(dev, filter);
4215 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4223 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4225 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4226 struct e1000_5tuple_filter_info *filter_info)
4228 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4230 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4231 return -EINVAL; /* filter index is out of range. */
4232 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4233 return -EINVAL; /* flags is invalid. */
4235 switch (filter->dst_ip_mask) {
4237 filter_info->dst_ip_mask = 0;
4238 filter_info->dst_ip = filter->dst_ip;
4241 filter_info->dst_ip_mask = 1;
4244 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4248 switch (filter->src_ip_mask) {
4250 filter_info->src_ip_mask = 0;
4251 filter_info->src_ip = filter->src_ip;
4254 filter_info->src_ip_mask = 1;
4257 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4261 switch (filter->dst_port_mask) {
4263 filter_info->dst_port_mask = 0;
4264 filter_info->dst_port = filter->dst_port;
4267 filter_info->dst_port_mask = 1;
4270 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4274 switch (filter->src_port_mask) {
4276 filter_info->src_port_mask = 0;
4277 filter_info->src_port = filter->src_port;
4280 filter_info->src_port_mask = 1;
4283 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4287 switch (filter->proto_mask) {
4289 filter_info->proto_mask = 0;
4290 filter_info->proto = filter->proto;
4293 filter_info->proto_mask = 1;
4296 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4300 filter_info->priority = (uint8_t)filter->priority;
4301 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4302 filter_info->tcp_flags = filter->tcp_flags;
4304 filter_info->tcp_flags = 0;
4309 static inline struct e1000_5tuple_filter *
4310 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4311 struct e1000_5tuple_filter_info *key)
4313 struct e1000_5tuple_filter *it;
4315 TAILQ_FOREACH(it, filter_list, entries) {
4316 if (memcmp(key, &it->filter_info,
4317 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4324 /* inject a igb 5-tuple filter to HW */
4326 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4327 struct e1000_5tuple_filter *filter)
4329 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4330 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4331 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4335 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4336 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4337 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4338 if (filter->filter_info.dst_ip_mask == 0)
4339 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4340 if (filter->filter_info.src_port_mask == 0)
4341 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4342 if (filter->filter_info.proto_mask == 0)
4343 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4344 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4345 E1000_FTQF_QUEUE_MASK;
4346 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4347 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4348 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4349 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4351 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4352 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4354 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4355 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4356 imir |= E1000_IMIR_PORT_BP;
4358 imir &= ~E1000_IMIR_PORT_BP;
4359 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4361 /* tcp flags bits setting. */
4362 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4363 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4364 imir_ext |= E1000_IMIREXT_CTRL_URG;
4365 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4366 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4367 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4368 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4369 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4370 imir_ext |= E1000_IMIREXT_CTRL_RST;
4371 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4372 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4373 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4374 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4376 imir_ext |= E1000_IMIREXT_CTRL_BP;
4378 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4379 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4383 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4386 * dev: Pointer to struct rte_eth_dev.
4387 * ntuple_filter: ponter to the filter that will be added.
4390 * - On success, zero.
4391 * - On failure, a negative value.
4394 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4395 struct rte_eth_ntuple_filter *ntuple_filter)
4397 struct e1000_filter_info *filter_info =
4398 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4399 struct e1000_5tuple_filter *filter;
4403 filter = rte_zmalloc("e1000_5tuple_filter",
4404 sizeof(struct e1000_5tuple_filter), 0);
4408 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4409 &filter->filter_info);
4415 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4416 &filter->filter_info) != NULL) {
4417 PMD_DRV_LOG(ERR, "filter exists.");
4421 filter->queue = ntuple_filter->queue;
4424 * look for an unused 5tuple filter index,
4425 * and insert the filter to list.
4427 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4428 if (!(filter_info->fivetuple_mask & (1 << i))) {
4429 filter_info->fivetuple_mask |= 1 << i;
4431 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4437 if (i >= E1000_MAX_FTQF_FILTERS) {
4438 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4443 igb_inject_5tuple_filter_82576(dev, filter);
4448 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4449 struct e1000_5tuple_filter *filter)
4451 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4452 struct e1000_filter_info *filter_info =
4453 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4455 filter_info->fivetuple_mask &= ~(1 << filter->index);
4456 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4459 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4460 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4461 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4462 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4463 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4464 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4465 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4470 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4473 * dev: Pointer to struct rte_eth_dev.
4474 * ntuple_filter: ponter to the filter that will be removed.
4477 * - On success, zero.
4478 * - On failure, a negative value.
4481 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4482 struct rte_eth_ntuple_filter *ntuple_filter)
4484 struct e1000_filter_info *filter_info =
4485 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4486 struct e1000_5tuple_filter_info filter_5tuple;
4487 struct e1000_5tuple_filter *filter;
4490 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4491 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4496 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4498 if (filter == NULL) {
4499 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4503 igb_delete_5tuple_filter_82576(dev, filter);
4509 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4512 struct e1000_hw *hw;
4513 struct rte_eth_dev_info dev_info;
4514 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4517 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4519 #ifdef RTE_LIBRTE_82571_SUPPORT
4520 /* XXX: not bigger than max_rx_pktlen */
4521 if (hw->mac.type == e1000_82571)
4524 ret = eth_igb_infos_get(dev, &dev_info);
4528 /* check that mtu is within the allowed range */
4529 if (mtu < RTE_ETHER_MIN_MTU ||
4530 frame_size > dev_info.max_rx_pktlen)
4533 /* refuse mtu that requires the support of scattered packets when this
4534 * feature has not been enabled before. */
4535 if (!dev->data->scattered_rx &&
4536 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4539 rctl = E1000_READ_REG(hw, E1000_RCTL);
4541 /* switch to jumbo mode if needed */
4542 if (frame_size > RTE_ETHER_MAX_LEN) {
4543 dev->data->dev_conf.rxmode.offloads |=
4544 DEV_RX_OFFLOAD_JUMBO_FRAME;
4545 rctl |= E1000_RCTL_LPE;
4547 dev->data->dev_conf.rxmode.offloads &=
4548 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4549 rctl &= ~E1000_RCTL_LPE;
4551 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4553 /* update max frame size */
4554 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4556 E1000_WRITE_REG(hw, E1000_RLPML,
4557 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4563 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4566 * dev: Pointer to struct rte_eth_dev.
4567 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4568 * add: if true, add filter, if false, remove filter
4571 * - On success, zero.
4572 * - On failure, a negative value.
4575 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4576 struct rte_eth_ntuple_filter *ntuple_filter,
4579 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4582 switch (ntuple_filter->flags) {
4583 case RTE_5TUPLE_FLAGS:
4584 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4585 if (hw->mac.type != e1000_82576)
4588 ret = igb_add_5tuple_filter_82576(dev,
4591 ret = igb_remove_5tuple_filter_82576(dev,
4594 case RTE_2TUPLE_FLAGS:
4595 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4596 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4597 hw->mac.type != e1000_i210 &&
4598 hw->mac.type != e1000_i211)
4601 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4603 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4614 * igb_get_ntuple_filter - get a ntuple filter
4617 * dev: Pointer to struct rte_eth_dev.
4618 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4621 * - On success, zero.
4622 * - On failure, a negative value.
4625 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4626 struct rte_eth_ntuple_filter *ntuple_filter)
4628 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629 struct e1000_filter_info *filter_info =
4630 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4631 struct e1000_5tuple_filter_info filter_5tuple;
4632 struct e1000_2tuple_filter_info filter_2tuple;
4633 struct e1000_5tuple_filter *p_5tuple_filter;
4634 struct e1000_2tuple_filter *p_2tuple_filter;
4637 switch (ntuple_filter->flags) {
4638 case RTE_5TUPLE_FLAGS:
4639 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4640 if (hw->mac.type != e1000_82576)
4642 memset(&filter_5tuple,
4644 sizeof(struct e1000_5tuple_filter_info));
4645 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4649 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4650 &filter_info->fivetuple_list,
4652 if (p_5tuple_filter == NULL) {
4653 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4656 ntuple_filter->queue = p_5tuple_filter->queue;
4658 case RTE_2TUPLE_FLAGS:
4659 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4660 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4662 memset(&filter_2tuple,
4664 sizeof(struct e1000_2tuple_filter_info));
4665 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4668 p_2tuple_filter = igb_2tuple_filter_lookup(
4669 &filter_info->twotuple_list,
4671 if (p_2tuple_filter == NULL) {
4672 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4675 ntuple_filter->queue = p_2tuple_filter->queue;
4686 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4687 * @dev: pointer to rte_eth_dev structure
4688 * @filter_op:operation will be taken.
4689 * @arg: a pointer to specific structure corresponding to the filter_op
4692 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4693 enum rte_filter_op filter_op,
4696 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699 MAC_TYPE_FILTER_SUP(hw->mac.type);
4701 if (filter_op == RTE_ETH_FILTER_NOP)
4705 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4710 switch (filter_op) {
4711 case RTE_ETH_FILTER_ADD:
4712 ret = igb_add_del_ntuple_filter(dev,
4713 (struct rte_eth_ntuple_filter *)arg,
4716 case RTE_ETH_FILTER_DELETE:
4717 ret = igb_add_del_ntuple_filter(dev,
4718 (struct rte_eth_ntuple_filter *)arg,
4721 case RTE_ETH_FILTER_GET:
4722 ret = igb_get_ntuple_filter(dev,
4723 (struct rte_eth_ntuple_filter *)arg);
4726 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4734 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4739 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4740 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4741 (filter_info->ethertype_mask & (1 << i)))
4748 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4749 uint16_t ethertype, uint32_t etqf)
4753 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4754 if (!(filter_info->ethertype_mask & (1 << i))) {
4755 filter_info->ethertype_mask |= 1 << i;
4756 filter_info->ethertype_filters[i].ethertype = ethertype;
4757 filter_info->ethertype_filters[i].etqf = etqf;
4765 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4768 if (idx >= E1000_MAX_ETQF_FILTERS)
4770 filter_info->ethertype_mask &= ~(1 << idx);
4771 filter_info->ethertype_filters[idx].ethertype = 0;
4772 filter_info->ethertype_filters[idx].etqf = 0;
4778 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4779 struct rte_eth_ethertype_filter *filter,
4782 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4783 struct e1000_filter_info *filter_info =
4784 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4788 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4789 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4790 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4791 " ethertype filter.", filter->ether_type);
4795 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4796 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4799 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4800 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4804 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4805 if (ret >= 0 && add) {
4806 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4807 filter->ether_type);
4810 if (ret < 0 && !add) {
4811 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4812 filter->ether_type);
4817 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4818 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4819 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4820 ret = igb_ethertype_filter_insert(filter_info,
4821 filter->ether_type, etqf);
4823 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4827 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4831 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4832 E1000_WRITE_FLUSH(hw);
4838 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4839 struct rte_eth_ethertype_filter *filter)
4841 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4842 struct e1000_filter_info *filter_info =
4843 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4847 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4849 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4850 filter->ether_type);
4854 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4855 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4856 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4858 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4859 E1000_ETQF_QUEUE_SHIFT;
4867 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4868 * @dev: pointer to rte_eth_dev structure
4869 * @filter_op:operation will be taken.
4870 * @arg: a pointer to specific structure corresponding to the filter_op
4873 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4874 enum rte_filter_op filter_op,
4877 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4880 MAC_TYPE_FILTER_SUP(hw->mac.type);
4882 if (filter_op == RTE_ETH_FILTER_NOP)
4886 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4891 switch (filter_op) {
4892 case RTE_ETH_FILTER_ADD:
4893 ret = igb_add_del_ethertype_filter(dev,
4894 (struct rte_eth_ethertype_filter *)arg,
4897 case RTE_ETH_FILTER_DELETE:
4898 ret = igb_add_del_ethertype_filter(dev,
4899 (struct rte_eth_ethertype_filter *)arg,
4902 case RTE_ETH_FILTER_GET:
4903 ret = igb_get_ethertype_filter(dev,
4904 (struct rte_eth_ethertype_filter *)arg);
4907 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4915 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4916 enum rte_filter_type filter_type,
4917 enum rte_filter_op filter_op,
4922 switch (filter_type) {
4923 case RTE_ETH_FILTER_NTUPLE:
4924 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4926 case RTE_ETH_FILTER_ETHERTYPE:
4927 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4929 case RTE_ETH_FILTER_SYN:
4930 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4932 case RTE_ETH_FILTER_FLEXIBLE:
4933 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4935 case RTE_ETH_FILTER_GENERIC:
4936 if (filter_op != RTE_ETH_FILTER_GET)
4938 *(const void **)arg = &igb_flow_ops;
4941 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4950 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4951 struct rte_ether_addr *mc_addr_set,
4952 uint32_t nb_mc_addr)
4954 struct e1000_hw *hw;
4956 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4957 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4962 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4964 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4965 uint64_t systime_cycles;
4967 switch (hw->mac.type) {
4971 * Need to read System Time Residue Register to be able
4972 * to read the other two registers.
4974 E1000_READ_REG(hw, E1000_SYSTIMR);
4975 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4976 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4977 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4984 * Need to read System Time Residue Register to be able
4985 * to read the other two registers.
4987 E1000_READ_REG(hw, E1000_SYSTIMR);
4988 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4989 /* Only the 8 LSB are valid. */
4990 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4994 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4995 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
5000 return systime_cycles;
5004 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5006 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5007 uint64_t rx_tstamp_cycles;
5009 switch (hw->mac.type) {
5012 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5013 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5014 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5020 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5021 /* Only the 8 LSB are valid. */
5022 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5026 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5027 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5032 return rx_tstamp_cycles;
5036 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5038 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5039 uint64_t tx_tstamp_cycles;
5041 switch (hw->mac.type) {
5044 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5045 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5046 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5052 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5053 /* Only the 8 LSB are valid. */
5054 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5058 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5059 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5064 return tx_tstamp_cycles;
5068 igb_start_timecounters(struct rte_eth_dev *dev)
5070 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071 struct e1000_adapter *adapter = dev->data->dev_private;
5072 uint32_t incval = 1;
5074 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5076 switch (hw->mac.type) {
5080 /* 32 LSB bits + 8 MSB bits = 40 bits */
5081 mask = (1ULL << 40) - 1;
5086 * Start incrementing the register
5087 * used to timestamp PTP packets.
5089 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5092 incval = E1000_INCVALUE_82576;
5093 shift = IGB_82576_TSYNC_SHIFT;
5094 E1000_WRITE_REG(hw, E1000_TIMINCA,
5095 E1000_INCPERIOD_82576 | incval);
5102 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5103 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5104 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5106 adapter->systime_tc.cc_mask = mask;
5107 adapter->systime_tc.cc_shift = shift;
5108 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5110 adapter->rx_tstamp_tc.cc_mask = mask;
5111 adapter->rx_tstamp_tc.cc_shift = shift;
5112 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5114 adapter->tx_tstamp_tc.cc_mask = mask;
5115 adapter->tx_tstamp_tc.cc_shift = shift;
5116 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5120 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5122 struct e1000_adapter *adapter = dev->data->dev_private;
5124 adapter->systime_tc.nsec += delta;
5125 adapter->rx_tstamp_tc.nsec += delta;
5126 adapter->tx_tstamp_tc.nsec += delta;
5132 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5135 struct e1000_adapter *adapter = dev->data->dev_private;
5137 ns = rte_timespec_to_ns(ts);
5139 /* Set the timecounters to a new value. */
5140 adapter->systime_tc.nsec = ns;
5141 adapter->rx_tstamp_tc.nsec = ns;
5142 adapter->tx_tstamp_tc.nsec = ns;
5148 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5150 uint64_t ns, systime_cycles;
5151 struct e1000_adapter *adapter = dev->data->dev_private;
5153 systime_cycles = igb_read_systime_cyclecounter(dev);
5154 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5155 *ts = rte_ns_to_timespec(ns);
5161 igb_timesync_enable(struct rte_eth_dev *dev)
5163 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167 /* Stop the timesync system time. */
5168 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5169 /* Reset the timesync system time value. */
5170 switch (hw->mac.type) {
5176 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5179 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5180 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5183 /* Not supported. */
5187 /* Enable system time for it isn't on by default. */
5188 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5189 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5190 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5192 igb_start_timecounters(dev);
5194 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5195 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5196 (RTE_ETHER_TYPE_1588 |
5197 E1000_ETQF_FILTER_ENABLE |
5200 /* Enable timestamping of received PTP packets. */
5201 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5202 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5203 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5205 /* Enable Timestamping of transmitted PTP packets. */
5206 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5207 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5208 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5214 igb_timesync_disable(struct rte_eth_dev *dev)
5216 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5219 /* Disable timestamping of transmitted PTP packets. */
5220 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5221 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5222 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5224 /* Disable timestamping of received PTP packets. */
5225 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5226 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5227 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5229 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5230 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5232 /* Stop incrementating the System Time registers. */
5233 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5239 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5240 struct timespec *timestamp,
5241 uint32_t flags __rte_unused)
5243 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5244 struct e1000_adapter *adapter = dev->data->dev_private;
5245 uint32_t tsync_rxctl;
5246 uint64_t rx_tstamp_cycles;
5249 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5250 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5253 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5254 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5255 *timestamp = rte_ns_to_timespec(ns);
5261 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5262 struct timespec *timestamp)
5264 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5265 struct e1000_adapter *adapter = dev->data->dev_private;
5266 uint32_t tsync_txctl;
5267 uint64_t tx_tstamp_cycles;
5270 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5271 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5274 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5275 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5276 *timestamp = rte_ns_to_timespec(ns);
5282 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5286 const struct reg_info *reg_group;
5288 while ((reg_group = igb_regs[g_ind++]))
5289 count += igb_reg_group_count(reg_group);
5295 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5299 const struct reg_info *reg_group;
5301 while ((reg_group = igbvf_regs[g_ind++]))
5302 count += igb_reg_group_count(reg_group);
5308 eth_igb_get_regs(struct rte_eth_dev *dev,
5309 struct rte_dev_reg_info *regs)
5311 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312 uint32_t *data = regs->data;
5315 const struct reg_info *reg_group;
5318 regs->length = eth_igb_get_reg_length(dev);
5319 regs->width = sizeof(uint32_t);
5323 /* Support only full register dump */
5324 if ((regs->length == 0) ||
5325 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5326 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5328 while ((reg_group = igb_regs[g_ind++]))
5329 count += igb_read_regs_group(dev, &data[count],
5338 igbvf_get_regs(struct rte_eth_dev *dev,
5339 struct rte_dev_reg_info *regs)
5341 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5342 uint32_t *data = regs->data;
5345 const struct reg_info *reg_group;
5348 regs->length = igbvf_get_reg_length(dev);
5349 regs->width = sizeof(uint32_t);
5353 /* Support only full register dump */
5354 if ((regs->length == 0) ||
5355 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5356 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5358 while ((reg_group = igbvf_regs[g_ind++]))
5359 count += igb_read_regs_group(dev, &data[count],
5368 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5370 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5372 /* Return unit is byte count */
5373 return hw->nvm.word_size * 2;
5377 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5378 struct rte_dev_eeprom_info *in_eeprom)
5380 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5381 struct e1000_nvm_info *nvm = &hw->nvm;
5382 uint16_t *data = in_eeprom->data;
5385 first = in_eeprom->offset >> 1;
5386 length = in_eeprom->length >> 1;
5387 if ((first >= hw->nvm.word_size) ||
5388 ((first + length) >= hw->nvm.word_size))
5391 in_eeprom->magic = hw->vendor_id |
5392 ((uint32_t)hw->device_id << 16);
5394 if ((nvm->ops.read) == NULL)
5397 return nvm->ops.read(hw, first, length, data);
5401 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5402 struct rte_dev_eeprom_info *in_eeprom)
5404 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5405 struct e1000_nvm_info *nvm = &hw->nvm;
5406 uint16_t *data = in_eeprom->data;
5409 first = in_eeprom->offset >> 1;
5410 length = in_eeprom->length >> 1;
5411 if ((first >= hw->nvm.word_size) ||
5412 ((first + length) >= hw->nvm.word_size))
5415 in_eeprom->magic = (uint32_t)hw->vendor_id |
5416 ((uint32_t)hw->device_id << 16);
5418 if ((nvm->ops.write) == NULL)
5420 return nvm->ops.write(hw, first, length, data);
5424 eth_igb_get_module_info(struct rte_eth_dev *dev,
5425 struct rte_eth_dev_module_info *modinfo)
5427 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5429 uint32_t status = 0;
5430 uint16_t sff8472_rev, addr_mode;
5431 bool page_swap = false;
5433 if (hw->phy.media_type == e1000_media_type_copper ||
5434 hw->phy.media_type == e1000_media_type_unknown)
5437 /* Check whether we support SFF-8472 or not */
5438 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5442 /* addressing mode is not supported */
5443 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5447 /* addressing mode is not supported */
5448 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5450 "Address change required to access page 0xA2, "
5451 "but not supported. Please report the module "
5452 "type to the driver maintainers.\n");
5456 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5457 /* We have an SFP, but it does not support SFF-8472 */
5458 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5459 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5461 /* We have an SFP which supports a revision of SFF-8472 */
5462 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5463 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5470 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5471 struct rte_dev_eeprom_info *info)
5473 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5475 uint32_t status = 0;
5476 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5477 u16 first_word, last_word;
5480 if (info->length == 0)
5483 first_word = info->offset >> 1;
5484 last_word = (info->offset + info->length - 1) >> 1;
5486 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5487 for (i = 0; i < last_word - first_word + 1; i++) {
5488 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5491 /* Error occurred while reading module */
5495 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5498 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5504 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5506 struct e1000_hw *hw =
5507 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5509 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5510 uint32_t vec = E1000_MISC_VEC_ID;
5512 if (rte_intr_allow_others(intr_handle))
5513 vec = E1000_RX_VEC_START;
5515 uint32_t mask = 1 << (queue_id + vec);
5517 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5518 E1000_WRITE_FLUSH(hw);
5524 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5526 struct e1000_hw *hw =
5527 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5529 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5530 uint32_t vec = E1000_MISC_VEC_ID;
5532 if (rte_intr_allow_others(intr_handle))
5533 vec = E1000_RX_VEC_START;
5535 uint32_t mask = 1 << (queue_id + vec);
5538 regval = E1000_READ_REG(hw, E1000_EIMS);
5539 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5540 E1000_WRITE_FLUSH(hw);
5542 rte_intr_ack(intr_handle);
5548 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5549 uint8_t index, uint8_t offset)
5551 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5554 val &= ~((uint32_t)0xFF << offset);
5556 /* write vector and valid bit */
5557 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5559 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5563 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5564 uint8_t queue, uint8_t msix_vector)
5568 if (hw->mac.type == e1000_82575) {
5570 tmp = E1000_EICR_RX_QUEUE0 << queue;
5571 else if (direction == 1)
5572 tmp = E1000_EICR_TX_QUEUE0 << queue;
5573 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5574 } else if (hw->mac.type == e1000_82576) {
5575 if ((direction == 0) || (direction == 1))
5576 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5577 ((queue & 0x8) << 1) +
5579 } else if ((hw->mac.type == e1000_82580) ||
5580 (hw->mac.type == e1000_i350) ||
5581 (hw->mac.type == e1000_i354) ||
5582 (hw->mac.type == e1000_i210) ||
5583 (hw->mac.type == e1000_i211)) {
5584 if ((direction == 0) || (direction == 1))
5585 eth_igb_write_ivar(hw, msix_vector,
5587 ((queue & 0x1) << 4) +
5592 /* Sets up the hardware to generate MSI-X interrupts properly
5594 * board private structure
5597 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5600 uint32_t tmpval, regval, intr_mask;
5601 struct e1000_hw *hw =
5602 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5603 uint32_t vec = E1000_MISC_VEC_ID;
5604 uint32_t base = E1000_MISC_VEC_ID;
5605 uint32_t misc_shift = 0;
5606 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5607 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5609 /* won't configure msix register if no mapping is done
5610 * between intr vector and event fd
5612 if (!rte_intr_dp_is_en(intr_handle))
5615 if (rte_intr_allow_others(intr_handle)) {
5616 vec = base = E1000_RX_VEC_START;
5620 /* set interrupt vector for other causes */
5621 if (hw->mac.type == e1000_82575) {
5622 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5623 /* enable MSI-X PBA support */
5624 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5626 /* Auto-Mask interrupts upon ICR read */
5627 tmpval |= E1000_CTRL_EXT_EIAME;
5628 tmpval |= E1000_CTRL_EXT_IRCA;
5630 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5632 /* enable msix_other interrupt */
5633 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5634 regval = E1000_READ_REG(hw, E1000_EIAC);
5635 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5636 regval = E1000_READ_REG(hw, E1000_EIAM);
5637 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5638 } else if ((hw->mac.type == e1000_82576) ||
5639 (hw->mac.type == e1000_82580) ||
5640 (hw->mac.type == e1000_i350) ||
5641 (hw->mac.type == e1000_i354) ||
5642 (hw->mac.type == e1000_i210) ||
5643 (hw->mac.type == e1000_i211)) {
5644 /* turn on MSI-X capability first */
5645 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5646 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5648 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5651 if (dev->data->dev_conf.intr_conf.lsc != 0)
5652 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5654 regval = E1000_READ_REG(hw, E1000_EIAC);
5655 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5657 /* enable msix_other interrupt */
5658 regval = E1000_READ_REG(hw, E1000_EIMS);
5659 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5660 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5661 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5664 /* use EIAM to auto-mask when MSI-X interrupt
5665 * is asserted, this saves a register write for every interrupt
5667 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5670 if (dev->data->dev_conf.intr_conf.lsc != 0)
5671 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5673 regval = E1000_READ_REG(hw, E1000_EIAM);
5674 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5676 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5677 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5678 intr_handle->intr_vec[queue_id] = vec;
5679 if (vec < base + intr_handle->nb_efd - 1)
5683 E1000_WRITE_FLUSH(hw);
5686 /* restore n-tuple filter */
5688 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5690 struct e1000_filter_info *filter_info =
5691 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5692 struct e1000_5tuple_filter *p_5tuple;
5693 struct e1000_2tuple_filter *p_2tuple;
5695 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5696 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5699 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5700 igb_inject_2uple_filter(dev, p_2tuple);
5704 /* restore SYN filter */
5706 igb_syn_filter_restore(struct rte_eth_dev *dev)
5708 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5709 struct e1000_filter_info *filter_info =
5710 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5713 synqf = filter_info->syn_info;
5715 if (synqf & E1000_SYN_FILTER_ENABLE) {
5716 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5717 E1000_WRITE_FLUSH(hw);
5721 /* restore ethernet type filter */
5723 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5725 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5726 struct e1000_filter_info *filter_info =
5727 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5730 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5731 if (filter_info->ethertype_mask & (1 << i)) {
5732 E1000_WRITE_REG(hw, E1000_ETQF(i),
5733 filter_info->ethertype_filters[i].etqf);
5734 E1000_WRITE_FLUSH(hw);
5739 /* restore flex byte filter */
5741 igb_flex_filter_restore(struct rte_eth_dev *dev)
5743 struct e1000_filter_info *filter_info =
5744 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5745 struct e1000_flex_filter *flex_filter;
5747 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5748 igb_inject_flex_filter(dev, flex_filter);
5752 /* restore rss filter */
5754 igb_rss_filter_restore(struct rte_eth_dev *dev)
5756 struct e1000_filter_info *filter_info =
5757 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5759 if (filter_info->rss_info.conf.queue_num)
5760 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5763 /* restore all types filter */
5765 igb_filter_restore(struct rte_eth_dev *dev)
5767 igb_ntuple_filter_restore(dev);
5768 igb_ethertype_filter_restore(dev);
5769 igb_syn_filter_restore(dev);
5770 igb_flex_filter_restore(dev);
5771 igb_rss_filter_restore(dev);
5776 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5777 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5778 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5779 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5780 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5781 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5783 /* see e1000_logs.c */
5784 RTE_INIT(e1000_init_log)
5786 e1000_igb_init_log();