1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static void eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static void eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static void eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
158 static void igbvf_dev_close(struct rte_eth_dev *dev);
159 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
190 struct rte_eth_syn_filter *filter);
191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
192 enum rte_filter_op filter_op,
194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
197 struct rte_eth_ntuple_filter *ntuple_filter);
198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
199 struct rte_eth_flex_filter *filter);
200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
201 enum rte_filter_op filter_op,
203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
204 struct rte_eth_ntuple_filter *ntuple_filter);
205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
206 struct rte_eth_ntuple_filter *ntuple_filter);
207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
208 struct rte_eth_ntuple_filter *filter);
209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
210 enum rte_filter_op filter_op,
212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ethertype_filter *filter);
217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
218 enum rte_filter_type filter_type,
219 enum rte_filter_op filter_op,
221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
223 struct rte_dev_reg_info *regs);
224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
226 struct rte_dev_eeprom_info *eeprom);
227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
228 struct rte_dev_eeprom_info *eeprom);
229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
230 struct rte_eth_dev_module_info *modinfo);
231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
232 struct rte_dev_eeprom_info *info);
233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
234 struct rte_ether_addr *mc_addr_set,
235 uint32_t nb_mc_addr);
236 static int igb_timesync_enable(struct rte_eth_dev *dev);
237 static int igb_timesync_disable(struct rte_eth_dev *dev);
238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
239 struct timespec *timestamp,
241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
242 struct timespec *timestamp);
243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
245 struct timespec *timestamp);
246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
247 const struct timespec *timestamp);
248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
253 uint8_t queue, uint8_t msix_vector);
254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
255 uint8_t index, uint8_t offset);
256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
257 static void eth_igbvf_interrupt_handler(void *param);
258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
259 static int igb_filter_restore(struct rte_eth_dev *dev);
262 * Define VF Stats MACRO for Non "cleared on read" register
264 #define UPDATE_VF_STAT(reg, last, cur) \
266 u32 latest = E1000_READ_REG(hw, reg); \
267 cur += (latest - last) & UINT_MAX; \
271 #define IGB_FC_PAUSE_TIME 0x0680
272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
275 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
280 * The set of PCI devices this driver supports
282 static const struct rte_pci_id pci_id_igb_map[] = {
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
324 { .vendor_id = 0, /* sentinel */ },
328 * The set of PCI devices this driver supports (for 82576&I350 VF)
330 static const struct rte_pci_id pci_id_igbvf_map[] = {
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
335 { .vendor_id = 0, /* sentinel */ },
338 static const struct rte_eth_desc_lim rx_desc_lim = {
339 .nb_max = E1000_MAX_RING_DESC,
340 .nb_min = E1000_MIN_RING_DESC,
341 .nb_align = IGB_RXD_ALIGN,
344 static const struct rte_eth_desc_lim tx_desc_lim = {
345 .nb_max = E1000_MAX_RING_DESC,
346 .nb_min = E1000_MIN_RING_DESC,
347 .nb_align = IGB_RXD_ALIGN,
348 .nb_seg_max = IGB_TX_MAX_SEG,
349 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
352 static const struct eth_dev_ops eth_igb_ops = {
353 .dev_configure = eth_igb_configure,
354 .dev_start = eth_igb_start,
355 .dev_stop = eth_igb_stop,
356 .dev_set_link_up = eth_igb_dev_set_link_up,
357 .dev_set_link_down = eth_igb_dev_set_link_down,
358 .dev_close = eth_igb_close,
359 .dev_reset = eth_igb_reset,
360 .promiscuous_enable = eth_igb_promiscuous_enable,
361 .promiscuous_disable = eth_igb_promiscuous_disable,
362 .allmulticast_enable = eth_igb_allmulticast_enable,
363 .allmulticast_disable = eth_igb_allmulticast_disable,
364 .link_update = eth_igb_link_update,
365 .stats_get = eth_igb_stats_get,
366 .xstats_get = eth_igb_xstats_get,
367 .xstats_get_by_id = eth_igb_xstats_get_by_id,
368 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
369 .xstats_get_names = eth_igb_xstats_get_names,
370 .stats_reset = eth_igb_stats_reset,
371 .xstats_reset = eth_igb_xstats_reset,
372 .fw_version_get = eth_igb_fw_version_get,
373 .dev_infos_get = eth_igb_infos_get,
374 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
375 .mtu_set = eth_igb_mtu_set,
376 .vlan_filter_set = eth_igb_vlan_filter_set,
377 .vlan_tpid_set = eth_igb_vlan_tpid_set,
378 .vlan_offload_set = eth_igb_vlan_offload_set,
379 .rx_queue_setup = eth_igb_rx_queue_setup,
380 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
381 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
382 .rx_queue_release = eth_igb_rx_queue_release,
383 .rx_queue_count = eth_igb_rx_queue_count,
384 .rx_descriptor_done = eth_igb_rx_descriptor_done,
385 .rx_descriptor_status = eth_igb_rx_descriptor_status,
386 .tx_descriptor_status = eth_igb_tx_descriptor_status,
387 .tx_queue_setup = eth_igb_tx_queue_setup,
388 .tx_queue_release = eth_igb_tx_queue_release,
389 .tx_done_cleanup = eth_igb_tx_done_cleanup,
390 .dev_led_on = eth_igb_led_on,
391 .dev_led_off = eth_igb_led_off,
392 .flow_ctrl_get = eth_igb_flow_ctrl_get,
393 .flow_ctrl_set = eth_igb_flow_ctrl_set,
394 .mac_addr_add = eth_igb_rar_set,
395 .mac_addr_remove = eth_igb_rar_clear,
396 .mac_addr_set = eth_igb_default_mac_addr_set,
397 .reta_update = eth_igb_rss_reta_update,
398 .reta_query = eth_igb_rss_reta_query,
399 .rss_hash_update = eth_igb_rss_hash_update,
400 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
401 .filter_ctrl = eth_igb_filter_ctrl,
402 .set_mc_addr_list = eth_igb_set_mc_addr_list,
403 .rxq_info_get = igb_rxq_info_get,
404 .txq_info_get = igb_txq_info_get,
405 .timesync_enable = igb_timesync_enable,
406 .timesync_disable = igb_timesync_disable,
407 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
408 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
409 .get_reg = eth_igb_get_regs,
410 .get_eeprom_length = eth_igb_get_eeprom_length,
411 .get_eeprom = eth_igb_get_eeprom,
412 .set_eeprom = eth_igb_set_eeprom,
413 .get_module_info = eth_igb_get_module_info,
414 .get_module_eeprom = eth_igb_get_module_eeprom,
415 .timesync_adjust_time = igb_timesync_adjust_time,
416 .timesync_read_time = igb_timesync_read_time,
417 .timesync_write_time = igb_timesync_write_time,
421 * dev_ops for virtual function, bare necessities for basic vf
422 * operation have been implemented
424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
425 .dev_configure = igbvf_dev_configure,
426 .dev_start = igbvf_dev_start,
427 .dev_stop = igbvf_dev_stop,
428 .dev_close = igbvf_dev_close,
429 .promiscuous_enable = igbvf_promiscuous_enable,
430 .promiscuous_disable = igbvf_promiscuous_disable,
431 .allmulticast_enable = igbvf_allmulticast_enable,
432 .allmulticast_disable = igbvf_allmulticast_disable,
433 .link_update = eth_igb_link_update,
434 .stats_get = eth_igbvf_stats_get,
435 .xstats_get = eth_igbvf_xstats_get,
436 .xstats_get_names = eth_igbvf_xstats_get_names,
437 .stats_reset = eth_igbvf_stats_reset,
438 .xstats_reset = eth_igbvf_stats_reset,
439 .vlan_filter_set = igbvf_vlan_filter_set,
440 .dev_infos_get = eth_igbvf_infos_get,
441 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
442 .rx_queue_setup = eth_igb_rx_queue_setup,
443 .rx_queue_release = eth_igb_rx_queue_release,
444 .rx_descriptor_done = eth_igb_rx_descriptor_done,
445 .rx_descriptor_status = eth_igb_rx_descriptor_status,
446 .tx_descriptor_status = eth_igb_tx_descriptor_status,
447 .tx_queue_setup = eth_igb_tx_queue_setup,
448 .tx_queue_release = eth_igb_tx_queue_release,
449 .set_mc_addr_list = eth_igb_set_mc_addr_list,
450 .rxq_info_get = igb_rxq_info_get,
451 .txq_info_get = igb_txq_info_get,
452 .mac_addr_set = igbvf_default_mac_addr_set,
453 .get_reg = igbvf_get_regs,
456 /* store statistics names and its offset in stats structure */
457 struct rte_igb_xstats_name_off {
458 char name[RTE_ETH_XSTATS_NAME_SIZE];
462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
463 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
464 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
465 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
466 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
467 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
468 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
469 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
471 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
472 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
473 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
474 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
475 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
476 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
477 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
478 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
479 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
480 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
481 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
483 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
484 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
485 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
486 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
487 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
489 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
491 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
492 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
493 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
494 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
495 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
496 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
497 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
498 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
499 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
500 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
501 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
502 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
503 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
504 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
505 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
506 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
507 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
508 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
510 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
512 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
513 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
514 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
515 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
516 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
517 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
518 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
520 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
524 sizeof(rte_igb_stats_strings[0]))
526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
527 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
528 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
529 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
530 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
531 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
535 sizeof(rte_igbvf_stats_strings[0]))
539 igb_intr_enable(struct rte_eth_dev *dev)
541 struct e1000_interrupt *intr =
542 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
543 struct e1000_hw *hw =
544 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
545 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
546 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
548 if (rte_intr_allow_others(intr_handle) &&
549 dev->data->dev_conf.intr_conf.lsc != 0) {
550 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
553 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
554 E1000_WRITE_FLUSH(hw);
558 igb_intr_disable(struct rte_eth_dev *dev)
560 struct e1000_hw *hw =
561 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
565 if (rte_intr_allow_others(intr_handle) &&
566 dev->data->dev_conf.intr_conf.lsc != 0) {
567 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
570 E1000_WRITE_REG(hw, E1000_IMC, ~0);
571 E1000_WRITE_FLUSH(hw);
575 igbvf_intr_enable(struct rte_eth_dev *dev)
577 struct e1000_hw *hw =
578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
580 /* only for mailbox */
581 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
582 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
583 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
584 E1000_WRITE_FLUSH(hw);
587 /* only for mailbox now. If RX/TX needed, should extend this function. */
589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
594 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
595 tmp |= E1000_VTIVAR_VALID;
596 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
602 struct e1000_hw *hw =
603 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 /* Configure VF other cause ivar */
606 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
609 static inline int32_t
610 igb_pf_reset_hw(struct e1000_hw *hw)
615 status = e1000_reset_hw(hw);
617 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
618 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
619 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
620 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
621 E1000_WRITE_FLUSH(hw);
627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
629 struct e1000_hw *hw =
630 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 hw->vendor_id = pci_dev->id.vendor_id;
634 hw->device_id = pci_dev->id.device_id;
635 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
636 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
638 e1000_set_mac_type(hw);
640 /* need to check if it is a vf device below */
644 igb_reset_swfw_lock(struct e1000_hw *hw)
649 * Do mac ops initialization manually here, since we will need
650 * some function pointers set by this call.
652 ret_val = e1000_init_mac_params(hw);
657 * SMBI lock should not fail in this early stage. If this is the case,
658 * it is due to an improper exit of the application.
659 * So force the release of the faulty lock.
661 if (e1000_get_hw_semaphore_generic(hw) < 0) {
662 PMD_DRV_LOG(DEBUG, "SMBI lock released");
664 e1000_put_hw_semaphore_generic(hw);
666 if (hw->mac.ops.acquire_swfw_sync != NULL) {
670 * Phy lock should not fail in this early stage. If this is the case,
671 * it is due to an improper exit of the application.
672 * So force the release of the faulty lock.
674 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
675 if (hw->bus.func > E1000_FUNC_1)
677 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
678 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
681 hw->mac.ops.release_swfw_sync(hw, mask);
684 * This one is more tricky since it is common to all ports; but
685 * swfw_sync retries last long enough (1s) to be almost sure that if
686 * lock can not be taken it is due to an improper lock of the
689 mask = E1000_SWFW_EEP_SM;
690 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
691 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
693 hw->mac.ops.release_swfw_sync(hw, mask);
696 return E1000_SUCCESS;
699 /* Remove all ntuple filters of the device */
700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
702 struct e1000_filter_info *filter_info =
703 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
704 struct e1000_5tuple_filter *p_5tuple;
705 struct e1000_2tuple_filter *p_2tuple;
707 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
708 TAILQ_REMOVE(&filter_info->fivetuple_list,
712 filter_info->fivetuple_mask = 0;
713 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
714 TAILQ_REMOVE(&filter_info->twotuple_list,
718 filter_info->twotuple_mask = 0;
723 /* Remove all flex filters of the device */
724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
726 struct e1000_filter_info *filter_info =
727 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
728 struct e1000_flex_filter *p_flex;
730 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
731 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
734 filter_info->flex_mask = 0;
740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
743 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
744 struct e1000_hw *hw =
745 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
746 struct e1000_vfta * shadow_vfta =
747 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
748 struct e1000_filter_info *filter_info =
749 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
750 struct e1000_adapter *adapter =
751 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
755 eth_dev->dev_ops = ð_igb_ops;
756 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
757 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
758 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
760 /* for secondary processes, we don't initialise any further as primary
761 * has already done this work. Only check we don't need a different
763 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
764 if (eth_dev->data->scattered_rx)
765 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
769 rte_eth_copy_pci_info(eth_dev, pci_dev);
771 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
773 igb_identify_hardware(eth_dev, pci_dev);
774 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
779 e1000_get_bus_info(hw);
781 /* Reset any pending lock */
782 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
787 /* Finish initialization */
788 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
794 hw->phy.autoneg_wait_to_complete = 0;
795 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
798 if (hw->phy.media_type == e1000_media_type_copper) {
799 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
800 hw->phy.disable_polarity_correction = 0;
801 hw->phy.ms_type = e1000_ms_hw_default;
805 * Start from a known state, this is important in reading the nvm
810 /* Make sure we have a good EEPROM before we read from it */
811 if (e1000_validate_nvm_checksum(hw) < 0) {
813 * Some PCI-E parts fail the first check due to
814 * the link being in sleep state, call it again,
815 * if it fails a second time its a real issue.
817 if (e1000_validate_nvm_checksum(hw) < 0) {
818 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
824 /* Read the permanent MAC address out of the EEPROM */
825 if (e1000_read_mac_addr(hw) != 0) {
826 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
831 /* Allocate memory for storing MAC addresses */
832 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
833 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
834 if (eth_dev->data->mac_addrs == NULL) {
835 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
836 "store MAC addresses",
837 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
842 /* Copy the permanent MAC address */
843 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
844 ð_dev->data->mac_addrs[0]);
846 /* initialize the vfta */
847 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
849 /* Now initialize the hardware */
850 if (igb_hardware_init(hw) != 0) {
851 PMD_INIT_LOG(ERR, "Hardware initialization failed");
852 rte_free(eth_dev->data->mac_addrs);
853 eth_dev->data->mac_addrs = NULL;
857 hw->mac.get_link_status = 1;
858 adapter->stopped = 0;
860 /* Indicate SOL/IDER usage */
861 if (e1000_check_reset_block(hw) < 0) {
862 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
866 /* initialize PF if max_vfs not zero */
867 igb_pf_host_init(eth_dev);
869 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
870 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
871 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
872 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
873 E1000_WRITE_FLUSH(hw);
875 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
876 eth_dev->data->port_id, pci_dev->id.vendor_id,
877 pci_dev->id.device_id);
879 rte_intr_callback_register(&pci_dev->intr_handle,
880 eth_igb_interrupt_handler,
883 /* enable uio/vfio intr/eventfd mapping */
884 rte_intr_enable(&pci_dev->intr_handle);
886 /* enable support intr */
887 igb_intr_enable(eth_dev);
889 /* initialize filter info */
890 memset(filter_info, 0,
891 sizeof(struct e1000_filter_info));
893 TAILQ_INIT(&filter_info->flex_list);
894 TAILQ_INIT(&filter_info->twotuple_list);
895 TAILQ_INIT(&filter_info->fivetuple_list);
897 TAILQ_INIT(&igb_filter_ntuple_list);
898 TAILQ_INIT(&igb_filter_ethertype_list);
899 TAILQ_INIT(&igb_filter_syn_list);
900 TAILQ_INIT(&igb_filter_flex_list);
901 TAILQ_INIT(&igb_filter_rss_list);
902 TAILQ_INIT(&igb_flow_list);
907 igb_hw_control_release(hw);
913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
915 struct rte_pci_device *pci_dev;
916 struct rte_intr_handle *intr_handle;
918 struct e1000_adapter *adapter =
919 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
920 struct e1000_filter_info *filter_info =
921 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
923 PMD_INIT_FUNC_TRACE();
925 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
928 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
929 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
930 intr_handle = &pci_dev->intr_handle;
932 if (adapter->stopped == 0)
933 eth_igb_close(eth_dev);
935 eth_dev->dev_ops = NULL;
936 eth_dev->rx_pkt_burst = NULL;
937 eth_dev->tx_pkt_burst = NULL;
939 /* Reset any pending lock */
940 igb_reset_swfw_lock(hw);
942 /* uninitialize PF if max_vfs not zero */
943 igb_pf_host_uninit(eth_dev);
945 /* disable uio intr before callback unregister */
946 rte_intr_disable(intr_handle);
947 rte_intr_callback_unregister(intr_handle,
948 eth_igb_interrupt_handler, eth_dev);
950 /* clear the SYN filter info */
951 filter_info->syn_info = 0;
953 /* clear the ethertype filters info */
954 filter_info->ethertype_mask = 0;
955 memset(filter_info->ethertype_filters, 0,
956 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
958 /* clear the rss filter info */
959 memset(&filter_info->rss_info, 0,
960 sizeof(struct igb_rte_flow_rss_conf));
962 /* remove all ntuple filters of the device */
963 igb_ntuple_filter_uninit(eth_dev);
965 /* remove all flex filters of the device */
966 igb_flex_filter_uninit(eth_dev);
968 /* clear all the filters list */
969 igb_filterlist_flush(eth_dev);
975 * Virtual Function device init
978 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
980 struct rte_pci_device *pci_dev;
981 struct rte_intr_handle *intr_handle;
982 struct e1000_adapter *adapter =
983 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
984 struct e1000_hw *hw =
985 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
987 struct rte_ether_addr *perm_addr =
988 (struct rte_ether_addr *)hw->mac.perm_addr;
990 PMD_INIT_FUNC_TRACE();
992 eth_dev->dev_ops = &igbvf_eth_dev_ops;
993 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
994 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
995 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
997 /* for secondary processes, we don't initialise any further as primary
998 * has already done this work. Only check we don't need a different
1000 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1001 if (eth_dev->data->scattered_rx)
1002 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
1006 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1007 rte_eth_copy_pci_info(eth_dev, pci_dev);
1009 hw->device_id = pci_dev->id.device_id;
1010 hw->vendor_id = pci_dev->id.vendor_id;
1011 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1012 adapter->stopped = 0;
1014 /* Initialize the shared code (base driver) */
1015 diag = e1000_setup_init_funcs(hw, TRUE);
1017 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1022 /* init_mailbox_params */
1023 hw->mbx.ops.init_params(hw);
1025 /* Disable the interrupts for VF */
1026 igbvf_intr_disable(hw);
1028 diag = hw->mac.ops.reset_hw(hw);
1030 /* Allocate memory for storing MAC addresses */
1031 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
1032 hw->mac.rar_entry_count, 0);
1033 if (eth_dev->data->mac_addrs == NULL) {
1035 "Failed to allocate %d bytes needed to store MAC "
1037 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1041 /* Generate a random MAC address, if none was assigned by PF. */
1042 if (rte_is_zero_ether_addr(perm_addr)) {
1043 rte_eth_random_addr(perm_addr->addr_bytes);
1044 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1045 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1046 "%02x:%02x:%02x:%02x:%02x:%02x",
1047 perm_addr->addr_bytes[0],
1048 perm_addr->addr_bytes[1],
1049 perm_addr->addr_bytes[2],
1050 perm_addr->addr_bytes[3],
1051 perm_addr->addr_bytes[4],
1052 perm_addr->addr_bytes[5]);
1055 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1057 rte_free(eth_dev->data->mac_addrs);
1058 eth_dev->data->mac_addrs = NULL;
1061 /* Copy the permanent MAC address */
1062 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1063 ð_dev->data->mac_addrs[0]);
1065 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1067 eth_dev->data->port_id, pci_dev->id.vendor_id,
1068 pci_dev->id.device_id, "igb_mac_82576_vf");
1070 intr_handle = &pci_dev->intr_handle;
1071 rte_intr_callback_register(intr_handle,
1072 eth_igbvf_interrupt_handler, eth_dev);
1078 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1080 struct e1000_adapter *adapter =
1081 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1082 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1084 PMD_INIT_FUNC_TRACE();
1086 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1089 if (adapter->stopped == 0)
1090 igbvf_dev_close(eth_dev);
1092 eth_dev->dev_ops = NULL;
1093 eth_dev->rx_pkt_burst = NULL;
1094 eth_dev->tx_pkt_burst = NULL;
1096 /* disable uio intr before callback unregister */
1097 rte_intr_disable(&pci_dev->intr_handle);
1098 rte_intr_callback_unregister(&pci_dev->intr_handle,
1099 eth_igbvf_interrupt_handler,
1105 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1106 struct rte_pci_device *pci_dev)
1108 return rte_eth_dev_pci_generic_probe(pci_dev,
1109 sizeof(struct e1000_adapter), eth_igb_dev_init);
1112 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1114 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1117 static struct rte_pci_driver rte_igb_pmd = {
1118 .id_table = pci_id_igb_map,
1119 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1120 RTE_PCI_DRV_IOVA_AS_VA,
1121 .probe = eth_igb_pci_probe,
1122 .remove = eth_igb_pci_remove,
1126 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1127 struct rte_pci_device *pci_dev)
1129 return rte_eth_dev_pci_generic_probe(pci_dev,
1130 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1133 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1135 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1139 * virtual function driver struct
1141 static struct rte_pci_driver rte_igbvf_pmd = {
1142 .id_table = pci_id_igbvf_map,
1143 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1144 .probe = eth_igbvf_pci_probe,
1145 .remove = eth_igbvf_pci_remove,
1149 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1151 struct e1000_hw *hw =
1152 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1153 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1154 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1155 rctl |= E1000_RCTL_VFE;
1156 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1160 igb_check_mq_mode(struct rte_eth_dev *dev)
1162 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1163 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1164 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1165 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1167 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1168 tx_mq_mode == ETH_MQ_TX_DCB ||
1169 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1170 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1173 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1174 /* Check multi-queue mode.
1175 * To no break software we accept ETH_MQ_RX_NONE as this might
1176 * be used to turn off VLAN filter.
1179 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1180 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1181 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1182 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1184 /* Only support one queue on VFs.
1185 * RSS together with SRIOV is not supported.
1187 PMD_INIT_LOG(ERR, "SRIOV is active,"
1188 " wrong mq_mode rx %d.",
1192 /* TX mode is not used here, so mode might be ignored.*/
1193 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1194 /* SRIOV only works in VMDq enable mode */
1195 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1196 " TX mode %d is not supported. "
1197 " Driver will behave as %d mode.",
1198 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1201 /* check valid queue number */
1202 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1203 PMD_INIT_LOG(ERR, "SRIOV is active,"
1204 " only support one queue on VFs.");
1208 /* To no break software that set invalid mode, only display
1209 * warning if invalid mode is used.
1211 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1212 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1213 rx_mq_mode != ETH_MQ_RX_RSS) {
1214 /* RSS together with VMDq not supported*/
1215 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1220 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1221 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1222 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1223 " Due to txmode is meaningless in this"
1224 " driver, just ignore.",
1232 eth_igb_configure(struct rte_eth_dev *dev)
1234 struct e1000_interrupt *intr =
1235 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1238 PMD_INIT_FUNC_TRACE();
1240 /* multipe queue mode checking */
1241 ret = igb_check_mq_mode(dev);
1243 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1248 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1249 PMD_INIT_FUNC_TRACE();
1255 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1258 struct e1000_hw *hw =
1259 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260 uint32_t tctl, rctl;
1262 tctl = E1000_READ_REG(hw, E1000_TCTL);
1263 rctl = E1000_READ_REG(hw, E1000_RCTL);
1267 tctl |= E1000_TCTL_EN;
1268 rctl |= E1000_RCTL_EN;
1271 tctl &= ~E1000_TCTL_EN;
1272 rctl &= ~E1000_RCTL_EN;
1274 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1275 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1276 E1000_WRITE_FLUSH(hw);
1280 eth_igb_start(struct rte_eth_dev *dev)
1282 struct e1000_hw *hw =
1283 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284 struct e1000_adapter *adapter =
1285 E1000_DEV_PRIVATE(dev->data->dev_private);
1286 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1287 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1289 uint32_t intr_vector = 0;
1295 PMD_INIT_FUNC_TRACE();
1297 /* disable uio/vfio intr/eventfd mapping */
1298 rte_intr_disable(intr_handle);
1300 /* Power up the phy. Needed to make the link go Up */
1301 eth_igb_dev_set_link_up(dev);
1304 * Packet Buffer Allocation (PBA)
1305 * Writing PBA sets the receive portion of the buffer
1306 * the remainder is used for the transmit buffer.
1308 if (hw->mac.type == e1000_82575) {
1311 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1312 E1000_WRITE_REG(hw, E1000_PBA, pba);
1315 /* Put the address into the Receive Address Array */
1316 e1000_rar_set(hw, hw->mac.addr, 0);
1318 /* Initialize the hardware */
1319 if (igb_hardware_init(hw)) {
1320 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1323 adapter->stopped = 0;
1325 E1000_WRITE_REG(hw, E1000_VET,
1326 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1328 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1329 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1330 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1331 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1332 E1000_WRITE_FLUSH(hw);
1334 /* configure PF module if SRIOV enabled */
1335 igb_pf_host_configure(dev);
1337 /* check and configure queue intr-vector mapping */
1338 if ((rte_intr_cap_multiple(intr_handle) ||
1339 !RTE_ETH_DEV_SRIOV(dev).active) &&
1340 dev->data->dev_conf.intr_conf.rxq != 0) {
1341 intr_vector = dev->data->nb_rx_queues;
1342 if (rte_intr_efd_enable(intr_handle, intr_vector))
1346 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1347 intr_handle->intr_vec =
1348 rte_zmalloc("intr_vec",
1349 dev->data->nb_rx_queues * sizeof(int), 0);
1350 if (intr_handle->intr_vec == NULL) {
1351 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1352 " intr_vec", dev->data->nb_rx_queues);
1357 /* confiugre msix for rx interrupt */
1358 eth_igb_configure_msix_intr(dev);
1360 /* Configure for OS presence */
1361 igb_init_manageability(hw);
1363 eth_igb_tx_init(dev);
1365 /* This can fail when allocating mbufs for descriptor rings */
1366 ret = eth_igb_rx_init(dev);
1368 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1369 igb_dev_clear_queues(dev);
1373 e1000_clear_hw_cntrs_base_generic(hw);
1376 * VLAN Offload Settings
1378 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1379 ETH_VLAN_EXTEND_MASK;
1380 ret = eth_igb_vlan_offload_set(dev, mask);
1382 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1383 igb_dev_clear_queues(dev);
1387 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1388 /* Enable VLAN filter since VMDq always use VLAN filter */
1389 igb_vmdq_vlan_hw_filter_enable(dev);
1392 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1393 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1394 (hw->mac.type == e1000_i211)) {
1395 /* Configure EITR with the maximum possible value (0xFFFF) */
1396 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1399 /* Setup link speed and duplex */
1400 speeds = &dev->data->dev_conf.link_speeds;
1401 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1402 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1403 hw->mac.autoneg = 1;
1406 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1409 hw->phy.autoneg_advertised = 0;
1411 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1412 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1413 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1415 goto error_invalid_config;
1417 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1418 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1421 if (*speeds & ETH_LINK_SPEED_10M) {
1422 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1425 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1426 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1429 if (*speeds & ETH_LINK_SPEED_100M) {
1430 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1433 if (*speeds & ETH_LINK_SPEED_1G) {
1434 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1437 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1438 goto error_invalid_config;
1440 /* Set/reset the mac.autoneg based on the link speed,
1444 hw->mac.autoneg = 0;
1445 hw->mac.forced_speed_duplex =
1446 hw->phy.autoneg_advertised;
1448 hw->mac.autoneg = 1;
1452 e1000_setup_link(hw);
1454 if (rte_intr_allow_others(intr_handle)) {
1455 /* check if lsc interrupt is enabled */
1456 if (dev->data->dev_conf.intr_conf.lsc != 0)
1457 eth_igb_lsc_interrupt_setup(dev, TRUE);
1459 eth_igb_lsc_interrupt_setup(dev, FALSE);
1461 rte_intr_callback_unregister(intr_handle,
1462 eth_igb_interrupt_handler,
1464 if (dev->data->dev_conf.intr_conf.lsc != 0)
1465 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1466 " no intr multiplex");
1469 /* check if rxq interrupt is enabled */
1470 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1471 rte_intr_dp_is_en(intr_handle))
1472 eth_igb_rxq_interrupt_setup(dev);
1474 /* enable uio/vfio intr/eventfd mapping */
1475 rte_intr_enable(intr_handle);
1477 /* resume enabled intr since hw reset */
1478 igb_intr_enable(dev);
1480 /* restore all types filter */
1481 igb_filter_restore(dev);
1483 eth_igb_rxtx_control(dev, true);
1484 eth_igb_link_update(dev, 0);
1486 PMD_INIT_LOG(DEBUG, "<<");
1490 error_invalid_config:
1491 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1492 dev->data->dev_conf.link_speeds, dev->data->port_id);
1493 igb_dev_clear_queues(dev);
1497 /*********************************************************************
1499 * This routine disables all traffic on the adapter by issuing a
1500 * global reset on the MAC.
1502 **********************************************************************/
1504 eth_igb_stop(struct rte_eth_dev *dev)
1506 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1508 struct rte_eth_link link;
1509 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1511 eth_igb_rxtx_control(dev, false);
1513 igb_intr_disable(dev);
1515 /* disable intr eventfd mapping */
1516 rte_intr_disable(intr_handle);
1518 igb_pf_reset_hw(hw);
1519 E1000_WRITE_REG(hw, E1000_WUC, 0);
1521 /* Set bit for Go Link disconnect */
1522 if (hw->mac.type >= e1000_82580) {
1525 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1526 phpm_reg |= E1000_82580_PM_GO_LINKD;
1527 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1530 /* Power down the phy. Needed to make the link go Down */
1531 eth_igb_dev_set_link_down(dev);
1533 igb_dev_clear_queues(dev);
1535 /* clear the recorded link status */
1536 memset(&link, 0, sizeof(link));
1537 rte_eth_linkstatus_set(dev, &link);
1539 if (!rte_intr_allow_others(intr_handle))
1540 /* resume to the default handler */
1541 rte_intr_callback_register(intr_handle,
1542 eth_igb_interrupt_handler,
1545 /* Clean datapath event and queue/vec mapping */
1546 rte_intr_efd_disable(intr_handle);
1547 if (intr_handle->intr_vec != NULL) {
1548 rte_free(intr_handle->intr_vec);
1549 intr_handle->intr_vec = NULL;
1554 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1556 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1558 if (hw->phy.media_type == e1000_media_type_copper)
1559 e1000_power_up_phy(hw);
1561 e1000_power_up_fiber_serdes_link(hw);
1567 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1569 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571 if (hw->phy.media_type == e1000_media_type_copper)
1572 e1000_power_down_phy(hw);
1574 e1000_shutdown_fiber_serdes_link(hw);
1580 eth_igb_close(struct rte_eth_dev *dev)
1582 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583 struct e1000_adapter *adapter =
1584 E1000_DEV_PRIVATE(dev->data->dev_private);
1585 struct rte_eth_link link;
1586 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1587 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1590 adapter->stopped = 1;
1592 e1000_phy_hw_reset(hw);
1593 igb_release_manageability(hw);
1594 igb_hw_control_release(hw);
1596 /* Clear bit for Go Link disconnect */
1597 if (hw->mac.type >= e1000_82580) {
1600 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1601 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1602 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1605 igb_dev_free_queues(dev);
1607 if (intr_handle->intr_vec) {
1608 rte_free(intr_handle->intr_vec);
1609 intr_handle->intr_vec = NULL;
1612 memset(&link, 0, sizeof(link));
1613 rte_eth_linkstatus_set(dev, &link);
1620 eth_igb_reset(struct rte_eth_dev *dev)
1624 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1625 * its VF to make them align with it. The detailed notification
1626 * mechanism is PMD specific and is currently not implemented.
1627 * To avoid unexpected behavior in VF, currently reset of PF with
1628 * SR-IOV activation is not supported. It might be supported later.
1630 if (dev->data->sriov.active)
1633 ret = eth_igb_dev_uninit(dev);
1637 ret = eth_igb_dev_init(dev);
1644 igb_get_rx_buffer_size(struct e1000_hw *hw)
1646 uint32_t rx_buf_size;
1647 if (hw->mac.type == e1000_82576) {
1648 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1649 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1650 /* PBS needs to be translated according to a lookup table */
1651 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1652 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1653 rx_buf_size = (rx_buf_size << 10);
1654 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1655 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1657 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1663 /*********************************************************************
1665 * Initialize the hardware
1667 **********************************************************************/
1669 igb_hardware_init(struct e1000_hw *hw)
1671 uint32_t rx_buf_size;
1674 /* Let the firmware know the OS is in control */
1675 igb_hw_control_acquire(hw);
1678 * These parameters control the automatic generation (Tx) and
1679 * response (Rx) to Ethernet PAUSE frames.
1680 * - High water mark should allow for at least two standard size (1518)
1681 * frames to be received after sending an XOFF.
1682 * - Low water mark works best when it is very near the high water mark.
1683 * This allows the receiver to restart by sending XON when it has
1684 * drained a bit. Here we use an arbitrary value of 1500 which will
1685 * restart after one full frame is pulled from the buffer. There
1686 * could be several smaller frames in the buffer and if so they will
1687 * not trigger the XON until their total number reduces the buffer
1689 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1691 rx_buf_size = igb_get_rx_buffer_size(hw);
1693 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1694 hw->fc.low_water = hw->fc.high_water - 1500;
1695 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1696 hw->fc.send_xon = 1;
1698 /* Set Flow control, use the tunable location if sane */
1699 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1700 hw->fc.requested_mode = igb_fc_setting;
1702 hw->fc.requested_mode = e1000_fc_none;
1704 /* Issue a global reset */
1705 igb_pf_reset_hw(hw);
1706 E1000_WRITE_REG(hw, E1000_WUC, 0);
1708 diag = e1000_init_hw(hw);
1712 E1000_WRITE_REG(hw, E1000_VET,
1713 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1714 e1000_get_phy_info(hw);
1715 e1000_check_for_link(hw);
1720 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1722 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1726 uint64_t old_gprc = stats->gprc;
1727 uint64_t old_gptc = stats->gptc;
1728 uint64_t old_tpr = stats->tpr;
1729 uint64_t old_tpt = stats->tpt;
1730 uint64_t old_rpthc = stats->rpthc;
1731 uint64_t old_hgptc = stats->hgptc;
1733 if(hw->phy.media_type == e1000_media_type_copper ||
1734 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1736 E1000_READ_REG(hw,E1000_SYMERRS);
1737 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1740 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1741 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1742 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1743 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1745 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1746 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1747 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1748 stats->dc += E1000_READ_REG(hw, E1000_DC);
1749 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1750 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1751 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1753 ** For watchdog management we need to know if we have been
1754 ** paused during the last interval, so capture that here.
1756 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1757 stats->xoffrxc += pause_frames;
1758 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1759 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1760 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1761 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1762 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1763 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1764 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1765 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1766 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1767 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1768 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1769 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1771 /* For the 64-bit byte counters the low dword must be read first. */
1772 /* Both registers clear on the read of the high dword */
1774 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1775 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1776 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1777 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1778 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1779 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1780 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1782 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1783 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1784 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1785 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1786 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1788 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1789 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1791 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1792 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1793 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1794 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1795 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1796 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1798 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1799 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1800 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1801 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1802 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1803 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1804 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1805 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1807 /* Interrupt Counts */
1809 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1810 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1811 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1812 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1813 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1814 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1815 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1816 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1817 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1819 /* Host to Card Statistics */
1821 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1822 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1823 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1824 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1825 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1826 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1827 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1828 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1829 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1830 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1831 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1832 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1833 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1834 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1835 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1836 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1838 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1839 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1840 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1841 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1842 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1843 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1847 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1849 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850 struct e1000_hw_stats *stats =
1851 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1853 igb_read_stats_registers(hw, stats);
1855 if (rte_stats == NULL)
1859 rte_stats->imissed = stats->mpc;
1860 rte_stats->ierrors = stats->crcerrs +
1861 stats->rlec + stats->ruc + stats->roc +
1862 stats->rxerrc + stats->algnerrc + stats->cexterr;
1865 rte_stats->oerrors = stats->ecol + stats->latecol;
1867 rte_stats->ipackets = stats->gprc;
1868 rte_stats->opackets = stats->gptc;
1869 rte_stats->ibytes = stats->gorc;
1870 rte_stats->obytes = stats->gotc;
1875 eth_igb_stats_reset(struct rte_eth_dev *dev)
1877 struct e1000_hw_stats *hw_stats =
1878 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1880 /* HW registers are cleared on read */
1881 eth_igb_stats_get(dev, NULL);
1883 /* Reset software totals */
1884 memset(hw_stats, 0, sizeof(*hw_stats));
1888 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1890 struct e1000_hw_stats *stats =
1891 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1893 /* HW registers are cleared on read */
1894 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1896 /* Reset software totals */
1897 memset(stats, 0, sizeof(*stats));
1900 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1901 struct rte_eth_xstat_name *xstats_names,
1902 __rte_unused unsigned int size)
1906 if (xstats_names == NULL)
1907 return IGB_NB_XSTATS;
1909 /* Note: limit checked in rte_eth_xstats_names() */
1911 for (i = 0; i < IGB_NB_XSTATS; i++) {
1912 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1913 sizeof(xstats_names[i].name));
1916 return IGB_NB_XSTATS;
1919 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1920 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1926 if (xstats_names == NULL)
1927 return IGB_NB_XSTATS;
1929 for (i = 0; i < IGB_NB_XSTATS; i++)
1930 strlcpy(xstats_names[i].name,
1931 rte_igb_stats_strings[i].name,
1932 sizeof(xstats_names[i].name));
1934 return IGB_NB_XSTATS;
1937 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1939 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1942 for (i = 0; i < limit; i++) {
1943 if (ids[i] >= IGB_NB_XSTATS) {
1944 PMD_INIT_LOG(ERR, "id value isn't valid");
1947 strcpy(xstats_names[i].name,
1948 xstats_names_copy[ids[i]].name);
1955 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1958 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959 struct e1000_hw_stats *hw_stats =
1960 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1963 if (n < IGB_NB_XSTATS)
1964 return IGB_NB_XSTATS;
1966 igb_read_stats_registers(hw, hw_stats);
1968 /* If this is a reset xstats is NULL, and we have cleared the
1969 * registers by reading them.
1974 /* Extended stats */
1975 for (i = 0; i < IGB_NB_XSTATS; i++) {
1977 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1978 rte_igb_stats_strings[i].offset);
1981 return IGB_NB_XSTATS;
1985 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1986 uint64_t *values, unsigned int n)
1991 struct e1000_hw *hw =
1992 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993 struct e1000_hw_stats *hw_stats =
1994 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1996 if (n < IGB_NB_XSTATS)
1997 return IGB_NB_XSTATS;
1999 igb_read_stats_registers(hw, hw_stats);
2001 /* If this is a reset xstats is NULL, and we have cleared the
2002 * registers by reading them.
2007 /* Extended stats */
2008 for (i = 0; i < IGB_NB_XSTATS; i++)
2009 values[i] = *(uint64_t *)(((char *)hw_stats) +
2010 rte_igb_stats_strings[i].offset);
2012 return IGB_NB_XSTATS;
2015 uint64_t values_copy[IGB_NB_XSTATS];
2017 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2020 for (i = 0; i < n; i++) {
2021 if (ids[i] >= IGB_NB_XSTATS) {
2022 PMD_INIT_LOG(ERR, "id value isn't valid");
2025 values[i] = values_copy[ids[i]];
2032 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2034 /* Good Rx packets, include VF loopback */
2035 UPDATE_VF_STAT(E1000_VFGPRC,
2036 hw_stats->last_gprc, hw_stats->gprc);
2038 /* Good Rx octets, include VF loopback */
2039 UPDATE_VF_STAT(E1000_VFGORC,
2040 hw_stats->last_gorc, hw_stats->gorc);
2042 /* Good Tx packets, include VF loopback */
2043 UPDATE_VF_STAT(E1000_VFGPTC,
2044 hw_stats->last_gptc, hw_stats->gptc);
2046 /* Good Tx octets, include VF loopback */
2047 UPDATE_VF_STAT(E1000_VFGOTC,
2048 hw_stats->last_gotc, hw_stats->gotc);
2050 /* Rx Multicst packets */
2051 UPDATE_VF_STAT(E1000_VFMPRC,
2052 hw_stats->last_mprc, hw_stats->mprc);
2054 /* Good Rx loopback packets */
2055 UPDATE_VF_STAT(E1000_VFGPRLBC,
2056 hw_stats->last_gprlbc, hw_stats->gprlbc);
2058 /* Good Rx loopback octets */
2059 UPDATE_VF_STAT(E1000_VFGORLBC,
2060 hw_stats->last_gorlbc, hw_stats->gorlbc);
2062 /* Good Tx loopback packets */
2063 UPDATE_VF_STAT(E1000_VFGPTLBC,
2064 hw_stats->last_gptlbc, hw_stats->gptlbc);
2066 /* Good Tx loopback octets */
2067 UPDATE_VF_STAT(E1000_VFGOTLBC,
2068 hw_stats->last_gotlbc, hw_stats->gotlbc);
2071 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2072 struct rte_eth_xstat_name *xstats_names,
2073 __rte_unused unsigned limit)
2077 if (xstats_names != NULL)
2078 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2079 strlcpy(xstats_names[i].name,
2080 rte_igbvf_stats_strings[i].name,
2081 sizeof(xstats_names[i].name));
2083 return IGBVF_NB_XSTATS;
2087 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2090 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2092 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2095 if (n < IGBVF_NB_XSTATS)
2096 return IGBVF_NB_XSTATS;
2098 igbvf_read_stats_registers(hw, hw_stats);
2103 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2105 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2106 rte_igbvf_stats_strings[i].offset);
2109 return IGBVF_NB_XSTATS;
2113 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2115 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2116 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2117 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2119 igbvf_read_stats_registers(hw, hw_stats);
2121 if (rte_stats == NULL)
2124 rte_stats->ipackets = hw_stats->gprc;
2125 rte_stats->ibytes = hw_stats->gorc;
2126 rte_stats->opackets = hw_stats->gptc;
2127 rte_stats->obytes = hw_stats->gotc;
2132 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2134 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2135 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2137 /* Sync HW register to the last stats */
2138 eth_igbvf_stats_get(dev, NULL);
2140 /* reset HW current stats*/
2141 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2142 offsetof(struct e1000_vf_stats, gprc));
2146 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2149 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 struct e1000_fw_version fw;
2153 e1000_get_fw_version(hw, &fw);
2155 switch (hw->mac.type) {
2158 if (!(e1000_get_flash_presence_i210(hw))) {
2159 ret = snprintf(fw_version, fw_size,
2161 fw.invm_major, fw.invm_minor,
2167 /* if option rom is valid, display its version too */
2169 ret = snprintf(fw_version, fw_size,
2170 "%d.%d, 0x%08x, %d.%d.%d",
2171 fw.eep_major, fw.eep_minor, fw.etrack_id,
2172 fw.or_major, fw.or_build, fw.or_patch);
2175 if (fw.etrack_id != 0X0000) {
2176 ret = snprintf(fw_version, fw_size,
2178 fw.eep_major, fw.eep_minor,
2181 ret = snprintf(fw_version, fw_size,
2183 fw.eep_major, fw.eep_minor,
2190 ret += 1; /* add the size of '\0' */
2191 if (fw_size < (u32)ret)
2198 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2200 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2203 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2204 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2205 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2206 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2207 dev_info->rx_queue_offload_capa;
2208 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2209 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2210 dev_info->tx_queue_offload_capa;
2212 switch (hw->mac.type) {
2214 dev_info->max_rx_queues = 4;
2215 dev_info->max_tx_queues = 4;
2216 dev_info->max_vmdq_pools = 0;
2220 dev_info->max_rx_queues = 16;
2221 dev_info->max_tx_queues = 16;
2222 dev_info->max_vmdq_pools = ETH_8_POOLS;
2223 dev_info->vmdq_queue_num = 16;
2227 dev_info->max_rx_queues = 8;
2228 dev_info->max_tx_queues = 8;
2229 dev_info->max_vmdq_pools = ETH_8_POOLS;
2230 dev_info->vmdq_queue_num = 8;
2234 dev_info->max_rx_queues = 8;
2235 dev_info->max_tx_queues = 8;
2236 dev_info->max_vmdq_pools = ETH_8_POOLS;
2237 dev_info->vmdq_queue_num = 8;
2241 dev_info->max_rx_queues = 8;
2242 dev_info->max_tx_queues = 8;
2246 dev_info->max_rx_queues = 4;
2247 dev_info->max_tx_queues = 4;
2248 dev_info->max_vmdq_pools = 0;
2252 dev_info->max_rx_queues = 2;
2253 dev_info->max_tx_queues = 2;
2254 dev_info->max_vmdq_pools = 0;
2258 /* Should not happen */
2261 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2262 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2263 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2265 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2267 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2268 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2269 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2271 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2276 dev_info->default_txconf = (struct rte_eth_txconf) {
2278 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2279 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2280 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2285 dev_info->rx_desc_lim = rx_desc_lim;
2286 dev_info->tx_desc_lim = tx_desc_lim;
2288 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2289 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2292 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2293 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2297 static const uint32_t *
2298 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2300 static const uint32_t ptypes[] = {
2301 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2304 RTE_PTYPE_L3_IPV4_EXT,
2306 RTE_PTYPE_L3_IPV6_EXT,
2310 RTE_PTYPE_TUNNEL_IP,
2311 RTE_PTYPE_INNER_L3_IPV6,
2312 RTE_PTYPE_INNER_L3_IPV6_EXT,
2313 RTE_PTYPE_INNER_L4_TCP,
2314 RTE_PTYPE_INNER_L4_UDP,
2318 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2319 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2325 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2327 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2329 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2330 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2331 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2332 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2333 DEV_TX_OFFLOAD_IPV4_CKSUM |
2334 DEV_TX_OFFLOAD_UDP_CKSUM |
2335 DEV_TX_OFFLOAD_TCP_CKSUM |
2336 DEV_TX_OFFLOAD_SCTP_CKSUM |
2337 DEV_TX_OFFLOAD_TCP_TSO;
2338 switch (hw->mac.type) {
2340 dev_info->max_rx_queues = 2;
2341 dev_info->max_tx_queues = 2;
2343 case e1000_vfadapt_i350:
2344 dev_info->max_rx_queues = 1;
2345 dev_info->max_tx_queues = 1;
2348 /* Should not happen */
2352 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2353 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2354 dev_info->rx_queue_offload_capa;
2355 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2356 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2357 dev_info->tx_queue_offload_capa;
2359 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2361 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2362 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2363 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2365 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2370 dev_info->default_txconf = (struct rte_eth_txconf) {
2372 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2373 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2374 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2379 dev_info->rx_desc_lim = rx_desc_lim;
2380 dev_info->tx_desc_lim = tx_desc_lim;
2383 /* return 0 means link status changed, -1 means not changed */
2385 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2387 struct e1000_hw *hw =
2388 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 struct rte_eth_link link;
2390 int link_check, count;
2393 hw->mac.get_link_status = 1;
2395 /* possible wait-to-complete in up to 9 seconds */
2396 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2397 /* Read the real link status */
2398 switch (hw->phy.media_type) {
2399 case e1000_media_type_copper:
2400 /* Do the work to read phy */
2401 e1000_check_for_link(hw);
2402 link_check = !hw->mac.get_link_status;
2405 case e1000_media_type_fiber:
2406 e1000_check_for_link(hw);
2407 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2411 case e1000_media_type_internal_serdes:
2412 e1000_check_for_link(hw);
2413 link_check = hw->mac.serdes_has_link;
2416 /* VF device is type_unknown */
2417 case e1000_media_type_unknown:
2418 eth_igbvf_link_update(hw);
2419 link_check = !hw->mac.get_link_status;
2425 if (link_check || wait_to_complete == 0)
2427 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2429 memset(&link, 0, sizeof(link));
2431 /* Now we check if a transition has happened */
2433 uint16_t duplex, speed;
2434 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2435 link.link_duplex = (duplex == FULL_DUPLEX) ?
2436 ETH_LINK_FULL_DUPLEX :
2437 ETH_LINK_HALF_DUPLEX;
2438 link.link_speed = speed;
2439 link.link_status = ETH_LINK_UP;
2440 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2441 ETH_LINK_SPEED_FIXED);
2442 } else if (!link_check) {
2443 link.link_speed = 0;
2444 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2445 link.link_status = ETH_LINK_DOWN;
2446 link.link_autoneg = ETH_LINK_FIXED;
2449 return rte_eth_linkstatus_set(dev, &link);
2453 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2454 * For ASF and Pass Through versions of f/w this means
2455 * that the driver is loaded.
2458 igb_hw_control_acquire(struct e1000_hw *hw)
2462 /* Let firmware know the driver has taken over */
2463 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2464 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2468 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2469 * For ASF and Pass Through versions of f/w this means that the
2470 * driver is no longer loaded.
2473 igb_hw_control_release(struct e1000_hw *hw)
2477 /* Let firmware taken over control of h/w */
2478 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2479 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2480 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2484 * Bit of a misnomer, what this really means is
2485 * to enable OS management of the system... aka
2486 * to disable special hardware management features.
2489 igb_init_manageability(struct e1000_hw *hw)
2491 if (e1000_enable_mng_pass_thru(hw)) {
2492 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2493 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2495 /* disable hardware interception of ARP */
2496 manc &= ~(E1000_MANC_ARP_EN);
2498 /* enable receiving management packets to the host */
2499 manc |= E1000_MANC_EN_MNG2HOST;
2500 manc2h |= 1 << 5; /* Mng Port 623 */
2501 manc2h |= 1 << 6; /* Mng Port 664 */
2502 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2503 E1000_WRITE_REG(hw, E1000_MANC, manc);
2508 igb_release_manageability(struct e1000_hw *hw)
2510 if (e1000_enable_mng_pass_thru(hw)) {
2511 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2513 manc |= E1000_MANC_ARP_EN;
2514 manc &= ~E1000_MANC_EN_MNG2HOST;
2516 E1000_WRITE_REG(hw, E1000_MANC, manc);
2521 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2523 struct e1000_hw *hw =
2524 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527 rctl = E1000_READ_REG(hw, E1000_RCTL);
2528 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2529 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2533 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2535 struct e1000_hw *hw =
2536 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539 rctl = E1000_READ_REG(hw, E1000_RCTL);
2540 rctl &= (~E1000_RCTL_UPE);
2541 if (dev->data->all_multicast == 1)
2542 rctl |= E1000_RCTL_MPE;
2544 rctl &= (~E1000_RCTL_MPE);
2545 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2549 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2551 struct e1000_hw *hw =
2552 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555 rctl = E1000_READ_REG(hw, E1000_RCTL);
2556 rctl |= E1000_RCTL_MPE;
2557 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2561 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2563 struct e1000_hw *hw =
2564 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2567 if (dev->data->promiscuous == 1)
2568 return; /* must remain in all_multicast mode */
2569 rctl = E1000_READ_REG(hw, E1000_RCTL);
2570 rctl &= (~E1000_RCTL_MPE);
2571 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2575 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2577 struct e1000_hw *hw =
2578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579 struct e1000_vfta * shadow_vfta =
2580 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2585 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2586 E1000_VFTA_ENTRY_MASK);
2587 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2588 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2593 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2595 /* update local VFTA copy */
2596 shadow_vfta->vfta[vid_idx] = vfta;
2602 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2603 enum rte_vlan_type vlan_type,
2606 struct e1000_hw *hw =
2607 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2611 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2613 /* only outer TPID of double VLAN can be configured*/
2614 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2615 reg = E1000_READ_REG(hw, E1000_VET);
2616 reg = (reg & (~E1000_VET_VET_EXT)) |
2617 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2618 E1000_WRITE_REG(hw, E1000_VET, reg);
2623 /* all other TPID values are read-only*/
2624 PMD_DRV_LOG(ERR, "Not supported");
2630 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2632 struct e1000_hw *hw =
2633 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636 /* Filter Table Disable */
2637 reg = E1000_READ_REG(hw, E1000_RCTL);
2638 reg &= ~E1000_RCTL_CFIEN;
2639 reg &= ~E1000_RCTL_VFE;
2640 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2644 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2646 struct e1000_hw *hw =
2647 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2648 struct e1000_vfta * shadow_vfta =
2649 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2653 /* Filter Table Enable, CFI not used for packet acceptance */
2654 reg = E1000_READ_REG(hw, E1000_RCTL);
2655 reg &= ~E1000_RCTL_CFIEN;
2656 reg |= E1000_RCTL_VFE;
2657 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2659 /* restore VFTA table */
2660 for (i = 0; i < IGB_VFTA_SIZE; i++)
2661 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2665 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2667 struct e1000_hw *hw =
2668 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671 /* VLAN Mode Disable */
2672 reg = E1000_READ_REG(hw, E1000_CTRL);
2673 reg &= ~E1000_CTRL_VME;
2674 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2678 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2680 struct e1000_hw *hw =
2681 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684 /* VLAN Mode Enable */
2685 reg = E1000_READ_REG(hw, E1000_CTRL);
2686 reg |= E1000_CTRL_VME;
2687 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2691 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2693 struct e1000_hw *hw =
2694 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697 /* CTRL_EXT: Extended VLAN */
2698 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2699 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2700 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2702 /* Update maximum packet length */
2703 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2704 E1000_WRITE_REG(hw, E1000_RLPML,
2705 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2710 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2712 struct e1000_hw *hw =
2713 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2716 /* CTRL_EXT: Extended VLAN */
2717 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2718 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2719 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2721 /* Update maximum packet length */
2722 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2723 E1000_WRITE_REG(hw, E1000_RLPML,
2724 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2729 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2731 struct rte_eth_rxmode *rxmode;
2733 rxmode = &dev->data->dev_conf.rxmode;
2734 if(mask & ETH_VLAN_STRIP_MASK){
2735 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2736 igb_vlan_hw_strip_enable(dev);
2738 igb_vlan_hw_strip_disable(dev);
2741 if(mask & ETH_VLAN_FILTER_MASK){
2742 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2743 igb_vlan_hw_filter_enable(dev);
2745 igb_vlan_hw_filter_disable(dev);
2748 if(mask & ETH_VLAN_EXTEND_MASK){
2749 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2750 igb_vlan_hw_extend_enable(dev);
2752 igb_vlan_hw_extend_disable(dev);
2760 * It enables the interrupt mask and then enable the interrupt.
2763 * Pointer to struct rte_eth_dev.
2768 * - On success, zero.
2769 * - On failure, a negative value.
2772 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2774 struct e1000_interrupt *intr =
2775 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2778 intr->mask |= E1000_ICR_LSC;
2780 intr->mask &= ~E1000_ICR_LSC;
2785 /* It clears the interrupt causes and enables the interrupt.
2786 * It will be called once only during nic initialized.
2789 * Pointer to struct rte_eth_dev.
2792 * - On success, zero.
2793 * - On failure, a negative value.
2795 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2797 uint32_t mask, regval;
2798 struct e1000_hw *hw =
2799 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2800 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2801 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2802 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2803 struct rte_eth_dev_info dev_info;
2805 memset(&dev_info, 0, sizeof(dev_info));
2806 eth_igb_infos_get(dev, &dev_info);
2808 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2809 regval = E1000_READ_REG(hw, E1000_EIMS);
2810 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2816 * It reads ICR and gets interrupt causes, check it and set a bit flag
2817 * to update link status.
2820 * Pointer to struct rte_eth_dev.
2823 * - On success, zero.
2824 * - On failure, a negative value.
2827 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2830 struct e1000_hw *hw =
2831 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832 struct e1000_interrupt *intr =
2833 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2835 igb_intr_disable(dev);
2837 /* read-on-clear nic registers here */
2838 icr = E1000_READ_REG(hw, E1000_ICR);
2841 if (icr & E1000_ICR_LSC) {
2842 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2845 if (icr & E1000_ICR_VMMB)
2846 intr->flags |= E1000_FLAG_MAILBOX;
2852 * It executes link_update after knowing an interrupt is prsent.
2855 * Pointer to struct rte_eth_dev.
2858 * - On success, zero.
2859 * - On failure, a negative value.
2862 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2863 struct rte_intr_handle *intr_handle)
2865 struct e1000_hw *hw =
2866 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2867 struct e1000_interrupt *intr =
2868 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2869 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2870 struct rte_eth_link link;
2873 if (intr->flags & E1000_FLAG_MAILBOX) {
2874 igb_pf_mbx_process(dev);
2875 intr->flags &= ~E1000_FLAG_MAILBOX;
2878 igb_intr_enable(dev);
2879 rte_intr_enable(intr_handle);
2881 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2882 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2884 /* set get_link_status to check register later */
2885 hw->mac.get_link_status = 1;
2886 ret = eth_igb_link_update(dev, 0);
2888 /* check if link has changed */
2892 rte_eth_linkstatus_get(dev, &link);
2893 if (link.link_status) {
2895 " Port %d: Link Up - speed %u Mbps - %s",
2897 (unsigned)link.link_speed,
2898 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2899 "full-duplex" : "half-duplex");
2901 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2902 dev->data->port_id);
2905 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2906 pci_dev->addr.domain,
2908 pci_dev->addr.devid,
2909 pci_dev->addr.function);
2910 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2918 * Interrupt handler which shall be registered at first.
2921 * Pointer to interrupt handle.
2923 * The address of parameter (struct rte_eth_dev *) regsitered before.
2929 eth_igb_interrupt_handler(void *param)
2931 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2933 eth_igb_interrupt_get_status(dev);
2934 eth_igb_interrupt_action(dev, dev->intr_handle);
2938 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2941 struct e1000_hw *hw =
2942 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943 struct e1000_interrupt *intr =
2944 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2946 igbvf_intr_disable(hw);
2948 /* read-on-clear nic registers here */
2949 eicr = E1000_READ_REG(hw, E1000_EICR);
2952 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2953 intr->flags |= E1000_FLAG_MAILBOX;
2958 void igbvf_mbx_process(struct rte_eth_dev *dev)
2960 struct e1000_hw *hw =
2961 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962 struct e1000_mbx_info *mbx = &hw->mbx;
2965 /* peek the message first */
2966 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2968 /* PF reset VF event */
2969 if (in_msg == E1000_PF_CONTROL_MSG) {
2970 /* dummy mbx read to ack pf */
2971 if (mbx->ops.read(hw, &in_msg, 1, 0))
2973 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2979 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2981 struct e1000_interrupt *intr =
2982 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2984 if (intr->flags & E1000_FLAG_MAILBOX) {
2985 igbvf_mbx_process(dev);
2986 intr->flags &= ~E1000_FLAG_MAILBOX;
2989 igbvf_intr_enable(dev);
2990 rte_intr_enable(intr_handle);
2996 eth_igbvf_interrupt_handler(void *param)
2998 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3000 eth_igbvf_interrupt_get_status(dev);
3001 eth_igbvf_interrupt_action(dev, dev->intr_handle);
3005 eth_igb_led_on(struct rte_eth_dev *dev)
3007 struct e1000_hw *hw;
3009 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3014 eth_igb_led_off(struct rte_eth_dev *dev)
3016 struct e1000_hw *hw;
3018 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3023 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3025 struct e1000_hw *hw;
3030 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3031 fc_conf->pause_time = hw->fc.pause_time;
3032 fc_conf->high_water = hw->fc.high_water;
3033 fc_conf->low_water = hw->fc.low_water;
3034 fc_conf->send_xon = hw->fc.send_xon;
3035 fc_conf->autoneg = hw->mac.autoneg;
3038 * Return rx_pause and tx_pause status according to actual setting of
3039 * the TFCE and RFCE bits in the CTRL register.
3041 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3042 if (ctrl & E1000_CTRL_TFCE)
3047 if (ctrl & E1000_CTRL_RFCE)
3052 if (rx_pause && tx_pause)
3053 fc_conf->mode = RTE_FC_FULL;
3055 fc_conf->mode = RTE_FC_RX_PAUSE;
3057 fc_conf->mode = RTE_FC_TX_PAUSE;
3059 fc_conf->mode = RTE_FC_NONE;
3065 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3067 struct e1000_hw *hw;
3069 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3075 uint32_t rx_buf_size;
3076 uint32_t max_high_water;
3079 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3080 if (fc_conf->autoneg != hw->mac.autoneg)
3082 rx_buf_size = igb_get_rx_buffer_size(hw);
3083 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3085 /* At least reserve one Ethernet frame for watermark */
3086 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3087 if ((fc_conf->high_water > max_high_water) ||
3088 (fc_conf->high_water < fc_conf->low_water)) {
3089 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3090 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3094 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3095 hw->fc.pause_time = fc_conf->pause_time;
3096 hw->fc.high_water = fc_conf->high_water;
3097 hw->fc.low_water = fc_conf->low_water;
3098 hw->fc.send_xon = fc_conf->send_xon;
3100 err = e1000_setup_link_generic(hw);
3101 if (err == E1000_SUCCESS) {
3103 /* check if we want to forward MAC frames - driver doesn't have native
3104 * capability to do that, so we'll write the registers ourselves */
3106 rctl = E1000_READ_REG(hw, E1000_RCTL);
3108 /* set or clear MFLCN.PMCF bit depending on configuration */
3109 if (fc_conf->mac_ctrl_frame_fwd != 0)
3110 rctl |= E1000_RCTL_PMCF;
3112 rctl &= ~E1000_RCTL_PMCF;
3114 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3115 E1000_WRITE_FLUSH(hw);
3120 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3124 #define E1000_RAH_POOLSEL_SHIFT (18)
3126 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3127 uint32_t index, uint32_t pool)
3129 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3133 rah = E1000_READ_REG(hw, E1000_RAH(index));
3134 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3135 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3140 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3142 uint8_t addr[RTE_ETHER_ADDR_LEN];
3143 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3145 memset(addr, 0, sizeof(addr));
3147 e1000_rar_set(hw, addr, index);
3151 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3152 struct rte_ether_addr *addr)
3154 eth_igb_rar_clear(dev, 0);
3155 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3160 * Virtual Function operations
3163 igbvf_intr_disable(struct e1000_hw *hw)
3165 PMD_INIT_FUNC_TRACE();
3167 /* Clear interrupt mask to stop from interrupts being generated */
3168 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3170 E1000_WRITE_FLUSH(hw);
3174 igbvf_stop_adapter(struct rte_eth_dev *dev)
3178 struct rte_eth_dev_info dev_info;
3179 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3181 memset(&dev_info, 0, sizeof(dev_info));
3182 eth_igbvf_infos_get(dev, &dev_info);
3184 /* Clear interrupt mask to stop from interrupts being generated */
3185 igbvf_intr_disable(hw);
3187 /* Clear any pending interrupts, flush previous writes */
3188 E1000_READ_REG(hw, E1000_EICR);
3190 /* Disable the transmit unit. Each queue must be disabled. */
3191 for (i = 0; i < dev_info.max_tx_queues; i++)
3192 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3194 /* Disable the receive unit by stopping each queue */
3195 for (i = 0; i < dev_info.max_rx_queues; i++) {
3196 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3197 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3198 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3199 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3203 /* flush all queues disables */
3204 E1000_WRITE_FLUSH(hw);
3208 static int eth_igbvf_link_update(struct e1000_hw *hw)
3210 struct e1000_mbx_info *mbx = &hw->mbx;
3211 struct e1000_mac_info *mac = &hw->mac;
3212 int ret_val = E1000_SUCCESS;
3214 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3217 * We only want to run this if there has been a rst asserted.
3218 * in this case that could mean a link change, device reset,
3219 * or a virtual function reset
3222 /* If we were hit with a reset or timeout drop the link */
3223 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3224 mac->get_link_status = TRUE;
3226 if (!mac->get_link_status)
3229 /* if link status is down no point in checking to see if pf is up */
3230 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3233 /* if we passed all the tests above then the link is up and we no
3234 * longer need to check for link */
3235 mac->get_link_status = FALSE;
3243 igbvf_dev_configure(struct rte_eth_dev *dev)
3245 struct rte_eth_conf* conf = &dev->data->dev_conf;
3247 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3248 dev->data->port_id);
3251 * VF has no ability to enable/disable HW CRC
3252 * Keep the persistent behavior the same as Host PF
3254 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3255 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3256 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3257 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3260 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3261 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3262 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3270 igbvf_dev_start(struct rte_eth_dev *dev)
3272 struct e1000_hw *hw =
3273 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3274 struct e1000_adapter *adapter =
3275 E1000_DEV_PRIVATE(dev->data->dev_private);
3276 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3277 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3279 uint32_t intr_vector = 0;
3281 PMD_INIT_FUNC_TRACE();
3283 hw->mac.ops.reset_hw(hw);
3284 adapter->stopped = 0;
3287 igbvf_set_vfta_all(dev,1);
3289 eth_igbvf_tx_init(dev);
3291 /* This can fail when allocating mbufs for descriptor rings */
3292 ret = eth_igbvf_rx_init(dev);
3294 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3295 igb_dev_clear_queues(dev);
3299 /* check and configure queue intr-vector mapping */
3300 if (rte_intr_cap_multiple(intr_handle) &&
3301 dev->data->dev_conf.intr_conf.rxq) {
3302 intr_vector = dev->data->nb_rx_queues;
3303 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3308 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3309 intr_handle->intr_vec =
3310 rte_zmalloc("intr_vec",
3311 dev->data->nb_rx_queues * sizeof(int), 0);
3312 if (!intr_handle->intr_vec) {
3313 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3314 " intr_vec", dev->data->nb_rx_queues);
3319 eth_igbvf_configure_msix_intr(dev);
3321 /* enable uio/vfio intr/eventfd mapping */
3322 rte_intr_enable(intr_handle);
3324 /* resume enabled intr since hw reset */
3325 igbvf_intr_enable(dev);
3331 igbvf_dev_stop(struct rte_eth_dev *dev)
3333 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3334 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3336 PMD_INIT_FUNC_TRACE();
3338 igbvf_stop_adapter(dev);
3341 * Clear what we set, but we still keep shadow_vfta to
3342 * restore after device starts
3344 igbvf_set_vfta_all(dev,0);
3346 igb_dev_clear_queues(dev);
3348 /* disable intr eventfd mapping */
3349 rte_intr_disable(intr_handle);
3351 /* Clean datapath event and queue/vec mapping */
3352 rte_intr_efd_disable(intr_handle);
3353 if (intr_handle->intr_vec) {
3354 rte_free(intr_handle->intr_vec);
3355 intr_handle->intr_vec = NULL;
3360 igbvf_dev_close(struct rte_eth_dev *dev)
3362 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363 struct e1000_adapter *adapter =
3364 E1000_DEV_PRIVATE(dev->data->dev_private);
3365 struct rte_ether_addr addr;
3367 PMD_INIT_FUNC_TRACE();
3371 igbvf_dev_stop(dev);
3372 adapter->stopped = 1;
3373 igb_dev_free_queues(dev);
3376 * reprogram the RAR with a zero mac address,
3377 * to ensure that the VF traffic goes to the PF
3378 * after stop, close and detach of the VF.
3381 memset(&addr, 0, sizeof(addr));
3382 igbvf_default_mac_addr_set(dev, &addr);
3386 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3388 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390 /* Set both unicast and multicast promisc */
3391 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3395 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3397 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399 /* If in allmulticast mode leave multicast promisc */
3400 if (dev->data->all_multicast == 1)
3401 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3403 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3407 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3409 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3411 /* In promiscuous mode multicast promisc already set */
3412 if (dev->data->promiscuous == 0)
3413 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3417 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3419 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3421 /* In promiscuous mode leave multicast promisc enabled */
3422 if (dev->data->promiscuous == 0)
3423 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3426 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3428 struct e1000_mbx_info *mbx = &hw->mbx;
3432 /* After set vlan, vlan strip will also be enabled in igb driver*/
3433 msgbuf[0] = E1000_VF_SET_VLAN;
3435 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3437 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3439 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3443 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3447 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3448 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3455 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3457 struct e1000_hw *hw =
3458 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3459 struct e1000_vfta * shadow_vfta =
3460 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3461 int i = 0, j = 0, vfta = 0, mask = 1;
3463 for (i = 0; i < IGB_VFTA_SIZE; i++){
3464 vfta = shadow_vfta->vfta[i];
3467 for (j = 0; j < 32; j++){
3470 (uint16_t)((i<<5)+j), on);
3479 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3481 struct e1000_hw *hw =
3482 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483 struct e1000_vfta * shadow_vfta =
3484 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3485 uint32_t vid_idx = 0;
3486 uint32_t vid_bit = 0;
3489 PMD_INIT_FUNC_TRACE();
3491 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3492 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3494 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3497 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3498 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3500 /*Save what we set and retore it after device reset*/
3502 shadow_vfta->vfta[vid_idx] |= vid_bit;
3504 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3510 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3512 struct e1000_hw *hw =
3513 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515 /* index is not used by rar_set() */
3516 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3522 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3523 struct rte_eth_rss_reta_entry64 *reta_conf,
3528 uint16_t idx, shift;
3529 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3531 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3532 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3533 "(%d) doesn't match the number hardware can supported "
3534 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3538 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3539 idx = i / RTE_RETA_GROUP_SIZE;
3540 shift = i % RTE_RETA_GROUP_SIZE;
3541 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3545 if (mask == IGB_4_BIT_MASK)
3548 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3549 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3550 if (mask & (0x1 << j))
3551 reta |= reta_conf[idx].reta[shift + j] <<
3554 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3556 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3563 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3564 struct rte_eth_rss_reta_entry64 *reta_conf,
3569 uint16_t idx, shift;
3570 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3573 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3574 "(%d) doesn't match the number hardware can supported "
3575 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3579 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3580 idx = i / RTE_RETA_GROUP_SIZE;
3581 shift = i % RTE_RETA_GROUP_SIZE;
3582 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3586 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3587 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3588 if (mask & (0x1 << j))
3589 reta_conf[idx].reta[shift + j] =
3590 ((reta >> (CHAR_BIT * j)) &
3599 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3600 struct rte_eth_syn_filter *filter,
3603 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604 struct e1000_filter_info *filter_info =
3605 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3606 uint32_t synqf, rfctl;
3608 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3611 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3614 if (synqf & E1000_SYN_FILTER_ENABLE)
3617 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3618 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3620 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3621 if (filter->hig_pri)
3622 rfctl |= E1000_RFCTL_SYNQFP;
3624 rfctl &= ~E1000_RFCTL_SYNQFP;
3626 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3628 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3633 filter_info->syn_info = synqf;
3634 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3635 E1000_WRITE_FLUSH(hw);
3640 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3641 struct rte_eth_syn_filter *filter)
3643 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3644 uint32_t synqf, rfctl;
3646 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3647 if (synqf & E1000_SYN_FILTER_ENABLE) {
3648 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3649 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3650 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3651 E1000_SYN_FILTER_QUEUE_SHIFT);
3659 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3660 enum rte_filter_op filter_op,
3663 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3666 MAC_TYPE_FILTER_SUP(hw->mac.type);
3668 if (filter_op == RTE_ETH_FILTER_NOP)
3672 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3677 switch (filter_op) {
3678 case RTE_ETH_FILTER_ADD:
3679 ret = eth_igb_syn_filter_set(dev,
3680 (struct rte_eth_syn_filter *)arg,
3683 case RTE_ETH_FILTER_DELETE:
3684 ret = eth_igb_syn_filter_set(dev,
3685 (struct rte_eth_syn_filter *)arg,
3688 case RTE_ETH_FILTER_GET:
3689 ret = eth_igb_syn_filter_get(dev,
3690 (struct rte_eth_syn_filter *)arg);
3693 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3701 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3703 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3704 struct e1000_2tuple_filter_info *filter_info)
3706 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3708 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3709 return -EINVAL; /* filter index is out of range. */
3710 if (filter->tcp_flags > TCP_FLAG_ALL)
3711 return -EINVAL; /* flags is invalid. */
3713 switch (filter->dst_port_mask) {
3715 filter_info->dst_port_mask = 0;
3716 filter_info->dst_port = filter->dst_port;
3719 filter_info->dst_port_mask = 1;
3722 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3726 switch (filter->proto_mask) {
3728 filter_info->proto_mask = 0;
3729 filter_info->proto = filter->proto;
3732 filter_info->proto_mask = 1;
3735 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3739 filter_info->priority = (uint8_t)filter->priority;
3740 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3741 filter_info->tcp_flags = filter->tcp_flags;
3743 filter_info->tcp_flags = 0;
3748 static inline struct e1000_2tuple_filter *
3749 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3750 struct e1000_2tuple_filter_info *key)
3752 struct e1000_2tuple_filter *it;
3754 TAILQ_FOREACH(it, filter_list, entries) {
3755 if (memcmp(key, &it->filter_info,
3756 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3763 /* inject a igb 2tuple filter to HW */
3765 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3766 struct e1000_2tuple_filter *filter)
3768 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3769 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3770 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3774 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3775 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3776 imir |= E1000_IMIR_PORT_BP;
3778 imir &= ~E1000_IMIR_PORT_BP;
3780 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3782 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3783 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3784 ttqf |= (uint32_t)(filter->filter_info.proto &
3785 E1000_TTQF_PROTOCOL_MASK);
3786 if (filter->filter_info.proto_mask == 0)
3787 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3789 /* tcp flags bits setting. */
3790 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3791 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3792 imir_ext |= E1000_IMIREXT_CTRL_URG;
3793 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3794 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3795 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3796 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3797 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3798 imir_ext |= E1000_IMIREXT_CTRL_RST;
3799 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3800 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3801 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3802 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3804 imir_ext |= E1000_IMIREXT_CTRL_BP;
3806 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3807 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3808 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3812 * igb_add_2tuple_filter - add a 2tuple filter
3815 * dev: Pointer to struct rte_eth_dev.
3816 * ntuple_filter: ponter to the filter that will be added.
3819 * - On success, zero.
3820 * - On failure, a negative value.
3823 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3824 struct rte_eth_ntuple_filter *ntuple_filter)
3826 struct e1000_filter_info *filter_info =
3827 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3828 struct e1000_2tuple_filter *filter;
3831 filter = rte_zmalloc("e1000_2tuple_filter",
3832 sizeof(struct e1000_2tuple_filter), 0);
3836 ret = ntuple_filter_to_2tuple(ntuple_filter,
3837 &filter->filter_info);
3842 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3843 &filter->filter_info) != NULL) {
3844 PMD_DRV_LOG(ERR, "filter exists.");
3848 filter->queue = ntuple_filter->queue;
3851 * look for an unused 2tuple filter index,
3852 * and insert the filter to list.
3854 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3855 if (!(filter_info->twotuple_mask & (1 << i))) {
3856 filter_info->twotuple_mask |= 1 << i;
3858 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3864 if (i >= E1000_MAX_TTQF_FILTERS) {
3865 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3870 igb_inject_2uple_filter(dev, filter);
3875 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3876 struct e1000_2tuple_filter *filter)
3878 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879 struct e1000_filter_info *filter_info =
3880 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3882 filter_info->twotuple_mask &= ~(1 << filter->index);
3883 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3886 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3887 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3888 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3893 * igb_remove_2tuple_filter - remove a 2tuple filter
3896 * dev: Pointer to struct rte_eth_dev.
3897 * ntuple_filter: ponter to the filter that will be removed.
3900 * - On success, zero.
3901 * - On failure, a negative value.
3904 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3905 struct rte_eth_ntuple_filter *ntuple_filter)
3907 struct e1000_filter_info *filter_info =
3908 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3909 struct e1000_2tuple_filter_info filter_2tuple;
3910 struct e1000_2tuple_filter *filter;
3913 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3914 ret = ntuple_filter_to_2tuple(ntuple_filter,
3919 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3921 if (filter == NULL) {
3922 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3926 igb_delete_2tuple_filter(dev, filter);
3931 /* inject a igb flex filter to HW */
3933 igb_inject_flex_filter(struct rte_eth_dev *dev,
3934 struct e1000_flex_filter *filter)
3936 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937 uint32_t wufc, queueing;
3941 wufc = E1000_READ_REG(hw, E1000_WUFC);
3942 if (filter->index < E1000_MAX_FHFT)
3943 reg_off = E1000_FHFT(filter->index);
3945 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3947 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3948 (E1000_WUFC_FLX0 << filter->index));
3949 queueing = filter->filter_info.len |
3950 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3951 (filter->filter_info.priority <<
3952 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3953 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3956 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3957 E1000_WRITE_REG(hw, reg_off,
3958 filter->filter_info.dwords[j]);
3959 reg_off += sizeof(uint32_t);
3960 E1000_WRITE_REG(hw, reg_off,
3961 filter->filter_info.dwords[++j]);
3962 reg_off += sizeof(uint32_t);
3963 E1000_WRITE_REG(hw, reg_off,
3964 (uint32_t)filter->filter_info.mask[i]);
3965 reg_off += sizeof(uint32_t) * 2;
3970 static inline struct e1000_flex_filter *
3971 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3972 struct e1000_flex_filter_info *key)
3974 struct e1000_flex_filter *it;
3976 TAILQ_FOREACH(it, filter_list, entries) {
3977 if (memcmp(key, &it->filter_info,
3978 sizeof(struct e1000_flex_filter_info)) == 0)
3985 /* remove a flex byte filter
3987 * dev: Pointer to struct rte_eth_dev.
3988 * filter: the pointer of the filter will be removed.
3991 igb_remove_flex_filter(struct rte_eth_dev *dev,
3992 struct e1000_flex_filter *filter)
3994 struct e1000_filter_info *filter_info =
3995 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3996 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4000 wufc = E1000_READ_REG(hw, E1000_WUFC);
4001 if (filter->index < E1000_MAX_FHFT)
4002 reg_off = E1000_FHFT(filter->index);
4004 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4006 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4007 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4009 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4010 (~(E1000_WUFC_FLX0 << filter->index)));
4012 filter_info->flex_mask &= ~(1 << filter->index);
4013 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4018 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4019 struct rte_eth_flex_filter *filter,
4022 struct e1000_filter_info *filter_info =
4023 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4024 struct e1000_flex_filter *flex_filter, *it;
4028 flex_filter = rte_zmalloc("e1000_flex_filter",
4029 sizeof(struct e1000_flex_filter), 0);
4030 if (flex_filter == NULL)
4033 flex_filter->filter_info.len = filter->len;
4034 flex_filter->filter_info.priority = filter->priority;
4035 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4036 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4038 /* reverse bits in flex filter's mask*/
4039 for (shift = 0; shift < CHAR_BIT; shift++) {
4040 if (filter->mask[i] & (0x01 << shift))
4041 mask |= (0x80 >> shift);
4043 flex_filter->filter_info.mask[i] = mask;
4046 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4047 &flex_filter->filter_info);
4048 if (it == NULL && !add) {
4049 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4050 rte_free(flex_filter);
4053 if (it != NULL && add) {
4054 PMD_DRV_LOG(ERR, "filter exists.");
4055 rte_free(flex_filter);
4060 flex_filter->queue = filter->queue;
4062 * look for an unused flex filter index
4063 * and insert the filter into the list.
4065 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4066 if (!(filter_info->flex_mask & (1 << i))) {
4067 filter_info->flex_mask |= 1 << i;
4068 flex_filter->index = i;
4069 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4075 if (i >= E1000_MAX_FLEX_FILTERS) {
4076 PMD_DRV_LOG(ERR, "flex filters are full.");
4077 rte_free(flex_filter);
4081 igb_inject_flex_filter(dev, flex_filter);
4084 igb_remove_flex_filter(dev, it);
4085 rte_free(flex_filter);
4092 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4093 struct rte_eth_flex_filter *filter)
4095 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4096 struct e1000_filter_info *filter_info =
4097 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4098 struct e1000_flex_filter flex_filter, *it;
4099 uint32_t wufc, queueing, wufc_en = 0;
4101 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4102 flex_filter.filter_info.len = filter->len;
4103 flex_filter.filter_info.priority = filter->priority;
4104 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4105 memcpy(flex_filter.filter_info.mask, filter->mask,
4106 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4108 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4109 &flex_filter.filter_info);
4111 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4115 wufc = E1000_READ_REG(hw, E1000_WUFC);
4116 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4118 if ((wufc & wufc_en) == wufc_en) {
4119 uint32_t reg_off = 0;
4120 if (it->index < E1000_MAX_FHFT)
4121 reg_off = E1000_FHFT(it->index);
4123 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4125 queueing = E1000_READ_REG(hw,
4126 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4127 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4128 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4129 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4130 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4131 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4138 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4139 enum rte_filter_op filter_op,
4142 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4143 struct rte_eth_flex_filter *filter;
4146 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4148 if (filter_op == RTE_ETH_FILTER_NOP)
4152 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4157 filter = (struct rte_eth_flex_filter *)arg;
4158 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4159 || filter->len % sizeof(uint64_t) != 0) {
4160 PMD_DRV_LOG(ERR, "filter's length is out of range");
4163 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4164 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4168 switch (filter_op) {
4169 case RTE_ETH_FILTER_ADD:
4170 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4172 case RTE_ETH_FILTER_DELETE:
4173 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4175 case RTE_ETH_FILTER_GET:
4176 ret = eth_igb_get_flex_filter(dev, filter);
4179 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4187 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4189 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4190 struct e1000_5tuple_filter_info *filter_info)
4192 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4194 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4195 return -EINVAL; /* filter index is out of range. */
4196 if (filter->tcp_flags > TCP_FLAG_ALL)
4197 return -EINVAL; /* flags is invalid. */
4199 switch (filter->dst_ip_mask) {
4201 filter_info->dst_ip_mask = 0;
4202 filter_info->dst_ip = filter->dst_ip;
4205 filter_info->dst_ip_mask = 1;
4208 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4212 switch (filter->src_ip_mask) {
4214 filter_info->src_ip_mask = 0;
4215 filter_info->src_ip = filter->src_ip;
4218 filter_info->src_ip_mask = 1;
4221 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4225 switch (filter->dst_port_mask) {
4227 filter_info->dst_port_mask = 0;
4228 filter_info->dst_port = filter->dst_port;
4231 filter_info->dst_port_mask = 1;
4234 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4238 switch (filter->src_port_mask) {
4240 filter_info->src_port_mask = 0;
4241 filter_info->src_port = filter->src_port;
4244 filter_info->src_port_mask = 1;
4247 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4251 switch (filter->proto_mask) {
4253 filter_info->proto_mask = 0;
4254 filter_info->proto = filter->proto;
4257 filter_info->proto_mask = 1;
4260 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4264 filter_info->priority = (uint8_t)filter->priority;
4265 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4266 filter_info->tcp_flags = filter->tcp_flags;
4268 filter_info->tcp_flags = 0;
4273 static inline struct e1000_5tuple_filter *
4274 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4275 struct e1000_5tuple_filter_info *key)
4277 struct e1000_5tuple_filter *it;
4279 TAILQ_FOREACH(it, filter_list, entries) {
4280 if (memcmp(key, &it->filter_info,
4281 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4288 /* inject a igb 5-tuple filter to HW */
4290 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4291 struct e1000_5tuple_filter *filter)
4293 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4294 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4295 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4299 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4300 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4301 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4302 if (filter->filter_info.dst_ip_mask == 0)
4303 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4304 if (filter->filter_info.src_port_mask == 0)
4305 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4306 if (filter->filter_info.proto_mask == 0)
4307 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4308 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4309 E1000_FTQF_QUEUE_MASK;
4310 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4311 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4312 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4313 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4315 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4316 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4318 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4319 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4320 imir |= E1000_IMIR_PORT_BP;
4322 imir &= ~E1000_IMIR_PORT_BP;
4323 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4325 /* tcp flags bits setting. */
4326 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4327 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4328 imir_ext |= E1000_IMIREXT_CTRL_URG;
4329 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4330 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4331 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4332 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4333 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4334 imir_ext |= E1000_IMIREXT_CTRL_RST;
4335 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4336 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4337 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4338 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4340 imir_ext |= E1000_IMIREXT_CTRL_BP;
4342 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4343 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4347 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4350 * dev: Pointer to struct rte_eth_dev.
4351 * ntuple_filter: ponter to the filter that will be added.
4354 * - On success, zero.
4355 * - On failure, a negative value.
4358 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4359 struct rte_eth_ntuple_filter *ntuple_filter)
4361 struct e1000_filter_info *filter_info =
4362 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4363 struct e1000_5tuple_filter *filter;
4367 filter = rte_zmalloc("e1000_5tuple_filter",
4368 sizeof(struct e1000_5tuple_filter), 0);
4372 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4373 &filter->filter_info);
4379 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4380 &filter->filter_info) != NULL) {
4381 PMD_DRV_LOG(ERR, "filter exists.");
4385 filter->queue = ntuple_filter->queue;
4388 * look for an unused 5tuple filter index,
4389 * and insert the filter to list.
4391 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4392 if (!(filter_info->fivetuple_mask & (1 << i))) {
4393 filter_info->fivetuple_mask |= 1 << i;
4395 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4401 if (i >= E1000_MAX_FTQF_FILTERS) {
4402 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4407 igb_inject_5tuple_filter_82576(dev, filter);
4412 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4413 struct e1000_5tuple_filter *filter)
4415 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416 struct e1000_filter_info *filter_info =
4417 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4419 filter_info->fivetuple_mask &= ~(1 << filter->index);
4420 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4423 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4424 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4425 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4426 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4427 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4428 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4429 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4434 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4437 * dev: Pointer to struct rte_eth_dev.
4438 * ntuple_filter: ponter to the filter that will be removed.
4441 * - On success, zero.
4442 * - On failure, a negative value.
4445 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4446 struct rte_eth_ntuple_filter *ntuple_filter)
4448 struct e1000_filter_info *filter_info =
4449 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4450 struct e1000_5tuple_filter_info filter_5tuple;
4451 struct e1000_5tuple_filter *filter;
4454 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4455 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4460 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4462 if (filter == NULL) {
4463 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4467 igb_delete_5tuple_filter_82576(dev, filter);
4473 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4476 struct e1000_hw *hw;
4477 struct rte_eth_dev_info dev_info;
4478 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4480 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482 #ifdef RTE_LIBRTE_82571_SUPPORT
4483 /* XXX: not bigger than max_rx_pktlen */
4484 if (hw->mac.type == e1000_82571)
4487 eth_igb_infos_get(dev, &dev_info);
4489 /* check that mtu is within the allowed range */
4490 if (mtu < RTE_ETHER_MIN_MTU ||
4491 frame_size > dev_info.max_rx_pktlen)
4494 /* refuse mtu that requires the support of scattered packets when this
4495 * feature has not been enabled before. */
4496 if (!dev->data->scattered_rx &&
4497 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4500 rctl = E1000_READ_REG(hw, E1000_RCTL);
4502 /* switch to jumbo mode if needed */
4503 if (frame_size > RTE_ETHER_MAX_LEN) {
4504 dev->data->dev_conf.rxmode.offloads |=
4505 DEV_RX_OFFLOAD_JUMBO_FRAME;
4506 rctl |= E1000_RCTL_LPE;
4508 dev->data->dev_conf.rxmode.offloads &=
4509 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4510 rctl &= ~E1000_RCTL_LPE;
4512 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4514 /* update max frame size */
4515 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4517 E1000_WRITE_REG(hw, E1000_RLPML,
4518 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4524 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4527 * dev: Pointer to struct rte_eth_dev.
4528 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4529 * add: if true, add filter, if false, remove filter
4532 * - On success, zero.
4533 * - On failure, a negative value.
4536 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4537 struct rte_eth_ntuple_filter *ntuple_filter,
4540 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4543 switch (ntuple_filter->flags) {
4544 case RTE_5TUPLE_FLAGS:
4545 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4546 if (hw->mac.type != e1000_82576)
4549 ret = igb_add_5tuple_filter_82576(dev,
4552 ret = igb_remove_5tuple_filter_82576(dev,
4555 case RTE_2TUPLE_FLAGS:
4556 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4557 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4558 hw->mac.type != e1000_i210 &&
4559 hw->mac.type != e1000_i211)
4562 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4564 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4575 * igb_get_ntuple_filter - get a ntuple filter
4578 * dev: Pointer to struct rte_eth_dev.
4579 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4582 * - On success, zero.
4583 * - On failure, a negative value.
4586 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4587 struct rte_eth_ntuple_filter *ntuple_filter)
4589 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4590 struct e1000_filter_info *filter_info =
4591 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4592 struct e1000_5tuple_filter_info filter_5tuple;
4593 struct e1000_2tuple_filter_info filter_2tuple;
4594 struct e1000_5tuple_filter *p_5tuple_filter;
4595 struct e1000_2tuple_filter *p_2tuple_filter;
4598 switch (ntuple_filter->flags) {
4599 case RTE_5TUPLE_FLAGS:
4600 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4601 if (hw->mac.type != e1000_82576)
4603 memset(&filter_5tuple,
4605 sizeof(struct e1000_5tuple_filter_info));
4606 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4610 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4611 &filter_info->fivetuple_list,
4613 if (p_5tuple_filter == NULL) {
4614 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4617 ntuple_filter->queue = p_5tuple_filter->queue;
4619 case RTE_2TUPLE_FLAGS:
4620 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4621 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4623 memset(&filter_2tuple,
4625 sizeof(struct e1000_2tuple_filter_info));
4626 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4629 p_2tuple_filter = igb_2tuple_filter_lookup(
4630 &filter_info->twotuple_list,
4632 if (p_2tuple_filter == NULL) {
4633 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4636 ntuple_filter->queue = p_2tuple_filter->queue;
4647 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4648 * @dev: pointer to rte_eth_dev structure
4649 * @filter_op:operation will be taken.
4650 * @arg: a pointer to specific structure corresponding to the filter_op
4653 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4654 enum rte_filter_op filter_op,
4657 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4660 MAC_TYPE_FILTER_SUP(hw->mac.type);
4662 if (filter_op == RTE_ETH_FILTER_NOP)
4666 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4671 switch (filter_op) {
4672 case RTE_ETH_FILTER_ADD:
4673 ret = igb_add_del_ntuple_filter(dev,
4674 (struct rte_eth_ntuple_filter *)arg,
4677 case RTE_ETH_FILTER_DELETE:
4678 ret = igb_add_del_ntuple_filter(dev,
4679 (struct rte_eth_ntuple_filter *)arg,
4682 case RTE_ETH_FILTER_GET:
4683 ret = igb_get_ntuple_filter(dev,
4684 (struct rte_eth_ntuple_filter *)arg);
4687 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4695 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4700 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4701 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4702 (filter_info->ethertype_mask & (1 << i)))
4709 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4710 uint16_t ethertype, uint32_t etqf)
4714 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4715 if (!(filter_info->ethertype_mask & (1 << i))) {
4716 filter_info->ethertype_mask |= 1 << i;
4717 filter_info->ethertype_filters[i].ethertype = ethertype;
4718 filter_info->ethertype_filters[i].etqf = etqf;
4726 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4729 if (idx >= E1000_MAX_ETQF_FILTERS)
4731 filter_info->ethertype_mask &= ~(1 << idx);
4732 filter_info->ethertype_filters[idx].ethertype = 0;
4733 filter_info->ethertype_filters[idx].etqf = 0;
4739 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4740 struct rte_eth_ethertype_filter *filter,
4743 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744 struct e1000_filter_info *filter_info =
4745 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4749 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4750 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4751 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4752 " ethertype filter.", filter->ether_type);
4756 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4757 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4760 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4761 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4765 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4766 if (ret >= 0 && add) {
4767 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4768 filter->ether_type);
4771 if (ret < 0 && !add) {
4772 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4773 filter->ether_type);
4778 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4779 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4780 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4781 ret = igb_ethertype_filter_insert(filter_info,
4782 filter->ether_type, etqf);
4784 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4788 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4792 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4793 E1000_WRITE_FLUSH(hw);
4799 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4800 struct rte_eth_ethertype_filter *filter)
4802 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4803 struct e1000_filter_info *filter_info =
4804 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4808 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4810 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4811 filter->ether_type);
4815 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4816 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4817 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4819 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4820 E1000_ETQF_QUEUE_SHIFT;
4828 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4829 * @dev: pointer to rte_eth_dev structure
4830 * @filter_op:operation will be taken.
4831 * @arg: a pointer to specific structure corresponding to the filter_op
4834 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4835 enum rte_filter_op filter_op,
4838 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4841 MAC_TYPE_FILTER_SUP(hw->mac.type);
4843 if (filter_op == RTE_ETH_FILTER_NOP)
4847 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4852 switch (filter_op) {
4853 case RTE_ETH_FILTER_ADD:
4854 ret = igb_add_del_ethertype_filter(dev,
4855 (struct rte_eth_ethertype_filter *)arg,
4858 case RTE_ETH_FILTER_DELETE:
4859 ret = igb_add_del_ethertype_filter(dev,
4860 (struct rte_eth_ethertype_filter *)arg,
4863 case RTE_ETH_FILTER_GET:
4864 ret = igb_get_ethertype_filter(dev,
4865 (struct rte_eth_ethertype_filter *)arg);
4868 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4876 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4877 enum rte_filter_type filter_type,
4878 enum rte_filter_op filter_op,
4883 switch (filter_type) {
4884 case RTE_ETH_FILTER_NTUPLE:
4885 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4887 case RTE_ETH_FILTER_ETHERTYPE:
4888 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4890 case RTE_ETH_FILTER_SYN:
4891 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4893 case RTE_ETH_FILTER_FLEXIBLE:
4894 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4896 case RTE_ETH_FILTER_GENERIC:
4897 if (filter_op != RTE_ETH_FILTER_GET)
4899 *(const void **)arg = &igb_flow_ops;
4902 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4911 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4912 struct rte_ether_addr *mc_addr_set,
4913 uint32_t nb_mc_addr)
4915 struct e1000_hw *hw;
4917 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4923 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4925 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926 uint64_t systime_cycles;
4928 switch (hw->mac.type) {
4932 * Need to read System Time Residue Register to be able
4933 * to read the other two registers.
4935 E1000_READ_REG(hw, E1000_SYSTIMR);
4936 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4937 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4938 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4945 * Need to read System Time Residue Register to be able
4946 * to read the other two registers.
4948 E1000_READ_REG(hw, E1000_SYSTIMR);
4949 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4950 /* Only the 8 LSB are valid. */
4951 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4955 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4956 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4961 return systime_cycles;
4965 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4967 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968 uint64_t rx_tstamp_cycles;
4970 switch (hw->mac.type) {
4973 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4974 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4975 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4981 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4982 /* Only the 8 LSB are valid. */
4983 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4987 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4988 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4993 return rx_tstamp_cycles;
4997 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4999 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000 uint64_t tx_tstamp_cycles;
5002 switch (hw->mac.type) {
5005 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5006 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5007 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5013 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5014 /* Only the 8 LSB are valid. */
5015 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5019 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5020 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5025 return tx_tstamp_cycles;
5029 igb_start_timecounters(struct rte_eth_dev *dev)
5031 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5032 struct e1000_adapter *adapter = dev->data->dev_private;
5033 uint32_t incval = 1;
5035 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5037 switch (hw->mac.type) {
5041 /* 32 LSB bits + 8 MSB bits = 40 bits */
5042 mask = (1ULL << 40) - 1;
5047 * Start incrementing the register
5048 * used to timestamp PTP packets.
5050 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5053 incval = E1000_INCVALUE_82576;
5054 shift = IGB_82576_TSYNC_SHIFT;
5055 E1000_WRITE_REG(hw, E1000_TIMINCA,
5056 E1000_INCPERIOD_82576 | incval);
5063 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5064 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5065 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5067 adapter->systime_tc.cc_mask = mask;
5068 adapter->systime_tc.cc_shift = shift;
5069 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5071 adapter->rx_tstamp_tc.cc_mask = mask;
5072 adapter->rx_tstamp_tc.cc_shift = shift;
5073 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5075 adapter->tx_tstamp_tc.cc_mask = mask;
5076 adapter->tx_tstamp_tc.cc_shift = shift;
5077 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5081 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5083 struct e1000_adapter *adapter = dev->data->dev_private;
5085 adapter->systime_tc.nsec += delta;
5086 adapter->rx_tstamp_tc.nsec += delta;
5087 adapter->tx_tstamp_tc.nsec += delta;
5093 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5096 struct e1000_adapter *adapter = dev->data->dev_private;
5098 ns = rte_timespec_to_ns(ts);
5100 /* Set the timecounters to a new value. */
5101 adapter->systime_tc.nsec = ns;
5102 adapter->rx_tstamp_tc.nsec = ns;
5103 adapter->tx_tstamp_tc.nsec = ns;
5109 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5111 uint64_t ns, systime_cycles;
5112 struct e1000_adapter *adapter = dev->data->dev_private;
5114 systime_cycles = igb_read_systime_cyclecounter(dev);
5115 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5116 *ts = rte_ns_to_timespec(ns);
5122 igb_timesync_enable(struct rte_eth_dev *dev)
5124 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5128 /* Stop the timesync system time. */
5129 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5130 /* Reset the timesync system time value. */
5131 switch (hw->mac.type) {
5137 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5140 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5141 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5144 /* Not supported. */
5148 /* Enable system time for it isn't on by default. */
5149 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5150 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5151 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5153 igb_start_timecounters(dev);
5155 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5156 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5157 (RTE_ETHER_TYPE_1588 |
5158 E1000_ETQF_FILTER_ENABLE |
5161 /* Enable timestamping of received PTP packets. */
5162 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5163 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5164 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5166 /* Enable Timestamping of transmitted PTP packets. */
5167 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5168 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5169 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5175 igb_timesync_disable(struct rte_eth_dev *dev)
5177 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5180 /* Disable timestamping of transmitted PTP packets. */
5181 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5182 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5183 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5185 /* Disable timestamping of received PTP packets. */
5186 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5187 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5188 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5190 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5191 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5193 /* Stop incrementating the System Time registers. */
5194 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5200 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5201 struct timespec *timestamp,
5202 uint32_t flags __rte_unused)
5204 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205 struct e1000_adapter *adapter = dev->data->dev_private;
5206 uint32_t tsync_rxctl;
5207 uint64_t rx_tstamp_cycles;
5210 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5211 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5214 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5215 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5216 *timestamp = rte_ns_to_timespec(ns);
5222 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5223 struct timespec *timestamp)
5225 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5226 struct e1000_adapter *adapter = dev->data->dev_private;
5227 uint32_t tsync_txctl;
5228 uint64_t tx_tstamp_cycles;
5231 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5232 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5235 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5236 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5237 *timestamp = rte_ns_to_timespec(ns);
5243 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5247 const struct reg_info *reg_group;
5249 while ((reg_group = igb_regs[g_ind++]))
5250 count += igb_reg_group_count(reg_group);
5256 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5260 const struct reg_info *reg_group;
5262 while ((reg_group = igbvf_regs[g_ind++]))
5263 count += igb_reg_group_count(reg_group);
5269 eth_igb_get_regs(struct rte_eth_dev *dev,
5270 struct rte_dev_reg_info *regs)
5272 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5273 uint32_t *data = regs->data;
5276 const struct reg_info *reg_group;
5279 regs->length = eth_igb_get_reg_length(dev);
5280 regs->width = sizeof(uint32_t);
5284 /* Support only full register dump */
5285 if ((regs->length == 0) ||
5286 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5287 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5289 while ((reg_group = igb_regs[g_ind++]))
5290 count += igb_read_regs_group(dev, &data[count],
5299 igbvf_get_regs(struct rte_eth_dev *dev,
5300 struct rte_dev_reg_info *regs)
5302 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303 uint32_t *data = regs->data;
5306 const struct reg_info *reg_group;
5309 regs->length = igbvf_get_reg_length(dev);
5310 regs->width = sizeof(uint32_t);
5314 /* Support only full register dump */
5315 if ((regs->length == 0) ||
5316 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5317 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5319 while ((reg_group = igbvf_regs[g_ind++]))
5320 count += igb_read_regs_group(dev, &data[count],
5329 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5331 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5333 /* Return unit is byte count */
5334 return hw->nvm.word_size * 2;
5338 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5339 struct rte_dev_eeprom_info *in_eeprom)
5341 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5342 struct e1000_nvm_info *nvm = &hw->nvm;
5343 uint16_t *data = in_eeprom->data;
5346 first = in_eeprom->offset >> 1;
5347 length = in_eeprom->length >> 1;
5348 if ((first >= hw->nvm.word_size) ||
5349 ((first + length) >= hw->nvm.word_size))
5352 in_eeprom->magic = hw->vendor_id |
5353 ((uint32_t)hw->device_id << 16);
5355 if ((nvm->ops.read) == NULL)
5358 return nvm->ops.read(hw, first, length, data);
5362 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5363 struct rte_dev_eeprom_info *in_eeprom)
5365 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5366 struct e1000_nvm_info *nvm = &hw->nvm;
5367 uint16_t *data = in_eeprom->data;
5370 first = in_eeprom->offset >> 1;
5371 length = in_eeprom->length >> 1;
5372 if ((first >= hw->nvm.word_size) ||
5373 ((first + length) >= hw->nvm.word_size))
5376 in_eeprom->magic = (uint32_t)hw->vendor_id |
5377 ((uint32_t)hw->device_id << 16);
5379 if ((nvm->ops.write) == NULL)
5381 return nvm->ops.write(hw, first, length, data);
5385 eth_igb_get_module_info(struct rte_eth_dev *dev,
5386 struct rte_eth_dev_module_info *modinfo)
5388 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5390 uint32_t status = 0;
5391 uint16_t sff8472_rev, addr_mode;
5392 bool page_swap = false;
5394 if (hw->phy.media_type == e1000_media_type_copper ||
5395 hw->phy.media_type == e1000_media_type_unknown)
5398 /* Check whether we support SFF-8472 or not */
5399 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5403 /* addressing mode is not supported */
5404 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5408 /* addressing mode is not supported */
5409 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5411 "Address change required to access page 0xA2, "
5412 "but not supported. Please report the module "
5413 "type to the driver maintainers.\n");
5417 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5418 /* We have an SFP, but it does not support SFF-8472 */
5419 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5420 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5422 /* We have an SFP which supports a revision of SFF-8472 */
5423 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5424 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5431 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5432 struct rte_dev_eeprom_info *info)
5434 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5436 uint32_t status = 0;
5437 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5438 u16 first_word, last_word;
5441 if (info->length == 0)
5444 first_word = info->offset >> 1;
5445 last_word = (info->offset + info->length - 1) >> 1;
5447 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5448 for (i = 0; i < last_word - first_word + 1; i++) {
5449 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5452 /* Error occurred while reading module */
5456 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5459 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5465 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5467 struct e1000_hw *hw =
5468 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5469 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5470 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5471 uint32_t vec = E1000_MISC_VEC_ID;
5473 if (rte_intr_allow_others(intr_handle))
5474 vec = E1000_RX_VEC_START;
5476 uint32_t mask = 1 << (queue_id + vec);
5478 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5479 E1000_WRITE_FLUSH(hw);
5485 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5487 struct e1000_hw *hw =
5488 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5489 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5490 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5491 uint32_t vec = E1000_MISC_VEC_ID;
5493 if (rte_intr_allow_others(intr_handle))
5494 vec = E1000_RX_VEC_START;
5496 uint32_t mask = 1 << (queue_id + vec);
5499 regval = E1000_READ_REG(hw, E1000_EIMS);
5500 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5501 E1000_WRITE_FLUSH(hw);
5503 rte_intr_enable(intr_handle);
5509 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5510 uint8_t index, uint8_t offset)
5512 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5515 val &= ~((uint32_t)0xFF << offset);
5517 /* write vector and valid bit */
5518 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5520 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5524 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5525 uint8_t queue, uint8_t msix_vector)
5529 if (hw->mac.type == e1000_82575) {
5531 tmp = E1000_EICR_RX_QUEUE0 << queue;
5532 else if (direction == 1)
5533 tmp = E1000_EICR_TX_QUEUE0 << queue;
5534 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5535 } else if (hw->mac.type == e1000_82576) {
5536 if ((direction == 0) || (direction == 1))
5537 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5538 ((queue & 0x8) << 1) +
5540 } else if ((hw->mac.type == e1000_82580) ||
5541 (hw->mac.type == e1000_i350) ||
5542 (hw->mac.type == e1000_i354) ||
5543 (hw->mac.type == e1000_i210) ||
5544 (hw->mac.type == e1000_i211)) {
5545 if ((direction == 0) || (direction == 1))
5546 eth_igb_write_ivar(hw, msix_vector,
5548 ((queue & 0x1) << 4) +
5553 /* Sets up the hardware to generate MSI-X interrupts properly
5555 * board private structure
5558 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5561 uint32_t tmpval, regval, intr_mask;
5562 struct e1000_hw *hw =
5563 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5564 uint32_t vec = E1000_MISC_VEC_ID;
5565 uint32_t base = E1000_MISC_VEC_ID;
5566 uint32_t misc_shift = 0;
5567 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5568 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5570 /* won't configure msix register if no mapping is done
5571 * between intr vector and event fd
5573 if (!rte_intr_dp_is_en(intr_handle))
5576 if (rte_intr_allow_others(intr_handle)) {
5577 vec = base = E1000_RX_VEC_START;
5581 /* set interrupt vector for other causes */
5582 if (hw->mac.type == e1000_82575) {
5583 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5584 /* enable MSI-X PBA support */
5585 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5587 /* Auto-Mask interrupts upon ICR read */
5588 tmpval |= E1000_CTRL_EXT_EIAME;
5589 tmpval |= E1000_CTRL_EXT_IRCA;
5591 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5593 /* enable msix_other interrupt */
5594 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5595 regval = E1000_READ_REG(hw, E1000_EIAC);
5596 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5597 regval = E1000_READ_REG(hw, E1000_EIAM);
5598 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5599 } else if ((hw->mac.type == e1000_82576) ||
5600 (hw->mac.type == e1000_82580) ||
5601 (hw->mac.type == e1000_i350) ||
5602 (hw->mac.type == e1000_i354) ||
5603 (hw->mac.type == e1000_i210) ||
5604 (hw->mac.type == e1000_i211)) {
5605 /* turn on MSI-X capability first */
5606 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5607 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5609 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5612 if (dev->data->dev_conf.intr_conf.lsc != 0)
5613 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5615 regval = E1000_READ_REG(hw, E1000_EIAC);
5616 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5618 /* enable msix_other interrupt */
5619 regval = E1000_READ_REG(hw, E1000_EIMS);
5620 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5621 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5622 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5625 /* use EIAM to auto-mask when MSI-X interrupt
5626 * is asserted, this saves a register write for every interrupt
5628 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5631 if (dev->data->dev_conf.intr_conf.lsc != 0)
5632 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5634 regval = E1000_READ_REG(hw, E1000_EIAM);
5635 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5637 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5638 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5639 intr_handle->intr_vec[queue_id] = vec;
5640 if (vec < base + intr_handle->nb_efd - 1)
5644 E1000_WRITE_FLUSH(hw);
5647 /* restore n-tuple filter */
5649 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5651 struct e1000_filter_info *filter_info =
5652 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5653 struct e1000_5tuple_filter *p_5tuple;
5654 struct e1000_2tuple_filter *p_2tuple;
5656 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5657 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5660 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5661 igb_inject_2uple_filter(dev, p_2tuple);
5665 /* restore SYN filter */
5667 igb_syn_filter_restore(struct rte_eth_dev *dev)
5669 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5670 struct e1000_filter_info *filter_info =
5671 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5674 synqf = filter_info->syn_info;
5676 if (synqf & E1000_SYN_FILTER_ENABLE) {
5677 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5678 E1000_WRITE_FLUSH(hw);
5682 /* restore ethernet type filter */
5684 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5686 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5687 struct e1000_filter_info *filter_info =
5688 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5691 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5692 if (filter_info->ethertype_mask & (1 << i)) {
5693 E1000_WRITE_REG(hw, E1000_ETQF(i),
5694 filter_info->ethertype_filters[i].etqf);
5695 E1000_WRITE_FLUSH(hw);
5700 /* restore flex byte filter */
5702 igb_flex_filter_restore(struct rte_eth_dev *dev)
5704 struct e1000_filter_info *filter_info =
5705 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5706 struct e1000_flex_filter *flex_filter;
5708 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5709 igb_inject_flex_filter(dev, flex_filter);
5713 /* restore rss filter */
5715 igb_rss_filter_restore(struct rte_eth_dev *dev)
5717 struct e1000_filter_info *filter_info =
5718 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5720 if (filter_info->rss_info.conf.queue_num)
5721 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5724 /* restore all types filter */
5726 igb_filter_restore(struct rte_eth_dev *dev)
5728 igb_ntuple_filter_restore(dev);
5729 igb_ethertype_filter_restore(dev);
5730 igb_syn_filter_restore(dev);
5731 igb_flex_filter_restore(dev);
5732 igb_rss_filter_restore(dev);
5737 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5738 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5739 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5740 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5741 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5742 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5744 /* see e1000_logs.c */
5745 RTE_INIT(e1000_init_log)
5747 e1000_igb_init_log();