4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "base/e1000_api.h"
58 #include "e1000_ethdev.h"
62 * Default values for port configuration
64 #define IGB_DEFAULT_RX_FREE_THRESH 32
66 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
67 #define IGB_DEFAULT_RX_HTHRESH 8
68 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
70 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
71 #define IGB_DEFAULT_TX_HTHRESH 1
72 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
74 #define IGB_HKEY_MAX_INDEX 10
76 /* Bit shift and mask */
77 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
78 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
79 #define IGB_8_BIT_WIDTH CHAR_BIT
80 #define IGB_8_BIT_MASK UINT8_MAX
82 /* Additional timesync values. */
83 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
84 #define E1000_ETQF_FILTER_1588 3
85 #define IGB_82576_TSYNC_SHIFT 16
86 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
87 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
90 #define E1000_VTIVAR_MISC 0x01740
91 #define E1000_VTIVAR_MISC_MASK 0xFF
92 #define E1000_VTIVAR_VALID 0x80
93 #define E1000_VTIVAR_MISC_MAILBOX 0
94 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
96 /* External VLAN Enable bit mask */
97 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
99 /* External VLAN Ether Type bit mask and shift */
100 #define E1000_VET_VET_EXT 0xFFFF0000
101 #define E1000_VET_VET_EXT_SHIFT 16
103 static int eth_igb_configure(struct rte_eth_dev *dev);
104 static int eth_igb_start(struct rte_eth_dev *dev);
105 static void eth_igb_stop(struct rte_eth_dev *dev);
106 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
107 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
108 static void eth_igb_close(struct rte_eth_dev *dev);
109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
113 static int eth_igb_link_update(struct rte_eth_dev *dev,
114 int wait_to_complete);
115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
116 struct rte_eth_stats *rte_stats);
117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
118 struct rte_eth_xstat *xstats, unsigned n);
119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
121 uint64_t *values, unsigned int n);
122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
123 struct rte_eth_xstat_name *xstats_names,
125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
126 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
131 char *fw_version, size_t fw_size);
132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
133 struct rte_eth_dev_info *dev_info);
134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
136 struct rte_eth_dev_info *dev_info);
137 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
138 struct rte_eth_fc_conf *fc_conf);
139 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
140 struct rte_eth_fc_conf *fc_conf);
141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
145 struct rte_intr_handle *handle);
146 static void eth_igb_interrupt_handler(void *param);
147 static int igb_hardware_init(struct e1000_hw *hw);
148 static void igb_hw_control_acquire(struct e1000_hw *hw);
149 static void igb_hw_control_release(struct e1000_hw *hw);
150 static void igb_init_manageability(struct e1000_hw *hw);
151 static void igb_release_manageability(struct e1000_hw *hw);
153 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
156 uint16_t vlan_id, int on);
157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
158 enum rte_vlan_type vlan_type,
160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
169 static int eth_igb_led_on(struct rte_eth_dev *dev);
170 static int eth_igb_led_off(struct rte_eth_dev *dev);
172 static void igb_intr_disable(struct e1000_hw *hw);
173 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
175 struct ether_addr *mac_addr,
176 uint32_t index, uint32_t pool);
177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
179 struct ether_addr *addr);
181 static void igbvf_intr_disable(struct e1000_hw *hw);
182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
183 static int igbvf_dev_start(struct rte_eth_dev *dev);
184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
185 static void igbvf_dev_close(struct rte_eth_dev *dev);
186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
190 static int eth_igbvf_link_update(struct e1000_hw *hw);
191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
192 struct rte_eth_stats *rte_stats);
193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
194 struct rte_eth_xstat *xstats, unsigned n);
195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
196 struct rte_eth_xstat_name *xstats_names,
198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
200 uint16_t vlan_id, int on);
201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
204 struct ether_addr *addr);
205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
206 static int igbvf_get_regs(struct rte_eth_dev *dev,
207 struct rte_dev_reg_info *regs);
209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
216 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
217 struct rte_eth_syn_filter *filter,
219 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
220 struct rte_eth_syn_filter *filter);
221 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
222 enum rte_filter_op filter_op,
224 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
225 struct rte_eth_ntuple_filter *ntuple_filter);
226 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
227 struct rte_eth_ntuple_filter *ntuple_filter);
228 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
229 struct rte_eth_flex_filter *filter,
231 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
232 struct rte_eth_flex_filter *filter);
233 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
234 enum rte_filter_op filter_op,
236 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
237 struct rte_eth_ntuple_filter *ntuple_filter);
238 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
239 struct rte_eth_ntuple_filter *ntuple_filter);
240 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
241 struct rte_eth_ntuple_filter *filter,
243 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
244 struct rte_eth_ntuple_filter *filter);
245 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
246 enum rte_filter_op filter_op,
248 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
249 struct rte_eth_ethertype_filter *filter,
251 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
252 enum rte_filter_op filter_op,
254 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
255 struct rte_eth_ethertype_filter *filter);
256 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
257 enum rte_filter_type filter_type,
258 enum rte_filter_op filter_op,
260 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
261 static int eth_igb_get_regs(struct rte_eth_dev *dev,
262 struct rte_dev_reg_info *regs);
263 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
264 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
265 struct rte_dev_eeprom_info *eeprom);
266 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
267 struct rte_dev_eeprom_info *eeprom);
268 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
269 struct ether_addr *mc_addr_set,
270 uint32_t nb_mc_addr);
271 static int igb_timesync_enable(struct rte_eth_dev *dev);
272 static int igb_timesync_disable(struct rte_eth_dev *dev);
273 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
274 struct timespec *timestamp,
276 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
277 struct timespec *timestamp);
278 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
279 static int igb_timesync_read_time(struct rte_eth_dev *dev,
280 struct timespec *timestamp);
281 static int igb_timesync_write_time(struct rte_eth_dev *dev,
282 const struct timespec *timestamp);
283 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
285 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
287 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
288 uint8_t queue, uint8_t msix_vector);
289 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
290 uint8_t index, uint8_t offset);
291 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
292 static void eth_igbvf_interrupt_handler(void *param);
293 static void igbvf_mbx_process(struct rte_eth_dev *dev);
294 static int igb_filter_restore(struct rte_eth_dev *dev);
297 * Define VF Stats MACRO for Non "cleared on read" register
299 #define UPDATE_VF_STAT(reg, last, cur) \
301 u32 latest = E1000_READ_REG(hw, reg); \
302 cur += (latest - last) & UINT_MAX; \
306 #define IGB_FC_PAUSE_TIME 0x0680
307 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
308 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
310 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
312 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
315 * The set of PCI devices this driver supports
317 static const struct rte_pci_id pci_id_igb_map[] = {
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
325 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
335 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
336 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
338 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
339 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
340 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
341 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
342 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
343 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
344 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
345 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
346 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
347 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
348 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
349 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
350 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
351 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
352 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
353 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
354 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
355 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
356 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
357 { .vendor_id = 0, /* sentinel */ },
361 * The set of PCI devices this driver supports (for 82576&I350 VF)
363 static const struct rte_pci_id pci_id_igbvf_map[] = {
364 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
365 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
366 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
367 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
368 { .vendor_id = 0, /* sentinel */ },
371 static const struct rte_eth_desc_lim rx_desc_lim = {
372 .nb_max = E1000_MAX_RING_DESC,
373 .nb_min = E1000_MIN_RING_DESC,
374 .nb_align = IGB_RXD_ALIGN,
377 static const struct rte_eth_desc_lim tx_desc_lim = {
378 .nb_max = E1000_MAX_RING_DESC,
379 .nb_min = E1000_MIN_RING_DESC,
380 .nb_align = IGB_RXD_ALIGN,
381 .nb_seg_max = IGB_TX_MAX_SEG,
382 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
385 static const struct eth_dev_ops eth_igb_ops = {
386 .dev_configure = eth_igb_configure,
387 .dev_start = eth_igb_start,
388 .dev_stop = eth_igb_stop,
389 .dev_set_link_up = eth_igb_dev_set_link_up,
390 .dev_set_link_down = eth_igb_dev_set_link_down,
391 .dev_close = eth_igb_close,
392 .promiscuous_enable = eth_igb_promiscuous_enable,
393 .promiscuous_disable = eth_igb_promiscuous_disable,
394 .allmulticast_enable = eth_igb_allmulticast_enable,
395 .allmulticast_disable = eth_igb_allmulticast_disable,
396 .link_update = eth_igb_link_update,
397 .stats_get = eth_igb_stats_get,
398 .xstats_get = eth_igb_xstats_get,
399 .xstats_get_by_id = eth_igb_xstats_get_by_id,
400 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
401 .xstats_get_names = eth_igb_xstats_get_names,
402 .stats_reset = eth_igb_stats_reset,
403 .xstats_reset = eth_igb_xstats_reset,
404 .fw_version_get = eth_igb_fw_version_get,
405 .dev_infos_get = eth_igb_infos_get,
406 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
407 .mtu_set = eth_igb_mtu_set,
408 .vlan_filter_set = eth_igb_vlan_filter_set,
409 .vlan_tpid_set = eth_igb_vlan_tpid_set,
410 .vlan_offload_set = eth_igb_vlan_offload_set,
411 .rx_queue_setup = eth_igb_rx_queue_setup,
412 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
413 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
414 .rx_queue_release = eth_igb_rx_queue_release,
415 .rx_queue_count = eth_igb_rx_queue_count,
416 .rx_descriptor_done = eth_igb_rx_descriptor_done,
417 .rx_descriptor_status = eth_igb_rx_descriptor_status,
418 .tx_descriptor_status = eth_igb_tx_descriptor_status,
419 .tx_queue_setup = eth_igb_tx_queue_setup,
420 .tx_queue_release = eth_igb_tx_queue_release,
421 .tx_done_cleanup = eth_igb_tx_done_cleanup,
422 .dev_led_on = eth_igb_led_on,
423 .dev_led_off = eth_igb_led_off,
424 .flow_ctrl_get = eth_igb_flow_ctrl_get,
425 .flow_ctrl_set = eth_igb_flow_ctrl_set,
426 .mac_addr_add = eth_igb_rar_set,
427 .mac_addr_remove = eth_igb_rar_clear,
428 .mac_addr_set = eth_igb_default_mac_addr_set,
429 .reta_update = eth_igb_rss_reta_update,
430 .reta_query = eth_igb_rss_reta_query,
431 .rss_hash_update = eth_igb_rss_hash_update,
432 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
433 .filter_ctrl = eth_igb_filter_ctrl,
434 .set_mc_addr_list = eth_igb_set_mc_addr_list,
435 .rxq_info_get = igb_rxq_info_get,
436 .txq_info_get = igb_txq_info_get,
437 .timesync_enable = igb_timesync_enable,
438 .timesync_disable = igb_timesync_disable,
439 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
440 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
441 .get_reg = eth_igb_get_regs,
442 .get_eeprom_length = eth_igb_get_eeprom_length,
443 .get_eeprom = eth_igb_get_eeprom,
444 .set_eeprom = eth_igb_set_eeprom,
445 .timesync_adjust_time = igb_timesync_adjust_time,
446 .timesync_read_time = igb_timesync_read_time,
447 .timesync_write_time = igb_timesync_write_time,
451 * dev_ops for virtual function, bare necessities for basic vf
452 * operation have been implemented
454 static const struct eth_dev_ops igbvf_eth_dev_ops = {
455 .dev_configure = igbvf_dev_configure,
456 .dev_start = igbvf_dev_start,
457 .dev_stop = igbvf_dev_stop,
458 .dev_close = igbvf_dev_close,
459 .promiscuous_enable = igbvf_promiscuous_enable,
460 .promiscuous_disable = igbvf_promiscuous_disable,
461 .allmulticast_enable = igbvf_allmulticast_enable,
462 .allmulticast_disable = igbvf_allmulticast_disable,
463 .link_update = eth_igb_link_update,
464 .stats_get = eth_igbvf_stats_get,
465 .xstats_get = eth_igbvf_xstats_get,
466 .xstats_get_names = eth_igbvf_xstats_get_names,
467 .stats_reset = eth_igbvf_stats_reset,
468 .xstats_reset = eth_igbvf_stats_reset,
469 .vlan_filter_set = igbvf_vlan_filter_set,
470 .dev_infos_get = eth_igbvf_infos_get,
471 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
472 .rx_queue_setup = eth_igb_rx_queue_setup,
473 .rx_queue_release = eth_igb_rx_queue_release,
474 .tx_queue_setup = eth_igb_tx_queue_setup,
475 .tx_queue_release = eth_igb_tx_queue_release,
476 .set_mc_addr_list = eth_igb_set_mc_addr_list,
477 .rxq_info_get = igb_rxq_info_get,
478 .txq_info_get = igb_txq_info_get,
479 .mac_addr_set = igbvf_default_mac_addr_set,
480 .get_reg = igbvf_get_regs,
483 /* store statistics names and its offset in stats structure */
484 struct rte_igb_xstats_name_off {
485 char name[RTE_ETH_XSTATS_NAME_SIZE];
489 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
490 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
491 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
492 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
493 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
494 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
495 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
496 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
498 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
499 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
500 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
501 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
502 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
503 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
504 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
505 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
506 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
507 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
508 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
510 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
511 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
512 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
513 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
514 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
516 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
518 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
519 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
520 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
521 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
522 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
523 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
524 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
525 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
526 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
527 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
528 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
529 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
530 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
531 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
532 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
533 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
534 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
535 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
537 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
539 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
540 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
541 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
542 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
543 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
544 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
545 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
547 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
550 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
551 sizeof(rte_igb_stats_strings[0]))
553 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
554 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
555 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
556 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
557 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
558 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
561 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
562 sizeof(rte_igbvf_stats_strings[0]))
565 * Atomically reads the link status information from global
566 * structure rte_eth_dev.
569 * - Pointer to the structure rte_eth_dev to read from.
570 * - Pointer to the buffer to be saved with the link status.
573 * - On success, zero.
574 * - On failure, negative value.
577 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
578 struct rte_eth_link *link)
580 struct rte_eth_link *dst = link;
581 struct rte_eth_link *src = &(dev->data->dev_link);
583 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
584 *(uint64_t *)src) == 0)
591 * Atomically writes the link status information into global
592 * structure rte_eth_dev.
595 * - Pointer to the structure rte_eth_dev to read from.
596 * - Pointer to the buffer to be saved with the link status.
599 * - On success, zero.
600 * - On failure, negative value.
603 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
604 struct rte_eth_link *link)
606 struct rte_eth_link *dst = &(dev->data->dev_link);
607 struct rte_eth_link *src = link;
609 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
610 *(uint64_t *)src) == 0)
617 igb_intr_enable(struct rte_eth_dev *dev)
619 struct e1000_interrupt *intr =
620 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
621 struct e1000_hw *hw =
622 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
624 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
625 E1000_WRITE_FLUSH(hw);
629 igb_intr_disable(struct e1000_hw *hw)
631 E1000_WRITE_REG(hw, E1000_IMC, ~0);
632 E1000_WRITE_FLUSH(hw);
636 igbvf_intr_enable(struct rte_eth_dev *dev)
638 struct e1000_hw *hw =
639 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
641 /* only for mailbox */
642 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
643 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
644 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
645 E1000_WRITE_FLUSH(hw);
648 /* only for mailbox now. If RX/TX needed, should extend this function. */
650 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
655 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
656 tmp |= E1000_VTIVAR_VALID;
657 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
661 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
663 struct e1000_hw *hw =
664 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
666 /* Configure VF other cause ivar */
667 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
670 static inline int32_t
671 igb_pf_reset_hw(struct e1000_hw *hw)
676 status = e1000_reset_hw(hw);
678 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
679 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
680 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
681 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
682 E1000_WRITE_FLUSH(hw);
688 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
690 struct e1000_hw *hw =
691 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
694 hw->vendor_id = pci_dev->id.vendor_id;
695 hw->device_id = pci_dev->id.device_id;
696 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
697 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
699 e1000_set_mac_type(hw);
701 /* need to check if it is a vf device below */
705 igb_reset_swfw_lock(struct e1000_hw *hw)
710 * Do mac ops initialization manually here, since we will need
711 * some function pointers set by this call.
713 ret_val = e1000_init_mac_params(hw);
718 * SMBI lock should not fail in this early stage. If this is the case,
719 * it is due to an improper exit of the application.
720 * So force the release of the faulty lock.
722 if (e1000_get_hw_semaphore_generic(hw) < 0) {
723 PMD_DRV_LOG(DEBUG, "SMBI lock released");
725 e1000_put_hw_semaphore_generic(hw);
727 if (hw->mac.ops.acquire_swfw_sync != NULL) {
731 * Phy lock should not fail in this early stage. If this is the case,
732 * it is due to an improper exit of the application.
733 * So force the release of the faulty lock.
735 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
736 if (hw->bus.func > E1000_FUNC_1)
738 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
739 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
742 hw->mac.ops.release_swfw_sync(hw, mask);
745 * This one is more tricky since it is common to all ports; but
746 * swfw_sync retries last long enough (1s) to be almost sure that if
747 * lock can not be taken it is due to an improper lock of the
750 mask = E1000_SWFW_EEP_SM;
751 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
752 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
754 hw->mac.ops.release_swfw_sync(hw, mask);
757 return E1000_SUCCESS;
760 /* Remove all ntuple filters of the device */
761 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
763 struct e1000_filter_info *filter_info =
764 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
765 struct e1000_5tuple_filter *p_5tuple;
766 struct e1000_2tuple_filter *p_2tuple;
768 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
769 TAILQ_REMOVE(&filter_info->fivetuple_list,
773 filter_info->fivetuple_mask = 0;
774 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
775 TAILQ_REMOVE(&filter_info->twotuple_list,
779 filter_info->twotuple_mask = 0;
784 /* Remove all flex filters of the device */
785 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
787 struct e1000_filter_info *filter_info =
788 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
789 struct e1000_flex_filter *p_flex;
791 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
792 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
795 filter_info->flex_mask = 0;
801 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
804 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
805 struct e1000_hw *hw =
806 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
807 struct e1000_vfta * shadow_vfta =
808 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
809 struct e1000_filter_info *filter_info =
810 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
811 struct e1000_adapter *adapter =
812 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
816 eth_dev->dev_ops = ð_igb_ops;
817 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
818 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
819 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
821 /* for secondary processes, we don't initialise any further as primary
822 * has already done this work. Only check we don't need a different
824 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
825 if (eth_dev->data->scattered_rx)
826 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
830 rte_eth_copy_pci_info(eth_dev, pci_dev);
831 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
833 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
835 igb_identify_hardware(eth_dev, pci_dev);
836 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
841 e1000_get_bus_info(hw);
843 /* Reset any pending lock */
844 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
849 /* Finish initialization */
850 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
856 hw->phy.autoneg_wait_to_complete = 0;
857 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
860 if (hw->phy.media_type == e1000_media_type_copper) {
861 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
862 hw->phy.disable_polarity_correction = 0;
863 hw->phy.ms_type = e1000_ms_hw_default;
867 * Start from a known state, this is important in reading the nvm
872 /* Make sure we have a good EEPROM before we read from it */
873 if (e1000_validate_nvm_checksum(hw) < 0) {
875 * Some PCI-E parts fail the first check due to
876 * the link being in sleep state, call it again,
877 * if it fails a second time its a real issue.
879 if (e1000_validate_nvm_checksum(hw) < 0) {
880 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
886 /* Read the permanent MAC address out of the EEPROM */
887 if (e1000_read_mac_addr(hw) != 0) {
888 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
893 /* Allocate memory for storing MAC addresses */
894 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
895 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
896 if (eth_dev->data->mac_addrs == NULL) {
897 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
898 "store MAC addresses",
899 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
904 /* Copy the permanent MAC address */
905 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
907 /* initialize the vfta */
908 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
910 /* Now initialize the hardware */
911 if (igb_hardware_init(hw) != 0) {
912 PMD_INIT_LOG(ERR, "Hardware initialization failed");
913 rte_free(eth_dev->data->mac_addrs);
914 eth_dev->data->mac_addrs = NULL;
918 hw->mac.get_link_status = 1;
919 adapter->stopped = 0;
921 /* Indicate SOL/IDER usage */
922 if (e1000_check_reset_block(hw) < 0) {
923 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
927 /* initialize PF if max_vfs not zero */
928 igb_pf_host_init(eth_dev);
930 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
931 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
932 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
933 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
934 E1000_WRITE_FLUSH(hw);
936 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
937 eth_dev->data->port_id, pci_dev->id.vendor_id,
938 pci_dev->id.device_id);
940 rte_intr_callback_register(&pci_dev->intr_handle,
941 eth_igb_interrupt_handler,
944 /* enable uio/vfio intr/eventfd mapping */
945 rte_intr_enable(&pci_dev->intr_handle);
947 /* enable support intr */
948 igb_intr_enable(eth_dev);
950 /* initialize filter info */
951 memset(filter_info, 0,
952 sizeof(struct e1000_filter_info));
954 TAILQ_INIT(&filter_info->flex_list);
955 TAILQ_INIT(&filter_info->twotuple_list);
956 TAILQ_INIT(&filter_info->fivetuple_list);
961 igb_hw_control_release(hw);
967 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
969 struct rte_pci_device *pci_dev;
970 struct rte_intr_handle *intr_handle;
972 struct e1000_adapter *adapter =
973 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
974 struct e1000_filter_info *filter_info =
975 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
977 PMD_INIT_FUNC_TRACE();
979 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
982 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
983 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
984 intr_handle = &pci_dev->intr_handle;
986 if (adapter->stopped == 0)
987 eth_igb_close(eth_dev);
989 eth_dev->dev_ops = NULL;
990 eth_dev->rx_pkt_burst = NULL;
991 eth_dev->tx_pkt_burst = NULL;
993 /* Reset any pending lock */
994 igb_reset_swfw_lock(hw);
996 rte_free(eth_dev->data->mac_addrs);
997 eth_dev->data->mac_addrs = NULL;
999 /* uninitialize PF if max_vfs not zero */
1000 igb_pf_host_uninit(eth_dev);
1002 /* disable uio intr before callback unregister */
1003 rte_intr_disable(intr_handle);
1004 rte_intr_callback_unregister(intr_handle,
1005 eth_igb_interrupt_handler, eth_dev);
1007 /* clear the SYN filter info */
1008 filter_info->syn_info = 0;
1010 /* clear the ethertype filters info */
1011 filter_info->ethertype_mask = 0;
1012 memset(filter_info->ethertype_filters, 0,
1013 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1015 /* remove all ntuple filters of the device */
1016 igb_ntuple_filter_uninit(eth_dev);
1018 /* remove all flex filters of the device */
1019 igb_flex_filter_uninit(eth_dev);
1025 * Virtual Function device init
1028 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1030 struct rte_pci_device *pci_dev;
1031 struct rte_intr_handle *intr_handle;
1032 struct e1000_adapter *adapter =
1033 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1034 struct e1000_hw *hw =
1035 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1037 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1039 PMD_INIT_FUNC_TRACE();
1041 eth_dev->dev_ops = &igbvf_eth_dev_ops;
1042 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
1043 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
1044 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
1046 /* for secondary processes, we don't initialise any further as primary
1047 * has already done this work. Only check we don't need a different
1049 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1050 if (eth_dev->data->scattered_rx)
1051 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
1055 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1056 rte_eth_copy_pci_info(eth_dev, pci_dev);
1057 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1059 hw->device_id = pci_dev->id.device_id;
1060 hw->vendor_id = pci_dev->id.vendor_id;
1061 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1062 adapter->stopped = 0;
1064 /* Initialize the shared code (base driver) */
1065 diag = e1000_setup_init_funcs(hw, TRUE);
1067 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1072 /* init_mailbox_params */
1073 hw->mbx.ops.init_params(hw);
1075 /* Disable the interrupts for VF */
1076 igbvf_intr_disable(hw);
1078 diag = hw->mac.ops.reset_hw(hw);
1080 /* Allocate memory for storing MAC addresses */
1081 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1082 hw->mac.rar_entry_count, 0);
1083 if (eth_dev->data->mac_addrs == NULL) {
1085 "Failed to allocate %d bytes needed to store MAC "
1087 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1091 /* Generate a random MAC address, if none was assigned by PF. */
1092 if (is_zero_ether_addr(perm_addr)) {
1093 eth_random_addr(perm_addr->addr_bytes);
1094 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1095 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1096 "%02x:%02x:%02x:%02x:%02x:%02x",
1097 perm_addr->addr_bytes[0],
1098 perm_addr->addr_bytes[1],
1099 perm_addr->addr_bytes[2],
1100 perm_addr->addr_bytes[3],
1101 perm_addr->addr_bytes[4],
1102 perm_addr->addr_bytes[5]);
1105 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1107 rte_free(eth_dev->data->mac_addrs);
1108 eth_dev->data->mac_addrs = NULL;
1111 /* Copy the permanent MAC address */
1112 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1113 ð_dev->data->mac_addrs[0]);
1115 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1117 eth_dev->data->port_id, pci_dev->id.vendor_id,
1118 pci_dev->id.device_id, "igb_mac_82576_vf");
1120 intr_handle = &pci_dev->intr_handle;
1121 rte_intr_callback_register(intr_handle,
1122 eth_igbvf_interrupt_handler, eth_dev);
1128 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1130 struct e1000_adapter *adapter =
1131 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1132 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1134 PMD_INIT_FUNC_TRACE();
1136 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1139 if (adapter->stopped == 0)
1140 igbvf_dev_close(eth_dev);
1142 eth_dev->dev_ops = NULL;
1143 eth_dev->rx_pkt_burst = NULL;
1144 eth_dev->tx_pkt_burst = NULL;
1146 rte_free(eth_dev->data->mac_addrs);
1147 eth_dev->data->mac_addrs = NULL;
1149 /* disable uio intr before callback unregister */
1150 rte_intr_disable(&pci_dev->intr_handle);
1151 rte_intr_callback_unregister(&pci_dev->intr_handle,
1152 eth_igbvf_interrupt_handler,
1158 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1159 struct rte_pci_device *pci_dev)
1161 return rte_eth_dev_pci_generic_probe(pci_dev,
1162 sizeof(struct e1000_adapter), eth_igb_dev_init);
1165 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1167 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1170 static struct rte_pci_driver rte_igb_pmd = {
1171 .id_table = pci_id_igb_map,
1172 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1173 .probe = eth_igb_pci_probe,
1174 .remove = eth_igb_pci_remove,
1178 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1179 struct rte_pci_device *pci_dev)
1181 return rte_eth_dev_pci_generic_probe(pci_dev,
1182 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1185 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1187 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1191 * virtual function driver struct
1193 static struct rte_pci_driver rte_igbvf_pmd = {
1194 .id_table = pci_id_igbvf_map,
1195 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1196 .probe = eth_igbvf_pci_probe,
1197 .remove = eth_igbvf_pci_remove,
1201 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1203 struct e1000_hw *hw =
1204 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1206 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1207 rctl |= E1000_RCTL_VFE;
1208 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1212 igb_check_mq_mode(struct rte_eth_dev *dev)
1214 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1215 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1216 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1217 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1219 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1220 tx_mq_mode == ETH_MQ_TX_DCB ||
1221 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1222 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1225 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1226 /* Check multi-queue mode.
1227 * To no break software we accept ETH_MQ_RX_NONE as this might
1228 * be used to turn off VLAN filter.
1231 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1232 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1233 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1234 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1236 /* Only support one queue on VFs.
1237 * RSS together with SRIOV is not supported.
1239 PMD_INIT_LOG(ERR, "SRIOV is active,"
1240 " wrong mq_mode rx %d.",
1244 /* TX mode is not used here, so mode might be ignored.*/
1245 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1246 /* SRIOV only works in VMDq enable mode */
1247 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1248 " TX mode %d is not supported. "
1249 " Driver will behave as %d mode.",
1250 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1253 /* check valid queue number */
1254 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1255 PMD_INIT_LOG(ERR, "SRIOV is active,"
1256 " only support one queue on VFs.");
1260 /* To no break software that set invalid mode, only display
1261 * warning if invalid mode is used.
1263 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1264 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1265 rx_mq_mode != ETH_MQ_RX_RSS) {
1266 /* RSS together with VMDq not supported*/
1267 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1272 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1273 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1274 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1275 " Due to txmode is meaningless in this"
1276 " driver, just ignore.",
1284 eth_igb_configure(struct rte_eth_dev *dev)
1286 struct e1000_interrupt *intr =
1287 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1290 PMD_INIT_FUNC_TRACE();
1292 /* multipe queue mode checking */
1293 ret = igb_check_mq_mode(dev);
1295 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1300 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1301 PMD_INIT_FUNC_TRACE();
1307 eth_igb_start(struct rte_eth_dev *dev)
1309 struct e1000_hw *hw =
1310 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1311 struct e1000_adapter *adapter =
1312 E1000_DEV_PRIVATE(dev->data->dev_private);
1313 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1314 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1316 uint32_t intr_vector = 0;
1322 PMD_INIT_FUNC_TRACE();
1324 /* disable uio/vfio intr/eventfd mapping */
1325 rte_intr_disable(intr_handle);
1327 /* Power up the phy. Needed to make the link go Up */
1328 eth_igb_dev_set_link_up(dev);
1331 * Packet Buffer Allocation (PBA)
1332 * Writing PBA sets the receive portion of the buffer
1333 * the remainder is used for the transmit buffer.
1335 if (hw->mac.type == e1000_82575) {
1338 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1339 E1000_WRITE_REG(hw, E1000_PBA, pba);
1342 /* Put the address into the Receive Address Array */
1343 e1000_rar_set(hw, hw->mac.addr, 0);
1345 /* Initialize the hardware */
1346 if (igb_hardware_init(hw)) {
1347 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1350 adapter->stopped = 0;
1352 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1354 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1355 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1356 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1357 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1358 E1000_WRITE_FLUSH(hw);
1360 /* configure PF module if SRIOV enabled */
1361 igb_pf_host_configure(dev);
1363 /* check and configure queue intr-vector mapping */
1364 if ((rte_intr_cap_multiple(intr_handle) ||
1365 !RTE_ETH_DEV_SRIOV(dev).active) &&
1366 dev->data->dev_conf.intr_conf.rxq != 0) {
1367 intr_vector = dev->data->nb_rx_queues;
1368 if (rte_intr_efd_enable(intr_handle, intr_vector))
1372 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1373 intr_handle->intr_vec =
1374 rte_zmalloc("intr_vec",
1375 dev->data->nb_rx_queues * sizeof(int), 0);
1376 if (intr_handle->intr_vec == NULL) {
1377 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1378 " intr_vec", dev->data->nb_rx_queues);
1383 /* confiugre msix for rx interrupt */
1384 eth_igb_configure_msix_intr(dev);
1386 /* Configure for OS presence */
1387 igb_init_manageability(hw);
1389 eth_igb_tx_init(dev);
1391 /* This can fail when allocating mbufs for descriptor rings */
1392 ret = eth_igb_rx_init(dev);
1394 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1395 igb_dev_clear_queues(dev);
1399 e1000_clear_hw_cntrs_base_generic(hw);
1402 * VLAN Offload Settings
1404 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1405 ETH_VLAN_EXTEND_MASK;
1406 eth_igb_vlan_offload_set(dev, mask);
1408 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1409 /* Enable VLAN filter since VMDq always use VLAN filter */
1410 igb_vmdq_vlan_hw_filter_enable(dev);
1413 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1414 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1415 (hw->mac.type == e1000_i211)) {
1416 /* Configure EITR with the maximum possible value (0xFFFF) */
1417 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1420 /* Setup link speed and duplex */
1421 speeds = &dev->data->dev_conf.link_speeds;
1422 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1423 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1424 hw->mac.autoneg = 1;
1427 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1430 hw->phy.autoneg_advertised = 0;
1432 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1433 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1434 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1436 goto error_invalid_config;
1438 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1439 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1442 if (*speeds & ETH_LINK_SPEED_10M) {
1443 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1446 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1447 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1450 if (*speeds & ETH_LINK_SPEED_100M) {
1451 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1454 if (*speeds & ETH_LINK_SPEED_1G) {
1455 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1458 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1459 goto error_invalid_config;
1461 /* Set/reset the mac.autoneg based on the link speed,
1465 hw->mac.autoneg = 0;
1466 hw->mac.forced_speed_duplex =
1467 hw->phy.autoneg_advertised;
1469 hw->mac.autoneg = 1;
1473 e1000_setup_link(hw);
1475 if (rte_intr_allow_others(intr_handle)) {
1476 /* check if lsc interrupt is enabled */
1477 if (dev->data->dev_conf.intr_conf.lsc != 0)
1478 eth_igb_lsc_interrupt_setup(dev);
1480 rte_intr_callback_unregister(intr_handle,
1481 eth_igb_interrupt_handler,
1483 if (dev->data->dev_conf.intr_conf.lsc != 0)
1484 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1485 " no intr multiplex");
1488 /* check if rxq interrupt is enabled */
1489 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1490 rte_intr_dp_is_en(intr_handle))
1491 eth_igb_rxq_interrupt_setup(dev);
1493 /* enable uio/vfio intr/eventfd mapping */
1494 rte_intr_enable(intr_handle);
1496 /* resume enabled intr since hw reset */
1497 igb_intr_enable(dev);
1499 /* restore all types filter */
1500 igb_filter_restore(dev);
1502 PMD_INIT_LOG(DEBUG, "<<");
1506 error_invalid_config:
1507 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1508 dev->data->dev_conf.link_speeds, dev->data->port_id);
1509 igb_dev_clear_queues(dev);
1513 /*********************************************************************
1515 * This routine disables all traffic on the adapter by issuing a
1516 * global reset on the MAC.
1518 **********************************************************************/
1520 eth_igb_stop(struct rte_eth_dev *dev)
1522 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1523 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1524 struct rte_eth_link link;
1525 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1527 igb_intr_disable(hw);
1529 /* disable intr eventfd mapping */
1530 rte_intr_disable(intr_handle);
1532 igb_pf_reset_hw(hw);
1533 E1000_WRITE_REG(hw, E1000_WUC, 0);
1535 /* Set bit for Go Link disconnect */
1536 if (hw->mac.type >= e1000_82580) {
1539 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1540 phpm_reg |= E1000_82580_PM_GO_LINKD;
1541 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1544 /* Power down the phy. Needed to make the link go Down */
1545 eth_igb_dev_set_link_down(dev);
1547 igb_dev_clear_queues(dev);
1549 /* clear the recorded link status */
1550 memset(&link, 0, sizeof(link));
1551 rte_igb_dev_atomic_write_link_status(dev, &link);
1553 if (!rte_intr_allow_others(intr_handle))
1554 /* resume to the default handler */
1555 rte_intr_callback_register(intr_handle,
1556 eth_igb_interrupt_handler,
1559 /* Clean datapath event and queue/vec mapping */
1560 rte_intr_efd_disable(intr_handle);
1561 if (intr_handle->intr_vec != NULL) {
1562 rte_free(intr_handle->intr_vec);
1563 intr_handle->intr_vec = NULL;
1568 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1570 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1572 if (hw->phy.media_type == e1000_media_type_copper)
1573 e1000_power_up_phy(hw);
1575 e1000_power_up_fiber_serdes_link(hw);
1581 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1583 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585 if (hw->phy.media_type == e1000_media_type_copper)
1586 e1000_power_down_phy(hw);
1588 e1000_shutdown_fiber_serdes_link(hw);
1594 eth_igb_close(struct rte_eth_dev *dev)
1596 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597 struct e1000_adapter *adapter =
1598 E1000_DEV_PRIVATE(dev->data->dev_private);
1599 struct rte_eth_link link;
1600 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1601 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1604 adapter->stopped = 1;
1606 e1000_phy_hw_reset(hw);
1607 igb_release_manageability(hw);
1608 igb_hw_control_release(hw);
1610 /* Clear bit for Go Link disconnect */
1611 if (hw->mac.type >= e1000_82580) {
1614 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1615 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1616 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1619 igb_dev_free_queues(dev);
1621 if (intr_handle->intr_vec) {
1622 rte_free(intr_handle->intr_vec);
1623 intr_handle->intr_vec = NULL;
1626 memset(&link, 0, sizeof(link));
1627 rte_igb_dev_atomic_write_link_status(dev, &link);
1631 igb_get_rx_buffer_size(struct e1000_hw *hw)
1633 uint32_t rx_buf_size;
1634 if (hw->mac.type == e1000_82576) {
1635 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1636 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1637 /* PBS needs to be translated according to a lookup table */
1638 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1639 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1640 rx_buf_size = (rx_buf_size << 10);
1641 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1642 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1644 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1650 /*********************************************************************
1652 * Initialize the hardware
1654 **********************************************************************/
1656 igb_hardware_init(struct e1000_hw *hw)
1658 uint32_t rx_buf_size;
1661 /* Let the firmware know the OS is in control */
1662 igb_hw_control_acquire(hw);
1665 * These parameters control the automatic generation (Tx) and
1666 * response (Rx) to Ethernet PAUSE frames.
1667 * - High water mark should allow for at least two standard size (1518)
1668 * frames to be received after sending an XOFF.
1669 * - Low water mark works best when it is very near the high water mark.
1670 * This allows the receiver to restart by sending XON when it has
1671 * drained a bit. Here we use an arbitrary value of 1500 which will
1672 * restart after one full frame is pulled from the buffer. There
1673 * could be several smaller frames in the buffer and if so they will
1674 * not trigger the XON until their total number reduces the buffer
1676 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1678 rx_buf_size = igb_get_rx_buffer_size(hw);
1680 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1681 hw->fc.low_water = hw->fc.high_water - 1500;
1682 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1683 hw->fc.send_xon = 1;
1685 /* Set Flow control, use the tunable location if sane */
1686 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1687 hw->fc.requested_mode = igb_fc_setting;
1689 hw->fc.requested_mode = e1000_fc_none;
1691 /* Issue a global reset */
1692 igb_pf_reset_hw(hw);
1693 E1000_WRITE_REG(hw, E1000_WUC, 0);
1695 diag = e1000_init_hw(hw);
1699 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1700 e1000_get_phy_info(hw);
1701 e1000_check_for_link(hw);
1706 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1708 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1712 uint64_t old_gprc = stats->gprc;
1713 uint64_t old_gptc = stats->gptc;
1714 uint64_t old_tpr = stats->tpr;
1715 uint64_t old_tpt = stats->tpt;
1716 uint64_t old_rpthc = stats->rpthc;
1717 uint64_t old_hgptc = stats->hgptc;
1719 if(hw->phy.media_type == e1000_media_type_copper ||
1720 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1722 E1000_READ_REG(hw,E1000_SYMERRS);
1723 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1726 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1727 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1728 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1729 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1731 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1732 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1733 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1734 stats->dc += E1000_READ_REG(hw, E1000_DC);
1735 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1736 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1737 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1739 ** For watchdog management we need to know if we have been
1740 ** paused during the last interval, so capture that here.
1742 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1743 stats->xoffrxc += pause_frames;
1744 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1745 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1746 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1747 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1748 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1749 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1750 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1751 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1752 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1753 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1754 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1755 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1757 /* For the 64-bit byte counters the low dword must be read first. */
1758 /* Both registers clear on the read of the high dword */
1760 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1761 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1762 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1763 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1764 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1765 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1766 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1768 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1769 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1770 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1771 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1772 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1774 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1775 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1777 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1778 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1779 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1780 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1781 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1782 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1784 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1785 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1786 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1787 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1788 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1789 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1790 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1791 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1793 /* Interrupt Counts */
1795 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1796 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1797 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1798 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1799 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1800 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1801 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1802 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1803 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1805 /* Host to Card Statistics */
1807 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1808 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1809 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1810 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1811 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1812 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1813 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1814 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1815 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1816 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1817 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1818 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1819 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1820 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1821 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1822 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1824 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1825 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1826 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1827 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1828 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1829 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1833 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1835 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836 struct e1000_hw_stats *stats =
1837 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1839 igb_read_stats_registers(hw, stats);
1841 if (rte_stats == NULL)
1845 rte_stats->imissed = stats->mpc;
1846 rte_stats->ierrors = stats->crcerrs +
1847 stats->rlec + stats->ruc + stats->roc +
1848 stats->rxerrc + stats->algnerrc + stats->cexterr;
1851 rte_stats->oerrors = stats->ecol + stats->latecol;
1853 rte_stats->ipackets = stats->gprc;
1854 rte_stats->opackets = stats->gptc;
1855 rte_stats->ibytes = stats->gorc;
1856 rte_stats->obytes = stats->gotc;
1860 eth_igb_stats_reset(struct rte_eth_dev *dev)
1862 struct e1000_hw_stats *hw_stats =
1863 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1865 /* HW registers are cleared on read */
1866 eth_igb_stats_get(dev, NULL);
1868 /* Reset software totals */
1869 memset(hw_stats, 0, sizeof(*hw_stats));
1873 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1875 struct e1000_hw_stats *stats =
1876 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1878 /* HW registers are cleared on read */
1879 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1881 /* Reset software totals */
1882 memset(stats, 0, sizeof(*stats));
1885 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1886 struct rte_eth_xstat_name *xstats_names,
1887 __rte_unused unsigned int size)
1891 if (xstats_names == NULL)
1892 return IGB_NB_XSTATS;
1894 /* Note: limit checked in rte_eth_xstats_names() */
1896 for (i = 0; i < IGB_NB_XSTATS; i++) {
1897 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1898 "%s", rte_igb_stats_strings[i].name);
1901 return IGB_NB_XSTATS;
1904 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1905 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1911 if (xstats_names == NULL)
1912 return IGB_NB_XSTATS;
1914 for (i = 0; i < IGB_NB_XSTATS; i++)
1915 snprintf(xstats_names[i].name,
1916 sizeof(xstats_names[i].name),
1917 "%s", rte_igb_stats_strings[i].name);
1919 return IGB_NB_XSTATS;
1922 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1924 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1927 for (i = 0; i < limit; i++) {
1928 if (ids[i] >= IGB_NB_XSTATS) {
1929 PMD_INIT_LOG(ERR, "id value isn't valid");
1932 strcpy(xstats_names[i].name,
1933 xstats_names_copy[ids[i]].name);
1940 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1943 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944 struct e1000_hw_stats *hw_stats =
1945 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1948 if (n < IGB_NB_XSTATS)
1949 return IGB_NB_XSTATS;
1951 igb_read_stats_registers(hw, hw_stats);
1953 /* If this is a reset xstats is NULL, and we have cleared the
1954 * registers by reading them.
1959 /* Extended stats */
1960 for (i = 0; i < IGB_NB_XSTATS; i++) {
1962 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1963 rte_igb_stats_strings[i].offset);
1966 return IGB_NB_XSTATS;
1970 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1971 uint64_t *values, unsigned int n)
1976 struct e1000_hw *hw =
1977 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978 struct e1000_hw_stats *hw_stats =
1979 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1981 if (n < IGB_NB_XSTATS)
1982 return IGB_NB_XSTATS;
1984 igb_read_stats_registers(hw, hw_stats);
1986 /* If this is a reset xstats is NULL, and we have cleared the
1987 * registers by reading them.
1992 /* Extended stats */
1993 for (i = 0; i < IGB_NB_XSTATS; i++)
1994 values[i] = *(uint64_t *)(((char *)hw_stats) +
1995 rte_igb_stats_strings[i].offset);
1997 return IGB_NB_XSTATS;
2000 uint64_t values_copy[IGB_NB_XSTATS];
2002 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2005 for (i = 0; i < n; i++) {
2006 if (ids[i] >= IGB_NB_XSTATS) {
2007 PMD_INIT_LOG(ERR, "id value isn't valid");
2010 values[i] = values_copy[ids[i]];
2017 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2019 /* Good Rx packets, include VF loopback */
2020 UPDATE_VF_STAT(E1000_VFGPRC,
2021 hw_stats->last_gprc, hw_stats->gprc);
2023 /* Good Rx octets, include VF loopback */
2024 UPDATE_VF_STAT(E1000_VFGORC,
2025 hw_stats->last_gorc, hw_stats->gorc);
2027 /* Good Tx packets, include VF loopback */
2028 UPDATE_VF_STAT(E1000_VFGPTC,
2029 hw_stats->last_gptc, hw_stats->gptc);
2031 /* Good Tx octets, include VF loopback */
2032 UPDATE_VF_STAT(E1000_VFGOTC,
2033 hw_stats->last_gotc, hw_stats->gotc);
2035 /* Rx Multicst packets */
2036 UPDATE_VF_STAT(E1000_VFMPRC,
2037 hw_stats->last_mprc, hw_stats->mprc);
2039 /* Good Rx loopback packets */
2040 UPDATE_VF_STAT(E1000_VFGPRLBC,
2041 hw_stats->last_gprlbc, hw_stats->gprlbc);
2043 /* Good Rx loopback octets */
2044 UPDATE_VF_STAT(E1000_VFGORLBC,
2045 hw_stats->last_gorlbc, hw_stats->gorlbc);
2047 /* Good Tx loopback packets */
2048 UPDATE_VF_STAT(E1000_VFGPTLBC,
2049 hw_stats->last_gptlbc, hw_stats->gptlbc);
2051 /* Good Tx loopback octets */
2052 UPDATE_VF_STAT(E1000_VFGOTLBC,
2053 hw_stats->last_gotlbc, hw_stats->gotlbc);
2056 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2057 struct rte_eth_xstat_name *xstats_names,
2058 __rte_unused unsigned limit)
2062 if (xstats_names != NULL)
2063 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2064 snprintf(xstats_names[i].name,
2065 sizeof(xstats_names[i].name), "%s",
2066 rte_igbvf_stats_strings[i].name);
2068 return IGBVF_NB_XSTATS;
2072 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2075 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2076 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2077 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2080 if (n < IGBVF_NB_XSTATS)
2081 return IGBVF_NB_XSTATS;
2083 igbvf_read_stats_registers(hw, hw_stats);
2088 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2090 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2091 rte_igbvf_stats_strings[i].offset);
2094 return IGBVF_NB_XSTATS;
2098 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2100 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2102 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2104 igbvf_read_stats_registers(hw, hw_stats);
2106 if (rte_stats == NULL)
2109 rte_stats->ipackets = hw_stats->gprc;
2110 rte_stats->ibytes = hw_stats->gorc;
2111 rte_stats->opackets = hw_stats->gptc;
2112 rte_stats->obytes = hw_stats->gotc;
2116 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2118 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2119 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2121 /* Sync HW register to the last stats */
2122 eth_igbvf_stats_get(dev, NULL);
2124 /* reset HW current stats*/
2125 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2126 offsetof(struct e1000_vf_stats, gprc));
2130 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2133 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134 struct e1000_fw_version fw;
2137 e1000_get_fw_version(hw, &fw);
2139 switch (hw->mac.type) {
2142 if (!(e1000_get_flash_presence_i210(hw))) {
2143 ret = snprintf(fw_version, fw_size,
2145 fw.invm_major, fw.invm_minor,
2151 /* if option rom is valid, display its version too */
2153 ret = snprintf(fw_version, fw_size,
2154 "%d.%d, 0x%08x, %d.%d.%d",
2155 fw.eep_major, fw.eep_minor, fw.etrack_id,
2156 fw.or_major, fw.or_build, fw.or_patch);
2159 if (fw.etrack_id != 0X0000) {
2160 ret = snprintf(fw_version, fw_size,
2162 fw.eep_major, fw.eep_minor,
2165 ret = snprintf(fw_version, fw_size,
2167 fw.eep_major, fw.eep_minor,
2174 ret += 1; /* add the size of '\0' */
2175 if (fw_size < (u32)ret)
2182 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2184 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2187 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2188 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2189 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2190 dev_info->rx_offload_capa =
2191 DEV_RX_OFFLOAD_VLAN_STRIP |
2192 DEV_RX_OFFLOAD_IPV4_CKSUM |
2193 DEV_RX_OFFLOAD_UDP_CKSUM |
2194 DEV_RX_OFFLOAD_TCP_CKSUM;
2195 dev_info->tx_offload_capa =
2196 DEV_TX_OFFLOAD_VLAN_INSERT |
2197 DEV_TX_OFFLOAD_IPV4_CKSUM |
2198 DEV_TX_OFFLOAD_UDP_CKSUM |
2199 DEV_TX_OFFLOAD_TCP_CKSUM |
2200 DEV_TX_OFFLOAD_SCTP_CKSUM |
2201 DEV_TX_OFFLOAD_TCP_TSO;
2203 switch (hw->mac.type) {
2205 dev_info->max_rx_queues = 4;
2206 dev_info->max_tx_queues = 4;
2207 dev_info->max_vmdq_pools = 0;
2211 dev_info->max_rx_queues = 16;
2212 dev_info->max_tx_queues = 16;
2213 dev_info->max_vmdq_pools = ETH_8_POOLS;
2214 dev_info->vmdq_queue_num = 16;
2218 dev_info->max_rx_queues = 8;
2219 dev_info->max_tx_queues = 8;
2220 dev_info->max_vmdq_pools = ETH_8_POOLS;
2221 dev_info->vmdq_queue_num = 8;
2225 dev_info->max_rx_queues = 8;
2226 dev_info->max_tx_queues = 8;
2227 dev_info->max_vmdq_pools = ETH_8_POOLS;
2228 dev_info->vmdq_queue_num = 8;
2232 dev_info->max_rx_queues = 8;
2233 dev_info->max_tx_queues = 8;
2237 dev_info->max_rx_queues = 4;
2238 dev_info->max_tx_queues = 4;
2239 dev_info->max_vmdq_pools = 0;
2243 dev_info->max_rx_queues = 2;
2244 dev_info->max_tx_queues = 2;
2245 dev_info->max_vmdq_pools = 0;
2249 /* Should not happen */
2252 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2253 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2254 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2256 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2258 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2259 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2260 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2262 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2266 dev_info->default_txconf = (struct rte_eth_txconf) {
2268 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2269 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2270 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2275 dev_info->rx_desc_lim = rx_desc_lim;
2276 dev_info->tx_desc_lim = tx_desc_lim;
2278 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2279 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2283 static const uint32_t *
2284 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2286 static const uint32_t ptypes[] = {
2287 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2290 RTE_PTYPE_L3_IPV4_EXT,
2292 RTE_PTYPE_L3_IPV6_EXT,
2296 RTE_PTYPE_TUNNEL_IP,
2297 RTE_PTYPE_INNER_L3_IPV6,
2298 RTE_PTYPE_INNER_L3_IPV6_EXT,
2299 RTE_PTYPE_INNER_L4_TCP,
2300 RTE_PTYPE_INNER_L4_UDP,
2304 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2305 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2311 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2313 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2316 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2317 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2318 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2319 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2320 DEV_RX_OFFLOAD_IPV4_CKSUM |
2321 DEV_RX_OFFLOAD_UDP_CKSUM |
2322 DEV_RX_OFFLOAD_TCP_CKSUM;
2323 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2324 DEV_TX_OFFLOAD_IPV4_CKSUM |
2325 DEV_TX_OFFLOAD_UDP_CKSUM |
2326 DEV_TX_OFFLOAD_TCP_CKSUM |
2327 DEV_TX_OFFLOAD_SCTP_CKSUM |
2328 DEV_TX_OFFLOAD_TCP_TSO;
2329 switch (hw->mac.type) {
2331 dev_info->max_rx_queues = 2;
2332 dev_info->max_tx_queues = 2;
2334 case e1000_vfadapt_i350:
2335 dev_info->max_rx_queues = 1;
2336 dev_info->max_tx_queues = 1;
2339 /* Should not happen */
2343 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2345 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2346 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2347 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2349 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2353 dev_info->default_txconf = (struct rte_eth_txconf) {
2355 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2356 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2357 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2362 dev_info->rx_desc_lim = rx_desc_lim;
2363 dev_info->tx_desc_lim = tx_desc_lim;
2366 /* return 0 means link status changed, -1 means not changed */
2368 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2370 struct e1000_hw *hw =
2371 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372 struct rte_eth_link link, old;
2373 int link_check, count;
2376 hw->mac.get_link_status = 1;
2378 /* possible wait-to-complete in up to 9 seconds */
2379 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2380 /* Read the real link status */
2381 switch (hw->phy.media_type) {
2382 case e1000_media_type_copper:
2383 /* Do the work to read phy */
2384 e1000_check_for_link(hw);
2385 link_check = !hw->mac.get_link_status;
2388 case e1000_media_type_fiber:
2389 e1000_check_for_link(hw);
2390 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2394 case e1000_media_type_internal_serdes:
2395 e1000_check_for_link(hw);
2396 link_check = hw->mac.serdes_has_link;
2399 /* VF device is type_unknown */
2400 case e1000_media_type_unknown:
2401 eth_igbvf_link_update(hw);
2402 link_check = !hw->mac.get_link_status;
2408 if (link_check || wait_to_complete == 0)
2410 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2412 memset(&link, 0, sizeof(link));
2413 rte_igb_dev_atomic_read_link_status(dev, &link);
2416 /* Now we check if a transition has happened */
2418 uint16_t duplex, speed;
2419 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2420 link.link_duplex = (duplex == FULL_DUPLEX) ?
2421 ETH_LINK_FULL_DUPLEX :
2422 ETH_LINK_HALF_DUPLEX;
2423 link.link_speed = speed;
2424 link.link_status = ETH_LINK_UP;
2425 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2426 ETH_LINK_SPEED_FIXED);
2427 } else if (!link_check) {
2428 link.link_speed = 0;
2429 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2430 link.link_status = ETH_LINK_DOWN;
2431 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2433 rte_igb_dev_atomic_write_link_status(dev, &link);
2436 if (old.link_status == link.link_status)
2444 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2445 * For ASF and Pass Through versions of f/w this means
2446 * that the driver is loaded.
2449 igb_hw_control_acquire(struct e1000_hw *hw)
2453 /* Let firmware know the driver has taken over */
2454 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2455 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2459 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2460 * For ASF and Pass Through versions of f/w this means that the
2461 * driver is no longer loaded.
2464 igb_hw_control_release(struct e1000_hw *hw)
2468 /* Let firmware taken over control of h/w */
2469 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2470 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2471 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2475 * Bit of a misnomer, what this really means is
2476 * to enable OS management of the system... aka
2477 * to disable special hardware management features.
2480 igb_init_manageability(struct e1000_hw *hw)
2482 if (e1000_enable_mng_pass_thru(hw)) {
2483 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2484 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2486 /* disable hardware interception of ARP */
2487 manc &= ~(E1000_MANC_ARP_EN);
2489 /* enable receiving management packets to the host */
2490 manc |= E1000_MANC_EN_MNG2HOST;
2491 manc2h |= 1 << 5; /* Mng Port 623 */
2492 manc2h |= 1 << 6; /* Mng Port 664 */
2493 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2494 E1000_WRITE_REG(hw, E1000_MANC, manc);
2499 igb_release_manageability(struct e1000_hw *hw)
2501 if (e1000_enable_mng_pass_thru(hw)) {
2502 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2504 manc |= E1000_MANC_ARP_EN;
2505 manc &= ~E1000_MANC_EN_MNG2HOST;
2507 E1000_WRITE_REG(hw, E1000_MANC, manc);
2512 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2514 struct e1000_hw *hw =
2515 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518 rctl = E1000_READ_REG(hw, E1000_RCTL);
2519 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2520 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2524 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2526 struct e1000_hw *hw =
2527 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2530 rctl = E1000_READ_REG(hw, E1000_RCTL);
2531 rctl &= (~E1000_RCTL_UPE);
2532 if (dev->data->all_multicast == 1)
2533 rctl |= E1000_RCTL_MPE;
2535 rctl &= (~E1000_RCTL_MPE);
2536 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2540 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2542 struct e1000_hw *hw =
2543 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2546 rctl = E1000_READ_REG(hw, E1000_RCTL);
2547 rctl |= E1000_RCTL_MPE;
2548 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2552 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2554 struct e1000_hw *hw =
2555 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2558 if (dev->data->promiscuous == 1)
2559 return; /* must remain in all_multicast mode */
2560 rctl = E1000_READ_REG(hw, E1000_RCTL);
2561 rctl &= (~E1000_RCTL_MPE);
2562 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2566 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2568 struct e1000_hw *hw =
2569 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570 struct e1000_vfta * shadow_vfta =
2571 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2576 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2577 E1000_VFTA_ENTRY_MASK);
2578 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2579 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2584 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2586 /* update local VFTA copy */
2587 shadow_vfta->vfta[vid_idx] = vfta;
2593 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2594 enum rte_vlan_type vlan_type,
2597 struct e1000_hw *hw =
2598 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2602 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2604 /* only outer TPID of double VLAN can be configured*/
2605 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2606 reg = E1000_READ_REG(hw, E1000_VET);
2607 reg = (reg & (~E1000_VET_VET_EXT)) |
2608 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2609 E1000_WRITE_REG(hw, E1000_VET, reg);
2614 /* all other TPID values are read-only*/
2615 PMD_DRV_LOG(ERR, "Not supported");
2621 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2623 struct e1000_hw *hw =
2624 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627 /* Filter Table Disable */
2628 reg = E1000_READ_REG(hw, E1000_RCTL);
2629 reg &= ~E1000_RCTL_CFIEN;
2630 reg &= ~E1000_RCTL_VFE;
2631 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2635 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2637 struct e1000_hw *hw =
2638 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639 struct e1000_vfta * shadow_vfta =
2640 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2644 /* Filter Table Enable, CFI not used for packet acceptance */
2645 reg = E1000_READ_REG(hw, E1000_RCTL);
2646 reg &= ~E1000_RCTL_CFIEN;
2647 reg |= E1000_RCTL_VFE;
2648 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2650 /* restore VFTA table */
2651 for (i = 0; i < IGB_VFTA_SIZE; i++)
2652 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2656 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2658 struct e1000_hw *hw =
2659 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662 /* VLAN Mode Disable */
2663 reg = E1000_READ_REG(hw, E1000_CTRL);
2664 reg &= ~E1000_CTRL_VME;
2665 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2669 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2671 struct e1000_hw *hw =
2672 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2675 /* VLAN Mode Enable */
2676 reg = E1000_READ_REG(hw, E1000_CTRL);
2677 reg |= E1000_CTRL_VME;
2678 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2682 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2684 struct e1000_hw *hw =
2685 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688 /* CTRL_EXT: Extended VLAN */
2689 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2690 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2691 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2693 /* Update maximum packet length */
2694 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2695 E1000_WRITE_REG(hw, E1000_RLPML,
2696 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2701 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2703 struct e1000_hw *hw =
2704 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707 /* CTRL_EXT: Extended VLAN */
2708 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2709 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2710 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2712 /* Update maximum packet length */
2713 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2714 E1000_WRITE_REG(hw, E1000_RLPML,
2715 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2720 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2722 if(mask & ETH_VLAN_STRIP_MASK){
2723 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2724 igb_vlan_hw_strip_enable(dev);
2726 igb_vlan_hw_strip_disable(dev);
2729 if(mask & ETH_VLAN_FILTER_MASK){
2730 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2731 igb_vlan_hw_filter_enable(dev);
2733 igb_vlan_hw_filter_disable(dev);
2736 if(mask & ETH_VLAN_EXTEND_MASK){
2737 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2738 igb_vlan_hw_extend_enable(dev);
2740 igb_vlan_hw_extend_disable(dev);
2746 * It enables the interrupt mask and then enable the interrupt.
2749 * Pointer to struct rte_eth_dev.
2752 * - On success, zero.
2753 * - On failure, a negative value.
2756 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2758 struct e1000_interrupt *intr =
2759 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2761 intr->mask |= E1000_ICR_LSC;
2766 /* It clears the interrupt causes and enables the interrupt.
2767 * It will be called once only during nic initialized.
2770 * Pointer to struct rte_eth_dev.
2773 * - On success, zero.
2774 * - On failure, a negative value.
2776 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2778 uint32_t mask, regval;
2779 struct e1000_hw *hw =
2780 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2781 struct rte_eth_dev_info dev_info;
2783 memset(&dev_info, 0, sizeof(dev_info));
2784 eth_igb_infos_get(dev, &dev_info);
2786 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2787 regval = E1000_READ_REG(hw, E1000_EIMS);
2788 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2794 * It reads ICR and gets interrupt causes, check it and set a bit flag
2795 * to update link status.
2798 * Pointer to struct rte_eth_dev.
2801 * - On success, zero.
2802 * - On failure, a negative value.
2805 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2808 struct e1000_hw *hw =
2809 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810 struct e1000_interrupt *intr =
2811 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2813 igb_intr_disable(hw);
2815 /* read-on-clear nic registers here */
2816 icr = E1000_READ_REG(hw, E1000_ICR);
2819 if (icr & E1000_ICR_LSC) {
2820 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2823 if (icr & E1000_ICR_VMMB)
2824 intr->flags |= E1000_FLAG_MAILBOX;
2830 * It executes link_update after knowing an interrupt is prsent.
2833 * Pointer to struct rte_eth_dev.
2836 * - On success, zero.
2837 * - On failure, a negative value.
2840 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2841 struct rte_intr_handle *intr_handle)
2843 struct e1000_hw *hw =
2844 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2845 struct e1000_interrupt *intr =
2846 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2847 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2848 uint32_t tctl, rctl;
2849 struct rte_eth_link link;
2852 if (intr->flags & E1000_FLAG_MAILBOX) {
2853 igb_pf_mbx_process(dev);
2854 intr->flags &= ~E1000_FLAG_MAILBOX;
2857 igb_intr_enable(dev);
2858 rte_intr_enable(intr_handle);
2860 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2861 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2863 /* set get_link_status to check register later */
2864 hw->mac.get_link_status = 1;
2865 ret = eth_igb_link_update(dev, 0);
2867 /* check if link has changed */
2871 memset(&link, 0, sizeof(link));
2872 rte_igb_dev_atomic_read_link_status(dev, &link);
2873 if (link.link_status) {
2875 " Port %d: Link Up - speed %u Mbps - %s",
2877 (unsigned)link.link_speed,
2878 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2879 "full-duplex" : "half-duplex");
2881 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2882 dev->data->port_id);
2885 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2886 pci_dev->addr.domain,
2888 pci_dev->addr.devid,
2889 pci_dev->addr.function);
2890 tctl = E1000_READ_REG(hw, E1000_TCTL);
2891 rctl = E1000_READ_REG(hw, E1000_RCTL);
2892 if (link.link_status) {
2894 tctl |= E1000_TCTL_EN;
2895 rctl |= E1000_RCTL_EN;
2898 tctl &= ~E1000_TCTL_EN;
2899 rctl &= ~E1000_RCTL_EN;
2901 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2902 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2903 E1000_WRITE_FLUSH(hw);
2904 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2911 * Interrupt handler which shall be registered at first.
2914 * Pointer to interrupt handle.
2916 * The address of parameter (struct rte_eth_dev *) regsitered before.
2922 eth_igb_interrupt_handler(void *param)
2924 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2926 eth_igb_interrupt_get_status(dev);
2927 eth_igb_interrupt_action(dev, dev->intr_handle);
2931 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2934 struct e1000_hw *hw =
2935 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936 struct e1000_interrupt *intr =
2937 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2939 igbvf_intr_disable(hw);
2941 /* read-on-clear nic registers here */
2942 eicr = E1000_READ_REG(hw, E1000_EICR);
2945 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2946 intr->flags |= E1000_FLAG_MAILBOX;
2951 void igbvf_mbx_process(struct rte_eth_dev *dev)
2953 struct e1000_hw *hw =
2954 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955 struct e1000_mbx_info *mbx = &hw->mbx;
2958 if (mbx->ops.read(hw, &in_msg, 1, 0))
2961 /* PF reset VF event */
2962 if (in_msg == E1000_PF_CONTROL_MSG)
2963 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2967 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2969 struct e1000_interrupt *intr =
2970 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2972 if (intr->flags & E1000_FLAG_MAILBOX) {
2973 igbvf_mbx_process(dev);
2974 intr->flags &= ~E1000_FLAG_MAILBOX;
2977 igbvf_intr_enable(dev);
2978 rte_intr_enable(intr_handle);
2984 eth_igbvf_interrupt_handler(void *param)
2986 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2988 eth_igbvf_interrupt_get_status(dev);
2989 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2993 eth_igb_led_on(struct rte_eth_dev *dev)
2995 struct e1000_hw *hw;
2997 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2998 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3002 eth_igb_led_off(struct rte_eth_dev *dev)
3004 struct e1000_hw *hw;
3006 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3007 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3011 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3013 struct e1000_hw *hw;
3018 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019 fc_conf->pause_time = hw->fc.pause_time;
3020 fc_conf->high_water = hw->fc.high_water;
3021 fc_conf->low_water = hw->fc.low_water;
3022 fc_conf->send_xon = hw->fc.send_xon;
3023 fc_conf->autoneg = hw->mac.autoneg;
3026 * Return rx_pause and tx_pause status according to actual setting of
3027 * the TFCE and RFCE bits in the CTRL register.
3029 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3030 if (ctrl & E1000_CTRL_TFCE)
3035 if (ctrl & E1000_CTRL_RFCE)
3040 if (rx_pause && tx_pause)
3041 fc_conf->mode = RTE_FC_FULL;
3043 fc_conf->mode = RTE_FC_RX_PAUSE;
3045 fc_conf->mode = RTE_FC_TX_PAUSE;
3047 fc_conf->mode = RTE_FC_NONE;
3053 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3055 struct e1000_hw *hw;
3057 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3063 uint32_t rx_buf_size;
3064 uint32_t max_high_water;
3067 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068 if (fc_conf->autoneg != hw->mac.autoneg)
3070 rx_buf_size = igb_get_rx_buffer_size(hw);
3071 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3073 /* At least reserve one Ethernet frame for watermark */
3074 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3075 if ((fc_conf->high_water > max_high_water) ||
3076 (fc_conf->high_water < fc_conf->low_water)) {
3077 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3078 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3082 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3083 hw->fc.pause_time = fc_conf->pause_time;
3084 hw->fc.high_water = fc_conf->high_water;
3085 hw->fc.low_water = fc_conf->low_water;
3086 hw->fc.send_xon = fc_conf->send_xon;
3088 err = e1000_setup_link_generic(hw);
3089 if (err == E1000_SUCCESS) {
3091 /* check if we want to forward MAC frames - driver doesn't have native
3092 * capability to do that, so we'll write the registers ourselves */
3094 rctl = E1000_READ_REG(hw, E1000_RCTL);
3096 /* set or clear MFLCN.PMCF bit depending on configuration */
3097 if (fc_conf->mac_ctrl_frame_fwd != 0)
3098 rctl |= E1000_RCTL_PMCF;
3100 rctl &= ~E1000_RCTL_PMCF;
3102 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3103 E1000_WRITE_FLUSH(hw);
3108 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3112 #define E1000_RAH_POOLSEL_SHIFT (18)
3114 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3115 uint32_t index, uint32_t pool)
3117 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3121 rah = E1000_READ_REG(hw, E1000_RAH(index));
3122 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3123 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3128 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3130 uint8_t addr[ETHER_ADDR_LEN];
3131 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3133 memset(addr, 0, sizeof(addr));
3135 e1000_rar_set(hw, addr, index);
3139 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3140 struct ether_addr *addr)
3142 eth_igb_rar_clear(dev, 0);
3144 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3147 * Virtual Function operations
3150 igbvf_intr_disable(struct e1000_hw *hw)
3152 PMD_INIT_FUNC_TRACE();
3154 /* Clear interrupt mask to stop from interrupts being generated */
3155 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3157 E1000_WRITE_FLUSH(hw);
3161 igbvf_stop_adapter(struct rte_eth_dev *dev)
3165 struct rte_eth_dev_info dev_info;
3166 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3168 memset(&dev_info, 0, sizeof(dev_info));
3169 eth_igbvf_infos_get(dev, &dev_info);
3171 /* Clear interrupt mask to stop from interrupts being generated */
3172 igbvf_intr_disable(hw);
3174 /* Clear any pending interrupts, flush previous writes */
3175 E1000_READ_REG(hw, E1000_EICR);
3177 /* Disable the transmit unit. Each queue must be disabled. */
3178 for (i = 0; i < dev_info.max_tx_queues; i++)
3179 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3181 /* Disable the receive unit by stopping each queue */
3182 for (i = 0; i < dev_info.max_rx_queues; i++) {
3183 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3184 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3185 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3186 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3190 /* flush all queues disables */
3191 E1000_WRITE_FLUSH(hw);
3195 static int eth_igbvf_link_update(struct e1000_hw *hw)
3197 struct e1000_mbx_info *mbx = &hw->mbx;
3198 struct e1000_mac_info *mac = &hw->mac;
3199 int ret_val = E1000_SUCCESS;
3201 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3204 * We only want to run this if there has been a rst asserted.
3205 * in this case that could mean a link change, device reset,
3206 * or a virtual function reset
3209 /* If we were hit with a reset or timeout drop the link */
3210 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3211 mac->get_link_status = TRUE;
3213 if (!mac->get_link_status)
3216 /* if link status is down no point in checking to see if pf is up */
3217 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3220 /* if we passed all the tests above then the link is up and we no
3221 * longer need to check for link */
3222 mac->get_link_status = FALSE;
3230 igbvf_dev_configure(struct rte_eth_dev *dev)
3232 struct rte_eth_conf* conf = &dev->data->dev_conf;
3234 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3235 dev->data->port_id);
3238 * VF has no ability to enable/disable HW CRC
3239 * Keep the persistent behavior the same as Host PF
3241 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3242 if (!conf->rxmode.hw_strip_crc) {
3243 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3244 conf->rxmode.hw_strip_crc = 1;
3247 if (conf->rxmode.hw_strip_crc) {
3248 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3249 conf->rxmode.hw_strip_crc = 0;
3257 igbvf_dev_start(struct rte_eth_dev *dev)
3259 struct e1000_hw *hw =
3260 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3261 struct e1000_adapter *adapter =
3262 E1000_DEV_PRIVATE(dev->data->dev_private);
3263 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3264 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3266 uint32_t intr_vector = 0;
3268 PMD_INIT_FUNC_TRACE();
3270 hw->mac.ops.reset_hw(hw);
3271 adapter->stopped = 0;
3274 igbvf_set_vfta_all(dev,1);
3276 eth_igbvf_tx_init(dev);
3278 /* This can fail when allocating mbufs for descriptor rings */
3279 ret = eth_igbvf_rx_init(dev);
3281 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3282 igb_dev_clear_queues(dev);
3286 /* check and configure queue intr-vector mapping */
3287 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3288 intr_vector = dev->data->nb_rx_queues;
3289 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3294 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3295 intr_handle->intr_vec =
3296 rte_zmalloc("intr_vec",
3297 dev->data->nb_rx_queues * sizeof(int), 0);
3298 if (!intr_handle->intr_vec) {
3299 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3300 " intr_vec", dev->data->nb_rx_queues);
3305 eth_igbvf_configure_msix_intr(dev);
3307 /* enable uio/vfio intr/eventfd mapping */
3308 rte_intr_enable(intr_handle);
3310 /* resume enabled intr since hw reset */
3311 igbvf_intr_enable(dev);
3317 igbvf_dev_stop(struct rte_eth_dev *dev)
3319 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3320 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3322 PMD_INIT_FUNC_TRACE();
3324 igbvf_stop_adapter(dev);
3327 * Clear what we set, but we still keep shadow_vfta to
3328 * restore after device starts
3330 igbvf_set_vfta_all(dev,0);
3332 igb_dev_clear_queues(dev);
3334 /* disable intr eventfd mapping */
3335 rte_intr_disable(intr_handle);
3337 /* Clean datapath event and queue/vec mapping */
3338 rte_intr_efd_disable(intr_handle);
3339 if (intr_handle->intr_vec) {
3340 rte_free(intr_handle->intr_vec);
3341 intr_handle->intr_vec = NULL;
3346 igbvf_dev_close(struct rte_eth_dev *dev)
3348 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3349 struct e1000_adapter *adapter =
3350 E1000_DEV_PRIVATE(dev->data->dev_private);
3351 struct ether_addr addr;
3353 PMD_INIT_FUNC_TRACE();
3357 igbvf_dev_stop(dev);
3358 adapter->stopped = 1;
3359 igb_dev_free_queues(dev);
3362 * reprogram the RAR with a zero mac address,
3363 * to ensure that the VF traffic goes to the PF
3364 * after stop, close and detach of the VF.
3367 memset(&addr, 0, sizeof(addr));
3368 igbvf_default_mac_addr_set(dev, &addr);
3372 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3374 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3376 /* Set both unicast and multicast promisc */
3377 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3381 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3383 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3385 /* If in allmulticast mode leave multicast promisc */
3386 if (dev->data->all_multicast == 1)
3387 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3389 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3393 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3395 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3397 /* In promiscuous mode multicast promisc already set */
3398 if (dev->data->promiscuous == 0)
3399 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3403 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3405 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3407 /* In promiscuous mode leave multicast promisc enabled */
3408 if (dev->data->promiscuous == 0)
3409 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3412 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3414 struct e1000_mbx_info *mbx = &hw->mbx;
3418 /* After set vlan, vlan strip will also be enabled in igb driver*/
3419 msgbuf[0] = E1000_VF_SET_VLAN;
3421 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3423 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3425 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3429 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3433 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3434 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3441 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3443 struct e1000_hw *hw =
3444 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445 struct e1000_vfta * shadow_vfta =
3446 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3447 int i = 0, j = 0, vfta = 0, mask = 1;
3449 for (i = 0; i < IGB_VFTA_SIZE; i++){
3450 vfta = shadow_vfta->vfta[i];
3453 for (j = 0; j < 32; j++){
3456 (uint16_t)((i<<5)+j), on);
3465 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3467 struct e1000_hw *hw =
3468 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469 struct e1000_vfta * shadow_vfta =
3470 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3471 uint32_t vid_idx = 0;
3472 uint32_t vid_bit = 0;
3475 PMD_INIT_FUNC_TRACE();
3477 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3478 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3480 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3483 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3484 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3486 /*Save what we set and retore it after device reset*/
3488 shadow_vfta->vfta[vid_idx] |= vid_bit;
3490 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3496 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3498 struct e1000_hw *hw =
3499 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3501 /* index is not used by rar_set() */
3502 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3507 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3508 struct rte_eth_rss_reta_entry64 *reta_conf,
3513 uint16_t idx, shift;
3514 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3517 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3518 "(%d) doesn't match the number hardware can supported "
3519 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3523 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3524 idx = i / RTE_RETA_GROUP_SIZE;
3525 shift = i % RTE_RETA_GROUP_SIZE;
3526 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3530 if (mask == IGB_4_BIT_MASK)
3533 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3534 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3535 if (mask & (0x1 << j))
3536 reta |= reta_conf[idx].reta[shift + j] <<
3539 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3541 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3548 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3549 struct rte_eth_rss_reta_entry64 *reta_conf,
3554 uint16_t idx, shift;
3555 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3557 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3558 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3559 "(%d) doesn't match the number hardware can supported "
3560 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3564 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3565 idx = i / RTE_RETA_GROUP_SIZE;
3566 shift = i % RTE_RETA_GROUP_SIZE;
3567 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3571 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3572 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3573 if (mask & (0x1 << j))
3574 reta_conf[idx].reta[shift + j] =
3575 ((reta >> (CHAR_BIT * j)) &
3583 #define MAC_TYPE_FILTER_SUP(type) do {\
3584 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3585 (type) != e1000_82576 && (type) != e1000_i210 &&\
3586 (type) != e1000_i211)\
3591 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3592 struct rte_eth_syn_filter *filter,
3595 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596 struct e1000_filter_info *filter_info =
3597 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3598 uint32_t synqf, rfctl;
3600 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3603 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3606 if (synqf & E1000_SYN_FILTER_ENABLE)
3609 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3610 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3612 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3613 if (filter->hig_pri)
3614 rfctl |= E1000_RFCTL_SYNQFP;
3616 rfctl &= ~E1000_RFCTL_SYNQFP;
3618 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3620 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3625 filter_info->syn_info = synqf;
3626 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3627 E1000_WRITE_FLUSH(hw);
3632 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3633 struct rte_eth_syn_filter *filter)
3635 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3636 uint32_t synqf, rfctl;
3638 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3639 if (synqf & E1000_SYN_FILTER_ENABLE) {
3640 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3641 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3642 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3643 E1000_SYN_FILTER_QUEUE_SHIFT);
3651 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3652 enum rte_filter_op filter_op,
3655 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658 MAC_TYPE_FILTER_SUP(hw->mac.type);
3660 if (filter_op == RTE_ETH_FILTER_NOP)
3664 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3669 switch (filter_op) {
3670 case RTE_ETH_FILTER_ADD:
3671 ret = eth_igb_syn_filter_set(dev,
3672 (struct rte_eth_syn_filter *)arg,
3675 case RTE_ETH_FILTER_DELETE:
3676 ret = eth_igb_syn_filter_set(dev,
3677 (struct rte_eth_syn_filter *)arg,
3680 case RTE_ETH_FILTER_GET:
3681 ret = eth_igb_syn_filter_get(dev,
3682 (struct rte_eth_syn_filter *)arg);
3685 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3693 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3694 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3695 (type) != e1000_i210 && (type) != e1000_i211)\
3699 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3701 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3702 struct e1000_2tuple_filter_info *filter_info)
3704 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3706 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3707 return -EINVAL; /* filter index is out of range. */
3708 if (filter->tcp_flags > TCP_FLAG_ALL)
3709 return -EINVAL; /* flags is invalid. */
3711 switch (filter->dst_port_mask) {
3713 filter_info->dst_port_mask = 0;
3714 filter_info->dst_port = filter->dst_port;
3717 filter_info->dst_port_mask = 1;
3720 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3724 switch (filter->proto_mask) {
3726 filter_info->proto_mask = 0;
3727 filter_info->proto = filter->proto;
3730 filter_info->proto_mask = 1;
3733 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3737 filter_info->priority = (uint8_t)filter->priority;
3738 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3739 filter_info->tcp_flags = filter->tcp_flags;
3741 filter_info->tcp_flags = 0;
3746 static inline struct e1000_2tuple_filter *
3747 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3748 struct e1000_2tuple_filter_info *key)
3750 struct e1000_2tuple_filter *it;
3752 TAILQ_FOREACH(it, filter_list, entries) {
3753 if (memcmp(key, &it->filter_info,
3754 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3761 /* inject a igb 2tuple filter to HW */
3763 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3764 struct e1000_2tuple_filter *filter)
3766 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3767 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3768 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3772 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3773 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3774 imir |= E1000_IMIR_PORT_BP;
3776 imir &= ~E1000_IMIR_PORT_BP;
3778 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3780 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3781 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3782 ttqf |= (uint32_t)(filter->filter_info.proto &
3783 E1000_TTQF_PROTOCOL_MASK);
3784 if (filter->filter_info.proto_mask == 0)
3785 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3787 /* tcp flags bits setting. */
3788 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3789 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3790 imir_ext |= E1000_IMIREXT_CTRL_URG;
3791 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3792 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3793 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3794 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3795 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3796 imir_ext |= E1000_IMIREXT_CTRL_RST;
3797 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3798 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3799 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3800 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3802 imir_ext |= E1000_IMIREXT_CTRL_BP;
3804 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3805 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3806 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3810 * igb_add_2tuple_filter - add a 2tuple filter
3813 * dev: Pointer to struct rte_eth_dev.
3814 * ntuple_filter: ponter to the filter that will be added.
3817 * - On success, zero.
3818 * - On failure, a negative value.
3821 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3822 struct rte_eth_ntuple_filter *ntuple_filter)
3824 struct e1000_filter_info *filter_info =
3825 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3826 struct e1000_2tuple_filter *filter;
3829 filter = rte_zmalloc("e1000_2tuple_filter",
3830 sizeof(struct e1000_2tuple_filter), 0);
3834 ret = ntuple_filter_to_2tuple(ntuple_filter,
3835 &filter->filter_info);
3840 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3841 &filter->filter_info) != NULL) {
3842 PMD_DRV_LOG(ERR, "filter exists.");
3846 filter->queue = ntuple_filter->queue;
3849 * look for an unused 2tuple filter index,
3850 * and insert the filter to list.
3852 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3853 if (!(filter_info->twotuple_mask & (1 << i))) {
3854 filter_info->twotuple_mask |= 1 << i;
3856 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3862 if (i >= E1000_MAX_TTQF_FILTERS) {
3863 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3868 igb_inject_2uple_filter(dev, filter);
3873 * igb_remove_2tuple_filter - remove a 2tuple filter
3876 * dev: Pointer to struct rte_eth_dev.
3877 * ntuple_filter: ponter to the filter that will be removed.
3880 * - On success, zero.
3881 * - On failure, a negative value.
3884 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3885 struct rte_eth_ntuple_filter *ntuple_filter)
3887 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888 struct e1000_filter_info *filter_info =
3889 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3890 struct e1000_2tuple_filter_info filter_2tuple;
3891 struct e1000_2tuple_filter *filter;
3894 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3895 ret = ntuple_filter_to_2tuple(ntuple_filter,
3900 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3902 if (filter == NULL) {
3903 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3907 filter_info->twotuple_mask &= ~(1 << filter->index);
3908 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3911 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3912 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3913 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3917 /* inject a igb flex filter to HW */
3919 igb_inject_flex_filter(struct rte_eth_dev *dev,
3920 struct e1000_flex_filter *filter)
3922 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3923 uint32_t wufc, queueing;
3927 wufc = E1000_READ_REG(hw, E1000_WUFC);
3928 if (filter->index < E1000_MAX_FHFT)
3929 reg_off = E1000_FHFT(filter->index);
3931 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3933 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3934 (E1000_WUFC_FLX0 << filter->index));
3935 queueing = filter->filter_info.len |
3936 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3937 (filter->filter_info.priority <<
3938 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3939 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3942 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3943 E1000_WRITE_REG(hw, reg_off,
3944 filter->filter_info.dwords[j]);
3945 reg_off += sizeof(uint32_t);
3946 E1000_WRITE_REG(hw, reg_off,
3947 filter->filter_info.dwords[++j]);
3948 reg_off += sizeof(uint32_t);
3949 E1000_WRITE_REG(hw, reg_off,
3950 (uint32_t)filter->filter_info.mask[i]);
3951 reg_off += sizeof(uint32_t) * 2;
3956 static inline struct e1000_flex_filter *
3957 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3958 struct e1000_flex_filter_info *key)
3960 struct e1000_flex_filter *it;
3962 TAILQ_FOREACH(it, filter_list, entries) {
3963 if (memcmp(key, &it->filter_info,
3964 sizeof(struct e1000_flex_filter_info)) == 0)
3971 /* remove a flex byte filter
3973 * dev: Pointer to struct rte_eth_dev.
3974 * filter: the pointer of the filter will be removed.
3977 igb_remove_flex_filter(struct rte_eth_dev *dev,
3978 struct e1000_flex_filter *filter)
3980 struct e1000_filter_info *filter_info =
3981 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3982 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3986 wufc = E1000_READ_REG(hw, E1000_WUFC);
3987 if (filter->index < E1000_MAX_FHFT)
3988 reg_off = E1000_FHFT(filter->index);
3990 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3992 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3993 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3995 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3996 (~(E1000_WUFC_FLX0 << filter->index)));
3998 filter_info->flex_mask &= ~(1 << filter->index);
3999 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4004 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4005 struct rte_eth_flex_filter *filter,
4008 struct e1000_filter_info *filter_info =
4009 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4010 struct e1000_flex_filter *flex_filter, *it;
4014 flex_filter = rte_zmalloc("e1000_flex_filter",
4015 sizeof(struct e1000_flex_filter), 0);
4016 if (flex_filter == NULL)
4019 flex_filter->filter_info.len = filter->len;
4020 flex_filter->filter_info.priority = filter->priority;
4021 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4022 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4024 /* reverse bits in flex filter's mask*/
4025 for (shift = 0; shift < CHAR_BIT; shift++) {
4026 if (filter->mask[i] & (0x01 << shift))
4027 mask |= (0x80 >> shift);
4029 flex_filter->filter_info.mask[i] = mask;
4032 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4033 &flex_filter->filter_info);
4034 if (it == NULL && !add) {
4035 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4036 rte_free(flex_filter);
4039 if (it != NULL && add) {
4040 PMD_DRV_LOG(ERR, "filter exists.");
4041 rte_free(flex_filter);
4046 flex_filter->queue = filter->queue;
4048 * look for an unused flex filter index
4049 * and insert the filter into the list.
4051 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4052 if (!(filter_info->flex_mask & (1 << i))) {
4053 filter_info->flex_mask |= 1 << i;
4054 flex_filter->index = i;
4055 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4061 if (i >= E1000_MAX_FLEX_FILTERS) {
4062 PMD_DRV_LOG(ERR, "flex filters are full.");
4063 rte_free(flex_filter);
4067 igb_inject_flex_filter(dev, flex_filter);
4070 igb_remove_flex_filter(dev, it);
4071 rte_free(flex_filter);
4078 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4079 struct rte_eth_flex_filter *filter)
4081 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4082 struct e1000_filter_info *filter_info =
4083 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4084 struct e1000_flex_filter flex_filter, *it;
4085 uint32_t wufc, queueing, wufc_en = 0;
4087 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4088 flex_filter.filter_info.len = filter->len;
4089 flex_filter.filter_info.priority = filter->priority;
4090 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4091 memcpy(flex_filter.filter_info.mask, filter->mask,
4092 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4094 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4095 &flex_filter.filter_info);
4097 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4101 wufc = E1000_READ_REG(hw, E1000_WUFC);
4102 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4104 if ((wufc & wufc_en) == wufc_en) {
4105 uint32_t reg_off = 0;
4106 if (it->index < E1000_MAX_FHFT)
4107 reg_off = E1000_FHFT(it->index);
4109 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4111 queueing = E1000_READ_REG(hw,
4112 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4113 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4114 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4115 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4116 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4117 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4124 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4125 enum rte_filter_op filter_op,
4128 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129 struct rte_eth_flex_filter *filter;
4132 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4134 if (filter_op == RTE_ETH_FILTER_NOP)
4138 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4143 filter = (struct rte_eth_flex_filter *)arg;
4144 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4145 || filter->len % sizeof(uint64_t) != 0) {
4146 PMD_DRV_LOG(ERR, "filter's length is out of range");
4149 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4150 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4154 switch (filter_op) {
4155 case RTE_ETH_FILTER_ADD:
4156 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4158 case RTE_ETH_FILTER_DELETE:
4159 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4161 case RTE_ETH_FILTER_GET:
4162 ret = eth_igb_get_flex_filter(dev, filter);
4165 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4173 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4175 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4176 struct e1000_5tuple_filter_info *filter_info)
4178 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4180 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4181 return -EINVAL; /* filter index is out of range. */
4182 if (filter->tcp_flags > TCP_FLAG_ALL)
4183 return -EINVAL; /* flags is invalid. */
4185 switch (filter->dst_ip_mask) {
4187 filter_info->dst_ip_mask = 0;
4188 filter_info->dst_ip = filter->dst_ip;
4191 filter_info->dst_ip_mask = 1;
4194 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4198 switch (filter->src_ip_mask) {
4200 filter_info->src_ip_mask = 0;
4201 filter_info->src_ip = filter->src_ip;
4204 filter_info->src_ip_mask = 1;
4207 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4211 switch (filter->dst_port_mask) {
4213 filter_info->dst_port_mask = 0;
4214 filter_info->dst_port = filter->dst_port;
4217 filter_info->dst_port_mask = 1;
4220 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4224 switch (filter->src_port_mask) {
4226 filter_info->src_port_mask = 0;
4227 filter_info->src_port = filter->src_port;
4230 filter_info->src_port_mask = 1;
4233 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4237 switch (filter->proto_mask) {
4239 filter_info->proto_mask = 0;
4240 filter_info->proto = filter->proto;
4243 filter_info->proto_mask = 1;
4246 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4250 filter_info->priority = (uint8_t)filter->priority;
4251 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4252 filter_info->tcp_flags = filter->tcp_flags;
4254 filter_info->tcp_flags = 0;
4259 static inline struct e1000_5tuple_filter *
4260 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4261 struct e1000_5tuple_filter_info *key)
4263 struct e1000_5tuple_filter *it;
4265 TAILQ_FOREACH(it, filter_list, entries) {
4266 if (memcmp(key, &it->filter_info,
4267 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4274 /* inject a igb 5-tuple filter to HW */
4276 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4277 struct e1000_5tuple_filter *filter)
4279 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4280 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4281 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4285 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4286 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4287 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4288 if (filter->filter_info.dst_ip_mask == 0)
4289 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4290 if (filter->filter_info.src_port_mask == 0)
4291 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4292 if (filter->filter_info.proto_mask == 0)
4293 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4294 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4295 E1000_FTQF_QUEUE_MASK;
4296 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4297 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4298 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4299 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4301 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4302 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4304 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4305 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4306 imir |= E1000_IMIR_PORT_BP;
4308 imir &= ~E1000_IMIR_PORT_BP;
4309 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4311 /* tcp flags bits setting. */
4312 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4313 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4314 imir_ext |= E1000_IMIREXT_CTRL_URG;
4315 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4316 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4317 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4318 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4319 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4320 imir_ext |= E1000_IMIREXT_CTRL_RST;
4321 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4322 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4323 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4324 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4326 imir_ext |= E1000_IMIREXT_CTRL_BP;
4328 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4329 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4333 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4336 * dev: Pointer to struct rte_eth_dev.
4337 * ntuple_filter: ponter to the filter that will be added.
4340 * - On success, zero.
4341 * - On failure, a negative value.
4344 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4345 struct rte_eth_ntuple_filter *ntuple_filter)
4347 struct e1000_filter_info *filter_info =
4348 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4349 struct e1000_5tuple_filter *filter;
4353 filter = rte_zmalloc("e1000_5tuple_filter",
4354 sizeof(struct e1000_5tuple_filter), 0);
4358 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4359 &filter->filter_info);
4365 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4366 &filter->filter_info) != NULL) {
4367 PMD_DRV_LOG(ERR, "filter exists.");
4371 filter->queue = ntuple_filter->queue;
4374 * look for an unused 5tuple filter index,
4375 * and insert the filter to list.
4377 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4378 if (!(filter_info->fivetuple_mask & (1 << i))) {
4379 filter_info->fivetuple_mask |= 1 << i;
4381 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4387 if (i >= E1000_MAX_FTQF_FILTERS) {
4388 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4393 igb_inject_5tuple_filter_82576(dev, filter);
4398 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4401 * dev: Pointer to struct rte_eth_dev.
4402 * ntuple_filter: ponter to the filter that will be removed.
4405 * - On success, zero.
4406 * - On failure, a negative value.
4409 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4410 struct rte_eth_ntuple_filter *ntuple_filter)
4412 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4413 struct e1000_filter_info *filter_info =
4414 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4415 struct e1000_5tuple_filter_info filter_5tuple;
4416 struct e1000_5tuple_filter *filter;
4419 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4420 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4425 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4427 if (filter == NULL) {
4428 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4432 filter_info->fivetuple_mask &= ~(1 << filter->index);
4433 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4436 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4437 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4438 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4439 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4440 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4441 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4442 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4447 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4450 struct e1000_hw *hw;
4451 struct rte_eth_dev_info dev_info;
4452 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4455 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4457 #ifdef RTE_LIBRTE_82571_SUPPORT
4458 /* XXX: not bigger than max_rx_pktlen */
4459 if (hw->mac.type == e1000_82571)
4462 eth_igb_infos_get(dev, &dev_info);
4464 /* check that mtu is within the allowed range */
4465 if ((mtu < ETHER_MIN_MTU) ||
4466 (frame_size > dev_info.max_rx_pktlen))
4469 /* refuse mtu that requires the support of scattered packets when this
4470 * feature has not been enabled before. */
4471 if (!dev->data->scattered_rx &&
4472 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4475 rctl = E1000_READ_REG(hw, E1000_RCTL);
4477 /* switch to jumbo mode if needed */
4478 if (frame_size > ETHER_MAX_LEN) {
4479 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4480 rctl |= E1000_RCTL_LPE;
4482 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4483 rctl &= ~E1000_RCTL_LPE;
4485 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4487 /* update max frame size */
4488 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4490 E1000_WRITE_REG(hw, E1000_RLPML,
4491 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4497 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4500 * dev: Pointer to struct rte_eth_dev.
4501 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4502 * add: if true, add filter, if false, remove filter
4505 * - On success, zero.
4506 * - On failure, a negative value.
4509 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4510 struct rte_eth_ntuple_filter *ntuple_filter,
4513 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4516 switch (ntuple_filter->flags) {
4517 case RTE_5TUPLE_FLAGS:
4518 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4519 if (hw->mac.type != e1000_82576)
4522 ret = igb_add_5tuple_filter_82576(dev,
4525 ret = igb_remove_5tuple_filter_82576(dev,
4528 case RTE_2TUPLE_FLAGS:
4529 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4530 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4531 hw->mac.type != e1000_i210 &&
4532 hw->mac.type != e1000_i211)
4535 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4537 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4548 * igb_get_ntuple_filter - get a ntuple filter
4551 * dev: Pointer to struct rte_eth_dev.
4552 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4555 * - On success, zero.
4556 * - On failure, a negative value.
4559 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4560 struct rte_eth_ntuple_filter *ntuple_filter)
4562 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4563 struct e1000_filter_info *filter_info =
4564 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4565 struct e1000_5tuple_filter_info filter_5tuple;
4566 struct e1000_2tuple_filter_info filter_2tuple;
4567 struct e1000_5tuple_filter *p_5tuple_filter;
4568 struct e1000_2tuple_filter *p_2tuple_filter;
4571 switch (ntuple_filter->flags) {
4572 case RTE_5TUPLE_FLAGS:
4573 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4574 if (hw->mac.type != e1000_82576)
4576 memset(&filter_5tuple,
4578 sizeof(struct e1000_5tuple_filter_info));
4579 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4583 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4584 &filter_info->fivetuple_list,
4586 if (p_5tuple_filter == NULL) {
4587 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4590 ntuple_filter->queue = p_5tuple_filter->queue;
4592 case RTE_2TUPLE_FLAGS:
4593 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4594 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4596 memset(&filter_2tuple,
4598 sizeof(struct e1000_2tuple_filter_info));
4599 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4602 p_2tuple_filter = igb_2tuple_filter_lookup(
4603 &filter_info->twotuple_list,
4605 if (p_2tuple_filter == NULL) {
4606 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4609 ntuple_filter->queue = p_2tuple_filter->queue;
4620 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4621 * @dev: pointer to rte_eth_dev structure
4622 * @filter_op:operation will be taken.
4623 * @arg: a pointer to specific structure corresponding to the filter_op
4626 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4627 enum rte_filter_op filter_op,
4630 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4633 MAC_TYPE_FILTER_SUP(hw->mac.type);
4635 if (filter_op == RTE_ETH_FILTER_NOP)
4639 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4644 switch (filter_op) {
4645 case RTE_ETH_FILTER_ADD:
4646 ret = igb_add_del_ntuple_filter(dev,
4647 (struct rte_eth_ntuple_filter *)arg,
4650 case RTE_ETH_FILTER_DELETE:
4651 ret = igb_add_del_ntuple_filter(dev,
4652 (struct rte_eth_ntuple_filter *)arg,
4655 case RTE_ETH_FILTER_GET:
4656 ret = igb_get_ntuple_filter(dev,
4657 (struct rte_eth_ntuple_filter *)arg);
4660 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4668 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4673 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4674 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4675 (filter_info->ethertype_mask & (1 << i)))
4682 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4683 uint16_t ethertype, uint32_t etqf)
4687 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4688 if (!(filter_info->ethertype_mask & (1 << i))) {
4689 filter_info->ethertype_mask |= 1 << i;
4690 filter_info->ethertype_filters[i].ethertype = ethertype;
4691 filter_info->ethertype_filters[i].etqf = etqf;
4699 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4702 if (idx >= E1000_MAX_ETQF_FILTERS)
4704 filter_info->ethertype_mask &= ~(1 << idx);
4705 filter_info->ethertype_filters[idx].ethertype = 0;
4706 filter_info->ethertype_filters[idx].etqf = 0;
4712 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4713 struct rte_eth_ethertype_filter *filter,
4716 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4717 struct e1000_filter_info *filter_info =
4718 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4722 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4723 filter->ether_type == ETHER_TYPE_IPv6) {
4724 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4725 " ethertype filter.", filter->ether_type);
4729 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4730 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4733 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4734 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4738 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4739 if (ret >= 0 && add) {
4740 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4741 filter->ether_type);
4744 if (ret < 0 && !add) {
4745 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4746 filter->ether_type);
4751 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4752 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4753 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4754 ret = igb_ethertype_filter_insert(filter_info,
4755 filter->ether_type, etqf);
4757 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4761 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4765 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4766 E1000_WRITE_FLUSH(hw);
4772 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4773 struct rte_eth_ethertype_filter *filter)
4775 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4776 struct e1000_filter_info *filter_info =
4777 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4781 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4783 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4784 filter->ether_type);
4788 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4789 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4790 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4792 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4793 E1000_ETQF_QUEUE_SHIFT;
4801 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4802 * @dev: pointer to rte_eth_dev structure
4803 * @filter_op:operation will be taken.
4804 * @arg: a pointer to specific structure corresponding to the filter_op
4807 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4808 enum rte_filter_op filter_op,
4811 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814 MAC_TYPE_FILTER_SUP(hw->mac.type);
4816 if (filter_op == RTE_ETH_FILTER_NOP)
4820 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4825 switch (filter_op) {
4826 case RTE_ETH_FILTER_ADD:
4827 ret = igb_add_del_ethertype_filter(dev,
4828 (struct rte_eth_ethertype_filter *)arg,
4831 case RTE_ETH_FILTER_DELETE:
4832 ret = igb_add_del_ethertype_filter(dev,
4833 (struct rte_eth_ethertype_filter *)arg,
4836 case RTE_ETH_FILTER_GET:
4837 ret = igb_get_ethertype_filter(dev,
4838 (struct rte_eth_ethertype_filter *)arg);
4841 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4849 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4850 enum rte_filter_type filter_type,
4851 enum rte_filter_op filter_op,
4856 switch (filter_type) {
4857 case RTE_ETH_FILTER_NTUPLE:
4858 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4860 case RTE_ETH_FILTER_ETHERTYPE:
4861 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4863 case RTE_ETH_FILTER_SYN:
4864 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4866 case RTE_ETH_FILTER_FLEXIBLE:
4867 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4870 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4879 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4880 struct ether_addr *mc_addr_set,
4881 uint32_t nb_mc_addr)
4883 struct e1000_hw *hw;
4885 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4891 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4893 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4894 uint64_t systime_cycles;
4896 switch (hw->mac.type) {
4900 * Need to read System Time Residue Register to be able
4901 * to read the other two registers.
4903 E1000_READ_REG(hw, E1000_SYSTIMR);
4904 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4905 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4906 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4913 * Need to read System Time Residue Register to be able
4914 * to read the other two registers.
4916 E1000_READ_REG(hw, E1000_SYSTIMR);
4917 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4918 /* Only the 8 LSB are valid. */
4919 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4923 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4924 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4929 return systime_cycles;
4933 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4935 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4936 uint64_t rx_tstamp_cycles;
4938 switch (hw->mac.type) {
4941 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4942 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4943 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4949 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4950 /* Only the 8 LSB are valid. */
4951 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4955 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4956 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4961 return rx_tstamp_cycles;
4965 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4967 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968 uint64_t tx_tstamp_cycles;
4970 switch (hw->mac.type) {
4973 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4974 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4975 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4981 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4982 /* Only the 8 LSB are valid. */
4983 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4987 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4988 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4993 return tx_tstamp_cycles;
4997 igb_start_timecounters(struct rte_eth_dev *dev)
4999 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000 struct e1000_adapter *adapter =
5001 (struct e1000_adapter *)dev->data->dev_private;
5002 uint32_t incval = 1;
5004 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5006 switch (hw->mac.type) {
5010 /* 32 LSB bits + 8 MSB bits = 40 bits */
5011 mask = (1ULL << 40) - 1;
5016 * Start incrementing the register
5017 * used to timestamp PTP packets.
5019 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5022 incval = E1000_INCVALUE_82576;
5023 shift = IGB_82576_TSYNC_SHIFT;
5024 E1000_WRITE_REG(hw, E1000_TIMINCA,
5025 E1000_INCPERIOD_82576 | incval);
5032 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5033 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5034 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5036 adapter->systime_tc.cc_mask = mask;
5037 adapter->systime_tc.cc_shift = shift;
5038 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5040 adapter->rx_tstamp_tc.cc_mask = mask;
5041 adapter->rx_tstamp_tc.cc_shift = shift;
5042 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5044 adapter->tx_tstamp_tc.cc_mask = mask;
5045 adapter->tx_tstamp_tc.cc_shift = shift;
5046 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5050 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5052 struct e1000_adapter *adapter =
5053 (struct e1000_adapter *)dev->data->dev_private;
5055 adapter->systime_tc.nsec += delta;
5056 adapter->rx_tstamp_tc.nsec += delta;
5057 adapter->tx_tstamp_tc.nsec += delta;
5063 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5066 struct e1000_adapter *adapter =
5067 (struct e1000_adapter *)dev->data->dev_private;
5069 ns = rte_timespec_to_ns(ts);
5071 /* Set the timecounters to a new value. */
5072 adapter->systime_tc.nsec = ns;
5073 adapter->rx_tstamp_tc.nsec = ns;
5074 adapter->tx_tstamp_tc.nsec = ns;
5080 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5082 uint64_t ns, systime_cycles;
5083 struct e1000_adapter *adapter =
5084 (struct e1000_adapter *)dev->data->dev_private;
5086 systime_cycles = igb_read_systime_cyclecounter(dev);
5087 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5088 *ts = rte_ns_to_timespec(ns);
5094 igb_timesync_enable(struct rte_eth_dev *dev)
5096 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5100 /* Stop the timesync system time. */
5101 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5102 /* Reset the timesync system time value. */
5103 switch (hw->mac.type) {
5109 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5112 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5113 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5116 /* Not supported. */
5120 /* Enable system time for it isn't on by default. */
5121 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5122 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5123 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5125 igb_start_timecounters(dev);
5127 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5128 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5130 E1000_ETQF_FILTER_ENABLE |
5133 /* Enable timestamping of received PTP packets. */
5134 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5135 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5136 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5138 /* Enable Timestamping of transmitted PTP packets. */
5139 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5140 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5141 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5147 igb_timesync_disable(struct rte_eth_dev *dev)
5149 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5152 /* Disable timestamping of transmitted PTP packets. */
5153 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5154 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5155 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5157 /* Disable timestamping of received PTP packets. */
5158 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5159 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5160 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5162 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5163 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5165 /* Stop incrementating the System Time registers. */
5166 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5172 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5173 struct timespec *timestamp,
5174 uint32_t flags __rte_unused)
5176 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5177 struct e1000_adapter *adapter =
5178 (struct e1000_adapter *)dev->data->dev_private;
5179 uint32_t tsync_rxctl;
5180 uint64_t rx_tstamp_cycles;
5183 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5184 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5187 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5188 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5189 *timestamp = rte_ns_to_timespec(ns);
5195 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5196 struct timespec *timestamp)
5198 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5199 struct e1000_adapter *adapter =
5200 (struct e1000_adapter *)dev->data->dev_private;
5201 uint32_t tsync_txctl;
5202 uint64_t tx_tstamp_cycles;
5205 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5206 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5209 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5210 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5211 *timestamp = rte_ns_to_timespec(ns);
5217 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5221 const struct reg_info *reg_group;
5223 while ((reg_group = igb_regs[g_ind++]))
5224 count += igb_reg_group_count(reg_group);
5230 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5234 const struct reg_info *reg_group;
5236 while ((reg_group = igbvf_regs[g_ind++]))
5237 count += igb_reg_group_count(reg_group);
5243 eth_igb_get_regs(struct rte_eth_dev *dev,
5244 struct rte_dev_reg_info *regs)
5246 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5247 uint32_t *data = regs->data;
5250 const struct reg_info *reg_group;
5253 regs->length = eth_igb_get_reg_length(dev);
5254 regs->width = sizeof(uint32_t);
5258 /* Support only full register dump */
5259 if ((regs->length == 0) ||
5260 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5261 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5263 while ((reg_group = igb_regs[g_ind++]))
5264 count += igb_read_regs_group(dev, &data[count],
5273 igbvf_get_regs(struct rte_eth_dev *dev,
5274 struct rte_dev_reg_info *regs)
5276 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5277 uint32_t *data = regs->data;
5280 const struct reg_info *reg_group;
5283 regs->length = igbvf_get_reg_length(dev);
5284 regs->width = sizeof(uint32_t);
5288 /* Support only full register dump */
5289 if ((regs->length == 0) ||
5290 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5291 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5293 while ((reg_group = igbvf_regs[g_ind++]))
5294 count += igb_read_regs_group(dev, &data[count],
5303 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5305 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5307 /* Return unit is byte count */
5308 return hw->nvm.word_size * 2;
5312 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5313 struct rte_dev_eeprom_info *in_eeprom)
5315 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5316 struct e1000_nvm_info *nvm = &hw->nvm;
5317 uint16_t *data = in_eeprom->data;
5320 first = in_eeprom->offset >> 1;
5321 length = in_eeprom->length >> 1;
5322 if ((first >= hw->nvm.word_size) ||
5323 ((first + length) >= hw->nvm.word_size))
5326 in_eeprom->magic = hw->vendor_id |
5327 ((uint32_t)hw->device_id << 16);
5329 if ((nvm->ops.read) == NULL)
5332 return nvm->ops.read(hw, first, length, data);
5336 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5337 struct rte_dev_eeprom_info *in_eeprom)
5339 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5340 struct e1000_nvm_info *nvm = &hw->nvm;
5341 uint16_t *data = in_eeprom->data;
5344 first = in_eeprom->offset >> 1;
5345 length = in_eeprom->length >> 1;
5346 if ((first >= hw->nvm.word_size) ||
5347 ((first + length) >= hw->nvm.word_size))
5350 in_eeprom->magic = (uint32_t)hw->vendor_id |
5351 ((uint32_t)hw->device_id << 16);
5353 if ((nvm->ops.write) == NULL)
5355 return nvm->ops.write(hw, first, length, data);
5359 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5361 struct e1000_hw *hw =
5362 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5363 uint32_t mask = 1 << queue_id;
5365 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5366 E1000_WRITE_FLUSH(hw);
5372 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5374 struct e1000_hw *hw =
5375 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5376 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5377 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5378 uint32_t mask = 1 << queue_id;
5381 regval = E1000_READ_REG(hw, E1000_EIMS);
5382 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5383 E1000_WRITE_FLUSH(hw);
5385 rte_intr_enable(intr_handle);
5391 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5392 uint8_t index, uint8_t offset)
5394 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5397 val &= ~((uint32_t)0xFF << offset);
5399 /* write vector and valid bit */
5400 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5402 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5406 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5407 uint8_t queue, uint8_t msix_vector)
5411 if (hw->mac.type == e1000_82575) {
5413 tmp = E1000_EICR_RX_QUEUE0 << queue;
5414 else if (direction == 1)
5415 tmp = E1000_EICR_TX_QUEUE0 << queue;
5416 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5417 } else if (hw->mac.type == e1000_82576) {
5418 if ((direction == 0) || (direction == 1))
5419 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5420 ((queue & 0x8) << 1) +
5422 } else if ((hw->mac.type == e1000_82580) ||
5423 (hw->mac.type == e1000_i350) ||
5424 (hw->mac.type == e1000_i354) ||
5425 (hw->mac.type == e1000_i210) ||
5426 (hw->mac.type == e1000_i211)) {
5427 if ((direction == 0) || (direction == 1))
5428 eth_igb_write_ivar(hw, msix_vector,
5430 ((queue & 0x1) << 4) +
5435 /* Sets up the hardware to generate MSI-X interrupts properly
5437 * board private structure
5440 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5443 uint32_t tmpval, regval, intr_mask;
5444 struct e1000_hw *hw =
5445 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5446 uint32_t vec = E1000_MISC_VEC_ID;
5447 uint32_t base = E1000_MISC_VEC_ID;
5448 uint32_t misc_shift = 0;
5449 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5450 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5452 /* won't configure msix register if no mapping is done
5453 * between intr vector and event fd
5455 if (!rte_intr_dp_is_en(intr_handle))
5458 if (rte_intr_allow_others(intr_handle)) {
5459 vec = base = E1000_RX_VEC_START;
5463 /* set interrupt vector for other causes */
5464 if (hw->mac.type == e1000_82575) {
5465 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5466 /* enable MSI-X PBA support */
5467 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5469 /* Auto-Mask interrupts upon ICR read */
5470 tmpval |= E1000_CTRL_EXT_EIAME;
5471 tmpval |= E1000_CTRL_EXT_IRCA;
5473 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5475 /* enable msix_other interrupt */
5476 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5477 regval = E1000_READ_REG(hw, E1000_EIAC);
5478 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5479 regval = E1000_READ_REG(hw, E1000_EIAM);
5480 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5481 } else if ((hw->mac.type == e1000_82576) ||
5482 (hw->mac.type == e1000_82580) ||
5483 (hw->mac.type == e1000_i350) ||
5484 (hw->mac.type == e1000_i354) ||
5485 (hw->mac.type == e1000_i210) ||
5486 (hw->mac.type == e1000_i211)) {
5487 /* turn on MSI-X capability first */
5488 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5489 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5491 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5493 regval = E1000_READ_REG(hw, E1000_EIAC);
5494 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5496 /* enable msix_other interrupt */
5497 regval = E1000_READ_REG(hw, E1000_EIMS);
5498 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5499 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5500 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5503 /* use EIAM to auto-mask when MSI-X interrupt
5504 * is asserted, this saves a register write for every interrupt
5506 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5508 regval = E1000_READ_REG(hw, E1000_EIAM);
5509 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5511 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5512 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5513 intr_handle->intr_vec[queue_id] = vec;
5514 if (vec < base + intr_handle->nb_efd - 1)
5518 E1000_WRITE_FLUSH(hw);
5521 /* restore n-tuple filter */
5523 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5525 struct e1000_filter_info *filter_info =
5526 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5527 struct e1000_5tuple_filter *p_5tuple;
5528 struct e1000_2tuple_filter *p_2tuple;
5530 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5531 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5534 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5535 igb_inject_2uple_filter(dev, p_2tuple);
5539 /* restore SYN filter */
5541 igb_syn_filter_restore(struct rte_eth_dev *dev)
5543 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544 struct e1000_filter_info *filter_info =
5545 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5548 synqf = filter_info->syn_info;
5550 if (synqf & E1000_SYN_FILTER_ENABLE) {
5551 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5552 E1000_WRITE_FLUSH(hw);
5556 /* restore ethernet type filter */
5558 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5560 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5561 struct e1000_filter_info *filter_info =
5562 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5565 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5566 if (filter_info->ethertype_mask & (1 << i)) {
5567 E1000_WRITE_REG(hw, E1000_ETQF(i),
5568 filter_info->ethertype_filters[i].etqf);
5569 E1000_WRITE_FLUSH(hw);
5574 /* restore flex byte filter */
5576 igb_flex_filter_restore(struct rte_eth_dev *dev)
5578 struct e1000_filter_info *filter_info =
5579 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5580 struct e1000_flex_filter *flex_filter;
5582 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5583 igb_inject_flex_filter(dev, flex_filter);
5587 /* restore all types filter */
5589 igb_filter_restore(struct rte_eth_dev *dev)
5591 igb_ntuple_filter_restore(dev);
5592 igb_ethertype_filter_restore(dev);
5593 igb_syn_filter_restore(dev);
5594 igb_flex_filter_restore(dev);
5599 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5600 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5601 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5602 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5603 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5604 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");