drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 137                                                         void *param);
 138 static int  igb_hardware_init(struct e1000_hw *hw);
 139 static void igb_hw_control_acquire(struct e1000_hw *hw);
 140 static void igb_hw_control_release(struct e1000_hw *hw);
 141 static void igb_init_manageability(struct e1000_hw *hw);
 142 static void igb_release_manageability(struct e1000_hw *hw);
 143
 144 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 145
 146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 147                 uint16_t vlan_id, int on);
 148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 149                                  enum rte_vlan_type vlan_type,
 150                                  uint16_t tpid_id);
 151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 152
 153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int eth_igb_led_on(struct rte_eth_dev *dev);
 161 static int eth_igb_led_off(struct rte_eth_dev *dev);
 162
 163 static void igb_intr_disable(struct e1000_hw *hw);
 164 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 166                 struct ether_addr *mac_addr,
 167                 uint32_t index, uint32_t pool);
 168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 170                 struct ether_addr *addr);
 171
 172 static void igbvf_intr_disable(struct e1000_hw *hw);
 173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 174 static int igbvf_dev_start(struct rte_eth_dev *dev);
 175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 176 static void igbvf_dev_close(struct rte_eth_dev *dev);
 177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int eth_igbvf_link_update(struct e1000_hw *hw);
 182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_stats *rte_stats);
 184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 185                                 struct rte_eth_xstat *xstats, unsigned n);
 186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 187                                       struct rte_eth_xstat_name *xstats_names,
 188                                       unsigned limit);
 189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 191                 uint16_t vlan_id, int on);
 192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 195                 struct ether_addr *addr);
 196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 197 static int igbvf_get_regs(struct rte_eth_dev *dev,
 198                 struct rte_dev_reg_info *regs);
 199
 200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 201                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 202                                    uint16_t reta_size);
 203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 204                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 205                                   uint16_t reta_size);
 206
 207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 208                         struct rte_eth_syn_filter *filter,
 209                         bool add);
 210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 211                         struct rte_eth_syn_filter *filter);
 212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 213                         enum rte_filter_op filter_op,
 214                         void *arg);
 215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ntuple_filter *ntuple_filter);
 217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 218                         struct rte_eth_ntuple_filter *ntuple_filter);
 219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 220                         struct rte_eth_flex_filter *filter,
 221                         bool add);
 222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_flex_filter *filter);
 224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 225                         enum rte_filter_op filter_op,
 226                         void *arg);
 227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 228                         struct rte_eth_ntuple_filter *ntuple_filter);
 229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 230                         struct rte_eth_ntuple_filter *ntuple_filter);
 231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_ntuple_filter *filter,
 233                         bool add);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 240                         struct rte_eth_ethertype_filter *filter,
 241                         bool add);
 242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 243                                 enum rte_filter_op filter_op,
 244                                 void *arg);
 245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 246                         struct rte_eth_ethertype_filter *filter);
 247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 248                      enum rte_filter_type filter_type,
 249                      enum rte_filter_op filter_op,
 250                      void *arg);
 251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 253                 struct rte_dev_reg_info *regs);
 254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 256                 struct rte_dev_eeprom_info *eeprom);
 257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 258                 struct rte_dev_eeprom_info *eeprom);
 259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 260                                     struct ether_addr *mc_addr_set,
 261                                     uint32_t nb_mc_addr);
 262 static int igb_timesync_enable(struct rte_eth_dev *dev);
 263 static int igb_timesync_disable(struct rte_eth_dev *dev);
 264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp,
 266                                           uint32_t flags);
 267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 268                                           struct timespec *timestamp);
 269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 271                                   struct timespec *timestamp);
 272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 273                                    const struct timespec *timestamp);
 274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                         uint16_t queue_id);
 276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                          uint16_t queue_id);
 278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 279                                        uint8_t queue, uint8_t msix_vector);
 280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 281                                uint8_t index, uint8_t offset);
 282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 284                                         void *param);
 285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 286
 287 /*
 288  * Define VF Stats MACRO for Non "cleared on read" register
 289  */
 290 #define UPDATE_VF_STAT(reg, last, cur)            \
 291 {                                                 \
 292         u32 latest = E1000_READ_REG(hw, reg);     \
 293         cur += (latest - last) & UINT_MAX;        \
 294         last = latest;                            \
 295 }
 296
 297 #define IGB_FC_PAUSE_TIME 0x0680
 298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 300
 301 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 302
 303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 304
 305 /*
 306  * The set of PCI devices this driver supports
 307  */
 308 static const struct rte_pci_id pci_id_igb_map[] = {
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 317
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 321
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 328
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 348         { .vendor_id = 0, /* sentinel */ },
 349 };
 350
 351 /*
 352  * The set of PCI devices this driver supports (for 82576&I350 VF)
 353  */
 354 static const struct rte_pci_id pci_id_igbvf_map[] = {
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 359         { .vendor_id = 0, /* sentinel */ },
 360 };
 361
 362 static const struct rte_eth_desc_lim rx_desc_lim = {
 363         .nb_max = E1000_MAX_RING_DESC,
 364         .nb_min = E1000_MIN_RING_DESC,
 365         .nb_align = IGB_RXD_ALIGN,
 366 };
 367
 368 static const struct rte_eth_desc_lim tx_desc_lim = {
 369         .nb_max = E1000_MAX_RING_DESC,
 370         .nb_min = E1000_MIN_RING_DESC,
 371         .nb_align = IGB_RXD_ALIGN,
 372 };
 373
 374 static const struct eth_dev_ops eth_igb_ops = {
 375         .dev_configure        = eth_igb_configure,
 376         .dev_start            = eth_igb_start,
 377         .dev_stop             = eth_igb_stop,
 378         .dev_set_link_up      = eth_igb_dev_set_link_up,
 379         .dev_set_link_down    = eth_igb_dev_set_link_down,
 380         .dev_close            = eth_igb_close,
 381         .promiscuous_enable   = eth_igb_promiscuous_enable,
 382         .promiscuous_disable  = eth_igb_promiscuous_disable,
 383         .allmulticast_enable  = eth_igb_allmulticast_enable,
 384         .allmulticast_disable = eth_igb_allmulticast_disable,
 385         .link_update          = eth_igb_link_update,
 386         .stats_get            = eth_igb_stats_get,
 387         .xstats_get           = eth_igb_xstats_get,
 388         .xstats_get_names     = eth_igb_xstats_get_names,
 389         .stats_reset          = eth_igb_stats_reset,
 390         .xstats_reset         = eth_igb_xstats_reset,
 391         .dev_infos_get        = eth_igb_infos_get,
 392         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 393         .mtu_set              = eth_igb_mtu_set,
 394         .vlan_filter_set      = eth_igb_vlan_filter_set,
 395         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 396         .vlan_offload_set     = eth_igb_vlan_offload_set,
 397         .rx_queue_setup       = eth_igb_rx_queue_setup,
 398         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 399         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 400         .rx_queue_release     = eth_igb_rx_queue_release,
 401         .rx_queue_count       = eth_igb_rx_queue_count,
 402         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 403         .tx_queue_setup       = eth_igb_tx_queue_setup,
 404         .tx_queue_release     = eth_igb_tx_queue_release,
 405         .dev_led_on           = eth_igb_led_on,
 406         .dev_led_off          = eth_igb_led_off,
 407         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 408         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 409         .mac_addr_add         = eth_igb_rar_set,
 410         .mac_addr_remove      = eth_igb_rar_clear,
 411         .mac_addr_set         = eth_igb_default_mac_addr_set,
 412         .reta_update          = eth_igb_rss_reta_update,
 413         .reta_query           = eth_igb_rss_reta_query,
 414         .rss_hash_update      = eth_igb_rss_hash_update,
 415         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 416         .filter_ctrl          = eth_igb_filter_ctrl,
 417         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 418         .rxq_info_get         = igb_rxq_info_get,
 419         .txq_info_get         = igb_txq_info_get,
 420         .timesync_enable      = igb_timesync_enable,
 421         .timesync_disable     = igb_timesync_disable,
 422         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 423         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 424         .get_reg              = eth_igb_get_regs,
 425         .get_eeprom_length    = eth_igb_get_eeprom_length,
 426         .get_eeprom           = eth_igb_get_eeprom,
 427         .set_eeprom           = eth_igb_set_eeprom,
 428         .timesync_adjust_time = igb_timesync_adjust_time,
 429         .timesync_read_time   = igb_timesync_read_time,
 430         .timesync_write_time  = igb_timesync_write_time,
 431 };
 432
 433 /*
 434  * dev_ops for virtual function, bare necessities for basic vf
 435  * operation have been implemented
 436  */
 437 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 438         .dev_configure        = igbvf_dev_configure,
 439         .dev_start            = igbvf_dev_start,
 440         .dev_stop             = igbvf_dev_stop,
 441         .dev_close            = igbvf_dev_close,
 442         .promiscuous_enable   = igbvf_promiscuous_enable,
 443         .promiscuous_disable  = igbvf_promiscuous_disable,
 444         .allmulticast_enable  = igbvf_allmulticast_enable,
 445         .allmulticast_disable = igbvf_allmulticast_disable,
 446         .link_update          = eth_igb_link_update,
 447         .stats_get            = eth_igbvf_stats_get,
 448         .xstats_get           = eth_igbvf_xstats_get,
 449         .xstats_get_names     = eth_igbvf_xstats_get_names,
 450         .stats_reset          = eth_igbvf_stats_reset,
 451         .xstats_reset         = eth_igbvf_stats_reset,
 452         .vlan_filter_set      = igbvf_vlan_filter_set,
 453         .dev_infos_get        = eth_igbvf_infos_get,
 454         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 455         .rx_queue_setup       = eth_igb_rx_queue_setup,
 456         .rx_queue_release     = eth_igb_rx_queue_release,
 457         .tx_queue_setup       = eth_igb_tx_queue_setup,
 458         .tx_queue_release     = eth_igb_tx_queue_release,
 459         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 460         .rxq_info_get         = igb_rxq_info_get,
 461         .txq_info_get         = igb_txq_info_get,
 462         .mac_addr_set         = igbvf_default_mac_addr_set,
 463         .get_reg              = igbvf_get_regs,
 464 };
 465
 466 /* store statistics names and its offset in stats structure */
 467 struct rte_igb_xstats_name_off {
 468         char name[RTE_ETH_XSTATS_NAME_SIZE];
 469         unsigned offset;
 470 };
 471
 472 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 473         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 474         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 475         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 476         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 477         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 478         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 479         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 480                 ecol)},
 481         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 482         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 483         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 484         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 485         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 486         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 487         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 488         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 489         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 490         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 491         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 492                 fcruc)},
 493         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 494         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 495         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 496         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 497         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 498                 prc1023)},
 499         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 500                 prc1522)},
 501         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 502         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 503         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 504         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 505         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 506         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 507         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 508         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 509         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 510         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 511         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 512         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 513         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 514         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 515         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 516         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 517         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 518         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 519                 ptc1023)},
 520         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 521                 ptc1522)},
 522         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 523         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 524         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 525         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 526         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 527         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 528         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 529
 530         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 531 };
 532
 533 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 534                 sizeof(rte_igb_stats_strings[0]))
 535
 536 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 537         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 538         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 539         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 540         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 541         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 542 };
 543
 544 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 545                 sizeof(rte_igbvf_stats_strings[0]))
 546
 547 /**
 548  * Atomically reads the link status information from global
 549  * structure rte_eth_dev.
 550  *
 551  * @param dev
 552  *   - Pointer to the structure rte_eth_dev to read from.
 553  *   - Pointer to the buffer to be saved with the link status.
 554  *
 555  * @return
 556  *   - On success, zero.
 557  *   - On failure, negative value.
 558  */
 559 static inline int
 560 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 561                                 struct rte_eth_link *link)
 562 {
 563         struct rte_eth_link *dst = link;
 564         struct rte_eth_link *src = &(dev->data->dev_link);
 565
 566         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 567                                         *(uint64_t *)src) == 0)
 568                 return -1;
 569
 570         return 0;
 571 }
 572
 573 /**
 574  * Atomically writes the link status information into global
 575  * structure rte_eth_dev.
 576  *
 577  * @param dev
 578  *   - Pointer to the structure rte_eth_dev to read from.
 579  *   - Pointer to the buffer to be saved with the link status.
 580  *
 581  * @return
 582  *   - On success, zero.
 583  *   - On failure, negative value.
 584  */
 585 static inline int
 586 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 587                                 struct rte_eth_link *link)
 588 {
 589         struct rte_eth_link *dst = &(dev->data->dev_link);
 590         struct rte_eth_link *src = link;
 591
 592         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 593                                         *(uint64_t *)src) == 0)
 594                 return -1;
 595
 596         return 0;
 597 }
 598
 599 static inline void
 600 igb_intr_enable(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_interrupt *intr =
 603                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 604         struct e1000_hw *hw =
 605                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 606
 607         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 608         E1000_WRITE_FLUSH(hw);
 609 }
 610
 611 static void
 612 igb_intr_disable(struct e1000_hw *hw)
 613 {
 614         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 615         E1000_WRITE_FLUSH(hw);
 616 }
 617
 618 static inline void
 619 igbvf_intr_enable(struct rte_eth_dev *dev)
 620 {
 621         struct e1000_hw *hw =
 622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623
 624         /* only for mailbox */
 625         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 626         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 627         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 628         E1000_WRITE_FLUSH(hw);
 629 }
 630
 631 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 632 static void
 633 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 634 {
 635         uint32_t tmp = 0;
 636
 637         /* mailbox */
 638         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 639         tmp |= E1000_VTIVAR_VALID;
 640         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 641 }
 642
 643 static void
 644 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 645 {
 646         struct e1000_hw *hw =
 647                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 648
 649         /* Configure VF other cause ivar */
 650         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 651 }
 652
 653 static inline int32_t
 654 igb_pf_reset_hw(struct e1000_hw *hw)
 655 {
 656         uint32_t ctrl_ext;
 657         int32_t status;
 658
 659         status = e1000_reset_hw(hw);
 660
 661         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 662         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 663         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 664         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 665         E1000_WRITE_FLUSH(hw);
 666
 667         return status;
 668 }
 669
 670 static void
 671 igb_identify_hardware(struct rte_eth_dev *dev)
 672 {
 673         struct e1000_hw *hw =
 674                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 675
 676         hw->vendor_id = dev->pci_dev->id.vendor_id;
 677         hw->device_id = dev->pci_dev->id.device_id;
 678         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 679         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 680
 681         e1000_set_mac_type(hw);
 682
 683         /* need to check if it is a vf device below */
 684 }
 685
 686 static int
 687 igb_reset_swfw_lock(struct e1000_hw *hw)
 688 {
 689         int ret_val;
 690
 691         /*
 692          * Do mac ops initialization manually here, since we will need
 693          * some function pointers set by this call.
 694          */
 695         ret_val = e1000_init_mac_params(hw);
 696         if (ret_val)
 697                 return ret_val;
 698
 699         /*
 700          * SMBI lock should not fail in this early stage. If this is the case,
 701          * it is due to an improper exit of the application.
 702          * So force the release of the faulty lock.
 703          */
 704         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 705                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 706         }
 707         e1000_put_hw_semaphore_generic(hw);
 708
 709         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 710                 uint16_t mask;
 711
 712                 /*
 713                  * Phy lock should not fail in this early stage. If this is the case,
 714                  * it is due to an improper exit of the application.
 715                  * So force the release of the faulty lock.
 716                  */
 717                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 718                 if (hw->bus.func > E1000_FUNC_1)
 719                         mask <<= 2;
 720                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 721                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 722                                     hw->bus.func);
 723                 }
 724                 hw->mac.ops.release_swfw_sync(hw, mask);
 725
 726                 /*
 727                  * This one is more tricky since it is common to all ports; but
 728                  * swfw_sync retries last long enough (1s) to be almost sure that if
 729                  * lock can not be taken it is due to an improper lock of the
 730                  * semaphore.
 731                  */
 732                 mask = E1000_SWFW_EEP_SM;
 733                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 734                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 735                 }
 736                 hw->mac.ops.release_swfw_sync(hw, mask);
 737         }
 738
 739         return E1000_SUCCESS;
 740 }
 741
 742 static int
 743 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 744 {
 745         int error = 0;
 746         struct rte_pci_device *pci_dev;
 747         struct e1000_hw *hw =
 748                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 749         struct e1000_vfta * shadow_vfta =
 750                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 751         struct e1000_filter_info *filter_info =
 752                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 753         struct e1000_adapter *adapter =
 754                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 755
 756         uint32_t ctrl_ext;
 757
 758         pci_dev = eth_dev->pci_dev;
 759
 760         eth_dev->dev_ops = &eth_igb_ops;
 761         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 762         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 763
 764         /* for secondary processes, we don't initialise any further as primary
 765          * has already done this work. Only check we don't need a different
 766          * RX function */
 767         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 768                 if (eth_dev->data->scattered_rx)
 769                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 770                 return 0;
 771         }
 772
 773         rte_eth_copy_pci_info(eth_dev, pci_dev);
 774
 775         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 776
 777         igb_identify_hardware(eth_dev);
 778         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 779                 error = -EIO;
 780                 goto err_late;
 781         }
 782
 783         e1000_get_bus_info(hw);
 784
 785         /* Reset any pending lock */
 786         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 787                 error = -EIO;
 788                 goto err_late;
 789         }
 790
 791         /* Finish initialization */
 792         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 793                 error = -EIO;
 794                 goto err_late;
 795         }
 796
 797         hw->mac.autoneg = 1;
 798         hw->phy.autoneg_wait_to_complete = 0;
 799         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 800
 801         /* Copper options */
 802         if (hw->phy.media_type == e1000_media_type_copper) {
 803                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 804                 hw->phy.disable_polarity_correction = 0;
 805                 hw->phy.ms_type = e1000_ms_hw_default;
 806         }
 807
 808         /*
 809          * Start from a known state, this is important in reading the nvm
 810          * and mac from that.
 811          */
 812         igb_pf_reset_hw(hw);
 813
 814         /* Make sure we have a good EEPROM before we read from it */
 815         if (e1000_validate_nvm_checksum(hw) < 0) {
 816                 /*
 817                  * Some PCI-E parts fail the first check due to
 818                  * the link being in sleep state, call it again,
 819                  * if it fails a second time its a real issue.
 820                  */
 821                 if (e1000_validate_nvm_checksum(hw) < 0) {
 822                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 823                         error = -EIO;
 824                         goto err_late;
 825                 }
 826         }
 827
 828         /* Read the permanent MAC address out of the EEPROM */
 829         if (e1000_read_mac_addr(hw) != 0) {
 830                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 831                 error = -EIO;
 832                 goto err_late;
 833         }
 834
 835         /* Allocate memory for storing MAC addresses */
 836         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 837                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 838         if (eth_dev->data->mac_addrs == NULL) {
 839                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 840                                                 "store MAC addresses",
 841                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 842                 error = -ENOMEM;
 843                 goto err_late;
 844         }
 845
 846         /* Copy the permanent MAC address */
 847         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 848
 849         /* initialize the vfta */
 850         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 851
 852         /* Now initialize the hardware */
 853         if (igb_hardware_init(hw) != 0) {
 854                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 855                 rte_free(eth_dev->data->mac_addrs);
 856                 eth_dev->data->mac_addrs = NULL;
 857                 error = -ENODEV;
 858                 goto err_late;
 859         }
 860         hw->mac.get_link_status = 1;
 861         adapter->stopped = 0;
 862
 863         /* Indicate SOL/IDER usage */
 864         if (e1000_check_reset_block(hw) < 0) {
 865                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 866                                         "SOL/IDER session");
 867         }
 868
 869         /* initialize PF if max_vfs not zero */
 870         igb_pf_host_init(eth_dev);
 871
 872         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 873         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 874         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 875         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 876         E1000_WRITE_FLUSH(hw);
 877
 878         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 879                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 880                      pci_dev->id.device_id);
 881
 882         rte_intr_callback_register(&pci_dev->intr_handle,
 883                                    eth_igb_interrupt_handler,
 884                                    (void *)eth_dev);
 885
 886         /* enable uio/vfio intr/eventfd mapping */
 887         rte_intr_enable(&pci_dev->intr_handle);
 888
 889         /* enable support intr */
 890         igb_intr_enable(eth_dev);
 891
 892         TAILQ_INIT(&filter_info->flex_list);
 893         filter_info->flex_mask = 0;
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         filter_info->twotuple_mask = 0;
 896         TAILQ_INIT(&filter_info->fivetuple_list);
 897         filter_info->fivetuple_mask = 0;
 898
 899         return 0;
 900
 901 err_late:
 902         igb_hw_control_release(hw);
 903
 904         return error;
 905 }
 906
 907 static int
 908 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 909 {
 910         struct rte_pci_device *pci_dev;
 911         struct e1000_hw *hw;
 912         struct e1000_adapter *adapter =
 913                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 914
 915         PMD_INIT_FUNC_TRACE();
 916
 917         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 918                 return -EPERM;
 919
 920         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 921         pci_dev = eth_dev->pci_dev;
 922
 923         if (adapter->stopped == 0)
 924                 eth_igb_close(eth_dev);
 925
 926         eth_dev->dev_ops = NULL;
 927         eth_dev->rx_pkt_burst = NULL;
 928         eth_dev->tx_pkt_burst = NULL;
 929
 930         /* Reset any pending lock */
 931         igb_reset_swfw_lock(hw);
 932
 933         rte_free(eth_dev->data->mac_addrs);
 934         eth_dev->data->mac_addrs = NULL;
 935
 936         /* uninitialize PF if max_vfs not zero */
 937         igb_pf_host_uninit(eth_dev);
 938
 939         /* disable uio intr before callback unregister */
 940         rte_intr_disable(&(pci_dev->intr_handle));
 941         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 942                 eth_igb_interrupt_handler, (void *)eth_dev);
 943
 944         return 0;
 945 }
 946
 947 /*
 948  * Virtual Function device init
 949  */
 950 static int
 951 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 952 {
 953         struct rte_pci_device *pci_dev;
 954         struct e1000_adapter *adapter =
 955                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 956         struct e1000_hw *hw =
 957                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 958         int diag;
 959         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 964         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 965         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 966
 967         /* for secondary processes, we don't initialise any further as primary
 968          * has already done this work. Only check we don't need a different
 969          * RX function */
 970         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 971                 if (eth_dev->data->scattered_rx)
 972                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 973                 return 0;
 974         }
 975
 976         pci_dev = eth_dev->pci_dev;
 977
 978         rte_eth_copy_pci_info(eth_dev, pci_dev);
 979
 980         hw->device_id = pci_dev->id.device_id;
 981         hw->vendor_id = pci_dev->id.vendor_id;
 982         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 983         adapter->stopped = 0;
 984
 985         /* Initialize the shared code (base driver) */
 986         diag = e1000_setup_init_funcs(hw, TRUE);
 987         if (diag != 0) {
 988                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 989                         diag);
 990                 return -EIO;
 991         }
 992
 993         /* init_mailbox_params */
 994         hw->mbx.ops.init_params(hw);
 995
 996         /* Disable the interrupts for VF */
 997         igbvf_intr_disable(hw);
 998
 999         diag = hw->mac.ops.reset_hw(hw);
1000
1001         /* Allocate memory for storing MAC addresses */
1002         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003                 hw->mac.rar_entry_count, 0);
1004         if (eth_dev->data->mac_addrs == NULL) {
1005                 PMD_INIT_LOG(ERR,
1006                         "Failed to allocate %d bytes needed to store MAC "
1007                         "addresses",
1008                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1009                 return -ENOMEM;
1010         }
1011
1012         /* Generate a random MAC address, if none was assigned by PF. */
1013         if (is_zero_ether_addr(perm_addr)) {
1014                 eth_random_addr(perm_addr->addr_bytes);
1015                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1016                 if (diag) {
1017                         rte_free(eth_dev->data->mac_addrs);
1018                         eth_dev->data->mac_addrs = NULL;
1019                         return diag;
1020                 }
1021                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1022                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1023                              "%02x:%02x:%02x:%02x:%02x:%02x",
1024                              perm_addr->addr_bytes[0],
1025                              perm_addr->addr_bytes[1],
1026                              perm_addr->addr_bytes[2],
1027                              perm_addr->addr_bytes[3],
1028                              perm_addr->addr_bytes[4],
1029                              perm_addr->addr_bytes[5]);
1030         }
1031
1032         /* Copy the permanent MAC address */
1033         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034                         &eth_dev->data->mac_addrs[0]);
1035
1036         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1037                      "mac.type=%s",
1038                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1039                      pci_dev->id.device_id, "igb_mac_82576_vf");
1040
1041         rte_intr_callback_register(&pci_dev->intr_handle,
1042                                    eth_igbvf_interrupt_handler,
1043                                    (void *)eth_dev);
1044
1045         return 0;
1046 }
1047
1048 static int
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1050 {
1051         struct e1000_adapter *adapter =
1052                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1058                 return -EPERM;
1059
1060         if (adapter->stopped == 0)
1061                 igbvf_dev_close(eth_dev);
1062
1063         eth_dev->dev_ops = NULL;
1064         eth_dev->rx_pkt_burst = NULL;
1065         eth_dev->tx_pkt_burst = NULL;
1066
1067         rte_free(eth_dev->data->mac_addrs);
1068         eth_dev->data->mac_addrs = NULL;
1069
1070         /* disable uio intr before callback unregister */
1071         rte_intr_disable(&pci_dev->intr_handle);
1072         rte_intr_callback_unregister(&pci_dev->intr_handle,
1073                                      eth_igbvf_interrupt_handler,
1074                                      (void *)eth_dev);
1075
1076         return 0;
1077 }
1078
1079 static struct eth_driver rte_igb_pmd = {
1080         .pci_drv = {
1081                 .id_table = pci_id_igb_map,
1082                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1083                         RTE_PCI_DRV_DETACHABLE,
1084                 .probe = rte_eth_dev_pci_probe,
1085                 .remove = rte_eth_dev_pci_remove,
1086         },
1087         .eth_dev_init = eth_igb_dev_init,
1088         .eth_dev_uninit = eth_igb_dev_uninit,
1089         .dev_private_size = sizeof(struct e1000_adapter),
1090 };
1091
1092 /*
1093  * virtual function driver struct
1094  */
1095 static struct eth_driver rte_igbvf_pmd = {
1096         .pci_drv = {
1097                 .id_table = pci_id_igbvf_map,
1098                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1099                 .probe = rte_eth_dev_pci_probe,
1100                 .remove = rte_eth_dev_pci_remove,
1101         },
1102         .eth_dev_init = eth_igbvf_dev_init,
1103         .eth_dev_uninit = eth_igbvf_dev_uninit,
1104         .dev_private_size = sizeof(struct e1000_adapter),
1105 };
1106
1107 static void
1108 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1109 {
1110         struct e1000_hw *hw =
1111                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1113         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1114         rctl |= E1000_RCTL_VFE;
1115         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1116 }
1117
1118 static int
1119 igb_check_mq_mode(struct rte_eth_dev *dev)
1120 {
1121         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1122         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1123         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1124         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1125
1126         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1127             tx_mq_mode == ETH_MQ_TX_DCB ||
1128             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1129                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1130                 return -EINVAL;
1131         }
1132         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1133                 /* Check multi-queue mode.
1134                  * To no break software we accept ETH_MQ_RX_NONE as this might
1135                  * be used to turn off VLAN filter.
1136                  */
1137
1138                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1139                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1140                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1141                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1142                 } else {
1143                         /* Only support one queue on VFs.
1144                          * RSS together with SRIOV is not supported.
1145                          */
1146                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1147                                         " wrong mq_mode rx %d.",
1148                                         rx_mq_mode);
1149                         return -EINVAL;
1150                 }
1151                 /* TX mode is not used here, so mode might be ignored.*/
1152                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1153                         /* SRIOV only works in VMDq enable mode */
1154                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1155                                         " TX mode %d is not supported. "
1156                                         " Driver will behave as %d mode.",
1157                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1158                 }
1159
1160                 /* check valid queue number */
1161                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1162                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1163                                         " only support one queue on VFs.");
1164                         return -EINVAL;
1165                 }
1166         } else {
1167                 /* To no break software that set invalid mode, only display
1168                  * warning if invalid mode is used.
1169                  */
1170                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1171                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1172                     rx_mq_mode != ETH_MQ_RX_RSS) {
1173                         /* RSS together with VMDq not supported*/
1174                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1175                                      rx_mq_mode);
1176                         return -EINVAL;
1177                 }
1178
1179                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1180                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1181                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1182                                         " Due to txmode is meaningless in this"
1183                                         " driver, just ignore.",
1184                                         tx_mq_mode);
1185                 }
1186         }
1187         return 0;
1188 }
1189
1190 static int
1191 eth_igb_configure(struct rte_eth_dev *dev)
1192 {
1193         struct e1000_interrupt *intr =
1194                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1195         int ret;
1196
1197         PMD_INIT_FUNC_TRACE();
1198
1199         /* multipe queue mode checking */
1200         ret  = igb_check_mq_mode(dev);
1201         if (ret != 0) {
1202                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1203                             ret);
1204                 return ret;
1205         }
1206
1207         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1208         PMD_INIT_FUNC_TRACE();
1209
1210         return 0;
1211 }
1212
1213 static int
1214 eth_igb_start(struct rte_eth_dev *dev)
1215 {
1216         struct e1000_hw *hw =
1217                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218         struct e1000_adapter *adapter =
1219                 E1000_DEV_PRIVATE(dev->data->dev_private);
1220         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1221         int ret, mask;
1222         uint32_t intr_vector = 0;
1223         uint32_t ctrl_ext;
1224         uint32_t *speeds;
1225         int num_speeds;
1226         bool autoneg;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         /* disable uio/vfio intr/eventfd mapping */
1231         rte_intr_disable(intr_handle);
1232
1233         /* Power up the phy. Needed to make the link go Up */
1234         eth_igb_dev_set_link_up(dev);
1235
1236         /*
1237          * Packet Buffer Allocation (PBA)
1238          * Writing PBA sets the receive portion of the buffer
1239          * the remainder is used for the transmit buffer.
1240          */
1241         if (hw->mac.type == e1000_82575) {
1242                 uint32_t pba;
1243
1244                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1245                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1246         }
1247
1248         /* Put the address into the Receive Address Array */
1249         e1000_rar_set(hw, hw->mac.addr, 0);
1250
1251         /* Initialize the hardware */
1252         if (igb_hardware_init(hw)) {
1253                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1254                 return -EIO;
1255         }
1256         adapter->stopped = 0;
1257
1258         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1259
1260         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1261         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1262         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1263         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1264         E1000_WRITE_FLUSH(hw);
1265
1266         /* configure PF module if SRIOV enabled */
1267         igb_pf_host_configure(dev);
1268
1269         /* check and configure queue intr-vector mapping */
1270         if ((rte_intr_cap_multiple(intr_handle) ||
1271              !RTE_ETH_DEV_SRIOV(dev).active) &&
1272             dev->data->dev_conf.intr_conf.rxq != 0) {
1273                 intr_vector = dev->data->nb_rx_queues;
1274                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1275                         return -1;
1276         }
1277
1278         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1279                 intr_handle->intr_vec =
1280                         rte_zmalloc("intr_vec",
1281                                     dev->data->nb_rx_queues * sizeof(int), 0);
1282                 if (intr_handle->intr_vec == NULL) {
1283                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1284                                      " intr_vec\n", dev->data->nb_rx_queues);
1285                         return -ENOMEM;
1286                 }
1287         }
1288
1289         /* confiugre msix for rx interrupt */
1290         eth_igb_configure_msix_intr(dev);
1291
1292         /* Configure for OS presence */
1293         igb_init_manageability(hw);
1294
1295         eth_igb_tx_init(dev);
1296
1297         /* This can fail when allocating mbufs for descriptor rings */
1298         ret = eth_igb_rx_init(dev);
1299         if (ret) {
1300                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1301                 igb_dev_clear_queues(dev);
1302                 return ret;
1303         }
1304
1305         e1000_clear_hw_cntrs_base_generic(hw);
1306
1307         /*
1308          * VLAN Offload Settings
1309          */
1310         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1311                         ETH_VLAN_EXTEND_MASK;
1312         eth_igb_vlan_offload_set(dev, mask);
1313
1314         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1315                 /* Enable VLAN filter since VMDq always use VLAN filter */
1316                 igb_vmdq_vlan_hw_filter_enable(dev);
1317         }
1318
1319         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1320                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1321                 (hw->mac.type == e1000_i211)) {
1322                 /* Configure EITR with the maximum possible value (0xFFFF) */
1323                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1324         }
1325
1326         /* Setup link speed and duplex */
1327         speeds = &dev->data->dev_conf.link_speeds;
1328         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1329                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1330         } else {
1331                 num_speeds = 0;
1332                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1333
1334                 /* Reset */
1335                 hw->phy.autoneg_advertised = 0;
1336
1337                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1338                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1339                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1340                         num_speeds = -1;
1341                         goto error_invalid_config;
1342                 }
1343                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1344                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1345                         num_speeds++;
1346                 }
1347                 if (*speeds & ETH_LINK_SPEED_10M) {
1348                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1349                         num_speeds++;
1350                 }
1351                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1352                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1353                         num_speeds++;
1354                 }
1355                 if (*speeds & ETH_LINK_SPEED_100M) {
1356                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1357                         num_speeds++;
1358                 }
1359                 if (*speeds & ETH_LINK_SPEED_1G) {
1360                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1361                         num_speeds++;
1362                 }
1363                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1364                         goto error_invalid_config;
1365         }
1366
1367         e1000_setup_link(hw);
1368
1369         if (rte_intr_allow_others(intr_handle)) {
1370                 /* check if lsc interrupt is enabled */
1371                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1372                         eth_igb_lsc_interrupt_setup(dev);
1373         } else {
1374                 rte_intr_callback_unregister(intr_handle,
1375                                              eth_igb_interrupt_handler,
1376                                              (void *)dev);
1377                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1378                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1379                                      " no intr multiplex\n");
1380         }
1381
1382         /* check if rxq interrupt is enabled */
1383         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1384             rte_intr_dp_is_en(intr_handle))
1385                 eth_igb_rxq_interrupt_setup(dev);
1386
1387         /* enable uio/vfio intr/eventfd mapping */
1388         rte_intr_enable(intr_handle);
1389
1390         /* resume enabled intr since hw reset */
1391         igb_intr_enable(dev);
1392
1393         PMD_INIT_LOG(DEBUG, "<<");
1394
1395         return 0;
1396
1397 error_invalid_config:
1398         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1399                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1400         igb_dev_clear_queues(dev);
1401         return -EINVAL;
1402 }
1403
1404 /*********************************************************************
1405  *
1406  *  This routine disables all traffic on the adapter by issuing a
1407  *  global reset on the MAC.
1408  *
1409  **********************************************************************/
1410 static void
1411 eth_igb_stop(struct rte_eth_dev *dev)
1412 {
1413         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414         struct e1000_filter_info *filter_info =
1415                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1416         struct rte_eth_link link;
1417         struct e1000_flex_filter *p_flex;
1418         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1419         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1420         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1421
1422         igb_intr_disable(hw);
1423
1424         /* disable intr eventfd mapping */
1425         rte_intr_disable(intr_handle);
1426
1427         igb_pf_reset_hw(hw);
1428         E1000_WRITE_REG(hw, E1000_WUC, 0);
1429
1430         /* Set bit for Go Link disconnect */
1431         if (hw->mac.type >= e1000_82580) {
1432                 uint32_t phpm_reg;
1433
1434                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1435                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1436                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1437         }
1438
1439         /* Power down the phy. Needed to make the link go Down */
1440         eth_igb_dev_set_link_down(dev);
1441
1442         igb_dev_clear_queues(dev);
1443
1444         /* clear the recorded link status */
1445         memset(&link, 0, sizeof(link));
1446         rte_igb_dev_atomic_write_link_status(dev, &link);
1447
1448         /* Remove all flex filters of the device */
1449         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1450                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1451                 rte_free(p_flex);
1452         }
1453         filter_info->flex_mask = 0;
1454
1455         /* Remove all ntuple filters of the device */
1456         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1457              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1458                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1459                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1460                              p_5tuple, entries);
1461                 rte_free(p_5tuple);
1462         }
1463         filter_info->fivetuple_mask = 0;
1464         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1465              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1466                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1467                 TAILQ_REMOVE(&filter_info->twotuple_list,
1468                              p_2tuple, entries);
1469                 rte_free(p_2tuple);
1470         }
1471         filter_info->twotuple_mask = 0;
1472
1473         if (!rte_intr_allow_others(intr_handle))
1474                 /* resume to the default handler */
1475                 rte_intr_callback_register(intr_handle,
1476                                            eth_igb_interrupt_handler,
1477                                            (void *)dev);
1478
1479         /* Clean datapath event and queue/vec mapping */
1480         rte_intr_efd_disable(intr_handle);
1481         if (intr_handle->intr_vec != NULL) {
1482                 rte_free(intr_handle->intr_vec);
1483                 intr_handle->intr_vec = NULL;
1484         }
1485 }
1486
1487 static int
1488 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1489 {
1490         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1491
1492         if (hw->phy.media_type == e1000_media_type_copper)
1493                 e1000_power_up_phy(hw);
1494         else
1495                 e1000_power_up_fiber_serdes_link(hw);
1496
1497         return 0;
1498 }
1499
1500 static int
1501 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1502 {
1503         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504
1505         if (hw->phy.media_type == e1000_media_type_copper)
1506                 e1000_power_down_phy(hw);
1507         else
1508                 e1000_shutdown_fiber_serdes_link(hw);
1509
1510         return 0;
1511 }
1512
1513 static void
1514 eth_igb_close(struct rte_eth_dev *dev)
1515 {
1516         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         struct e1000_adapter *adapter =
1518                 E1000_DEV_PRIVATE(dev->data->dev_private);
1519         struct rte_eth_link link;
1520         struct rte_pci_device *pci_dev;
1521
1522         eth_igb_stop(dev);
1523         adapter->stopped = 1;
1524
1525         e1000_phy_hw_reset(hw);
1526         igb_release_manageability(hw);
1527         igb_hw_control_release(hw);
1528
1529         /* Clear bit for Go Link disconnect */
1530         if (hw->mac.type >= e1000_82580) {
1531                 uint32_t phpm_reg;
1532
1533                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1534                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1535                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1536         }
1537
1538         igb_dev_free_queues(dev);
1539
1540         pci_dev = dev->pci_dev;
1541         if (pci_dev->intr_handle.intr_vec) {
1542                 rte_free(pci_dev->intr_handle.intr_vec);
1543                 pci_dev->intr_handle.intr_vec = NULL;
1544         }
1545
1546         memset(&link, 0, sizeof(link));
1547         rte_igb_dev_atomic_write_link_status(dev, &link);
1548 }
1549
1550 static int
1551 igb_get_rx_buffer_size(struct e1000_hw *hw)
1552 {
1553         uint32_t rx_buf_size;
1554         if (hw->mac.type == e1000_82576) {
1555                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1556         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1557                 /* PBS needs to be translated according to a lookup table */
1558                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1559                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1560                 rx_buf_size = (rx_buf_size << 10);
1561         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1562                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1563         } else {
1564                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1565         }
1566
1567         return rx_buf_size;
1568 }
1569
1570 /*********************************************************************
1571  *
1572  *  Initialize the hardware
1573  *
1574  **********************************************************************/
1575 static int
1576 igb_hardware_init(struct e1000_hw *hw)
1577 {
1578         uint32_t rx_buf_size;
1579         int diag;
1580
1581         /* Let the firmware know the OS is in control */
1582         igb_hw_control_acquire(hw);
1583
1584         /*
1585          * These parameters control the automatic generation (Tx) and
1586          * response (Rx) to Ethernet PAUSE frames.
1587          * - High water mark should allow for at least two standard size (1518)
1588          *   frames to be received after sending an XOFF.
1589          * - Low water mark works best when it is very near the high water mark.
1590          *   This allows the receiver to restart by sending XON when it has
1591          *   drained a bit. Here we use an arbitrary value of 1500 which will
1592          *   restart after one full frame is pulled from the buffer. There
1593          *   could be several smaller frames in the buffer and if so they will
1594          *   not trigger the XON until their total number reduces the buffer
1595          *   by 1500.
1596          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1597          */
1598         rx_buf_size = igb_get_rx_buffer_size(hw);
1599
1600         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1601         hw->fc.low_water = hw->fc.high_water - 1500;
1602         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1603         hw->fc.send_xon = 1;
1604
1605         /* Set Flow control, use the tunable location if sane */
1606         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1607                 hw->fc.requested_mode = igb_fc_setting;
1608         else
1609                 hw->fc.requested_mode = e1000_fc_none;
1610
1611         /* Issue a global reset */
1612         igb_pf_reset_hw(hw);
1613         E1000_WRITE_REG(hw, E1000_WUC, 0);
1614
1615         diag = e1000_init_hw(hw);
1616         if (diag < 0)
1617                 return diag;
1618
1619         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1620         e1000_get_phy_info(hw);
1621         e1000_check_for_link(hw);
1622
1623         return 0;
1624 }
1625
1626 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1627 static void
1628 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1629 {
1630         int pause_frames;
1631
1632         uint64_t old_gprc  = stats->gprc;
1633         uint64_t old_gptc  = stats->gptc;
1634         uint64_t old_tpr   = stats->tpr;
1635         uint64_t old_tpt   = stats->tpt;
1636         uint64_t old_rpthc = stats->rpthc;
1637         uint64_t old_hgptc = stats->hgptc;
1638
1639         if(hw->phy.media_type == e1000_media_type_copper ||
1640             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1641                 stats->symerrs +=
1642                     E1000_READ_REG(hw,E1000_SYMERRS);
1643                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1644         }
1645
1646         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1647         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1648         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1649         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1650
1651         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1652         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1653         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1654         stats->dc += E1000_READ_REG(hw, E1000_DC);
1655         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1656         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1657         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1658         /*
1659         ** For watchdog management we need to know if we have been
1660         ** paused during the last interval, so capture that here.
1661         */
1662         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1663         stats->xoffrxc += pause_frames;
1664         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1665         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1666         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1667         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1668         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1669         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1670         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1671         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1672         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1673         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1674         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1675         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1676
1677         /* For the 64-bit byte counters the low dword must be read first. */
1678         /* Both registers clear on the read of the high dword */
1679
1680         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1681         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1682         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1683         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1684         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1685         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1686         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1687
1688         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1689         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1690         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1691         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1692         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1693
1694         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1695         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1696
1697         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1698         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1699         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1700         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1701         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1702         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1703
1704         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1705         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1706         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1707         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1708         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1709         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1710         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1711         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1712
1713         /* Interrupt Counts */
1714
1715         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1716         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1717         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1718         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1719         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1720         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1721         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1722         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1723         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1724
1725         /* Host to Card Statistics */
1726
1727         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1728         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1729         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1730         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1731         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1732         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1733         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1734         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1735         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1736         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1737         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1738         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1739         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1740         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1741         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1742         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1743
1744         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1745         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1746         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1747         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1748         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1749         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1750 }
1751
1752 static void
1753 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1754 {
1755         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756         struct e1000_hw_stats *stats =
1757                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1758
1759         igb_read_stats_registers(hw, stats);
1760
1761         if (rte_stats == NULL)
1762                 return;
1763
1764         /* Rx Errors */
1765         rte_stats->imissed = stats->mpc;
1766         rte_stats->ierrors = stats->crcerrs +
1767                              stats->rlec + stats->ruc + stats->roc +
1768                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1769
1770         /* Tx Errors */
1771         rte_stats->oerrors = stats->ecol + stats->latecol;
1772
1773         rte_stats->ipackets = stats->gprc;
1774         rte_stats->opackets = stats->gptc;
1775         rte_stats->ibytes   = stats->gorc;
1776         rte_stats->obytes   = stats->gotc;
1777 }
1778
1779 static void
1780 eth_igb_stats_reset(struct rte_eth_dev *dev)
1781 {
1782         struct e1000_hw_stats *hw_stats =
1783                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1784
1785         /* HW registers are cleared on read */
1786         eth_igb_stats_get(dev, NULL);
1787
1788         /* Reset software totals */
1789         memset(hw_stats, 0, sizeof(*hw_stats));
1790 }
1791
1792 static void
1793 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1794 {
1795         struct e1000_hw_stats *stats =
1796                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1797
1798         /* HW registers are cleared on read */
1799         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1800
1801         /* Reset software totals */
1802         memset(stats, 0, sizeof(*stats));
1803 }
1804
1805 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1806         struct rte_eth_xstat_name *xstats_names,
1807         __rte_unused unsigned limit)
1808 {
1809         unsigned i;
1810
1811         if (xstats_names == NULL)
1812                 return IGB_NB_XSTATS;
1813
1814         /* Note: limit checked in rte_eth_xstats_names() */
1815
1816         for (i = 0; i < IGB_NB_XSTATS; i++) {
1817                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1818                          "%s", rte_igb_stats_strings[i].name);
1819         }
1820
1821         return IGB_NB_XSTATS;
1822 }
1823
1824 static int
1825 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1826                    unsigned n)
1827 {
1828         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829         struct e1000_hw_stats *hw_stats =
1830                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1831         unsigned i;
1832
1833         if (n < IGB_NB_XSTATS)
1834                 return IGB_NB_XSTATS;
1835
1836         igb_read_stats_registers(hw, hw_stats);
1837
1838         /* If this is a reset xstats is NULL, and we have cleared the
1839          * registers by reading them.
1840          */
1841         if (!xstats)
1842                 return 0;
1843
1844         /* Extended stats */
1845         for (i = 0; i < IGB_NB_XSTATS; i++) {
1846                 xstats[i].id = i;
1847                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1848                         rte_igb_stats_strings[i].offset);
1849         }
1850
1851         return IGB_NB_XSTATS;
1852 }
1853
1854 static void
1855 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1856 {
1857         /* Good Rx packets, include VF loopback */
1858         UPDATE_VF_STAT(E1000_VFGPRC,
1859             hw_stats->last_gprc, hw_stats->gprc);
1860
1861         /* Good Rx octets, include VF loopback */
1862         UPDATE_VF_STAT(E1000_VFGORC,
1863             hw_stats->last_gorc, hw_stats->gorc);
1864
1865         /* Good Tx packets, include VF loopback */
1866         UPDATE_VF_STAT(E1000_VFGPTC,
1867             hw_stats->last_gptc, hw_stats->gptc);
1868
1869         /* Good Tx octets, include VF loopback */
1870         UPDATE_VF_STAT(E1000_VFGOTC,
1871             hw_stats->last_gotc, hw_stats->gotc);
1872
1873         /* Rx Multicst packets */
1874         UPDATE_VF_STAT(E1000_VFMPRC,
1875             hw_stats->last_mprc, hw_stats->mprc);
1876
1877         /* Good Rx loopback packets */
1878         UPDATE_VF_STAT(E1000_VFGPRLBC,
1879             hw_stats->last_gprlbc, hw_stats->gprlbc);
1880
1881         /* Good Rx loopback octets */
1882         UPDATE_VF_STAT(E1000_VFGORLBC,
1883             hw_stats->last_gorlbc, hw_stats->gorlbc);
1884
1885         /* Good Tx loopback packets */
1886         UPDATE_VF_STAT(E1000_VFGPTLBC,
1887             hw_stats->last_gptlbc, hw_stats->gptlbc);
1888
1889         /* Good Tx loopback octets */
1890         UPDATE_VF_STAT(E1000_VFGOTLBC,
1891             hw_stats->last_gotlbc, hw_stats->gotlbc);
1892 }
1893
1894 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1895                                      struct rte_eth_xstat_name *xstats_names,
1896                                      __rte_unused unsigned limit)
1897 {
1898         unsigned i;
1899
1900         if (xstats_names != NULL)
1901                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1902                         snprintf(xstats_names[i].name,
1903                                 sizeof(xstats_names[i].name), "%s",
1904                                 rte_igbvf_stats_strings[i].name);
1905                 }
1906         return IGBVF_NB_XSTATS;
1907 }
1908
1909 static int
1910 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1911                      unsigned n)
1912 {
1913         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1915                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1916         unsigned i;
1917
1918         if (n < IGBVF_NB_XSTATS)
1919                 return IGBVF_NB_XSTATS;
1920
1921         igbvf_read_stats_registers(hw, hw_stats);
1922
1923         if (!xstats)
1924                 return 0;
1925
1926         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1927                 xstats[i].id = i;
1928                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1929                         rte_igbvf_stats_strings[i].offset);
1930         }
1931
1932         return IGBVF_NB_XSTATS;
1933 }
1934
1935 static void
1936 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1937 {
1938         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1940                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1941
1942         igbvf_read_stats_registers(hw, hw_stats);
1943
1944         if (rte_stats == NULL)
1945                 return;
1946
1947         rte_stats->ipackets = hw_stats->gprc;
1948         rte_stats->ibytes = hw_stats->gorc;
1949         rte_stats->opackets = hw_stats->gptc;
1950         rte_stats->obytes = hw_stats->gotc;
1951 }
1952
1953 static void
1954 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1955 {
1956         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1957                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1958
1959         /* Sync HW register to the last stats */
1960         eth_igbvf_stats_get(dev, NULL);
1961
1962         /* reset HW current stats*/
1963         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1964                offsetof(struct e1000_vf_stats, gprc));
1965 }
1966
1967 static void
1968 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1969 {
1970         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1971
1972         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1973         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1974         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1975         dev_info->rx_offload_capa =
1976                 DEV_RX_OFFLOAD_VLAN_STRIP |
1977                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1978                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1979                 DEV_RX_OFFLOAD_TCP_CKSUM;
1980         dev_info->tx_offload_capa =
1981                 DEV_TX_OFFLOAD_VLAN_INSERT |
1982                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1983                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1984                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1985                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1986                 DEV_TX_OFFLOAD_TCP_TSO;
1987
1988         switch (hw->mac.type) {
1989         case e1000_82575:
1990                 dev_info->max_rx_queues = 4;
1991                 dev_info->max_tx_queues = 4;
1992                 dev_info->max_vmdq_pools = 0;
1993                 break;
1994
1995         case e1000_82576:
1996                 dev_info->max_rx_queues = 16;
1997                 dev_info->max_tx_queues = 16;
1998                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1999                 dev_info->vmdq_queue_num = 16;
2000                 break;
2001
2002         case e1000_82580:
2003                 dev_info->max_rx_queues = 8;
2004                 dev_info->max_tx_queues = 8;
2005                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2006                 dev_info->vmdq_queue_num = 8;
2007                 break;
2008
2009         case e1000_i350:
2010                 dev_info->max_rx_queues = 8;
2011                 dev_info->max_tx_queues = 8;
2012                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2013                 dev_info->vmdq_queue_num = 8;
2014                 break;
2015
2016         case e1000_i354:
2017                 dev_info->max_rx_queues = 8;
2018                 dev_info->max_tx_queues = 8;
2019                 break;
2020
2021         case e1000_i210:
2022                 dev_info->max_rx_queues = 4;
2023                 dev_info->max_tx_queues = 4;
2024                 dev_info->max_vmdq_pools = 0;
2025                 break;
2026
2027         case e1000_i211:
2028                 dev_info->max_rx_queues = 2;
2029                 dev_info->max_tx_queues = 2;
2030                 dev_info->max_vmdq_pools = 0;
2031                 break;
2032
2033         default:
2034                 /* Should not happen */
2035                 break;
2036         }
2037         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2038         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2039         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2040
2041         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2042                 .rx_thresh = {
2043                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2044                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2045                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2046                 },
2047                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2048                 .rx_drop_en = 0,
2049         };
2050
2051         dev_info->default_txconf = (struct rte_eth_txconf) {
2052                 .tx_thresh = {
2053                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2054                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2055                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2056                 },
2057                 .txq_flags = 0,
2058         };
2059
2060         dev_info->rx_desc_lim = rx_desc_lim;
2061         dev_info->tx_desc_lim = tx_desc_lim;
2062
2063         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2064                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2065                         ETH_LINK_SPEED_1G;
2066 }
2067
2068 static const uint32_t *
2069 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2070 {
2071         static const uint32_t ptypes[] = {
2072                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2073                 RTE_PTYPE_L2_ETHER,
2074                 RTE_PTYPE_L3_IPV4,
2075                 RTE_PTYPE_L3_IPV4_EXT,
2076                 RTE_PTYPE_L3_IPV6,
2077                 RTE_PTYPE_L3_IPV6_EXT,
2078                 RTE_PTYPE_L4_TCP,
2079                 RTE_PTYPE_L4_UDP,
2080                 RTE_PTYPE_L4_SCTP,
2081                 RTE_PTYPE_TUNNEL_IP,
2082                 RTE_PTYPE_INNER_L3_IPV6,
2083                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2084                 RTE_PTYPE_INNER_L4_TCP,
2085                 RTE_PTYPE_INNER_L4_UDP,
2086                 RTE_PTYPE_UNKNOWN
2087         };
2088
2089         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2090             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2091                 return ptypes;
2092         return NULL;
2093 }
2094
2095 static void
2096 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2097 {
2098         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099
2100         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2101         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2102         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2103         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2104                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2105                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2106                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2107         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2108                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2109                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2110                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2111                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2112                                 DEV_TX_OFFLOAD_TCP_TSO;
2113         switch (hw->mac.type) {
2114         case e1000_vfadapt:
2115                 dev_info->max_rx_queues = 2;
2116                 dev_info->max_tx_queues = 2;
2117                 break;
2118         case e1000_vfadapt_i350:
2119                 dev_info->max_rx_queues = 1;
2120                 dev_info->max_tx_queues = 1;
2121                 break;
2122         default:
2123                 /* Should not happen */
2124                 break;
2125         }
2126
2127         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2128                 .rx_thresh = {
2129                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2130                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2131                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2132                 },
2133                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2134                 .rx_drop_en = 0,
2135         };
2136
2137         dev_info->default_txconf = (struct rte_eth_txconf) {
2138                 .tx_thresh = {
2139                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2140                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2141                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2142                 },
2143                 .txq_flags = 0,
2144         };
2145
2146         dev_info->rx_desc_lim = rx_desc_lim;
2147         dev_info->tx_desc_lim = tx_desc_lim;
2148 }
2149
2150 /* return 0 means link status changed, -1 means not changed */
2151 static int
2152 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2153 {
2154         struct e1000_hw *hw =
2155                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156         struct rte_eth_link link, old;
2157         int link_check, count;
2158
2159         link_check = 0;
2160         hw->mac.get_link_status = 1;
2161
2162         /* possible wait-to-complete in up to 9 seconds */
2163         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2164                 /* Read the real link status */
2165                 switch (hw->phy.media_type) {
2166                 case e1000_media_type_copper:
2167                         /* Do the work to read phy */
2168                         e1000_check_for_link(hw);
2169                         link_check = !hw->mac.get_link_status;
2170                         break;
2171
2172                 case e1000_media_type_fiber:
2173                         e1000_check_for_link(hw);
2174                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2175                                       E1000_STATUS_LU);
2176                         break;
2177
2178                 case e1000_media_type_internal_serdes:
2179                         e1000_check_for_link(hw);
2180                         link_check = hw->mac.serdes_has_link;
2181                         break;
2182
2183                 /* VF device is type_unknown */
2184                 case e1000_media_type_unknown:
2185                         eth_igbvf_link_update(hw);
2186                         link_check = !hw->mac.get_link_status;
2187                         break;
2188
2189                 default:
2190                         break;
2191                 }
2192                 if (link_check || wait_to_complete == 0)
2193                         break;
2194                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2195         }
2196         memset(&link, 0, sizeof(link));
2197         rte_igb_dev_atomic_read_link_status(dev, &link);
2198         old = link;
2199
2200         /* Now we check if a transition has happened */
2201         if (link_check) {
2202                 uint16_t duplex, speed;
2203                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2204                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2205                                 ETH_LINK_FULL_DUPLEX :
2206                                 ETH_LINK_HALF_DUPLEX;
2207                 link.link_speed = speed;
2208                 link.link_status = ETH_LINK_UP;
2209                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2210                                 ETH_LINK_SPEED_FIXED);
2211         } else if (!link_check) {
2212                 link.link_speed = 0;
2213                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2214                 link.link_status = ETH_LINK_DOWN;
2215                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2216         }
2217         rte_igb_dev_atomic_write_link_status(dev, &link);
2218
2219         /* not changed */
2220         if (old.link_status == link.link_status)
2221                 return -1;
2222
2223         /* changed */
2224         return 0;
2225 }
2226
2227 /*
2228  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2229  * For ASF and Pass Through versions of f/w this means
2230  * that the driver is loaded.
2231  */
2232 static void
2233 igb_hw_control_acquire(struct e1000_hw *hw)
2234 {
2235         uint32_t ctrl_ext;
2236
2237         /* Let firmware know the driver has taken over */
2238         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2239         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2240 }
2241
2242 /*
2243  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2244  * For ASF and Pass Through versions of f/w this means that the
2245  * driver is no longer loaded.
2246  */
2247 static void
2248 igb_hw_control_release(struct e1000_hw *hw)
2249 {
2250         uint32_t ctrl_ext;
2251
2252         /* Let firmware taken over control of h/w */
2253         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2254         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2255                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2256 }
2257
2258 /*
2259  * Bit of a misnomer, what this really means is
2260  * to enable OS management of the system... aka
2261  * to disable special hardware management features.
2262  */
2263 static void
2264 igb_init_manageability(struct e1000_hw *hw)
2265 {
2266         if (e1000_enable_mng_pass_thru(hw)) {
2267                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2268                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2269
2270                 /* disable hardware interception of ARP */
2271                 manc &= ~(E1000_MANC_ARP_EN);
2272
2273                 /* enable receiving management packets to the host */
2274                 manc |= E1000_MANC_EN_MNG2HOST;
2275                 manc2h |= 1 << 5;  /* Mng Port 623 */
2276                 manc2h |= 1 << 6;  /* Mng Port 664 */
2277                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2278                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2279         }
2280 }
2281
2282 static void
2283 igb_release_manageability(struct e1000_hw *hw)
2284 {
2285         if (e1000_enable_mng_pass_thru(hw)) {
2286                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2287
2288                 manc |= E1000_MANC_ARP_EN;
2289                 manc &= ~E1000_MANC_EN_MNG2HOST;
2290
2291                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2292         }
2293 }
2294
2295 static void
2296 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2297 {
2298         struct e1000_hw *hw =
2299                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300         uint32_t rctl;
2301
2302         rctl = E1000_READ_REG(hw, E1000_RCTL);
2303         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2304         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2305 }
2306
2307 static void
2308 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2309 {
2310         struct e1000_hw *hw =
2311                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2312         uint32_t rctl;
2313
2314         rctl = E1000_READ_REG(hw, E1000_RCTL);
2315         rctl &= (~E1000_RCTL_UPE);
2316         if (dev->data->all_multicast == 1)
2317                 rctl |= E1000_RCTL_MPE;
2318         else
2319                 rctl &= (~E1000_RCTL_MPE);
2320         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2321 }
2322
2323 static void
2324 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2325 {
2326         struct e1000_hw *hw =
2327                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328         uint32_t rctl;
2329
2330         rctl = E1000_READ_REG(hw, E1000_RCTL);
2331         rctl |= E1000_RCTL_MPE;
2332         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2333 }
2334
2335 static void
2336 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2337 {
2338         struct e1000_hw *hw =
2339                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340         uint32_t rctl;
2341
2342         if (dev->data->promiscuous == 1)
2343                 return; /* must remain in all_multicast mode */
2344         rctl = E1000_READ_REG(hw, E1000_RCTL);
2345         rctl &= (~E1000_RCTL_MPE);
2346         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2347 }
2348
2349 static int
2350 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2351 {
2352         struct e1000_hw *hw =
2353                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         struct e1000_vfta * shadow_vfta =
2355                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2356         uint32_t vfta;
2357         uint32_t vid_idx;
2358         uint32_t vid_bit;
2359
2360         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2361                               E1000_VFTA_ENTRY_MASK);
2362         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2363         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2364         if (on)
2365                 vfta |= vid_bit;
2366         else
2367                 vfta &= ~vid_bit;
2368         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2369
2370         /* update local VFTA copy */
2371         shadow_vfta->vfta[vid_idx] = vfta;
2372
2373         return 0;
2374 }
2375
2376 static int
2377 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2378                       enum rte_vlan_type vlan_type,
2379                       uint16_t tpid)
2380 {
2381         struct e1000_hw *hw =
2382                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383         uint32_t reg, qinq;
2384
2385         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2386         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2387
2388         /* only outer TPID of double VLAN can be configured*/
2389         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2390                 reg = E1000_READ_REG(hw, E1000_VET);
2391                 reg = (reg & (~E1000_VET_VET_EXT)) |
2392                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2393                 E1000_WRITE_REG(hw, E1000_VET, reg);
2394
2395                 return 0;
2396         }
2397
2398         /* all other TPID values are read-only*/
2399         PMD_DRV_LOG(ERR, "Not supported");
2400
2401         return -ENOTSUP;
2402 }
2403
2404 static void
2405 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2406 {
2407         struct e1000_hw *hw =
2408                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409         uint32_t reg;
2410
2411         /* Filter Table Disable */
2412         reg = E1000_READ_REG(hw, E1000_RCTL);
2413         reg &= ~E1000_RCTL_CFIEN;
2414         reg &= ~E1000_RCTL_VFE;
2415         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2416 }
2417
2418 static void
2419 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2420 {
2421         struct e1000_hw *hw =
2422                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         struct e1000_vfta * shadow_vfta =
2424                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2425         uint32_t reg;
2426         int i;
2427
2428         /* Filter Table Enable, CFI not used for packet acceptance */
2429         reg = E1000_READ_REG(hw, E1000_RCTL);
2430         reg &= ~E1000_RCTL_CFIEN;
2431         reg |= E1000_RCTL_VFE;
2432         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2433
2434         /* restore VFTA table */
2435         for (i = 0; i < IGB_VFTA_SIZE; i++)
2436                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2437 }
2438
2439 static void
2440 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2441 {
2442         struct e1000_hw *hw =
2443                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444         uint32_t reg;
2445
2446         /* VLAN Mode Disable */
2447         reg = E1000_READ_REG(hw, E1000_CTRL);
2448         reg &= ~E1000_CTRL_VME;
2449         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2450 }
2451
2452 static void
2453 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2454 {
2455         struct e1000_hw *hw =
2456                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457         uint32_t reg;
2458
2459         /* VLAN Mode Enable */
2460         reg = E1000_READ_REG(hw, E1000_CTRL);
2461         reg |= E1000_CTRL_VME;
2462         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2463 }
2464
2465 static void
2466 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2467 {
2468         struct e1000_hw *hw =
2469                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2470         uint32_t reg;
2471
2472         /* CTRL_EXT: Extended VLAN */
2473         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2474         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2475         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2476
2477         /* Update maximum packet length */
2478         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2479                 E1000_WRITE_REG(hw, E1000_RLPML,
2480                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2481                                                 VLAN_TAG_SIZE);
2482 }
2483
2484 static void
2485 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2486 {
2487         struct e1000_hw *hw =
2488                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489         uint32_t reg;
2490
2491         /* CTRL_EXT: Extended VLAN */
2492         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2493         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2494         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2495
2496         /* Update maximum packet length */
2497         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2498                 E1000_WRITE_REG(hw, E1000_RLPML,
2499                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2500                                                 2 * VLAN_TAG_SIZE);
2501 }
2502
2503 static void
2504 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2505 {
2506         if(mask & ETH_VLAN_STRIP_MASK){
2507                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2508                         igb_vlan_hw_strip_enable(dev);
2509                 else
2510                         igb_vlan_hw_strip_disable(dev);
2511         }
2512
2513         if(mask & ETH_VLAN_FILTER_MASK){
2514                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2515                         igb_vlan_hw_filter_enable(dev);
2516                 else
2517                         igb_vlan_hw_filter_disable(dev);
2518         }
2519
2520         if(mask & ETH_VLAN_EXTEND_MASK){
2521                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2522                         igb_vlan_hw_extend_enable(dev);
2523                 else
2524                         igb_vlan_hw_extend_disable(dev);
2525         }
2526 }
2527
2528
2529 /**
2530  * It enables the interrupt mask and then enable the interrupt.
2531  *
2532  * @param dev
2533  *  Pointer to struct rte_eth_dev.
2534  *
2535  * @return
2536  *  - On success, zero.
2537  *  - On failure, a negative value.
2538  */
2539 static int
2540 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2541 {
2542         struct e1000_interrupt *intr =
2543                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2544
2545         intr->mask |= E1000_ICR_LSC;
2546
2547         return 0;
2548 }
2549
2550 /* It clears the interrupt causes and enables the interrupt.
2551  * It will be called once only during nic initialized.
2552  *
2553  * @param dev
2554  *  Pointer to struct rte_eth_dev.
2555  *
2556  * @return
2557  *  - On success, zero.
2558  *  - On failure, a negative value.
2559  */
2560 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2561 {
2562         uint32_t mask, regval;
2563         struct e1000_hw *hw =
2564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565         struct rte_eth_dev_info dev_info;
2566
2567         memset(&dev_info, 0, sizeof(dev_info));
2568         eth_igb_infos_get(dev, &dev_info);
2569
2570         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2571         regval = E1000_READ_REG(hw, E1000_EIMS);
2572         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2573
2574         return 0;
2575 }
2576
2577 /*
2578  * It reads ICR and gets interrupt causes, check it and set a bit flag
2579  * to update link status.
2580  *
2581  * @param dev
2582  *  Pointer to struct rte_eth_dev.
2583  *
2584  * @return
2585  *  - On success, zero.
2586  *  - On failure, a negative value.
2587  */
2588 static int
2589 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2590 {
2591         uint32_t icr;
2592         struct e1000_hw *hw =
2593                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2594         struct e1000_interrupt *intr =
2595                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2596
2597         igb_intr_disable(hw);
2598
2599         /* read-on-clear nic registers here */
2600         icr = E1000_READ_REG(hw, E1000_ICR);
2601
2602         intr->flags = 0;
2603         if (icr & E1000_ICR_LSC) {
2604                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2605         }
2606
2607         if (icr & E1000_ICR_VMMB)
2608                 intr->flags |= E1000_FLAG_MAILBOX;
2609
2610         return 0;
2611 }
2612
2613 /*
2614  * It executes link_update after knowing an interrupt is prsent.
2615  *
2616  * @param dev
2617  *  Pointer to struct rte_eth_dev.
2618  *
2619  * @return
2620  *  - On success, zero.
2621  *  - On failure, a negative value.
2622  */
2623 static int
2624 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2625 {
2626         struct e1000_hw *hw =
2627                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628         struct e1000_interrupt *intr =
2629                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2630         uint32_t tctl, rctl;
2631         struct rte_eth_link link;
2632         int ret;
2633
2634         if (intr->flags & E1000_FLAG_MAILBOX) {
2635                 igb_pf_mbx_process(dev);
2636                 intr->flags &= ~E1000_FLAG_MAILBOX;
2637         }
2638
2639         igb_intr_enable(dev);
2640         rte_intr_enable(&(dev->pci_dev->intr_handle));
2641
2642         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2643                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2644
2645                 /* set get_link_status to check register later */
2646                 hw->mac.get_link_status = 1;
2647                 ret = eth_igb_link_update(dev, 0);
2648
2649                 /* check if link has changed */
2650                 if (ret < 0)
2651                         return 0;
2652
2653                 memset(&link, 0, sizeof(link));
2654                 rte_igb_dev_atomic_read_link_status(dev, &link);
2655                 if (link.link_status) {
2656                         PMD_INIT_LOG(INFO,
2657                                      " Port %d: Link Up - speed %u Mbps - %s",
2658                                      dev->data->port_id,
2659                                      (unsigned)link.link_speed,
2660                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2661                                      "full-duplex" : "half-duplex");
2662                 } else {
2663                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2664                                      dev->data->port_id);
2665                 }
2666
2667                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2668                              dev->pci_dev->addr.domain,
2669                              dev->pci_dev->addr.bus,
2670                              dev->pci_dev->addr.devid,
2671                              dev->pci_dev->addr.function);
2672                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2673                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2674                 if (link.link_status) {
2675                         /* enable Tx/Rx */
2676                         tctl |= E1000_TCTL_EN;
2677                         rctl |= E1000_RCTL_EN;
2678                 } else {
2679                         /* disable Tx/Rx */
2680                         tctl &= ~E1000_TCTL_EN;
2681                         rctl &= ~E1000_RCTL_EN;
2682                 }
2683                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2684                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2685                 E1000_WRITE_FLUSH(hw);
2686                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2687         }
2688
2689         return 0;
2690 }
2691
2692 /**
2693  * Interrupt handler which shall be registered at first.
2694  *
2695  * @param handle
2696  *  Pointer to interrupt handle.
2697  * @param param
2698  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2699  *
2700  * @return
2701  *  void
2702  */
2703 static void
2704 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2705                                                         void *param)
2706 {
2707         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2708
2709         eth_igb_interrupt_get_status(dev);
2710         eth_igb_interrupt_action(dev);
2711 }
2712
2713 static int
2714 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2715 {
2716         uint32_t eicr;
2717         struct e1000_hw *hw =
2718                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2719         struct e1000_interrupt *intr =
2720                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2721
2722         igbvf_intr_disable(hw);
2723
2724         /* read-on-clear nic registers here */
2725         eicr = E1000_READ_REG(hw, E1000_EICR);
2726         intr->flags = 0;
2727
2728         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2729                 intr->flags |= E1000_FLAG_MAILBOX;
2730
2731         return 0;
2732 }
2733
2734 void igbvf_mbx_process(struct rte_eth_dev *dev)
2735 {
2736         struct e1000_hw *hw =
2737                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738         struct e1000_mbx_info *mbx = &hw->mbx;
2739         u32 in_msg = 0;
2740
2741         if (mbx->ops.read(hw, &in_msg, 1, 0))
2742                 return;
2743
2744         /* PF reset VF event */
2745         if (in_msg == E1000_PF_CONTROL_MSG)
2746                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
2747 }
2748
2749 static int
2750 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2751 {
2752         struct e1000_interrupt *intr =
2753                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2754
2755         if (intr->flags & E1000_FLAG_MAILBOX) {
2756                 igbvf_mbx_process(dev);
2757                 intr->flags &= ~E1000_FLAG_MAILBOX;
2758         }
2759
2760         igbvf_intr_enable(dev);
2761         rte_intr_enable(&dev->pci_dev->intr_handle);
2762
2763         return 0;
2764 }
2765
2766 static void
2767 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2768                             void *param)
2769 {
2770         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2771
2772         eth_igbvf_interrupt_get_status(dev);
2773         eth_igbvf_interrupt_action(dev);
2774 }
2775
2776 static int
2777 eth_igb_led_on(struct rte_eth_dev *dev)
2778 {
2779         struct e1000_hw *hw;
2780
2781         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2783 }
2784
2785 static int
2786 eth_igb_led_off(struct rte_eth_dev *dev)
2787 {
2788         struct e1000_hw *hw;
2789
2790         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2792 }
2793
2794 static int
2795 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2796 {
2797         struct e1000_hw *hw;
2798         uint32_t ctrl;
2799         int tx_pause;
2800         int rx_pause;
2801
2802         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803         fc_conf->pause_time = hw->fc.pause_time;
2804         fc_conf->high_water = hw->fc.high_water;
2805         fc_conf->low_water = hw->fc.low_water;
2806         fc_conf->send_xon = hw->fc.send_xon;
2807         fc_conf->autoneg = hw->mac.autoneg;
2808
2809         /*
2810          * Return rx_pause and tx_pause status according to actual setting of
2811          * the TFCE and RFCE bits in the CTRL register.
2812          */
2813         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2814         if (ctrl & E1000_CTRL_TFCE)
2815                 tx_pause = 1;
2816         else
2817                 tx_pause = 0;
2818
2819         if (ctrl & E1000_CTRL_RFCE)
2820                 rx_pause = 1;
2821         else
2822                 rx_pause = 0;
2823
2824         if (rx_pause && tx_pause)
2825                 fc_conf->mode = RTE_FC_FULL;
2826         else if (rx_pause)
2827                 fc_conf->mode = RTE_FC_RX_PAUSE;
2828         else if (tx_pause)
2829                 fc_conf->mode = RTE_FC_TX_PAUSE;
2830         else
2831                 fc_conf->mode = RTE_FC_NONE;
2832
2833         return 0;
2834 }
2835
2836 static int
2837 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2838 {
2839         struct e1000_hw *hw;
2840         int err;
2841         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2842                 e1000_fc_none,
2843                 e1000_fc_rx_pause,
2844                 e1000_fc_tx_pause,
2845                 e1000_fc_full
2846         };
2847         uint32_t rx_buf_size;
2848         uint32_t max_high_water;
2849         uint32_t rctl;
2850
2851         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2852         if (fc_conf->autoneg != hw->mac.autoneg)
2853                 return -ENOTSUP;
2854         rx_buf_size = igb_get_rx_buffer_size(hw);
2855         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2856
2857         /* At least reserve one Ethernet frame for watermark */
2858         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2859         if ((fc_conf->high_water > max_high_water) ||
2860             (fc_conf->high_water < fc_conf->low_water)) {
2861                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2862                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2863                 return -EINVAL;
2864         }
2865
2866         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2867         hw->fc.pause_time     = fc_conf->pause_time;
2868         hw->fc.high_water     = fc_conf->high_water;
2869         hw->fc.low_water      = fc_conf->low_water;
2870         hw->fc.send_xon       = fc_conf->send_xon;
2871
2872         err = e1000_setup_link_generic(hw);
2873         if (err == E1000_SUCCESS) {
2874
2875                 /* check if we want to forward MAC frames - driver doesn't have native
2876                  * capability to do that, so we'll write the registers ourselves */
2877
2878                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2879
2880                 /* set or clear MFLCN.PMCF bit depending on configuration */
2881                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2882                         rctl |= E1000_RCTL_PMCF;
2883                 else
2884                         rctl &= ~E1000_RCTL_PMCF;
2885
2886                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2887                 E1000_WRITE_FLUSH(hw);
2888
2889                 return 0;
2890         }
2891
2892         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2893         return -EIO;
2894 }
2895
2896 #define E1000_RAH_POOLSEL_SHIFT      (18)
2897 static void
2898 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2899                 uint32_t index, __rte_unused uint32_t pool)
2900 {
2901         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2902         uint32_t rah;
2903
2904         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2905         rah = E1000_READ_REG(hw, E1000_RAH(index));
2906         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2907         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2908 }
2909
2910 static void
2911 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2912 {
2913         uint8_t addr[ETHER_ADDR_LEN];
2914         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2915
2916         memset(addr, 0, sizeof(addr));
2917
2918         e1000_rar_set(hw, addr, index);
2919 }
2920
2921 static void
2922 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2923                                 struct ether_addr *addr)
2924 {
2925         eth_igb_rar_clear(dev, 0);
2926
2927         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2928 }
2929 /*
2930  * Virtual Function operations
2931  */
2932 static void
2933 igbvf_intr_disable(struct e1000_hw *hw)
2934 {
2935         PMD_INIT_FUNC_TRACE();
2936
2937         /* Clear interrupt mask to stop from interrupts being generated */
2938         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2939
2940         E1000_WRITE_FLUSH(hw);
2941 }
2942
2943 static void
2944 igbvf_stop_adapter(struct rte_eth_dev *dev)
2945 {
2946         u32 reg_val;
2947         u16 i;
2948         struct rte_eth_dev_info dev_info;
2949         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2950
2951         memset(&dev_info, 0, sizeof(dev_info));
2952         eth_igbvf_infos_get(dev, &dev_info);
2953
2954         /* Clear interrupt mask to stop from interrupts being generated */
2955         igbvf_intr_disable(hw);
2956
2957         /* Clear any pending interrupts, flush previous writes */
2958         E1000_READ_REG(hw, E1000_EICR);
2959
2960         /* Disable the transmit unit.  Each queue must be disabled. */
2961         for (i = 0; i < dev_info.max_tx_queues; i++)
2962                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2963
2964         /* Disable the receive unit by stopping each queue */
2965         for (i = 0; i < dev_info.max_rx_queues; i++) {
2966                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2967                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2968                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2969                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2970                         ;
2971         }
2972
2973         /* flush all queues disables */
2974         E1000_WRITE_FLUSH(hw);
2975         msec_delay(2);
2976 }
2977
2978 static int eth_igbvf_link_update(struct e1000_hw *hw)
2979 {
2980         struct e1000_mbx_info *mbx = &hw->mbx;
2981         struct e1000_mac_info *mac = &hw->mac;
2982         int ret_val = E1000_SUCCESS;
2983
2984         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2985
2986         /*
2987          * We only want to run this if there has been a rst asserted.
2988          * in this case that could mean a link change, device reset,
2989          * or a virtual function reset
2990          */
2991
2992         /* If we were hit with a reset or timeout drop the link */
2993         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2994                 mac->get_link_status = TRUE;
2995
2996         if (!mac->get_link_status)
2997                 goto out;
2998
2999         /* if link status is down no point in checking to see if pf is up */
3000         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3001                 goto out;
3002
3003         /* if we passed all the tests above then the link is up and we no
3004          * longer need to check for link */
3005         mac->get_link_status = FALSE;
3006
3007 out:
3008         return ret_val;
3009 }
3010
3011
3012 static int
3013 igbvf_dev_configure(struct rte_eth_dev *dev)
3014 {
3015         struct rte_eth_conf* conf = &dev->data->dev_conf;
3016
3017         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3018                      dev->data->port_id);
3019
3020         /*
3021          * VF has no ability to enable/disable HW CRC
3022          * Keep the persistent behavior the same as Host PF
3023          */
3024 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3025         if (!conf->rxmode.hw_strip_crc) {
3026                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3027                 conf->rxmode.hw_strip_crc = 1;
3028         }
3029 #else
3030         if (conf->rxmode.hw_strip_crc) {
3031                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3032                 conf->rxmode.hw_strip_crc = 0;
3033         }
3034 #endif
3035
3036         return 0;
3037 }
3038
3039 static int
3040 igbvf_dev_start(struct rte_eth_dev *dev)
3041 {
3042         struct e1000_hw *hw =
3043                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3044         struct e1000_adapter *adapter =
3045                 E1000_DEV_PRIVATE(dev->data->dev_private);
3046         int ret;
3047         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3048         uint32_t intr_vector = 0;
3049
3050         PMD_INIT_FUNC_TRACE();
3051
3052         hw->mac.ops.reset_hw(hw);
3053         adapter->stopped = 0;
3054
3055         /* Set all vfta */
3056         igbvf_set_vfta_all(dev,1);
3057
3058         eth_igbvf_tx_init(dev);
3059
3060         /* This can fail when allocating mbufs for descriptor rings */
3061         ret = eth_igbvf_rx_init(dev);
3062         if (ret) {
3063                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3064                 igb_dev_clear_queues(dev);
3065                 return ret;
3066         }
3067
3068         /* check and configure queue intr-vector mapping */
3069         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3070                 intr_vector = dev->data->nb_rx_queues;
3071                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3072                 if (ret)
3073                         return ret;
3074         }
3075
3076         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3077                 intr_handle->intr_vec =
3078                         rte_zmalloc("intr_vec",
3079                                     dev->data->nb_rx_queues * sizeof(int), 0);
3080                 if (!intr_handle->intr_vec) {
3081                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3082                                      " intr_vec\n", dev->data->nb_rx_queues);
3083                         return -ENOMEM;
3084                 }
3085         }
3086
3087         eth_igbvf_configure_msix_intr(dev);
3088
3089         /* enable uio/vfio intr/eventfd mapping */
3090         rte_intr_enable(intr_handle);
3091
3092         /* resume enabled intr since hw reset */
3093         igbvf_intr_enable(dev);
3094
3095         return 0;
3096 }
3097
3098 static void
3099 igbvf_dev_stop(struct rte_eth_dev *dev)
3100 {
3101         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3102
3103         PMD_INIT_FUNC_TRACE();
3104
3105         igbvf_stop_adapter(dev);
3106
3107         /*
3108           * Clear what we set, but we still keep shadow_vfta to
3109           * restore after device starts
3110           */
3111         igbvf_set_vfta_all(dev,0);
3112
3113         igb_dev_clear_queues(dev);
3114
3115         /* disable intr eventfd mapping */
3116         rte_intr_disable(intr_handle);
3117
3118         /* Clean datapath event and queue/vec mapping */
3119         rte_intr_efd_disable(intr_handle);
3120         if (intr_handle->intr_vec) {
3121                 rte_free(intr_handle->intr_vec);
3122                 intr_handle->intr_vec = NULL;
3123         }
3124 }
3125
3126 static void
3127 igbvf_dev_close(struct rte_eth_dev *dev)
3128 {
3129         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130         struct e1000_adapter *adapter =
3131                 E1000_DEV_PRIVATE(dev->data->dev_private);
3132         struct ether_addr addr;
3133
3134         PMD_INIT_FUNC_TRACE();
3135
3136         e1000_reset_hw(hw);
3137
3138         igbvf_dev_stop(dev);
3139         adapter->stopped = 1;
3140         igb_dev_free_queues(dev);
3141
3142         /**
3143          * reprogram the RAR with a zero mac address,
3144          * to ensure that the VF traffic goes to the PF
3145          * after stop, close and detach of the VF.
3146          **/
3147
3148         memset(&addr, 0, sizeof(addr));
3149         igbvf_default_mac_addr_set(dev, &addr);
3150 }
3151
3152 static void
3153 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3154 {
3155         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3156
3157         /* Set both unicast and multicast promisc */
3158         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3159 }
3160
3161 static void
3162 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3163 {
3164         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3165
3166         /* If in allmulticast mode leave multicast promisc */
3167         if (dev->data->all_multicast == 1)
3168                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3169         else
3170                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3171 }
3172
3173 static void
3174 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3175 {
3176         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3177
3178         /* In promiscuous mode multicast promisc already set */
3179         if (dev->data->promiscuous == 0)
3180                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3181 }
3182
3183 static void
3184 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3185 {
3186         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3187
3188         /* In promiscuous mode leave multicast promisc enabled */
3189         if (dev->data->promiscuous == 0)
3190                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3191 }
3192
3193 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3194 {
3195         struct e1000_mbx_info *mbx = &hw->mbx;
3196         uint32_t msgbuf[2];
3197         s32 err;
3198
3199         /* After set vlan, vlan strip will also be enabled in igb driver*/
3200         msgbuf[0] = E1000_VF_SET_VLAN;
3201         msgbuf[1] = vid;
3202         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3203         if (on)
3204                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3205
3206         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3207         if (err)
3208                 goto mbx_err;
3209
3210         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3211         if (err)
3212                 goto mbx_err;
3213
3214         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3215         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3216                 err = -EINVAL;
3217
3218 mbx_err:
3219         return err;
3220 }
3221
3222 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3223 {
3224         struct e1000_hw *hw =
3225                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3226         struct e1000_vfta * shadow_vfta =
3227                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3228         int i = 0, j = 0, vfta = 0, mask = 1;
3229
3230         for (i = 0; i < IGB_VFTA_SIZE; i++){
3231                 vfta = shadow_vfta->vfta[i];
3232                 if(vfta){
3233                         mask = 1;
3234                         for (j = 0; j < 32; j++){
3235                                 if(vfta & mask)
3236                                         igbvf_set_vfta(hw,
3237                                                 (uint16_t)((i<<5)+j), on);
3238                                 mask<<=1;
3239                         }
3240                 }
3241         }
3242
3243 }
3244
3245 static int
3246 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3247 {
3248         struct e1000_hw *hw =
3249                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3250         struct e1000_vfta * shadow_vfta =
3251                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3252         uint32_t vid_idx = 0;
3253         uint32_t vid_bit = 0;
3254         int ret = 0;
3255
3256         PMD_INIT_FUNC_TRACE();
3257
3258         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3259         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3260         if(ret){
3261                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3262                 return ret;
3263         }
3264         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3265         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3266
3267         /*Save what we set and retore it after device reset*/
3268         if (on)
3269                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3270         else
3271                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3272
3273         return 0;
3274 }
3275
3276 static void
3277 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3278 {
3279         struct e1000_hw *hw =
3280                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281
3282         /* index is not used by rar_set() */
3283         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3284 }
3285
3286
3287 static int
3288 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3289                         struct rte_eth_rss_reta_entry64 *reta_conf,
3290                         uint16_t reta_size)
3291 {
3292         uint8_t i, j, mask;
3293         uint32_t reta, r;
3294         uint16_t idx, shift;
3295         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296
3297         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3298                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3299                         "(%d) doesn't match the number hardware can supported "
3300                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3301                 return -EINVAL;
3302         }
3303
3304         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3305                 idx = i / RTE_RETA_GROUP_SIZE;
3306                 shift = i % RTE_RETA_GROUP_SIZE;
3307                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3308                                                 IGB_4_BIT_MASK);
3309                 if (!mask)
3310                         continue;
3311                 if (mask == IGB_4_BIT_MASK)
3312                         r = 0;
3313                 else
3314                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3315                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3316                         if (mask & (0x1 << j))
3317                                 reta |= reta_conf[idx].reta[shift + j] <<
3318                                                         (CHAR_BIT * j);
3319                         else
3320                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3321                 }
3322                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3323         }
3324
3325         return 0;
3326 }
3327
3328 static int
3329 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3330                        struct rte_eth_rss_reta_entry64 *reta_conf,
3331                        uint16_t reta_size)
3332 {
3333         uint8_t i, j, mask;
3334         uint32_t reta;
3335         uint16_t idx, shift;
3336         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337
3338         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3339                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3340                         "(%d) doesn't match the number hardware can supported "
3341                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3342                 return -EINVAL;
3343         }
3344
3345         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3346                 idx = i / RTE_RETA_GROUP_SIZE;
3347                 shift = i % RTE_RETA_GROUP_SIZE;
3348                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3349                                                 IGB_4_BIT_MASK);
3350                 if (!mask)
3351                         continue;
3352                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3353                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3354                         if (mask & (0x1 << j))
3355                                 reta_conf[idx].reta[shift + j] =
3356                                         ((reta >> (CHAR_BIT * j)) &
3357                                                 IGB_8_BIT_MASK);
3358                 }
3359         }
3360
3361         return 0;
3362 }
3363
3364 #define MAC_TYPE_FILTER_SUP(type)    do {\
3365         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3366                 (type) != e1000_82576)\
3367                 return -ENOTSUP;\
3368 } while (0)
3369
3370 static int
3371 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3372                         struct rte_eth_syn_filter *filter,
3373                         bool add)
3374 {
3375         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3376         uint32_t synqf, rfctl;
3377
3378         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3379                 return -EINVAL;
3380
3381         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3382
3383         if (add) {
3384                 if (synqf & E1000_SYN_FILTER_ENABLE)
3385                         return -EINVAL;
3386
3387                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3388                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3389
3390                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3391                 if (filter->hig_pri)
3392                         rfctl |= E1000_RFCTL_SYNQFP;
3393                 else
3394                         rfctl &= ~E1000_RFCTL_SYNQFP;
3395
3396                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3397         } else {
3398                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3399                         return -ENOENT;
3400                 synqf = 0;
3401         }
3402
3403         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3404         E1000_WRITE_FLUSH(hw);
3405         return 0;
3406 }
3407
3408 static int
3409 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3410                         struct rte_eth_syn_filter *filter)
3411 {
3412         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3413         uint32_t synqf, rfctl;
3414
3415         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3416         if (synqf & E1000_SYN_FILTER_ENABLE) {
3417                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3418                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3419                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3420                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3421                 return 0;
3422         }
3423
3424         return -ENOENT;
3425 }
3426
3427 static int
3428 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3429                         enum rte_filter_op filter_op,
3430                         void *arg)
3431 {
3432         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3433         int ret;
3434
3435         MAC_TYPE_FILTER_SUP(hw->mac.type);
3436
3437         if (filter_op == RTE_ETH_FILTER_NOP)
3438                 return 0;
3439
3440         if (arg == NULL) {
3441                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3442                             filter_op);
3443                 return -EINVAL;
3444         }
3445
3446         switch (filter_op) {
3447         case RTE_ETH_FILTER_ADD:
3448                 ret = eth_igb_syn_filter_set(dev,
3449                                 (struct rte_eth_syn_filter *)arg,
3450                                 TRUE);
3451                 break;
3452         case RTE_ETH_FILTER_DELETE:
3453                 ret = eth_igb_syn_filter_set(dev,
3454                                 (struct rte_eth_syn_filter *)arg,
3455                                 FALSE);
3456                 break;
3457         case RTE_ETH_FILTER_GET:
3458                 ret = eth_igb_syn_filter_get(dev,
3459                                 (struct rte_eth_syn_filter *)arg);
3460                 break;
3461         default:
3462                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3463                 ret = -EINVAL;
3464                 break;
3465         }
3466
3467         return ret;
3468 }
3469
3470 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3471         if ((type) != e1000_82580 && (type) != e1000_i350)\
3472                 return -ENOSYS; \
3473 } while (0)
3474
3475 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3476 static inline int
3477 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3478                         struct e1000_2tuple_filter_info *filter_info)
3479 {
3480         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3481                 return -EINVAL;
3482         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3483                 return -EINVAL;  /* filter index is out of range. */
3484         if (filter->tcp_flags > TCP_FLAG_ALL)
3485                 return -EINVAL;  /* flags is invalid. */
3486
3487         switch (filter->dst_port_mask) {
3488         case UINT16_MAX:
3489                 filter_info->dst_port_mask = 0;
3490                 filter_info->dst_port = filter->dst_port;
3491                 break;
3492         case 0:
3493                 filter_info->dst_port_mask = 1;
3494                 break;
3495         default:
3496                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3497                 return -EINVAL;
3498         }
3499
3500         switch (filter->proto_mask) {
3501         case UINT8_MAX:
3502                 filter_info->proto_mask = 0;
3503                 filter_info->proto = filter->proto;
3504                 break;
3505         case 0:
3506                 filter_info->proto_mask = 1;
3507                 break;
3508         default:
3509                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3510                 return -EINVAL;
3511         }
3512
3513         filter_info->priority = (uint8_t)filter->priority;
3514         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3515                 filter_info->tcp_flags = filter->tcp_flags;
3516         else
3517                 filter_info->tcp_flags = 0;
3518
3519         return 0;
3520 }
3521
3522 static inline struct e1000_2tuple_filter *
3523 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3524                         struct e1000_2tuple_filter_info *key)
3525 {
3526         struct e1000_2tuple_filter *it;
3527
3528         TAILQ_FOREACH(it, filter_list, entries) {
3529                 if (memcmp(key, &it->filter_info,
3530                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3531                         return it;
3532                 }
3533         }
3534         return NULL;
3535 }
3536
3537 /*
3538  * igb_add_2tuple_filter - add a 2tuple filter
3539  *
3540  * @param
3541  * dev: Pointer to struct rte_eth_dev.
3542  * ntuple_filter: ponter to the filter that will be added.
3543  *
3544  * @return
3545  *    - On success, zero.
3546  *    - On failure, a negative value.
3547  */
3548 static int
3549 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3550                         struct rte_eth_ntuple_filter *ntuple_filter)
3551 {
3552         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3553         struct e1000_filter_info *filter_info =
3554                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3555         struct e1000_2tuple_filter *filter;
3556         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3557         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3558         int i, ret;
3559
3560         filter = rte_zmalloc("e1000_2tuple_filter",
3561                         sizeof(struct e1000_2tuple_filter), 0);
3562         if (filter == NULL)
3563                 return -ENOMEM;
3564
3565         ret = ntuple_filter_to_2tuple(ntuple_filter,
3566                                       &filter->filter_info);
3567         if (ret < 0) {
3568                 rte_free(filter);
3569                 return ret;
3570         }
3571         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3572                                          &filter->filter_info) != NULL) {
3573                 PMD_DRV_LOG(ERR, "filter exists.");
3574                 rte_free(filter);
3575                 return -EEXIST;
3576         }
3577         filter->queue = ntuple_filter->queue;
3578
3579         /*
3580          * look for an unused 2tuple filter index,
3581          * and insert the filter to list.
3582          */
3583         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3584                 if (!(filter_info->twotuple_mask & (1 << i))) {
3585                         filter_info->twotuple_mask |= 1 << i;
3586                         filter->index = i;
3587                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3588                                           filter,
3589                                           entries);
3590                         break;
3591                 }
3592         }
3593         if (i >= E1000_MAX_TTQF_FILTERS) {
3594                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3595                 rte_free(filter);
3596                 return -ENOSYS;
3597         }
3598
3599         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3600         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3601                 imir |= E1000_IMIR_PORT_BP;
3602         else
3603                 imir &= ~E1000_IMIR_PORT_BP;
3604
3605         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3606
3607         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3608         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3609         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3610         if (filter->filter_info.proto_mask == 0)
3611                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3612
3613         /* tcp flags bits setting. */
3614         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3615                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3616                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3617                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3618                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3619                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3620                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3621                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3622                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3623                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3624                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3625                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3626                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3627         } else
3628                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3629         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3630         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3631         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3632         return 0;
3633 }
3634
3635 /*
3636  * igb_remove_2tuple_filter - remove a 2tuple filter
3637  *
3638  * @param
3639  * dev: Pointer to struct rte_eth_dev.
3640  * ntuple_filter: ponter to the filter that will be removed.
3641  *
3642  * @return
3643  *    - On success, zero.
3644  *    - On failure, a negative value.
3645  */
3646 static int
3647 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3648                         struct rte_eth_ntuple_filter *ntuple_filter)
3649 {
3650         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3651         struct e1000_filter_info *filter_info =
3652                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3653         struct e1000_2tuple_filter_info filter_2tuple;
3654         struct e1000_2tuple_filter *filter;
3655         int ret;
3656
3657         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3658         ret = ntuple_filter_to_2tuple(ntuple_filter,
3659                                       &filter_2tuple);
3660         if (ret < 0)
3661                 return ret;
3662
3663         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3664                                          &filter_2tuple);
3665         if (filter == NULL) {
3666                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3667                 return -ENOENT;
3668         }
3669
3670         filter_info->twotuple_mask &= ~(1 << filter->index);
3671         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3672         rte_free(filter);
3673
3674         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3675         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3676         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3677         return 0;
3678 }
3679
3680 static inline struct e1000_flex_filter *
3681 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3682                         struct e1000_flex_filter_info *key)
3683 {
3684         struct e1000_flex_filter *it;
3685
3686         TAILQ_FOREACH(it, filter_list, entries) {
3687                 if (memcmp(key, &it->filter_info,
3688                         sizeof(struct e1000_flex_filter_info)) == 0)
3689                         return it;
3690         }
3691
3692         return NULL;
3693 }
3694
3695 static int
3696 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3697                         struct rte_eth_flex_filter *filter,
3698                         bool add)
3699 {
3700         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3701         struct e1000_filter_info *filter_info =
3702                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3703         struct e1000_flex_filter *flex_filter, *it;
3704         uint32_t wufc, queueing, mask;
3705         uint32_t reg_off;
3706         uint8_t shift, i, j = 0;
3707
3708         flex_filter = rte_zmalloc("e1000_flex_filter",
3709                         sizeof(struct e1000_flex_filter), 0);
3710         if (flex_filter == NULL)
3711                 return -ENOMEM;
3712
3713         flex_filter->filter_info.len = filter->len;
3714         flex_filter->filter_info.priority = filter->priority;
3715         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3716         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3717                 mask = 0;
3718                 /* reverse bits in flex filter's mask*/
3719                 for (shift = 0; shift < CHAR_BIT; shift++) {
3720                         if (filter->mask[i] & (0x01 << shift))
3721                                 mask |= (0x80 >> shift);
3722                 }
3723                 flex_filter->filter_info.mask[i] = mask;
3724         }
3725
3726         wufc = E1000_READ_REG(hw, E1000_WUFC);
3727         if (flex_filter->index < E1000_MAX_FHFT)
3728                 reg_off = E1000_FHFT(flex_filter->index);
3729         else
3730                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3731
3732         if (add) {
3733                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3734                                 &flex_filter->filter_info) != NULL) {
3735                         PMD_DRV_LOG(ERR, "filter exists.");
3736                         rte_free(flex_filter);
3737                         return -EEXIST;
3738                 }
3739                 flex_filter->queue = filter->queue;
3740                 /*
3741                  * look for an unused flex filter index
3742                  * and insert the filter into the list.
3743                  */
3744                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3745                         if (!(filter_info->flex_mask & (1 << i))) {
3746                                 filter_info->flex_mask |= 1 << i;
3747                                 flex_filter->index = i;
3748                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3749                                         flex_filter,
3750                                         entries);
3751                                 break;
3752                         }
3753                 }
3754                 if (i >= E1000_MAX_FLEX_FILTERS) {
3755                         PMD_DRV_LOG(ERR, "flex filters are full.");
3756                         rte_free(flex_filter);
3757                         return -ENOSYS;
3758                 }
3759
3760                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3761                                 (E1000_WUFC_FLX0 << flex_filter->index));
3762                 queueing = filter->len |
3763                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3764                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3765                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3766                                 queueing);
3767                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3768                         E1000_WRITE_REG(hw, reg_off,
3769                                         flex_filter->filter_info.dwords[j]);
3770                         reg_off += sizeof(uint32_t);
3771                         E1000_WRITE_REG(hw, reg_off,
3772                                         flex_filter->filter_info.dwords[++j]);
3773                         reg_off += sizeof(uint32_t);
3774                         E1000_WRITE_REG(hw, reg_off,
3775                                 (uint32_t)flex_filter->filter_info.mask[i]);
3776                         reg_off += sizeof(uint32_t) * 2;
3777                         ++j;
3778                 }
3779         } else {
3780                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3781                                 &flex_filter->filter_info);
3782                 if (it == NULL) {
3783                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3784                         rte_free(flex_filter);
3785                         return -ENOENT;
3786                 }
3787
3788                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3789                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3790                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3791                         (~(E1000_WUFC_FLX0 << it->index)));
3792
3793                 filter_info->flex_mask &= ~(1 << it->index);
3794                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3795                 rte_free(it);
3796                 rte_free(flex_filter);
3797         }
3798
3799         return 0;
3800 }
3801
3802 static int
3803 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3804                         struct rte_eth_flex_filter *filter)
3805 {
3806         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807         struct e1000_filter_info *filter_info =
3808                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3809         struct e1000_flex_filter flex_filter, *it;
3810         uint32_t wufc, queueing, wufc_en = 0;
3811
3812         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3813         flex_filter.filter_info.len = filter->len;
3814         flex_filter.filter_info.priority = filter->priority;
3815         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3816         memcpy(flex_filter.filter_info.mask, filter->mask,
3817                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3818
3819         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3820                                 &flex_filter.filter_info);
3821         if (it == NULL) {
3822                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3823                 return -ENOENT;
3824         }
3825
3826         wufc = E1000_READ_REG(hw, E1000_WUFC);
3827         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3828
3829         if ((wufc & wufc_en) == wufc_en) {
3830                 uint32_t reg_off = 0;
3831                 if (it->index < E1000_MAX_FHFT)
3832                         reg_off = E1000_FHFT(it->index);
3833                 else
3834                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3835
3836                 queueing = E1000_READ_REG(hw,
3837                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3838                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3839                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3840                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3841                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3842                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3843                 return 0;
3844         }
3845         return -ENOENT;
3846 }
3847
3848 static int
3849 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3850                         enum rte_filter_op filter_op,
3851                         void *arg)
3852 {
3853         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3854         struct rte_eth_flex_filter *filter;
3855         int ret = 0;
3856
3857         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3858
3859         if (filter_op == RTE_ETH_FILTER_NOP)
3860                 return ret;
3861
3862         if (arg == NULL) {
3863                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3864                             filter_op);
3865                 return -EINVAL;
3866         }
3867
3868         filter = (struct rte_eth_flex_filter *)arg;
3869         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3870             || filter->len % sizeof(uint64_t) != 0) {
3871                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3872                 return -EINVAL;
3873         }
3874         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3875                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3876                 return -EINVAL;
3877         }
3878
3879         switch (filter_op) {
3880         case RTE_ETH_FILTER_ADD:
3881                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3882                 break;
3883         case RTE_ETH_FILTER_DELETE:
3884                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3885                 break;
3886         case RTE_ETH_FILTER_GET:
3887                 ret = eth_igb_get_flex_filter(dev, filter);
3888                 break;
3889         default:
3890                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3891                 ret = -EINVAL;
3892                 break;
3893         }
3894
3895         return ret;
3896 }
3897
3898 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3899 static inline int
3900 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3901                         struct e1000_5tuple_filter_info *filter_info)
3902 {
3903         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3904                 return -EINVAL;
3905         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3906                 return -EINVAL;  /* filter index is out of range. */
3907         if (filter->tcp_flags > TCP_FLAG_ALL)
3908                 return -EINVAL;  /* flags is invalid. */
3909
3910         switch (filter->dst_ip_mask) {
3911         case UINT32_MAX:
3912                 filter_info->dst_ip_mask = 0;
3913                 filter_info->dst_ip = filter->dst_ip;
3914                 break;
3915         case 0:
3916                 filter_info->dst_ip_mask = 1;
3917                 break;
3918         default:
3919                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3920                 return -EINVAL;
3921         }
3922
3923         switch (filter->src_ip_mask) {
3924         case UINT32_MAX:
3925                 filter_info->src_ip_mask = 0;
3926                 filter_info->src_ip = filter->src_ip;
3927                 break;
3928         case 0:
3929                 filter_info->src_ip_mask = 1;
3930                 break;
3931         default:
3932                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3933                 return -EINVAL;
3934         }
3935
3936         switch (filter->dst_port_mask) {
3937         case UINT16_MAX:
3938                 filter_info->dst_port_mask = 0;
3939                 filter_info->dst_port = filter->dst_port;
3940                 break;
3941         case 0:
3942                 filter_info->dst_port_mask = 1;
3943                 break;
3944         default:
3945                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3946                 return -EINVAL;
3947         }
3948
3949         switch (filter->src_port_mask) {
3950         case UINT16_MAX:
3951                 filter_info->src_port_mask = 0;
3952                 filter_info->src_port = filter->src_port;
3953                 break;
3954         case 0:
3955                 filter_info->src_port_mask = 1;
3956                 break;
3957         default:
3958                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3959                 return -EINVAL;
3960         }
3961
3962         switch (filter->proto_mask) {
3963         case UINT8_MAX:
3964                 filter_info->proto_mask = 0;
3965                 filter_info->proto = filter->proto;
3966                 break;
3967         case 0:
3968                 filter_info->proto_mask = 1;
3969                 break;
3970         default:
3971                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3972                 return -EINVAL;
3973         }
3974
3975         filter_info->priority = (uint8_t)filter->priority;
3976         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3977                 filter_info->tcp_flags = filter->tcp_flags;
3978         else
3979                 filter_info->tcp_flags = 0;
3980
3981         return 0;
3982 }
3983
3984 static inline struct e1000_5tuple_filter *
3985 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3986                         struct e1000_5tuple_filter_info *key)
3987 {
3988         struct e1000_5tuple_filter *it;
3989
3990         TAILQ_FOREACH(it, filter_list, entries) {
3991                 if (memcmp(key, &it->filter_info,
3992                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3993                         return it;
3994                 }
3995         }
3996         return NULL;
3997 }
3998
3999 /*
4000  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4001  *
4002  * @param
4003  * dev: Pointer to struct rte_eth_dev.
4004  * ntuple_filter: ponter to the filter that will be added.
4005  *
4006  * @return
4007  *    - On success, zero.
4008  *    - On failure, a negative value.
4009  */
4010 static int
4011 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4012                         struct rte_eth_ntuple_filter *ntuple_filter)
4013 {
4014         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015         struct e1000_filter_info *filter_info =
4016                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4017         struct e1000_5tuple_filter *filter;
4018         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4019         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4020         uint8_t i;
4021         int ret;
4022
4023         filter = rte_zmalloc("e1000_5tuple_filter",
4024                         sizeof(struct e1000_5tuple_filter), 0);
4025         if (filter == NULL)
4026                 return -ENOMEM;
4027
4028         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4029                                             &filter->filter_info);
4030         if (ret < 0) {
4031                 rte_free(filter);
4032                 return ret;
4033         }
4034
4035         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4036                                          &filter->filter_info) != NULL) {
4037                 PMD_DRV_LOG(ERR, "filter exists.");
4038                 rte_free(filter);
4039                 return -EEXIST;
4040         }
4041         filter->queue = ntuple_filter->queue;
4042
4043         /*
4044          * look for an unused 5tuple filter index,
4045          * and insert the filter to list.
4046          */
4047         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4048                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4049                         filter_info->fivetuple_mask |= 1 << i;
4050                         filter->index = i;
4051                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4052                                           filter,
4053                                           entries);
4054                         break;
4055                 }
4056         }
4057         if (i >= E1000_MAX_FTQF_FILTERS) {
4058                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4059                 rte_free(filter);
4060                 return -ENOSYS;
4061         }
4062
4063         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4064         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4065                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4066         if (filter->filter_info.dst_ip_mask == 0)
4067                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4068         if (filter->filter_info.src_port_mask == 0)
4069                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4070         if (filter->filter_info.proto_mask == 0)
4071                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4072         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4073                 E1000_FTQF_QUEUE_MASK;
4074         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4075         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4076         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4077         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4078
4079         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4080         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4081
4082         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4083         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4084                 imir |= E1000_IMIR_PORT_BP;
4085         else
4086                 imir &= ~E1000_IMIR_PORT_BP;
4087         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4088
4089         /* tcp flags bits setting. */
4090         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4091                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4092                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4093                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4094                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4095                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4096                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4097                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4098                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4099                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4100                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4101                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4102                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4103         } else
4104                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4105         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4106         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4107         return 0;
4108 }
4109
4110 /*
4111  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4112  *
4113  * @param
4114  * dev: Pointer to struct rte_eth_dev.
4115  * ntuple_filter: ponter to the filter that will be removed.
4116  *
4117  * @return
4118  *    - On success, zero.
4119  *    - On failure, a negative value.
4120  */
4121 static int
4122 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4123                                 struct rte_eth_ntuple_filter *ntuple_filter)
4124 {
4125         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4126         struct e1000_filter_info *filter_info =
4127                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4128         struct e1000_5tuple_filter_info filter_5tuple;
4129         struct e1000_5tuple_filter *filter;
4130         int ret;
4131
4132         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4133         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4134                                             &filter_5tuple);
4135         if (ret < 0)
4136                 return ret;
4137
4138         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4139                                          &filter_5tuple);
4140         if (filter == NULL) {
4141                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4142                 return -ENOENT;
4143         }
4144
4145         filter_info->fivetuple_mask &= ~(1 << filter->index);
4146         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4147         rte_free(filter);
4148
4149         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4150                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4151         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4152         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4153         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4154         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4155         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4156         return 0;
4157 }
4158
4159 static int
4160 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4161 {
4162         uint32_t rctl;
4163         struct e1000_hw *hw;
4164         struct rte_eth_dev_info dev_info;
4165         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4166                                      VLAN_TAG_SIZE);
4167
4168         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4169
4170 #ifdef RTE_LIBRTE_82571_SUPPORT
4171         /* XXX: not bigger than max_rx_pktlen */
4172         if (hw->mac.type == e1000_82571)
4173                 return -ENOTSUP;
4174 #endif
4175         eth_igb_infos_get(dev, &dev_info);
4176
4177         /* check that mtu is within the allowed range */
4178         if ((mtu < ETHER_MIN_MTU) ||
4179             (frame_size > dev_info.max_rx_pktlen))
4180                 return -EINVAL;
4181
4182         /* refuse mtu that requires the support of scattered packets when this
4183          * feature has not been enabled before. */
4184         if (!dev->data->scattered_rx &&
4185             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4186                 return -EINVAL;
4187
4188         rctl = E1000_READ_REG(hw, E1000_RCTL);
4189
4190         /* switch to jumbo mode if needed */
4191         if (frame_size > ETHER_MAX_LEN) {
4192                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4193                 rctl |= E1000_RCTL_LPE;
4194         } else {
4195                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4196                 rctl &= ~E1000_RCTL_LPE;
4197         }
4198         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4199
4200         /* update max frame size */
4201         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4202
4203         E1000_WRITE_REG(hw, E1000_RLPML,
4204                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4205
4206         return 0;
4207 }
4208
4209 /*
4210  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4211  *
4212  * @param
4213  * dev: Pointer to struct rte_eth_dev.
4214  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4215  * add: if true, add filter, if false, remove filter
4216  *
4217  * @return
4218  *    - On success, zero.
4219  *    - On failure, a negative value.
4220  */
4221 static int
4222 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4223                         struct rte_eth_ntuple_filter *ntuple_filter,
4224                         bool add)
4225 {
4226         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4227         int ret;
4228
4229         switch (ntuple_filter->flags) {
4230         case RTE_5TUPLE_FLAGS:
4231         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4232                 if (hw->mac.type != e1000_82576)
4233                         return -ENOTSUP;
4234                 if (add)
4235                         ret = igb_add_5tuple_filter_82576(dev,
4236                                                           ntuple_filter);
4237                 else
4238                         ret = igb_remove_5tuple_filter_82576(dev,
4239                                                              ntuple_filter);
4240                 break;
4241         case RTE_2TUPLE_FLAGS:
4242         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4243                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4244                         return -ENOTSUP;
4245                 if (add)
4246                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4247                 else
4248                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4249                 break;
4250         default:
4251                 ret = -EINVAL;
4252                 break;
4253         }
4254
4255         return ret;
4256 }
4257
4258 /*
4259  * igb_get_ntuple_filter - get a ntuple filter
4260  *
4261  * @param
4262  * dev: Pointer to struct rte_eth_dev.
4263  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4264  *
4265  * @return
4266  *    - On success, zero.
4267  *    - On failure, a negative value.
4268  */
4269 static int
4270 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4271                         struct rte_eth_ntuple_filter *ntuple_filter)
4272 {
4273         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4274         struct e1000_filter_info *filter_info =
4275                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4276         struct e1000_5tuple_filter_info filter_5tuple;
4277         struct e1000_2tuple_filter_info filter_2tuple;
4278         struct e1000_5tuple_filter *p_5tuple_filter;
4279         struct e1000_2tuple_filter *p_2tuple_filter;
4280         int ret;
4281
4282         switch (ntuple_filter->flags) {
4283         case RTE_5TUPLE_FLAGS:
4284         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4285                 if (hw->mac.type != e1000_82576)
4286                         return -ENOTSUP;
4287                 memset(&filter_5tuple,
4288                         0,
4289                         sizeof(struct e1000_5tuple_filter_info));
4290                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4291                                                     &filter_5tuple);
4292                 if (ret < 0)
4293                         return ret;
4294                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4295                                         &filter_info->fivetuple_list,
4296                                         &filter_5tuple);
4297                 if (p_5tuple_filter == NULL) {
4298                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4299                         return -ENOENT;
4300                 }
4301                 ntuple_filter->queue = p_5tuple_filter->queue;
4302                 break;
4303         case RTE_2TUPLE_FLAGS:
4304         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4305                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4306                         return -ENOTSUP;
4307                 memset(&filter_2tuple,
4308                         0,
4309                         sizeof(struct e1000_2tuple_filter_info));
4310                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4311                 if (ret < 0)
4312                         return ret;
4313                 p_2tuple_filter = igb_2tuple_filter_lookup(
4314                                         &filter_info->twotuple_list,
4315                                         &filter_2tuple);
4316                 if (p_2tuple_filter == NULL) {
4317                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4318                         return -ENOENT;
4319                 }
4320                 ntuple_filter->queue = p_2tuple_filter->queue;
4321                 break;
4322         default:
4323                 ret = -EINVAL;
4324                 break;
4325         }
4326
4327         return 0;
4328 }
4329
4330 /*
4331  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4332  * @dev: pointer to rte_eth_dev structure
4333  * @filter_op:operation will be taken.
4334  * @arg: a pointer to specific structure corresponding to the filter_op
4335  */
4336 static int
4337 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4338                                 enum rte_filter_op filter_op,
4339                                 void *arg)
4340 {
4341         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342         int ret;
4343
4344         MAC_TYPE_FILTER_SUP(hw->mac.type);
4345
4346         if (filter_op == RTE_ETH_FILTER_NOP)
4347                 return 0;
4348
4349         if (arg == NULL) {
4350                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4351                             filter_op);
4352                 return -EINVAL;
4353         }
4354
4355         switch (filter_op) {
4356         case RTE_ETH_FILTER_ADD:
4357                 ret = igb_add_del_ntuple_filter(dev,
4358                         (struct rte_eth_ntuple_filter *)arg,
4359                         TRUE);
4360                 break;
4361         case RTE_ETH_FILTER_DELETE:
4362                 ret = igb_add_del_ntuple_filter(dev,
4363                         (struct rte_eth_ntuple_filter *)arg,
4364                         FALSE);
4365                 break;
4366         case RTE_ETH_FILTER_GET:
4367                 ret = igb_get_ntuple_filter(dev,
4368                         (struct rte_eth_ntuple_filter *)arg);
4369                 break;
4370         default:
4371                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4372                 ret = -EINVAL;
4373                 break;
4374         }
4375         return ret;
4376 }
4377
4378 static inline int
4379 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4380                         uint16_t ethertype)
4381 {
4382         int i;
4383
4384         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4385                 if (filter_info->ethertype_filters[i] == ethertype &&
4386                     (filter_info->ethertype_mask & (1 << i)))
4387                         return i;
4388         }
4389         return -1;
4390 }
4391
4392 static inline int
4393 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4394                         uint16_t ethertype)
4395 {
4396         int i;
4397
4398         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4399                 if (!(filter_info->ethertype_mask & (1 << i))) {
4400                         filter_info->ethertype_mask |= 1 << i;
4401                         filter_info->ethertype_filters[i] = ethertype;
4402                         return i;
4403                 }
4404         }
4405         return -1;
4406 }
4407
4408 static inline int
4409 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4410                         uint8_t idx)
4411 {
4412         if (idx >= E1000_MAX_ETQF_FILTERS)
4413                 return -1;
4414         filter_info->ethertype_mask &= ~(1 << idx);
4415         filter_info->ethertype_filters[idx] = 0;
4416         return idx;
4417 }
4418
4419
4420 static int
4421 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4422                         struct rte_eth_ethertype_filter *filter,
4423                         bool add)
4424 {
4425         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426         struct e1000_filter_info *filter_info =
4427                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4428         uint32_t etqf = 0;
4429         int ret;
4430
4431         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4432                 filter->ether_type == ETHER_TYPE_IPv6) {
4433                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4434                         " ethertype filter.", filter->ether_type);
4435                 return -EINVAL;
4436         }
4437
4438         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4439                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4440                 return -EINVAL;
4441         }
4442         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4443                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4444                 return -EINVAL;
4445         }
4446
4447         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4448         if (ret >= 0 && add) {
4449                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4450                             filter->ether_type);
4451                 return -EEXIST;
4452         }
4453         if (ret < 0 && !add) {
4454                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4455                             filter->ether_type);
4456                 return -ENOENT;
4457         }
4458
4459         if (add) {
4460                 ret = igb_ethertype_filter_insert(filter_info,
4461                         filter->ether_type);
4462                 if (ret < 0) {
4463                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4464                         return -ENOSYS;
4465                 }
4466
4467                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4468                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4469                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4470         } else {
4471                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4472                 if (ret < 0)
4473                         return -ENOSYS;
4474         }
4475         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4476         E1000_WRITE_FLUSH(hw);
4477
4478         return 0;
4479 }
4480
4481 static int
4482 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4483                         struct rte_eth_ethertype_filter *filter)
4484 {
4485         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4486         struct e1000_filter_info *filter_info =
4487                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4488         uint32_t etqf;
4489         int ret;
4490
4491         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4492         if (ret < 0) {
4493                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4494                             filter->ether_type);
4495                 return -ENOENT;
4496         }
4497
4498         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4499         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4500                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4501                 filter->flags = 0;
4502                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4503                                 E1000_ETQF_QUEUE_SHIFT;
4504                 return 0;
4505         }
4506
4507         return -ENOENT;
4508 }
4509
4510 /*
4511  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4512  * @dev: pointer to rte_eth_dev structure
4513  * @filter_op:operation will be taken.
4514  * @arg: a pointer to specific structure corresponding to the filter_op
4515  */
4516 static int
4517 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4518                                 enum rte_filter_op filter_op,
4519                                 void *arg)
4520 {
4521         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4522         int ret;
4523
4524         MAC_TYPE_FILTER_SUP(hw->mac.type);
4525
4526         if (filter_op == RTE_ETH_FILTER_NOP)
4527                 return 0;
4528
4529         if (arg == NULL) {
4530                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4531                             filter_op);
4532                 return -EINVAL;
4533         }
4534
4535         switch (filter_op) {
4536         case RTE_ETH_FILTER_ADD:
4537                 ret = igb_add_del_ethertype_filter(dev,
4538                         (struct rte_eth_ethertype_filter *)arg,
4539                         TRUE);
4540                 break;
4541         case RTE_ETH_FILTER_DELETE:
4542                 ret = igb_add_del_ethertype_filter(dev,
4543                         (struct rte_eth_ethertype_filter *)arg,
4544                         FALSE);
4545                 break;
4546         case RTE_ETH_FILTER_GET:
4547                 ret = igb_get_ethertype_filter(dev,
4548                         (struct rte_eth_ethertype_filter *)arg);
4549                 break;
4550         default:
4551                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4552                 ret = -EINVAL;
4553                 break;
4554         }
4555         return ret;
4556 }
4557
4558 static int
4559 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4560                      enum rte_filter_type filter_type,
4561                      enum rte_filter_op filter_op,
4562                      void *arg)
4563 {
4564         int ret = -EINVAL;
4565
4566         switch (filter_type) {
4567         case RTE_ETH_FILTER_NTUPLE:
4568                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4569                 break;
4570         case RTE_ETH_FILTER_ETHERTYPE:
4571                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4572                 break;
4573         case RTE_ETH_FILTER_SYN:
4574                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4575                 break;
4576         case RTE_ETH_FILTER_FLEXIBLE:
4577                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4578                 break;
4579         default:
4580                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4581                                                         filter_type);
4582                 break;
4583         }
4584
4585         return ret;
4586 }
4587
4588 static int
4589 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4590                          struct ether_addr *mc_addr_set,
4591                          uint32_t nb_mc_addr)
4592 {
4593         struct e1000_hw *hw;
4594
4595         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4596         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4597         return 0;
4598 }
4599
4600 static uint64_t
4601 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4602 {
4603         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4604         uint64_t systime_cycles;
4605
4606         switch (hw->mac.type) {
4607         case e1000_i210:
4608         case e1000_i211:
4609                 /*
4610                  * Need to read System Time Residue Register to be able
4611                  * to read the other two registers.
4612                  */
4613                 E1000_READ_REG(hw, E1000_SYSTIMR);
4614                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4615                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4616                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4617                                 * NSEC_PER_SEC;
4618                 break;
4619         case e1000_82580:
4620         case e1000_i350:
4621         case e1000_i354:
4622                 /*
4623                  * Need to read System Time Residue Register to be able
4624                  * to read the other two registers.
4625                  */
4626                 E1000_READ_REG(hw, E1000_SYSTIMR);
4627                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4628                 /* Only the 8 LSB are valid. */
4629                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4630                                 & 0xff) << 32;
4631                 break;
4632         default:
4633                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4634                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4635                                 << 32;
4636                 break;
4637         }
4638
4639         return systime_cycles;
4640 }
4641
4642 static uint64_t
4643 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4644 {
4645         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4646         uint64_t rx_tstamp_cycles;
4647
4648         switch (hw->mac.type) {
4649         case e1000_i210:
4650         case e1000_i211:
4651                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4652                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4653                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4654                                 * NSEC_PER_SEC;
4655                 break;
4656         case e1000_82580:
4657         case e1000_i350:
4658         case e1000_i354:
4659                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4660                 /* Only the 8 LSB are valid. */
4661                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4662                                 & 0xff) << 32;
4663                 break;
4664         default:
4665                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4666                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4667                                 << 32;
4668                 break;
4669         }
4670
4671         return rx_tstamp_cycles;
4672 }
4673
4674 static uint64_t
4675 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4676 {
4677         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4678         uint64_t tx_tstamp_cycles;
4679
4680         switch (hw->mac.type) {
4681         case e1000_i210:
4682         case e1000_i211:
4683                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4684                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4685                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4686                                 * NSEC_PER_SEC;
4687                 break;
4688         case e1000_82580:
4689         case e1000_i350:
4690         case e1000_i354:
4691                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4692                 /* Only the 8 LSB are valid. */
4693                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4694                                 & 0xff) << 32;
4695                 break;
4696         default:
4697                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4698                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4699                                 << 32;
4700                 break;
4701         }
4702
4703         return tx_tstamp_cycles;
4704 }
4705
4706 static void
4707 igb_start_timecounters(struct rte_eth_dev *dev)
4708 {
4709         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4710         struct e1000_adapter *adapter =
4711                 (struct e1000_adapter *)dev->data->dev_private;
4712         uint32_t incval = 1;
4713         uint32_t shift = 0;
4714         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4715
4716         switch (hw->mac.type) {
4717         case e1000_82580:
4718         case e1000_i350:
4719         case e1000_i354:
4720                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4721                 mask = (1ULL << 40) - 1;
4722                 /* fall-through */
4723         case e1000_i210:
4724         case e1000_i211:
4725                 /*
4726                  * Start incrementing the register
4727                  * used to timestamp PTP packets.
4728                  */
4729                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4730                 break;
4731         case e1000_82576:
4732                 incval = E1000_INCVALUE_82576;
4733                 shift = IGB_82576_TSYNC_SHIFT;
4734                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4735                                 E1000_INCPERIOD_82576 | incval);
4736                 break;
4737         default:
4738                 /* Not supported */
4739                 return;
4740         }
4741
4742         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4743         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4744         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4745
4746         adapter->systime_tc.cc_mask = mask;
4747         adapter->systime_tc.cc_shift = shift;
4748         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4749
4750         adapter->rx_tstamp_tc.cc_mask = mask;
4751         adapter->rx_tstamp_tc.cc_shift = shift;
4752         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4753
4754         adapter->tx_tstamp_tc.cc_mask = mask;
4755         adapter->tx_tstamp_tc.cc_shift = shift;
4756         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4757 }
4758
4759 static int
4760 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4761 {
4762         struct e1000_adapter *adapter =
4763                         (struct e1000_adapter *)dev->data->dev_private;
4764
4765         adapter->systime_tc.nsec += delta;
4766         adapter->rx_tstamp_tc.nsec += delta;
4767         adapter->tx_tstamp_tc.nsec += delta;
4768
4769         return 0;
4770 }
4771
4772 static int
4773 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4774 {
4775         uint64_t ns;
4776         struct e1000_adapter *adapter =
4777                         (struct e1000_adapter *)dev->data->dev_private;
4778
4779         ns = rte_timespec_to_ns(ts);
4780
4781         /* Set the timecounters to a new value. */
4782         adapter->systime_tc.nsec = ns;
4783         adapter->rx_tstamp_tc.nsec = ns;
4784         adapter->tx_tstamp_tc.nsec = ns;
4785
4786         return 0;
4787 }
4788
4789 static int
4790 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4791 {
4792         uint64_t ns, systime_cycles;
4793         struct e1000_adapter *adapter =
4794                         (struct e1000_adapter *)dev->data->dev_private;
4795
4796         systime_cycles = igb_read_systime_cyclecounter(dev);
4797         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4798         *ts = rte_ns_to_timespec(ns);
4799
4800         return 0;
4801 }
4802
4803 static int
4804 igb_timesync_enable(struct rte_eth_dev *dev)
4805 {
4806         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4807         uint32_t tsync_ctl;
4808         uint32_t tsauxc;
4809
4810         /* Stop the timesync system time. */
4811         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4812         /* Reset the timesync system time value. */
4813         switch (hw->mac.type) {
4814         case e1000_82580:
4815         case e1000_i350:
4816         case e1000_i354:
4817         case e1000_i210:
4818         case e1000_i211:
4819                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4820                 /* fall-through */
4821         case e1000_82576:
4822                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4823                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4824                 break;
4825         default:
4826                 /* Not supported. */
4827                 return -ENOTSUP;
4828         }
4829
4830         /* Enable system time for it isn't on by default. */
4831         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4832         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4833         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4834
4835         igb_start_timecounters(dev);
4836
4837         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4838         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4839                         (ETHER_TYPE_1588 |
4840                          E1000_ETQF_FILTER_ENABLE |
4841                          E1000_ETQF_1588));
4842
4843         /* Enable timestamping of received PTP packets. */
4844         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4845         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4846         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4847
4848         /* Enable Timestamping of transmitted PTP packets. */
4849         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4850         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4851         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4852
4853         return 0;
4854 }
4855
4856 static int
4857 igb_timesync_disable(struct rte_eth_dev *dev)
4858 {
4859         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860         uint32_t tsync_ctl;
4861
4862         /* Disable timestamping of transmitted PTP packets. */
4863         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4864         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4865         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4866
4867         /* Disable timestamping of received PTP packets. */
4868         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4869         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4870         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4871
4872         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4873         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4874
4875         /* Stop incrementating the System Time registers. */
4876         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4877
4878         return 0;
4879 }
4880
4881 static int
4882 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4883                                struct timespec *timestamp,
4884                                uint32_t flags __rte_unused)
4885 {
4886         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4887         struct e1000_adapter *adapter =
4888                         (struct e1000_adapter *)dev->data->dev_private;
4889         uint32_t tsync_rxctl;
4890         uint64_t rx_tstamp_cycles;
4891         uint64_t ns;
4892
4893         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4894         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4895                 return -EINVAL;
4896
4897         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4898         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4899         *timestamp = rte_ns_to_timespec(ns);
4900
4901         return  0;
4902 }
4903
4904 static int
4905 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4906                                struct timespec *timestamp)
4907 {
4908         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4909         struct e1000_adapter *adapter =
4910                         (struct e1000_adapter *)dev->data->dev_private;
4911         uint32_t tsync_txctl;
4912         uint64_t tx_tstamp_cycles;
4913         uint64_t ns;
4914
4915         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4916         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4917                 return -EINVAL;
4918
4919         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4920         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4921         *timestamp = rte_ns_to_timespec(ns);
4922
4923         return  0;
4924 }
4925
4926 static int
4927 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4928 {
4929         int count = 0;
4930         int g_ind = 0;
4931         const struct reg_info *reg_group;
4932
4933         while ((reg_group = igb_regs[g_ind++]))
4934                 count += igb_reg_group_count(reg_group);
4935
4936         return count;
4937 }
4938
4939 static int
4940 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4941 {
4942         int count = 0;
4943         int g_ind = 0;
4944         const struct reg_info *reg_group;
4945
4946         while ((reg_group = igbvf_regs[g_ind++]))
4947                 count += igb_reg_group_count(reg_group);
4948
4949         return count;
4950 }
4951
4952 static int
4953 eth_igb_get_regs(struct rte_eth_dev *dev,
4954         struct rte_dev_reg_info *regs)
4955 {
4956         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4957         uint32_t *data = regs->data;
4958         int g_ind = 0;
4959         int count = 0;
4960         const struct reg_info *reg_group;
4961
4962         if (data == NULL) {
4963                 regs->length = eth_igb_get_reg_length(dev);
4964                 regs->width = sizeof(uint32_t);
4965                 return 0;
4966         }
4967
4968         /* Support only full register dump */
4969         if ((regs->length == 0) ||
4970             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4971                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4972                         hw->device_id;
4973                 while ((reg_group = igb_regs[g_ind++]))
4974                         count += igb_read_regs_group(dev, &data[count],
4975                                                         reg_group);
4976                 return 0;
4977         }
4978
4979         return -ENOTSUP;
4980 }
4981
4982 static int
4983 igbvf_get_regs(struct rte_eth_dev *dev,
4984         struct rte_dev_reg_info *regs)
4985 {
4986         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4987         uint32_t *data = regs->data;
4988         int g_ind = 0;
4989         int count = 0;
4990         const struct reg_info *reg_group;
4991
4992         if (data == NULL) {
4993                 regs->length = igbvf_get_reg_length(dev);
4994                 regs->width = sizeof(uint32_t);
4995                 return 0;
4996         }
4997
4998         /* Support only full register dump */
4999         if ((regs->length == 0) ||
5000             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5001                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5002                         hw->device_id;
5003                 while ((reg_group = igbvf_regs[g_ind++]))
5004                         count += igb_read_regs_group(dev, &data[count],
5005                                                         reg_group);
5006                 return 0;
5007         }
5008
5009         return -ENOTSUP;
5010 }
5011
5012 static int
5013 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5014 {
5015         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5016
5017         /* Return unit is byte count */
5018         return hw->nvm.word_size * 2;
5019 }
5020
5021 static int
5022 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5023         struct rte_dev_eeprom_info *in_eeprom)
5024 {
5025         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5026         struct e1000_nvm_info *nvm = &hw->nvm;
5027         uint16_t *data = in_eeprom->data;
5028         int first, length;
5029
5030         first = in_eeprom->offset >> 1;
5031         length = in_eeprom->length >> 1;
5032         if ((first >= hw->nvm.word_size) ||
5033             ((first + length) >= hw->nvm.word_size))
5034                 return -EINVAL;
5035
5036         in_eeprom->magic = hw->vendor_id |
5037                 ((uint32_t)hw->device_id << 16);
5038
5039         if ((nvm->ops.read) == NULL)
5040                 return -ENOTSUP;
5041
5042         return nvm->ops.read(hw, first, length, data);
5043 }
5044
5045 static int
5046 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5047         struct rte_dev_eeprom_info *in_eeprom)
5048 {
5049         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5050         struct e1000_nvm_info *nvm = &hw->nvm;
5051         uint16_t *data = in_eeprom->data;
5052         int first, length;
5053
5054         first = in_eeprom->offset >> 1;
5055         length = in_eeprom->length >> 1;
5056         if ((first >= hw->nvm.word_size) ||
5057             ((first + length) >= hw->nvm.word_size))
5058                 return -EINVAL;
5059
5060         in_eeprom->magic = (uint32_t)hw->vendor_id |
5061                 ((uint32_t)hw->device_id << 16);
5062
5063         if ((nvm->ops.write) == NULL)
5064                 return -ENOTSUP;
5065         return nvm->ops.write(hw,  first, length, data);
5066 }
5067
5068 static int
5069 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5070 {
5071         struct e1000_hw *hw =
5072                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073         uint32_t mask = 1 << queue_id;
5074
5075         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5076         E1000_WRITE_FLUSH(hw);
5077
5078         return 0;
5079 }
5080
5081 static int
5082 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5083 {
5084         struct e1000_hw *hw =
5085                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086         uint32_t mask = 1 << queue_id;
5087         uint32_t regval;
5088
5089         regval = E1000_READ_REG(hw, E1000_EIMS);
5090         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5091         E1000_WRITE_FLUSH(hw);
5092
5093         rte_intr_enable(&dev->pci_dev->intr_handle);
5094
5095         return 0;
5096 }
5097
5098 static void
5099 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5100                    uint8_t index, uint8_t offset)
5101 {
5102         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5103
5104         /* clear bits */
5105         val &= ~((uint32_t)0xFF << offset);
5106
5107         /* write vector and valid bit */
5108         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5109
5110         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5111 }
5112
5113 static void
5114 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5115                            uint8_t queue, uint8_t msix_vector)
5116 {
5117         uint32_t tmp = 0;
5118
5119         if (hw->mac.type == e1000_82575) {
5120                 if (direction == 0)
5121                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5122                 else if (direction == 1)
5123                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5124                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5125         } else if (hw->mac.type == e1000_82576) {
5126                 if ((direction == 0) || (direction == 1))
5127                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5128                                            ((queue & 0x8) << 1) +
5129                                            8 * direction);
5130         } else if ((hw->mac.type == e1000_82580) ||
5131                         (hw->mac.type == e1000_i350) ||
5132                         (hw->mac.type == e1000_i354) ||
5133                         (hw->mac.type == e1000_i210) ||
5134                         (hw->mac.type == e1000_i211)) {
5135                 if ((direction == 0) || (direction == 1))
5136                         eth_igb_write_ivar(hw, msix_vector,
5137                                            queue >> 1,
5138                                            ((queue & 0x1) << 4) +
5139                                            8 * direction);
5140         }
5141 }
5142
5143 /* Sets up the hardware to generate MSI-X interrupts properly
5144  * @hw
5145  *  board private structure
5146  */
5147 static void
5148 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5149 {
5150         int queue_id;
5151         uint32_t tmpval, regval, intr_mask;
5152         struct e1000_hw *hw =
5153                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5154         uint32_t vec = E1000_MISC_VEC_ID;
5155         uint32_t base = E1000_MISC_VEC_ID;
5156         uint32_t misc_shift = 0;
5157
5158         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5159
5160         /* won't configure msix register if no mapping is done
5161          * between intr vector and event fd
5162          */
5163         if (!rte_intr_dp_is_en(intr_handle))
5164                 return;
5165
5166         if (rte_intr_allow_others(intr_handle)) {
5167                 vec = base = E1000_RX_VEC_START;
5168                 misc_shift = 1;
5169         }
5170
5171         /* set interrupt vector for other causes */
5172         if (hw->mac.type == e1000_82575) {
5173                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5174                 /* enable MSI-X PBA support */
5175                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5176
5177                 /* Auto-Mask interrupts upon ICR read */
5178                 tmpval |= E1000_CTRL_EXT_EIAME;
5179                 tmpval |= E1000_CTRL_EXT_IRCA;
5180
5181                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5182
5183                 /* enable msix_other interrupt */
5184                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5185                 regval = E1000_READ_REG(hw, E1000_EIAC);
5186                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5187                 regval = E1000_READ_REG(hw, E1000_EIAM);
5188                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5189         } else if ((hw->mac.type == e1000_82576) ||
5190                         (hw->mac.type == e1000_82580) ||
5191                         (hw->mac.type == e1000_i350) ||
5192                         (hw->mac.type == e1000_i354) ||
5193                         (hw->mac.type == e1000_i210) ||
5194                         (hw->mac.type == e1000_i211)) {
5195                 /* turn on MSI-X capability first */
5196                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5197                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5198                                         E1000_GPIE_NSICR);
5199                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5200                         misc_shift;
5201                 regval = E1000_READ_REG(hw, E1000_EIAC);
5202                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5203
5204                 /* enable msix_other interrupt */
5205                 regval = E1000_READ_REG(hw, E1000_EIMS);
5206                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5207                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5208                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5209         }
5210
5211         /* use EIAM to auto-mask when MSI-X interrupt
5212          * is asserted, this saves a register write for every interrupt
5213          */
5214         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5215                 misc_shift;
5216         regval = E1000_READ_REG(hw, E1000_EIAM);
5217         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5218
5219         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5220                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5221                 intr_handle->intr_vec[queue_id] = vec;
5222                 if (vec < base + intr_handle->nb_efd - 1)
5223                         vec++;
5224         }
5225
5226         E1000_WRITE_FLUSH(hw);
5227 }
5228
5229 DRIVER_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5230 DRIVER_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5231 DRIVER_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5232 DRIVER_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);