1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static int eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static int eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names,
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
158 static int igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
190 struct rte_eth_ntuple_filter *ntuple_filter);
191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
194 struct rte_eth_ntuple_filter *ntuple_filter);
195 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
196 struct rte_eth_ntuple_filter *ntuple_filter);
197 static int eth_igb_flow_ops_get(struct rte_eth_dev *dev,
198 const struct rte_flow_ops **ops);
199 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
200 static int eth_igb_get_regs(struct rte_eth_dev *dev,
201 struct rte_dev_reg_info *regs);
202 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
203 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
204 struct rte_dev_eeprom_info *eeprom);
205 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
206 struct rte_dev_eeprom_info *eeprom);
207 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
208 struct rte_eth_dev_module_info *modinfo);
209 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
210 struct rte_dev_eeprom_info *info);
211 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
212 struct rte_ether_addr *mc_addr_set,
213 uint32_t nb_mc_addr);
214 static int igb_timesync_enable(struct rte_eth_dev *dev);
215 static int igb_timesync_disable(struct rte_eth_dev *dev);
216 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
217 struct timespec *timestamp,
219 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
220 struct timespec *timestamp);
221 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
222 static int igb_timesync_read_time(struct rte_eth_dev *dev,
223 struct timespec *timestamp);
224 static int igb_timesync_write_time(struct rte_eth_dev *dev,
225 const struct timespec *timestamp);
226 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
228 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
230 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
231 uint8_t queue, uint8_t msix_vector);
232 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
233 uint8_t index, uint8_t offset);
234 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
235 static void eth_igbvf_interrupt_handler(void *param);
236 static void igbvf_mbx_process(struct rte_eth_dev *dev);
237 static int igb_filter_restore(struct rte_eth_dev *dev);
240 * Define VF Stats MACRO for Non "cleared on read" register
242 #define UPDATE_VF_STAT(reg, last, cur) \
244 u32 latest = E1000_READ_REG(hw, reg); \
245 cur += (latest - last) & UINT_MAX; \
249 #define IGB_FC_PAUSE_TIME 0x0680
250 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
251 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
253 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
255 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
258 * The set of PCI devices this driver supports
260 static const struct rte_pci_id pci_id_igb_map[] = {
261 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
262 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
263 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
264 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
265 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
266 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
267 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
268 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
270 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
271 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
272 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
274 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
275 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
276 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
302 { .vendor_id = 0, /* sentinel */ },
306 * The set of PCI devices this driver supports (for 82576&I350 VF)
308 static const struct rte_pci_id pci_id_igbvf_map[] = {
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
313 { .vendor_id = 0, /* sentinel */ },
316 static const struct rte_eth_desc_lim rx_desc_lim = {
317 .nb_max = E1000_MAX_RING_DESC,
318 .nb_min = E1000_MIN_RING_DESC,
319 .nb_align = IGB_RXD_ALIGN,
322 static const struct rte_eth_desc_lim tx_desc_lim = {
323 .nb_max = E1000_MAX_RING_DESC,
324 .nb_min = E1000_MIN_RING_DESC,
325 .nb_align = IGB_RXD_ALIGN,
326 .nb_seg_max = IGB_TX_MAX_SEG,
327 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
330 static const struct eth_dev_ops eth_igb_ops = {
331 .dev_configure = eth_igb_configure,
332 .dev_start = eth_igb_start,
333 .dev_stop = eth_igb_stop,
334 .dev_set_link_up = eth_igb_dev_set_link_up,
335 .dev_set_link_down = eth_igb_dev_set_link_down,
336 .dev_close = eth_igb_close,
337 .dev_reset = eth_igb_reset,
338 .promiscuous_enable = eth_igb_promiscuous_enable,
339 .promiscuous_disable = eth_igb_promiscuous_disable,
340 .allmulticast_enable = eth_igb_allmulticast_enable,
341 .allmulticast_disable = eth_igb_allmulticast_disable,
342 .link_update = eth_igb_link_update,
343 .stats_get = eth_igb_stats_get,
344 .xstats_get = eth_igb_xstats_get,
345 .xstats_get_by_id = eth_igb_xstats_get_by_id,
346 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
347 .xstats_get_names = eth_igb_xstats_get_names,
348 .stats_reset = eth_igb_stats_reset,
349 .xstats_reset = eth_igb_xstats_reset,
350 .fw_version_get = eth_igb_fw_version_get,
351 .dev_infos_get = eth_igb_infos_get,
352 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
353 .mtu_set = eth_igb_mtu_set,
354 .vlan_filter_set = eth_igb_vlan_filter_set,
355 .vlan_tpid_set = eth_igb_vlan_tpid_set,
356 .vlan_offload_set = eth_igb_vlan_offload_set,
357 .rx_queue_setup = eth_igb_rx_queue_setup,
358 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
359 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
360 .rx_queue_release = eth_igb_rx_queue_release,
361 .tx_queue_setup = eth_igb_tx_queue_setup,
362 .tx_queue_release = eth_igb_tx_queue_release,
363 .tx_done_cleanup = eth_igb_tx_done_cleanup,
364 .dev_led_on = eth_igb_led_on,
365 .dev_led_off = eth_igb_led_off,
366 .flow_ctrl_get = eth_igb_flow_ctrl_get,
367 .flow_ctrl_set = eth_igb_flow_ctrl_set,
368 .mac_addr_add = eth_igb_rar_set,
369 .mac_addr_remove = eth_igb_rar_clear,
370 .mac_addr_set = eth_igb_default_mac_addr_set,
371 .reta_update = eth_igb_rss_reta_update,
372 .reta_query = eth_igb_rss_reta_query,
373 .rss_hash_update = eth_igb_rss_hash_update,
374 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
375 .flow_ops_get = eth_igb_flow_ops_get,
376 .set_mc_addr_list = eth_igb_set_mc_addr_list,
377 .rxq_info_get = igb_rxq_info_get,
378 .txq_info_get = igb_txq_info_get,
379 .timesync_enable = igb_timesync_enable,
380 .timesync_disable = igb_timesync_disable,
381 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
382 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
383 .get_reg = eth_igb_get_regs,
384 .get_eeprom_length = eth_igb_get_eeprom_length,
385 .get_eeprom = eth_igb_get_eeprom,
386 .set_eeprom = eth_igb_set_eeprom,
387 .get_module_info = eth_igb_get_module_info,
388 .get_module_eeprom = eth_igb_get_module_eeprom,
389 .timesync_adjust_time = igb_timesync_adjust_time,
390 .timesync_read_time = igb_timesync_read_time,
391 .timesync_write_time = igb_timesync_write_time,
395 * dev_ops for virtual function, bare necessities for basic vf
396 * operation have been implemented
398 static const struct eth_dev_ops igbvf_eth_dev_ops = {
399 .dev_configure = igbvf_dev_configure,
400 .dev_start = igbvf_dev_start,
401 .dev_stop = igbvf_dev_stop,
402 .dev_close = igbvf_dev_close,
403 .promiscuous_enable = igbvf_promiscuous_enable,
404 .promiscuous_disable = igbvf_promiscuous_disable,
405 .allmulticast_enable = igbvf_allmulticast_enable,
406 .allmulticast_disable = igbvf_allmulticast_disable,
407 .link_update = eth_igb_link_update,
408 .stats_get = eth_igbvf_stats_get,
409 .xstats_get = eth_igbvf_xstats_get,
410 .xstats_get_names = eth_igbvf_xstats_get_names,
411 .stats_reset = eth_igbvf_stats_reset,
412 .xstats_reset = eth_igbvf_stats_reset,
413 .vlan_filter_set = igbvf_vlan_filter_set,
414 .dev_infos_get = eth_igbvf_infos_get,
415 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
416 .rx_queue_setup = eth_igb_rx_queue_setup,
417 .rx_queue_release = eth_igb_rx_queue_release,
418 .tx_queue_setup = eth_igb_tx_queue_setup,
419 .tx_queue_release = eth_igb_tx_queue_release,
420 .tx_done_cleanup = eth_igb_tx_done_cleanup,
421 .set_mc_addr_list = eth_igb_set_mc_addr_list,
422 .rxq_info_get = igb_rxq_info_get,
423 .txq_info_get = igb_txq_info_get,
424 .mac_addr_set = igbvf_default_mac_addr_set,
425 .get_reg = igbvf_get_regs,
428 /* store statistics names and its offset in stats structure */
429 struct rte_igb_xstats_name_off {
430 char name[RTE_ETH_XSTATS_NAME_SIZE];
434 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
435 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
436 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
437 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
438 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
439 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
440 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
441 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
443 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
444 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
445 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
446 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
447 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
448 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
449 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
450 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
451 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
452 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
453 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
455 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
456 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
457 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
458 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
459 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
461 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
463 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
464 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
465 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
466 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
467 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
468 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
469 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
470 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
471 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
472 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
473 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
474 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
475 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
476 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
477 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
478 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
479 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
480 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
482 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
484 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
485 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
486 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
487 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
488 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
489 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
490 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
492 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
495 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
496 sizeof(rte_igb_stats_strings[0]))
498 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
499 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
500 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
501 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
502 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
503 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
506 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
507 sizeof(rte_igbvf_stats_strings[0]))
511 igb_intr_enable(struct rte_eth_dev *dev)
513 struct e1000_interrupt *intr =
514 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
515 struct e1000_hw *hw =
516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
517 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
518 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
520 if (rte_intr_allow_others(intr_handle) &&
521 dev->data->dev_conf.intr_conf.lsc != 0) {
522 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
525 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
526 E1000_WRITE_FLUSH(hw);
530 igb_intr_disable(struct rte_eth_dev *dev)
532 struct e1000_hw *hw =
533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
535 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
537 if (rte_intr_allow_others(intr_handle) &&
538 dev->data->dev_conf.intr_conf.lsc != 0) {
539 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
542 E1000_WRITE_REG(hw, E1000_IMC, ~0);
543 E1000_WRITE_FLUSH(hw);
547 igbvf_intr_enable(struct rte_eth_dev *dev)
549 struct e1000_hw *hw =
550 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 /* only for mailbox */
553 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
554 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
555 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
556 E1000_WRITE_FLUSH(hw);
559 /* only for mailbox now. If RX/TX needed, should extend this function. */
561 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
566 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
567 tmp |= E1000_VTIVAR_VALID;
568 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
572 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
574 struct e1000_hw *hw =
575 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
577 /* Configure VF other cause ivar */
578 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
581 static inline int32_t
582 igb_pf_reset_hw(struct e1000_hw *hw)
587 status = e1000_reset_hw(hw);
589 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
590 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
591 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
592 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
593 E1000_WRITE_FLUSH(hw);
599 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
601 struct e1000_hw *hw =
602 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 hw->vendor_id = pci_dev->id.vendor_id;
606 hw->device_id = pci_dev->id.device_id;
607 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
608 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
610 e1000_set_mac_type(hw);
612 /* need to check if it is a vf device below */
616 igb_reset_swfw_lock(struct e1000_hw *hw)
621 * Do mac ops initialization manually here, since we will need
622 * some function pointers set by this call.
624 ret_val = e1000_init_mac_params(hw);
629 * SMBI lock should not fail in this early stage. If this is the case,
630 * it is due to an improper exit of the application.
631 * So force the release of the faulty lock.
633 if (e1000_get_hw_semaphore_generic(hw) < 0) {
634 PMD_DRV_LOG(DEBUG, "SMBI lock released");
636 e1000_put_hw_semaphore_generic(hw);
638 if (hw->mac.ops.acquire_swfw_sync != NULL) {
642 * Phy lock should not fail in this early stage. If this is the case,
643 * it is due to an improper exit of the application.
644 * So force the release of the faulty lock.
646 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
647 if (hw->bus.func > E1000_FUNC_1)
649 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
650 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
653 hw->mac.ops.release_swfw_sync(hw, mask);
656 * This one is more tricky since it is common to all ports; but
657 * swfw_sync retries last long enough (1s) to be almost sure that if
658 * lock can not be taken it is due to an improper lock of the
661 mask = E1000_SWFW_EEP_SM;
662 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
663 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
665 hw->mac.ops.release_swfw_sync(hw, mask);
668 return E1000_SUCCESS;
671 /* Remove all ntuple filters of the device */
672 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
674 struct e1000_filter_info *filter_info =
675 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
676 struct e1000_5tuple_filter *p_5tuple;
677 struct e1000_2tuple_filter *p_2tuple;
679 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
680 TAILQ_REMOVE(&filter_info->fivetuple_list,
684 filter_info->fivetuple_mask = 0;
685 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
686 TAILQ_REMOVE(&filter_info->twotuple_list,
690 filter_info->twotuple_mask = 0;
695 /* Remove all flex filters of the device */
696 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
698 struct e1000_filter_info *filter_info =
699 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
700 struct e1000_flex_filter *p_flex;
702 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
703 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
706 filter_info->flex_mask = 0;
712 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
716 struct e1000_hw *hw =
717 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
718 struct e1000_vfta * shadow_vfta =
719 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
720 struct e1000_filter_info *filter_info =
721 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
722 struct e1000_adapter *adapter =
723 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
727 eth_dev->dev_ops = ð_igb_ops;
728 eth_dev->rx_queue_count = eth_igb_rx_queue_count;
729 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
730 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
731 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
732 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
733 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
735 /* for secondary processes, we don't initialise any further as primary
736 * has already done this work. Only check we don't need a different
738 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
739 if (eth_dev->data->scattered_rx)
740 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
744 rte_eth_copy_pci_info(eth_dev, pci_dev);
746 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
748 igb_identify_hardware(eth_dev, pci_dev);
749 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
754 e1000_get_bus_info(hw);
756 /* Reset any pending lock */
757 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
762 /* Finish initialization */
763 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
769 hw->phy.autoneg_wait_to_complete = 0;
770 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
773 if (hw->phy.media_type == e1000_media_type_copper) {
774 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
775 hw->phy.disable_polarity_correction = 0;
776 hw->phy.ms_type = e1000_ms_hw_default;
780 * Start from a known state, this is important in reading the nvm
785 /* Make sure we have a good EEPROM before we read from it */
786 if (e1000_validate_nvm_checksum(hw) < 0) {
788 * Some PCI-E parts fail the first check due to
789 * the link being in sleep state, call it again,
790 * if it fails a second time its a real issue.
792 if (e1000_validate_nvm_checksum(hw) < 0) {
793 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
799 /* Read the permanent MAC address out of the EEPROM */
800 if (e1000_read_mac_addr(hw) != 0) {
801 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
806 /* Allocate memory for storing MAC addresses */
807 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
808 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
809 if (eth_dev->data->mac_addrs == NULL) {
810 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
811 "store MAC addresses",
812 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
817 /* Copy the permanent MAC address */
818 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
819 ð_dev->data->mac_addrs[0]);
821 /* initialize the vfta */
822 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
824 /* Now initialize the hardware */
825 if (igb_hardware_init(hw) != 0) {
826 PMD_INIT_LOG(ERR, "Hardware initialization failed");
827 rte_free(eth_dev->data->mac_addrs);
828 eth_dev->data->mac_addrs = NULL;
832 hw->mac.get_link_status = 1;
833 adapter->stopped = 0;
835 /* Indicate SOL/IDER usage */
836 if (e1000_check_reset_block(hw) < 0) {
837 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
841 /* initialize PF if max_vfs not zero */
842 igb_pf_host_init(eth_dev);
844 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
845 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
846 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
847 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
848 E1000_WRITE_FLUSH(hw);
850 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
851 eth_dev->data->port_id, pci_dev->id.vendor_id,
852 pci_dev->id.device_id);
854 rte_intr_callback_register(&pci_dev->intr_handle,
855 eth_igb_interrupt_handler,
858 /* enable uio/vfio intr/eventfd mapping */
859 rte_intr_enable(&pci_dev->intr_handle);
861 /* enable support intr */
862 igb_intr_enable(eth_dev);
864 eth_igb_dev_set_link_down(eth_dev);
866 /* initialize filter info */
867 memset(filter_info, 0,
868 sizeof(struct e1000_filter_info));
870 TAILQ_INIT(&filter_info->flex_list);
871 TAILQ_INIT(&filter_info->twotuple_list);
872 TAILQ_INIT(&filter_info->fivetuple_list);
874 TAILQ_INIT(&igb_filter_ntuple_list);
875 TAILQ_INIT(&igb_filter_ethertype_list);
876 TAILQ_INIT(&igb_filter_syn_list);
877 TAILQ_INIT(&igb_filter_flex_list);
878 TAILQ_INIT(&igb_filter_rss_list);
879 TAILQ_INIT(&igb_flow_list);
884 igb_hw_control_release(hw);
890 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
892 PMD_INIT_FUNC_TRACE();
894 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
897 eth_igb_close(eth_dev);
903 * Virtual Function device init
906 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
908 struct rte_pci_device *pci_dev;
909 struct rte_intr_handle *intr_handle;
910 struct e1000_adapter *adapter =
911 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
912 struct e1000_hw *hw =
913 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
915 struct rte_ether_addr *perm_addr =
916 (struct rte_ether_addr *)hw->mac.perm_addr;
918 PMD_INIT_FUNC_TRACE();
920 eth_dev->dev_ops = &igbvf_eth_dev_ops;
921 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
922 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
923 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
924 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
925 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
927 /* for secondary processes, we don't initialise any further as primary
928 * has already done this work. Only check we don't need a different
930 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
931 if (eth_dev->data->scattered_rx)
932 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
936 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
937 rte_eth_copy_pci_info(eth_dev, pci_dev);
939 hw->device_id = pci_dev->id.device_id;
940 hw->vendor_id = pci_dev->id.vendor_id;
941 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
942 adapter->stopped = 0;
944 /* Initialize the shared code (base driver) */
945 diag = e1000_setup_init_funcs(hw, TRUE);
947 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
952 /* init_mailbox_params */
953 hw->mbx.ops.init_params(hw);
955 /* Disable the interrupts for VF */
956 igbvf_intr_disable(hw);
958 diag = hw->mac.ops.reset_hw(hw);
960 /* Allocate memory for storing MAC addresses */
961 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
962 hw->mac.rar_entry_count, 0);
963 if (eth_dev->data->mac_addrs == NULL) {
965 "Failed to allocate %d bytes needed to store MAC "
967 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
971 /* Generate a random MAC address, if none was assigned by PF. */
972 if (rte_is_zero_ether_addr(perm_addr)) {
973 rte_eth_random_addr(perm_addr->addr_bytes);
974 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
975 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
976 RTE_ETHER_ADDR_PRT_FMT,
977 RTE_ETHER_ADDR_BYTES(perm_addr));
980 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
982 rte_free(eth_dev->data->mac_addrs);
983 eth_dev->data->mac_addrs = NULL;
986 /* Copy the permanent MAC address */
987 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
988 ð_dev->data->mac_addrs[0]);
990 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
992 eth_dev->data->port_id, pci_dev->id.vendor_id,
993 pci_dev->id.device_id, "igb_mac_82576_vf");
995 intr_handle = &pci_dev->intr_handle;
996 rte_intr_callback_register(intr_handle,
997 eth_igbvf_interrupt_handler, eth_dev);
1003 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1005 PMD_INIT_FUNC_TRACE();
1007 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1010 igbvf_dev_close(eth_dev);
1015 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1016 struct rte_pci_device *pci_dev)
1018 return rte_eth_dev_pci_generic_probe(pci_dev,
1019 sizeof(struct e1000_adapter), eth_igb_dev_init);
1022 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1024 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1027 static struct rte_pci_driver rte_igb_pmd = {
1028 .id_table = pci_id_igb_map,
1029 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1030 .probe = eth_igb_pci_probe,
1031 .remove = eth_igb_pci_remove,
1035 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1036 struct rte_pci_device *pci_dev)
1038 return rte_eth_dev_pci_generic_probe(pci_dev,
1039 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1042 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1044 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1048 * virtual function driver struct
1050 static struct rte_pci_driver rte_igbvf_pmd = {
1051 .id_table = pci_id_igbvf_map,
1052 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1053 .probe = eth_igbvf_pci_probe,
1054 .remove = eth_igbvf_pci_remove,
1058 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1060 struct e1000_hw *hw =
1061 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1062 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1063 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1064 rctl |= E1000_RCTL_VFE;
1065 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1069 igb_check_mq_mode(struct rte_eth_dev *dev)
1071 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1072 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1073 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1074 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1076 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1077 tx_mq_mode == ETH_MQ_TX_DCB ||
1078 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1079 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1082 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1083 /* Check multi-queue mode.
1084 * To no break software we accept ETH_MQ_RX_NONE as this might
1085 * be used to turn off VLAN filter.
1088 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1089 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1090 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1091 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1093 /* Only support one queue on VFs.
1094 * RSS together with SRIOV is not supported.
1096 PMD_INIT_LOG(ERR, "SRIOV is active,"
1097 " wrong mq_mode rx %d.",
1101 /* TX mode is not used here, so mode might be ignored.*/
1102 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1103 /* SRIOV only works in VMDq enable mode */
1104 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1105 " TX mode %d is not supported. "
1106 " Driver will behave as %d mode.",
1107 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1110 /* check valid queue number */
1111 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1112 PMD_INIT_LOG(ERR, "SRIOV is active,"
1113 " only support one queue on VFs.");
1117 /* To no break software that set invalid mode, only display
1118 * warning if invalid mode is used.
1120 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1121 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1122 rx_mq_mode != ETH_MQ_RX_RSS) {
1123 /* RSS together with VMDq not supported*/
1124 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1129 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1130 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1131 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1132 " Due to txmode is meaningless in this"
1133 " driver, just ignore.",
1141 eth_igb_configure(struct rte_eth_dev *dev)
1143 struct e1000_interrupt *intr =
1144 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1147 PMD_INIT_FUNC_TRACE();
1149 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1150 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1152 /* multipe queue mode checking */
1153 ret = igb_check_mq_mode(dev);
1155 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1160 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1161 PMD_INIT_FUNC_TRACE();
1167 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1170 struct e1000_hw *hw =
1171 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1172 uint32_t tctl, rctl;
1174 tctl = E1000_READ_REG(hw, E1000_TCTL);
1175 rctl = E1000_READ_REG(hw, E1000_RCTL);
1179 tctl |= E1000_TCTL_EN;
1180 rctl |= E1000_RCTL_EN;
1183 tctl &= ~E1000_TCTL_EN;
1184 rctl &= ~E1000_RCTL_EN;
1186 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1187 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1188 E1000_WRITE_FLUSH(hw);
1192 eth_igb_start(struct rte_eth_dev *dev)
1194 struct e1000_hw *hw =
1195 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1196 struct e1000_adapter *adapter =
1197 E1000_DEV_PRIVATE(dev->data->dev_private);
1198 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1199 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1201 uint32_t intr_vector = 0;
1207 PMD_INIT_FUNC_TRACE();
1209 /* disable uio/vfio intr/eventfd mapping */
1210 rte_intr_disable(intr_handle);
1212 /* Power up the phy. Needed to make the link go Up */
1213 eth_igb_dev_set_link_up(dev);
1216 * Packet Buffer Allocation (PBA)
1217 * Writing PBA sets the receive portion of the buffer
1218 * the remainder is used for the transmit buffer.
1220 if (hw->mac.type == e1000_82575) {
1223 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1224 E1000_WRITE_REG(hw, E1000_PBA, pba);
1227 /* Put the address into the Receive Address Array */
1228 e1000_rar_set(hw, hw->mac.addr, 0);
1230 /* Initialize the hardware */
1231 if (igb_hardware_init(hw)) {
1232 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1235 adapter->stopped = 0;
1237 E1000_WRITE_REG(hw, E1000_VET,
1238 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1240 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1241 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1242 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1243 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1244 E1000_WRITE_FLUSH(hw);
1246 /* configure PF module if SRIOV enabled */
1247 igb_pf_host_configure(dev);
1249 /* check and configure queue intr-vector mapping */
1250 if ((rte_intr_cap_multiple(intr_handle) ||
1251 !RTE_ETH_DEV_SRIOV(dev).active) &&
1252 dev->data->dev_conf.intr_conf.rxq != 0) {
1253 intr_vector = dev->data->nb_rx_queues;
1254 if (rte_intr_efd_enable(intr_handle, intr_vector))
1258 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1259 intr_handle->intr_vec =
1260 rte_zmalloc("intr_vec",
1261 dev->data->nb_rx_queues * sizeof(int), 0);
1262 if (intr_handle->intr_vec == NULL) {
1263 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1264 " intr_vec", dev->data->nb_rx_queues);
1269 /* confiugre msix for rx interrupt */
1270 eth_igb_configure_msix_intr(dev);
1272 /* Configure for OS presence */
1273 igb_init_manageability(hw);
1275 eth_igb_tx_init(dev);
1277 /* This can fail when allocating mbufs for descriptor rings */
1278 ret = eth_igb_rx_init(dev);
1280 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1281 igb_dev_clear_queues(dev);
1285 e1000_clear_hw_cntrs_base_generic(hw);
1288 * VLAN Offload Settings
1290 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1291 ETH_VLAN_EXTEND_MASK;
1292 ret = eth_igb_vlan_offload_set(dev, mask);
1294 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1295 igb_dev_clear_queues(dev);
1299 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1300 /* Enable VLAN filter since VMDq always use VLAN filter */
1301 igb_vmdq_vlan_hw_filter_enable(dev);
1304 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1305 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1306 (hw->mac.type == e1000_i211)) {
1307 /* Configure EITR with the maximum possible value (0xFFFF) */
1308 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1311 /* Setup link speed and duplex */
1312 speeds = &dev->data->dev_conf.link_speeds;
1313 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1314 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1315 hw->mac.autoneg = 1;
1318 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1321 hw->phy.autoneg_advertised = 0;
1323 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1324 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1325 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1327 goto error_invalid_config;
1329 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1330 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1333 if (*speeds & ETH_LINK_SPEED_10M) {
1334 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1337 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1338 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1341 if (*speeds & ETH_LINK_SPEED_100M) {
1342 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1345 if (*speeds & ETH_LINK_SPEED_1G) {
1346 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1349 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1350 goto error_invalid_config;
1352 /* Set/reset the mac.autoneg based on the link speed,
1356 hw->mac.autoneg = 0;
1357 hw->mac.forced_speed_duplex =
1358 hw->phy.autoneg_advertised;
1360 hw->mac.autoneg = 1;
1364 e1000_setup_link(hw);
1366 if (rte_intr_allow_others(intr_handle)) {
1367 /* check if lsc interrupt is enabled */
1368 if (dev->data->dev_conf.intr_conf.lsc != 0)
1369 eth_igb_lsc_interrupt_setup(dev, TRUE);
1371 eth_igb_lsc_interrupt_setup(dev, FALSE);
1373 rte_intr_callback_unregister(intr_handle,
1374 eth_igb_interrupt_handler,
1376 if (dev->data->dev_conf.intr_conf.lsc != 0)
1377 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1378 " no intr multiplex");
1381 /* check if rxq interrupt is enabled */
1382 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1383 rte_intr_dp_is_en(intr_handle))
1384 eth_igb_rxq_interrupt_setup(dev);
1386 /* enable uio/vfio intr/eventfd mapping */
1387 rte_intr_enable(intr_handle);
1389 /* resume enabled intr since hw reset */
1390 igb_intr_enable(dev);
1392 /* restore all types filter */
1393 igb_filter_restore(dev);
1395 eth_igb_rxtx_control(dev, true);
1396 eth_igb_link_update(dev, 0);
1398 PMD_INIT_LOG(DEBUG, "<<");
1402 error_invalid_config:
1403 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1404 dev->data->dev_conf.link_speeds, dev->data->port_id);
1405 igb_dev_clear_queues(dev);
1409 /*********************************************************************
1411 * This routine disables all traffic on the adapter by issuing a
1412 * global reset on the MAC.
1414 **********************************************************************/
1416 eth_igb_stop(struct rte_eth_dev *dev)
1418 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1420 struct rte_eth_link link;
1421 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1422 struct e1000_adapter *adapter =
1423 E1000_DEV_PRIVATE(dev->data->dev_private);
1425 if (adapter->stopped)
1428 eth_igb_rxtx_control(dev, false);
1430 igb_intr_disable(dev);
1432 /* disable intr eventfd mapping */
1433 rte_intr_disable(intr_handle);
1435 igb_pf_reset_hw(hw);
1436 E1000_WRITE_REG(hw, E1000_WUC, 0);
1438 /* Set bit for Go Link disconnect if PHY reset is not blocked */
1439 if (hw->mac.type >= e1000_82580 &&
1440 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1443 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1444 phpm_reg |= E1000_82580_PM_GO_LINKD;
1445 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1448 /* Power down the phy. Needed to make the link go Down */
1449 eth_igb_dev_set_link_down(dev);
1451 igb_dev_clear_queues(dev);
1453 /* clear the recorded link status */
1454 memset(&link, 0, sizeof(link));
1455 rte_eth_linkstatus_set(dev, &link);
1457 if (!rte_intr_allow_others(intr_handle))
1458 /* resume to the default handler */
1459 rte_intr_callback_register(intr_handle,
1460 eth_igb_interrupt_handler,
1463 /* Clean datapath event and queue/vec mapping */
1464 rte_intr_efd_disable(intr_handle);
1465 if (intr_handle->intr_vec != NULL) {
1466 rte_free(intr_handle->intr_vec);
1467 intr_handle->intr_vec = NULL;
1470 adapter->stopped = true;
1471 dev->data->dev_started = 0;
1477 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1479 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1481 if (hw->phy.media_type == e1000_media_type_copper)
1482 e1000_power_up_phy(hw);
1484 e1000_power_up_fiber_serdes_link(hw);
1490 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1492 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1494 if (hw->phy.media_type == e1000_media_type_copper)
1495 e1000_power_down_phy(hw);
1497 e1000_shutdown_fiber_serdes_link(hw);
1503 eth_igb_close(struct rte_eth_dev *dev)
1505 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506 struct rte_eth_link link;
1507 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1508 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1509 struct e1000_filter_info *filter_info =
1510 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1513 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1516 ret = eth_igb_stop(dev);
1518 e1000_phy_hw_reset(hw);
1519 igb_release_manageability(hw);
1520 igb_hw_control_release(hw);
1522 /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1523 if (hw->mac.type >= e1000_82580 &&
1524 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1527 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1528 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1529 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1532 igb_dev_free_queues(dev);
1534 if (intr_handle->intr_vec) {
1535 rte_free(intr_handle->intr_vec);
1536 intr_handle->intr_vec = NULL;
1539 memset(&link, 0, sizeof(link));
1540 rte_eth_linkstatus_set(dev, &link);
1542 /* Reset any pending lock */
1543 igb_reset_swfw_lock(hw);
1545 /* uninitialize PF if max_vfs not zero */
1546 igb_pf_host_uninit(dev);
1548 rte_intr_callback_unregister(intr_handle,
1549 eth_igb_interrupt_handler, dev);
1551 /* clear the SYN filter info */
1552 filter_info->syn_info = 0;
1554 /* clear the ethertype filters info */
1555 filter_info->ethertype_mask = 0;
1556 memset(filter_info->ethertype_filters, 0,
1557 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1559 /* clear the rss filter info */
1560 memset(&filter_info->rss_info, 0,
1561 sizeof(struct igb_rte_flow_rss_conf));
1563 /* remove all ntuple filters of the device */
1564 igb_ntuple_filter_uninit(dev);
1566 /* remove all flex filters of the device */
1567 igb_flex_filter_uninit(dev);
1569 /* clear all the filters list */
1570 igb_filterlist_flush(dev);
1579 eth_igb_reset(struct rte_eth_dev *dev)
1583 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1584 * its VF to make them align with it. The detailed notification
1585 * mechanism is PMD specific and is currently not implemented.
1586 * To avoid unexpected behavior in VF, currently reset of PF with
1587 * SR-IOV activation is not supported. It might be supported later.
1589 if (dev->data->sriov.active)
1592 ret = eth_igb_dev_uninit(dev);
1596 ret = eth_igb_dev_init(dev);
1603 igb_get_rx_buffer_size(struct e1000_hw *hw)
1605 uint32_t rx_buf_size;
1606 if (hw->mac.type == e1000_82576) {
1607 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1608 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1609 /* PBS needs to be translated according to a lookup table */
1610 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1611 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1612 rx_buf_size = (rx_buf_size << 10);
1613 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1614 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1616 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1622 /*********************************************************************
1624 * Initialize the hardware
1626 **********************************************************************/
1628 igb_hardware_init(struct e1000_hw *hw)
1630 uint32_t rx_buf_size;
1633 /* Let the firmware know the OS is in control */
1634 igb_hw_control_acquire(hw);
1637 * These parameters control the automatic generation (Tx) and
1638 * response (Rx) to Ethernet PAUSE frames.
1639 * - High water mark should allow for at least two standard size (1518)
1640 * frames to be received after sending an XOFF.
1641 * - Low water mark works best when it is very near the high water mark.
1642 * This allows the receiver to restart by sending XON when it has
1643 * drained a bit. Here we use an arbitrary value of 1500 which will
1644 * restart after one full frame is pulled from the buffer. There
1645 * could be several smaller frames in the buffer and if so they will
1646 * not trigger the XON until their total number reduces the buffer
1648 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1650 rx_buf_size = igb_get_rx_buffer_size(hw);
1652 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1653 hw->fc.low_water = hw->fc.high_water - 1500;
1654 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1655 hw->fc.send_xon = 1;
1657 /* Set Flow control, use the tunable location if sane */
1658 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1659 hw->fc.requested_mode = igb_fc_setting;
1661 hw->fc.requested_mode = e1000_fc_none;
1663 /* Issue a global reset */
1664 igb_pf_reset_hw(hw);
1665 E1000_WRITE_REG(hw, E1000_WUC, 0);
1667 diag = e1000_init_hw(hw);
1671 E1000_WRITE_REG(hw, E1000_VET,
1672 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1673 e1000_get_phy_info(hw);
1674 e1000_check_for_link(hw);
1679 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1681 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1685 uint64_t old_gprc = stats->gprc;
1686 uint64_t old_gptc = stats->gptc;
1687 uint64_t old_tpr = stats->tpr;
1688 uint64_t old_tpt = stats->tpt;
1689 uint64_t old_rpthc = stats->rpthc;
1690 uint64_t old_hgptc = stats->hgptc;
1692 if(hw->phy.media_type == e1000_media_type_copper ||
1693 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1695 E1000_READ_REG(hw,E1000_SYMERRS);
1696 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1699 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1700 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1701 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1702 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1704 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1705 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1706 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1707 stats->dc += E1000_READ_REG(hw, E1000_DC);
1708 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1709 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1710 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1712 ** For watchdog management we need to know if we have been
1713 ** paused during the last interval, so capture that here.
1715 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1716 stats->xoffrxc += pause_frames;
1717 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1718 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1719 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1720 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1721 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1722 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1723 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1724 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1725 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1726 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1727 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1728 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1730 /* For the 64-bit byte counters the low dword must be read first. */
1731 /* Both registers clear on the read of the high dword */
1733 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1734 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1735 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1736 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1737 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1738 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1739 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1741 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1742 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1743 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1744 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1745 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1747 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1748 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1750 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1751 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1752 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1753 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1754 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1755 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1757 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1758 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1759 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1760 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1761 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1762 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1763 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1764 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1766 /* Interrupt Counts */
1768 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1769 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1770 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1771 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1772 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1773 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1774 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1775 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1776 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1778 /* Host to Card Statistics */
1780 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1781 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1782 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1783 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1784 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1785 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1786 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1787 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1788 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1789 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1790 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1791 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1792 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1793 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1794 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1795 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1797 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1798 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1799 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1800 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1801 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1802 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1806 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1808 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1809 struct e1000_hw_stats *stats =
1810 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1812 igb_read_stats_registers(hw, stats);
1814 if (rte_stats == NULL)
1818 rte_stats->imissed = stats->mpc;
1819 rte_stats->ierrors = stats->crcerrs + stats->rlec +
1820 stats->rxerrc + stats->algnerrc + stats->cexterr;
1823 rte_stats->oerrors = stats->ecol + stats->latecol;
1825 rte_stats->ipackets = stats->gprc;
1826 rte_stats->opackets = stats->gptc;
1827 rte_stats->ibytes = stats->gorc;
1828 rte_stats->obytes = stats->gotc;
1833 eth_igb_stats_reset(struct rte_eth_dev *dev)
1835 struct e1000_hw_stats *hw_stats =
1836 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1838 /* HW registers are cleared on read */
1839 eth_igb_stats_get(dev, NULL);
1841 /* Reset software totals */
1842 memset(hw_stats, 0, sizeof(*hw_stats));
1848 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1850 struct e1000_hw_stats *stats =
1851 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1853 /* HW registers are cleared on read */
1854 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1856 /* Reset software totals */
1857 memset(stats, 0, sizeof(*stats));
1862 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1863 struct rte_eth_xstat_name *xstats_names,
1864 __rte_unused unsigned int size)
1868 if (xstats_names == NULL)
1869 return IGB_NB_XSTATS;
1871 /* Note: limit checked in rte_eth_xstats_names() */
1873 for (i = 0; i < IGB_NB_XSTATS; i++) {
1874 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1875 sizeof(xstats_names[i].name));
1878 return IGB_NB_XSTATS;
1881 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1882 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names,
1888 if (xstats_names == NULL)
1889 return IGB_NB_XSTATS;
1891 for (i = 0; i < IGB_NB_XSTATS; i++)
1892 strlcpy(xstats_names[i].name,
1893 rte_igb_stats_strings[i].name,
1894 sizeof(xstats_names[i].name));
1896 return IGB_NB_XSTATS;
1899 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1901 eth_igb_xstats_get_names_by_id(dev, NULL, xstats_names_copy,
1904 for (i = 0; i < limit; i++) {
1905 if (ids[i] >= IGB_NB_XSTATS) {
1906 PMD_INIT_LOG(ERR, "id value isn't valid");
1909 strcpy(xstats_names[i].name,
1910 xstats_names_copy[ids[i]].name);
1917 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1920 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921 struct e1000_hw_stats *hw_stats =
1922 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1925 if (n < IGB_NB_XSTATS)
1926 return IGB_NB_XSTATS;
1928 igb_read_stats_registers(hw, hw_stats);
1930 /* If this is a reset xstats is NULL, and we have cleared the
1931 * registers by reading them.
1936 /* Extended stats */
1937 for (i = 0; i < IGB_NB_XSTATS; i++) {
1939 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1940 rte_igb_stats_strings[i].offset);
1943 return IGB_NB_XSTATS;
1947 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1948 uint64_t *values, unsigned int n)
1953 struct e1000_hw *hw =
1954 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955 struct e1000_hw_stats *hw_stats =
1956 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1958 if (n < IGB_NB_XSTATS)
1959 return IGB_NB_XSTATS;
1961 igb_read_stats_registers(hw, hw_stats);
1963 /* If this is a reset xstats is NULL, and we have cleared the
1964 * registers by reading them.
1969 /* Extended stats */
1970 for (i = 0; i < IGB_NB_XSTATS; i++)
1971 values[i] = *(uint64_t *)(((char *)hw_stats) +
1972 rte_igb_stats_strings[i].offset);
1974 return IGB_NB_XSTATS;
1977 uint64_t values_copy[IGB_NB_XSTATS];
1979 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1982 for (i = 0; i < n; i++) {
1983 if (ids[i] >= IGB_NB_XSTATS) {
1984 PMD_INIT_LOG(ERR, "id value isn't valid");
1987 values[i] = values_copy[ids[i]];
1994 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1996 /* Good Rx packets, include VF loopback */
1997 UPDATE_VF_STAT(E1000_VFGPRC,
1998 hw_stats->last_gprc, hw_stats->gprc);
2000 /* Good Rx octets, include VF loopback */
2001 UPDATE_VF_STAT(E1000_VFGORC,
2002 hw_stats->last_gorc, hw_stats->gorc);
2004 /* Good Tx packets, include VF loopback */
2005 UPDATE_VF_STAT(E1000_VFGPTC,
2006 hw_stats->last_gptc, hw_stats->gptc);
2008 /* Good Tx octets, include VF loopback */
2009 UPDATE_VF_STAT(E1000_VFGOTC,
2010 hw_stats->last_gotc, hw_stats->gotc);
2012 /* Rx Multicst packets */
2013 UPDATE_VF_STAT(E1000_VFMPRC,
2014 hw_stats->last_mprc, hw_stats->mprc);
2016 /* Good Rx loopback packets */
2017 UPDATE_VF_STAT(E1000_VFGPRLBC,
2018 hw_stats->last_gprlbc, hw_stats->gprlbc);
2020 /* Good Rx loopback octets */
2021 UPDATE_VF_STAT(E1000_VFGORLBC,
2022 hw_stats->last_gorlbc, hw_stats->gorlbc);
2024 /* Good Tx loopback packets */
2025 UPDATE_VF_STAT(E1000_VFGPTLBC,
2026 hw_stats->last_gptlbc, hw_stats->gptlbc);
2028 /* Good Tx loopback octets */
2029 UPDATE_VF_STAT(E1000_VFGOTLBC,
2030 hw_stats->last_gotlbc, hw_stats->gotlbc);
2033 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2034 struct rte_eth_xstat_name *xstats_names,
2035 __rte_unused unsigned limit)
2039 if (xstats_names != NULL)
2040 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2041 strlcpy(xstats_names[i].name,
2042 rte_igbvf_stats_strings[i].name,
2043 sizeof(xstats_names[i].name));
2045 return IGBVF_NB_XSTATS;
2049 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2052 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2054 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2057 if (n < IGBVF_NB_XSTATS)
2058 return IGBVF_NB_XSTATS;
2060 igbvf_read_stats_registers(hw, hw_stats);
2065 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2067 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2068 rte_igbvf_stats_strings[i].offset);
2071 return IGBVF_NB_XSTATS;
2075 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2077 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2079 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2081 igbvf_read_stats_registers(hw, hw_stats);
2083 if (rte_stats == NULL)
2086 rte_stats->ipackets = hw_stats->gprc;
2087 rte_stats->ibytes = hw_stats->gorc;
2088 rte_stats->opackets = hw_stats->gptc;
2089 rte_stats->obytes = hw_stats->gotc;
2094 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2096 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2097 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2099 /* Sync HW register to the last stats */
2100 eth_igbvf_stats_get(dev, NULL);
2102 /* reset HW current stats*/
2103 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2104 offsetof(struct e1000_vf_stats, gprc));
2110 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2113 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2114 struct e1000_fw_version fw;
2117 e1000_get_fw_version(hw, &fw);
2119 switch (hw->mac.type) {
2122 if (!(e1000_get_flash_presence_i210(hw))) {
2123 ret = snprintf(fw_version, fw_size,
2125 fw.invm_major, fw.invm_minor,
2131 /* if option rom is valid, display its version too */
2133 ret = snprintf(fw_version, fw_size,
2134 "%d.%d, 0x%08x, %d.%d.%d",
2135 fw.eep_major, fw.eep_minor, fw.etrack_id,
2136 fw.or_major, fw.or_build, fw.or_patch);
2139 if (fw.etrack_id != 0X0000) {
2140 ret = snprintf(fw_version, fw_size,
2142 fw.eep_major, fw.eep_minor,
2145 ret = snprintf(fw_version, fw_size,
2147 fw.eep_major, fw.eep_minor,
2156 ret += 1; /* add the size of '\0' */
2157 if (fw_size < (size_t)ret)
2164 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2166 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2169 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2170 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2171 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2172 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2173 dev_info->rx_queue_offload_capa;
2174 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2175 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2176 dev_info->tx_queue_offload_capa;
2178 switch (hw->mac.type) {
2180 dev_info->max_rx_queues = 4;
2181 dev_info->max_tx_queues = 4;
2182 dev_info->max_vmdq_pools = 0;
2186 dev_info->max_rx_queues = 16;
2187 dev_info->max_tx_queues = 16;
2188 dev_info->max_vmdq_pools = ETH_8_POOLS;
2189 dev_info->vmdq_queue_num = 16;
2193 dev_info->max_rx_queues = 8;
2194 dev_info->max_tx_queues = 8;
2195 dev_info->max_vmdq_pools = ETH_8_POOLS;
2196 dev_info->vmdq_queue_num = 8;
2200 dev_info->max_rx_queues = 8;
2201 dev_info->max_tx_queues = 8;
2202 dev_info->max_vmdq_pools = ETH_8_POOLS;
2203 dev_info->vmdq_queue_num = 8;
2207 dev_info->max_rx_queues = 8;
2208 dev_info->max_tx_queues = 8;
2212 dev_info->max_rx_queues = 4;
2213 dev_info->max_tx_queues = 4;
2214 dev_info->max_vmdq_pools = 0;
2218 dev_info->max_rx_queues = 2;
2219 dev_info->max_tx_queues = 2;
2220 dev_info->max_vmdq_pools = 0;
2224 /* Should not happen */
2227 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2228 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2229 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2231 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2233 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2234 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2235 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2237 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2242 dev_info->default_txconf = (struct rte_eth_txconf) {
2244 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2245 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2246 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2251 dev_info->rx_desc_lim = rx_desc_lim;
2252 dev_info->tx_desc_lim = tx_desc_lim;
2254 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2255 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2258 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2259 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2264 static const uint32_t *
2265 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2267 static const uint32_t ptypes[] = {
2268 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2271 RTE_PTYPE_L3_IPV4_EXT,
2273 RTE_PTYPE_L3_IPV6_EXT,
2277 RTE_PTYPE_TUNNEL_IP,
2278 RTE_PTYPE_INNER_L3_IPV6,
2279 RTE_PTYPE_INNER_L3_IPV6_EXT,
2280 RTE_PTYPE_INNER_L4_TCP,
2281 RTE_PTYPE_INNER_L4_UDP,
2285 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2286 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2292 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2294 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2297 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2298 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2299 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2300 DEV_TX_OFFLOAD_IPV4_CKSUM |
2301 DEV_TX_OFFLOAD_UDP_CKSUM |
2302 DEV_TX_OFFLOAD_TCP_CKSUM |
2303 DEV_TX_OFFLOAD_SCTP_CKSUM |
2304 DEV_TX_OFFLOAD_TCP_TSO;
2305 switch (hw->mac.type) {
2307 dev_info->max_rx_queues = 2;
2308 dev_info->max_tx_queues = 2;
2310 case e1000_vfadapt_i350:
2311 dev_info->max_rx_queues = 1;
2312 dev_info->max_tx_queues = 1;
2315 /* Should not happen */
2319 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2320 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2321 dev_info->rx_queue_offload_capa;
2322 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2323 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2324 dev_info->tx_queue_offload_capa;
2326 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2328 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2329 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2330 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2332 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2337 dev_info->default_txconf = (struct rte_eth_txconf) {
2339 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2340 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2341 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2346 dev_info->rx_desc_lim = rx_desc_lim;
2347 dev_info->tx_desc_lim = tx_desc_lim;
2352 /* return 0 means link status changed, -1 means not changed */
2354 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2356 struct e1000_hw *hw =
2357 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358 struct rte_eth_link link;
2359 int link_check, count;
2362 hw->mac.get_link_status = 1;
2364 /* possible wait-to-complete in up to 9 seconds */
2365 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2366 /* Read the real link status */
2367 switch (hw->phy.media_type) {
2368 case e1000_media_type_copper:
2369 /* Do the work to read phy */
2370 e1000_check_for_link(hw);
2371 link_check = !hw->mac.get_link_status;
2374 case e1000_media_type_fiber:
2375 e1000_check_for_link(hw);
2376 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2380 case e1000_media_type_internal_serdes:
2381 e1000_check_for_link(hw);
2382 link_check = hw->mac.serdes_has_link;
2385 /* VF device is type_unknown */
2386 case e1000_media_type_unknown:
2387 eth_igbvf_link_update(hw);
2388 link_check = !hw->mac.get_link_status;
2394 if (link_check || wait_to_complete == 0)
2396 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2398 memset(&link, 0, sizeof(link));
2400 /* Now we check if a transition has happened */
2402 uint16_t duplex, speed;
2403 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2404 link.link_duplex = (duplex == FULL_DUPLEX) ?
2405 ETH_LINK_FULL_DUPLEX :
2406 ETH_LINK_HALF_DUPLEX;
2407 link.link_speed = speed;
2408 link.link_status = ETH_LINK_UP;
2409 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2410 ETH_LINK_SPEED_FIXED);
2411 } else if (!link_check) {
2412 link.link_speed = 0;
2413 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2414 link.link_status = ETH_LINK_DOWN;
2415 link.link_autoneg = ETH_LINK_FIXED;
2418 return rte_eth_linkstatus_set(dev, &link);
2422 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2423 * For ASF and Pass Through versions of f/w this means
2424 * that the driver is loaded.
2427 igb_hw_control_acquire(struct e1000_hw *hw)
2431 /* Let firmware know the driver has taken over */
2432 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2433 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2437 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2438 * For ASF and Pass Through versions of f/w this means that the
2439 * driver is no longer loaded.
2442 igb_hw_control_release(struct e1000_hw *hw)
2446 /* Let firmware taken over control of h/w */
2447 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2448 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2449 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2453 * Bit of a misnomer, what this really means is
2454 * to enable OS management of the system... aka
2455 * to disable special hardware management features.
2458 igb_init_manageability(struct e1000_hw *hw)
2460 if (e1000_enable_mng_pass_thru(hw)) {
2461 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2462 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2464 /* disable hardware interception of ARP */
2465 manc &= ~(E1000_MANC_ARP_EN);
2467 /* enable receiving management packets to the host */
2468 manc |= E1000_MANC_EN_MNG2HOST;
2469 manc2h |= 1 << 5; /* Mng Port 623 */
2470 manc2h |= 1 << 6; /* Mng Port 664 */
2471 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2472 E1000_WRITE_REG(hw, E1000_MANC, manc);
2477 igb_release_manageability(struct e1000_hw *hw)
2479 if (e1000_enable_mng_pass_thru(hw)) {
2480 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2482 manc |= E1000_MANC_ARP_EN;
2483 manc &= ~E1000_MANC_EN_MNG2HOST;
2485 E1000_WRITE_REG(hw, E1000_MANC, manc);
2490 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2492 struct e1000_hw *hw =
2493 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496 rctl = E1000_READ_REG(hw, E1000_RCTL);
2497 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2498 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2504 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2506 struct e1000_hw *hw =
2507 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510 rctl = E1000_READ_REG(hw, E1000_RCTL);
2511 rctl &= (~E1000_RCTL_UPE);
2512 if (dev->data->all_multicast == 1)
2513 rctl |= E1000_RCTL_MPE;
2515 rctl &= (~E1000_RCTL_MPE);
2516 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2522 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2524 struct e1000_hw *hw =
2525 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2528 rctl = E1000_READ_REG(hw, E1000_RCTL);
2529 rctl |= E1000_RCTL_MPE;
2530 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2536 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2538 struct e1000_hw *hw =
2539 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2542 if (dev->data->promiscuous == 1)
2543 return 0; /* must remain in all_multicast mode */
2544 rctl = E1000_READ_REG(hw, E1000_RCTL);
2545 rctl &= (~E1000_RCTL_MPE);
2546 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2552 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2554 struct e1000_hw *hw =
2555 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2556 struct e1000_vfta * shadow_vfta =
2557 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2562 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2563 E1000_VFTA_ENTRY_MASK);
2564 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2565 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2570 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2572 /* update local VFTA copy */
2573 shadow_vfta->vfta[vid_idx] = vfta;
2579 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2580 enum rte_vlan_type vlan_type,
2583 struct e1000_hw *hw =
2584 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2587 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2588 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2590 /* only outer TPID of double VLAN can be configured*/
2591 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2592 reg = E1000_READ_REG(hw, E1000_VET);
2593 reg = (reg & (~E1000_VET_VET_EXT)) |
2594 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2595 E1000_WRITE_REG(hw, E1000_VET, reg);
2600 /* all other TPID values are read-only*/
2601 PMD_DRV_LOG(ERR, "Not supported");
2607 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2609 struct e1000_hw *hw =
2610 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613 /* Filter Table Disable */
2614 reg = E1000_READ_REG(hw, E1000_RCTL);
2615 reg &= ~E1000_RCTL_CFIEN;
2616 reg &= ~E1000_RCTL_VFE;
2617 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2621 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2623 struct e1000_hw *hw =
2624 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2625 struct e1000_vfta * shadow_vfta =
2626 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2630 /* Filter Table Enable, CFI not used for packet acceptance */
2631 reg = E1000_READ_REG(hw, E1000_RCTL);
2632 reg &= ~E1000_RCTL_CFIEN;
2633 reg |= E1000_RCTL_VFE;
2634 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2636 /* restore VFTA table */
2637 for (i = 0; i < IGB_VFTA_SIZE; i++)
2638 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2642 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2644 struct e1000_hw *hw =
2645 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2648 /* VLAN Mode Disable */
2649 reg = E1000_READ_REG(hw, E1000_CTRL);
2650 reg &= ~E1000_CTRL_VME;
2651 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2655 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2657 struct e1000_hw *hw =
2658 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2661 /* VLAN Mode Enable */
2662 reg = E1000_READ_REG(hw, E1000_CTRL);
2663 reg |= E1000_CTRL_VME;
2664 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2668 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2670 struct e1000_hw *hw =
2671 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2674 /* CTRL_EXT: Extended VLAN */
2675 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2676 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2677 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2679 /* Update maximum packet length */
2680 E1000_WRITE_REG(hw, E1000_RLPML, dev->data->mtu + E1000_ETH_OVERHEAD);
2684 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2686 struct e1000_hw *hw =
2687 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690 /* CTRL_EXT: Extended VLAN */
2691 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2692 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2693 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2695 /* Update maximum packet length */
2696 E1000_WRITE_REG(hw, E1000_RLPML,
2697 dev->data->mtu + E1000_ETH_OVERHEAD + VLAN_TAG_SIZE);
2701 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2703 struct rte_eth_rxmode *rxmode;
2705 rxmode = &dev->data->dev_conf.rxmode;
2706 if(mask & ETH_VLAN_STRIP_MASK){
2707 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2708 igb_vlan_hw_strip_enable(dev);
2710 igb_vlan_hw_strip_disable(dev);
2713 if(mask & ETH_VLAN_FILTER_MASK){
2714 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2715 igb_vlan_hw_filter_enable(dev);
2717 igb_vlan_hw_filter_disable(dev);
2720 if(mask & ETH_VLAN_EXTEND_MASK){
2721 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2722 igb_vlan_hw_extend_enable(dev);
2724 igb_vlan_hw_extend_disable(dev);
2732 * It enables the interrupt mask and then enable the interrupt.
2735 * Pointer to struct rte_eth_dev.
2740 * - On success, zero.
2741 * - On failure, a negative value.
2744 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2746 struct e1000_interrupt *intr =
2747 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2750 intr->mask |= E1000_ICR_LSC;
2752 intr->mask &= ~E1000_ICR_LSC;
2757 /* It clears the interrupt causes and enables the interrupt.
2758 * It will be called once only during nic initialized.
2761 * Pointer to struct rte_eth_dev.
2764 * - On success, zero.
2765 * - On failure, a negative value.
2767 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2769 uint32_t mask, regval;
2771 struct e1000_hw *hw =
2772 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2773 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2774 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2775 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2776 struct rte_eth_dev_info dev_info;
2778 memset(&dev_info, 0, sizeof(dev_info));
2779 ret = eth_igb_infos_get(dev, &dev_info);
2783 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2784 regval = E1000_READ_REG(hw, E1000_EIMS);
2785 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2791 * It reads ICR and gets interrupt causes, check it and set a bit flag
2792 * to update link status.
2795 * Pointer to struct rte_eth_dev.
2798 * - On success, zero.
2799 * - On failure, a negative value.
2802 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2805 struct e1000_hw *hw =
2806 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807 struct e1000_interrupt *intr =
2808 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2810 igb_intr_disable(dev);
2812 /* read-on-clear nic registers here */
2813 icr = E1000_READ_REG(hw, E1000_ICR);
2816 if (icr & E1000_ICR_LSC) {
2817 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2820 if (icr & E1000_ICR_VMMB)
2821 intr->flags |= E1000_FLAG_MAILBOX;
2827 * It executes link_update after knowing an interrupt is prsent.
2830 * Pointer to struct rte_eth_dev.
2833 * - On success, zero.
2834 * - On failure, a negative value.
2837 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2838 struct rte_intr_handle *intr_handle)
2840 struct e1000_hw *hw =
2841 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 struct e1000_interrupt *intr =
2843 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2844 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2845 struct rte_eth_link link;
2848 if (intr->flags & E1000_FLAG_MAILBOX) {
2849 igb_pf_mbx_process(dev);
2850 intr->flags &= ~E1000_FLAG_MAILBOX;
2853 igb_intr_enable(dev);
2854 rte_intr_ack(intr_handle);
2856 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2857 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2859 /* set get_link_status to check register later */
2860 hw->mac.get_link_status = 1;
2861 ret = eth_igb_link_update(dev, 0);
2863 /* check if link has changed */
2867 rte_eth_linkstatus_get(dev, &link);
2868 if (link.link_status) {
2870 " Port %d: Link Up - speed %u Mbps - %s",
2872 (unsigned)link.link_speed,
2873 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2874 "full-duplex" : "half-duplex");
2876 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2877 dev->data->port_id);
2880 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2881 pci_dev->addr.domain,
2883 pci_dev->addr.devid,
2884 pci_dev->addr.function);
2885 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2892 * Interrupt handler which shall be registered at first.
2895 * Pointer to interrupt handle.
2897 * The address of parameter (struct rte_eth_dev *) regsitered before.
2903 eth_igb_interrupt_handler(void *param)
2905 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2907 eth_igb_interrupt_get_status(dev);
2908 eth_igb_interrupt_action(dev, dev->intr_handle);
2912 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2915 struct e1000_hw *hw =
2916 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2917 struct e1000_interrupt *intr =
2918 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2920 igbvf_intr_disable(hw);
2922 /* read-on-clear nic registers here */
2923 eicr = E1000_READ_REG(hw, E1000_EICR);
2926 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2927 intr->flags |= E1000_FLAG_MAILBOX;
2932 void igbvf_mbx_process(struct rte_eth_dev *dev)
2934 struct e1000_hw *hw =
2935 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936 struct e1000_mbx_info *mbx = &hw->mbx;
2939 /* peek the message first */
2940 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2942 /* PF reset VF event */
2943 if (in_msg == E1000_PF_CONTROL_MSG) {
2944 /* dummy mbx read to ack pf */
2945 if (mbx->ops.read(hw, &in_msg, 1, 0))
2947 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2953 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2955 struct e1000_interrupt *intr =
2956 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2958 if (intr->flags & E1000_FLAG_MAILBOX) {
2959 igbvf_mbx_process(dev);
2960 intr->flags &= ~E1000_FLAG_MAILBOX;
2963 igbvf_intr_enable(dev);
2964 rte_intr_ack(intr_handle);
2970 eth_igbvf_interrupt_handler(void *param)
2972 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2974 eth_igbvf_interrupt_get_status(dev);
2975 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2979 eth_igb_led_on(struct rte_eth_dev *dev)
2981 struct e1000_hw *hw;
2983 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2988 eth_igb_led_off(struct rte_eth_dev *dev)
2990 struct e1000_hw *hw;
2992 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2993 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2997 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2999 struct e1000_hw *hw;
3004 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3005 fc_conf->pause_time = hw->fc.pause_time;
3006 fc_conf->high_water = hw->fc.high_water;
3007 fc_conf->low_water = hw->fc.low_water;
3008 fc_conf->send_xon = hw->fc.send_xon;
3009 fc_conf->autoneg = hw->mac.autoneg;
3012 * Return rx_pause and tx_pause status according to actual setting of
3013 * the TFCE and RFCE bits in the CTRL register.
3015 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3016 if (ctrl & E1000_CTRL_TFCE)
3021 if (ctrl & E1000_CTRL_RFCE)
3026 if (rx_pause && tx_pause)
3027 fc_conf->mode = RTE_FC_FULL;
3029 fc_conf->mode = RTE_FC_RX_PAUSE;
3031 fc_conf->mode = RTE_FC_TX_PAUSE;
3033 fc_conf->mode = RTE_FC_NONE;
3039 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3041 struct e1000_hw *hw;
3043 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3049 uint32_t rx_buf_size;
3050 uint32_t max_high_water;
3054 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3055 if (fc_conf->autoneg != hw->mac.autoneg)
3057 rx_buf_size = igb_get_rx_buffer_size(hw);
3058 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3060 /* At least reserve one Ethernet frame for watermark */
3061 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3062 if ((fc_conf->high_water > max_high_water) ||
3063 (fc_conf->high_water < fc_conf->low_water)) {
3064 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3065 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3069 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3070 hw->fc.pause_time = fc_conf->pause_time;
3071 hw->fc.high_water = fc_conf->high_water;
3072 hw->fc.low_water = fc_conf->low_water;
3073 hw->fc.send_xon = fc_conf->send_xon;
3075 err = e1000_setup_link_generic(hw);
3076 if (err == E1000_SUCCESS) {
3078 /* check if we want to forward MAC frames - driver doesn't have native
3079 * capability to do that, so we'll write the registers ourselves */
3081 rctl = E1000_READ_REG(hw, E1000_RCTL);
3083 /* set or clear MFLCN.PMCF bit depending on configuration */
3084 if (fc_conf->mac_ctrl_frame_fwd != 0)
3085 rctl |= E1000_RCTL_PMCF;
3087 rctl &= ~E1000_RCTL_PMCF;
3089 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3092 * check if we want to change flow control mode - driver doesn't have native
3093 * capability to do that, so we'll write the registers ourselves
3095 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3098 * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits depending
3101 switch (fc_conf->mode) {
3103 ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE;
3105 case RTE_FC_RX_PAUSE:
3106 ctrl |= E1000_CTRL_RFCE;
3107 ctrl &= ~E1000_CTRL_TFCE;
3109 case RTE_FC_TX_PAUSE:
3110 ctrl |= E1000_CTRL_TFCE;
3111 ctrl &= ~E1000_CTRL_RFCE;
3114 ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE;
3117 PMD_INIT_LOG(ERR, "invalid flow control mode");
3121 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3123 E1000_WRITE_FLUSH(hw);
3128 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3132 #define E1000_RAH_POOLSEL_SHIFT (18)
3134 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3135 uint32_t index, uint32_t pool)
3137 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3140 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3141 rah = E1000_READ_REG(hw, E1000_RAH(index));
3142 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3143 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3148 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3150 uint8_t addr[RTE_ETHER_ADDR_LEN];
3151 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153 memset(addr, 0, sizeof(addr));
3155 e1000_rar_set(hw, addr, index);
3159 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3160 struct rte_ether_addr *addr)
3162 eth_igb_rar_clear(dev, 0);
3163 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3168 * Virtual Function operations
3171 igbvf_intr_disable(struct e1000_hw *hw)
3173 PMD_INIT_FUNC_TRACE();
3175 /* Clear interrupt mask to stop from interrupts being generated */
3176 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3178 E1000_WRITE_FLUSH(hw);
3182 igbvf_stop_adapter(struct rte_eth_dev *dev)
3186 struct rte_eth_dev_info dev_info;
3187 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190 memset(&dev_info, 0, sizeof(dev_info));
3191 ret = eth_igbvf_infos_get(dev, &dev_info);
3195 /* Clear interrupt mask to stop from interrupts being generated */
3196 igbvf_intr_disable(hw);
3198 /* Clear any pending interrupts, flush previous writes */
3199 E1000_READ_REG(hw, E1000_EICR);
3201 /* Disable the transmit unit. Each queue must be disabled. */
3202 for (i = 0; i < dev_info.max_tx_queues; i++)
3203 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3205 /* Disable the receive unit by stopping each queue */
3206 for (i = 0; i < dev_info.max_rx_queues; i++) {
3207 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3208 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3209 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3210 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3214 /* flush all queues disables */
3215 E1000_WRITE_FLUSH(hw);
3219 static int eth_igbvf_link_update(struct e1000_hw *hw)
3221 struct e1000_mbx_info *mbx = &hw->mbx;
3222 struct e1000_mac_info *mac = &hw->mac;
3223 int ret_val = E1000_SUCCESS;
3225 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3228 * We only want to run this if there has been a rst asserted.
3229 * in this case that could mean a link change, device reset,
3230 * or a virtual function reset
3233 /* If we were hit with a reset or timeout drop the link */
3234 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3235 mac->get_link_status = TRUE;
3237 if (!mac->get_link_status)
3240 /* if link status is down no point in checking to see if pf is up */
3241 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3244 /* if we passed all the tests above then the link is up and we no
3245 * longer need to check for link */
3246 mac->get_link_status = FALSE;
3254 igbvf_dev_configure(struct rte_eth_dev *dev)
3256 struct rte_eth_conf* conf = &dev->data->dev_conf;
3258 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3259 dev->data->port_id);
3261 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3262 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3265 * VF has no ability to enable/disable HW CRC
3266 * Keep the persistent behavior the same as Host PF
3268 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3269 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3270 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3271 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3274 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3275 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3276 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3284 igbvf_dev_start(struct rte_eth_dev *dev)
3286 struct e1000_hw *hw =
3287 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288 struct e1000_adapter *adapter =
3289 E1000_DEV_PRIVATE(dev->data->dev_private);
3290 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3291 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3293 uint32_t intr_vector = 0;
3295 PMD_INIT_FUNC_TRACE();
3297 hw->mac.ops.reset_hw(hw);
3298 adapter->stopped = 0;
3301 igbvf_set_vfta_all(dev,1);
3303 eth_igbvf_tx_init(dev);
3305 /* This can fail when allocating mbufs for descriptor rings */
3306 ret = eth_igbvf_rx_init(dev);
3308 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3309 igb_dev_clear_queues(dev);
3313 /* check and configure queue intr-vector mapping */
3314 if (rte_intr_cap_multiple(intr_handle) &&
3315 dev->data->dev_conf.intr_conf.rxq) {
3316 intr_vector = dev->data->nb_rx_queues;
3317 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3322 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3323 intr_handle->intr_vec =
3324 rte_zmalloc("intr_vec",
3325 dev->data->nb_rx_queues * sizeof(int), 0);
3326 if (!intr_handle->intr_vec) {
3327 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3328 " intr_vec", dev->data->nb_rx_queues);
3333 eth_igbvf_configure_msix_intr(dev);
3335 /* enable uio/vfio intr/eventfd mapping */
3336 rte_intr_enable(intr_handle);
3338 /* resume enabled intr since hw reset */
3339 igbvf_intr_enable(dev);
3345 igbvf_dev_stop(struct rte_eth_dev *dev)
3347 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3348 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3349 struct e1000_adapter *adapter =
3350 E1000_DEV_PRIVATE(dev->data->dev_private);
3352 if (adapter->stopped)
3355 PMD_INIT_FUNC_TRACE();
3357 igbvf_stop_adapter(dev);
3360 * Clear what we set, but we still keep shadow_vfta to
3361 * restore after device starts
3363 igbvf_set_vfta_all(dev,0);
3365 igb_dev_clear_queues(dev);
3367 /* disable intr eventfd mapping */
3368 rte_intr_disable(intr_handle);
3370 /* Clean datapath event and queue/vec mapping */
3371 rte_intr_efd_disable(intr_handle);
3372 if (intr_handle->intr_vec) {
3373 rte_free(intr_handle->intr_vec);
3374 intr_handle->intr_vec = NULL;
3377 adapter->stopped = true;
3378 dev->data->dev_started = 0;
3384 igbvf_dev_close(struct rte_eth_dev *dev)
3386 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3387 struct rte_ether_addr addr;
3388 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3391 PMD_INIT_FUNC_TRACE();
3393 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3398 ret = igbvf_dev_stop(dev);
3402 igb_dev_free_queues(dev);
3405 * reprogram the RAR with a zero mac address,
3406 * to ensure that the VF traffic goes to the PF
3407 * after stop, close and detach of the VF.
3410 memset(&addr, 0, sizeof(addr));
3411 igbvf_default_mac_addr_set(dev, &addr);
3413 rte_intr_callback_unregister(&pci_dev->intr_handle,
3414 eth_igbvf_interrupt_handler,
3421 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3423 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425 /* Set both unicast and multicast promisc */
3426 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3432 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3434 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3436 /* If in allmulticast mode leave multicast promisc */
3437 if (dev->data->all_multicast == 1)
3438 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3440 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3446 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3448 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3450 /* In promiscuous mode multicast promisc already set */
3451 if (dev->data->promiscuous == 0)
3452 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3458 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3460 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462 /* In promiscuous mode leave multicast promisc enabled */
3463 if (dev->data->promiscuous == 0)
3464 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3469 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3471 struct e1000_mbx_info *mbx = &hw->mbx;
3475 /* After set vlan, vlan strip will also be enabled in igb driver*/
3476 msgbuf[0] = E1000_VF_SET_VLAN;
3478 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3480 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3482 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3486 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3490 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3491 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3498 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3500 struct e1000_hw *hw =
3501 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3502 struct e1000_vfta * shadow_vfta =
3503 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3504 int i = 0, j = 0, vfta = 0, mask = 1;
3506 for (i = 0; i < IGB_VFTA_SIZE; i++){
3507 vfta = shadow_vfta->vfta[i];
3510 for (j = 0; j < 32; j++){
3513 (uint16_t)((i<<5)+j), on);
3522 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3524 struct e1000_hw *hw =
3525 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3526 struct e1000_vfta * shadow_vfta =
3527 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3528 uint32_t vid_idx = 0;
3529 uint32_t vid_bit = 0;
3532 PMD_INIT_FUNC_TRACE();
3534 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3535 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3537 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3540 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3541 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3543 /*Save what we set and retore it after device reset*/
3545 shadow_vfta->vfta[vid_idx] |= vid_bit;
3547 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3553 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3555 struct e1000_hw *hw =
3556 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3558 /* index is not used by rar_set() */
3559 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3565 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3566 struct rte_eth_rss_reta_entry64 *reta_conf,
3571 uint16_t idx, shift;
3572 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3574 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3575 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3576 "(%d) doesn't match the number hardware can supported "
3577 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3581 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3582 idx = i / RTE_RETA_GROUP_SIZE;
3583 shift = i % RTE_RETA_GROUP_SIZE;
3584 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3588 if (mask == IGB_4_BIT_MASK)
3591 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3592 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3593 if (mask & (0x1 << j))
3594 reta |= reta_conf[idx].reta[shift + j] <<
3597 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3599 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3606 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3607 struct rte_eth_rss_reta_entry64 *reta_conf,
3612 uint16_t idx, shift;
3613 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3616 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3617 "(%d) doesn't match the number hardware can supported "
3618 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3622 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3623 idx = i / RTE_RETA_GROUP_SIZE;
3624 shift = i % RTE_RETA_GROUP_SIZE;
3625 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3629 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3630 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3631 if (mask & (0x1 << j))
3632 reta_conf[idx].reta[shift + j] =
3633 ((reta >> (CHAR_BIT * j)) &
3642 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3643 struct rte_eth_syn_filter *filter,
3646 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3647 struct e1000_filter_info *filter_info =
3648 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3649 uint32_t synqf, rfctl;
3651 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3654 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3657 if (synqf & E1000_SYN_FILTER_ENABLE)
3660 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3661 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3663 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3664 if (filter->hig_pri)
3665 rfctl |= E1000_RFCTL_SYNQFP;
3667 rfctl &= ~E1000_RFCTL_SYNQFP;
3669 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3671 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3676 filter_info->syn_info = synqf;
3677 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3678 E1000_WRITE_FLUSH(hw);
3682 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3684 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3685 struct e1000_2tuple_filter_info *filter_info)
3687 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3689 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3690 return -EINVAL; /* filter index is out of range. */
3691 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3692 return -EINVAL; /* flags is invalid. */
3694 switch (filter->dst_port_mask) {
3696 filter_info->dst_port_mask = 0;
3697 filter_info->dst_port = filter->dst_port;
3700 filter_info->dst_port_mask = 1;
3703 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3707 switch (filter->proto_mask) {
3709 filter_info->proto_mask = 0;
3710 filter_info->proto = filter->proto;
3713 filter_info->proto_mask = 1;
3716 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3720 filter_info->priority = (uint8_t)filter->priority;
3721 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3722 filter_info->tcp_flags = filter->tcp_flags;
3724 filter_info->tcp_flags = 0;
3729 static inline struct e1000_2tuple_filter *
3730 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3731 struct e1000_2tuple_filter_info *key)
3733 struct e1000_2tuple_filter *it;
3735 TAILQ_FOREACH(it, filter_list, entries) {
3736 if (memcmp(key, &it->filter_info,
3737 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3744 /* inject a igb 2tuple filter to HW */
3746 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3747 struct e1000_2tuple_filter *filter)
3749 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3750 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3751 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3755 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3756 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3757 imir |= E1000_IMIR_PORT_BP;
3759 imir &= ~E1000_IMIR_PORT_BP;
3761 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3763 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3764 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3765 ttqf |= (uint32_t)(filter->filter_info.proto &
3766 E1000_TTQF_PROTOCOL_MASK);
3767 if (filter->filter_info.proto_mask == 0)
3768 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3770 /* tcp flags bits setting. */
3771 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3772 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3773 imir_ext |= E1000_IMIREXT_CTRL_URG;
3774 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3775 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3776 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3777 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3778 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3779 imir_ext |= E1000_IMIREXT_CTRL_RST;
3780 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3781 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3782 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3783 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3785 imir_ext |= E1000_IMIREXT_CTRL_BP;
3787 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3788 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3789 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3793 * igb_add_2tuple_filter - add a 2tuple filter
3796 * dev: Pointer to struct rte_eth_dev.
3797 * ntuple_filter: ponter to the filter that will be added.
3800 * - On success, zero.
3801 * - On failure, a negative value.
3804 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3805 struct rte_eth_ntuple_filter *ntuple_filter)
3807 struct e1000_filter_info *filter_info =
3808 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3809 struct e1000_2tuple_filter *filter;
3812 filter = rte_zmalloc("e1000_2tuple_filter",
3813 sizeof(struct e1000_2tuple_filter), 0);
3817 ret = ntuple_filter_to_2tuple(ntuple_filter,
3818 &filter->filter_info);
3823 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3824 &filter->filter_info) != NULL) {
3825 PMD_DRV_LOG(ERR, "filter exists.");
3829 filter->queue = ntuple_filter->queue;
3832 * look for an unused 2tuple filter index,
3833 * and insert the filter to list.
3835 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3836 if (!(filter_info->twotuple_mask & (1 << i))) {
3837 filter_info->twotuple_mask |= 1 << i;
3839 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3845 if (i >= E1000_MAX_TTQF_FILTERS) {
3846 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3851 igb_inject_2uple_filter(dev, filter);
3856 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3857 struct e1000_2tuple_filter *filter)
3859 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3860 struct e1000_filter_info *filter_info =
3861 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3863 filter_info->twotuple_mask &= ~(1 << filter->index);
3864 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3867 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3868 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3869 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3874 * igb_remove_2tuple_filter - remove a 2tuple filter
3877 * dev: Pointer to struct rte_eth_dev.
3878 * ntuple_filter: ponter to the filter that will be removed.
3881 * - On success, zero.
3882 * - On failure, a negative value.
3885 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3886 struct rte_eth_ntuple_filter *ntuple_filter)
3888 struct e1000_filter_info *filter_info =
3889 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3890 struct e1000_2tuple_filter_info filter_2tuple;
3891 struct e1000_2tuple_filter *filter;
3894 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3895 ret = ntuple_filter_to_2tuple(ntuple_filter,
3900 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3902 if (filter == NULL) {
3903 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3907 igb_delete_2tuple_filter(dev, filter);
3912 /* inject a igb flex filter to HW */
3914 igb_inject_flex_filter(struct rte_eth_dev *dev,
3915 struct e1000_flex_filter *filter)
3917 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3918 uint32_t wufc, queueing;
3922 wufc = E1000_READ_REG(hw, E1000_WUFC);
3923 if (filter->index < E1000_MAX_FHFT)
3924 reg_off = E1000_FHFT(filter->index);
3926 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3928 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3929 (E1000_WUFC_FLX0 << filter->index));
3930 queueing = filter->filter_info.len |
3931 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3932 (filter->filter_info.priority <<
3933 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3934 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3937 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3938 E1000_WRITE_REG(hw, reg_off,
3939 filter->filter_info.dwords[j]);
3940 reg_off += sizeof(uint32_t);
3941 E1000_WRITE_REG(hw, reg_off,
3942 filter->filter_info.dwords[++j]);
3943 reg_off += sizeof(uint32_t);
3944 E1000_WRITE_REG(hw, reg_off,
3945 (uint32_t)filter->filter_info.mask[i]);
3946 reg_off += sizeof(uint32_t) * 2;
3951 static inline struct e1000_flex_filter *
3952 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3953 struct e1000_flex_filter_info *key)
3955 struct e1000_flex_filter *it;
3957 TAILQ_FOREACH(it, filter_list, entries) {
3958 if (memcmp(key, &it->filter_info,
3959 sizeof(struct e1000_flex_filter_info)) == 0)
3966 /* remove a flex byte filter
3968 * dev: Pointer to struct rte_eth_dev.
3969 * filter: the pointer of the filter will be removed.
3972 igb_remove_flex_filter(struct rte_eth_dev *dev,
3973 struct e1000_flex_filter *filter)
3975 struct e1000_filter_info *filter_info =
3976 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3977 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3981 wufc = E1000_READ_REG(hw, E1000_WUFC);
3982 if (filter->index < E1000_MAX_FHFT)
3983 reg_off = E1000_FHFT(filter->index);
3985 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3987 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3988 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3990 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3991 (~(E1000_WUFC_FLX0 << filter->index)));
3993 filter_info->flex_mask &= ~(1 << filter->index);
3994 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3999 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4000 struct igb_flex_filter *filter,
4003 struct e1000_filter_info *filter_info =
4004 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4005 struct e1000_flex_filter *flex_filter, *it;
4009 flex_filter = rte_zmalloc("e1000_flex_filter",
4010 sizeof(struct e1000_flex_filter), 0);
4011 if (flex_filter == NULL)
4014 flex_filter->filter_info.len = filter->len;
4015 flex_filter->filter_info.priority = filter->priority;
4016 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4017 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4019 /* reverse bits in flex filter's mask*/
4020 for (shift = 0; shift < CHAR_BIT; shift++) {
4021 if (filter->mask[i] & (0x01 << shift))
4022 mask |= (0x80 >> shift);
4024 flex_filter->filter_info.mask[i] = mask;
4027 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4028 &flex_filter->filter_info);
4029 if (it == NULL && !add) {
4030 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4031 rte_free(flex_filter);
4034 if (it != NULL && add) {
4035 PMD_DRV_LOG(ERR, "filter exists.");
4036 rte_free(flex_filter);
4041 flex_filter->queue = filter->queue;
4043 * look for an unused flex filter index
4044 * and insert the filter into the list.
4046 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4047 if (!(filter_info->flex_mask & (1 << i))) {
4048 filter_info->flex_mask |= 1 << i;
4049 flex_filter->index = i;
4050 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4056 if (i >= E1000_MAX_FLEX_FILTERS) {
4057 PMD_DRV_LOG(ERR, "flex filters are full.");
4058 rte_free(flex_filter);
4062 igb_inject_flex_filter(dev, flex_filter);
4065 igb_remove_flex_filter(dev, it);
4066 rte_free(flex_filter);
4072 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4074 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4075 struct e1000_5tuple_filter_info *filter_info)
4077 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4079 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4080 return -EINVAL; /* filter index is out of range. */
4081 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4082 return -EINVAL; /* flags is invalid. */
4084 switch (filter->dst_ip_mask) {
4086 filter_info->dst_ip_mask = 0;
4087 filter_info->dst_ip = filter->dst_ip;
4090 filter_info->dst_ip_mask = 1;
4093 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4097 switch (filter->src_ip_mask) {
4099 filter_info->src_ip_mask = 0;
4100 filter_info->src_ip = filter->src_ip;
4103 filter_info->src_ip_mask = 1;
4106 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4110 switch (filter->dst_port_mask) {
4112 filter_info->dst_port_mask = 0;
4113 filter_info->dst_port = filter->dst_port;
4116 filter_info->dst_port_mask = 1;
4119 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4123 switch (filter->src_port_mask) {
4125 filter_info->src_port_mask = 0;
4126 filter_info->src_port = filter->src_port;
4129 filter_info->src_port_mask = 1;
4132 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4136 switch (filter->proto_mask) {
4138 filter_info->proto_mask = 0;
4139 filter_info->proto = filter->proto;
4142 filter_info->proto_mask = 1;
4145 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4149 filter_info->priority = (uint8_t)filter->priority;
4150 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4151 filter_info->tcp_flags = filter->tcp_flags;
4153 filter_info->tcp_flags = 0;
4158 static inline struct e1000_5tuple_filter *
4159 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4160 struct e1000_5tuple_filter_info *key)
4162 struct e1000_5tuple_filter *it;
4164 TAILQ_FOREACH(it, filter_list, entries) {
4165 if (memcmp(key, &it->filter_info,
4166 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4173 /* inject a igb 5-tuple filter to HW */
4175 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4176 struct e1000_5tuple_filter *filter)
4178 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4179 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4180 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4184 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4185 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4186 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4187 if (filter->filter_info.dst_ip_mask == 0)
4188 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4189 if (filter->filter_info.src_port_mask == 0)
4190 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4191 if (filter->filter_info.proto_mask == 0)
4192 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4193 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4194 E1000_FTQF_QUEUE_MASK;
4195 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4196 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4197 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4198 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4200 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4201 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4203 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4204 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4205 imir |= E1000_IMIR_PORT_BP;
4207 imir &= ~E1000_IMIR_PORT_BP;
4208 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4210 /* tcp flags bits setting. */
4211 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4212 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4213 imir_ext |= E1000_IMIREXT_CTRL_URG;
4214 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4215 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4216 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4217 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4218 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4219 imir_ext |= E1000_IMIREXT_CTRL_RST;
4220 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4221 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4222 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4223 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4225 imir_ext |= E1000_IMIREXT_CTRL_BP;
4227 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4228 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4232 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4235 * dev: Pointer to struct rte_eth_dev.
4236 * ntuple_filter: ponter to the filter that will be added.
4239 * - On success, zero.
4240 * - On failure, a negative value.
4243 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4244 struct rte_eth_ntuple_filter *ntuple_filter)
4246 struct e1000_filter_info *filter_info =
4247 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4248 struct e1000_5tuple_filter *filter;
4252 filter = rte_zmalloc("e1000_5tuple_filter",
4253 sizeof(struct e1000_5tuple_filter), 0);
4257 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4258 &filter->filter_info);
4264 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4265 &filter->filter_info) != NULL) {
4266 PMD_DRV_LOG(ERR, "filter exists.");
4270 filter->queue = ntuple_filter->queue;
4273 * look for an unused 5tuple filter index,
4274 * and insert the filter to list.
4276 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4277 if (!(filter_info->fivetuple_mask & (1 << i))) {
4278 filter_info->fivetuple_mask |= 1 << i;
4280 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4286 if (i >= E1000_MAX_FTQF_FILTERS) {
4287 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4292 igb_inject_5tuple_filter_82576(dev, filter);
4297 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4298 struct e1000_5tuple_filter *filter)
4300 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4301 struct e1000_filter_info *filter_info =
4302 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4304 filter_info->fivetuple_mask &= ~(1 << filter->index);
4305 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4308 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4309 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4310 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4311 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4312 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4313 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4314 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4319 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4322 * dev: Pointer to struct rte_eth_dev.
4323 * ntuple_filter: ponter to the filter that will be removed.
4326 * - On success, zero.
4327 * - On failure, a negative value.
4330 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4331 struct rte_eth_ntuple_filter *ntuple_filter)
4333 struct e1000_filter_info *filter_info =
4334 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4335 struct e1000_5tuple_filter_info filter_5tuple;
4336 struct e1000_5tuple_filter *filter;
4339 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4340 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4345 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4347 if (filter == NULL) {
4348 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4352 igb_delete_5tuple_filter_82576(dev, filter);
4358 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4361 struct e1000_hw *hw;
4362 struct rte_eth_dev_info dev_info;
4363 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4366 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4368 #ifdef RTE_LIBRTE_82571_SUPPORT
4369 /* XXX: not bigger than max_rx_pktlen */
4370 if (hw->mac.type == e1000_82571)
4373 ret = eth_igb_infos_get(dev, &dev_info);
4377 /* check that mtu is within the allowed range */
4378 if (mtu < RTE_ETHER_MIN_MTU ||
4379 frame_size > dev_info.max_rx_pktlen)
4383 * If device is started, refuse mtu that requires the support of
4384 * scattered packets when this feature has not been enabled before.
4386 if (dev->data->dev_started && !dev->data->scattered_rx &&
4387 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
4388 PMD_INIT_LOG(ERR, "Stop port first.");
4392 rctl = E1000_READ_REG(hw, E1000_RCTL);
4394 /* switch to jumbo mode if needed */
4395 if (mtu > RTE_ETHER_MTU)
4396 rctl |= E1000_RCTL_LPE;
4398 rctl &= ~E1000_RCTL_LPE;
4399 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4401 E1000_WRITE_REG(hw, E1000_RLPML, frame_size);
4407 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4410 * dev: Pointer to struct rte_eth_dev.
4411 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4412 * add: if true, add filter, if false, remove filter
4415 * - On success, zero.
4416 * - On failure, a negative value.
4419 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4420 struct rte_eth_ntuple_filter *ntuple_filter,
4423 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426 switch (ntuple_filter->flags) {
4427 case RTE_5TUPLE_FLAGS:
4428 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4429 if (hw->mac.type != e1000_82576)
4432 ret = igb_add_5tuple_filter_82576(dev,
4435 ret = igb_remove_5tuple_filter_82576(dev,
4438 case RTE_2TUPLE_FLAGS:
4439 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4440 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4441 hw->mac.type != e1000_i210 &&
4442 hw->mac.type != e1000_i211)
4445 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4447 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4458 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4463 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4464 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4465 (filter_info->ethertype_mask & (1 << i)))
4472 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4473 uint16_t ethertype, uint32_t etqf)
4477 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4478 if (!(filter_info->ethertype_mask & (1 << i))) {
4479 filter_info->ethertype_mask |= 1 << i;
4480 filter_info->ethertype_filters[i].ethertype = ethertype;
4481 filter_info->ethertype_filters[i].etqf = etqf;
4489 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4492 if (idx >= E1000_MAX_ETQF_FILTERS)
4494 filter_info->ethertype_mask &= ~(1 << idx);
4495 filter_info->ethertype_filters[idx].ethertype = 0;
4496 filter_info->ethertype_filters[idx].etqf = 0;
4502 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4503 struct rte_eth_ethertype_filter *filter,
4506 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4507 struct e1000_filter_info *filter_info =
4508 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4512 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4513 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4514 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4515 " ethertype filter.", filter->ether_type);
4519 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4520 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4523 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4524 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4528 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4529 if (ret >= 0 && add) {
4530 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4531 filter->ether_type);
4534 if (ret < 0 && !add) {
4535 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4536 filter->ether_type);
4541 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4542 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4543 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4544 ret = igb_ethertype_filter_insert(filter_info,
4545 filter->ether_type, etqf);
4547 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4551 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4555 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4556 E1000_WRITE_FLUSH(hw);
4562 eth_igb_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
4563 const struct rte_flow_ops **ops)
4565 *ops = &igb_flow_ops;
4570 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4571 struct rte_ether_addr *mc_addr_set,
4572 uint32_t nb_mc_addr)
4574 struct e1000_hw *hw;
4576 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4577 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4582 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4584 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4585 uint64_t systime_cycles;
4587 switch (hw->mac.type) {
4591 * Need to read System Time Residue Register to be able
4592 * to read the other two registers.
4594 E1000_READ_REG(hw, E1000_SYSTIMR);
4595 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4596 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4597 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4604 * Need to read System Time Residue Register to be able
4605 * to read the other two registers.
4607 E1000_READ_REG(hw, E1000_SYSTIMR);
4608 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4609 /* Only the 8 LSB are valid. */
4610 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4614 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4615 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4620 return systime_cycles;
4624 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4626 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627 uint64_t rx_tstamp_cycles;
4629 switch (hw->mac.type) {
4632 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4633 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4634 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4640 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4641 /* Only the 8 LSB are valid. */
4642 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4646 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4647 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4652 return rx_tstamp_cycles;
4656 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4658 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4659 uint64_t tx_tstamp_cycles;
4661 switch (hw->mac.type) {
4664 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4665 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4666 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4672 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4673 /* Only the 8 LSB are valid. */
4674 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4678 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4679 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4684 return tx_tstamp_cycles;
4688 igb_start_timecounters(struct rte_eth_dev *dev)
4690 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4691 struct e1000_adapter *adapter = dev->data->dev_private;
4692 uint32_t incval = 1;
4694 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4696 switch (hw->mac.type) {
4700 /* 32 LSB bits + 8 MSB bits = 40 bits */
4701 mask = (1ULL << 40) - 1;
4706 * Start incrementing the register
4707 * used to timestamp PTP packets.
4709 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4712 incval = E1000_INCVALUE_82576;
4713 shift = IGB_82576_TSYNC_SHIFT;
4714 E1000_WRITE_REG(hw, E1000_TIMINCA,
4715 E1000_INCPERIOD_82576 | incval);
4722 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4723 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4724 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4726 adapter->systime_tc.cc_mask = mask;
4727 adapter->systime_tc.cc_shift = shift;
4728 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4730 adapter->rx_tstamp_tc.cc_mask = mask;
4731 adapter->rx_tstamp_tc.cc_shift = shift;
4732 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4734 adapter->tx_tstamp_tc.cc_mask = mask;
4735 adapter->tx_tstamp_tc.cc_shift = shift;
4736 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4740 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4742 struct e1000_adapter *adapter = dev->data->dev_private;
4744 adapter->systime_tc.nsec += delta;
4745 adapter->rx_tstamp_tc.nsec += delta;
4746 adapter->tx_tstamp_tc.nsec += delta;
4752 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4755 struct e1000_adapter *adapter = dev->data->dev_private;
4757 ns = rte_timespec_to_ns(ts);
4759 /* Set the timecounters to a new value. */
4760 adapter->systime_tc.nsec = ns;
4761 adapter->rx_tstamp_tc.nsec = ns;
4762 adapter->tx_tstamp_tc.nsec = ns;
4768 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4770 uint64_t ns, systime_cycles;
4771 struct e1000_adapter *adapter = dev->data->dev_private;
4773 systime_cycles = igb_read_systime_cyclecounter(dev);
4774 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4775 *ts = rte_ns_to_timespec(ns);
4781 igb_timesync_enable(struct rte_eth_dev *dev)
4783 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4787 /* Stop the timesync system time. */
4788 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4789 /* Reset the timesync system time value. */
4790 switch (hw->mac.type) {
4796 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4799 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4800 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4803 /* Not supported. */
4807 /* Enable system time for it isn't on by default. */
4808 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4809 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4810 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4812 igb_start_timecounters(dev);
4814 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4815 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4816 (RTE_ETHER_TYPE_1588 |
4817 E1000_ETQF_FILTER_ENABLE |
4820 /* Enable timestamping of received PTP packets. */
4821 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4822 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4823 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4825 /* Enable Timestamping of transmitted PTP packets. */
4826 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4827 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4828 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4834 igb_timesync_disable(struct rte_eth_dev *dev)
4836 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839 /* Disable timestamping of transmitted PTP packets. */
4840 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4841 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4842 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4844 /* Disable timestamping of received PTP packets. */
4845 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4846 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4847 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4849 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4850 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4852 /* Stop incrementating the System Time registers. */
4853 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4859 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4860 struct timespec *timestamp,
4861 uint32_t flags __rte_unused)
4863 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4864 struct e1000_adapter *adapter = dev->data->dev_private;
4865 uint32_t tsync_rxctl;
4866 uint64_t rx_tstamp_cycles;
4869 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4870 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4873 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4874 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4875 *timestamp = rte_ns_to_timespec(ns);
4881 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4882 struct timespec *timestamp)
4884 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4885 struct e1000_adapter *adapter = dev->data->dev_private;
4886 uint32_t tsync_txctl;
4887 uint64_t tx_tstamp_cycles;
4890 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4891 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4894 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4895 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4896 *timestamp = rte_ns_to_timespec(ns);
4902 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4906 const struct reg_info *reg_group;
4908 while ((reg_group = igb_regs[g_ind++]))
4909 count += igb_reg_group_count(reg_group);
4915 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4919 const struct reg_info *reg_group;
4921 while ((reg_group = igbvf_regs[g_ind++]))
4922 count += igb_reg_group_count(reg_group);
4928 eth_igb_get_regs(struct rte_eth_dev *dev,
4929 struct rte_dev_reg_info *regs)
4931 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4932 uint32_t *data = regs->data;
4935 const struct reg_info *reg_group;
4938 regs->length = eth_igb_get_reg_length(dev);
4939 regs->width = sizeof(uint32_t);
4943 /* Support only full register dump */
4944 if ((regs->length == 0) ||
4945 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4946 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4948 while ((reg_group = igb_regs[g_ind++]))
4949 count += igb_read_regs_group(dev, &data[count],
4958 igbvf_get_regs(struct rte_eth_dev *dev,
4959 struct rte_dev_reg_info *regs)
4961 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4962 uint32_t *data = regs->data;
4965 const struct reg_info *reg_group;
4968 regs->length = igbvf_get_reg_length(dev);
4969 regs->width = sizeof(uint32_t);
4973 /* Support only full register dump */
4974 if ((regs->length == 0) ||
4975 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4976 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4978 while ((reg_group = igbvf_regs[g_ind++]))
4979 count += igb_read_regs_group(dev, &data[count],
4988 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4990 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992 /* Return unit is byte count */
4993 return hw->nvm.word_size * 2;
4997 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4998 struct rte_dev_eeprom_info *in_eeprom)
5000 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5001 struct e1000_nvm_info *nvm = &hw->nvm;
5002 uint16_t *data = in_eeprom->data;
5005 first = in_eeprom->offset >> 1;
5006 length = in_eeprom->length >> 1;
5007 if ((first >= hw->nvm.word_size) ||
5008 ((first + length) >= hw->nvm.word_size))
5011 in_eeprom->magic = hw->vendor_id |
5012 ((uint32_t)hw->device_id << 16);
5014 if ((nvm->ops.read) == NULL)
5017 return nvm->ops.read(hw, first, length, data);
5021 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5022 struct rte_dev_eeprom_info *in_eeprom)
5024 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5025 struct e1000_nvm_info *nvm = &hw->nvm;
5026 uint16_t *data = in_eeprom->data;
5029 first = in_eeprom->offset >> 1;
5030 length = in_eeprom->length >> 1;
5031 if ((first >= hw->nvm.word_size) ||
5032 ((first + length) >= hw->nvm.word_size))
5035 in_eeprom->magic = (uint32_t)hw->vendor_id |
5036 ((uint32_t)hw->device_id << 16);
5038 if ((nvm->ops.write) == NULL)
5040 return nvm->ops.write(hw, first, length, data);
5044 eth_igb_get_module_info(struct rte_eth_dev *dev,
5045 struct rte_eth_dev_module_info *modinfo)
5047 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5049 uint32_t status = 0;
5050 uint16_t sff8472_rev, addr_mode;
5051 bool page_swap = false;
5053 if (hw->phy.media_type == e1000_media_type_copper ||
5054 hw->phy.media_type == e1000_media_type_unknown)
5057 /* Check whether we support SFF-8472 or not */
5058 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5062 /* addressing mode is not supported */
5063 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5067 /* addressing mode is not supported */
5068 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5070 "Address change required to access page 0xA2, "
5071 "but not supported. Please report the module "
5072 "type to the driver maintainers.\n");
5076 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5077 /* We have an SFP, but it does not support SFF-8472 */
5078 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5079 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5081 /* We have an SFP which supports a revision of SFF-8472 */
5082 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5083 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5090 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5091 struct rte_dev_eeprom_info *info)
5093 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5095 uint32_t status = 0;
5096 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5097 u16 first_word, last_word;
5100 first_word = info->offset >> 1;
5101 last_word = (info->offset + info->length - 1) >> 1;
5103 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5104 for (i = 0; i < last_word - first_word + 1; i++) {
5105 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5108 /* Error occurred while reading module */
5112 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5115 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5121 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5123 struct e1000_hw *hw =
5124 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5125 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5126 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5127 uint32_t vec = E1000_MISC_VEC_ID;
5129 if (rte_intr_allow_others(intr_handle))
5130 vec = E1000_RX_VEC_START;
5132 uint32_t mask = 1 << (queue_id + vec);
5134 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5135 E1000_WRITE_FLUSH(hw);
5141 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5143 struct e1000_hw *hw =
5144 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5145 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5146 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5147 uint32_t vec = E1000_MISC_VEC_ID;
5149 if (rte_intr_allow_others(intr_handle))
5150 vec = E1000_RX_VEC_START;
5152 uint32_t mask = 1 << (queue_id + vec);
5155 regval = E1000_READ_REG(hw, E1000_EIMS);
5156 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5157 E1000_WRITE_FLUSH(hw);
5159 rte_intr_ack(intr_handle);
5165 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5166 uint8_t index, uint8_t offset)
5168 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5171 val &= ~((uint32_t)0xFF << offset);
5173 /* write vector and valid bit */
5174 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5176 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5180 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5181 uint8_t queue, uint8_t msix_vector)
5185 if (hw->mac.type == e1000_82575) {
5187 tmp = E1000_EICR_RX_QUEUE0 << queue;
5188 else if (direction == 1)
5189 tmp = E1000_EICR_TX_QUEUE0 << queue;
5190 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5191 } else if (hw->mac.type == e1000_82576) {
5192 if ((direction == 0) || (direction == 1))
5193 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5194 ((queue & 0x8) << 1) +
5196 } else if ((hw->mac.type == e1000_82580) ||
5197 (hw->mac.type == e1000_i350) ||
5198 (hw->mac.type == e1000_i354) ||
5199 (hw->mac.type == e1000_i210) ||
5200 (hw->mac.type == e1000_i211)) {
5201 if ((direction == 0) || (direction == 1))
5202 eth_igb_write_ivar(hw, msix_vector,
5204 ((queue & 0x1) << 4) +
5209 /* Sets up the hardware to generate MSI-X interrupts properly
5211 * board private structure
5214 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5217 uint32_t tmpval, regval, intr_mask;
5218 struct e1000_hw *hw =
5219 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5220 uint32_t vec = E1000_MISC_VEC_ID;
5221 uint32_t base = E1000_MISC_VEC_ID;
5222 uint32_t misc_shift = 0;
5223 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5224 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5226 /* won't configure msix register if no mapping is done
5227 * between intr vector and event fd
5229 if (!rte_intr_dp_is_en(intr_handle))
5232 if (rte_intr_allow_others(intr_handle)) {
5233 vec = base = E1000_RX_VEC_START;
5237 /* set interrupt vector for other causes */
5238 if (hw->mac.type == e1000_82575) {
5239 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5240 /* enable MSI-X PBA support */
5241 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5243 /* Auto-Mask interrupts upon ICR read */
5244 tmpval |= E1000_CTRL_EXT_EIAME;
5245 tmpval |= E1000_CTRL_EXT_IRCA;
5247 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5249 /* enable msix_other interrupt */
5250 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5251 regval = E1000_READ_REG(hw, E1000_EIAC);
5252 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5253 regval = E1000_READ_REG(hw, E1000_EIAM);
5254 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5255 } else if ((hw->mac.type == e1000_82576) ||
5256 (hw->mac.type == e1000_82580) ||
5257 (hw->mac.type == e1000_i350) ||
5258 (hw->mac.type == e1000_i354) ||
5259 (hw->mac.type == e1000_i210) ||
5260 (hw->mac.type == e1000_i211)) {
5261 /* turn on MSI-X capability first */
5262 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5263 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5265 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5268 if (dev->data->dev_conf.intr_conf.lsc != 0)
5269 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5271 regval = E1000_READ_REG(hw, E1000_EIAC);
5272 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5274 /* enable msix_other interrupt */
5275 regval = E1000_READ_REG(hw, E1000_EIMS);
5276 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5277 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5278 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5281 /* use EIAM to auto-mask when MSI-X interrupt
5282 * is asserted, this saves a register write for every interrupt
5284 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5287 if (dev->data->dev_conf.intr_conf.lsc != 0)
5288 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5290 regval = E1000_READ_REG(hw, E1000_EIAM);
5291 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5293 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5294 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5295 intr_handle->intr_vec[queue_id] = vec;
5296 if (vec < base + intr_handle->nb_efd - 1)
5300 E1000_WRITE_FLUSH(hw);
5303 /* restore n-tuple filter */
5305 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5307 struct e1000_filter_info *filter_info =
5308 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5309 struct e1000_5tuple_filter *p_5tuple;
5310 struct e1000_2tuple_filter *p_2tuple;
5312 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5313 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5316 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5317 igb_inject_2uple_filter(dev, p_2tuple);
5321 /* restore SYN filter */
5323 igb_syn_filter_restore(struct rte_eth_dev *dev)
5325 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5326 struct e1000_filter_info *filter_info =
5327 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5330 synqf = filter_info->syn_info;
5332 if (synqf & E1000_SYN_FILTER_ENABLE) {
5333 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5334 E1000_WRITE_FLUSH(hw);
5338 /* restore ethernet type filter */
5340 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5342 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343 struct e1000_filter_info *filter_info =
5344 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5347 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5348 if (filter_info->ethertype_mask & (1 << i)) {
5349 E1000_WRITE_REG(hw, E1000_ETQF(i),
5350 filter_info->ethertype_filters[i].etqf);
5351 E1000_WRITE_FLUSH(hw);
5356 /* restore flex byte filter */
5358 igb_flex_filter_restore(struct rte_eth_dev *dev)
5360 struct e1000_filter_info *filter_info =
5361 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5362 struct e1000_flex_filter *flex_filter;
5364 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5365 igb_inject_flex_filter(dev, flex_filter);
5369 /* restore rss filter */
5371 igb_rss_filter_restore(struct rte_eth_dev *dev)
5373 struct e1000_filter_info *filter_info =
5374 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5376 if (filter_info->rss_info.conf.queue_num)
5377 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5380 /* restore all types filter */
5382 igb_filter_restore(struct rte_eth_dev *dev)
5384 igb_ntuple_filter_restore(dev);
5385 igb_ethertype_filter_restore(dev);
5386 igb_syn_filter_restore(dev);
5387 igb_flex_filter_restore(dev);
5388 igb_rss_filter_restore(dev);
5393 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5394 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5395 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5396 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5397 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5398 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");