4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "base/e1000_api.h"
58 #include "e1000_ethdev.h"
62 * Default values for port configuration
64 #define IGB_DEFAULT_RX_FREE_THRESH 32
66 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
67 #define IGB_DEFAULT_RX_HTHRESH 8
68 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
70 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
71 #define IGB_DEFAULT_TX_HTHRESH 1
72 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
74 #define IGB_HKEY_MAX_INDEX 10
76 /* Bit shift and mask */
77 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
78 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
79 #define IGB_8_BIT_WIDTH CHAR_BIT
80 #define IGB_8_BIT_MASK UINT8_MAX
82 /* Additional timesync values. */
83 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
84 #define E1000_ETQF_FILTER_1588 3
85 #define IGB_82576_TSYNC_SHIFT 16
86 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
87 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
90 #define E1000_VTIVAR_MISC 0x01740
91 #define E1000_VTIVAR_MISC_MASK 0xFF
92 #define E1000_VTIVAR_VALID 0x80
93 #define E1000_VTIVAR_MISC_MAILBOX 0
94 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
96 /* External VLAN Enable bit mask */
97 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
99 /* External VLAN Ether Type bit mask and shift */
100 #define E1000_VET_VET_EXT 0xFFFF0000
101 #define E1000_VET_VET_EXT_SHIFT 16
103 static int eth_igb_configure(struct rte_eth_dev *dev);
104 static int eth_igb_start(struct rte_eth_dev *dev);
105 static void eth_igb_stop(struct rte_eth_dev *dev);
106 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
107 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
108 static void eth_igb_close(struct rte_eth_dev *dev);
109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
113 static int eth_igb_link_update(struct rte_eth_dev *dev,
114 int wait_to_complete);
115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
116 struct rte_eth_stats *rte_stats);
117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
118 struct rte_eth_xstat *xstats, unsigned n);
119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
121 uint64_t *values, unsigned int n);
122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
123 struct rte_eth_xstat_name *xstats_names,
125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
126 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
131 char *fw_version, size_t fw_size);
132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
133 struct rte_eth_dev_info *dev_info);
134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
136 struct rte_eth_dev_info *dev_info);
137 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
138 struct rte_eth_fc_conf *fc_conf);
139 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
140 struct rte_eth_fc_conf *fc_conf);
141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
145 struct rte_intr_handle *handle);
146 static void eth_igb_interrupt_handler(void *param);
147 static int igb_hardware_init(struct e1000_hw *hw);
148 static void igb_hw_control_acquire(struct e1000_hw *hw);
149 static void igb_hw_control_release(struct e1000_hw *hw);
150 static void igb_init_manageability(struct e1000_hw *hw);
151 static void igb_release_manageability(struct e1000_hw *hw);
153 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
156 uint16_t vlan_id, int on);
157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
158 enum rte_vlan_type vlan_type,
160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
169 static int eth_igb_led_on(struct rte_eth_dev *dev);
170 static int eth_igb_led_off(struct rte_eth_dev *dev);
172 static void igb_intr_disable(struct e1000_hw *hw);
173 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
175 struct ether_addr *mac_addr,
176 uint32_t index, uint32_t pool);
177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
179 struct ether_addr *addr);
181 static void igbvf_intr_disable(struct e1000_hw *hw);
182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
183 static int igbvf_dev_start(struct rte_eth_dev *dev);
184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
185 static void igbvf_dev_close(struct rte_eth_dev *dev);
186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
190 static int eth_igbvf_link_update(struct e1000_hw *hw);
191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
192 struct rte_eth_stats *rte_stats);
193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
194 struct rte_eth_xstat *xstats, unsigned n);
195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
196 struct rte_eth_xstat_name *xstats_names,
198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
200 uint16_t vlan_id, int on);
201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
204 struct ether_addr *addr);
205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
206 static int igbvf_get_regs(struct rte_eth_dev *dev,
207 struct rte_dev_reg_info *regs);
209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
216 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
217 struct rte_eth_syn_filter *filter,
219 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
220 struct rte_eth_syn_filter *filter);
221 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
222 enum rte_filter_op filter_op,
224 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
225 struct rte_eth_ntuple_filter *ntuple_filter);
226 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
227 struct rte_eth_ntuple_filter *ntuple_filter);
228 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
229 struct rte_eth_flex_filter *filter,
231 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
232 struct rte_eth_flex_filter *filter);
233 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
234 enum rte_filter_op filter_op,
236 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
237 struct rte_eth_ntuple_filter *ntuple_filter);
238 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
239 struct rte_eth_ntuple_filter *ntuple_filter);
240 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
241 struct rte_eth_ntuple_filter *filter,
243 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
244 struct rte_eth_ntuple_filter *filter);
245 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
246 enum rte_filter_op filter_op,
248 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
249 struct rte_eth_ethertype_filter *filter,
251 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
252 enum rte_filter_op filter_op,
254 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
255 struct rte_eth_ethertype_filter *filter);
256 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
257 enum rte_filter_type filter_type,
258 enum rte_filter_op filter_op,
260 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
261 static int eth_igb_get_regs(struct rte_eth_dev *dev,
262 struct rte_dev_reg_info *regs);
263 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
264 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
265 struct rte_dev_eeprom_info *eeprom);
266 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
267 struct rte_dev_eeprom_info *eeprom);
268 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
269 struct ether_addr *mc_addr_set,
270 uint32_t nb_mc_addr);
271 static int igb_timesync_enable(struct rte_eth_dev *dev);
272 static int igb_timesync_disable(struct rte_eth_dev *dev);
273 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
274 struct timespec *timestamp,
276 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
277 struct timespec *timestamp);
278 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
279 static int igb_timesync_read_time(struct rte_eth_dev *dev,
280 struct timespec *timestamp);
281 static int igb_timesync_write_time(struct rte_eth_dev *dev,
282 const struct timespec *timestamp);
283 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
285 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
287 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
288 uint8_t queue, uint8_t msix_vector);
289 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
290 uint8_t index, uint8_t offset);
291 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
292 static void eth_igbvf_interrupt_handler(void *param);
293 static void igbvf_mbx_process(struct rte_eth_dev *dev);
296 * Define VF Stats MACRO for Non "cleared on read" register
298 #define UPDATE_VF_STAT(reg, last, cur) \
300 u32 latest = E1000_READ_REG(hw, reg); \
301 cur += (latest - last) & UINT_MAX; \
305 #define IGB_FC_PAUSE_TIME 0x0680
306 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
307 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
309 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
311 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
314 * The set of PCI devices this driver supports
316 static const struct rte_pci_id pci_id_igb_map[] = {
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
335 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
337 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
338 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
339 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
340 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
341 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
342 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
343 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
344 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
345 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
346 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
347 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
348 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
349 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
350 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
351 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
352 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
353 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
354 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
355 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
356 { .vendor_id = 0, /* sentinel */ },
360 * The set of PCI devices this driver supports (for 82576&I350 VF)
362 static const struct rte_pci_id pci_id_igbvf_map[] = {
363 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
364 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
365 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
366 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
367 { .vendor_id = 0, /* sentinel */ },
370 static const struct rte_eth_desc_lim rx_desc_lim = {
371 .nb_max = E1000_MAX_RING_DESC,
372 .nb_min = E1000_MIN_RING_DESC,
373 .nb_align = IGB_RXD_ALIGN,
376 static const struct rte_eth_desc_lim tx_desc_lim = {
377 .nb_max = E1000_MAX_RING_DESC,
378 .nb_min = E1000_MIN_RING_DESC,
379 .nb_align = IGB_RXD_ALIGN,
380 .nb_seg_max = IGB_TX_MAX_SEG,
381 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
384 static const struct eth_dev_ops eth_igb_ops = {
385 .dev_configure = eth_igb_configure,
386 .dev_start = eth_igb_start,
387 .dev_stop = eth_igb_stop,
388 .dev_set_link_up = eth_igb_dev_set_link_up,
389 .dev_set_link_down = eth_igb_dev_set_link_down,
390 .dev_close = eth_igb_close,
391 .promiscuous_enable = eth_igb_promiscuous_enable,
392 .promiscuous_disable = eth_igb_promiscuous_disable,
393 .allmulticast_enable = eth_igb_allmulticast_enable,
394 .allmulticast_disable = eth_igb_allmulticast_disable,
395 .link_update = eth_igb_link_update,
396 .stats_get = eth_igb_stats_get,
397 .xstats_get = eth_igb_xstats_get,
398 .xstats_get_by_id = eth_igb_xstats_get_by_id,
399 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
400 .xstats_get_names = eth_igb_xstats_get_names,
401 .stats_reset = eth_igb_stats_reset,
402 .xstats_reset = eth_igb_xstats_reset,
403 .fw_version_get = eth_igb_fw_version_get,
404 .dev_infos_get = eth_igb_infos_get,
405 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
406 .mtu_set = eth_igb_mtu_set,
407 .vlan_filter_set = eth_igb_vlan_filter_set,
408 .vlan_tpid_set = eth_igb_vlan_tpid_set,
409 .vlan_offload_set = eth_igb_vlan_offload_set,
410 .rx_queue_setup = eth_igb_rx_queue_setup,
411 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
412 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
413 .rx_queue_release = eth_igb_rx_queue_release,
414 .rx_queue_count = eth_igb_rx_queue_count,
415 .rx_descriptor_done = eth_igb_rx_descriptor_done,
416 .rx_descriptor_status = eth_igb_rx_descriptor_status,
417 .tx_descriptor_status = eth_igb_tx_descriptor_status,
418 .tx_queue_setup = eth_igb_tx_queue_setup,
419 .tx_queue_release = eth_igb_tx_queue_release,
420 .tx_done_cleanup = eth_igb_tx_done_cleanup,
421 .dev_led_on = eth_igb_led_on,
422 .dev_led_off = eth_igb_led_off,
423 .flow_ctrl_get = eth_igb_flow_ctrl_get,
424 .flow_ctrl_set = eth_igb_flow_ctrl_set,
425 .mac_addr_add = eth_igb_rar_set,
426 .mac_addr_remove = eth_igb_rar_clear,
427 .mac_addr_set = eth_igb_default_mac_addr_set,
428 .reta_update = eth_igb_rss_reta_update,
429 .reta_query = eth_igb_rss_reta_query,
430 .rss_hash_update = eth_igb_rss_hash_update,
431 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
432 .filter_ctrl = eth_igb_filter_ctrl,
433 .set_mc_addr_list = eth_igb_set_mc_addr_list,
434 .rxq_info_get = igb_rxq_info_get,
435 .txq_info_get = igb_txq_info_get,
436 .timesync_enable = igb_timesync_enable,
437 .timesync_disable = igb_timesync_disable,
438 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
439 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
440 .get_reg = eth_igb_get_regs,
441 .get_eeprom_length = eth_igb_get_eeprom_length,
442 .get_eeprom = eth_igb_get_eeprom,
443 .set_eeprom = eth_igb_set_eeprom,
444 .timesync_adjust_time = igb_timesync_adjust_time,
445 .timesync_read_time = igb_timesync_read_time,
446 .timesync_write_time = igb_timesync_write_time,
450 * dev_ops for virtual function, bare necessities for basic vf
451 * operation have been implemented
453 static const struct eth_dev_ops igbvf_eth_dev_ops = {
454 .dev_configure = igbvf_dev_configure,
455 .dev_start = igbvf_dev_start,
456 .dev_stop = igbvf_dev_stop,
457 .dev_close = igbvf_dev_close,
458 .promiscuous_enable = igbvf_promiscuous_enable,
459 .promiscuous_disable = igbvf_promiscuous_disable,
460 .allmulticast_enable = igbvf_allmulticast_enable,
461 .allmulticast_disable = igbvf_allmulticast_disable,
462 .link_update = eth_igb_link_update,
463 .stats_get = eth_igbvf_stats_get,
464 .xstats_get = eth_igbvf_xstats_get,
465 .xstats_get_names = eth_igbvf_xstats_get_names,
466 .stats_reset = eth_igbvf_stats_reset,
467 .xstats_reset = eth_igbvf_stats_reset,
468 .vlan_filter_set = igbvf_vlan_filter_set,
469 .dev_infos_get = eth_igbvf_infos_get,
470 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
471 .rx_queue_setup = eth_igb_rx_queue_setup,
472 .rx_queue_release = eth_igb_rx_queue_release,
473 .tx_queue_setup = eth_igb_tx_queue_setup,
474 .tx_queue_release = eth_igb_tx_queue_release,
475 .set_mc_addr_list = eth_igb_set_mc_addr_list,
476 .rxq_info_get = igb_rxq_info_get,
477 .txq_info_get = igb_txq_info_get,
478 .mac_addr_set = igbvf_default_mac_addr_set,
479 .get_reg = igbvf_get_regs,
482 /* store statistics names and its offset in stats structure */
483 struct rte_igb_xstats_name_off {
484 char name[RTE_ETH_XSTATS_NAME_SIZE];
488 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
489 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
490 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
491 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
492 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
493 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
494 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
495 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
497 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
498 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
499 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
500 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
501 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
502 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
503 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
504 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
505 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
506 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
507 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
509 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
510 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
511 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
512 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
513 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
515 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
517 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
518 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
519 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
520 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
521 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
522 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
523 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
524 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
525 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
526 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
527 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
528 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
529 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
530 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
531 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
532 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
533 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
534 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
536 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
538 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
539 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
540 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
541 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
542 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
543 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
544 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
546 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
549 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
550 sizeof(rte_igb_stats_strings[0]))
552 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
553 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
554 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
555 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
556 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
557 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
560 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
561 sizeof(rte_igbvf_stats_strings[0]))
564 * Atomically reads the link status information from global
565 * structure rte_eth_dev.
568 * - Pointer to the structure rte_eth_dev to read from.
569 * - Pointer to the buffer to be saved with the link status.
572 * - On success, zero.
573 * - On failure, negative value.
576 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
577 struct rte_eth_link *link)
579 struct rte_eth_link *dst = link;
580 struct rte_eth_link *src = &(dev->data->dev_link);
582 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
583 *(uint64_t *)src) == 0)
590 * Atomically writes the link status information into global
591 * structure rte_eth_dev.
594 * - Pointer to the structure rte_eth_dev to read from.
595 * - Pointer to the buffer to be saved with the link status.
598 * - On success, zero.
599 * - On failure, negative value.
602 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
603 struct rte_eth_link *link)
605 struct rte_eth_link *dst = &(dev->data->dev_link);
606 struct rte_eth_link *src = link;
608 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
609 *(uint64_t *)src) == 0)
616 igb_intr_enable(struct rte_eth_dev *dev)
618 struct e1000_interrupt *intr =
619 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
620 struct e1000_hw *hw =
621 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
623 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
624 E1000_WRITE_FLUSH(hw);
628 igb_intr_disable(struct e1000_hw *hw)
630 E1000_WRITE_REG(hw, E1000_IMC, ~0);
631 E1000_WRITE_FLUSH(hw);
635 igbvf_intr_enable(struct rte_eth_dev *dev)
637 struct e1000_hw *hw =
638 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
640 /* only for mailbox */
641 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
642 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
643 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
644 E1000_WRITE_FLUSH(hw);
647 /* only for mailbox now. If RX/TX needed, should extend this function. */
649 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
654 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
655 tmp |= E1000_VTIVAR_VALID;
656 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
660 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
662 struct e1000_hw *hw =
663 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
665 /* Configure VF other cause ivar */
666 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
669 static inline int32_t
670 igb_pf_reset_hw(struct e1000_hw *hw)
675 status = e1000_reset_hw(hw);
677 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
678 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
679 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
680 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
681 E1000_WRITE_FLUSH(hw);
687 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
689 struct e1000_hw *hw =
690 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
693 hw->vendor_id = pci_dev->id.vendor_id;
694 hw->device_id = pci_dev->id.device_id;
695 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
696 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
698 e1000_set_mac_type(hw);
700 /* need to check if it is a vf device below */
704 igb_reset_swfw_lock(struct e1000_hw *hw)
709 * Do mac ops initialization manually here, since we will need
710 * some function pointers set by this call.
712 ret_val = e1000_init_mac_params(hw);
717 * SMBI lock should not fail in this early stage. If this is the case,
718 * it is due to an improper exit of the application.
719 * So force the release of the faulty lock.
721 if (e1000_get_hw_semaphore_generic(hw) < 0) {
722 PMD_DRV_LOG(DEBUG, "SMBI lock released");
724 e1000_put_hw_semaphore_generic(hw);
726 if (hw->mac.ops.acquire_swfw_sync != NULL) {
730 * Phy lock should not fail in this early stage. If this is the case,
731 * it is due to an improper exit of the application.
732 * So force the release of the faulty lock.
734 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
735 if (hw->bus.func > E1000_FUNC_1)
737 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
738 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
741 hw->mac.ops.release_swfw_sync(hw, mask);
744 * This one is more tricky since it is common to all ports; but
745 * swfw_sync retries last long enough (1s) to be almost sure that if
746 * lock can not be taken it is due to an improper lock of the
749 mask = E1000_SWFW_EEP_SM;
750 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
751 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
753 hw->mac.ops.release_swfw_sync(hw, mask);
756 return E1000_SUCCESS;
760 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
763 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
764 struct e1000_hw *hw =
765 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
766 struct e1000_vfta * shadow_vfta =
767 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
768 struct e1000_filter_info *filter_info =
769 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
770 struct e1000_adapter *adapter =
771 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
775 eth_dev->dev_ops = ð_igb_ops;
776 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
777 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
778 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
780 /* for secondary processes, we don't initialise any further as primary
781 * has already done this work. Only check we don't need a different
783 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
784 if (eth_dev->data->scattered_rx)
785 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
789 rte_eth_copy_pci_info(eth_dev, pci_dev);
790 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
792 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
794 igb_identify_hardware(eth_dev, pci_dev);
795 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
800 e1000_get_bus_info(hw);
802 /* Reset any pending lock */
803 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
808 /* Finish initialization */
809 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
815 hw->phy.autoneg_wait_to_complete = 0;
816 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
819 if (hw->phy.media_type == e1000_media_type_copper) {
820 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
821 hw->phy.disable_polarity_correction = 0;
822 hw->phy.ms_type = e1000_ms_hw_default;
826 * Start from a known state, this is important in reading the nvm
831 /* Make sure we have a good EEPROM before we read from it */
832 if (e1000_validate_nvm_checksum(hw) < 0) {
834 * Some PCI-E parts fail the first check due to
835 * the link being in sleep state, call it again,
836 * if it fails a second time its a real issue.
838 if (e1000_validate_nvm_checksum(hw) < 0) {
839 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
845 /* Read the permanent MAC address out of the EEPROM */
846 if (e1000_read_mac_addr(hw) != 0) {
847 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
852 /* Allocate memory for storing MAC addresses */
853 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
854 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
855 if (eth_dev->data->mac_addrs == NULL) {
856 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
857 "store MAC addresses",
858 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
863 /* Copy the permanent MAC address */
864 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
866 /* initialize the vfta */
867 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
869 /* Now initialize the hardware */
870 if (igb_hardware_init(hw) != 0) {
871 PMD_INIT_LOG(ERR, "Hardware initialization failed");
872 rte_free(eth_dev->data->mac_addrs);
873 eth_dev->data->mac_addrs = NULL;
877 hw->mac.get_link_status = 1;
878 adapter->stopped = 0;
880 /* Indicate SOL/IDER usage */
881 if (e1000_check_reset_block(hw) < 0) {
882 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
886 /* initialize PF if max_vfs not zero */
887 igb_pf_host_init(eth_dev);
889 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
890 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
891 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
892 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
893 E1000_WRITE_FLUSH(hw);
895 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
896 eth_dev->data->port_id, pci_dev->id.vendor_id,
897 pci_dev->id.device_id);
899 rte_intr_callback_register(&pci_dev->intr_handle,
900 eth_igb_interrupt_handler,
903 /* enable uio/vfio intr/eventfd mapping */
904 rte_intr_enable(&pci_dev->intr_handle);
906 /* enable support intr */
907 igb_intr_enable(eth_dev);
909 TAILQ_INIT(&filter_info->flex_list);
910 filter_info->flex_mask = 0;
911 TAILQ_INIT(&filter_info->twotuple_list);
912 filter_info->twotuple_mask = 0;
913 TAILQ_INIT(&filter_info->fivetuple_list);
914 filter_info->fivetuple_mask = 0;
919 igb_hw_control_release(hw);
925 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
927 struct rte_pci_device *pci_dev;
928 struct rte_intr_handle *intr_handle;
930 struct e1000_adapter *adapter =
931 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
933 PMD_INIT_FUNC_TRACE();
935 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
938 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
939 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
940 intr_handle = &pci_dev->intr_handle;
942 if (adapter->stopped == 0)
943 eth_igb_close(eth_dev);
945 eth_dev->dev_ops = NULL;
946 eth_dev->rx_pkt_burst = NULL;
947 eth_dev->tx_pkt_burst = NULL;
949 /* Reset any pending lock */
950 igb_reset_swfw_lock(hw);
952 rte_free(eth_dev->data->mac_addrs);
953 eth_dev->data->mac_addrs = NULL;
955 /* uninitialize PF if max_vfs not zero */
956 igb_pf_host_uninit(eth_dev);
958 /* disable uio intr before callback unregister */
959 rte_intr_disable(intr_handle);
960 rte_intr_callback_unregister(intr_handle,
961 eth_igb_interrupt_handler, eth_dev);
967 * Virtual Function device init
970 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
972 struct rte_pci_device *pci_dev;
973 struct rte_intr_handle *intr_handle;
974 struct e1000_adapter *adapter =
975 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
976 struct e1000_hw *hw =
977 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
979 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
981 PMD_INIT_FUNC_TRACE();
983 eth_dev->dev_ops = &igbvf_eth_dev_ops;
984 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
985 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
986 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
988 /* for secondary processes, we don't initialise any further as primary
989 * has already done this work. Only check we don't need a different
991 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
992 if (eth_dev->data->scattered_rx)
993 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
997 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
998 rte_eth_copy_pci_info(eth_dev, pci_dev);
999 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1001 hw->device_id = pci_dev->id.device_id;
1002 hw->vendor_id = pci_dev->id.vendor_id;
1003 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1004 adapter->stopped = 0;
1006 /* Initialize the shared code (base driver) */
1007 diag = e1000_setup_init_funcs(hw, TRUE);
1009 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1014 /* init_mailbox_params */
1015 hw->mbx.ops.init_params(hw);
1017 /* Disable the interrupts for VF */
1018 igbvf_intr_disable(hw);
1020 diag = hw->mac.ops.reset_hw(hw);
1022 /* Allocate memory for storing MAC addresses */
1023 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1024 hw->mac.rar_entry_count, 0);
1025 if (eth_dev->data->mac_addrs == NULL) {
1027 "Failed to allocate %d bytes needed to store MAC "
1029 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1033 /* Generate a random MAC address, if none was assigned by PF. */
1034 if (is_zero_ether_addr(perm_addr)) {
1035 eth_random_addr(perm_addr->addr_bytes);
1036 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1037 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1038 "%02x:%02x:%02x:%02x:%02x:%02x",
1039 perm_addr->addr_bytes[0],
1040 perm_addr->addr_bytes[1],
1041 perm_addr->addr_bytes[2],
1042 perm_addr->addr_bytes[3],
1043 perm_addr->addr_bytes[4],
1044 perm_addr->addr_bytes[5]);
1047 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1049 rte_free(eth_dev->data->mac_addrs);
1050 eth_dev->data->mac_addrs = NULL;
1053 /* Copy the permanent MAC address */
1054 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1055 ð_dev->data->mac_addrs[0]);
1057 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1059 eth_dev->data->port_id, pci_dev->id.vendor_id,
1060 pci_dev->id.device_id, "igb_mac_82576_vf");
1062 intr_handle = &pci_dev->intr_handle;
1063 rte_intr_callback_register(intr_handle,
1064 eth_igbvf_interrupt_handler, eth_dev);
1070 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1072 struct e1000_adapter *adapter =
1073 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1074 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1076 PMD_INIT_FUNC_TRACE();
1078 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1081 if (adapter->stopped == 0)
1082 igbvf_dev_close(eth_dev);
1084 eth_dev->dev_ops = NULL;
1085 eth_dev->rx_pkt_burst = NULL;
1086 eth_dev->tx_pkt_burst = NULL;
1088 rte_free(eth_dev->data->mac_addrs);
1089 eth_dev->data->mac_addrs = NULL;
1091 /* disable uio intr before callback unregister */
1092 rte_intr_disable(&pci_dev->intr_handle);
1093 rte_intr_callback_unregister(&pci_dev->intr_handle,
1094 eth_igbvf_interrupt_handler,
1100 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1101 struct rte_pci_device *pci_dev)
1103 return rte_eth_dev_pci_generic_probe(pci_dev,
1104 sizeof(struct e1000_adapter), eth_igb_dev_init);
1107 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1109 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1112 static struct rte_pci_driver rte_igb_pmd = {
1113 .id_table = pci_id_igb_map,
1114 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1115 .probe = eth_igb_pci_probe,
1116 .remove = eth_igb_pci_remove,
1120 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1121 struct rte_pci_device *pci_dev)
1123 return rte_eth_dev_pci_generic_probe(pci_dev,
1124 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1127 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1129 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1133 * virtual function driver struct
1135 static struct rte_pci_driver rte_igbvf_pmd = {
1136 .id_table = pci_id_igbvf_map,
1137 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1138 .probe = eth_igbvf_pci_probe,
1139 .remove = eth_igbvf_pci_remove,
1143 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1145 struct e1000_hw *hw =
1146 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1147 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1148 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1149 rctl |= E1000_RCTL_VFE;
1150 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1154 igb_check_mq_mode(struct rte_eth_dev *dev)
1156 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1157 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1158 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1159 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1161 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1162 tx_mq_mode == ETH_MQ_TX_DCB ||
1163 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1164 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1167 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1168 /* Check multi-queue mode.
1169 * To no break software we accept ETH_MQ_RX_NONE as this might
1170 * be used to turn off VLAN filter.
1173 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1174 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1175 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1176 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1178 /* Only support one queue on VFs.
1179 * RSS together with SRIOV is not supported.
1181 PMD_INIT_LOG(ERR, "SRIOV is active,"
1182 " wrong mq_mode rx %d.",
1186 /* TX mode is not used here, so mode might be ignored.*/
1187 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1188 /* SRIOV only works in VMDq enable mode */
1189 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1190 " TX mode %d is not supported. "
1191 " Driver will behave as %d mode.",
1192 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1195 /* check valid queue number */
1196 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1197 PMD_INIT_LOG(ERR, "SRIOV is active,"
1198 " only support one queue on VFs.");
1202 /* To no break software that set invalid mode, only display
1203 * warning if invalid mode is used.
1205 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1206 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1207 rx_mq_mode != ETH_MQ_RX_RSS) {
1208 /* RSS together with VMDq not supported*/
1209 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1214 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1215 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1216 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1217 " Due to txmode is meaningless in this"
1218 " driver, just ignore.",
1226 eth_igb_configure(struct rte_eth_dev *dev)
1228 struct e1000_interrupt *intr =
1229 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1232 PMD_INIT_FUNC_TRACE();
1234 /* multipe queue mode checking */
1235 ret = igb_check_mq_mode(dev);
1237 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1242 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1243 PMD_INIT_FUNC_TRACE();
1249 eth_igb_start(struct rte_eth_dev *dev)
1251 struct e1000_hw *hw =
1252 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1253 struct e1000_adapter *adapter =
1254 E1000_DEV_PRIVATE(dev->data->dev_private);
1255 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1256 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1258 uint32_t intr_vector = 0;
1264 PMD_INIT_FUNC_TRACE();
1266 /* disable uio/vfio intr/eventfd mapping */
1267 rte_intr_disable(intr_handle);
1269 /* Power up the phy. Needed to make the link go Up */
1270 eth_igb_dev_set_link_up(dev);
1273 * Packet Buffer Allocation (PBA)
1274 * Writing PBA sets the receive portion of the buffer
1275 * the remainder is used for the transmit buffer.
1277 if (hw->mac.type == e1000_82575) {
1280 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1281 E1000_WRITE_REG(hw, E1000_PBA, pba);
1284 /* Put the address into the Receive Address Array */
1285 e1000_rar_set(hw, hw->mac.addr, 0);
1287 /* Initialize the hardware */
1288 if (igb_hardware_init(hw)) {
1289 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1292 adapter->stopped = 0;
1294 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1296 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1297 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1298 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1299 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1300 E1000_WRITE_FLUSH(hw);
1302 /* configure PF module if SRIOV enabled */
1303 igb_pf_host_configure(dev);
1305 /* check and configure queue intr-vector mapping */
1306 if ((rte_intr_cap_multiple(intr_handle) ||
1307 !RTE_ETH_DEV_SRIOV(dev).active) &&
1308 dev->data->dev_conf.intr_conf.rxq != 0) {
1309 intr_vector = dev->data->nb_rx_queues;
1310 if (rte_intr_efd_enable(intr_handle, intr_vector))
1314 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1315 intr_handle->intr_vec =
1316 rte_zmalloc("intr_vec",
1317 dev->data->nb_rx_queues * sizeof(int), 0);
1318 if (intr_handle->intr_vec == NULL) {
1319 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1320 " intr_vec", dev->data->nb_rx_queues);
1325 /* confiugre msix for rx interrupt */
1326 eth_igb_configure_msix_intr(dev);
1328 /* Configure for OS presence */
1329 igb_init_manageability(hw);
1331 eth_igb_tx_init(dev);
1333 /* This can fail when allocating mbufs for descriptor rings */
1334 ret = eth_igb_rx_init(dev);
1336 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1337 igb_dev_clear_queues(dev);
1341 e1000_clear_hw_cntrs_base_generic(hw);
1344 * VLAN Offload Settings
1346 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1347 ETH_VLAN_EXTEND_MASK;
1348 eth_igb_vlan_offload_set(dev, mask);
1350 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1351 /* Enable VLAN filter since VMDq always use VLAN filter */
1352 igb_vmdq_vlan_hw_filter_enable(dev);
1355 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1356 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1357 (hw->mac.type == e1000_i211)) {
1358 /* Configure EITR with the maximum possible value (0xFFFF) */
1359 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1362 /* Setup link speed and duplex */
1363 speeds = &dev->data->dev_conf.link_speeds;
1364 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1365 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1366 hw->mac.autoneg = 1;
1369 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1372 hw->phy.autoneg_advertised = 0;
1374 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1375 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1376 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1378 goto error_invalid_config;
1380 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1381 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1384 if (*speeds & ETH_LINK_SPEED_10M) {
1385 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1388 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1389 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1392 if (*speeds & ETH_LINK_SPEED_100M) {
1393 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1396 if (*speeds & ETH_LINK_SPEED_1G) {
1397 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1400 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1401 goto error_invalid_config;
1403 /* Set/reset the mac.autoneg based on the link speed,
1407 hw->mac.autoneg = 0;
1408 hw->mac.forced_speed_duplex =
1409 hw->phy.autoneg_advertised;
1411 hw->mac.autoneg = 1;
1415 e1000_setup_link(hw);
1417 if (rte_intr_allow_others(intr_handle)) {
1418 /* check if lsc interrupt is enabled */
1419 if (dev->data->dev_conf.intr_conf.lsc != 0)
1420 eth_igb_lsc_interrupt_setup(dev);
1422 rte_intr_callback_unregister(intr_handle,
1423 eth_igb_interrupt_handler,
1425 if (dev->data->dev_conf.intr_conf.lsc != 0)
1426 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1427 " no intr multiplex");
1430 /* check if rxq interrupt is enabled */
1431 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1432 rte_intr_dp_is_en(intr_handle))
1433 eth_igb_rxq_interrupt_setup(dev);
1435 /* enable uio/vfio intr/eventfd mapping */
1436 rte_intr_enable(intr_handle);
1438 /* resume enabled intr since hw reset */
1439 igb_intr_enable(dev);
1441 PMD_INIT_LOG(DEBUG, "<<");
1445 error_invalid_config:
1446 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1447 dev->data->dev_conf.link_speeds, dev->data->port_id);
1448 igb_dev_clear_queues(dev);
1452 /*********************************************************************
1454 * This routine disables all traffic on the adapter by issuing a
1455 * global reset on the MAC.
1457 **********************************************************************/
1459 eth_igb_stop(struct rte_eth_dev *dev)
1461 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1462 struct e1000_filter_info *filter_info =
1463 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1464 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1465 struct rte_eth_link link;
1466 struct e1000_flex_filter *p_flex;
1467 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1468 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1469 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1471 igb_intr_disable(hw);
1473 /* disable intr eventfd mapping */
1474 rte_intr_disable(intr_handle);
1476 igb_pf_reset_hw(hw);
1477 E1000_WRITE_REG(hw, E1000_WUC, 0);
1479 /* Set bit for Go Link disconnect */
1480 if (hw->mac.type >= e1000_82580) {
1483 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1484 phpm_reg |= E1000_82580_PM_GO_LINKD;
1485 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1488 /* Power down the phy. Needed to make the link go Down */
1489 eth_igb_dev_set_link_down(dev);
1491 igb_dev_clear_queues(dev);
1493 /* clear the recorded link status */
1494 memset(&link, 0, sizeof(link));
1495 rte_igb_dev_atomic_write_link_status(dev, &link);
1497 /* Remove all flex filters of the device */
1498 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1499 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1502 filter_info->flex_mask = 0;
1504 /* Remove all ntuple filters of the device */
1505 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1506 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1507 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1508 TAILQ_REMOVE(&filter_info->fivetuple_list,
1512 filter_info->fivetuple_mask = 0;
1513 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1514 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1515 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1516 TAILQ_REMOVE(&filter_info->twotuple_list,
1520 filter_info->twotuple_mask = 0;
1522 if (!rte_intr_allow_others(intr_handle))
1523 /* resume to the default handler */
1524 rte_intr_callback_register(intr_handle,
1525 eth_igb_interrupt_handler,
1528 /* Clean datapath event and queue/vec mapping */
1529 rte_intr_efd_disable(intr_handle);
1530 if (intr_handle->intr_vec != NULL) {
1531 rte_free(intr_handle->intr_vec);
1532 intr_handle->intr_vec = NULL;
1537 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1539 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1541 if (hw->phy.media_type == e1000_media_type_copper)
1542 e1000_power_up_phy(hw);
1544 e1000_power_up_fiber_serdes_link(hw);
1550 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1552 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1554 if (hw->phy.media_type == e1000_media_type_copper)
1555 e1000_power_down_phy(hw);
1557 e1000_shutdown_fiber_serdes_link(hw);
1563 eth_igb_close(struct rte_eth_dev *dev)
1565 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566 struct e1000_adapter *adapter =
1567 E1000_DEV_PRIVATE(dev->data->dev_private);
1568 struct rte_eth_link link;
1569 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1570 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1573 adapter->stopped = 1;
1575 e1000_phy_hw_reset(hw);
1576 igb_release_manageability(hw);
1577 igb_hw_control_release(hw);
1579 /* Clear bit for Go Link disconnect */
1580 if (hw->mac.type >= e1000_82580) {
1583 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1584 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1585 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1588 igb_dev_free_queues(dev);
1590 if (intr_handle->intr_vec) {
1591 rte_free(intr_handle->intr_vec);
1592 intr_handle->intr_vec = NULL;
1595 memset(&link, 0, sizeof(link));
1596 rte_igb_dev_atomic_write_link_status(dev, &link);
1600 igb_get_rx_buffer_size(struct e1000_hw *hw)
1602 uint32_t rx_buf_size;
1603 if (hw->mac.type == e1000_82576) {
1604 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1605 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1606 /* PBS needs to be translated according to a lookup table */
1607 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1608 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1609 rx_buf_size = (rx_buf_size << 10);
1610 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1611 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1613 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1619 /*********************************************************************
1621 * Initialize the hardware
1623 **********************************************************************/
1625 igb_hardware_init(struct e1000_hw *hw)
1627 uint32_t rx_buf_size;
1630 /* Let the firmware know the OS is in control */
1631 igb_hw_control_acquire(hw);
1634 * These parameters control the automatic generation (Tx) and
1635 * response (Rx) to Ethernet PAUSE frames.
1636 * - High water mark should allow for at least two standard size (1518)
1637 * frames to be received after sending an XOFF.
1638 * - Low water mark works best when it is very near the high water mark.
1639 * This allows the receiver to restart by sending XON when it has
1640 * drained a bit. Here we use an arbitrary value of 1500 which will
1641 * restart after one full frame is pulled from the buffer. There
1642 * could be several smaller frames in the buffer and if so they will
1643 * not trigger the XON until their total number reduces the buffer
1645 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1647 rx_buf_size = igb_get_rx_buffer_size(hw);
1649 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1650 hw->fc.low_water = hw->fc.high_water - 1500;
1651 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1652 hw->fc.send_xon = 1;
1654 /* Set Flow control, use the tunable location if sane */
1655 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1656 hw->fc.requested_mode = igb_fc_setting;
1658 hw->fc.requested_mode = e1000_fc_none;
1660 /* Issue a global reset */
1661 igb_pf_reset_hw(hw);
1662 E1000_WRITE_REG(hw, E1000_WUC, 0);
1664 diag = e1000_init_hw(hw);
1668 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1669 e1000_get_phy_info(hw);
1670 e1000_check_for_link(hw);
1675 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1677 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1681 uint64_t old_gprc = stats->gprc;
1682 uint64_t old_gptc = stats->gptc;
1683 uint64_t old_tpr = stats->tpr;
1684 uint64_t old_tpt = stats->tpt;
1685 uint64_t old_rpthc = stats->rpthc;
1686 uint64_t old_hgptc = stats->hgptc;
1688 if(hw->phy.media_type == e1000_media_type_copper ||
1689 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1691 E1000_READ_REG(hw,E1000_SYMERRS);
1692 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1695 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1696 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1697 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1698 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1700 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1701 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1702 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1703 stats->dc += E1000_READ_REG(hw, E1000_DC);
1704 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1705 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1706 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1708 ** For watchdog management we need to know if we have been
1709 ** paused during the last interval, so capture that here.
1711 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1712 stats->xoffrxc += pause_frames;
1713 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1714 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1715 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1716 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1717 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1718 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1719 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1720 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1721 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1722 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1723 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1724 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1726 /* For the 64-bit byte counters the low dword must be read first. */
1727 /* Both registers clear on the read of the high dword */
1729 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1730 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1731 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1732 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1733 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1734 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1735 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1737 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1738 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1739 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1740 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1741 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1743 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1744 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1746 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1747 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1748 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1749 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1750 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1751 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1753 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1754 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1755 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1756 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1757 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1758 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1759 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1760 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1762 /* Interrupt Counts */
1764 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1765 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1766 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1767 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1768 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1769 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1770 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1771 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1772 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1774 /* Host to Card Statistics */
1776 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1777 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1778 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1779 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1780 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1781 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1782 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1783 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1784 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1785 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1786 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1787 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1788 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1789 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1790 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1791 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1793 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1794 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1795 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1796 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1797 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1798 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1802 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1804 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1805 struct e1000_hw_stats *stats =
1806 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1808 igb_read_stats_registers(hw, stats);
1810 if (rte_stats == NULL)
1814 rte_stats->imissed = stats->mpc;
1815 rte_stats->ierrors = stats->crcerrs +
1816 stats->rlec + stats->ruc + stats->roc +
1817 stats->rxerrc + stats->algnerrc + stats->cexterr;
1820 rte_stats->oerrors = stats->ecol + stats->latecol;
1822 rte_stats->ipackets = stats->gprc;
1823 rte_stats->opackets = stats->gptc;
1824 rte_stats->ibytes = stats->gorc;
1825 rte_stats->obytes = stats->gotc;
1829 eth_igb_stats_reset(struct rte_eth_dev *dev)
1831 struct e1000_hw_stats *hw_stats =
1832 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1834 /* HW registers are cleared on read */
1835 eth_igb_stats_get(dev, NULL);
1837 /* Reset software totals */
1838 memset(hw_stats, 0, sizeof(*hw_stats));
1842 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1844 struct e1000_hw_stats *stats =
1845 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1847 /* HW registers are cleared on read */
1848 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1850 /* Reset software totals */
1851 memset(stats, 0, sizeof(*stats));
1854 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1855 struct rte_eth_xstat_name *xstats_names,
1856 __rte_unused unsigned int size)
1860 if (xstats_names == NULL)
1861 return IGB_NB_XSTATS;
1863 /* Note: limit checked in rte_eth_xstats_names() */
1865 for (i = 0; i < IGB_NB_XSTATS; i++) {
1866 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1867 "%s", rte_igb_stats_strings[i].name);
1870 return IGB_NB_XSTATS;
1873 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1874 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1880 if (xstats_names == NULL)
1881 return IGB_NB_XSTATS;
1883 for (i = 0; i < IGB_NB_XSTATS; i++)
1884 snprintf(xstats_names[i].name,
1885 sizeof(xstats_names[i].name),
1886 "%s", rte_igb_stats_strings[i].name);
1888 return IGB_NB_XSTATS;
1891 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1893 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1896 for (i = 0; i < limit; i++) {
1897 if (ids[i] >= IGB_NB_XSTATS) {
1898 PMD_INIT_LOG(ERR, "id value isn't valid");
1901 strcpy(xstats_names[i].name,
1902 xstats_names_copy[ids[i]].name);
1909 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1912 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 struct e1000_hw_stats *hw_stats =
1914 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1917 if (n < IGB_NB_XSTATS)
1918 return IGB_NB_XSTATS;
1920 igb_read_stats_registers(hw, hw_stats);
1922 /* If this is a reset xstats is NULL, and we have cleared the
1923 * registers by reading them.
1928 /* Extended stats */
1929 for (i = 0; i < IGB_NB_XSTATS; i++) {
1931 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1932 rte_igb_stats_strings[i].offset);
1935 return IGB_NB_XSTATS;
1939 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1940 uint64_t *values, unsigned int n)
1945 struct e1000_hw *hw =
1946 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1947 struct e1000_hw_stats *hw_stats =
1948 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1950 if (n < IGB_NB_XSTATS)
1951 return IGB_NB_XSTATS;
1953 igb_read_stats_registers(hw, hw_stats);
1955 /* If this is a reset xstats is NULL, and we have cleared the
1956 * registers by reading them.
1961 /* Extended stats */
1962 for (i = 0; i < IGB_NB_XSTATS; i++)
1963 values[i] = *(uint64_t *)(((char *)hw_stats) +
1964 rte_igb_stats_strings[i].offset);
1966 return IGB_NB_XSTATS;
1969 uint64_t values_copy[IGB_NB_XSTATS];
1971 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1974 for (i = 0; i < n; i++) {
1975 if (ids[i] >= IGB_NB_XSTATS) {
1976 PMD_INIT_LOG(ERR, "id value isn't valid");
1979 values[i] = values_copy[ids[i]];
1986 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1988 /* Good Rx packets, include VF loopback */
1989 UPDATE_VF_STAT(E1000_VFGPRC,
1990 hw_stats->last_gprc, hw_stats->gprc);
1992 /* Good Rx octets, include VF loopback */
1993 UPDATE_VF_STAT(E1000_VFGORC,
1994 hw_stats->last_gorc, hw_stats->gorc);
1996 /* Good Tx packets, include VF loopback */
1997 UPDATE_VF_STAT(E1000_VFGPTC,
1998 hw_stats->last_gptc, hw_stats->gptc);
2000 /* Good Tx octets, include VF loopback */
2001 UPDATE_VF_STAT(E1000_VFGOTC,
2002 hw_stats->last_gotc, hw_stats->gotc);
2004 /* Rx Multicst packets */
2005 UPDATE_VF_STAT(E1000_VFMPRC,
2006 hw_stats->last_mprc, hw_stats->mprc);
2008 /* Good Rx loopback packets */
2009 UPDATE_VF_STAT(E1000_VFGPRLBC,
2010 hw_stats->last_gprlbc, hw_stats->gprlbc);
2012 /* Good Rx loopback octets */
2013 UPDATE_VF_STAT(E1000_VFGORLBC,
2014 hw_stats->last_gorlbc, hw_stats->gorlbc);
2016 /* Good Tx loopback packets */
2017 UPDATE_VF_STAT(E1000_VFGPTLBC,
2018 hw_stats->last_gptlbc, hw_stats->gptlbc);
2020 /* Good Tx loopback octets */
2021 UPDATE_VF_STAT(E1000_VFGOTLBC,
2022 hw_stats->last_gotlbc, hw_stats->gotlbc);
2025 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2026 struct rte_eth_xstat_name *xstats_names,
2027 __rte_unused unsigned limit)
2031 if (xstats_names != NULL)
2032 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2033 snprintf(xstats_names[i].name,
2034 sizeof(xstats_names[i].name), "%s",
2035 rte_igbvf_stats_strings[i].name);
2037 return IGBVF_NB_XSTATS;
2041 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2044 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2046 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2049 if (n < IGBVF_NB_XSTATS)
2050 return IGBVF_NB_XSTATS;
2052 igbvf_read_stats_registers(hw, hw_stats);
2057 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2059 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2060 rte_igbvf_stats_strings[i].offset);
2063 return IGBVF_NB_XSTATS;
2067 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2069 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2071 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2073 igbvf_read_stats_registers(hw, hw_stats);
2075 if (rte_stats == NULL)
2078 rte_stats->ipackets = hw_stats->gprc;
2079 rte_stats->ibytes = hw_stats->gorc;
2080 rte_stats->opackets = hw_stats->gptc;
2081 rte_stats->obytes = hw_stats->gotc;
2085 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2087 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2088 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2090 /* Sync HW register to the last stats */
2091 eth_igbvf_stats_get(dev, NULL);
2093 /* reset HW current stats*/
2094 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2095 offsetof(struct e1000_vf_stats, gprc));
2099 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2102 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103 struct e1000_fw_version fw;
2106 e1000_get_fw_version(hw, &fw);
2108 switch (hw->mac.type) {
2111 if (!(e1000_get_flash_presence_i210(hw))) {
2112 ret = snprintf(fw_version, fw_size,
2114 fw.invm_major, fw.invm_minor,
2120 /* if option rom is valid, display its version too */
2122 ret = snprintf(fw_version, fw_size,
2123 "%d.%d, 0x%08x, %d.%d.%d",
2124 fw.eep_major, fw.eep_minor, fw.etrack_id,
2125 fw.or_major, fw.or_build, fw.or_patch);
2128 if (fw.etrack_id != 0X0000) {
2129 ret = snprintf(fw_version, fw_size,
2131 fw.eep_major, fw.eep_minor,
2134 ret = snprintf(fw_version, fw_size,
2136 fw.eep_major, fw.eep_minor,
2143 ret += 1; /* add the size of '\0' */
2144 if (fw_size < (u32)ret)
2151 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2153 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2156 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2157 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2158 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2159 dev_info->rx_offload_capa =
2160 DEV_RX_OFFLOAD_VLAN_STRIP |
2161 DEV_RX_OFFLOAD_IPV4_CKSUM |
2162 DEV_RX_OFFLOAD_UDP_CKSUM |
2163 DEV_RX_OFFLOAD_TCP_CKSUM;
2164 dev_info->tx_offload_capa =
2165 DEV_TX_OFFLOAD_VLAN_INSERT |
2166 DEV_TX_OFFLOAD_IPV4_CKSUM |
2167 DEV_TX_OFFLOAD_UDP_CKSUM |
2168 DEV_TX_OFFLOAD_TCP_CKSUM |
2169 DEV_TX_OFFLOAD_SCTP_CKSUM |
2170 DEV_TX_OFFLOAD_TCP_TSO;
2172 switch (hw->mac.type) {
2174 dev_info->max_rx_queues = 4;
2175 dev_info->max_tx_queues = 4;
2176 dev_info->max_vmdq_pools = 0;
2180 dev_info->max_rx_queues = 16;
2181 dev_info->max_tx_queues = 16;
2182 dev_info->max_vmdq_pools = ETH_8_POOLS;
2183 dev_info->vmdq_queue_num = 16;
2187 dev_info->max_rx_queues = 8;
2188 dev_info->max_tx_queues = 8;
2189 dev_info->max_vmdq_pools = ETH_8_POOLS;
2190 dev_info->vmdq_queue_num = 8;
2194 dev_info->max_rx_queues = 8;
2195 dev_info->max_tx_queues = 8;
2196 dev_info->max_vmdq_pools = ETH_8_POOLS;
2197 dev_info->vmdq_queue_num = 8;
2201 dev_info->max_rx_queues = 8;
2202 dev_info->max_tx_queues = 8;
2206 dev_info->max_rx_queues = 4;
2207 dev_info->max_tx_queues = 4;
2208 dev_info->max_vmdq_pools = 0;
2212 dev_info->max_rx_queues = 2;
2213 dev_info->max_tx_queues = 2;
2214 dev_info->max_vmdq_pools = 0;
2218 /* Should not happen */
2221 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2222 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2223 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2225 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2227 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2228 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2229 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2231 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2235 dev_info->default_txconf = (struct rte_eth_txconf) {
2237 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2238 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2239 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2244 dev_info->rx_desc_lim = rx_desc_lim;
2245 dev_info->tx_desc_lim = tx_desc_lim;
2247 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2248 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2252 static const uint32_t *
2253 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2255 static const uint32_t ptypes[] = {
2256 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2259 RTE_PTYPE_L3_IPV4_EXT,
2261 RTE_PTYPE_L3_IPV6_EXT,
2265 RTE_PTYPE_TUNNEL_IP,
2266 RTE_PTYPE_INNER_L3_IPV6,
2267 RTE_PTYPE_INNER_L3_IPV6_EXT,
2268 RTE_PTYPE_INNER_L4_TCP,
2269 RTE_PTYPE_INNER_L4_UDP,
2273 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2274 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2280 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2282 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2284 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2285 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2286 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2287 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2288 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2289 DEV_RX_OFFLOAD_IPV4_CKSUM |
2290 DEV_RX_OFFLOAD_UDP_CKSUM |
2291 DEV_RX_OFFLOAD_TCP_CKSUM;
2292 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2293 DEV_TX_OFFLOAD_IPV4_CKSUM |
2294 DEV_TX_OFFLOAD_UDP_CKSUM |
2295 DEV_TX_OFFLOAD_TCP_CKSUM |
2296 DEV_TX_OFFLOAD_SCTP_CKSUM |
2297 DEV_TX_OFFLOAD_TCP_TSO;
2298 switch (hw->mac.type) {
2300 dev_info->max_rx_queues = 2;
2301 dev_info->max_tx_queues = 2;
2303 case e1000_vfadapt_i350:
2304 dev_info->max_rx_queues = 1;
2305 dev_info->max_tx_queues = 1;
2308 /* Should not happen */
2312 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2314 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2315 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2316 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2318 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2322 dev_info->default_txconf = (struct rte_eth_txconf) {
2324 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2325 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2326 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2331 dev_info->rx_desc_lim = rx_desc_lim;
2332 dev_info->tx_desc_lim = tx_desc_lim;
2335 /* return 0 means link status changed, -1 means not changed */
2337 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2339 struct e1000_hw *hw =
2340 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2341 struct rte_eth_link link, old;
2342 int link_check, count;
2345 hw->mac.get_link_status = 1;
2347 /* possible wait-to-complete in up to 9 seconds */
2348 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2349 /* Read the real link status */
2350 switch (hw->phy.media_type) {
2351 case e1000_media_type_copper:
2352 /* Do the work to read phy */
2353 e1000_check_for_link(hw);
2354 link_check = !hw->mac.get_link_status;
2357 case e1000_media_type_fiber:
2358 e1000_check_for_link(hw);
2359 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2363 case e1000_media_type_internal_serdes:
2364 e1000_check_for_link(hw);
2365 link_check = hw->mac.serdes_has_link;
2368 /* VF device is type_unknown */
2369 case e1000_media_type_unknown:
2370 eth_igbvf_link_update(hw);
2371 link_check = !hw->mac.get_link_status;
2377 if (link_check || wait_to_complete == 0)
2379 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2381 memset(&link, 0, sizeof(link));
2382 rte_igb_dev_atomic_read_link_status(dev, &link);
2385 /* Now we check if a transition has happened */
2387 uint16_t duplex, speed;
2388 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2389 link.link_duplex = (duplex == FULL_DUPLEX) ?
2390 ETH_LINK_FULL_DUPLEX :
2391 ETH_LINK_HALF_DUPLEX;
2392 link.link_speed = speed;
2393 link.link_status = ETH_LINK_UP;
2394 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2395 ETH_LINK_SPEED_FIXED);
2396 } else if (!link_check) {
2397 link.link_speed = 0;
2398 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2399 link.link_status = ETH_LINK_DOWN;
2400 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2402 rte_igb_dev_atomic_write_link_status(dev, &link);
2405 if (old.link_status == link.link_status)
2413 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2414 * For ASF and Pass Through versions of f/w this means
2415 * that the driver is loaded.
2418 igb_hw_control_acquire(struct e1000_hw *hw)
2422 /* Let firmware know the driver has taken over */
2423 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2424 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2428 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2429 * For ASF and Pass Through versions of f/w this means that the
2430 * driver is no longer loaded.
2433 igb_hw_control_release(struct e1000_hw *hw)
2437 /* Let firmware taken over control of h/w */
2438 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2439 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2440 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2444 * Bit of a misnomer, what this really means is
2445 * to enable OS management of the system... aka
2446 * to disable special hardware management features.
2449 igb_init_manageability(struct e1000_hw *hw)
2451 if (e1000_enable_mng_pass_thru(hw)) {
2452 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2453 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2455 /* disable hardware interception of ARP */
2456 manc &= ~(E1000_MANC_ARP_EN);
2458 /* enable receiving management packets to the host */
2459 manc |= E1000_MANC_EN_MNG2HOST;
2460 manc2h |= 1 << 5; /* Mng Port 623 */
2461 manc2h |= 1 << 6; /* Mng Port 664 */
2462 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2463 E1000_WRITE_REG(hw, E1000_MANC, manc);
2468 igb_release_manageability(struct e1000_hw *hw)
2470 if (e1000_enable_mng_pass_thru(hw)) {
2471 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2473 manc |= E1000_MANC_ARP_EN;
2474 manc &= ~E1000_MANC_EN_MNG2HOST;
2476 E1000_WRITE_REG(hw, E1000_MANC, manc);
2481 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2483 struct e1000_hw *hw =
2484 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487 rctl = E1000_READ_REG(hw, E1000_RCTL);
2488 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2489 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2493 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2495 struct e1000_hw *hw =
2496 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2499 rctl = E1000_READ_REG(hw, E1000_RCTL);
2500 rctl &= (~E1000_RCTL_UPE);
2501 if (dev->data->all_multicast == 1)
2502 rctl |= E1000_RCTL_MPE;
2504 rctl &= (~E1000_RCTL_MPE);
2505 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2509 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2511 struct e1000_hw *hw =
2512 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515 rctl = E1000_READ_REG(hw, E1000_RCTL);
2516 rctl |= E1000_RCTL_MPE;
2517 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2521 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2523 struct e1000_hw *hw =
2524 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527 if (dev->data->promiscuous == 1)
2528 return; /* must remain in all_multicast mode */
2529 rctl = E1000_READ_REG(hw, E1000_RCTL);
2530 rctl &= (~E1000_RCTL_MPE);
2531 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2535 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2537 struct e1000_hw *hw =
2538 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539 struct e1000_vfta * shadow_vfta =
2540 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2545 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2546 E1000_VFTA_ENTRY_MASK);
2547 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2548 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2553 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2555 /* update local VFTA copy */
2556 shadow_vfta->vfta[vid_idx] = vfta;
2562 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2563 enum rte_vlan_type vlan_type,
2566 struct e1000_hw *hw =
2567 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2571 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2573 /* only outer TPID of double VLAN can be configured*/
2574 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2575 reg = E1000_READ_REG(hw, E1000_VET);
2576 reg = (reg & (~E1000_VET_VET_EXT)) |
2577 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2578 E1000_WRITE_REG(hw, E1000_VET, reg);
2583 /* all other TPID values are read-only*/
2584 PMD_DRV_LOG(ERR, "Not supported");
2590 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2592 struct e1000_hw *hw =
2593 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2596 /* Filter Table Disable */
2597 reg = E1000_READ_REG(hw, E1000_RCTL);
2598 reg &= ~E1000_RCTL_CFIEN;
2599 reg &= ~E1000_RCTL_VFE;
2600 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2604 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2606 struct e1000_hw *hw =
2607 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2608 struct e1000_vfta * shadow_vfta =
2609 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2613 /* Filter Table Enable, CFI not used for packet acceptance */
2614 reg = E1000_READ_REG(hw, E1000_RCTL);
2615 reg &= ~E1000_RCTL_CFIEN;
2616 reg |= E1000_RCTL_VFE;
2617 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2619 /* restore VFTA table */
2620 for (i = 0; i < IGB_VFTA_SIZE; i++)
2621 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2625 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2627 struct e1000_hw *hw =
2628 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631 /* VLAN Mode Disable */
2632 reg = E1000_READ_REG(hw, E1000_CTRL);
2633 reg &= ~E1000_CTRL_VME;
2634 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2638 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2640 struct e1000_hw *hw =
2641 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2644 /* VLAN Mode Enable */
2645 reg = E1000_READ_REG(hw, E1000_CTRL);
2646 reg |= E1000_CTRL_VME;
2647 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2651 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2653 struct e1000_hw *hw =
2654 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657 /* CTRL_EXT: Extended VLAN */
2658 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2659 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2660 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2662 /* Update maximum packet length */
2663 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2664 E1000_WRITE_REG(hw, E1000_RLPML,
2665 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2670 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2672 struct e1000_hw *hw =
2673 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2676 /* CTRL_EXT: Extended VLAN */
2677 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2678 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2679 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2681 /* Update maximum packet length */
2682 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2683 E1000_WRITE_REG(hw, E1000_RLPML,
2684 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2689 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2691 if(mask & ETH_VLAN_STRIP_MASK){
2692 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2693 igb_vlan_hw_strip_enable(dev);
2695 igb_vlan_hw_strip_disable(dev);
2698 if(mask & ETH_VLAN_FILTER_MASK){
2699 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2700 igb_vlan_hw_filter_enable(dev);
2702 igb_vlan_hw_filter_disable(dev);
2705 if(mask & ETH_VLAN_EXTEND_MASK){
2706 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2707 igb_vlan_hw_extend_enable(dev);
2709 igb_vlan_hw_extend_disable(dev);
2715 * It enables the interrupt mask and then enable the interrupt.
2718 * Pointer to struct rte_eth_dev.
2721 * - On success, zero.
2722 * - On failure, a negative value.
2725 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2727 struct e1000_interrupt *intr =
2728 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2730 intr->mask |= E1000_ICR_LSC;
2735 /* It clears the interrupt causes and enables the interrupt.
2736 * It will be called once only during nic initialized.
2739 * Pointer to struct rte_eth_dev.
2742 * - On success, zero.
2743 * - On failure, a negative value.
2745 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2747 uint32_t mask, regval;
2748 struct e1000_hw *hw =
2749 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2750 struct rte_eth_dev_info dev_info;
2752 memset(&dev_info, 0, sizeof(dev_info));
2753 eth_igb_infos_get(dev, &dev_info);
2755 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2756 regval = E1000_READ_REG(hw, E1000_EIMS);
2757 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2763 * It reads ICR and gets interrupt causes, check it and set a bit flag
2764 * to update link status.
2767 * Pointer to struct rte_eth_dev.
2770 * - On success, zero.
2771 * - On failure, a negative value.
2774 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2777 struct e1000_hw *hw =
2778 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779 struct e1000_interrupt *intr =
2780 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2782 igb_intr_disable(hw);
2784 /* read-on-clear nic registers here */
2785 icr = E1000_READ_REG(hw, E1000_ICR);
2788 if (icr & E1000_ICR_LSC) {
2789 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2792 if (icr & E1000_ICR_VMMB)
2793 intr->flags |= E1000_FLAG_MAILBOX;
2799 * It executes link_update after knowing an interrupt is prsent.
2802 * Pointer to struct rte_eth_dev.
2805 * - On success, zero.
2806 * - On failure, a negative value.
2809 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2810 struct rte_intr_handle *intr_handle)
2812 struct e1000_hw *hw =
2813 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2814 struct e1000_interrupt *intr =
2815 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2816 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2817 uint32_t tctl, rctl;
2818 struct rte_eth_link link;
2821 if (intr->flags & E1000_FLAG_MAILBOX) {
2822 igb_pf_mbx_process(dev);
2823 intr->flags &= ~E1000_FLAG_MAILBOX;
2826 igb_intr_enable(dev);
2827 rte_intr_enable(intr_handle);
2829 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2830 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2832 /* set get_link_status to check register later */
2833 hw->mac.get_link_status = 1;
2834 ret = eth_igb_link_update(dev, 0);
2836 /* check if link has changed */
2840 memset(&link, 0, sizeof(link));
2841 rte_igb_dev_atomic_read_link_status(dev, &link);
2842 if (link.link_status) {
2844 " Port %d: Link Up - speed %u Mbps - %s",
2846 (unsigned)link.link_speed,
2847 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2848 "full-duplex" : "half-duplex");
2850 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2851 dev->data->port_id);
2854 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2855 pci_dev->addr.domain,
2857 pci_dev->addr.devid,
2858 pci_dev->addr.function);
2859 tctl = E1000_READ_REG(hw, E1000_TCTL);
2860 rctl = E1000_READ_REG(hw, E1000_RCTL);
2861 if (link.link_status) {
2863 tctl |= E1000_TCTL_EN;
2864 rctl |= E1000_RCTL_EN;
2867 tctl &= ~E1000_TCTL_EN;
2868 rctl &= ~E1000_RCTL_EN;
2870 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2871 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2872 E1000_WRITE_FLUSH(hw);
2873 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2880 * Interrupt handler which shall be registered at first.
2883 * Pointer to interrupt handle.
2885 * The address of parameter (struct rte_eth_dev *) regsitered before.
2891 eth_igb_interrupt_handler(void *param)
2893 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2895 eth_igb_interrupt_get_status(dev);
2896 eth_igb_interrupt_action(dev, dev->intr_handle);
2900 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2903 struct e1000_hw *hw =
2904 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2905 struct e1000_interrupt *intr =
2906 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2908 igbvf_intr_disable(hw);
2910 /* read-on-clear nic registers here */
2911 eicr = E1000_READ_REG(hw, E1000_EICR);
2914 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2915 intr->flags |= E1000_FLAG_MAILBOX;
2920 void igbvf_mbx_process(struct rte_eth_dev *dev)
2922 struct e1000_hw *hw =
2923 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2924 struct e1000_mbx_info *mbx = &hw->mbx;
2927 if (mbx->ops.read(hw, &in_msg, 1, 0))
2930 /* PF reset VF event */
2931 if (in_msg == E1000_PF_CONTROL_MSG)
2932 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2936 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2938 struct e1000_interrupt *intr =
2939 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2941 if (intr->flags & E1000_FLAG_MAILBOX) {
2942 igbvf_mbx_process(dev);
2943 intr->flags &= ~E1000_FLAG_MAILBOX;
2946 igbvf_intr_enable(dev);
2947 rte_intr_enable(intr_handle);
2953 eth_igbvf_interrupt_handler(void *param)
2955 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2957 eth_igbvf_interrupt_get_status(dev);
2958 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2962 eth_igb_led_on(struct rte_eth_dev *dev)
2964 struct e1000_hw *hw;
2966 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2971 eth_igb_led_off(struct rte_eth_dev *dev)
2973 struct e1000_hw *hw;
2975 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2976 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2980 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2982 struct e1000_hw *hw;
2987 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2988 fc_conf->pause_time = hw->fc.pause_time;
2989 fc_conf->high_water = hw->fc.high_water;
2990 fc_conf->low_water = hw->fc.low_water;
2991 fc_conf->send_xon = hw->fc.send_xon;
2992 fc_conf->autoneg = hw->mac.autoneg;
2995 * Return rx_pause and tx_pause status according to actual setting of
2996 * the TFCE and RFCE bits in the CTRL register.
2998 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2999 if (ctrl & E1000_CTRL_TFCE)
3004 if (ctrl & E1000_CTRL_RFCE)
3009 if (rx_pause && tx_pause)
3010 fc_conf->mode = RTE_FC_FULL;
3012 fc_conf->mode = RTE_FC_RX_PAUSE;
3014 fc_conf->mode = RTE_FC_TX_PAUSE;
3016 fc_conf->mode = RTE_FC_NONE;
3022 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3024 struct e1000_hw *hw;
3026 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3032 uint32_t rx_buf_size;
3033 uint32_t max_high_water;
3036 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3037 if (fc_conf->autoneg != hw->mac.autoneg)
3039 rx_buf_size = igb_get_rx_buffer_size(hw);
3040 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3042 /* At least reserve one Ethernet frame for watermark */
3043 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3044 if ((fc_conf->high_water > max_high_water) ||
3045 (fc_conf->high_water < fc_conf->low_water)) {
3046 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3047 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3051 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3052 hw->fc.pause_time = fc_conf->pause_time;
3053 hw->fc.high_water = fc_conf->high_water;
3054 hw->fc.low_water = fc_conf->low_water;
3055 hw->fc.send_xon = fc_conf->send_xon;
3057 err = e1000_setup_link_generic(hw);
3058 if (err == E1000_SUCCESS) {
3060 /* check if we want to forward MAC frames - driver doesn't have native
3061 * capability to do that, so we'll write the registers ourselves */
3063 rctl = E1000_READ_REG(hw, E1000_RCTL);
3065 /* set or clear MFLCN.PMCF bit depending on configuration */
3066 if (fc_conf->mac_ctrl_frame_fwd != 0)
3067 rctl |= E1000_RCTL_PMCF;
3069 rctl &= ~E1000_RCTL_PMCF;
3071 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3072 E1000_WRITE_FLUSH(hw);
3077 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3081 #define E1000_RAH_POOLSEL_SHIFT (18)
3083 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3084 uint32_t index, uint32_t pool)
3086 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3089 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3090 rah = E1000_READ_REG(hw, E1000_RAH(index));
3091 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3092 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3097 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3099 uint8_t addr[ETHER_ADDR_LEN];
3100 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3102 memset(addr, 0, sizeof(addr));
3104 e1000_rar_set(hw, addr, index);
3108 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3109 struct ether_addr *addr)
3111 eth_igb_rar_clear(dev, 0);
3113 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3116 * Virtual Function operations
3119 igbvf_intr_disable(struct e1000_hw *hw)
3121 PMD_INIT_FUNC_TRACE();
3123 /* Clear interrupt mask to stop from interrupts being generated */
3124 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3126 E1000_WRITE_FLUSH(hw);
3130 igbvf_stop_adapter(struct rte_eth_dev *dev)
3134 struct rte_eth_dev_info dev_info;
3135 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137 memset(&dev_info, 0, sizeof(dev_info));
3138 eth_igbvf_infos_get(dev, &dev_info);
3140 /* Clear interrupt mask to stop from interrupts being generated */
3141 igbvf_intr_disable(hw);
3143 /* Clear any pending interrupts, flush previous writes */
3144 E1000_READ_REG(hw, E1000_EICR);
3146 /* Disable the transmit unit. Each queue must be disabled. */
3147 for (i = 0; i < dev_info.max_tx_queues; i++)
3148 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3150 /* Disable the receive unit by stopping each queue */
3151 for (i = 0; i < dev_info.max_rx_queues; i++) {
3152 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3153 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3154 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3155 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3159 /* flush all queues disables */
3160 E1000_WRITE_FLUSH(hw);
3164 static int eth_igbvf_link_update(struct e1000_hw *hw)
3166 struct e1000_mbx_info *mbx = &hw->mbx;
3167 struct e1000_mac_info *mac = &hw->mac;
3168 int ret_val = E1000_SUCCESS;
3170 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3173 * We only want to run this if there has been a rst asserted.
3174 * in this case that could mean a link change, device reset,
3175 * or a virtual function reset
3178 /* If we were hit with a reset or timeout drop the link */
3179 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3180 mac->get_link_status = TRUE;
3182 if (!mac->get_link_status)
3185 /* if link status is down no point in checking to see if pf is up */
3186 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3189 /* if we passed all the tests above then the link is up and we no
3190 * longer need to check for link */
3191 mac->get_link_status = FALSE;
3199 igbvf_dev_configure(struct rte_eth_dev *dev)
3201 struct rte_eth_conf* conf = &dev->data->dev_conf;
3203 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3204 dev->data->port_id);
3207 * VF has no ability to enable/disable HW CRC
3208 * Keep the persistent behavior the same as Host PF
3210 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3211 if (!conf->rxmode.hw_strip_crc) {
3212 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3213 conf->rxmode.hw_strip_crc = 1;
3216 if (conf->rxmode.hw_strip_crc) {
3217 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3218 conf->rxmode.hw_strip_crc = 0;
3226 igbvf_dev_start(struct rte_eth_dev *dev)
3228 struct e1000_hw *hw =
3229 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3230 struct e1000_adapter *adapter =
3231 E1000_DEV_PRIVATE(dev->data->dev_private);
3232 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3233 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3235 uint32_t intr_vector = 0;
3237 PMD_INIT_FUNC_TRACE();
3239 hw->mac.ops.reset_hw(hw);
3240 adapter->stopped = 0;
3243 igbvf_set_vfta_all(dev,1);
3245 eth_igbvf_tx_init(dev);
3247 /* This can fail when allocating mbufs for descriptor rings */
3248 ret = eth_igbvf_rx_init(dev);
3250 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3251 igb_dev_clear_queues(dev);
3255 /* check and configure queue intr-vector mapping */
3256 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3257 intr_vector = dev->data->nb_rx_queues;
3258 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3263 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3264 intr_handle->intr_vec =
3265 rte_zmalloc("intr_vec",
3266 dev->data->nb_rx_queues * sizeof(int), 0);
3267 if (!intr_handle->intr_vec) {
3268 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3269 " intr_vec", dev->data->nb_rx_queues);
3274 eth_igbvf_configure_msix_intr(dev);
3276 /* enable uio/vfio intr/eventfd mapping */
3277 rte_intr_enable(intr_handle);
3279 /* resume enabled intr since hw reset */
3280 igbvf_intr_enable(dev);
3286 igbvf_dev_stop(struct rte_eth_dev *dev)
3288 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3289 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3291 PMD_INIT_FUNC_TRACE();
3293 igbvf_stop_adapter(dev);
3296 * Clear what we set, but we still keep shadow_vfta to
3297 * restore after device starts
3299 igbvf_set_vfta_all(dev,0);
3301 igb_dev_clear_queues(dev);
3303 /* disable intr eventfd mapping */
3304 rte_intr_disable(intr_handle);
3306 /* Clean datapath event and queue/vec mapping */
3307 rte_intr_efd_disable(intr_handle);
3308 if (intr_handle->intr_vec) {
3309 rte_free(intr_handle->intr_vec);
3310 intr_handle->intr_vec = NULL;
3315 igbvf_dev_close(struct rte_eth_dev *dev)
3317 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318 struct e1000_adapter *adapter =
3319 E1000_DEV_PRIVATE(dev->data->dev_private);
3320 struct ether_addr addr;
3322 PMD_INIT_FUNC_TRACE();
3326 igbvf_dev_stop(dev);
3327 adapter->stopped = 1;
3328 igb_dev_free_queues(dev);
3331 * reprogram the RAR with a zero mac address,
3332 * to ensure that the VF traffic goes to the PF
3333 * after stop, close and detach of the VF.
3336 memset(&addr, 0, sizeof(addr));
3337 igbvf_default_mac_addr_set(dev, &addr);
3341 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3343 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3345 /* Set both unicast and multicast promisc */
3346 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3350 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3352 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3354 /* If in allmulticast mode leave multicast promisc */
3355 if (dev->data->all_multicast == 1)
3356 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3358 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3362 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3364 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3366 /* In promiscuous mode multicast promisc already set */
3367 if (dev->data->promiscuous == 0)
3368 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3372 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3374 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3376 /* In promiscuous mode leave multicast promisc enabled */
3377 if (dev->data->promiscuous == 0)
3378 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3381 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3383 struct e1000_mbx_info *mbx = &hw->mbx;
3387 /* After set vlan, vlan strip will also be enabled in igb driver*/
3388 msgbuf[0] = E1000_VF_SET_VLAN;
3390 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3392 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3394 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3398 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3402 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3403 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3410 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3412 struct e1000_hw *hw =
3413 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3414 struct e1000_vfta * shadow_vfta =
3415 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3416 int i = 0, j = 0, vfta = 0, mask = 1;
3418 for (i = 0; i < IGB_VFTA_SIZE; i++){
3419 vfta = shadow_vfta->vfta[i];
3422 for (j = 0; j < 32; j++){
3425 (uint16_t)((i<<5)+j), on);
3434 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3436 struct e1000_hw *hw =
3437 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438 struct e1000_vfta * shadow_vfta =
3439 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3440 uint32_t vid_idx = 0;
3441 uint32_t vid_bit = 0;
3444 PMD_INIT_FUNC_TRACE();
3446 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3447 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3449 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3452 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3453 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3455 /*Save what we set and retore it after device reset*/
3457 shadow_vfta->vfta[vid_idx] |= vid_bit;
3459 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3465 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3467 struct e1000_hw *hw =
3468 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3470 /* index is not used by rar_set() */
3471 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3476 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3477 struct rte_eth_rss_reta_entry64 *reta_conf,
3482 uint16_t idx, shift;
3483 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3485 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3486 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3487 "(%d) doesn't match the number hardware can supported "
3488 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3492 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3493 idx = i / RTE_RETA_GROUP_SIZE;
3494 shift = i % RTE_RETA_GROUP_SIZE;
3495 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3499 if (mask == IGB_4_BIT_MASK)
3502 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3503 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3504 if (mask & (0x1 << j))
3505 reta |= reta_conf[idx].reta[shift + j] <<
3508 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3510 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3517 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3518 struct rte_eth_rss_reta_entry64 *reta_conf,
3523 uint16_t idx, shift;
3524 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3526 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3527 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3528 "(%d) doesn't match the number hardware can supported "
3529 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3533 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3534 idx = i / RTE_RETA_GROUP_SIZE;
3535 shift = i % RTE_RETA_GROUP_SIZE;
3536 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3540 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3541 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3542 if (mask & (0x1 << j))
3543 reta_conf[idx].reta[shift + j] =
3544 ((reta >> (CHAR_BIT * j)) &
3552 #define MAC_TYPE_FILTER_SUP(type) do {\
3553 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3554 (type) != e1000_82576 && (type) != e1000_i210 &&\
3555 (type) != e1000_i211)\
3560 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3561 struct rte_eth_syn_filter *filter,
3564 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565 uint32_t synqf, rfctl;
3567 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3570 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3573 if (synqf & E1000_SYN_FILTER_ENABLE)
3576 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3577 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3579 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3580 if (filter->hig_pri)
3581 rfctl |= E1000_RFCTL_SYNQFP;
3583 rfctl &= ~E1000_RFCTL_SYNQFP;
3585 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3587 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3592 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3593 E1000_WRITE_FLUSH(hw);
3598 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3599 struct rte_eth_syn_filter *filter)
3601 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602 uint32_t synqf, rfctl;
3604 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3605 if (synqf & E1000_SYN_FILTER_ENABLE) {
3606 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3607 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3608 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3609 E1000_SYN_FILTER_QUEUE_SHIFT);
3617 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3618 enum rte_filter_op filter_op,
3621 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3624 MAC_TYPE_FILTER_SUP(hw->mac.type);
3626 if (filter_op == RTE_ETH_FILTER_NOP)
3630 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3635 switch (filter_op) {
3636 case RTE_ETH_FILTER_ADD:
3637 ret = eth_igb_syn_filter_set(dev,
3638 (struct rte_eth_syn_filter *)arg,
3641 case RTE_ETH_FILTER_DELETE:
3642 ret = eth_igb_syn_filter_set(dev,
3643 (struct rte_eth_syn_filter *)arg,
3646 case RTE_ETH_FILTER_GET:
3647 ret = eth_igb_syn_filter_get(dev,
3648 (struct rte_eth_syn_filter *)arg);
3651 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3659 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3660 if ((type) != e1000_82580 && (type) != e1000_i350)\
3664 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3666 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3667 struct e1000_2tuple_filter_info *filter_info)
3669 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3671 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3672 return -EINVAL; /* filter index is out of range. */
3673 if (filter->tcp_flags > TCP_FLAG_ALL)
3674 return -EINVAL; /* flags is invalid. */
3676 switch (filter->dst_port_mask) {
3678 filter_info->dst_port_mask = 0;
3679 filter_info->dst_port = filter->dst_port;
3682 filter_info->dst_port_mask = 1;
3685 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3689 switch (filter->proto_mask) {
3691 filter_info->proto_mask = 0;
3692 filter_info->proto = filter->proto;
3695 filter_info->proto_mask = 1;
3698 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3702 filter_info->priority = (uint8_t)filter->priority;
3703 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3704 filter_info->tcp_flags = filter->tcp_flags;
3706 filter_info->tcp_flags = 0;
3711 static inline struct e1000_2tuple_filter *
3712 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3713 struct e1000_2tuple_filter_info *key)
3715 struct e1000_2tuple_filter *it;
3717 TAILQ_FOREACH(it, filter_list, entries) {
3718 if (memcmp(key, &it->filter_info,
3719 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3727 * igb_add_2tuple_filter - add a 2tuple filter
3730 * dev: Pointer to struct rte_eth_dev.
3731 * ntuple_filter: ponter to the filter that will be added.
3734 * - On success, zero.
3735 * - On failure, a negative value.
3738 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3739 struct rte_eth_ntuple_filter *ntuple_filter)
3741 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3742 struct e1000_filter_info *filter_info =
3743 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3744 struct e1000_2tuple_filter *filter;
3745 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3746 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3749 filter = rte_zmalloc("e1000_2tuple_filter",
3750 sizeof(struct e1000_2tuple_filter), 0);
3754 ret = ntuple_filter_to_2tuple(ntuple_filter,
3755 &filter->filter_info);
3760 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3761 &filter->filter_info) != NULL) {
3762 PMD_DRV_LOG(ERR, "filter exists.");
3766 filter->queue = ntuple_filter->queue;
3769 * look for an unused 2tuple filter index,
3770 * and insert the filter to list.
3772 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3773 if (!(filter_info->twotuple_mask & (1 << i))) {
3774 filter_info->twotuple_mask |= 1 << i;
3776 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3782 if (i >= E1000_MAX_TTQF_FILTERS) {
3783 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3788 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3789 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3790 imir |= E1000_IMIR_PORT_BP;
3792 imir &= ~E1000_IMIR_PORT_BP;
3794 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3796 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3797 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3798 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3799 if (filter->filter_info.proto_mask == 0)
3800 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3802 /* tcp flags bits setting. */
3803 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3804 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3805 imir_ext |= E1000_IMIREXT_CTRL_URG;
3806 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3807 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3808 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3809 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3810 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3811 imir_ext |= E1000_IMIREXT_CTRL_RST;
3812 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3813 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3814 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3815 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3817 imir_ext |= E1000_IMIREXT_CTRL_BP;
3818 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3819 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3820 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3825 * igb_remove_2tuple_filter - remove a 2tuple filter
3828 * dev: Pointer to struct rte_eth_dev.
3829 * ntuple_filter: ponter to the filter that will be removed.
3832 * - On success, zero.
3833 * - On failure, a negative value.
3836 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3837 struct rte_eth_ntuple_filter *ntuple_filter)
3839 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840 struct e1000_filter_info *filter_info =
3841 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3842 struct e1000_2tuple_filter_info filter_2tuple;
3843 struct e1000_2tuple_filter *filter;
3846 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3847 ret = ntuple_filter_to_2tuple(ntuple_filter,
3852 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3854 if (filter == NULL) {
3855 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3859 filter_info->twotuple_mask &= ~(1 << filter->index);
3860 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3863 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3864 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3865 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3869 static inline struct e1000_flex_filter *
3870 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3871 struct e1000_flex_filter_info *key)
3873 struct e1000_flex_filter *it;
3875 TAILQ_FOREACH(it, filter_list, entries) {
3876 if (memcmp(key, &it->filter_info,
3877 sizeof(struct e1000_flex_filter_info)) == 0)
3885 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3886 struct rte_eth_flex_filter *filter,
3889 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3890 struct e1000_filter_info *filter_info =
3891 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3892 struct e1000_flex_filter *flex_filter, *it;
3893 uint32_t wufc, queueing, mask;
3895 uint8_t shift, i, j = 0;
3897 flex_filter = rte_zmalloc("e1000_flex_filter",
3898 sizeof(struct e1000_flex_filter), 0);
3899 if (flex_filter == NULL)
3902 flex_filter->filter_info.len = filter->len;
3903 flex_filter->filter_info.priority = filter->priority;
3904 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3905 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3907 /* reverse bits in flex filter's mask*/
3908 for (shift = 0; shift < CHAR_BIT; shift++) {
3909 if (filter->mask[i] & (0x01 << shift))
3910 mask |= (0x80 >> shift);
3912 flex_filter->filter_info.mask[i] = mask;
3915 wufc = E1000_READ_REG(hw, E1000_WUFC);
3916 if (flex_filter->index < E1000_MAX_FHFT)
3917 reg_off = E1000_FHFT(flex_filter->index);
3919 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3922 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3923 &flex_filter->filter_info) != NULL) {
3924 PMD_DRV_LOG(ERR, "filter exists.");
3925 rte_free(flex_filter);
3928 flex_filter->queue = filter->queue;
3930 * look for an unused flex filter index
3931 * and insert the filter into the list.
3933 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3934 if (!(filter_info->flex_mask & (1 << i))) {
3935 filter_info->flex_mask |= 1 << i;
3936 flex_filter->index = i;
3937 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3943 if (i >= E1000_MAX_FLEX_FILTERS) {
3944 PMD_DRV_LOG(ERR, "flex filters are full.");
3945 rte_free(flex_filter);
3949 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3950 (E1000_WUFC_FLX0 << flex_filter->index));
3951 queueing = filter->len |
3952 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3953 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3954 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3956 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3957 E1000_WRITE_REG(hw, reg_off,
3958 flex_filter->filter_info.dwords[j]);
3959 reg_off += sizeof(uint32_t);
3960 E1000_WRITE_REG(hw, reg_off,
3961 flex_filter->filter_info.dwords[++j]);
3962 reg_off += sizeof(uint32_t);
3963 E1000_WRITE_REG(hw, reg_off,
3964 (uint32_t)flex_filter->filter_info.mask[i]);
3965 reg_off += sizeof(uint32_t) * 2;
3969 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3970 &flex_filter->filter_info);
3972 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3973 rte_free(flex_filter);
3977 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3978 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3979 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3980 (~(E1000_WUFC_FLX0 << it->index)));
3982 filter_info->flex_mask &= ~(1 << it->index);
3983 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3985 rte_free(flex_filter);
3992 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3993 struct rte_eth_flex_filter *filter)
3995 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3996 struct e1000_filter_info *filter_info =
3997 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3998 struct e1000_flex_filter flex_filter, *it;
3999 uint32_t wufc, queueing, wufc_en = 0;
4001 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4002 flex_filter.filter_info.len = filter->len;
4003 flex_filter.filter_info.priority = filter->priority;
4004 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4005 memcpy(flex_filter.filter_info.mask, filter->mask,
4006 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4008 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4009 &flex_filter.filter_info);
4011 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4015 wufc = E1000_READ_REG(hw, E1000_WUFC);
4016 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4018 if ((wufc & wufc_en) == wufc_en) {
4019 uint32_t reg_off = 0;
4020 if (it->index < E1000_MAX_FHFT)
4021 reg_off = E1000_FHFT(it->index);
4023 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4025 queueing = E1000_READ_REG(hw,
4026 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4027 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4028 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4029 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4030 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4031 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4038 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4039 enum rte_filter_op filter_op,
4042 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4043 struct rte_eth_flex_filter *filter;
4046 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4048 if (filter_op == RTE_ETH_FILTER_NOP)
4052 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4057 filter = (struct rte_eth_flex_filter *)arg;
4058 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4059 || filter->len % sizeof(uint64_t) != 0) {
4060 PMD_DRV_LOG(ERR, "filter's length is out of range");
4063 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4064 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4068 switch (filter_op) {
4069 case RTE_ETH_FILTER_ADD:
4070 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4072 case RTE_ETH_FILTER_DELETE:
4073 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4075 case RTE_ETH_FILTER_GET:
4076 ret = eth_igb_get_flex_filter(dev, filter);
4079 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4087 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4089 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4090 struct e1000_5tuple_filter_info *filter_info)
4092 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4094 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4095 return -EINVAL; /* filter index is out of range. */
4096 if (filter->tcp_flags > TCP_FLAG_ALL)
4097 return -EINVAL; /* flags is invalid. */
4099 switch (filter->dst_ip_mask) {
4101 filter_info->dst_ip_mask = 0;
4102 filter_info->dst_ip = filter->dst_ip;
4105 filter_info->dst_ip_mask = 1;
4108 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4112 switch (filter->src_ip_mask) {
4114 filter_info->src_ip_mask = 0;
4115 filter_info->src_ip = filter->src_ip;
4118 filter_info->src_ip_mask = 1;
4121 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4125 switch (filter->dst_port_mask) {
4127 filter_info->dst_port_mask = 0;
4128 filter_info->dst_port = filter->dst_port;
4131 filter_info->dst_port_mask = 1;
4134 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4138 switch (filter->src_port_mask) {
4140 filter_info->src_port_mask = 0;
4141 filter_info->src_port = filter->src_port;
4144 filter_info->src_port_mask = 1;
4147 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4151 switch (filter->proto_mask) {
4153 filter_info->proto_mask = 0;
4154 filter_info->proto = filter->proto;
4157 filter_info->proto_mask = 1;
4160 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4164 filter_info->priority = (uint8_t)filter->priority;
4165 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4166 filter_info->tcp_flags = filter->tcp_flags;
4168 filter_info->tcp_flags = 0;
4173 static inline struct e1000_5tuple_filter *
4174 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4175 struct e1000_5tuple_filter_info *key)
4177 struct e1000_5tuple_filter *it;
4179 TAILQ_FOREACH(it, filter_list, entries) {
4180 if (memcmp(key, &it->filter_info,
4181 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4189 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4192 * dev: Pointer to struct rte_eth_dev.
4193 * ntuple_filter: ponter to the filter that will be added.
4196 * - On success, zero.
4197 * - On failure, a negative value.
4200 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4201 struct rte_eth_ntuple_filter *ntuple_filter)
4203 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4204 struct e1000_filter_info *filter_info =
4205 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4206 struct e1000_5tuple_filter *filter;
4207 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4208 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4212 filter = rte_zmalloc("e1000_5tuple_filter",
4213 sizeof(struct e1000_5tuple_filter), 0);
4217 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4218 &filter->filter_info);
4224 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4225 &filter->filter_info) != NULL) {
4226 PMD_DRV_LOG(ERR, "filter exists.");
4230 filter->queue = ntuple_filter->queue;
4233 * look for an unused 5tuple filter index,
4234 * and insert the filter to list.
4236 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4237 if (!(filter_info->fivetuple_mask & (1 << i))) {
4238 filter_info->fivetuple_mask |= 1 << i;
4240 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4246 if (i >= E1000_MAX_FTQF_FILTERS) {
4247 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4252 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4253 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4254 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4255 if (filter->filter_info.dst_ip_mask == 0)
4256 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4257 if (filter->filter_info.src_port_mask == 0)
4258 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4259 if (filter->filter_info.proto_mask == 0)
4260 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4261 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4262 E1000_FTQF_QUEUE_MASK;
4263 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4264 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4265 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4266 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4268 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4269 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4271 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4272 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4273 imir |= E1000_IMIR_PORT_BP;
4275 imir &= ~E1000_IMIR_PORT_BP;
4276 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4278 /* tcp flags bits setting. */
4279 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4280 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4281 imir_ext |= E1000_IMIREXT_CTRL_URG;
4282 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4283 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4284 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4285 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4286 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4287 imir_ext |= E1000_IMIREXT_CTRL_RST;
4288 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4289 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4290 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4291 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4293 imir_ext |= E1000_IMIREXT_CTRL_BP;
4294 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4295 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4300 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4303 * dev: Pointer to struct rte_eth_dev.
4304 * ntuple_filter: ponter to the filter that will be removed.
4307 * - On success, zero.
4308 * - On failure, a negative value.
4311 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4312 struct rte_eth_ntuple_filter *ntuple_filter)
4314 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4315 struct e1000_filter_info *filter_info =
4316 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4317 struct e1000_5tuple_filter_info filter_5tuple;
4318 struct e1000_5tuple_filter *filter;
4321 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4322 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4327 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4329 if (filter == NULL) {
4330 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4334 filter_info->fivetuple_mask &= ~(1 << filter->index);
4335 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4338 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4339 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4340 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4341 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4342 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4343 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4344 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4349 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4352 struct e1000_hw *hw;
4353 struct rte_eth_dev_info dev_info;
4354 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4357 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4359 #ifdef RTE_LIBRTE_82571_SUPPORT
4360 /* XXX: not bigger than max_rx_pktlen */
4361 if (hw->mac.type == e1000_82571)
4364 eth_igb_infos_get(dev, &dev_info);
4366 /* check that mtu is within the allowed range */
4367 if ((mtu < ETHER_MIN_MTU) ||
4368 (frame_size > dev_info.max_rx_pktlen))
4371 /* refuse mtu that requires the support of scattered packets when this
4372 * feature has not been enabled before. */
4373 if (!dev->data->scattered_rx &&
4374 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4377 rctl = E1000_READ_REG(hw, E1000_RCTL);
4379 /* switch to jumbo mode if needed */
4380 if (frame_size > ETHER_MAX_LEN) {
4381 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4382 rctl |= E1000_RCTL_LPE;
4384 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4385 rctl &= ~E1000_RCTL_LPE;
4387 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4389 /* update max frame size */
4390 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4392 E1000_WRITE_REG(hw, E1000_RLPML,
4393 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4399 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4402 * dev: Pointer to struct rte_eth_dev.
4403 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4404 * add: if true, add filter, if false, remove filter
4407 * - On success, zero.
4408 * - On failure, a negative value.
4411 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4412 struct rte_eth_ntuple_filter *ntuple_filter,
4415 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418 switch (ntuple_filter->flags) {
4419 case RTE_5TUPLE_FLAGS:
4420 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4421 if (hw->mac.type != e1000_82576)
4424 ret = igb_add_5tuple_filter_82576(dev,
4427 ret = igb_remove_5tuple_filter_82576(dev,
4430 case RTE_2TUPLE_FLAGS:
4431 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4432 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4435 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4437 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4448 * igb_get_ntuple_filter - get a ntuple filter
4451 * dev: Pointer to struct rte_eth_dev.
4452 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4455 * - On success, zero.
4456 * - On failure, a negative value.
4459 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4460 struct rte_eth_ntuple_filter *ntuple_filter)
4462 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4463 struct e1000_filter_info *filter_info =
4464 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4465 struct e1000_5tuple_filter_info filter_5tuple;
4466 struct e1000_2tuple_filter_info filter_2tuple;
4467 struct e1000_5tuple_filter *p_5tuple_filter;
4468 struct e1000_2tuple_filter *p_2tuple_filter;
4471 switch (ntuple_filter->flags) {
4472 case RTE_5TUPLE_FLAGS:
4473 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4474 if (hw->mac.type != e1000_82576)
4476 memset(&filter_5tuple,
4478 sizeof(struct e1000_5tuple_filter_info));
4479 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4483 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4484 &filter_info->fivetuple_list,
4486 if (p_5tuple_filter == NULL) {
4487 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4490 ntuple_filter->queue = p_5tuple_filter->queue;
4492 case RTE_2TUPLE_FLAGS:
4493 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4494 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4496 memset(&filter_2tuple,
4498 sizeof(struct e1000_2tuple_filter_info));
4499 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4502 p_2tuple_filter = igb_2tuple_filter_lookup(
4503 &filter_info->twotuple_list,
4505 if (p_2tuple_filter == NULL) {
4506 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4509 ntuple_filter->queue = p_2tuple_filter->queue;
4520 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4521 * @dev: pointer to rte_eth_dev structure
4522 * @filter_op:operation will be taken.
4523 * @arg: a pointer to specific structure corresponding to the filter_op
4526 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4527 enum rte_filter_op filter_op,
4530 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4533 MAC_TYPE_FILTER_SUP(hw->mac.type);
4535 if (filter_op == RTE_ETH_FILTER_NOP)
4539 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4544 switch (filter_op) {
4545 case RTE_ETH_FILTER_ADD:
4546 ret = igb_add_del_ntuple_filter(dev,
4547 (struct rte_eth_ntuple_filter *)arg,
4550 case RTE_ETH_FILTER_DELETE:
4551 ret = igb_add_del_ntuple_filter(dev,
4552 (struct rte_eth_ntuple_filter *)arg,
4555 case RTE_ETH_FILTER_GET:
4556 ret = igb_get_ntuple_filter(dev,
4557 (struct rte_eth_ntuple_filter *)arg);
4560 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4568 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4573 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4574 if (filter_info->ethertype_filters[i] == ethertype &&
4575 (filter_info->ethertype_mask & (1 << i)))
4582 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4587 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4588 if (!(filter_info->ethertype_mask & (1 << i))) {
4589 filter_info->ethertype_mask |= 1 << i;
4590 filter_info->ethertype_filters[i] = ethertype;
4598 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4601 if (idx >= E1000_MAX_ETQF_FILTERS)
4603 filter_info->ethertype_mask &= ~(1 << idx);
4604 filter_info->ethertype_filters[idx] = 0;
4610 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4611 struct rte_eth_ethertype_filter *filter,
4614 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4615 struct e1000_filter_info *filter_info =
4616 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4620 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4621 filter->ether_type == ETHER_TYPE_IPv6) {
4622 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4623 " ethertype filter.", filter->ether_type);
4627 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4628 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4631 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4632 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4636 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4637 if (ret >= 0 && add) {
4638 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4639 filter->ether_type);
4642 if (ret < 0 && !add) {
4643 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4644 filter->ether_type);
4649 ret = igb_ethertype_filter_insert(filter_info,
4650 filter->ether_type);
4652 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4656 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4657 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4658 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4660 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4664 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4665 E1000_WRITE_FLUSH(hw);
4671 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4672 struct rte_eth_ethertype_filter *filter)
4674 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4675 struct e1000_filter_info *filter_info =
4676 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4680 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4682 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4683 filter->ether_type);
4687 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4688 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4689 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4691 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4692 E1000_ETQF_QUEUE_SHIFT;
4700 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4701 * @dev: pointer to rte_eth_dev structure
4702 * @filter_op:operation will be taken.
4703 * @arg: a pointer to specific structure corresponding to the filter_op
4706 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4707 enum rte_filter_op filter_op,
4710 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4713 MAC_TYPE_FILTER_SUP(hw->mac.type);
4715 if (filter_op == RTE_ETH_FILTER_NOP)
4719 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4724 switch (filter_op) {
4725 case RTE_ETH_FILTER_ADD:
4726 ret = igb_add_del_ethertype_filter(dev,
4727 (struct rte_eth_ethertype_filter *)arg,
4730 case RTE_ETH_FILTER_DELETE:
4731 ret = igb_add_del_ethertype_filter(dev,
4732 (struct rte_eth_ethertype_filter *)arg,
4735 case RTE_ETH_FILTER_GET:
4736 ret = igb_get_ethertype_filter(dev,
4737 (struct rte_eth_ethertype_filter *)arg);
4740 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4748 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4749 enum rte_filter_type filter_type,
4750 enum rte_filter_op filter_op,
4755 switch (filter_type) {
4756 case RTE_ETH_FILTER_NTUPLE:
4757 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4759 case RTE_ETH_FILTER_ETHERTYPE:
4760 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4762 case RTE_ETH_FILTER_SYN:
4763 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4765 case RTE_ETH_FILTER_FLEXIBLE:
4766 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4769 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4778 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4779 struct ether_addr *mc_addr_set,
4780 uint32_t nb_mc_addr)
4782 struct e1000_hw *hw;
4784 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4785 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4790 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4792 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4793 uint64_t systime_cycles;
4795 switch (hw->mac.type) {
4799 * Need to read System Time Residue Register to be able
4800 * to read the other two registers.
4802 E1000_READ_REG(hw, E1000_SYSTIMR);
4803 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4804 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4805 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4812 * Need to read System Time Residue Register to be able
4813 * to read the other two registers.
4815 E1000_READ_REG(hw, E1000_SYSTIMR);
4816 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4817 /* Only the 8 LSB are valid. */
4818 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4822 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4823 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4828 return systime_cycles;
4832 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4834 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4835 uint64_t rx_tstamp_cycles;
4837 switch (hw->mac.type) {
4840 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4841 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4842 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4848 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4849 /* Only the 8 LSB are valid. */
4850 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4854 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4855 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4860 return rx_tstamp_cycles;
4864 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4866 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4867 uint64_t tx_tstamp_cycles;
4869 switch (hw->mac.type) {
4872 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4873 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4874 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4880 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4881 /* Only the 8 LSB are valid. */
4882 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4886 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4887 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4892 return tx_tstamp_cycles;
4896 igb_start_timecounters(struct rte_eth_dev *dev)
4898 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4899 struct e1000_adapter *adapter =
4900 (struct e1000_adapter *)dev->data->dev_private;
4901 uint32_t incval = 1;
4903 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4905 switch (hw->mac.type) {
4909 /* 32 LSB bits + 8 MSB bits = 40 bits */
4910 mask = (1ULL << 40) - 1;
4915 * Start incrementing the register
4916 * used to timestamp PTP packets.
4918 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4921 incval = E1000_INCVALUE_82576;
4922 shift = IGB_82576_TSYNC_SHIFT;
4923 E1000_WRITE_REG(hw, E1000_TIMINCA,
4924 E1000_INCPERIOD_82576 | incval);
4931 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4932 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4933 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4935 adapter->systime_tc.cc_mask = mask;
4936 adapter->systime_tc.cc_shift = shift;
4937 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4939 adapter->rx_tstamp_tc.cc_mask = mask;
4940 adapter->rx_tstamp_tc.cc_shift = shift;
4941 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4943 adapter->tx_tstamp_tc.cc_mask = mask;
4944 adapter->tx_tstamp_tc.cc_shift = shift;
4945 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4949 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4951 struct e1000_adapter *adapter =
4952 (struct e1000_adapter *)dev->data->dev_private;
4954 adapter->systime_tc.nsec += delta;
4955 adapter->rx_tstamp_tc.nsec += delta;
4956 adapter->tx_tstamp_tc.nsec += delta;
4962 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4965 struct e1000_adapter *adapter =
4966 (struct e1000_adapter *)dev->data->dev_private;
4968 ns = rte_timespec_to_ns(ts);
4970 /* Set the timecounters to a new value. */
4971 adapter->systime_tc.nsec = ns;
4972 adapter->rx_tstamp_tc.nsec = ns;
4973 adapter->tx_tstamp_tc.nsec = ns;
4979 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4981 uint64_t ns, systime_cycles;
4982 struct e1000_adapter *adapter =
4983 (struct e1000_adapter *)dev->data->dev_private;
4985 systime_cycles = igb_read_systime_cyclecounter(dev);
4986 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4987 *ts = rte_ns_to_timespec(ns);
4993 igb_timesync_enable(struct rte_eth_dev *dev)
4995 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4999 /* Stop the timesync system time. */
5000 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5001 /* Reset the timesync system time value. */
5002 switch (hw->mac.type) {
5008 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5011 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5012 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5015 /* Not supported. */
5019 /* Enable system time for it isn't on by default. */
5020 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5021 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5022 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5024 igb_start_timecounters(dev);
5026 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5027 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5029 E1000_ETQF_FILTER_ENABLE |
5032 /* Enable timestamping of received PTP packets. */
5033 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5034 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5035 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5037 /* Enable Timestamping of transmitted PTP packets. */
5038 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5039 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5040 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5046 igb_timesync_disable(struct rte_eth_dev *dev)
5048 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051 /* Disable timestamping of transmitted PTP packets. */
5052 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5053 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5054 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5056 /* Disable timestamping of received PTP packets. */
5057 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5058 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5059 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5061 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5062 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5064 /* Stop incrementating the System Time registers. */
5065 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5071 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5072 struct timespec *timestamp,
5073 uint32_t flags __rte_unused)
5075 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5076 struct e1000_adapter *adapter =
5077 (struct e1000_adapter *)dev->data->dev_private;
5078 uint32_t tsync_rxctl;
5079 uint64_t rx_tstamp_cycles;
5082 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5083 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5086 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5087 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5088 *timestamp = rte_ns_to_timespec(ns);
5094 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5095 struct timespec *timestamp)
5097 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5098 struct e1000_adapter *adapter =
5099 (struct e1000_adapter *)dev->data->dev_private;
5100 uint32_t tsync_txctl;
5101 uint64_t tx_tstamp_cycles;
5104 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5105 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5108 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5109 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5110 *timestamp = rte_ns_to_timespec(ns);
5116 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5120 const struct reg_info *reg_group;
5122 while ((reg_group = igb_regs[g_ind++]))
5123 count += igb_reg_group_count(reg_group);
5129 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5133 const struct reg_info *reg_group;
5135 while ((reg_group = igbvf_regs[g_ind++]))
5136 count += igb_reg_group_count(reg_group);
5142 eth_igb_get_regs(struct rte_eth_dev *dev,
5143 struct rte_dev_reg_info *regs)
5145 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5146 uint32_t *data = regs->data;
5149 const struct reg_info *reg_group;
5152 regs->length = eth_igb_get_reg_length(dev);
5153 regs->width = sizeof(uint32_t);
5157 /* Support only full register dump */
5158 if ((regs->length == 0) ||
5159 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5160 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5162 while ((reg_group = igb_regs[g_ind++]))
5163 count += igb_read_regs_group(dev, &data[count],
5172 igbvf_get_regs(struct rte_eth_dev *dev,
5173 struct rte_dev_reg_info *regs)
5175 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5176 uint32_t *data = regs->data;
5179 const struct reg_info *reg_group;
5182 regs->length = igbvf_get_reg_length(dev);
5183 regs->width = sizeof(uint32_t);
5187 /* Support only full register dump */
5188 if ((regs->length == 0) ||
5189 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5190 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5192 while ((reg_group = igbvf_regs[g_ind++]))
5193 count += igb_read_regs_group(dev, &data[count],
5202 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5204 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5206 /* Return unit is byte count */
5207 return hw->nvm.word_size * 2;
5211 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5212 struct rte_dev_eeprom_info *in_eeprom)
5214 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5215 struct e1000_nvm_info *nvm = &hw->nvm;
5216 uint16_t *data = in_eeprom->data;
5219 first = in_eeprom->offset >> 1;
5220 length = in_eeprom->length >> 1;
5221 if ((first >= hw->nvm.word_size) ||
5222 ((first + length) >= hw->nvm.word_size))
5225 in_eeprom->magic = hw->vendor_id |
5226 ((uint32_t)hw->device_id << 16);
5228 if ((nvm->ops.read) == NULL)
5231 return nvm->ops.read(hw, first, length, data);
5235 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5236 struct rte_dev_eeprom_info *in_eeprom)
5238 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5239 struct e1000_nvm_info *nvm = &hw->nvm;
5240 uint16_t *data = in_eeprom->data;
5243 first = in_eeprom->offset >> 1;
5244 length = in_eeprom->length >> 1;
5245 if ((first >= hw->nvm.word_size) ||
5246 ((first + length) >= hw->nvm.word_size))
5249 in_eeprom->magic = (uint32_t)hw->vendor_id |
5250 ((uint32_t)hw->device_id << 16);
5252 if ((nvm->ops.write) == NULL)
5254 return nvm->ops.write(hw, first, length, data);
5258 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5260 struct e1000_hw *hw =
5261 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5262 uint32_t mask = 1 << queue_id;
5264 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5265 E1000_WRITE_FLUSH(hw);
5271 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5273 struct e1000_hw *hw =
5274 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5275 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5276 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5277 uint32_t mask = 1 << queue_id;
5280 regval = E1000_READ_REG(hw, E1000_EIMS);
5281 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5282 E1000_WRITE_FLUSH(hw);
5284 rte_intr_enable(intr_handle);
5290 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5291 uint8_t index, uint8_t offset)
5293 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5296 val &= ~((uint32_t)0xFF << offset);
5298 /* write vector and valid bit */
5299 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5301 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5305 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5306 uint8_t queue, uint8_t msix_vector)
5310 if (hw->mac.type == e1000_82575) {
5312 tmp = E1000_EICR_RX_QUEUE0 << queue;
5313 else if (direction == 1)
5314 tmp = E1000_EICR_TX_QUEUE0 << queue;
5315 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5316 } else if (hw->mac.type == e1000_82576) {
5317 if ((direction == 0) || (direction == 1))
5318 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5319 ((queue & 0x8) << 1) +
5321 } else if ((hw->mac.type == e1000_82580) ||
5322 (hw->mac.type == e1000_i350) ||
5323 (hw->mac.type == e1000_i354) ||
5324 (hw->mac.type == e1000_i210) ||
5325 (hw->mac.type == e1000_i211)) {
5326 if ((direction == 0) || (direction == 1))
5327 eth_igb_write_ivar(hw, msix_vector,
5329 ((queue & 0x1) << 4) +
5334 /* Sets up the hardware to generate MSI-X interrupts properly
5336 * board private structure
5339 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5342 uint32_t tmpval, regval, intr_mask;
5343 struct e1000_hw *hw =
5344 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5345 uint32_t vec = E1000_MISC_VEC_ID;
5346 uint32_t base = E1000_MISC_VEC_ID;
5347 uint32_t misc_shift = 0;
5348 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5349 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5351 /* won't configure msix register if no mapping is done
5352 * between intr vector and event fd
5354 if (!rte_intr_dp_is_en(intr_handle))
5357 if (rte_intr_allow_others(intr_handle)) {
5358 vec = base = E1000_RX_VEC_START;
5362 /* set interrupt vector for other causes */
5363 if (hw->mac.type == e1000_82575) {
5364 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5365 /* enable MSI-X PBA support */
5366 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5368 /* Auto-Mask interrupts upon ICR read */
5369 tmpval |= E1000_CTRL_EXT_EIAME;
5370 tmpval |= E1000_CTRL_EXT_IRCA;
5372 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5374 /* enable msix_other interrupt */
5375 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5376 regval = E1000_READ_REG(hw, E1000_EIAC);
5377 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5378 regval = E1000_READ_REG(hw, E1000_EIAM);
5379 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5380 } else if ((hw->mac.type == e1000_82576) ||
5381 (hw->mac.type == e1000_82580) ||
5382 (hw->mac.type == e1000_i350) ||
5383 (hw->mac.type == e1000_i354) ||
5384 (hw->mac.type == e1000_i210) ||
5385 (hw->mac.type == e1000_i211)) {
5386 /* turn on MSI-X capability first */
5387 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5388 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5390 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5392 regval = E1000_READ_REG(hw, E1000_EIAC);
5393 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5395 /* enable msix_other interrupt */
5396 regval = E1000_READ_REG(hw, E1000_EIMS);
5397 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5398 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5399 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5402 /* use EIAM to auto-mask when MSI-X interrupt
5403 * is asserted, this saves a register write for every interrupt
5405 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5407 regval = E1000_READ_REG(hw, E1000_EIAM);
5408 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5410 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5411 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5412 intr_handle->intr_vec[queue_id] = vec;
5413 if (vec < base + intr_handle->nb_efd - 1)
5417 E1000_WRITE_FLUSH(hw);
5420 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5421 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5422 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5423 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5424 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5425 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");