1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static int eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static int eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
158 static int igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
190 struct rte_eth_ntuple_filter *ntuple_filter);
191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
194 struct rte_eth_ntuple_filter *ntuple_filter);
195 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
196 struct rte_eth_ntuple_filter *ntuple_filter);
197 static int eth_igb_flow_ops_get(struct rte_eth_dev *dev,
198 const struct rte_flow_ops **ops);
199 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
200 static int eth_igb_get_regs(struct rte_eth_dev *dev,
201 struct rte_dev_reg_info *regs);
202 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
203 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
204 struct rte_dev_eeprom_info *eeprom);
205 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
206 struct rte_dev_eeprom_info *eeprom);
207 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
208 struct rte_eth_dev_module_info *modinfo);
209 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
210 struct rte_dev_eeprom_info *info);
211 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
212 struct rte_ether_addr *mc_addr_set,
213 uint32_t nb_mc_addr);
214 static int igb_timesync_enable(struct rte_eth_dev *dev);
215 static int igb_timesync_disable(struct rte_eth_dev *dev);
216 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
217 struct timespec *timestamp,
219 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
220 struct timespec *timestamp);
221 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
222 static int igb_timesync_read_time(struct rte_eth_dev *dev,
223 struct timespec *timestamp);
224 static int igb_timesync_write_time(struct rte_eth_dev *dev,
225 const struct timespec *timestamp);
226 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
228 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
230 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
231 uint8_t queue, uint8_t msix_vector);
232 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
233 uint8_t index, uint8_t offset);
234 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
235 static void eth_igbvf_interrupt_handler(void *param);
236 static void igbvf_mbx_process(struct rte_eth_dev *dev);
237 static int igb_filter_restore(struct rte_eth_dev *dev);
240 * Define VF Stats MACRO for Non "cleared on read" register
242 #define UPDATE_VF_STAT(reg, last, cur) \
244 u32 latest = E1000_READ_REG(hw, reg); \
245 cur += (latest - last) & UINT_MAX; \
249 #define IGB_FC_PAUSE_TIME 0x0680
250 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
251 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
253 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
255 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
258 * The set of PCI devices this driver supports
260 static const struct rte_pci_id pci_id_igb_map[] = {
261 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
262 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
263 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
264 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
265 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
266 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
267 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
268 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
270 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
271 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
272 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
274 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
275 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
276 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
302 { .vendor_id = 0, /* sentinel */ },
306 * The set of PCI devices this driver supports (for 82576&I350 VF)
308 static const struct rte_pci_id pci_id_igbvf_map[] = {
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
313 { .vendor_id = 0, /* sentinel */ },
316 static const struct rte_eth_desc_lim rx_desc_lim = {
317 .nb_max = E1000_MAX_RING_DESC,
318 .nb_min = E1000_MIN_RING_DESC,
319 .nb_align = IGB_RXD_ALIGN,
322 static const struct rte_eth_desc_lim tx_desc_lim = {
323 .nb_max = E1000_MAX_RING_DESC,
324 .nb_min = E1000_MIN_RING_DESC,
325 .nb_align = IGB_RXD_ALIGN,
326 .nb_seg_max = IGB_TX_MAX_SEG,
327 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
330 static const struct eth_dev_ops eth_igb_ops = {
331 .dev_configure = eth_igb_configure,
332 .dev_start = eth_igb_start,
333 .dev_stop = eth_igb_stop,
334 .dev_set_link_up = eth_igb_dev_set_link_up,
335 .dev_set_link_down = eth_igb_dev_set_link_down,
336 .dev_close = eth_igb_close,
337 .dev_reset = eth_igb_reset,
338 .promiscuous_enable = eth_igb_promiscuous_enable,
339 .promiscuous_disable = eth_igb_promiscuous_disable,
340 .allmulticast_enable = eth_igb_allmulticast_enable,
341 .allmulticast_disable = eth_igb_allmulticast_disable,
342 .link_update = eth_igb_link_update,
343 .stats_get = eth_igb_stats_get,
344 .xstats_get = eth_igb_xstats_get,
345 .xstats_get_by_id = eth_igb_xstats_get_by_id,
346 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
347 .xstats_get_names = eth_igb_xstats_get_names,
348 .stats_reset = eth_igb_stats_reset,
349 .xstats_reset = eth_igb_xstats_reset,
350 .fw_version_get = eth_igb_fw_version_get,
351 .dev_infos_get = eth_igb_infos_get,
352 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
353 .mtu_set = eth_igb_mtu_set,
354 .vlan_filter_set = eth_igb_vlan_filter_set,
355 .vlan_tpid_set = eth_igb_vlan_tpid_set,
356 .vlan_offload_set = eth_igb_vlan_offload_set,
357 .rx_queue_setup = eth_igb_rx_queue_setup,
358 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
359 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
360 .rx_queue_release = eth_igb_rx_queue_release,
361 .tx_queue_setup = eth_igb_tx_queue_setup,
362 .tx_queue_release = eth_igb_tx_queue_release,
363 .tx_done_cleanup = eth_igb_tx_done_cleanup,
364 .dev_led_on = eth_igb_led_on,
365 .dev_led_off = eth_igb_led_off,
366 .flow_ctrl_get = eth_igb_flow_ctrl_get,
367 .flow_ctrl_set = eth_igb_flow_ctrl_set,
368 .mac_addr_add = eth_igb_rar_set,
369 .mac_addr_remove = eth_igb_rar_clear,
370 .mac_addr_set = eth_igb_default_mac_addr_set,
371 .reta_update = eth_igb_rss_reta_update,
372 .reta_query = eth_igb_rss_reta_query,
373 .rss_hash_update = eth_igb_rss_hash_update,
374 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
375 .flow_ops_get = eth_igb_flow_ops_get,
376 .set_mc_addr_list = eth_igb_set_mc_addr_list,
377 .rxq_info_get = igb_rxq_info_get,
378 .txq_info_get = igb_txq_info_get,
379 .timesync_enable = igb_timesync_enable,
380 .timesync_disable = igb_timesync_disable,
381 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
382 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
383 .get_reg = eth_igb_get_regs,
384 .get_eeprom_length = eth_igb_get_eeprom_length,
385 .get_eeprom = eth_igb_get_eeprom,
386 .set_eeprom = eth_igb_set_eeprom,
387 .get_module_info = eth_igb_get_module_info,
388 .get_module_eeprom = eth_igb_get_module_eeprom,
389 .timesync_adjust_time = igb_timesync_adjust_time,
390 .timesync_read_time = igb_timesync_read_time,
391 .timesync_write_time = igb_timesync_write_time,
395 * dev_ops for virtual function, bare necessities for basic vf
396 * operation have been implemented
398 static const struct eth_dev_ops igbvf_eth_dev_ops = {
399 .dev_configure = igbvf_dev_configure,
400 .dev_start = igbvf_dev_start,
401 .dev_stop = igbvf_dev_stop,
402 .dev_close = igbvf_dev_close,
403 .promiscuous_enable = igbvf_promiscuous_enable,
404 .promiscuous_disable = igbvf_promiscuous_disable,
405 .allmulticast_enable = igbvf_allmulticast_enable,
406 .allmulticast_disable = igbvf_allmulticast_disable,
407 .link_update = eth_igb_link_update,
408 .stats_get = eth_igbvf_stats_get,
409 .xstats_get = eth_igbvf_xstats_get,
410 .xstats_get_names = eth_igbvf_xstats_get_names,
411 .stats_reset = eth_igbvf_stats_reset,
412 .xstats_reset = eth_igbvf_stats_reset,
413 .vlan_filter_set = igbvf_vlan_filter_set,
414 .dev_infos_get = eth_igbvf_infos_get,
415 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
416 .rx_queue_setup = eth_igb_rx_queue_setup,
417 .rx_queue_release = eth_igb_rx_queue_release,
418 .tx_queue_setup = eth_igb_tx_queue_setup,
419 .tx_queue_release = eth_igb_tx_queue_release,
420 .tx_done_cleanup = eth_igb_tx_done_cleanup,
421 .set_mc_addr_list = eth_igb_set_mc_addr_list,
422 .rxq_info_get = igb_rxq_info_get,
423 .txq_info_get = igb_txq_info_get,
424 .mac_addr_set = igbvf_default_mac_addr_set,
425 .get_reg = igbvf_get_regs,
428 /* store statistics names and its offset in stats structure */
429 struct rte_igb_xstats_name_off {
430 char name[RTE_ETH_XSTATS_NAME_SIZE];
434 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
435 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
436 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
437 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
438 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
439 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
440 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
441 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
443 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
444 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
445 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
446 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
447 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
448 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
449 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
450 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
451 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
452 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
453 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
455 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
456 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
457 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
458 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
459 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
461 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
463 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
464 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
465 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
466 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
467 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
468 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
469 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
470 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
471 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
472 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
473 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
474 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
475 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
476 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
477 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
478 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
479 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
480 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
482 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
484 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
485 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
486 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
487 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
488 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
489 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
490 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
492 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
495 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
496 sizeof(rte_igb_stats_strings[0]))
498 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
499 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
500 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
501 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
502 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
503 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
506 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
507 sizeof(rte_igbvf_stats_strings[0]))
511 igb_intr_enable(struct rte_eth_dev *dev)
513 struct e1000_interrupt *intr =
514 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
515 struct e1000_hw *hw =
516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
517 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
518 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
520 if (rte_intr_allow_others(intr_handle) &&
521 dev->data->dev_conf.intr_conf.lsc != 0) {
522 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
525 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
526 E1000_WRITE_FLUSH(hw);
530 igb_intr_disable(struct rte_eth_dev *dev)
532 struct e1000_hw *hw =
533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
535 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
537 if (rte_intr_allow_others(intr_handle) &&
538 dev->data->dev_conf.intr_conf.lsc != 0) {
539 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
542 E1000_WRITE_REG(hw, E1000_IMC, ~0);
543 E1000_WRITE_FLUSH(hw);
547 igbvf_intr_enable(struct rte_eth_dev *dev)
549 struct e1000_hw *hw =
550 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 /* only for mailbox */
553 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
554 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
555 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
556 E1000_WRITE_FLUSH(hw);
559 /* only for mailbox now. If RX/TX needed, should extend this function. */
561 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
566 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
567 tmp |= E1000_VTIVAR_VALID;
568 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
572 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
574 struct e1000_hw *hw =
575 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
577 /* Configure VF other cause ivar */
578 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
581 static inline int32_t
582 igb_pf_reset_hw(struct e1000_hw *hw)
587 status = e1000_reset_hw(hw);
589 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
590 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
591 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
592 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
593 E1000_WRITE_FLUSH(hw);
599 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
601 struct e1000_hw *hw =
602 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 hw->vendor_id = pci_dev->id.vendor_id;
606 hw->device_id = pci_dev->id.device_id;
607 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
608 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
610 e1000_set_mac_type(hw);
612 /* need to check if it is a vf device below */
616 igb_reset_swfw_lock(struct e1000_hw *hw)
621 * Do mac ops initialization manually here, since we will need
622 * some function pointers set by this call.
624 ret_val = e1000_init_mac_params(hw);
629 * SMBI lock should not fail in this early stage. If this is the case,
630 * it is due to an improper exit of the application.
631 * So force the release of the faulty lock.
633 if (e1000_get_hw_semaphore_generic(hw) < 0) {
634 PMD_DRV_LOG(DEBUG, "SMBI lock released");
636 e1000_put_hw_semaphore_generic(hw);
638 if (hw->mac.ops.acquire_swfw_sync != NULL) {
642 * Phy lock should not fail in this early stage. If this is the case,
643 * it is due to an improper exit of the application.
644 * So force the release of the faulty lock.
646 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
647 if (hw->bus.func > E1000_FUNC_1)
649 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
650 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
653 hw->mac.ops.release_swfw_sync(hw, mask);
656 * This one is more tricky since it is common to all ports; but
657 * swfw_sync retries last long enough (1s) to be almost sure that if
658 * lock can not be taken it is due to an improper lock of the
661 mask = E1000_SWFW_EEP_SM;
662 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
663 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
665 hw->mac.ops.release_swfw_sync(hw, mask);
668 return E1000_SUCCESS;
671 /* Remove all ntuple filters of the device */
672 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
674 struct e1000_filter_info *filter_info =
675 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
676 struct e1000_5tuple_filter *p_5tuple;
677 struct e1000_2tuple_filter *p_2tuple;
679 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
680 TAILQ_REMOVE(&filter_info->fivetuple_list,
684 filter_info->fivetuple_mask = 0;
685 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
686 TAILQ_REMOVE(&filter_info->twotuple_list,
690 filter_info->twotuple_mask = 0;
695 /* Remove all flex filters of the device */
696 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
698 struct e1000_filter_info *filter_info =
699 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
700 struct e1000_flex_filter *p_flex;
702 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
703 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
706 filter_info->flex_mask = 0;
712 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
716 struct e1000_hw *hw =
717 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
718 struct e1000_vfta * shadow_vfta =
719 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
720 struct e1000_filter_info *filter_info =
721 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
722 struct e1000_adapter *adapter =
723 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
727 eth_dev->dev_ops = ð_igb_ops;
728 eth_dev->rx_queue_count = eth_igb_rx_queue_count;
729 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
730 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
731 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
732 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
733 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
734 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
736 /* for secondary processes, we don't initialise any further as primary
737 * has already done this work. Only check we don't need a different
739 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
740 if (eth_dev->data->scattered_rx)
741 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
745 rte_eth_copy_pci_info(eth_dev, pci_dev);
746 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
748 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
750 igb_identify_hardware(eth_dev, pci_dev);
751 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
756 e1000_get_bus_info(hw);
758 /* Reset any pending lock */
759 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
764 /* Finish initialization */
765 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
771 hw->phy.autoneg_wait_to_complete = 0;
772 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
775 if (hw->phy.media_type == e1000_media_type_copper) {
776 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
777 hw->phy.disable_polarity_correction = 0;
778 hw->phy.ms_type = e1000_ms_hw_default;
782 * Start from a known state, this is important in reading the nvm
787 /* Make sure we have a good EEPROM before we read from it */
788 if (e1000_validate_nvm_checksum(hw) < 0) {
790 * Some PCI-E parts fail the first check due to
791 * the link being in sleep state, call it again,
792 * if it fails a second time its a real issue.
794 if (e1000_validate_nvm_checksum(hw) < 0) {
795 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
801 /* Read the permanent MAC address out of the EEPROM */
802 if (e1000_read_mac_addr(hw) != 0) {
803 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
808 /* Allocate memory for storing MAC addresses */
809 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
810 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
811 if (eth_dev->data->mac_addrs == NULL) {
812 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
813 "store MAC addresses",
814 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
819 /* Copy the permanent MAC address */
820 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
821 ð_dev->data->mac_addrs[0]);
823 /* initialize the vfta */
824 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
826 /* Now initialize the hardware */
827 if (igb_hardware_init(hw) != 0) {
828 PMD_INIT_LOG(ERR, "Hardware initialization failed");
829 rte_free(eth_dev->data->mac_addrs);
830 eth_dev->data->mac_addrs = NULL;
834 hw->mac.get_link_status = 1;
835 adapter->stopped = 0;
837 /* Indicate SOL/IDER usage */
838 if (e1000_check_reset_block(hw) < 0) {
839 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
843 /* initialize PF if max_vfs not zero */
844 igb_pf_host_init(eth_dev);
846 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
847 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
848 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
849 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
850 E1000_WRITE_FLUSH(hw);
852 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
853 eth_dev->data->port_id, pci_dev->id.vendor_id,
854 pci_dev->id.device_id);
856 rte_intr_callback_register(&pci_dev->intr_handle,
857 eth_igb_interrupt_handler,
860 /* enable uio/vfio intr/eventfd mapping */
861 rte_intr_enable(&pci_dev->intr_handle);
863 /* enable support intr */
864 igb_intr_enable(eth_dev);
866 eth_igb_dev_set_link_down(eth_dev);
868 /* initialize filter info */
869 memset(filter_info, 0,
870 sizeof(struct e1000_filter_info));
872 TAILQ_INIT(&filter_info->flex_list);
873 TAILQ_INIT(&filter_info->twotuple_list);
874 TAILQ_INIT(&filter_info->fivetuple_list);
876 TAILQ_INIT(&igb_filter_ntuple_list);
877 TAILQ_INIT(&igb_filter_ethertype_list);
878 TAILQ_INIT(&igb_filter_syn_list);
879 TAILQ_INIT(&igb_filter_flex_list);
880 TAILQ_INIT(&igb_filter_rss_list);
881 TAILQ_INIT(&igb_flow_list);
886 igb_hw_control_release(hw);
892 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
894 PMD_INIT_FUNC_TRACE();
896 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
899 eth_igb_close(eth_dev);
905 * Virtual Function device init
908 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
910 struct rte_pci_device *pci_dev;
911 struct rte_intr_handle *intr_handle;
912 struct e1000_adapter *adapter =
913 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
914 struct e1000_hw *hw =
915 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
917 struct rte_ether_addr *perm_addr =
918 (struct rte_ether_addr *)hw->mac.perm_addr;
920 PMD_INIT_FUNC_TRACE();
922 eth_dev->dev_ops = &igbvf_eth_dev_ops;
923 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
924 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
925 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
926 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
927 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
928 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
930 /* for secondary processes, we don't initialise any further as primary
931 * has already done this work. Only check we don't need a different
933 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
934 if (eth_dev->data->scattered_rx)
935 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
939 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
940 rte_eth_copy_pci_info(eth_dev, pci_dev);
941 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
943 hw->device_id = pci_dev->id.device_id;
944 hw->vendor_id = pci_dev->id.vendor_id;
945 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
946 adapter->stopped = 0;
948 /* Initialize the shared code (base driver) */
949 diag = e1000_setup_init_funcs(hw, TRUE);
951 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
956 /* init_mailbox_params */
957 hw->mbx.ops.init_params(hw);
959 /* Disable the interrupts for VF */
960 igbvf_intr_disable(hw);
962 diag = hw->mac.ops.reset_hw(hw);
964 /* Allocate memory for storing MAC addresses */
965 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
966 hw->mac.rar_entry_count, 0);
967 if (eth_dev->data->mac_addrs == NULL) {
969 "Failed to allocate %d bytes needed to store MAC "
971 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
975 /* Generate a random MAC address, if none was assigned by PF. */
976 if (rte_is_zero_ether_addr(perm_addr)) {
977 rte_eth_random_addr(perm_addr->addr_bytes);
978 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
979 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
980 "%02x:%02x:%02x:%02x:%02x:%02x",
981 perm_addr->addr_bytes[0],
982 perm_addr->addr_bytes[1],
983 perm_addr->addr_bytes[2],
984 perm_addr->addr_bytes[3],
985 perm_addr->addr_bytes[4],
986 perm_addr->addr_bytes[5]);
989 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
991 rte_free(eth_dev->data->mac_addrs);
992 eth_dev->data->mac_addrs = NULL;
995 /* Copy the permanent MAC address */
996 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
997 ð_dev->data->mac_addrs[0]);
999 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1001 eth_dev->data->port_id, pci_dev->id.vendor_id,
1002 pci_dev->id.device_id, "igb_mac_82576_vf");
1004 intr_handle = &pci_dev->intr_handle;
1005 rte_intr_callback_register(intr_handle,
1006 eth_igbvf_interrupt_handler, eth_dev);
1012 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1014 PMD_INIT_FUNC_TRACE();
1016 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1019 igbvf_dev_close(eth_dev);
1024 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1025 struct rte_pci_device *pci_dev)
1027 return rte_eth_dev_pci_generic_probe(pci_dev,
1028 sizeof(struct e1000_adapter), eth_igb_dev_init);
1031 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1033 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1036 static struct rte_pci_driver rte_igb_pmd = {
1037 .id_table = pci_id_igb_map,
1038 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1039 .probe = eth_igb_pci_probe,
1040 .remove = eth_igb_pci_remove,
1044 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1045 struct rte_pci_device *pci_dev)
1047 return rte_eth_dev_pci_generic_probe(pci_dev,
1048 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1051 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1053 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1057 * virtual function driver struct
1059 static struct rte_pci_driver rte_igbvf_pmd = {
1060 .id_table = pci_id_igbvf_map,
1061 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1062 .probe = eth_igbvf_pci_probe,
1063 .remove = eth_igbvf_pci_remove,
1067 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1069 struct e1000_hw *hw =
1070 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1071 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1072 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1073 rctl |= E1000_RCTL_VFE;
1074 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1078 igb_check_mq_mode(struct rte_eth_dev *dev)
1080 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1081 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1082 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1083 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1085 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1086 tx_mq_mode == ETH_MQ_TX_DCB ||
1087 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1088 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1091 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1092 /* Check multi-queue mode.
1093 * To no break software we accept ETH_MQ_RX_NONE as this might
1094 * be used to turn off VLAN filter.
1097 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1098 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1099 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1100 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1102 /* Only support one queue on VFs.
1103 * RSS together with SRIOV is not supported.
1105 PMD_INIT_LOG(ERR, "SRIOV is active,"
1106 " wrong mq_mode rx %d.",
1110 /* TX mode is not used here, so mode might be ignored.*/
1111 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1112 /* SRIOV only works in VMDq enable mode */
1113 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1114 " TX mode %d is not supported. "
1115 " Driver will behave as %d mode.",
1116 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1119 /* check valid queue number */
1120 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1121 PMD_INIT_LOG(ERR, "SRIOV is active,"
1122 " only support one queue on VFs.");
1126 /* To no break software that set invalid mode, only display
1127 * warning if invalid mode is used.
1129 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1130 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1131 rx_mq_mode != ETH_MQ_RX_RSS) {
1132 /* RSS together with VMDq not supported*/
1133 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1138 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1139 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1140 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1141 " Due to txmode is meaningless in this"
1142 " driver, just ignore.",
1150 eth_igb_configure(struct rte_eth_dev *dev)
1152 struct e1000_interrupt *intr =
1153 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1156 PMD_INIT_FUNC_TRACE();
1158 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1159 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1161 /* multipe queue mode checking */
1162 ret = igb_check_mq_mode(dev);
1164 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1169 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1170 PMD_INIT_FUNC_TRACE();
1176 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1179 struct e1000_hw *hw =
1180 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181 uint32_t tctl, rctl;
1183 tctl = E1000_READ_REG(hw, E1000_TCTL);
1184 rctl = E1000_READ_REG(hw, E1000_RCTL);
1188 tctl |= E1000_TCTL_EN;
1189 rctl |= E1000_RCTL_EN;
1192 tctl &= ~E1000_TCTL_EN;
1193 rctl &= ~E1000_RCTL_EN;
1195 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1196 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1197 E1000_WRITE_FLUSH(hw);
1201 eth_igb_start(struct rte_eth_dev *dev)
1203 struct e1000_hw *hw =
1204 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205 struct e1000_adapter *adapter =
1206 E1000_DEV_PRIVATE(dev->data->dev_private);
1207 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1208 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1210 uint32_t intr_vector = 0;
1216 PMD_INIT_FUNC_TRACE();
1218 /* disable uio/vfio intr/eventfd mapping */
1219 rte_intr_disable(intr_handle);
1221 /* Power up the phy. Needed to make the link go Up */
1222 eth_igb_dev_set_link_up(dev);
1225 * Packet Buffer Allocation (PBA)
1226 * Writing PBA sets the receive portion of the buffer
1227 * the remainder is used for the transmit buffer.
1229 if (hw->mac.type == e1000_82575) {
1232 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1233 E1000_WRITE_REG(hw, E1000_PBA, pba);
1236 /* Put the address into the Receive Address Array */
1237 e1000_rar_set(hw, hw->mac.addr, 0);
1239 /* Initialize the hardware */
1240 if (igb_hardware_init(hw)) {
1241 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1244 adapter->stopped = 0;
1246 E1000_WRITE_REG(hw, E1000_VET,
1247 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1249 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1250 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1251 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1252 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1253 E1000_WRITE_FLUSH(hw);
1255 /* configure PF module if SRIOV enabled */
1256 igb_pf_host_configure(dev);
1258 /* check and configure queue intr-vector mapping */
1259 if ((rte_intr_cap_multiple(intr_handle) ||
1260 !RTE_ETH_DEV_SRIOV(dev).active) &&
1261 dev->data->dev_conf.intr_conf.rxq != 0) {
1262 intr_vector = dev->data->nb_rx_queues;
1263 if (rte_intr_efd_enable(intr_handle, intr_vector))
1267 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1268 intr_handle->intr_vec =
1269 rte_zmalloc("intr_vec",
1270 dev->data->nb_rx_queues * sizeof(int), 0);
1271 if (intr_handle->intr_vec == NULL) {
1272 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1273 " intr_vec", dev->data->nb_rx_queues);
1278 /* confiugre msix for rx interrupt */
1279 eth_igb_configure_msix_intr(dev);
1281 /* Configure for OS presence */
1282 igb_init_manageability(hw);
1284 eth_igb_tx_init(dev);
1286 /* This can fail when allocating mbufs for descriptor rings */
1287 ret = eth_igb_rx_init(dev);
1289 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1290 igb_dev_clear_queues(dev);
1294 e1000_clear_hw_cntrs_base_generic(hw);
1297 * VLAN Offload Settings
1299 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1300 ETH_VLAN_EXTEND_MASK;
1301 ret = eth_igb_vlan_offload_set(dev, mask);
1303 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1304 igb_dev_clear_queues(dev);
1308 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1309 /* Enable VLAN filter since VMDq always use VLAN filter */
1310 igb_vmdq_vlan_hw_filter_enable(dev);
1313 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1314 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1315 (hw->mac.type == e1000_i211)) {
1316 /* Configure EITR with the maximum possible value (0xFFFF) */
1317 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1320 /* Setup link speed and duplex */
1321 speeds = &dev->data->dev_conf.link_speeds;
1322 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1323 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1324 hw->mac.autoneg = 1;
1327 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1330 hw->phy.autoneg_advertised = 0;
1332 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1333 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1334 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1336 goto error_invalid_config;
1338 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1339 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1342 if (*speeds & ETH_LINK_SPEED_10M) {
1343 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1346 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1347 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1350 if (*speeds & ETH_LINK_SPEED_100M) {
1351 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1354 if (*speeds & ETH_LINK_SPEED_1G) {
1355 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1358 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1359 goto error_invalid_config;
1361 /* Set/reset the mac.autoneg based on the link speed,
1365 hw->mac.autoneg = 0;
1366 hw->mac.forced_speed_duplex =
1367 hw->phy.autoneg_advertised;
1369 hw->mac.autoneg = 1;
1373 e1000_setup_link(hw);
1375 if (rte_intr_allow_others(intr_handle)) {
1376 /* check if lsc interrupt is enabled */
1377 if (dev->data->dev_conf.intr_conf.lsc != 0)
1378 eth_igb_lsc_interrupt_setup(dev, TRUE);
1380 eth_igb_lsc_interrupt_setup(dev, FALSE);
1382 rte_intr_callback_unregister(intr_handle,
1383 eth_igb_interrupt_handler,
1385 if (dev->data->dev_conf.intr_conf.lsc != 0)
1386 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1387 " no intr multiplex");
1390 /* check if rxq interrupt is enabled */
1391 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1392 rte_intr_dp_is_en(intr_handle))
1393 eth_igb_rxq_interrupt_setup(dev);
1395 /* enable uio/vfio intr/eventfd mapping */
1396 rte_intr_enable(intr_handle);
1398 /* resume enabled intr since hw reset */
1399 igb_intr_enable(dev);
1401 /* restore all types filter */
1402 igb_filter_restore(dev);
1404 eth_igb_rxtx_control(dev, true);
1405 eth_igb_link_update(dev, 0);
1407 PMD_INIT_LOG(DEBUG, "<<");
1411 error_invalid_config:
1412 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1413 dev->data->dev_conf.link_speeds, dev->data->port_id);
1414 igb_dev_clear_queues(dev);
1418 /*********************************************************************
1420 * This routine disables all traffic on the adapter by issuing a
1421 * global reset on the MAC.
1423 **********************************************************************/
1425 eth_igb_stop(struct rte_eth_dev *dev)
1427 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1429 struct rte_eth_link link;
1430 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1431 struct e1000_adapter *adapter =
1432 E1000_DEV_PRIVATE(dev->data->dev_private);
1434 if (adapter->stopped)
1437 eth_igb_rxtx_control(dev, false);
1439 igb_intr_disable(dev);
1441 /* disable intr eventfd mapping */
1442 rte_intr_disable(intr_handle);
1444 igb_pf_reset_hw(hw);
1445 E1000_WRITE_REG(hw, E1000_WUC, 0);
1447 /* Set bit for Go Link disconnect if PHY reset is not blocked */
1448 if (hw->mac.type >= e1000_82580 &&
1449 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1452 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1453 phpm_reg |= E1000_82580_PM_GO_LINKD;
1454 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1457 /* Power down the phy. Needed to make the link go Down */
1458 eth_igb_dev_set_link_down(dev);
1460 igb_dev_clear_queues(dev);
1462 /* clear the recorded link status */
1463 memset(&link, 0, sizeof(link));
1464 rte_eth_linkstatus_set(dev, &link);
1466 if (!rte_intr_allow_others(intr_handle))
1467 /* resume to the default handler */
1468 rte_intr_callback_register(intr_handle,
1469 eth_igb_interrupt_handler,
1472 /* Clean datapath event and queue/vec mapping */
1473 rte_intr_efd_disable(intr_handle);
1474 if (intr_handle->intr_vec != NULL) {
1475 rte_free(intr_handle->intr_vec);
1476 intr_handle->intr_vec = NULL;
1479 adapter->stopped = true;
1480 dev->data->dev_started = 0;
1486 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1488 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490 if (hw->phy.media_type == e1000_media_type_copper)
1491 e1000_power_up_phy(hw);
1493 e1000_power_up_fiber_serdes_link(hw);
1499 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1501 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503 if (hw->phy.media_type == e1000_media_type_copper)
1504 e1000_power_down_phy(hw);
1506 e1000_shutdown_fiber_serdes_link(hw);
1512 eth_igb_close(struct rte_eth_dev *dev)
1514 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515 struct rte_eth_link link;
1516 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1517 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1518 struct e1000_filter_info *filter_info =
1519 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1522 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1525 ret = eth_igb_stop(dev);
1527 e1000_phy_hw_reset(hw);
1528 igb_release_manageability(hw);
1529 igb_hw_control_release(hw);
1531 /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1532 if (hw->mac.type >= e1000_82580 &&
1533 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1536 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1537 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1538 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1541 igb_dev_free_queues(dev);
1543 if (intr_handle->intr_vec) {
1544 rte_free(intr_handle->intr_vec);
1545 intr_handle->intr_vec = NULL;
1548 memset(&link, 0, sizeof(link));
1549 rte_eth_linkstatus_set(dev, &link);
1551 /* Reset any pending lock */
1552 igb_reset_swfw_lock(hw);
1554 /* uninitialize PF if max_vfs not zero */
1555 igb_pf_host_uninit(dev);
1557 rte_intr_callback_unregister(intr_handle,
1558 eth_igb_interrupt_handler, dev);
1560 /* clear the SYN filter info */
1561 filter_info->syn_info = 0;
1563 /* clear the ethertype filters info */
1564 filter_info->ethertype_mask = 0;
1565 memset(filter_info->ethertype_filters, 0,
1566 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1568 /* clear the rss filter info */
1569 memset(&filter_info->rss_info, 0,
1570 sizeof(struct igb_rte_flow_rss_conf));
1572 /* remove all ntuple filters of the device */
1573 igb_ntuple_filter_uninit(dev);
1575 /* remove all flex filters of the device */
1576 igb_flex_filter_uninit(dev);
1578 /* clear all the filters list */
1579 igb_filterlist_flush(dev);
1588 eth_igb_reset(struct rte_eth_dev *dev)
1592 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1593 * its VF to make them align with it. The detailed notification
1594 * mechanism is PMD specific and is currently not implemented.
1595 * To avoid unexpected behavior in VF, currently reset of PF with
1596 * SR-IOV activation is not supported. It might be supported later.
1598 if (dev->data->sriov.active)
1601 ret = eth_igb_dev_uninit(dev);
1605 ret = eth_igb_dev_init(dev);
1612 igb_get_rx_buffer_size(struct e1000_hw *hw)
1614 uint32_t rx_buf_size;
1615 if (hw->mac.type == e1000_82576) {
1616 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1617 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1618 /* PBS needs to be translated according to a lookup table */
1619 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1620 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1621 rx_buf_size = (rx_buf_size << 10);
1622 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1623 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1625 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1631 /*********************************************************************
1633 * Initialize the hardware
1635 **********************************************************************/
1637 igb_hardware_init(struct e1000_hw *hw)
1639 uint32_t rx_buf_size;
1642 /* Let the firmware know the OS is in control */
1643 igb_hw_control_acquire(hw);
1646 * These parameters control the automatic generation (Tx) and
1647 * response (Rx) to Ethernet PAUSE frames.
1648 * - High water mark should allow for at least two standard size (1518)
1649 * frames to be received after sending an XOFF.
1650 * - Low water mark works best when it is very near the high water mark.
1651 * This allows the receiver to restart by sending XON when it has
1652 * drained a bit. Here we use an arbitrary value of 1500 which will
1653 * restart after one full frame is pulled from the buffer. There
1654 * could be several smaller frames in the buffer and if so they will
1655 * not trigger the XON until their total number reduces the buffer
1657 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1659 rx_buf_size = igb_get_rx_buffer_size(hw);
1661 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1662 hw->fc.low_water = hw->fc.high_water - 1500;
1663 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1664 hw->fc.send_xon = 1;
1666 /* Set Flow control, use the tunable location if sane */
1667 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1668 hw->fc.requested_mode = igb_fc_setting;
1670 hw->fc.requested_mode = e1000_fc_none;
1672 /* Issue a global reset */
1673 igb_pf_reset_hw(hw);
1674 E1000_WRITE_REG(hw, E1000_WUC, 0);
1676 diag = e1000_init_hw(hw);
1680 E1000_WRITE_REG(hw, E1000_VET,
1681 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1682 e1000_get_phy_info(hw);
1683 e1000_check_for_link(hw);
1688 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1690 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1694 uint64_t old_gprc = stats->gprc;
1695 uint64_t old_gptc = stats->gptc;
1696 uint64_t old_tpr = stats->tpr;
1697 uint64_t old_tpt = stats->tpt;
1698 uint64_t old_rpthc = stats->rpthc;
1699 uint64_t old_hgptc = stats->hgptc;
1701 if(hw->phy.media_type == e1000_media_type_copper ||
1702 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1704 E1000_READ_REG(hw,E1000_SYMERRS);
1705 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1708 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1709 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1710 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1711 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1713 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1714 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1715 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1716 stats->dc += E1000_READ_REG(hw, E1000_DC);
1717 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1718 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1719 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1721 ** For watchdog management we need to know if we have been
1722 ** paused during the last interval, so capture that here.
1724 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1725 stats->xoffrxc += pause_frames;
1726 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1727 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1728 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1729 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1730 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1731 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1732 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1733 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1734 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1735 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1736 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1737 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1739 /* For the 64-bit byte counters the low dword must be read first. */
1740 /* Both registers clear on the read of the high dword */
1742 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1743 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1744 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1745 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1746 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1747 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1748 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1750 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1751 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1752 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1753 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1754 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1756 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1757 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1759 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1760 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1761 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1762 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1763 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1764 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1766 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1767 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1768 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1769 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1770 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1771 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1772 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1773 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1775 /* Interrupt Counts */
1777 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1778 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1779 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1780 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1781 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1782 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1783 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1784 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1785 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1787 /* Host to Card Statistics */
1789 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1790 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1791 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1792 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1793 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1794 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1795 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1796 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1797 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1798 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1799 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1800 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1801 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1802 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1803 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1804 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1806 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1807 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1808 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1809 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1810 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1811 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1815 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1817 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818 struct e1000_hw_stats *stats =
1819 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1821 igb_read_stats_registers(hw, stats);
1823 if (rte_stats == NULL)
1827 rte_stats->imissed = stats->mpc;
1828 rte_stats->ierrors = stats->crcerrs + stats->rlec +
1829 stats->rxerrc + stats->algnerrc + stats->cexterr;
1832 rte_stats->oerrors = stats->ecol + stats->latecol;
1834 rte_stats->ipackets = stats->gprc;
1835 rte_stats->opackets = stats->gptc;
1836 rte_stats->ibytes = stats->gorc;
1837 rte_stats->obytes = stats->gotc;
1842 eth_igb_stats_reset(struct rte_eth_dev *dev)
1844 struct e1000_hw_stats *hw_stats =
1845 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1847 /* HW registers are cleared on read */
1848 eth_igb_stats_get(dev, NULL);
1850 /* Reset software totals */
1851 memset(hw_stats, 0, sizeof(*hw_stats));
1857 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1859 struct e1000_hw_stats *stats =
1860 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1862 /* HW registers are cleared on read */
1863 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1865 /* Reset software totals */
1866 memset(stats, 0, sizeof(*stats));
1871 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1872 struct rte_eth_xstat_name *xstats_names,
1873 __rte_unused unsigned int size)
1877 if (xstats_names == NULL)
1878 return IGB_NB_XSTATS;
1880 /* Note: limit checked in rte_eth_xstats_names() */
1882 for (i = 0; i < IGB_NB_XSTATS; i++) {
1883 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1884 sizeof(xstats_names[i].name));
1887 return IGB_NB_XSTATS;
1890 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1891 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1897 if (xstats_names == NULL)
1898 return IGB_NB_XSTATS;
1900 for (i = 0; i < IGB_NB_XSTATS; i++)
1901 strlcpy(xstats_names[i].name,
1902 rte_igb_stats_strings[i].name,
1903 sizeof(xstats_names[i].name));
1905 return IGB_NB_XSTATS;
1908 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1910 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1913 for (i = 0; i < limit; i++) {
1914 if (ids[i] >= IGB_NB_XSTATS) {
1915 PMD_INIT_LOG(ERR, "id value isn't valid");
1918 strcpy(xstats_names[i].name,
1919 xstats_names_copy[ids[i]].name);
1926 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1929 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930 struct e1000_hw_stats *hw_stats =
1931 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1934 if (n < IGB_NB_XSTATS)
1935 return IGB_NB_XSTATS;
1937 igb_read_stats_registers(hw, hw_stats);
1939 /* If this is a reset xstats is NULL, and we have cleared the
1940 * registers by reading them.
1945 /* Extended stats */
1946 for (i = 0; i < IGB_NB_XSTATS; i++) {
1948 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1949 rte_igb_stats_strings[i].offset);
1952 return IGB_NB_XSTATS;
1956 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1957 uint64_t *values, unsigned int n)
1962 struct e1000_hw *hw =
1963 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964 struct e1000_hw_stats *hw_stats =
1965 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1967 if (n < IGB_NB_XSTATS)
1968 return IGB_NB_XSTATS;
1970 igb_read_stats_registers(hw, hw_stats);
1972 /* If this is a reset xstats is NULL, and we have cleared the
1973 * registers by reading them.
1978 /* Extended stats */
1979 for (i = 0; i < IGB_NB_XSTATS; i++)
1980 values[i] = *(uint64_t *)(((char *)hw_stats) +
1981 rte_igb_stats_strings[i].offset);
1983 return IGB_NB_XSTATS;
1986 uint64_t values_copy[IGB_NB_XSTATS];
1988 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1991 for (i = 0; i < n; i++) {
1992 if (ids[i] >= IGB_NB_XSTATS) {
1993 PMD_INIT_LOG(ERR, "id value isn't valid");
1996 values[i] = values_copy[ids[i]];
2003 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2005 /* Good Rx packets, include VF loopback */
2006 UPDATE_VF_STAT(E1000_VFGPRC,
2007 hw_stats->last_gprc, hw_stats->gprc);
2009 /* Good Rx octets, include VF loopback */
2010 UPDATE_VF_STAT(E1000_VFGORC,
2011 hw_stats->last_gorc, hw_stats->gorc);
2013 /* Good Tx packets, include VF loopback */
2014 UPDATE_VF_STAT(E1000_VFGPTC,
2015 hw_stats->last_gptc, hw_stats->gptc);
2017 /* Good Tx octets, include VF loopback */
2018 UPDATE_VF_STAT(E1000_VFGOTC,
2019 hw_stats->last_gotc, hw_stats->gotc);
2021 /* Rx Multicst packets */
2022 UPDATE_VF_STAT(E1000_VFMPRC,
2023 hw_stats->last_mprc, hw_stats->mprc);
2025 /* Good Rx loopback packets */
2026 UPDATE_VF_STAT(E1000_VFGPRLBC,
2027 hw_stats->last_gprlbc, hw_stats->gprlbc);
2029 /* Good Rx loopback octets */
2030 UPDATE_VF_STAT(E1000_VFGORLBC,
2031 hw_stats->last_gorlbc, hw_stats->gorlbc);
2033 /* Good Tx loopback packets */
2034 UPDATE_VF_STAT(E1000_VFGPTLBC,
2035 hw_stats->last_gptlbc, hw_stats->gptlbc);
2037 /* Good Tx loopback octets */
2038 UPDATE_VF_STAT(E1000_VFGOTLBC,
2039 hw_stats->last_gotlbc, hw_stats->gotlbc);
2042 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2043 struct rte_eth_xstat_name *xstats_names,
2044 __rte_unused unsigned limit)
2048 if (xstats_names != NULL)
2049 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2050 strlcpy(xstats_names[i].name,
2051 rte_igbvf_stats_strings[i].name,
2052 sizeof(xstats_names[i].name));
2054 return IGBVF_NB_XSTATS;
2058 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2061 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2063 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2066 if (n < IGBVF_NB_XSTATS)
2067 return IGBVF_NB_XSTATS;
2069 igbvf_read_stats_registers(hw, hw_stats);
2074 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2076 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2077 rte_igbvf_stats_strings[i].offset);
2080 return IGBVF_NB_XSTATS;
2084 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2086 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2088 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2090 igbvf_read_stats_registers(hw, hw_stats);
2092 if (rte_stats == NULL)
2095 rte_stats->ipackets = hw_stats->gprc;
2096 rte_stats->ibytes = hw_stats->gorc;
2097 rte_stats->opackets = hw_stats->gptc;
2098 rte_stats->obytes = hw_stats->gotc;
2103 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2105 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2106 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2108 /* Sync HW register to the last stats */
2109 eth_igbvf_stats_get(dev, NULL);
2111 /* reset HW current stats*/
2112 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2113 offsetof(struct e1000_vf_stats, gprc));
2119 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2122 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123 struct e1000_fw_version fw;
2126 e1000_get_fw_version(hw, &fw);
2128 switch (hw->mac.type) {
2131 if (!(e1000_get_flash_presence_i210(hw))) {
2132 ret = snprintf(fw_version, fw_size,
2134 fw.invm_major, fw.invm_minor,
2140 /* if option rom is valid, display its version too */
2142 ret = snprintf(fw_version, fw_size,
2143 "%d.%d, 0x%08x, %d.%d.%d",
2144 fw.eep_major, fw.eep_minor, fw.etrack_id,
2145 fw.or_major, fw.or_build, fw.or_patch);
2148 if (fw.etrack_id != 0X0000) {
2149 ret = snprintf(fw_version, fw_size,
2151 fw.eep_major, fw.eep_minor,
2154 ret = snprintf(fw_version, fw_size,
2156 fw.eep_major, fw.eep_minor,
2163 ret += 1; /* add the size of '\0' */
2164 if (fw_size < (u32)ret)
2171 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2173 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2176 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2177 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2178 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2179 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2180 dev_info->rx_queue_offload_capa;
2181 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2182 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2183 dev_info->tx_queue_offload_capa;
2185 switch (hw->mac.type) {
2187 dev_info->max_rx_queues = 4;
2188 dev_info->max_tx_queues = 4;
2189 dev_info->max_vmdq_pools = 0;
2193 dev_info->max_rx_queues = 16;
2194 dev_info->max_tx_queues = 16;
2195 dev_info->max_vmdq_pools = ETH_8_POOLS;
2196 dev_info->vmdq_queue_num = 16;
2200 dev_info->max_rx_queues = 8;
2201 dev_info->max_tx_queues = 8;
2202 dev_info->max_vmdq_pools = ETH_8_POOLS;
2203 dev_info->vmdq_queue_num = 8;
2207 dev_info->max_rx_queues = 8;
2208 dev_info->max_tx_queues = 8;
2209 dev_info->max_vmdq_pools = ETH_8_POOLS;
2210 dev_info->vmdq_queue_num = 8;
2214 dev_info->max_rx_queues = 8;
2215 dev_info->max_tx_queues = 8;
2219 dev_info->max_rx_queues = 4;
2220 dev_info->max_tx_queues = 4;
2221 dev_info->max_vmdq_pools = 0;
2225 dev_info->max_rx_queues = 2;
2226 dev_info->max_tx_queues = 2;
2227 dev_info->max_vmdq_pools = 0;
2231 /* Should not happen */
2234 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2235 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2236 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2238 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2240 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2241 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2242 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2244 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2249 dev_info->default_txconf = (struct rte_eth_txconf) {
2251 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2252 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2253 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2258 dev_info->rx_desc_lim = rx_desc_lim;
2259 dev_info->tx_desc_lim = tx_desc_lim;
2261 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2262 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2265 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2266 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2271 static const uint32_t *
2272 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2274 static const uint32_t ptypes[] = {
2275 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2278 RTE_PTYPE_L3_IPV4_EXT,
2280 RTE_PTYPE_L3_IPV6_EXT,
2284 RTE_PTYPE_TUNNEL_IP,
2285 RTE_PTYPE_INNER_L3_IPV6,
2286 RTE_PTYPE_INNER_L3_IPV6_EXT,
2287 RTE_PTYPE_INNER_L4_TCP,
2288 RTE_PTYPE_INNER_L4_UDP,
2292 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2293 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2299 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2301 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2303 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2304 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2305 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2306 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2307 DEV_TX_OFFLOAD_IPV4_CKSUM |
2308 DEV_TX_OFFLOAD_UDP_CKSUM |
2309 DEV_TX_OFFLOAD_TCP_CKSUM |
2310 DEV_TX_OFFLOAD_SCTP_CKSUM |
2311 DEV_TX_OFFLOAD_TCP_TSO;
2312 switch (hw->mac.type) {
2314 dev_info->max_rx_queues = 2;
2315 dev_info->max_tx_queues = 2;
2317 case e1000_vfadapt_i350:
2318 dev_info->max_rx_queues = 1;
2319 dev_info->max_tx_queues = 1;
2322 /* Should not happen */
2326 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2327 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2328 dev_info->rx_queue_offload_capa;
2329 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2330 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2331 dev_info->tx_queue_offload_capa;
2333 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2335 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2336 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2337 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2339 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2344 dev_info->default_txconf = (struct rte_eth_txconf) {
2346 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2347 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2348 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2353 dev_info->rx_desc_lim = rx_desc_lim;
2354 dev_info->tx_desc_lim = tx_desc_lim;
2359 /* return 0 means link status changed, -1 means not changed */
2361 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2363 struct e1000_hw *hw =
2364 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2365 struct rte_eth_link link;
2366 int link_check, count;
2369 hw->mac.get_link_status = 1;
2371 /* possible wait-to-complete in up to 9 seconds */
2372 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2373 /* Read the real link status */
2374 switch (hw->phy.media_type) {
2375 case e1000_media_type_copper:
2376 /* Do the work to read phy */
2377 e1000_check_for_link(hw);
2378 link_check = !hw->mac.get_link_status;
2381 case e1000_media_type_fiber:
2382 e1000_check_for_link(hw);
2383 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2387 case e1000_media_type_internal_serdes:
2388 e1000_check_for_link(hw);
2389 link_check = hw->mac.serdes_has_link;
2392 /* VF device is type_unknown */
2393 case e1000_media_type_unknown:
2394 eth_igbvf_link_update(hw);
2395 link_check = !hw->mac.get_link_status;
2401 if (link_check || wait_to_complete == 0)
2403 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2405 memset(&link, 0, sizeof(link));
2407 /* Now we check if a transition has happened */
2409 uint16_t duplex, speed;
2410 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2411 link.link_duplex = (duplex == FULL_DUPLEX) ?
2412 ETH_LINK_FULL_DUPLEX :
2413 ETH_LINK_HALF_DUPLEX;
2414 link.link_speed = speed;
2415 link.link_status = ETH_LINK_UP;
2416 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2417 ETH_LINK_SPEED_FIXED);
2418 } else if (!link_check) {
2419 link.link_speed = 0;
2420 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2421 link.link_status = ETH_LINK_DOWN;
2422 link.link_autoneg = ETH_LINK_FIXED;
2425 return rte_eth_linkstatus_set(dev, &link);
2429 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2430 * For ASF and Pass Through versions of f/w this means
2431 * that the driver is loaded.
2434 igb_hw_control_acquire(struct e1000_hw *hw)
2438 /* Let firmware know the driver has taken over */
2439 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2440 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2444 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2445 * For ASF and Pass Through versions of f/w this means that the
2446 * driver is no longer loaded.
2449 igb_hw_control_release(struct e1000_hw *hw)
2453 /* Let firmware taken over control of h/w */
2454 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2455 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2456 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2460 * Bit of a misnomer, what this really means is
2461 * to enable OS management of the system... aka
2462 * to disable special hardware management features.
2465 igb_init_manageability(struct e1000_hw *hw)
2467 if (e1000_enable_mng_pass_thru(hw)) {
2468 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2469 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2471 /* disable hardware interception of ARP */
2472 manc &= ~(E1000_MANC_ARP_EN);
2474 /* enable receiving management packets to the host */
2475 manc |= E1000_MANC_EN_MNG2HOST;
2476 manc2h |= 1 << 5; /* Mng Port 623 */
2477 manc2h |= 1 << 6; /* Mng Port 664 */
2478 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2479 E1000_WRITE_REG(hw, E1000_MANC, manc);
2484 igb_release_manageability(struct e1000_hw *hw)
2486 if (e1000_enable_mng_pass_thru(hw)) {
2487 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2489 manc |= E1000_MANC_ARP_EN;
2490 manc &= ~E1000_MANC_EN_MNG2HOST;
2492 E1000_WRITE_REG(hw, E1000_MANC, manc);
2497 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2499 struct e1000_hw *hw =
2500 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2503 rctl = E1000_READ_REG(hw, E1000_RCTL);
2504 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2505 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2511 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2513 struct e1000_hw *hw =
2514 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2517 rctl = E1000_READ_REG(hw, E1000_RCTL);
2518 rctl &= (~E1000_RCTL_UPE);
2519 if (dev->data->all_multicast == 1)
2520 rctl |= E1000_RCTL_MPE;
2522 rctl &= (~E1000_RCTL_MPE);
2523 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2529 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2531 struct e1000_hw *hw =
2532 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535 rctl = E1000_READ_REG(hw, E1000_RCTL);
2536 rctl |= E1000_RCTL_MPE;
2537 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2543 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2545 struct e1000_hw *hw =
2546 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549 if (dev->data->promiscuous == 1)
2550 return 0; /* must remain in all_multicast mode */
2551 rctl = E1000_READ_REG(hw, E1000_RCTL);
2552 rctl &= (~E1000_RCTL_MPE);
2553 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2559 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2561 struct e1000_hw *hw =
2562 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2563 struct e1000_vfta * shadow_vfta =
2564 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2569 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2570 E1000_VFTA_ENTRY_MASK);
2571 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2572 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2577 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2579 /* update local VFTA copy */
2580 shadow_vfta->vfta[vid_idx] = vfta;
2586 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2587 enum rte_vlan_type vlan_type,
2590 struct e1000_hw *hw =
2591 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2594 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2595 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2597 /* only outer TPID of double VLAN can be configured*/
2598 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2599 reg = E1000_READ_REG(hw, E1000_VET);
2600 reg = (reg & (~E1000_VET_VET_EXT)) |
2601 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2602 E1000_WRITE_REG(hw, E1000_VET, reg);
2607 /* all other TPID values are read-only*/
2608 PMD_DRV_LOG(ERR, "Not supported");
2614 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2616 struct e1000_hw *hw =
2617 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2620 /* Filter Table Disable */
2621 reg = E1000_READ_REG(hw, E1000_RCTL);
2622 reg &= ~E1000_RCTL_CFIEN;
2623 reg &= ~E1000_RCTL_VFE;
2624 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2628 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2630 struct e1000_hw *hw =
2631 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632 struct e1000_vfta * shadow_vfta =
2633 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2637 /* Filter Table Enable, CFI not used for packet acceptance */
2638 reg = E1000_READ_REG(hw, E1000_RCTL);
2639 reg &= ~E1000_RCTL_CFIEN;
2640 reg |= E1000_RCTL_VFE;
2641 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2643 /* restore VFTA table */
2644 for (i = 0; i < IGB_VFTA_SIZE; i++)
2645 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2649 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2651 struct e1000_hw *hw =
2652 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2655 /* VLAN Mode Disable */
2656 reg = E1000_READ_REG(hw, E1000_CTRL);
2657 reg &= ~E1000_CTRL_VME;
2658 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2662 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2664 struct e1000_hw *hw =
2665 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668 /* VLAN Mode Enable */
2669 reg = E1000_READ_REG(hw, E1000_CTRL);
2670 reg |= E1000_CTRL_VME;
2671 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2675 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2677 struct e1000_hw *hw =
2678 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681 /* CTRL_EXT: Extended VLAN */
2682 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2683 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2684 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2686 /* Update maximum packet length */
2687 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2688 E1000_WRITE_REG(hw, E1000_RLPML,
2689 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2694 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2696 struct e1000_hw *hw =
2697 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2700 /* CTRL_EXT: Extended VLAN */
2701 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2702 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2703 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2705 /* Update maximum packet length */
2706 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2707 E1000_WRITE_REG(hw, E1000_RLPML,
2708 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2713 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2715 struct rte_eth_rxmode *rxmode;
2717 rxmode = &dev->data->dev_conf.rxmode;
2718 if(mask & ETH_VLAN_STRIP_MASK){
2719 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2720 igb_vlan_hw_strip_enable(dev);
2722 igb_vlan_hw_strip_disable(dev);
2725 if(mask & ETH_VLAN_FILTER_MASK){
2726 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2727 igb_vlan_hw_filter_enable(dev);
2729 igb_vlan_hw_filter_disable(dev);
2732 if(mask & ETH_VLAN_EXTEND_MASK){
2733 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2734 igb_vlan_hw_extend_enable(dev);
2736 igb_vlan_hw_extend_disable(dev);
2744 * It enables the interrupt mask and then enable the interrupt.
2747 * Pointer to struct rte_eth_dev.
2752 * - On success, zero.
2753 * - On failure, a negative value.
2756 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2758 struct e1000_interrupt *intr =
2759 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2762 intr->mask |= E1000_ICR_LSC;
2764 intr->mask &= ~E1000_ICR_LSC;
2769 /* It clears the interrupt causes and enables the interrupt.
2770 * It will be called once only during nic initialized.
2773 * Pointer to struct rte_eth_dev.
2776 * - On success, zero.
2777 * - On failure, a negative value.
2779 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2781 uint32_t mask, regval;
2783 struct e1000_hw *hw =
2784 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2786 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2787 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2788 struct rte_eth_dev_info dev_info;
2790 memset(&dev_info, 0, sizeof(dev_info));
2791 ret = eth_igb_infos_get(dev, &dev_info);
2795 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2796 regval = E1000_READ_REG(hw, E1000_EIMS);
2797 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2803 * It reads ICR and gets interrupt causes, check it and set a bit flag
2804 * to update link status.
2807 * Pointer to struct rte_eth_dev.
2810 * - On success, zero.
2811 * - On failure, a negative value.
2814 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2817 struct e1000_hw *hw =
2818 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819 struct e1000_interrupt *intr =
2820 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2822 igb_intr_disable(dev);
2824 /* read-on-clear nic registers here */
2825 icr = E1000_READ_REG(hw, E1000_ICR);
2828 if (icr & E1000_ICR_LSC) {
2829 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2832 if (icr & E1000_ICR_VMMB)
2833 intr->flags |= E1000_FLAG_MAILBOX;
2839 * It executes link_update after knowing an interrupt is prsent.
2842 * Pointer to struct rte_eth_dev.
2845 * - On success, zero.
2846 * - On failure, a negative value.
2849 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2850 struct rte_intr_handle *intr_handle)
2852 struct e1000_hw *hw =
2853 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854 struct e1000_interrupt *intr =
2855 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2856 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2857 struct rte_eth_link link;
2860 if (intr->flags & E1000_FLAG_MAILBOX) {
2861 igb_pf_mbx_process(dev);
2862 intr->flags &= ~E1000_FLAG_MAILBOX;
2865 igb_intr_enable(dev);
2866 rte_intr_ack(intr_handle);
2868 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2869 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2871 /* set get_link_status to check register later */
2872 hw->mac.get_link_status = 1;
2873 ret = eth_igb_link_update(dev, 0);
2875 /* check if link has changed */
2879 rte_eth_linkstatus_get(dev, &link);
2880 if (link.link_status) {
2882 " Port %d: Link Up - speed %u Mbps - %s",
2884 (unsigned)link.link_speed,
2885 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2886 "full-duplex" : "half-duplex");
2888 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2889 dev->data->port_id);
2892 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2893 pci_dev->addr.domain,
2895 pci_dev->addr.devid,
2896 pci_dev->addr.function);
2897 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2904 * Interrupt handler which shall be registered at first.
2907 * Pointer to interrupt handle.
2909 * The address of parameter (struct rte_eth_dev *) regsitered before.
2915 eth_igb_interrupt_handler(void *param)
2917 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2919 eth_igb_interrupt_get_status(dev);
2920 eth_igb_interrupt_action(dev, dev->intr_handle);
2924 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2927 struct e1000_hw *hw =
2928 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929 struct e1000_interrupt *intr =
2930 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2932 igbvf_intr_disable(hw);
2934 /* read-on-clear nic registers here */
2935 eicr = E1000_READ_REG(hw, E1000_EICR);
2938 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2939 intr->flags |= E1000_FLAG_MAILBOX;
2944 void igbvf_mbx_process(struct rte_eth_dev *dev)
2946 struct e1000_hw *hw =
2947 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2948 struct e1000_mbx_info *mbx = &hw->mbx;
2951 /* peek the message first */
2952 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2954 /* PF reset VF event */
2955 if (in_msg == E1000_PF_CONTROL_MSG) {
2956 /* dummy mbx read to ack pf */
2957 if (mbx->ops.read(hw, &in_msg, 1, 0))
2959 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2965 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2967 struct e1000_interrupt *intr =
2968 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2970 if (intr->flags & E1000_FLAG_MAILBOX) {
2971 igbvf_mbx_process(dev);
2972 intr->flags &= ~E1000_FLAG_MAILBOX;
2975 igbvf_intr_enable(dev);
2976 rte_intr_ack(intr_handle);
2982 eth_igbvf_interrupt_handler(void *param)
2984 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2986 eth_igbvf_interrupt_get_status(dev);
2987 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2991 eth_igb_led_on(struct rte_eth_dev *dev)
2993 struct e1000_hw *hw;
2995 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2996 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3000 eth_igb_led_off(struct rte_eth_dev *dev)
3002 struct e1000_hw *hw;
3004 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3005 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3009 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3011 struct e1000_hw *hw;
3016 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017 fc_conf->pause_time = hw->fc.pause_time;
3018 fc_conf->high_water = hw->fc.high_water;
3019 fc_conf->low_water = hw->fc.low_water;
3020 fc_conf->send_xon = hw->fc.send_xon;
3021 fc_conf->autoneg = hw->mac.autoneg;
3024 * Return rx_pause and tx_pause status according to actual setting of
3025 * the TFCE and RFCE bits in the CTRL register.
3027 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3028 if (ctrl & E1000_CTRL_TFCE)
3033 if (ctrl & E1000_CTRL_RFCE)
3038 if (rx_pause && tx_pause)
3039 fc_conf->mode = RTE_FC_FULL;
3041 fc_conf->mode = RTE_FC_RX_PAUSE;
3043 fc_conf->mode = RTE_FC_TX_PAUSE;
3045 fc_conf->mode = RTE_FC_NONE;
3051 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3053 struct e1000_hw *hw;
3055 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3061 uint32_t rx_buf_size;
3062 uint32_t max_high_water;
3066 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067 if (fc_conf->autoneg != hw->mac.autoneg)
3069 rx_buf_size = igb_get_rx_buffer_size(hw);
3070 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3072 /* At least reserve one Ethernet frame for watermark */
3073 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3074 if ((fc_conf->high_water > max_high_water) ||
3075 (fc_conf->high_water < fc_conf->low_water)) {
3076 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3077 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3081 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3082 hw->fc.pause_time = fc_conf->pause_time;
3083 hw->fc.high_water = fc_conf->high_water;
3084 hw->fc.low_water = fc_conf->low_water;
3085 hw->fc.send_xon = fc_conf->send_xon;
3087 err = e1000_setup_link_generic(hw);
3088 if (err == E1000_SUCCESS) {
3090 /* check if we want to forward MAC frames - driver doesn't have native
3091 * capability to do that, so we'll write the registers ourselves */
3093 rctl = E1000_READ_REG(hw, E1000_RCTL);
3095 /* set or clear MFLCN.PMCF bit depending on configuration */
3096 if (fc_conf->mac_ctrl_frame_fwd != 0)
3097 rctl |= E1000_RCTL_PMCF;
3099 rctl &= ~E1000_RCTL_PMCF;
3101 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3104 * check if we want to change flow control mode - driver doesn't have native
3105 * capability to do that, so we'll write the registers ourselves
3107 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3110 * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits depending
3113 switch (fc_conf->mode) {
3115 ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE;
3117 case RTE_FC_RX_PAUSE:
3118 ctrl |= E1000_CTRL_RFCE;
3119 ctrl &= ~E1000_CTRL_TFCE;
3121 case RTE_FC_TX_PAUSE:
3122 ctrl |= E1000_CTRL_TFCE;
3123 ctrl &= ~E1000_CTRL_RFCE;
3126 ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE;
3129 PMD_INIT_LOG(ERR, "invalid flow control mode");
3133 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3135 E1000_WRITE_FLUSH(hw);
3140 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3144 #define E1000_RAH_POOLSEL_SHIFT (18)
3146 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3147 uint32_t index, uint32_t pool)
3149 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3152 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3153 rah = E1000_READ_REG(hw, E1000_RAH(index));
3154 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3155 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3160 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3162 uint8_t addr[RTE_ETHER_ADDR_LEN];
3163 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3165 memset(addr, 0, sizeof(addr));
3167 e1000_rar_set(hw, addr, index);
3171 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3172 struct rte_ether_addr *addr)
3174 eth_igb_rar_clear(dev, 0);
3175 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3180 * Virtual Function operations
3183 igbvf_intr_disable(struct e1000_hw *hw)
3185 PMD_INIT_FUNC_TRACE();
3187 /* Clear interrupt mask to stop from interrupts being generated */
3188 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3190 E1000_WRITE_FLUSH(hw);
3194 igbvf_stop_adapter(struct rte_eth_dev *dev)
3198 struct rte_eth_dev_info dev_info;
3199 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3202 memset(&dev_info, 0, sizeof(dev_info));
3203 ret = eth_igbvf_infos_get(dev, &dev_info);
3207 /* Clear interrupt mask to stop from interrupts being generated */
3208 igbvf_intr_disable(hw);
3210 /* Clear any pending interrupts, flush previous writes */
3211 E1000_READ_REG(hw, E1000_EICR);
3213 /* Disable the transmit unit. Each queue must be disabled. */
3214 for (i = 0; i < dev_info.max_tx_queues; i++)
3215 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3217 /* Disable the receive unit by stopping each queue */
3218 for (i = 0; i < dev_info.max_rx_queues; i++) {
3219 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3220 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3221 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3222 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3226 /* flush all queues disables */
3227 E1000_WRITE_FLUSH(hw);
3231 static int eth_igbvf_link_update(struct e1000_hw *hw)
3233 struct e1000_mbx_info *mbx = &hw->mbx;
3234 struct e1000_mac_info *mac = &hw->mac;
3235 int ret_val = E1000_SUCCESS;
3237 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3240 * We only want to run this if there has been a rst asserted.
3241 * in this case that could mean a link change, device reset,
3242 * or a virtual function reset
3245 /* If we were hit with a reset or timeout drop the link */
3246 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3247 mac->get_link_status = TRUE;
3249 if (!mac->get_link_status)
3252 /* if link status is down no point in checking to see if pf is up */
3253 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3256 /* if we passed all the tests above then the link is up and we no
3257 * longer need to check for link */
3258 mac->get_link_status = FALSE;
3266 igbvf_dev_configure(struct rte_eth_dev *dev)
3268 struct rte_eth_conf* conf = &dev->data->dev_conf;
3270 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3271 dev->data->port_id);
3273 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3274 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3277 * VF has no ability to enable/disable HW CRC
3278 * Keep the persistent behavior the same as Host PF
3280 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3281 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3282 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3283 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3286 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3287 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3288 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3296 igbvf_dev_start(struct rte_eth_dev *dev)
3298 struct e1000_hw *hw =
3299 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300 struct e1000_adapter *adapter =
3301 E1000_DEV_PRIVATE(dev->data->dev_private);
3302 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3303 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3305 uint32_t intr_vector = 0;
3307 PMD_INIT_FUNC_TRACE();
3309 hw->mac.ops.reset_hw(hw);
3310 adapter->stopped = 0;
3313 igbvf_set_vfta_all(dev,1);
3315 eth_igbvf_tx_init(dev);
3317 /* This can fail when allocating mbufs for descriptor rings */
3318 ret = eth_igbvf_rx_init(dev);
3320 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3321 igb_dev_clear_queues(dev);
3325 /* check and configure queue intr-vector mapping */
3326 if (rte_intr_cap_multiple(intr_handle) &&
3327 dev->data->dev_conf.intr_conf.rxq) {
3328 intr_vector = dev->data->nb_rx_queues;
3329 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3334 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3335 intr_handle->intr_vec =
3336 rte_zmalloc("intr_vec",
3337 dev->data->nb_rx_queues * sizeof(int), 0);
3338 if (!intr_handle->intr_vec) {
3339 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3340 " intr_vec", dev->data->nb_rx_queues);
3345 eth_igbvf_configure_msix_intr(dev);
3347 /* enable uio/vfio intr/eventfd mapping */
3348 rte_intr_enable(intr_handle);
3350 /* resume enabled intr since hw reset */
3351 igbvf_intr_enable(dev);
3357 igbvf_dev_stop(struct rte_eth_dev *dev)
3359 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3360 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3361 struct e1000_adapter *adapter =
3362 E1000_DEV_PRIVATE(dev->data->dev_private);
3364 if (adapter->stopped)
3367 PMD_INIT_FUNC_TRACE();
3369 igbvf_stop_adapter(dev);
3372 * Clear what we set, but we still keep shadow_vfta to
3373 * restore after device starts
3375 igbvf_set_vfta_all(dev,0);
3377 igb_dev_clear_queues(dev);
3379 /* disable intr eventfd mapping */
3380 rte_intr_disable(intr_handle);
3382 /* Clean datapath event and queue/vec mapping */
3383 rte_intr_efd_disable(intr_handle);
3384 if (intr_handle->intr_vec) {
3385 rte_free(intr_handle->intr_vec);
3386 intr_handle->intr_vec = NULL;
3389 adapter->stopped = true;
3390 dev->data->dev_started = 0;
3396 igbvf_dev_close(struct rte_eth_dev *dev)
3398 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399 struct rte_ether_addr addr;
3400 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3403 PMD_INIT_FUNC_TRACE();
3405 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3410 ret = igbvf_dev_stop(dev);
3414 igb_dev_free_queues(dev);
3417 * reprogram the RAR with a zero mac address,
3418 * to ensure that the VF traffic goes to the PF
3419 * after stop, close and detach of the VF.
3422 memset(&addr, 0, sizeof(addr));
3423 igbvf_default_mac_addr_set(dev, &addr);
3425 rte_intr_callback_unregister(&pci_dev->intr_handle,
3426 eth_igbvf_interrupt_handler,
3433 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3435 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3437 /* Set both unicast and multicast promisc */
3438 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3444 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3446 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448 /* If in allmulticast mode leave multicast promisc */
3449 if (dev->data->all_multicast == 1)
3450 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3452 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3458 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3460 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462 /* In promiscuous mode multicast promisc already set */
3463 if (dev->data->promiscuous == 0)
3464 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3470 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3472 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3474 /* In promiscuous mode leave multicast promisc enabled */
3475 if (dev->data->promiscuous == 0)
3476 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3481 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3483 struct e1000_mbx_info *mbx = &hw->mbx;
3487 /* After set vlan, vlan strip will also be enabled in igb driver*/
3488 msgbuf[0] = E1000_VF_SET_VLAN;
3490 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3492 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3494 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3498 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3502 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3503 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3510 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3512 struct e1000_hw *hw =
3513 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514 struct e1000_vfta * shadow_vfta =
3515 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3516 int i = 0, j = 0, vfta = 0, mask = 1;
3518 for (i = 0; i < IGB_VFTA_SIZE; i++){
3519 vfta = shadow_vfta->vfta[i];
3522 for (j = 0; j < 32; j++){
3525 (uint16_t)((i<<5)+j), on);
3534 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3536 struct e1000_hw *hw =
3537 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3538 struct e1000_vfta * shadow_vfta =
3539 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3540 uint32_t vid_idx = 0;
3541 uint32_t vid_bit = 0;
3544 PMD_INIT_FUNC_TRACE();
3546 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3547 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3549 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3552 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3553 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3555 /*Save what we set and retore it after device reset*/
3557 shadow_vfta->vfta[vid_idx] |= vid_bit;
3559 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3565 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3567 struct e1000_hw *hw =
3568 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3570 /* index is not used by rar_set() */
3571 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3577 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3578 struct rte_eth_rss_reta_entry64 *reta_conf,
3583 uint16_t idx, shift;
3584 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3587 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3588 "(%d) doesn't match the number hardware can supported "
3589 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3593 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3594 idx = i / RTE_RETA_GROUP_SIZE;
3595 shift = i % RTE_RETA_GROUP_SIZE;
3596 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3600 if (mask == IGB_4_BIT_MASK)
3603 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3604 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3605 if (mask & (0x1 << j))
3606 reta |= reta_conf[idx].reta[shift + j] <<
3609 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3611 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3618 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3619 struct rte_eth_rss_reta_entry64 *reta_conf,
3624 uint16_t idx, shift;
3625 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3627 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3628 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3629 "(%d) doesn't match the number hardware can supported "
3630 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3634 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3635 idx = i / RTE_RETA_GROUP_SIZE;
3636 shift = i % RTE_RETA_GROUP_SIZE;
3637 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3641 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3642 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3643 if (mask & (0x1 << j))
3644 reta_conf[idx].reta[shift + j] =
3645 ((reta >> (CHAR_BIT * j)) &
3654 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3655 struct rte_eth_syn_filter *filter,
3658 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3659 struct e1000_filter_info *filter_info =
3660 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3661 uint32_t synqf, rfctl;
3663 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3666 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3669 if (synqf & E1000_SYN_FILTER_ENABLE)
3672 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3673 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3675 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3676 if (filter->hig_pri)
3677 rfctl |= E1000_RFCTL_SYNQFP;
3679 rfctl &= ~E1000_RFCTL_SYNQFP;
3681 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3683 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3688 filter_info->syn_info = synqf;
3689 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3690 E1000_WRITE_FLUSH(hw);
3694 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3696 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3697 struct e1000_2tuple_filter_info *filter_info)
3699 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3701 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3702 return -EINVAL; /* filter index is out of range. */
3703 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3704 return -EINVAL; /* flags is invalid. */
3706 switch (filter->dst_port_mask) {
3708 filter_info->dst_port_mask = 0;
3709 filter_info->dst_port = filter->dst_port;
3712 filter_info->dst_port_mask = 1;
3715 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3719 switch (filter->proto_mask) {
3721 filter_info->proto_mask = 0;
3722 filter_info->proto = filter->proto;
3725 filter_info->proto_mask = 1;
3728 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3732 filter_info->priority = (uint8_t)filter->priority;
3733 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3734 filter_info->tcp_flags = filter->tcp_flags;
3736 filter_info->tcp_flags = 0;
3741 static inline struct e1000_2tuple_filter *
3742 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3743 struct e1000_2tuple_filter_info *key)
3745 struct e1000_2tuple_filter *it;
3747 TAILQ_FOREACH(it, filter_list, entries) {
3748 if (memcmp(key, &it->filter_info,
3749 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3756 /* inject a igb 2tuple filter to HW */
3758 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3759 struct e1000_2tuple_filter *filter)
3761 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3762 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3763 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3767 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3768 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3769 imir |= E1000_IMIR_PORT_BP;
3771 imir &= ~E1000_IMIR_PORT_BP;
3773 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3775 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3776 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3777 ttqf |= (uint32_t)(filter->filter_info.proto &
3778 E1000_TTQF_PROTOCOL_MASK);
3779 if (filter->filter_info.proto_mask == 0)
3780 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3782 /* tcp flags bits setting. */
3783 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3784 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3785 imir_ext |= E1000_IMIREXT_CTRL_URG;
3786 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3787 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3788 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3789 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3790 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3791 imir_ext |= E1000_IMIREXT_CTRL_RST;
3792 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3793 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3794 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3795 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3797 imir_ext |= E1000_IMIREXT_CTRL_BP;
3799 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3800 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3801 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3805 * igb_add_2tuple_filter - add a 2tuple filter
3808 * dev: Pointer to struct rte_eth_dev.
3809 * ntuple_filter: ponter to the filter that will be added.
3812 * - On success, zero.
3813 * - On failure, a negative value.
3816 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3817 struct rte_eth_ntuple_filter *ntuple_filter)
3819 struct e1000_filter_info *filter_info =
3820 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3821 struct e1000_2tuple_filter *filter;
3824 filter = rte_zmalloc("e1000_2tuple_filter",
3825 sizeof(struct e1000_2tuple_filter), 0);
3829 ret = ntuple_filter_to_2tuple(ntuple_filter,
3830 &filter->filter_info);
3835 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3836 &filter->filter_info) != NULL) {
3837 PMD_DRV_LOG(ERR, "filter exists.");
3841 filter->queue = ntuple_filter->queue;
3844 * look for an unused 2tuple filter index,
3845 * and insert the filter to list.
3847 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3848 if (!(filter_info->twotuple_mask & (1 << i))) {
3849 filter_info->twotuple_mask |= 1 << i;
3851 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3857 if (i >= E1000_MAX_TTQF_FILTERS) {
3858 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3863 igb_inject_2uple_filter(dev, filter);
3868 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3869 struct e1000_2tuple_filter *filter)
3871 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3872 struct e1000_filter_info *filter_info =
3873 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3875 filter_info->twotuple_mask &= ~(1 << filter->index);
3876 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3879 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3880 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3881 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3886 * igb_remove_2tuple_filter - remove a 2tuple filter
3889 * dev: Pointer to struct rte_eth_dev.
3890 * ntuple_filter: ponter to the filter that will be removed.
3893 * - On success, zero.
3894 * - On failure, a negative value.
3897 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3898 struct rte_eth_ntuple_filter *ntuple_filter)
3900 struct e1000_filter_info *filter_info =
3901 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3902 struct e1000_2tuple_filter_info filter_2tuple;
3903 struct e1000_2tuple_filter *filter;
3906 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3907 ret = ntuple_filter_to_2tuple(ntuple_filter,
3912 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3914 if (filter == NULL) {
3915 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3919 igb_delete_2tuple_filter(dev, filter);
3924 /* inject a igb flex filter to HW */
3926 igb_inject_flex_filter(struct rte_eth_dev *dev,
3927 struct e1000_flex_filter *filter)
3929 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3930 uint32_t wufc, queueing;
3934 wufc = E1000_READ_REG(hw, E1000_WUFC);
3935 if (filter->index < E1000_MAX_FHFT)
3936 reg_off = E1000_FHFT(filter->index);
3938 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3940 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3941 (E1000_WUFC_FLX0 << filter->index));
3942 queueing = filter->filter_info.len |
3943 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3944 (filter->filter_info.priority <<
3945 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3946 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3949 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3950 E1000_WRITE_REG(hw, reg_off,
3951 filter->filter_info.dwords[j]);
3952 reg_off += sizeof(uint32_t);
3953 E1000_WRITE_REG(hw, reg_off,
3954 filter->filter_info.dwords[++j]);
3955 reg_off += sizeof(uint32_t);
3956 E1000_WRITE_REG(hw, reg_off,
3957 (uint32_t)filter->filter_info.mask[i]);
3958 reg_off += sizeof(uint32_t) * 2;
3963 static inline struct e1000_flex_filter *
3964 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3965 struct e1000_flex_filter_info *key)
3967 struct e1000_flex_filter *it;
3969 TAILQ_FOREACH(it, filter_list, entries) {
3970 if (memcmp(key, &it->filter_info,
3971 sizeof(struct e1000_flex_filter_info)) == 0)
3978 /* remove a flex byte filter
3980 * dev: Pointer to struct rte_eth_dev.
3981 * filter: the pointer of the filter will be removed.
3984 igb_remove_flex_filter(struct rte_eth_dev *dev,
3985 struct e1000_flex_filter *filter)
3987 struct e1000_filter_info *filter_info =
3988 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3989 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993 wufc = E1000_READ_REG(hw, E1000_WUFC);
3994 if (filter->index < E1000_MAX_FHFT)
3995 reg_off = E1000_FHFT(filter->index);
3997 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3999 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4000 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4002 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4003 (~(E1000_WUFC_FLX0 << filter->index)));
4005 filter_info->flex_mask &= ~(1 << filter->index);
4006 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4011 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4012 struct igb_flex_filter *filter,
4015 struct e1000_filter_info *filter_info =
4016 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4017 struct e1000_flex_filter *flex_filter, *it;
4021 flex_filter = rte_zmalloc("e1000_flex_filter",
4022 sizeof(struct e1000_flex_filter), 0);
4023 if (flex_filter == NULL)
4026 flex_filter->filter_info.len = filter->len;
4027 flex_filter->filter_info.priority = filter->priority;
4028 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4029 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4031 /* reverse bits in flex filter's mask*/
4032 for (shift = 0; shift < CHAR_BIT; shift++) {
4033 if (filter->mask[i] & (0x01 << shift))
4034 mask |= (0x80 >> shift);
4036 flex_filter->filter_info.mask[i] = mask;
4039 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4040 &flex_filter->filter_info);
4041 if (it == NULL && !add) {
4042 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4043 rte_free(flex_filter);
4046 if (it != NULL && add) {
4047 PMD_DRV_LOG(ERR, "filter exists.");
4048 rte_free(flex_filter);
4053 flex_filter->queue = filter->queue;
4055 * look for an unused flex filter index
4056 * and insert the filter into the list.
4058 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4059 if (!(filter_info->flex_mask & (1 << i))) {
4060 filter_info->flex_mask |= 1 << i;
4061 flex_filter->index = i;
4062 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4068 if (i >= E1000_MAX_FLEX_FILTERS) {
4069 PMD_DRV_LOG(ERR, "flex filters are full.");
4070 rte_free(flex_filter);
4074 igb_inject_flex_filter(dev, flex_filter);
4077 igb_remove_flex_filter(dev, it);
4078 rte_free(flex_filter);
4084 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4086 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4087 struct e1000_5tuple_filter_info *filter_info)
4089 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4091 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4092 return -EINVAL; /* filter index is out of range. */
4093 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4094 return -EINVAL; /* flags is invalid. */
4096 switch (filter->dst_ip_mask) {
4098 filter_info->dst_ip_mask = 0;
4099 filter_info->dst_ip = filter->dst_ip;
4102 filter_info->dst_ip_mask = 1;
4105 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4109 switch (filter->src_ip_mask) {
4111 filter_info->src_ip_mask = 0;
4112 filter_info->src_ip = filter->src_ip;
4115 filter_info->src_ip_mask = 1;
4118 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4122 switch (filter->dst_port_mask) {
4124 filter_info->dst_port_mask = 0;
4125 filter_info->dst_port = filter->dst_port;
4128 filter_info->dst_port_mask = 1;
4131 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4135 switch (filter->src_port_mask) {
4137 filter_info->src_port_mask = 0;
4138 filter_info->src_port = filter->src_port;
4141 filter_info->src_port_mask = 1;
4144 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4148 switch (filter->proto_mask) {
4150 filter_info->proto_mask = 0;
4151 filter_info->proto = filter->proto;
4154 filter_info->proto_mask = 1;
4157 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4161 filter_info->priority = (uint8_t)filter->priority;
4162 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4163 filter_info->tcp_flags = filter->tcp_flags;
4165 filter_info->tcp_flags = 0;
4170 static inline struct e1000_5tuple_filter *
4171 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4172 struct e1000_5tuple_filter_info *key)
4174 struct e1000_5tuple_filter *it;
4176 TAILQ_FOREACH(it, filter_list, entries) {
4177 if (memcmp(key, &it->filter_info,
4178 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4185 /* inject a igb 5-tuple filter to HW */
4187 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4188 struct e1000_5tuple_filter *filter)
4190 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4191 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4192 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4196 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4197 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4198 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4199 if (filter->filter_info.dst_ip_mask == 0)
4200 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4201 if (filter->filter_info.src_port_mask == 0)
4202 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4203 if (filter->filter_info.proto_mask == 0)
4204 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4205 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4206 E1000_FTQF_QUEUE_MASK;
4207 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4208 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4209 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4210 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4212 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4213 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4215 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4216 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4217 imir |= E1000_IMIR_PORT_BP;
4219 imir &= ~E1000_IMIR_PORT_BP;
4220 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4222 /* tcp flags bits setting. */
4223 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4224 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4225 imir_ext |= E1000_IMIREXT_CTRL_URG;
4226 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4227 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4228 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4229 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4230 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4231 imir_ext |= E1000_IMIREXT_CTRL_RST;
4232 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4233 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4234 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4235 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4237 imir_ext |= E1000_IMIREXT_CTRL_BP;
4239 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4240 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4244 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4247 * dev: Pointer to struct rte_eth_dev.
4248 * ntuple_filter: ponter to the filter that will be added.
4251 * - On success, zero.
4252 * - On failure, a negative value.
4255 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4256 struct rte_eth_ntuple_filter *ntuple_filter)
4258 struct e1000_filter_info *filter_info =
4259 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4260 struct e1000_5tuple_filter *filter;
4264 filter = rte_zmalloc("e1000_5tuple_filter",
4265 sizeof(struct e1000_5tuple_filter), 0);
4269 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4270 &filter->filter_info);
4276 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4277 &filter->filter_info) != NULL) {
4278 PMD_DRV_LOG(ERR, "filter exists.");
4282 filter->queue = ntuple_filter->queue;
4285 * look for an unused 5tuple filter index,
4286 * and insert the filter to list.
4288 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4289 if (!(filter_info->fivetuple_mask & (1 << i))) {
4290 filter_info->fivetuple_mask |= 1 << i;
4292 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4298 if (i >= E1000_MAX_FTQF_FILTERS) {
4299 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4304 igb_inject_5tuple_filter_82576(dev, filter);
4309 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4310 struct e1000_5tuple_filter *filter)
4312 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4313 struct e1000_filter_info *filter_info =
4314 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4316 filter_info->fivetuple_mask &= ~(1 << filter->index);
4317 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4320 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4321 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4322 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4323 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4324 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4325 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4326 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4331 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4334 * dev: Pointer to struct rte_eth_dev.
4335 * ntuple_filter: ponter to the filter that will be removed.
4338 * - On success, zero.
4339 * - On failure, a negative value.
4342 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4343 struct rte_eth_ntuple_filter *ntuple_filter)
4345 struct e1000_filter_info *filter_info =
4346 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4347 struct e1000_5tuple_filter_info filter_5tuple;
4348 struct e1000_5tuple_filter *filter;
4351 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4352 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4357 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4359 if (filter == NULL) {
4360 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4364 igb_delete_5tuple_filter_82576(dev, filter);
4370 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4373 struct e1000_hw *hw;
4374 struct rte_eth_dev_info dev_info;
4375 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4378 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4380 #ifdef RTE_LIBRTE_82571_SUPPORT
4381 /* XXX: not bigger than max_rx_pktlen */
4382 if (hw->mac.type == e1000_82571)
4385 ret = eth_igb_infos_get(dev, &dev_info);
4389 /* check that mtu is within the allowed range */
4390 if (mtu < RTE_ETHER_MIN_MTU ||
4391 frame_size > dev_info.max_rx_pktlen)
4395 * If device is started, refuse mtu that requires the support of
4396 * scattered packets when this feature has not been enabled before.
4398 if (dev->data->dev_started && !dev->data->scattered_rx &&
4399 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
4400 PMD_INIT_LOG(ERR, "Stop port first.");
4404 rctl = E1000_READ_REG(hw, E1000_RCTL);
4406 /* switch to jumbo mode if needed */
4407 if (frame_size > E1000_ETH_MAX_LEN) {
4408 dev->data->dev_conf.rxmode.offloads |=
4409 DEV_RX_OFFLOAD_JUMBO_FRAME;
4410 rctl |= E1000_RCTL_LPE;
4412 dev->data->dev_conf.rxmode.offloads &=
4413 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4414 rctl &= ~E1000_RCTL_LPE;
4416 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4418 /* update max frame size */
4419 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4421 E1000_WRITE_REG(hw, E1000_RLPML,
4422 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4428 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4431 * dev: Pointer to struct rte_eth_dev.
4432 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4433 * add: if true, add filter, if false, remove filter
4436 * - On success, zero.
4437 * - On failure, a negative value.
4440 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4441 struct rte_eth_ntuple_filter *ntuple_filter,
4444 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447 switch (ntuple_filter->flags) {
4448 case RTE_5TUPLE_FLAGS:
4449 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4450 if (hw->mac.type != e1000_82576)
4453 ret = igb_add_5tuple_filter_82576(dev,
4456 ret = igb_remove_5tuple_filter_82576(dev,
4459 case RTE_2TUPLE_FLAGS:
4460 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4461 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4462 hw->mac.type != e1000_i210 &&
4463 hw->mac.type != e1000_i211)
4466 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4468 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4479 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4484 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4485 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4486 (filter_info->ethertype_mask & (1 << i)))
4493 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4494 uint16_t ethertype, uint32_t etqf)
4498 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4499 if (!(filter_info->ethertype_mask & (1 << i))) {
4500 filter_info->ethertype_mask |= 1 << i;
4501 filter_info->ethertype_filters[i].ethertype = ethertype;
4502 filter_info->ethertype_filters[i].etqf = etqf;
4510 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4513 if (idx >= E1000_MAX_ETQF_FILTERS)
4515 filter_info->ethertype_mask &= ~(1 << idx);
4516 filter_info->ethertype_filters[idx].ethertype = 0;
4517 filter_info->ethertype_filters[idx].etqf = 0;
4523 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4524 struct rte_eth_ethertype_filter *filter,
4527 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4528 struct e1000_filter_info *filter_info =
4529 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4533 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4534 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4535 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4536 " ethertype filter.", filter->ether_type);
4540 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4541 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4544 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4545 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4549 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4550 if (ret >= 0 && add) {
4551 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4552 filter->ether_type);
4555 if (ret < 0 && !add) {
4556 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4557 filter->ether_type);
4562 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4563 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4564 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4565 ret = igb_ethertype_filter_insert(filter_info,
4566 filter->ether_type, etqf);
4568 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4572 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4576 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4577 E1000_WRITE_FLUSH(hw);
4583 eth_igb_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
4584 const struct rte_flow_ops **ops)
4586 *ops = &igb_flow_ops;
4591 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4592 struct rte_ether_addr *mc_addr_set,
4593 uint32_t nb_mc_addr)
4595 struct e1000_hw *hw;
4597 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4598 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4603 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4605 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4606 uint64_t systime_cycles;
4608 switch (hw->mac.type) {
4612 * Need to read System Time Residue Register to be able
4613 * to read the other two registers.
4615 E1000_READ_REG(hw, E1000_SYSTIMR);
4616 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4617 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4618 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4625 * Need to read System Time Residue Register to be able
4626 * to read the other two registers.
4628 E1000_READ_REG(hw, E1000_SYSTIMR);
4629 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4630 /* Only the 8 LSB are valid. */
4631 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4635 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4636 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4641 return systime_cycles;
4645 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4647 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4648 uint64_t rx_tstamp_cycles;
4650 switch (hw->mac.type) {
4653 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4654 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4655 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4661 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4662 /* Only the 8 LSB are valid. */
4663 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4667 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4668 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4673 return rx_tstamp_cycles;
4677 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4679 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4680 uint64_t tx_tstamp_cycles;
4682 switch (hw->mac.type) {
4685 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4686 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4687 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4693 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4694 /* Only the 8 LSB are valid. */
4695 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4699 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4700 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4705 return tx_tstamp_cycles;
4709 igb_start_timecounters(struct rte_eth_dev *dev)
4711 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4712 struct e1000_adapter *adapter = dev->data->dev_private;
4713 uint32_t incval = 1;
4715 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4717 switch (hw->mac.type) {
4721 /* 32 LSB bits + 8 MSB bits = 40 bits */
4722 mask = (1ULL << 40) - 1;
4727 * Start incrementing the register
4728 * used to timestamp PTP packets.
4730 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4733 incval = E1000_INCVALUE_82576;
4734 shift = IGB_82576_TSYNC_SHIFT;
4735 E1000_WRITE_REG(hw, E1000_TIMINCA,
4736 E1000_INCPERIOD_82576 | incval);
4743 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4744 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4745 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4747 adapter->systime_tc.cc_mask = mask;
4748 adapter->systime_tc.cc_shift = shift;
4749 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4751 adapter->rx_tstamp_tc.cc_mask = mask;
4752 adapter->rx_tstamp_tc.cc_shift = shift;
4753 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4755 adapter->tx_tstamp_tc.cc_mask = mask;
4756 adapter->tx_tstamp_tc.cc_shift = shift;
4757 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4761 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4763 struct e1000_adapter *adapter = dev->data->dev_private;
4765 adapter->systime_tc.nsec += delta;
4766 adapter->rx_tstamp_tc.nsec += delta;
4767 adapter->tx_tstamp_tc.nsec += delta;
4773 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4776 struct e1000_adapter *adapter = dev->data->dev_private;
4778 ns = rte_timespec_to_ns(ts);
4780 /* Set the timecounters to a new value. */
4781 adapter->systime_tc.nsec = ns;
4782 adapter->rx_tstamp_tc.nsec = ns;
4783 adapter->tx_tstamp_tc.nsec = ns;
4789 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4791 uint64_t ns, systime_cycles;
4792 struct e1000_adapter *adapter = dev->data->dev_private;
4794 systime_cycles = igb_read_systime_cyclecounter(dev);
4795 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4796 *ts = rte_ns_to_timespec(ns);
4802 igb_timesync_enable(struct rte_eth_dev *dev)
4804 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4808 /* Stop the timesync system time. */
4809 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4810 /* Reset the timesync system time value. */
4811 switch (hw->mac.type) {
4817 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4820 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4821 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4824 /* Not supported. */
4828 /* Enable system time for it isn't on by default. */
4829 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4830 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4831 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4833 igb_start_timecounters(dev);
4835 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4836 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4837 (RTE_ETHER_TYPE_1588 |
4838 E1000_ETQF_FILTER_ENABLE |
4841 /* Enable timestamping of received PTP packets. */
4842 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4843 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4844 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4846 /* Enable Timestamping of transmitted PTP packets. */
4847 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4848 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4849 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4855 igb_timesync_disable(struct rte_eth_dev *dev)
4857 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860 /* Disable timestamping of transmitted PTP packets. */
4861 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4862 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4863 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4865 /* Disable timestamping of received PTP packets. */
4866 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4867 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4868 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4870 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4871 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4873 /* Stop incrementating the System Time registers. */
4874 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4880 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4881 struct timespec *timestamp,
4882 uint32_t flags __rte_unused)
4884 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4885 struct e1000_adapter *adapter = dev->data->dev_private;
4886 uint32_t tsync_rxctl;
4887 uint64_t rx_tstamp_cycles;
4890 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4891 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4894 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4895 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4896 *timestamp = rte_ns_to_timespec(ns);
4902 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4903 struct timespec *timestamp)
4905 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906 struct e1000_adapter *adapter = dev->data->dev_private;
4907 uint32_t tsync_txctl;
4908 uint64_t tx_tstamp_cycles;
4911 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4912 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4915 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4916 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4917 *timestamp = rte_ns_to_timespec(ns);
4923 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4927 const struct reg_info *reg_group;
4929 while ((reg_group = igb_regs[g_ind++]))
4930 count += igb_reg_group_count(reg_group);
4936 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4940 const struct reg_info *reg_group;
4942 while ((reg_group = igbvf_regs[g_ind++]))
4943 count += igb_reg_group_count(reg_group);
4949 eth_igb_get_regs(struct rte_eth_dev *dev,
4950 struct rte_dev_reg_info *regs)
4952 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4953 uint32_t *data = regs->data;
4956 const struct reg_info *reg_group;
4959 regs->length = eth_igb_get_reg_length(dev);
4960 regs->width = sizeof(uint32_t);
4964 /* Support only full register dump */
4965 if ((regs->length == 0) ||
4966 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4967 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4969 while ((reg_group = igb_regs[g_ind++]))
4970 count += igb_read_regs_group(dev, &data[count],
4979 igbvf_get_regs(struct rte_eth_dev *dev,
4980 struct rte_dev_reg_info *regs)
4982 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4983 uint32_t *data = regs->data;
4986 const struct reg_info *reg_group;
4989 regs->length = igbvf_get_reg_length(dev);
4990 regs->width = sizeof(uint32_t);
4994 /* Support only full register dump */
4995 if ((regs->length == 0) ||
4996 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4997 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4999 while ((reg_group = igbvf_regs[g_ind++]))
5000 count += igb_read_regs_group(dev, &data[count],
5009 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5011 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5013 /* Return unit is byte count */
5014 return hw->nvm.word_size * 2;
5018 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5019 struct rte_dev_eeprom_info *in_eeprom)
5021 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5022 struct e1000_nvm_info *nvm = &hw->nvm;
5023 uint16_t *data = in_eeprom->data;
5026 first = in_eeprom->offset >> 1;
5027 length = in_eeprom->length >> 1;
5028 if ((first >= hw->nvm.word_size) ||
5029 ((first + length) >= hw->nvm.word_size))
5032 in_eeprom->magic = hw->vendor_id |
5033 ((uint32_t)hw->device_id << 16);
5035 if ((nvm->ops.read) == NULL)
5038 return nvm->ops.read(hw, first, length, data);
5042 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5043 struct rte_dev_eeprom_info *in_eeprom)
5045 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046 struct e1000_nvm_info *nvm = &hw->nvm;
5047 uint16_t *data = in_eeprom->data;
5050 first = in_eeprom->offset >> 1;
5051 length = in_eeprom->length >> 1;
5052 if ((first >= hw->nvm.word_size) ||
5053 ((first + length) >= hw->nvm.word_size))
5056 in_eeprom->magic = (uint32_t)hw->vendor_id |
5057 ((uint32_t)hw->device_id << 16);
5059 if ((nvm->ops.write) == NULL)
5061 return nvm->ops.write(hw, first, length, data);
5065 eth_igb_get_module_info(struct rte_eth_dev *dev,
5066 struct rte_eth_dev_module_info *modinfo)
5068 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5070 uint32_t status = 0;
5071 uint16_t sff8472_rev, addr_mode;
5072 bool page_swap = false;
5074 if (hw->phy.media_type == e1000_media_type_copper ||
5075 hw->phy.media_type == e1000_media_type_unknown)
5078 /* Check whether we support SFF-8472 or not */
5079 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5083 /* addressing mode is not supported */
5084 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5088 /* addressing mode is not supported */
5089 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5091 "Address change required to access page 0xA2, "
5092 "but not supported. Please report the module "
5093 "type to the driver maintainers.\n");
5097 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5098 /* We have an SFP, but it does not support SFF-8472 */
5099 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5100 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5102 /* We have an SFP which supports a revision of SFF-8472 */
5103 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5104 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5111 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5112 struct rte_dev_eeprom_info *info)
5114 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116 uint32_t status = 0;
5117 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5118 u16 first_word, last_word;
5121 first_word = info->offset >> 1;
5122 last_word = (info->offset + info->length - 1) >> 1;
5124 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5125 for (i = 0; i < last_word - first_word + 1; i++) {
5126 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5129 /* Error occurred while reading module */
5133 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5136 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5142 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5144 struct e1000_hw *hw =
5145 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5146 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5147 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5148 uint32_t vec = E1000_MISC_VEC_ID;
5150 if (rte_intr_allow_others(intr_handle))
5151 vec = E1000_RX_VEC_START;
5153 uint32_t mask = 1 << (queue_id + vec);
5155 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5156 E1000_WRITE_FLUSH(hw);
5162 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5164 struct e1000_hw *hw =
5165 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5167 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5168 uint32_t vec = E1000_MISC_VEC_ID;
5170 if (rte_intr_allow_others(intr_handle))
5171 vec = E1000_RX_VEC_START;
5173 uint32_t mask = 1 << (queue_id + vec);
5176 regval = E1000_READ_REG(hw, E1000_EIMS);
5177 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5178 E1000_WRITE_FLUSH(hw);
5180 rte_intr_ack(intr_handle);
5186 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5187 uint8_t index, uint8_t offset)
5189 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5192 val &= ~((uint32_t)0xFF << offset);
5194 /* write vector and valid bit */
5195 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5197 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5201 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5202 uint8_t queue, uint8_t msix_vector)
5206 if (hw->mac.type == e1000_82575) {
5208 tmp = E1000_EICR_RX_QUEUE0 << queue;
5209 else if (direction == 1)
5210 tmp = E1000_EICR_TX_QUEUE0 << queue;
5211 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5212 } else if (hw->mac.type == e1000_82576) {
5213 if ((direction == 0) || (direction == 1))
5214 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5215 ((queue & 0x8) << 1) +
5217 } else if ((hw->mac.type == e1000_82580) ||
5218 (hw->mac.type == e1000_i350) ||
5219 (hw->mac.type == e1000_i354) ||
5220 (hw->mac.type == e1000_i210) ||
5221 (hw->mac.type == e1000_i211)) {
5222 if ((direction == 0) || (direction == 1))
5223 eth_igb_write_ivar(hw, msix_vector,
5225 ((queue & 0x1) << 4) +
5230 /* Sets up the hardware to generate MSI-X interrupts properly
5232 * board private structure
5235 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5238 uint32_t tmpval, regval, intr_mask;
5239 struct e1000_hw *hw =
5240 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5241 uint32_t vec = E1000_MISC_VEC_ID;
5242 uint32_t base = E1000_MISC_VEC_ID;
5243 uint32_t misc_shift = 0;
5244 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5245 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5247 /* won't configure msix register if no mapping is done
5248 * between intr vector and event fd
5250 if (!rte_intr_dp_is_en(intr_handle))
5253 if (rte_intr_allow_others(intr_handle)) {
5254 vec = base = E1000_RX_VEC_START;
5258 /* set interrupt vector for other causes */
5259 if (hw->mac.type == e1000_82575) {
5260 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5261 /* enable MSI-X PBA support */
5262 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5264 /* Auto-Mask interrupts upon ICR read */
5265 tmpval |= E1000_CTRL_EXT_EIAME;
5266 tmpval |= E1000_CTRL_EXT_IRCA;
5268 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5270 /* enable msix_other interrupt */
5271 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5272 regval = E1000_READ_REG(hw, E1000_EIAC);
5273 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5274 regval = E1000_READ_REG(hw, E1000_EIAM);
5275 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5276 } else if ((hw->mac.type == e1000_82576) ||
5277 (hw->mac.type == e1000_82580) ||
5278 (hw->mac.type == e1000_i350) ||
5279 (hw->mac.type == e1000_i354) ||
5280 (hw->mac.type == e1000_i210) ||
5281 (hw->mac.type == e1000_i211)) {
5282 /* turn on MSI-X capability first */
5283 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5284 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5286 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5289 if (dev->data->dev_conf.intr_conf.lsc != 0)
5290 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5292 regval = E1000_READ_REG(hw, E1000_EIAC);
5293 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5295 /* enable msix_other interrupt */
5296 regval = E1000_READ_REG(hw, E1000_EIMS);
5297 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5298 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5299 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5302 /* use EIAM to auto-mask when MSI-X interrupt
5303 * is asserted, this saves a register write for every interrupt
5305 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5308 if (dev->data->dev_conf.intr_conf.lsc != 0)
5309 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5311 regval = E1000_READ_REG(hw, E1000_EIAM);
5312 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5314 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5315 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5316 intr_handle->intr_vec[queue_id] = vec;
5317 if (vec < base + intr_handle->nb_efd - 1)
5321 E1000_WRITE_FLUSH(hw);
5324 /* restore n-tuple filter */
5326 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5328 struct e1000_filter_info *filter_info =
5329 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5330 struct e1000_5tuple_filter *p_5tuple;
5331 struct e1000_2tuple_filter *p_2tuple;
5333 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5334 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5337 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5338 igb_inject_2uple_filter(dev, p_2tuple);
5342 /* restore SYN filter */
5344 igb_syn_filter_restore(struct rte_eth_dev *dev)
5346 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5347 struct e1000_filter_info *filter_info =
5348 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5351 synqf = filter_info->syn_info;
5353 if (synqf & E1000_SYN_FILTER_ENABLE) {
5354 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5355 E1000_WRITE_FLUSH(hw);
5359 /* restore ethernet type filter */
5361 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5363 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5364 struct e1000_filter_info *filter_info =
5365 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5368 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5369 if (filter_info->ethertype_mask & (1 << i)) {
5370 E1000_WRITE_REG(hw, E1000_ETQF(i),
5371 filter_info->ethertype_filters[i].etqf);
5372 E1000_WRITE_FLUSH(hw);
5377 /* restore flex byte filter */
5379 igb_flex_filter_restore(struct rte_eth_dev *dev)
5381 struct e1000_filter_info *filter_info =
5382 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5383 struct e1000_flex_filter *flex_filter;
5385 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5386 igb_inject_flex_filter(dev, flex_filter);
5390 /* restore rss filter */
5392 igb_rss_filter_restore(struct rte_eth_dev *dev)
5394 struct e1000_filter_info *filter_info =
5395 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5397 if (filter_info->rss_info.conf.queue_num)
5398 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5401 /* restore all types filter */
5403 igb_filter_restore(struct rte_eth_dev *dev)
5405 igb_ntuple_filter_restore(dev);
5406 igb_ethertype_filter_restore(dev);
5407 igb_syn_filter_restore(dev);
5408 igb_flex_filter_restore(dev);
5409 igb_rss_filter_restore(dev);
5414 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5415 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5416 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5417 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5418 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5419 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");