1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static int eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static int eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
158 static int igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
190 struct rte_eth_syn_filter *filter);
191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
192 enum rte_filter_op filter_op,
194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
197 struct rte_eth_ntuple_filter *ntuple_filter);
198 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
199 struct rte_eth_ntuple_filter *ntuple_filter);
200 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
201 struct rte_eth_ntuple_filter *ntuple_filter);
202 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
203 struct rte_eth_ntuple_filter *filter);
204 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
205 enum rte_filter_op filter_op,
207 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
208 enum rte_filter_type filter_type,
209 enum rte_filter_op filter_op,
211 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
212 static int eth_igb_get_regs(struct rte_eth_dev *dev,
213 struct rte_dev_reg_info *regs);
214 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
215 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
216 struct rte_dev_eeprom_info *eeprom);
217 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
218 struct rte_dev_eeprom_info *eeprom);
219 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
220 struct rte_eth_dev_module_info *modinfo);
221 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
222 struct rte_dev_eeprom_info *info);
223 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
224 struct rte_ether_addr *mc_addr_set,
225 uint32_t nb_mc_addr);
226 static int igb_timesync_enable(struct rte_eth_dev *dev);
227 static int igb_timesync_disable(struct rte_eth_dev *dev);
228 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
229 struct timespec *timestamp,
231 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
232 struct timespec *timestamp);
233 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
234 static int igb_timesync_read_time(struct rte_eth_dev *dev,
235 struct timespec *timestamp);
236 static int igb_timesync_write_time(struct rte_eth_dev *dev,
237 const struct timespec *timestamp);
238 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
240 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
242 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
243 uint8_t queue, uint8_t msix_vector);
244 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
245 uint8_t index, uint8_t offset);
246 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
247 static void eth_igbvf_interrupt_handler(void *param);
248 static void igbvf_mbx_process(struct rte_eth_dev *dev);
249 static int igb_filter_restore(struct rte_eth_dev *dev);
252 * Define VF Stats MACRO for Non "cleared on read" register
254 #define UPDATE_VF_STAT(reg, last, cur) \
256 u32 latest = E1000_READ_REG(hw, reg); \
257 cur += (latest - last) & UINT_MAX; \
261 #define IGB_FC_PAUSE_TIME 0x0680
262 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
263 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
265 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
267 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
270 * The set of PCI devices this driver supports
272 static const struct rte_pci_id pci_id_igb_map[] = {
273 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
274 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
275 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
276 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
280 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
302 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
314 { .vendor_id = 0, /* sentinel */ },
318 * The set of PCI devices this driver supports (for 82576&I350 VF)
320 static const struct rte_pci_id pci_id_igbvf_map[] = {
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
325 { .vendor_id = 0, /* sentinel */ },
328 static const struct rte_eth_desc_lim rx_desc_lim = {
329 .nb_max = E1000_MAX_RING_DESC,
330 .nb_min = E1000_MIN_RING_DESC,
331 .nb_align = IGB_RXD_ALIGN,
334 static const struct rte_eth_desc_lim tx_desc_lim = {
335 .nb_max = E1000_MAX_RING_DESC,
336 .nb_min = E1000_MIN_RING_DESC,
337 .nb_align = IGB_RXD_ALIGN,
338 .nb_seg_max = IGB_TX_MAX_SEG,
339 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
342 static const struct eth_dev_ops eth_igb_ops = {
343 .dev_configure = eth_igb_configure,
344 .dev_start = eth_igb_start,
345 .dev_stop = eth_igb_stop,
346 .dev_set_link_up = eth_igb_dev_set_link_up,
347 .dev_set_link_down = eth_igb_dev_set_link_down,
348 .dev_close = eth_igb_close,
349 .dev_reset = eth_igb_reset,
350 .promiscuous_enable = eth_igb_promiscuous_enable,
351 .promiscuous_disable = eth_igb_promiscuous_disable,
352 .allmulticast_enable = eth_igb_allmulticast_enable,
353 .allmulticast_disable = eth_igb_allmulticast_disable,
354 .link_update = eth_igb_link_update,
355 .stats_get = eth_igb_stats_get,
356 .xstats_get = eth_igb_xstats_get,
357 .xstats_get_by_id = eth_igb_xstats_get_by_id,
358 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
359 .xstats_get_names = eth_igb_xstats_get_names,
360 .stats_reset = eth_igb_stats_reset,
361 .xstats_reset = eth_igb_xstats_reset,
362 .fw_version_get = eth_igb_fw_version_get,
363 .dev_infos_get = eth_igb_infos_get,
364 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
365 .mtu_set = eth_igb_mtu_set,
366 .vlan_filter_set = eth_igb_vlan_filter_set,
367 .vlan_tpid_set = eth_igb_vlan_tpid_set,
368 .vlan_offload_set = eth_igb_vlan_offload_set,
369 .rx_queue_setup = eth_igb_rx_queue_setup,
370 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
371 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
372 .rx_queue_release = eth_igb_rx_queue_release,
373 .tx_queue_setup = eth_igb_tx_queue_setup,
374 .tx_queue_release = eth_igb_tx_queue_release,
375 .tx_done_cleanup = eth_igb_tx_done_cleanup,
376 .dev_led_on = eth_igb_led_on,
377 .dev_led_off = eth_igb_led_off,
378 .flow_ctrl_get = eth_igb_flow_ctrl_get,
379 .flow_ctrl_set = eth_igb_flow_ctrl_set,
380 .mac_addr_add = eth_igb_rar_set,
381 .mac_addr_remove = eth_igb_rar_clear,
382 .mac_addr_set = eth_igb_default_mac_addr_set,
383 .reta_update = eth_igb_rss_reta_update,
384 .reta_query = eth_igb_rss_reta_query,
385 .rss_hash_update = eth_igb_rss_hash_update,
386 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
387 .filter_ctrl = eth_igb_filter_ctrl,
388 .set_mc_addr_list = eth_igb_set_mc_addr_list,
389 .rxq_info_get = igb_rxq_info_get,
390 .txq_info_get = igb_txq_info_get,
391 .timesync_enable = igb_timesync_enable,
392 .timesync_disable = igb_timesync_disable,
393 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
394 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
395 .get_reg = eth_igb_get_regs,
396 .get_eeprom_length = eth_igb_get_eeprom_length,
397 .get_eeprom = eth_igb_get_eeprom,
398 .set_eeprom = eth_igb_set_eeprom,
399 .get_module_info = eth_igb_get_module_info,
400 .get_module_eeprom = eth_igb_get_module_eeprom,
401 .timesync_adjust_time = igb_timesync_adjust_time,
402 .timesync_read_time = igb_timesync_read_time,
403 .timesync_write_time = igb_timesync_write_time,
407 * dev_ops for virtual function, bare necessities for basic vf
408 * operation have been implemented
410 static const struct eth_dev_ops igbvf_eth_dev_ops = {
411 .dev_configure = igbvf_dev_configure,
412 .dev_start = igbvf_dev_start,
413 .dev_stop = igbvf_dev_stop,
414 .dev_close = igbvf_dev_close,
415 .promiscuous_enable = igbvf_promiscuous_enable,
416 .promiscuous_disable = igbvf_promiscuous_disable,
417 .allmulticast_enable = igbvf_allmulticast_enable,
418 .allmulticast_disable = igbvf_allmulticast_disable,
419 .link_update = eth_igb_link_update,
420 .stats_get = eth_igbvf_stats_get,
421 .xstats_get = eth_igbvf_xstats_get,
422 .xstats_get_names = eth_igbvf_xstats_get_names,
423 .stats_reset = eth_igbvf_stats_reset,
424 .xstats_reset = eth_igbvf_stats_reset,
425 .vlan_filter_set = igbvf_vlan_filter_set,
426 .dev_infos_get = eth_igbvf_infos_get,
427 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
428 .rx_queue_setup = eth_igb_rx_queue_setup,
429 .rx_queue_release = eth_igb_rx_queue_release,
430 .tx_queue_setup = eth_igb_tx_queue_setup,
431 .tx_queue_release = eth_igb_tx_queue_release,
432 .tx_done_cleanup = eth_igb_tx_done_cleanup,
433 .set_mc_addr_list = eth_igb_set_mc_addr_list,
434 .rxq_info_get = igb_rxq_info_get,
435 .txq_info_get = igb_txq_info_get,
436 .mac_addr_set = igbvf_default_mac_addr_set,
437 .get_reg = igbvf_get_regs,
440 /* store statistics names and its offset in stats structure */
441 struct rte_igb_xstats_name_off {
442 char name[RTE_ETH_XSTATS_NAME_SIZE];
446 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
447 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
448 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
449 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
450 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
451 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
452 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
453 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
455 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
456 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
457 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
458 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
459 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
460 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
461 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
462 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
463 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
464 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
465 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
467 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
468 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
469 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
470 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
471 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
473 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
475 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
476 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
477 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
478 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
479 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
480 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
481 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
482 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
483 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
484 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
485 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
486 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
487 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
488 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
489 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
490 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
491 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
492 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
494 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
496 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
497 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
498 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
499 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
500 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
501 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
502 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
504 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
507 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
508 sizeof(rte_igb_stats_strings[0]))
510 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
511 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
512 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
513 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
514 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
515 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
518 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
519 sizeof(rte_igbvf_stats_strings[0]))
523 igb_intr_enable(struct rte_eth_dev *dev)
525 struct e1000_interrupt *intr =
526 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
527 struct e1000_hw *hw =
528 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
529 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
530 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
532 if (rte_intr_allow_others(intr_handle) &&
533 dev->data->dev_conf.intr_conf.lsc != 0) {
534 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
537 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
538 E1000_WRITE_FLUSH(hw);
542 igb_intr_disable(struct rte_eth_dev *dev)
544 struct e1000_hw *hw =
545 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
546 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
547 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
549 if (rte_intr_allow_others(intr_handle) &&
550 dev->data->dev_conf.intr_conf.lsc != 0) {
551 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
554 E1000_WRITE_REG(hw, E1000_IMC, ~0);
555 E1000_WRITE_FLUSH(hw);
559 igbvf_intr_enable(struct rte_eth_dev *dev)
561 struct e1000_hw *hw =
562 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
564 /* only for mailbox */
565 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
566 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
567 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
568 E1000_WRITE_FLUSH(hw);
571 /* only for mailbox now. If RX/TX needed, should extend this function. */
573 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
578 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
579 tmp |= E1000_VTIVAR_VALID;
580 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
584 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
586 struct e1000_hw *hw =
587 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
589 /* Configure VF other cause ivar */
590 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
593 static inline int32_t
594 igb_pf_reset_hw(struct e1000_hw *hw)
599 status = e1000_reset_hw(hw);
601 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
602 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
603 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
604 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
605 E1000_WRITE_FLUSH(hw);
611 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
613 struct e1000_hw *hw =
614 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
617 hw->vendor_id = pci_dev->id.vendor_id;
618 hw->device_id = pci_dev->id.device_id;
619 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
620 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
622 e1000_set_mac_type(hw);
624 /* need to check if it is a vf device below */
628 igb_reset_swfw_lock(struct e1000_hw *hw)
633 * Do mac ops initialization manually here, since we will need
634 * some function pointers set by this call.
636 ret_val = e1000_init_mac_params(hw);
641 * SMBI lock should not fail in this early stage. If this is the case,
642 * it is due to an improper exit of the application.
643 * So force the release of the faulty lock.
645 if (e1000_get_hw_semaphore_generic(hw) < 0) {
646 PMD_DRV_LOG(DEBUG, "SMBI lock released");
648 e1000_put_hw_semaphore_generic(hw);
650 if (hw->mac.ops.acquire_swfw_sync != NULL) {
654 * Phy lock should not fail in this early stage. If this is the case,
655 * it is due to an improper exit of the application.
656 * So force the release of the faulty lock.
658 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
659 if (hw->bus.func > E1000_FUNC_1)
661 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
662 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
665 hw->mac.ops.release_swfw_sync(hw, mask);
668 * This one is more tricky since it is common to all ports; but
669 * swfw_sync retries last long enough (1s) to be almost sure that if
670 * lock can not be taken it is due to an improper lock of the
673 mask = E1000_SWFW_EEP_SM;
674 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
675 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
677 hw->mac.ops.release_swfw_sync(hw, mask);
680 return E1000_SUCCESS;
683 /* Remove all ntuple filters of the device */
684 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
686 struct e1000_filter_info *filter_info =
687 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
688 struct e1000_5tuple_filter *p_5tuple;
689 struct e1000_2tuple_filter *p_2tuple;
691 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
692 TAILQ_REMOVE(&filter_info->fivetuple_list,
696 filter_info->fivetuple_mask = 0;
697 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
698 TAILQ_REMOVE(&filter_info->twotuple_list,
702 filter_info->twotuple_mask = 0;
707 /* Remove all flex filters of the device */
708 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
710 struct e1000_filter_info *filter_info =
711 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
712 struct e1000_flex_filter *p_flex;
714 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
715 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
718 filter_info->flex_mask = 0;
724 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
727 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
728 struct e1000_hw *hw =
729 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
730 struct e1000_vfta * shadow_vfta =
731 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
732 struct e1000_filter_info *filter_info =
733 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
734 struct e1000_adapter *adapter =
735 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
739 eth_dev->dev_ops = ð_igb_ops;
740 eth_dev->rx_queue_count = eth_igb_rx_queue_count;
741 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
742 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
743 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
744 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
745 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
746 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
748 /* for secondary processes, we don't initialise any further as primary
749 * has already done this work. Only check we don't need a different
751 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
752 if (eth_dev->data->scattered_rx)
753 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
757 rte_eth_copy_pci_info(eth_dev, pci_dev);
758 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
760 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
762 igb_identify_hardware(eth_dev, pci_dev);
763 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
768 e1000_get_bus_info(hw);
770 /* Reset any pending lock */
771 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
776 /* Finish initialization */
777 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
783 hw->phy.autoneg_wait_to_complete = 0;
784 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
787 if (hw->phy.media_type == e1000_media_type_copper) {
788 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
789 hw->phy.disable_polarity_correction = 0;
790 hw->phy.ms_type = e1000_ms_hw_default;
794 * Start from a known state, this is important in reading the nvm
799 /* Make sure we have a good EEPROM before we read from it */
800 if (e1000_validate_nvm_checksum(hw) < 0) {
802 * Some PCI-E parts fail the first check due to
803 * the link being in sleep state, call it again,
804 * if it fails a second time its a real issue.
806 if (e1000_validate_nvm_checksum(hw) < 0) {
807 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
813 /* Read the permanent MAC address out of the EEPROM */
814 if (e1000_read_mac_addr(hw) != 0) {
815 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
820 /* Allocate memory for storing MAC addresses */
821 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
822 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
823 if (eth_dev->data->mac_addrs == NULL) {
824 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
825 "store MAC addresses",
826 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
831 /* Copy the permanent MAC address */
832 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
833 ð_dev->data->mac_addrs[0]);
835 /* initialize the vfta */
836 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
838 /* Now initialize the hardware */
839 if (igb_hardware_init(hw) != 0) {
840 PMD_INIT_LOG(ERR, "Hardware initialization failed");
841 rte_free(eth_dev->data->mac_addrs);
842 eth_dev->data->mac_addrs = NULL;
846 hw->mac.get_link_status = 1;
847 adapter->stopped = 0;
849 /* Indicate SOL/IDER usage */
850 if (e1000_check_reset_block(hw) < 0) {
851 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
855 /* initialize PF if max_vfs not zero */
856 igb_pf_host_init(eth_dev);
858 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
859 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
860 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
861 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
862 E1000_WRITE_FLUSH(hw);
864 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
865 eth_dev->data->port_id, pci_dev->id.vendor_id,
866 pci_dev->id.device_id);
868 rte_intr_callback_register(&pci_dev->intr_handle,
869 eth_igb_interrupt_handler,
872 /* enable uio/vfio intr/eventfd mapping */
873 rte_intr_enable(&pci_dev->intr_handle);
875 /* enable support intr */
876 igb_intr_enable(eth_dev);
878 eth_igb_dev_set_link_down(eth_dev);
880 /* initialize filter info */
881 memset(filter_info, 0,
882 sizeof(struct e1000_filter_info));
884 TAILQ_INIT(&filter_info->flex_list);
885 TAILQ_INIT(&filter_info->twotuple_list);
886 TAILQ_INIT(&filter_info->fivetuple_list);
888 TAILQ_INIT(&igb_filter_ntuple_list);
889 TAILQ_INIT(&igb_filter_ethertype_list);
890 TAILQ_INIT(&igb_filter_syn_list);
891 TAILQ_INIT(&igb_filter_flex_list);
892 TAILQ_INIT(&igb_filter_rss_list);
893 TAILQ_INIT(&igb_flow_list);
898 igb_hw_control_release(hw);
904 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
906 PMD_INIT_FUNC_TRACE();
908 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
911 eth_igb_close(eth_dev);
917 * Virtual Function device init
920 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
922 struct rte_pci_device *pci_dev;
923 struct rte_intr_handle *intr_handle;
924 struct e1000_adapter *adapter =
925 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
926 struct e1000_hw *hw =
927 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
929 struct rte_ether_addr *perm_addr =
930 (struct rte_ether_addr *)hw->mac.perm_addr;
932 PMD_INIT_FUNC_TRACE();
934 eth_dev->dev_ops = &igbvf_eth_dev_ops;
935 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
936 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
937 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
938 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
939 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
940 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
942 /* for secondary processes, we don't initialise any further as primary
943 * has already done this work. Only check we don't need a different
945 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
946 if (eth_dev->data->scattered_rx)
947 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
951 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
952 rte_eth_copy_pci_info(eth_dev, pci_dev);
953 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
955 hw->device_id = pci_dev->id.device_id;
956 hw->vendor_id = pci_dev->id.vendor_id;
957 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
958 adapter->stopped = 0;
960 /* Initialize the shared code (base driver) */
961 diag = e1000_setup_init_funcs(hw, TRUE);
963 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
968 /* init_mailbox_params */
969 hw->mbx.ops.init_params(hw);
971 /* Disable the interrupts for VF */
972 igbvf_intr_disable(hw);
974 diag = hw->mac.ops.reset_hw(hw);
976 /* Allocate memory for storing MAC addresses */
977 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
978 hw->mac.rar_entry_count, 0);
979 if (eth_dev->data->mac_addrs == NULL) {
981 "Failed to allocate %d bytes needed to store MAC "
983 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
987 /* Generate a random MAC address, if none was assigned by PF. */
988 if (rte_is_zero_ether_addr(perm_addr)) {
989 rte_eth_random_addr(perm_addr->addr_bytes);
990 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
991 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
992 "%02x:%02x:%02x:%02x:%02x:%02x",
993 perm_addr->addr_bytes[0],
994 perm_addr->addr_bytes[1],
995 perm_addr->addr_bytes[2],
996 perm_addr->addr_bytes[3],
997 perm_addr->addr_bytes[4],
998 perm_addr->addr_bytes[5]);
1001 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1003 rte_free(eth_dev->data->mac_addrs);
1004 eth_dev->data->mac_addrs = NULL;
1007 /* Copy the permanent MAC address */
1008 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1009 ð_dev->data->mac_addrs[0]);
1011 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1013 eth_dev->data->port_id, pci_dev->id.vendor_id,
1014 pci_dev->id.device_id, "igb_mac_82576_vf");
1016 intr_handle = &pci_dev->intr_handle;
1017 rte_intr_callback_register(intr_handle,
1018 eth_igbvf_interrupt_handler, eth_dev);
1024 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1026 PMD_INIT_FUNC_TRACE();
1028 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1031 igbvf_dev_close(eth_dev);
1036 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1037 struct rte_pci_device *pci_dev)
1039 return rte_eth_dev_pci_generic_probe(pci_dev,
1040 sizeof(struct e1000_adapter), eth_igb_dev_init);
1043 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1045 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1048 static struct rte_pci_driver rte_igb_pmd = {
1049 .id_table = pci_id_igb_map,
1050 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1051 .probe = eth_igb_pci_probe,
1052 .remove = eth_igb_pci_remove,
1056 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1057 struct rte_pci_device *pci_dev)
1059 return rte_eth_dev_pci_generic_probe(pci_dev,
1060 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1063 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1065 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1069 * virtual function driver struct
1071 static struct rte_pci_driver rte_igbvf_pmd = {
1072 .id_table = pci_id_igbvf_map,
1073 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1074 .probe = eth_igbvf_pci_probe,
1075 .remove = eth_igbvf_pci_remove,
1079 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1081 struct e1000_hw *hw =
1082 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1083 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1084 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1085 rctl |= E1000_RCTL_VFE;
1086 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1090 igb_check_mq_mode(struct rte_eth_dev *dev)
1092 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1093 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1094 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1095 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1097 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1098 tx_mq_mode == ETH_MQ_TX_DCB ||
1099 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1100 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1103 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1104 /* Check multi-queue mode.
1105 * To no break software we accept ETH_MQ_RX_NONE as this might
1106 * be used to turn off VLAN filter.
1109 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1110 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1111 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1112 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1114 /* Only support one queue on VFs.
1115 * RSS together with SRIOV is not supported.
1117 PMD_INIT_LOG(ERR, "SRIOV is active,"
1118 " wrong mq_mode rx %d.",
1122 /* TX mode is not used here, so mode might be ignored.*/
1123 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1124 /* SRIOV only works in VMDq enable mode */
1125 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1126 " TX mode %d is not supported. "
1127 " Driver will behave as %d mode.",
1128 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1131 /* check valid queue number */
1132 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1133 PMD_INIT_LOG(ERR, "SRIOV is active,"
1134 " only support one queue on VFs.");
1138 /* To no break software that set invalid mode, only display
1139 * warning if invalid mode is used.
1141 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1142 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1143 rx_mq_mode != ETH_MQ_RX_RSS) {
1144 /* RSS together with VMDq not supported*/
1145 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1150 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1151 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1152 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1153 " Due to txmode is meaningless in this"
1154 " driver, just ignore.",
1162 eth_igb_configure(struct rte_eth_dev *dev)
1164 struct e1000_interrupt *intr =
1165 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1168 PMD_INIT_FUNC_TRACE();
1170 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1171 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1173 /* multipe queue mode checking */
1174 ret = igb_check_mq_mode(dev);
1176 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1181 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1182 PMD_INIT_FUNC_TRACE();
1188 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1191 struct e1000_hw *hw =
1192 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1193 uint32_t tctl, rctl;
1195 tctl = E1000_READ_REG(hw, E1000_TCTL);
1196 rctl = E1000_READ_REG(hw, E1000_RCTL);
1200 tctl |= E1000_TCTL_EN;
1201 rctl |= E1000_RCTL_EN;
1204 tctl &= ~E1000_TCTL_EN;
1205 rctl &= ~E1000_RCTL_EN;
1207 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1208 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1209 E1000_WRITE_FLUSH(hw);
1213 eth_igb_start(struct rte_eth_dev *dev)
1215 struct e1000_hw *hw =
1216 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217 struct e1000_adapter *adapter =
1218 E1000_DEV_PRIVATE(dev->data->dev_private);
1219 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1220 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1222 uint32_t intr_vector = 0;
1228 PMD_INIT_FUNC_TRACE();
1230 /* disable uio/vfio intr/eventfd mapping */
1231 rte_intr_disable(intr_handle);
1233 /* Power up the phy. Needed to make the link go Up */
1234 eth_igb_dev_set_link_up(dev);
1237 * Packet Buffer Allocation (PBA)
1238 * Writing PBA sets the receive portion of the buffer
1239 * the remainder is used for the transmit buffer.
1241 if (hw->mac.type == e1000_82575) {
1244 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1245 E1000_WRITE_REG(hw, E1000_PBA, pba);
1248 /* Put the address into the Receive Address Array */
1249 e1000_rar_set(hw, hw->mac.addr, 0);
1251 /* Initialize the hardware */
1252 if (igb_hardware_init(hw)) {
1253 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1256 adapter->stopped = 0;
1258 E1000_WRITE_REG(hw, E1000_VET,
1259 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1261 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1262 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1263 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1264 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1265 E1000_WRITE_FLUSH(hw);
1267 /* configure PF module if SRIOV enabled */
1268 igb_pf_host_configure(dev);
1270 /* check and configure queue intr-vector mapping */
1271 if ((rte_intr_cap_multiple(intr_handle) ||
1272 !RTE_ETH_DEV_SRIOV(dev).active) &&
1273 dev->data->dev_conf.intr_conf.rxq != 0) {
1274 intr_vector = dev->data->nb_rx_queues;
1275 if (rte_intr_efd_enable(intr_handle, intr_vector))
1279 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1280 intr_handle->intr_vec =
1281 rte_zmalloc("intr_vec",
1282 dev->data->nb_rx_queues * sizeof(int), 0);
1283 if (intr_handle->intr_vec == NULL) {
1284 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1285 " intr_vec", dev->data->nb_rx_queues);
1290 /* confiugre msix for rx interrupt */
1291 eth_igb_configure_msix_intr(dev);
1293 /* Configure for OS presence */
1294 igb_init_manageability(hw);
1296 eth_igb_tx_init(dev);
1298 /* This can fail when allocating mbufs for descriptor rings */
1299 ret = eth_igb_rx_init(dev);
1301 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1302 igb_dev_clear_queues(dev);
1306 e1000_clear_hw_cntrs_base_generic(hw);
1309 * VLAN Offload Settings
1311 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1312 ETH_VLAN_EXTEND_MASK;
1313 ret = eth_igb_vlan_offload_set(dev, mask);
1315 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1316 igb_dev_clear_queues(dev);
1320 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1321 /* Enable VLAN filter since VMDq always use VLAN filter */
1322 igb_vmdq_vlan_hw_filter_enable(dev);
1325 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1326 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1327 (hw->mac.type == e1000_i211)) {
1328 /* Configure EITR with the maximum possible value (0xFFFF) */
1329 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1332 /* Setup link speed and duplex */
1333 speeds = &dev->data->dev_conf.link_speeds;
1334 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1335 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1336 hw->mac.autoneg = 1;
1339 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1342 hw->phy.autoneg_advertised = 0;
1344 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1345 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1346 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1348 goto error_invalid_config;
1350 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1351 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1354 if (*speeds & ETH_LINK_SPEED_10M) {
1355 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1358 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1359 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1362 if (*speeds & ETH_LINK_SPEED_100M) {
1363 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1366 if (*speeds & ETH_LINK_SPEED_1G) {
1367 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1370 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1371 goto error_invalid_config;
1373 /* Set/reset the mac.autoneg based on the link speed,
1377 hw->mac.autoneg = 0;
1378 hw->mac.forced_speed_duplex =
1379 hw->phy.autoneg_advertised;
1381 hw->mac.autoneg = 1;
1385 e1000_setup_link(hw);
1387 if (rte_intr_allow_others(intr_handle)) {
1388 /* check if lsc interrupt is enabled */
1389 if (dev->data->dev_conf.intr_conf.lsc != 0)
1390 eth_igb_lsc_interrupt_setup(dev, TRUE);
1392 eth_igb_lsc_interrupt_setup(dev, FALSE);
1394 rte_intr_callback_unregister(intr_handle,
1395 eth_igb_interrupt_handler,
1397 if (dev->data->dev_conf.intr_conf.lsc != 0)
1398 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1399 " no intr multiplex");
1402 /* check if rxq interrupt is enabled */
1403 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1404 rte_intr_dp_is_en(intr_handle))
1405 eth_igb_rxq_interrupt_setup(dev);
1407 /* enable uio/vfio intr/eventfd mapping */
1408 rte_intr_enable(intr_handle);
1410 /* resume enabled intr since hw reset */
1411 igb_intr_enable(dev);
1413 /* restore all types filter */
1414 igb_filter_restore(dev);
1416 eth_igb_rxtx_control(dev, true);
1417 eth_igb_link_update(dev, 0);
1419 PMD_INIT_LOG(DEBUG, "<<");
1423 error_invalid_config:
1424 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1425 dev->data->dev_conf.link_speeds, dev->data->port_id);
1426 igb_dev_clear_queues(dev);
1430 /*********************************************************************
1432 * This routine disables all traffic on the adapter by issuing a
1433 * global reset on the MAC.
1435 **********************************************************************/
1437 eth_igb_stop(struct rte_eth_dev *dev)
1439 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1440 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1441 struct rte_eth_link link;
1442 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1443 struct e1000_adapter *adapter =
1444 E1000_DEV_PRIVATE(dev->data->dev_private);
1446 if (adapter->stopped)
1449 eth_igb_rxtx_control(dev, false);
1451 igb_intr_disable(dev);
1453 /* disable intr eventfd mapping */
1454 rte_intr_disable(intr_handle);
1456 igb_pf_reset_hw(hw);
1457 E1000_WRITE_REG(hw, E1000_WUC, 0);
1459 /* Set bit for Go Link disconnect if PHY reset is not blocked */
1460 if (hw->mac.type >= e1000_82580 &&
1461 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1464 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1465 phpm_reg |= E1000_82580_PM_GO_LINKD;
1466 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1469 /* Power down the phy. Needed to make the link go Down */
1470 eth_igb_dev_set_link_down(dev);
1472 igb_dev_clear_queues(dev);
1474 /* clear the recorded link status */
1475 memset(&link, 0, sizeof(link));
1476 rte_eth_linkstatus_set(dev, &link);
1478 if (!rte_intr_allow_others(intr_handle))
1479 /* resume to the default handler */
1480 rte_intr_callback_register(intr_handle,
1481 eth_igb_interrupt_handler,
1484 /* Clean datapath event and queue/vec mapping */
1485 rte_intr_efd_disable(intr_handle);
1486 if (intr_handle->intr_vec != NULL) {
1487 rte_free(intr_handle->intr_vec);
1488 intr_handle->intr_vec = NULL;
1491 adapter->stopped = true;
1492 dev->data->dev_started = 0;
1498 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1500 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1502 if (hw->phy.media_type == e1000_media_type_copper)
1503 e1000_power_up_phy(hw);
1505 e1000_power_up_fiber_serdes_link(hw);
1511 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1513 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515 if (hw->phy.media_type == e1000_media_type_copper)
1516 e1000_power_down_phy(hw);
1518 e1000_shutdown_fiber_serdes_link(hw);
1524 eth_igb_close(struct rte_eth_dev *dev)
1526 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1527 struct rte_eth_link link;
1528 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1529 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1530 struct e1000_filter_info *filter_info =
1531 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1534 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1537 ret = eth_igb_stop(dev);
1539 e1000_phy_hw_reset(hw);
1540 igb_release_manageability(hw);
1541 igb_hw_control_release(hw);
1543 /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1544 if (hw->mac.type >= e1000_82580 &&
1545 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1548 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1549 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1550 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1553 igb_dev_free_queues(dev);
1555 if (intr_handle->intr_vec) {
1556 rte_free(intr_handle->intr_vec);
1557 intr_handle->intr_vec = NULL;
1560 memset(&link, 0, sizeof(link));
1561 rte_eth_linkstatus_set(dev, &link);
1563 /* Reset any pending lock */
1564 igb_reset_swfw_lock(hw);
1566 /* uninitialize PF if max_vfs not zero */
1567 igb_pf_host_uninit(dev);
1569 rte_intr_callback_unregister(intr_handle,
1570 eth_igb_interrupt_handler, dev);
1572 /* clear the SYN filter info */
1573 filter_info->syn_info = 0;
1575 /* clear the ethertype filters info */
1576 filter_info->ethertype_mask = 0;
1577 memset(filter_info->ethertype_filters, 0,
1578 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1580 /* clear the rss filter info */
1581 memset(&filter_info->rss_info, 0,
1582 sizeof(struct igb_rte_flow_rss_conf));
1584 /* remove all ntuple filters of the device */
1585 igb_ntuple_filter_uninit(dev);
1587 /* remove all flex filters of the device */
1588 igb_flex_filter_uninit(dev);
1590 /* clear all the filters list */
1591 igb_filterlist_flush(dev);
1600 eth_igb_reset(struct rte_eth_dev *dev)
1604 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1605 * its VF to make them align with it. The detailed notification
1606 * mechanism is PMD specific and is currently not implemented.
1607 * To avoid unexpected behavior in VF, currently reset of PF with
1608 * SR-IOV activation is not supported. It might be supported later.
1610 if (dev->data->sriov.active)
1613 ret = eth_igb_dev_uninit(dev);
1617 ret = eth_igb_dev_init(dev);
1624 igb_get_rx_buffer_size(struct e1000_hw *hw)
1626 uint32_t rx_buf_size;
1627 if (hw->mac.type == e1000_82576) {
1628 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1629 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1630 /* PBS needs to be translated according to a lookup table */
1631 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1632 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1633 rx_buf_size = (rx_buf_size << 10);
1634 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1635 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1637 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1643 /*********************************************************************
1645 * Initialize the hardware
1647 **********************************************************************/
1649 igb_hardware_init(struct e1000_hw *hw)
1651 uint32_t rx_buf_size;
1654 /* Let the firmware know the OS is in control */
1655 igb_hw_control_acquire(hw);
1658 * These parameters control the automatic generation (Tx) and
1659 * response (Rx) to Ethernet PAUSE frames.
1660 * - High water mark should allow for at least two standard size (1518)
1661 * frames to be received after sending an XOFF.
1662 * - Low water mark works best when it is very near the high water mark.
1663 * This allows the receiver to restart by sending XON when it has
1664 * drained a bit. Here we use an arbitrary value of 1500 which will
1665 * restart after one full frame is pulled from the buffer. There
1666 * could be several smaller frames in the buffer and if so they will
1667 * not trigger the XON until their total number reduces the buffer
1669 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1671 rx_buf_size = igb_get_rx_buffer_size(hw);
1673 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1674 hw->fc.low_water = hw->fc.high_water - 1500;
1675 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1676 hw->fc.send_xon = 1;
1678 /* Set Flow control, use the tunable location if sane */
1679 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1680 hw->fc.requested_mode = igb_fc_setting;
1682 hw->fc.requested_mode = e1000_fc_none;
1684 /* Issue a global reset */
1685 igb_pf_reset_hw(hw);
1686 E1000_WRITE_REG(hw, E1000_WUC, 0);
1688 diag = e1000_init_hw(hw);
1692 E1000_WRITE_REG(hw, E1000_VET,
1693 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1694 e1000_get_phy_info(hw);
1695 e1000_check_for_link(hw);
1700 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1702 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1706 uint64_t old_gprc = stats->gprc;
1707 uint64_t old_gptc = stats->gptc;
1708 uint64_t old_tpr = stats->tpr;
1709 uint64_t old_tpt = stats->tpt;
1710 uint64_t old_rpthc = stats->rpthc;
1711 uint64_t old_hgptc = stats->hgptc;
1713 if(hw->phy.media_type == e1000_media_type_copper ||
1714 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1716 E1000_READ_REG(hw,E1000_SYMERRS);
1717 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1720 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1721 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1722 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1723 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1725 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1726 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1727 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1728 stats->dc += E1000_READ_REG(hw, E1000_DC);
1729 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1730 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1731 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1733 ** For watchdog management we need to know if we have been
1734 ** paused during the last interval, so capture that here.
1736 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1737 stats->xoffrxc += pause_frames;
1738 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1739 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1740 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1741 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1742 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1743 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1744 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1745 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1746 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1747 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1748 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1749 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1751 /* For the 64-bit byte counters the low dword must be read first. */
1752 /* Both registers clear on the read of the high dword */
1754 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1755 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1756 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1757 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1758 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1759 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1760 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1762 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1763 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1764 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1765 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1766 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1768 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1769 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1771 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1772 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1773 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1774 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1775 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1776 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1778 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1779 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1780 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1781 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1782 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1783 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1784 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1785 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1787 /* Interrupt Counts */
1789 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1790 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1791 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1792 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1793 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1794 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1795 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1796 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1797 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1799 /* Host to Card Statistics */
1801 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1802 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1803 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1804 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1805 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1806 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1807 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1808 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1809 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1810 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1811 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1812 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1813 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1814 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1815 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1816 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1818 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1819 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1820 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1821 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1822 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1823 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1827 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1829 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1830 struct e1000_hw_stats *stats =
1831 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1833 igb_read_stats_registers(hw, stats);
1835 if (rte_stats == NULL)
1839 rte_stats->imissed = stats->mpc;
1840 rte_stats->ierrors = stats->crcerrs +
1841 stats->rlec + stats->ruc + stats->roc +
1842 stats->rxerrc + stats->algnerrc + stats->cexterr;
1845 rte_stats->oerrors = stats->ecol + stats->latecol;
1847 rte_stats->ipackets = stats->gprc;
1848 rte_stats->opackets = stats->gptc;
1849 rte_stats->ibytes = stats->gorc;
1850 rte_stats->obytes = stats->gotc;
1855 eth_igb_stats_reset(struct rte_eth_dev *dev)
1857 struct e1000_hw_stats *hw_stats =
1858 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1860 /* HW registers are cleared on read */
1861 eth_igb_stats_get(dev, NULL);
1863 /* Reset software totals */
1864 memset(hw_stats, 0, sizeof(*hw_stats));
1870 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1872 struct e1000_hw_stats *stats =
1873 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1875 /* HW registers are cleared on read */
1876 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1878 /* Reset software totals */
1879 memset(stats, 0, sizeof(*stats));
1884 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1885 struct rte_eth_xstat_name *xstats_names,
1886 __rte_unused unsigned int size)
1890 if (xstats_names == NULL)
1891 return IGB_NB_XSTATS;
1893 /* Note: limit checked in rte_eth_xstats_names() */
1895 for (i = 0; i < IGB_NB_XSTATS; i++) {
1896 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1897 sizeof(xstats_names[i].name));
1900 return IGB_NB_XSTATS;
1903 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1904 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1910 if (xstats_names == NULL)
1911 return IGB_NB_XSTATS;
1913 for (i = 0; i < IGB_NB_XSTATS; i++)
1914 strlcpy(xstats_names[i].name,
1915 rte_igb_stats_strings[i].name,
1916 sizeof(xstats_names[i].name));
1918 return IGB_NB_XSTATS;
1921 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1923 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1926 for (i = 0; i < limit; i++) {
1927 if (ids[i] >= IGB_NB_XSTATS) {
1928 PMD_INIT_LOG(ERR, "id value isn't valid");
1931 strcpy(xstats_names[i].name,
1932 xstats_names_copy[ids[i]].name);
1939 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1942 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943 struct e1000_hw_stats *hw_stats =
1944 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1947 if (n < IGB_NB_XSTATS)
1948 return IGB_NB_XSTATS;
1950 igb_read_stats_registers(hw, hw_stats);
1952 /* If this is a reset xstats is NULL, and we have cleared the
1953 * registers by reading them.
1958 /* Extended stats */
1959 for (i = 0; i < IGB_NB_XSTATS; i++) {
1961 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1962 rte_igb_stats_strings[i].offset);
1965 return IGB_NB_XSTATS;
1969 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1970 uint64_t *values, unsigned int n)
1975 struct e1000_hw *hw =
1976 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977 struct e1000_hw_stats *hw_stats =
1978 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1980 if (n < IGB_NB_XSTATS)
1981 return IGB_NB_XSTATS;
1983 igb_read_stats_registers(hw, hw_stats);
1985 /* If this is a reset xstats is NULL, and we have cleared the
1986 * registers by reading them.
1991 /* Extended stats */
1992 for (i = 0; i < IGB_NB_XSTATS; i++)
1993 values[i] = *(uint64_t *)(((char *)hw_stats) +
1994 rte_igb_stats_strings[i].offset);
1996 return IGB_NB_XSTATS;
1999 uint64_t values_copy[IGB_NB_XSTATS];
2001 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2004 for (i = 0; i < n; i++) {
2005 if (ids[i] >= IGB_NB_XSTATS) {
2006 PMD_INIT_LOG(ERR, "id value isn't valid");
2009 values[i] = values_copy[ids[i]];
2016 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2018 /* Good Rx packets, include VF loopback */
2019 UPDATE_VF_STAT(E1000_VFGPRC,
2020 hw_stats->last_gprc, hw_stats->gprc);
2022 /* Good Rx octets, include VF loopback */
2023 UPDATE_VF_STAT(E1000_VFGORC,
2024 hw_stats->last_gorc, hw_stats->gorc);
2026 /* Good Tx packets, include VF loopback */
2027 UPDATE_VF_STAT(E1000_VFGPTC,
2028 hw_stats->last_gptc, hw_stats->gptc);
2030 /* Good Tx octets, include VF loopback */
2031 UPDATE_VF_STAT(E1000_VFGOTC,
2032 hw_stats->last_gotc, hw_stats->gotc);
2034 /* Rx Multicst packets */
2035 UPDATE_VF_STAT(E1000_VFMPRC,
2036 hw_stats->last_mprc, hw_stats->mprc);
2038 /* Good Rx loopback packets */
2039 UPDATE_VF_STAT(E1000_VFGPRLBC,
2040 hw_stats->last_gprlbc, hw_stats->gprlbc);
2042 /* Good Rx loopback octets */
2043 UPDATE_VF_STAT(E1000_VFGORLBC,
2044 hw_stats->last_gorlbc, hw_stats->gorlbc);
2046 /* Good Tx loopback packets */
2047 UPDATE_VF_STAT(E1000_VFGPTLBC,
2048 hw_stats->last_gptlbc, hw_stats->gptlbc);
2050 /* Good Tx loopback octets */
2051 UPDATE_VF_STAT(E1000_VFGOTLBC,
2052 hw_stats->last_gotlbc, hw_stats->gotlbc);
2055 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2056 struct rte_eth_xstat_name *xstats_names,
2057 __rte_unused unsigned limit)
2061 if (xstats_names != NULL)
2062 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2063 strlcpy(xstats_names[i].name,
2064 rte_igbvf_stats_strings[i].name,
2065 sizeof(xstats_names[i].name));
2067 return IGBVF_NB_XSTATS;
2071 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2074 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2076 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2079 if (n < IGBVF_NB_XSTATS)
2080 return IGBVF_NB_XSTATS;
2082 igbvf_read_stats_registers(hw, hw_stats);
2087 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2089 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2090 rte_igbvf_stats_strings[i].offset);
2093 return IGBVF_NB_XSTATS;
2097 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2099 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2101 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2103 igbvf_read_stats_registers(hw, hw_stats);
2105 if (rte_stats == NULL)
2108 rte_stats->ipackets = hw_stats->gprc;
2109 rte_stats->ibytes = hw_stats->gorc;
2110 rte_stats->opackets = hw_stats->gptc;
2111 rte_stats->obytes = hw_stats->gotc;
2116 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2118 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2119 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2121 /* Sync HW register to the last stats */
2122 eth_igbvf_stats_get(dev, NULL);
2124 /* reset HW current stats*/
2125 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2126 offsetof(struct e1000_vf_stats, gprc));
2132 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2135 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2136 struct e1000_fw_version fw;
2139 e1000_get_fw_version(hw, &fw);
2141 switch (hw->mac.type) {
2144 if (!(e1000_get_flash_presence_i210(hw))) {
2145 ret = snprintf(fw_version, fw_size,
2147 fw.invm_major, fw.invm_minor,
2153 /* if option rom is valid, display its version too */
2155 ret = snprintf(fw_version, fw_size,
2156 "%d.%d, 0x%08x, %d.%d.%d",
2157 fw.eep_major, fw.eep_minor, fw.etrack_id,
2158 fw.or_major, fw.or_build, fw.or_patch);
2161 if (fw.etrack_id != 0X0000) {
2162 ret = snprintf(fw_version, fw_size,
2164 fw.eep_major, fw.eep_minor,
2167 ret = snprintf(fw_version, fw_size,
2169 fw.eep_major, fw.eep_minor,
2176 ret += 1; /* add the size of '\0' */
2177 if (fw_size < (u32)ret)
2184 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2186 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2189 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2190 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2191 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2192 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2193 dev_info->rx_queue_offload_capa;
2194 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2195 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2196 dev_info->tx_queue_offload_capa;
2198 switch (hw->mac.type) {
2200 dev_info->max_rx_queues = 4;
2201 dev_info->max_tx_queues = 4;
2202 dev_info->max_vmdq_pools = 0;
2206 dev_info->max_rx_queues = 16;
2207 dev_info->max_tx_queues = 16;
2208 dev_info->max_vmdq_pools = ETH_8_POOLS;
2209 dev_info->vmdq_queue_num = 16;
2213 dev_info->max_rx_queues = 8;
2214 dev_info->max_tx_queues = 8;
2215 dev_info->max_vmdq_pools = ETH_8_POOLS;
2216 dev_info->vmdq_queue_num = 8;
2220 dev_info->max_rx_queues = 8;
2221 dev_info->max_tx_queues = 8;
2222 dev_info->max_vmdq_pools = ETH_8_POOLS;
2223 dev_info->vmdq_queue_num = 8;
2227 dev_info->max_rx_queues = 8;
2228 dev_info->max_tx_queues = 8;
2232 dev_info->max_rx_queues = 4;
2233 dev_info->max_tx_queues = 4;
2234 dev_info->max_vmdq_pools = 0;
2238 dev_info->max_rx_queues = 2;
2239 dev_info->max_tx_queues = 2;
2240 dev_info->max_vmdq_pools = 0;
2244 /* Should not happen */
2247 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2248 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2249 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2251 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2253 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2254 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2255 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2257 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2262 dev_info->default_txconf = (struct rte_eth_txconf) {
2264 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2265 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2266 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2271 dev_info->rx_desc_lim = rx_desc_lim;
2272 dev_info->tx_desc_lim = tx_desc_lim;
2274 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2275 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2278 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2279 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2284 static const uint32_t *
2285 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2287 static const uint32_t ptypes[] = {
2288 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2291 RTE_PTYPE_L3_IPV4_EXT,
2293 RTE_PTYPE_L3_IPV6_EXT,
2297 RTE_PTYPE_TUNNEL_IP,
2298 RTE_PTYPE_INNER_L3_IPV6,
2299 RTE_PTYPE_INNER_L3_IPV6_EXT,
2300 RTE_PTYPE_INNER_L4_TCP,
2301 RTE_PTYPE_INNER_L4_UDP,
2305 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2306 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2312 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2314 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2317 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2318 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2319 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2320 DEV_TX_OFFLOAD_IPV4_CKSUM |
2321 DEV_TX_OFFLOAD_UDP_CKSUM |
2322 DEV_TX_OFFLOAD_TCP_CKSUM |
2323 DEV_TX_OFFLOAD_SCTP_CKSUM |
2324 DEV_TX_OFFLOAD_TCP_TSO;
2325 switch (hw->mac.type) {
2327 dev_info->max_rx_queues = 2;
2328 dev_info->max_tx_queues = 2;
2330 case e1000_vfadapt_i350:
2331 dev_info->max_rx_queues = 1;
2332 dev_info->max_tx_queues = 1;
2335 /* Should not happen */
2339 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2340 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2341 dev_info->rx_queue_offload_capa;
2342 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2343 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2344 dev_info->tx_queue_offload_capa;
2346 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2348 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2349 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2350 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2352 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2357 dev_info->default_txconf = (struct rte_eth_txconf) {
2359 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2360 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2361 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2366 dev_info->rx_desc_lim = rx_desc_lim;
2367 dev_info->tx_desc_lim = tx_desc_lim;
2372 /* return 0 means link status changed, -1 means not changed */
2374 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2376 struct e1000_hw *hw =
2377 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2378 struct rte_eth_link link;
2379 int link_check, count;
2382 hw->mac.get_link_status = 1;
2384 /* possible wait-to-complete in up to 9 seconds */
2385 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2386 /* Read the real link status */
2387 switch (hw->phy.media_type) {
2388 case e1000_media_type_copper:
2389 /* Do the work to read phy */
2390 e1000_check_for_link(hw);
2391 link_check = !hw->mac.get_link_status;
2394 case e1000_media_type_fiber:
2395 e1000_check_for_link(hw);
2396 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2400 case e1000_media_type_internal_serdes:
2401 e1000_check_for_link(hw);
2402 link_check = hw->mac.serdes_has_link;
2405 /* VF device is type_unknown */
2406 case e1000_media_type_unknown:
2407 eth_igbvf_link_update(hw);
2408 link_check = !hw->mac.get_link_status;
2414 if (link_check || wait_to_complete == 0)
2416 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2418 memset(&link, 0, sizeof(link));
2420 /* Now we check if a transition has happened */
2422 uint16_t duplex, speed;
2423 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2424 link.link_duplex = (duplex == FULL_DUPLEX) ?
2425 ETH_LINK_FULL_DUPLEX :
2426 ETH_LINK_HALF_DUPLEX;
2427 link.link_speed = speed;
2428 link.link_status = ETH_LINK_UP;
2429 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2430 ETH_LINK_SPEED_FIXED);
2431 } else if (!link_check) {
2432 link.link_speed = 0;
2433 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2434 link.link_status = ETH_LINK_DOWN;
2435 link.link_autoneg = ETH_LINK_FIXED;
2438 return rte_eth_linkstatus_set(dev, &link);
2442 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2443 * For ASF and Pass Through versions of f/w this means
2444 * that the driver is loaded.
2447 igb_hw_control_acquire(struct e1000_hw *hw)
2451 /* Let firmware know the driver has taken over */
2452 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2453 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2457 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2458 * For ASF and Pass Through versions of f/w this means that the
2459 * driver is no longer loaded.
2462 igb_hw_control_release(struct e1000_hw *hw)
2466 /* Let firmware taken over control of h/w */
2467 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2468 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2469 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2473 * Bit of a misnomer, what this really means is
2474 * to enable OS management of the system... aka
2475 * to disable special hardware management features.
2478 igb_init_manageability(struct e1000_hw *hw)
2480 if (e1000_enable_mng_pass_thru(hw)) {
2481 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2482 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2484 /* disable hardware interception of ARP */
2485 manc &= ~(E1000_MANC_ARP_EN);
2487 /* enable receiving management packets to the host */
2488 manc |= E1000_MANC_EN_MNG2HOST;
2489 manc2h |= 1 << 5; /* Mng Port 623 */
2490 manc2h |= 1 << 6; /* Mng Port 664 */
2491 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2492 E1000_WRITE_REG(hw, E1000_MANC, manc);
2497 igb_release_manageability(struct e1000_hw *hw)
2499 if (e1000_enable_mng_pass_thru(hw)) {
2500 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2502 manc |= E1000_MANC_ARP_EN;
2503 manc &= ~E1000_MANC_EN_MNG2HOST;
2505 E1000_WRITE_REG(hw, E1000_MANC, manc);
2510 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2512 struct e1000_hw *hw =
2513 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2516 rctl = E1000_READ_REG(hw, E1000_RCTL);
2517 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2518 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2524 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2526 struct e1000_hw *hw =
2527 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2530 rctl = E1000_READ_REG(hw, E1000_RCTL);
2531 rctl &= (~E1000_RCTL_UPE);
2532 if (dev->data->all_multicast == 1)
2533 rctl |= E1000_RCTL_MPE;
2535 rctl &= (~E1000_RCTL_MPE);
2536 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2542 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2544 struct e1000_hw *hw =
2545 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2548 rctl = E1000_READ_REG(hw, E1000_RCTL);
2549 rctl |= E1000_RCTL_MPE;
2550 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2556 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2558 struct e1000_hw *hw =
2559 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562 if (dev->data->promiscuous == 1)
2563 return 0; /* must remain in all_multicast mode */
2564 rctl = E1000_READ_REG(hw, E1000_RCTL);
2565 rctl &= (~E1000_RCTL_MPE);
2566 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2572 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2574 struct e1000_hw *hw =
2575 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576 struct e1000_vfta * shadow_vfta =
2577 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2582 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2583 E1000_VFTA_ENTRY_MASK);
2584 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2585 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2590 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2592 /* update local VFTA copy */
2593 shadow_vfta->vfta[vid_idx] = vfta;
2599 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2600 enum rte_vlan_type vlan_type,
2603 struct e1000_hw *hw =
2604 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2607 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2608 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2610 /* only outer TPID of double VLAN can be configured*/
2611 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2612 reg = E1000_READ_REG(hw, E1000_VET);
2613 reg = (reg & (~E1000_VET_VET_EXT)) |
2614 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2615 E1000_WRITE_REG(hw, E1000_VET, reg);
2620 /* all other TPID values are read-only*/
2621 PMD_DRV_LOG(ERR, "Not supported");
2627 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2629 struct e1000_hw *hw =
2630 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2633 /* Filter Table Disable */
2634 reg = E1000_READ_REG(hw, E1000_RCTL);
2635 reg &= ~E1000_RCTL_CFIEN;
2636 reg &= ~E1000_RCTL_VFE;
2637 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2641 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2643 struct e1000_hw *hw =
2644 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645 struct e1000_vfta * shadow_vfta =
2646 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2650 /* Filter Table Enable, CFI not used for packet acceptance */
2651 reg = E1000_READ_REG(hw, E1000_RCTL);
2652 reg &= ~E1000_RCTL_CFIEN;
2653 reg |= E1000_RCTL_VFE;
2654 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2656 /* restore VFTA table */
2657 for (i = 0; i < IGB_VFTA_SIZE; i++)
2658 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2662 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2664 struct e1000_hw *hw =
2665 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668 /* VLAN Mode Disable */
2669 reg = E1000_READ_REG(hw, E1000_CTRL);
2670 reg &= ~E1000_CTRL_VME;
2671 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2675 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2677 struct e1000_hw *hw =
2678 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681 /* VLAN Mode Enable */
2682 reg = E1000_READ_REG(hw, E1000_CTRL);
2683 reg |= E1000_CTRL_VME;
2684 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2688 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2690 struct e1000_hw *hw =
2691 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2694 /* CTRL_EXT: Extended VLAN */
2695 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2696 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2697 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2699 /* Update maximum packet length */
2700 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2701 E1000_WRITE_REG(hw, E1000_RLPML,
2702 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2707 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2709 struct e1000_hw *hw =
2710 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713 /* CTRL_EXT: Extended VLAN */
2714 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2715 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2716 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2718 /* Update maximum packet length */
2719 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2720 E1000_WRITE_REG(hw, E1000_RLPML,
2721 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2726 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2728 struct rte_eth_rxmode *rxmode;
2730 rxmode = &dev->data->dev_conf.rxmode;
2731 if(mask & ETH_VLAN_STRIP_MASK){
2732 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2733 igb_vlan_hw_strip_enable(dev);
2735 igb_vlan_hw_strip_disable(dev);
2738 if(mask & ETH_VLAN_FILTER_MASK){
2739 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2740 igb_vlan_hw_filter_enable(dev);
2742 igb_vlan_hw_filter_disable(dev);
2745 if(mask & ETH_VLAN_EXTEND_MASK){
2746 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2747 igb_vlan_hw_extend_enable(dev);
2749 igb_vlan_hw_extend_disable(dev);
2757 * It enables the interrupt mask and then enable the interrupt.
2760 * Pointer to struct rte_eth_dev.
2765 * - On success, zero.
2766 * - On failure, a negative value.
2769 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2771 struct e1000_interrupt *intr =
2772 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2775 intr->mask |= E1000_ICR_LSC;
2777 intr->mask &= ~E1000_ICR_LSC;
2782 /* It clears the interrupt causes and enables the interrupt.
2783 * It will be called once only during nic initialized.
2786 * Pointer to struct rte_eth_dev.
2789 * - On success, zero.
2790 * - On failure, a negative value.
2792 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2794 uint32_t mask, regval;
2796 struct e1000_hw *hw =
2797 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2798 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2799 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2800 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2801 struct rte_eth_dev_info dev_info;
2803 memset(&dev_info, 0, sizeof(dev_info));
2804 ret = eth_igb_infos_get(dev, &dev_info);
2808 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2809 regval = E1000_READ_REG(hw, E1000_EIMS);
2810 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2816 * It reads ICR and gets interrupt causes, check it and set a bit flag
2817 * to update link status.
2820 * Pointer to struct rte_eth_dev.
2823 * - On success, zero.
2824 * - On failure, a negative value.
2827 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2830 struct e1000_hw *hw =
2831 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832 struct e1000_interrupt *intr =
2833 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2835 igb_intr_disable(dev);
2837 /* read-on-clear nic registers here */
2838 icr = E1000_READ_REG(hw, E1000_ICR);
2841 if (icr & E1000_ICR_LSC) {
2842 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2845 if (icr & E1000_ICR_VMMB)
2846 intr->flags |= E1000_FLAG_MAILBOX;
2852 * It executes link_update after knowing an interrupt is prsent.
2855 * Pointer to struct rte_eth_dev.
2858 * - On success, zero.
2859 * - On failure, a negative value.
2862 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2863 struct rte_intr_handle *intr_handle)
2865 struct e1000_hw *hw =
2866 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2867 struct e1000_interrupt *intr =
2868 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2869 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2870 struct rte_eth_link link;
2873 if (intr->flags & E1000_FLAG_MAILBOX) {
2874 igb_pf_mbx_process(dev);
2875 intr->flags &= ~E1000_FLAG_MAILBOX;
2878 igb_intr_enable(dev);
2879 rte_intr_ack(intr_handle);
2881 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2882 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2884 /* set get_link_status to check register later */
2885 hw->mac.get_link_status = 1;
2886 ret = eth_igb_link_update(dev, 0);
2888 /* check if link has changed */
2892 rte_eth_linkstatus_get(dev, &link);
2893 if (link.link_status) {
2895 " Port %d: Link Up - speed %u Mbps - %s",
2897 (unsigned)link.link_speed,
2898 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2899 "full-duplex" : "half-duplex");
2901 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2902 dev->data->port_id);
2905 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2906 pci_dev->addr.domain,
2908 pci_dev->addr.devid,
2909 pci_dev->addr.function);
2910 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2917 * Interrupt handler which shall be registered at first.
2920 * Pointer to interrupt handle.
2922 * The address of parameter (struct rte_eth_dev *) regsitered before.
2928 eth_igb_interrupt_handler(void *param)
2930 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2932 eth_igb_interrupt_get_status(dev);
2933 eth_igb_interrupt_action(dev, dev->intr_handle);
2937 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2940 struct e1000_hw *hw =
2941 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942 struct e1000_interrupt *intr =
2943 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2945 igbvf_intr_disable(hw);
2947 /* read-on-clear nic registers here */
2948 eicr = E1000_READ_REG(hw, E1000_EICR);
2951 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2952 intr->flags |= E1000_FLAG_MAILBOX;
2957 void igbvf_mbx_process(struct rte_eth_dev *dev)
2959 struct e1000_hw *hw =
2960 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961 struct e1000_mbx_info *mbx = &hw->mbx;
2964 /* peek the message first */
2965 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2967 /* PF reset VF event */
2968 if (in_msg == E1000_PF_CONTROL_MSG) {
2969 /* dummy mbx read to ack pf */
2970 if (mbx->ops.read(hw, &in_msg, 1, 0))
2972 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2978 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2980 struct e1000_interrupt *intr =
2981 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2983 if (intr->flags & E1000_FLAG_MAILBOX) {
2984 igbvf_mbx_process(dev);
2985 intr->flags &= ~E1000_FLAG_MAILBOX;
2988 igbvf_intr_enable(dev);
2989 rte_intr_ack(intr_handle);
2995 eth_igbvf_interrupt_handler(void *param)
2997 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2999 eth_igbvf_interrupt_get_status(dev);
3000 eth_igbvf_interrupt_action(dev, dev->intr_handle);
3004 eth_igb_led_on(struct rte_eth_dev *dev)
3006 struct e1000_hw *hw;
3008 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3013 eth_igb_led_off(struct rte_eth_dev *dev)
3015 struct e1000_hw *hw;
3017 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3022 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3024 struct e1000_hw *hw;
3029 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030 fc_conf->pause_time = hw->fc.pause_time;
3031 fc_conf->high_water = hw->fc.high_water;
3032 fc_conf->low_water = hw->fc.low_water;
3033 fc_conf->send_xon = hw->fc.send_xon;
3034 fc_conf->autoneg = hw->mac.autoneg;
3037 * Return rx_pause and tx_pause status according to actual setting of
3038 * the TFCE and RFCE bits in the CTRL register.
3040 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3041 if (ctrl & E1000_CTRL_TFCE)
3046 if (ctrl & E1000_CTRL_RFCE)
3051 if (rx_pause && tx_pause)
3052 fc_conf->mode = RTE_FC_FULL;
3054 fc_conf->mode = RTE_FC_RX_PAUSE;
3056 fc_conf->mode = RTE_FC_TX_PAUSE;
3058 fc_conf->mode = RTE_FC_NONE;
3064 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3066 struct e1000_hw *hw;
3068 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3074 uint32_t rx_buf_size;
3075 uint32_t max_high_water;
3078 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079 if (fc_conf->autoneg != hw->mac.autoneg)
3081 rx_buf_size = igb_get_rx_buffer_size(hw);
3082 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3084 /* At least reserve one Ethernet frame for watermark */
3085 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3086 if ((fc_conf->high_water > max_high_water) ||
3087 (fc_conf->high_water < fc_conf->low_water)) {
3088 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3089 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3093 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3094 hw->fc.pause_time = fc_conf->pause_time;
3095 hw->fc.high_water = fc_conf->high_water;
3096 hw->fc.low_water = fc_conf->low_water;
3097 hw->fc.send_xon = fc_conf->send_xon;
3099 err = e1000_setup_link_generic(hw);
3100 if (err == E1000_SUCCESS) {
3102 /* check if we want to forward MAC frames - driver doesn't have native
3103 * capability to do that, so we'll write the registers ourselves */
3105 rctl = E1000_READ_REG(hw, E1000_RCTL);
3107 /* set or clear MFLCN.PMCF bit depending on configuration */
3108 if (fc_conf->mac_ctrl_frame_fwd != 0)
3109 rctl |= E1000_RCTL_PMCF;
3111 rctl &= ~E1000_RCTL_PMCF;
3113 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3114 E1000_WRITE_FLUSH(hw);
3119 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3123 #define E1000_RAH_POOLSEL_SHIFT (18)
3125 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3126 uint32_t index, uint32_t pool)
3128 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3132 rah = E1000_READ_REG(hw, E1000_RAH(index));
3133 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3134 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3139 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3141 uint8_t addr[RTE_ETHER_ADDR_LEN];
3142 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3144 memset(addr, 0, sizeof(addr));
3146 e1000_rar_set(hw, addr, index);
3150 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3151 struct rte_ether_addr *addr)
3153 eth_igb_rar_clear(dev, 0);
3154 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3159 * Virtual Function operations
3162 igbvf_intr_disable(struct e1000_hw *hw)
3164 PMD_INIT_FUNC_TRACE();
3166 /* Clear interrupt mask to stop from interrupts being generated */
3167 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3169 E1000_WRITE_FLUSH(hw);
3173 igbvf_stop_adapter(struct rte_eth_dev *dev)
3177 struct rte_eth_dev_info dev_info;
3178 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3181 memset(&dev_info, 0, sizeof(dev_info));
3182 ret = eth_igbvf_infos_get(dev, &dev_info);
3186 /* Clear interrupt mask to stop from interrupts being generated */
3187 igbvf_intr_disable(hw);
3189 /* Clear any pending interrupts, flush previous writes */
3190 E1000_READ_REG(hw, E1000_EICR);
3192 /* Disable the transmit unit. Each queue must be disabled. */
3193 for (i = 0; i < dev_info.max_tx_queues; i++)
3194 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3196 /* Disable the receive unit by stopping each queue */
3197 for (i = 0; i < dev_info.max_rx_queues; i++) {
3198 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3199 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3200 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3201 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3205 /* flush all queues disables */
3206 E1000_WRITE_FLUSH(hw);
3210 static int eth_igbvf_link_update(struct e1000_hw *hw)
3212 struct e1000_mbx_info *mbx = &hw->mbx;
3213 struct e1000_mac_info *mac = &hw->mac;
3214 int ret_val = E1000_SUCCESS;
3216 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3219 * We only want to run this if there has been a rst asserted.
3220 * in this case that could mean a link change, device reset,
3221 * or a virtual function reset
3224 /* If we were hit with a reset or timeout drop the link */
3225 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3226 mac->get_link_status = TRUE;
3228 if (!mac->get_link_status)
3231 /* if link status is down no point in checking to see if pf is up */
3232 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3235 /* if we passed all the tests above then the link is up and we no
3236 * longer need to check for link */
3237 mac->get_link_status = FALSE;
3245 igbvf_dev_configure(struct rte_eth_dev *dev)
3247 struct rte_eth_conf* conf = &dev->data->dev_conf;
3249 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3250 dev->data->port_id);
3252 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3253 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3256 * VF has no ability to enable/disable HW CRC
3257 * Keep the persistent behavior the same as Host PF
3259 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3260 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3261 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3262 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3265 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3266 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3267 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3275 igbvf_dev_start(struct rte_eth_dev *dev)
3277 struct e1000_hw *hw =
3278 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3279 struct e1000_adapter *adapter =
3280 E1000_DEV_PRIVATE(dev->data->dev_private);
3281 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3282 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3284 uint32_t intr_vector = 0;
3286 PMD_INIT_FUNC_TRACE();
3288 hw->mac.ops.reset_hw(hw);
3289 adapter->stopped = 0;
3292 igbvf_set_vfta_all(dev,1);
3294 eth_igbvf_tx_init(dev);
3296 /* This can fail when allocating mbufs for descriptor rings */
3297 ret = eth_igbvf_rx_init(dev);
3299 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3300 igb_dev_clear_queues(dev);
3304 /* check and configure queue intr-vector mapping */
3305 if (rte_intr_cap_multiple(intr_handle) &&
3306 dev->data->dev_conf.intr_conf.rxq) {
3307 intr_vector = dev->data->nb_rx_queues;
3308 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3313 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3314 intr_handle->intr_vec =
3315 rte_zmalloc("intr_vec",
3316 dev->data->nb_rx_queues * sizeof(int), 0);
3317 if (!intr_handle->intr_vec) {
3318 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3319 " intr_vec", dev->data->nb_rx_queues);
3324 eth_igbvf_configure_msix_intr(dev);
3326 /* enable uio/vfio intr/eventfd mapping */
3327 rte_intr_enable(intr_handle);
3329 /* resume enabled intr since hw reset */
3330 igbvf_intr_enable(dev);
3336 igbvf_dev_stop(struct rte_eth_dev *dev)
3338 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3339 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3340 struct e1000_adapter *adapter =
3341 E1000_DEV_PRIVATE(dev->data->dev_private);
3343 if (adapter->stopped)
3346 PMD_INIT_FUNC_TRACE();
3348 igbvf_stop_adapter(dev);
3351 * Clear what we set, but we still keep shadow_vfta to
3352 * restore after device starts
3354 igbvf_set_vfta_all(dev,0);
3356 igb_dev_clear_queues(dev);
3358 /* disable intr eventfd mapping */
3359 rte_intr_disable(intr_handle);
3361 /* Clean datapath event and queue/vec mapping */
3362 rte_intr_efd_disable(intr_handle);
3363 if (intr_handle->intr_vec) {
3364 rte_free(intr_handle->intr_vec);
3365 intr_handle->intr_vec = NULL;
3368 adapter->stopped = true;
3369 dev->data->dev_started = 0;
3375 igbvf_dev_close(struct rte_eth_dev *dev)
3377 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378 struct rte_ether_addr addr;
3379 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3382 PMD_INIT_FUNC_TRACE();
3384 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3389 ret = igbvf_dev_stop(dev);
3393 igb_dev_free_queues(dev);
3396 * reprogram the RAR with a zero mac address,
3397 * to ensure that the VF traffic goes to the PF
3398 * after stop, close and detach of the VF.
3401 memset(&addr, 0, sizeof(addr));
3402 igbvf_default_mac_addr_set(dev, &addr);
3404 rte_intr_callback_unregister(&pci_dev->intr_handle,
3405 eth_igbvf_interrupt_handler,
3412 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3414 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3416 /* Set both unicast and multicast promisc */
3417 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3423 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3425 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3427 /* If in allmulticast mode leave multicast promisc */
3428 if (dev->data->all_multicast == 1)
3429 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3431 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3437 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3439 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3441 /* In promiscuous mode multicast promisc already set */
3442 if (dev->data->promiscuous == 0)
3443 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3449 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3451 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3453 /* In promiscuous mode leave multicast promisc enabled */
3454 if (dev->data->promiscuous == 0)
3455 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3460 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3462 struct e1000_mbx_info *mbx = &hw->mbx;
3466 /* After set vlan, vlan strip will also be enabled in igb driver*/
3467 msgbuf[0] = E1000_VF_SET_VLAN;
3469 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3471 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3473 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3477 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3481 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3482 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3489 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3491 struct e1000_hw *hw =
3492 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3493 struct e1000_vfta * shadow_vfta =
3494 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3495 int i = 0, j = 0, vfta = 0, mask = 1;
3497 for (i = 0; i < IGB_VFTA_SIZE; i++){
3498 vfta = shadow_vfta->vfta[i];
3501 for (j = 0; j < 32; j++){
3504 (uint16_t)((i<<5)+j), on);
3513 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3515 struct e1000_hw *hw =
3516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517 struct e1000_vfta * shadow_vfta =
3518 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3519 uint32_t vid_idx = 0;
3520 uint32_t vid_bit = 0;
3523 PMD_INIT_FUNC_TRACE();
3525 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3526 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3528 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3531 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3532 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3534 /*Save what we set and retore it after device reset*/
3536 shadow_vfta->vfta[vid_idx] |= vid_bit;
3538 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3544 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3546 struct e1000_hw *hw =
3547 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549 /* index is not used by rar_set() */
3550 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3556 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3557 struct rte_eth_rss_reta_entry64 *reta_conf,
3562 uint16_t idx, shift;
3563 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3566 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3567 "(%d) doesn't match the number hardware can supported "
3568 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3572 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3573 idx = i / RTE_RETA_GROUP_SIZE;
3574 shift = i % RTE_RETA_GROUP_SIZE;
3575 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3579 if (mask == IGB_4_BIT_MASK)
3582 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3583 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3584 if (mask & (0x1 << j))
3585 reta |= reta_conf[idx].reta[shift + j] <<
3588 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3590 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3597 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3598 struct rte_eth_rss_reta_entry64 *reta_conf,
3603 uint16_t idx, shift;
3604 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3606 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3607 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3608 "(%d) doesn't match the number hardware can supported "
3609 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3613 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3614 idx = i / RTE_RETA_GROUP_SIZE;
3615 shift = i % RTE_RETA_GROUP_SIZE;
3616 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3620 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3621 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3622 if (mask & (0x1 << j))
3623 reta_conf[idx].reta[shift + j] =
3624 ((reta >> (CHAR_BIT * j)) &
3633 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3634 struct rte_eth_syn_filter *filter,
3637 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638 struct e1000_filter_info *filter_info =
3639 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3640 uint32_t synqf, rfctl;
3642 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3645 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3648 if (synqf & E1000_SYN_FILTER_ENABLE)
3651 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3652 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3654 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3655 if (filter->hig_pri)
3656 rfctl |= E1000_RFCTL_SYNQFP;
3658 rfctl &= ~E1000_RFCTL_SYNQFP;
3660 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3662 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3667 filter_info->syn_info = synqf;
3668 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3669 E1000_WRITE_FLUSH(hw);
3674 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3675 struct rte_eth_syn_filter *filter)
3677 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3678 uint32_t synqf, rfctl;
3680 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3681 if (synqf & E1000_SYN_FILTER_ENABLE) {
3682 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3683 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3684 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3685 E1000_SYN_FILTER_QUEUE_SHIFT);
3693 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3694 enum rte_filter_op filter_op,
3697 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3700 MAC_TYPE_FILTER_SUP(hw->mac.type);
3702 if (filter_op == RTE_ETH_FILTER_NOP)
3706 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3711 switch (filter_op) {
3712 case RTE_ETH_FILTER_ADD:
3713 ret = eth_igb_syn_filter_set(dev,
3714 (struct rte_eth_syn_filter *)arg,
3717 case RTE_ETH_FILTER_DELETE:
3718 ret = eth_igb_syn_filter_set(dev,
3719 (struct rte_eth_syn_filter *)arg,
3722 case RTE_ETH_FILTER_GET:
3723 ret = eth_igb_syn_filter_get(dev,
3724 (struct rte_eth_syn_filter *)arg);
3727 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3735 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3737 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3738 struct e1000_2tuple_filter_info *filter_info)
3740 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3742 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3743 return -EINVAL; /* filter index is out of range. */
3744 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3745 return -EINVAL; /* flags is invalid. */
3747 switch (filter->dst_port_mask) {
3749 filter_info->dst_port_mask = 0;
3750 filter_info->dst_port = filter->dst_port;
3753 filter_info->dst_port_mask = 1;
3756 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3760 switch (filter->proto_mask) {
3762 filter_info->proto_mask = 0;
3763 filter_info->proto = filter->proto;
3766 filter_info->proto_mask = 1;
3769 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3773 filter_info->priority = (uint8_t)filter->priority;
3774 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3775 filter_info->tcp_flags = filter->tcp_flags;
3777 filter_info->tcp_flags = 0;
3782 static inline struct e1000_2tuple_filter *
3783 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3784 struct e1000_2tuple_filter_info *key)
3786 struct e1000_2tuple_filter *it;
3788 TAILQ_FOREACH(it, filter_list, entries) {
3789 if (memcmp(key, &it->filter_info,
3790 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3797 /* inject a igb 2tuple filter to HW */
3799 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3800 struct e1000_2tuple_filter *filter)
3802 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3803 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3804 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3808 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3809 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3810 imir |= E1000_IMIR_PORT_BP;
3812 imir &= ~E1000_IMIR_PORT_BP;
3814 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3816 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3817 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3818 ttqf |= (uint32_t)(filter->filter_info.proto &
3819 E1000_TTQF_PROTOCOL_MASK);
3820 if (filter->filter_info.proto_mask == 0)
3821 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3823 /* tcp flags bits setting. */
3824 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3825 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3826 imir_ext |= E1000_IMIREXT_CTRL_URG;
3827 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3828 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3829 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3830 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3831 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3832 imir_ext |= E1000_IMIREXT_CTRL_RST;
3833 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3834 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3835 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3836 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3838 imir_ext |= E1000_IMIREXT_CTRL_BP;
3840 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3841 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3842 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3846 * igb_add_2tuple_filter - add a 2tuple filter
3849 * dev: Pointer to struct rte_eth_dev.
3850 * ntuple_filter: ponter to the filter that will be added.
3853 * - On success, zero.
3854 * - On failure, a negative value.
3857 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3858 struct rte_eth_ntuple_filter *ntuple_filter)
3860 struct e1000_filter_info *filter_info =
3861 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3862 struct e1000_2tuple_filter *filter;
3865 filter = rte_zmalloc("e1000_2tuple_filter",
3866 sizeof(struct e1000_2tuple_filter), 0);
3870 ret = ntuple_filter_to_2tuple(ntuple_filter,
3871 &filter->filter_info);
3876 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3877 &filter->filter_info) != NULL) {
3878 PMD_DRV_LOG(ERR, "filter exists.");
3882 filter->queue = ntuple_filter->queue;
3885 * look for an unused 2tuple filter index,
3886 * and insert the filter to list.
3888 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3889 if (!(filter_info->twotuple_mask & (1 << i))) {
3890 filter_info->twotuple_mask |= 1 << i;
3892 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3898 if (i >= E1000_MAX_TTQF_FILTERS) {
3899 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3904 igb_inject_2uple_filter(dev, filter);
3909 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3910 struct e1000_2tuple_filter *filter)
3912 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3913 struct e1000_filter_info *filter_info =
3914 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3916 filter_info->twotuple_mask &= ~(1 << filter->index);
3917 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3920 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3921 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3922 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3927 * igb_remove_2tuple_filter - remove a 2tuple filter
3930 * dev: Pointer to struct rte_eth_dev.
3931 * ntuple_filter: ponter to the filter that will be removed.
3934 * - On success, zero.
3935 * - On failure, a negative value.
3938 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3939 struct rte_eth_ntuple_filter *ntuple_filter)
3941 struct e1000_filter_info *filter_info =
3942 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3943 struct e1000_2tuple_filter_info filter_2tuple;
3944 struct e1000_2tuple_filter *filter;
3947 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3948 ret = ntuple_filter_to_2tuple(ntuple_filter,
3953 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3955 if (filter == NULL) {
3956 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3960 igb_delete_2tuple_filter(dev, filter);
3965 /* inject a igb flex filter to HW */
3967 igb_inject_flex_filter(struct rte_eth_dev *dev,
3968 struct e1000_flex_filter *filter)
3970 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3971 uint32_t wufc, queueing;
3975 wufc = E1000_READ_REG(hw, E1000_WUFC);
3976 if (filter->index < E1000_MAX_FHFT)
3977 reg_off = E1000_FHFT(filter->index);
3979 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3981 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3982 (E1000_WUFC_FLX0 << filter->index));
3983 queueing = filter->filter_info.len |
3984 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3985 (filter->filter_info.priority <<
3986 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3987 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3990 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3991 E1000_WRITE_REG(hw, reg_off,
3992 filter->filter_info.dwords[j]);
3993 reg_off += sizeof(uint32_t);
3994 E1000_WRITE_REG(hw, reg_off,
3995 filter->filter_info.dwords[++j]);
3996 reg_off += sizeof(uint32_t);
3997 E1000_WRITE_REG(hw, reg_off,
3998 (uint32_t)filter->filter_info.mask[i]);
3999 reg_off += sizeof(uint32_t) * 2;
4004 static inline struct e1000_flex_filter *
4005 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4006 struct e1000_flex_filter_info *key)
4008 struct e1000_flex_filter *it;
4010 TAILQ_FOREACH(it, filter_list, entries) {
4011 if (memcmp(key, &it->filter_info,
4012 sizeof(struct e1000_flex_filter_info)) == 0)
4019 /* remove a flex byte filter
4021 * dev: Pointer to struct rte_eth_dev.
4022 * filter: the pointer of the filter will be removed.
4025 igb_remove_flex_filter(struct rte_eth_dev *dev,
4026 struct e1000_flex_filter *filter)
4028 struct e1000_filter_info *filter_info =
4029 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4030 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4034 wufc = E1000_READ_REG(hw, E1000_WUFC);
4035 if (filter->index < E1000_MAX_FHFT)
4036 reg_off = E1000_FHFT(filter->index);
4038 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4040 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4041 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4043 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4044 (~(E1000_WUFC_FLX0 << filter->index)));
4046 filter_info->flex_mask &= ~(1 << filter->index);
4047 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4052 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4053 struct rte_eth_flex_filter *filter,
4056 struct e1000_filter_info *filter_info =
4057 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4058 struct e1000_flex_filter *flex_filter, *it;
4062 flex_filter = rte_zmalloc("e1000_flex_filter",
4063 sizeof(struct e1000_flex_filter), 0);
4064 if (flex_filter == NULL)
4067 flex_filter->filter_info.len = filter->len;
4068 flex_filter->filter_info.priority = filter->priority;
4069 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4070 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4072 /* reverse bits in flex filter's mask*/
4073 for (shift = 0; shift < CHAR_BIT; shift++) {
4074 if (filter->mask[i] & (0x01 << shift))
4075 mask |= (0x80 >> shift);
4077 flex_filter->filter_info.mask[i] = mask;
4080 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4081 &flex_filter->filter_info);
4082 if (it == NULL && !add) {
4083 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4084 rte_free(flex_filter);
4087 if (it != NULL && add) {
4088 PMD_DRV_LOG(ERR, "filter exists.");
4089 rte_free(flex_filter);
4094 flex_filter->queue = filter->queue;
4096 * look for an unused flex filter index
4097 * and insert the filter into the list.
4099 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4100 if (!(filter_info->flex_mask & (1 << i))) {
4101 filter_info->flex_mask |= 1 << i;
4102 flex_filter->index = i;
4103 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4109 if (i >= E1000_MAX_FLEX_FILTERS) {
4110 PMD_DRV_LOG(ERR, "flex filters are full.");
4111 rte_free(flex_filter);
4115 igb_inject_flex_filter(dev, flex_filter);
4118 igb_remove_flex_filter(dev, it);
4119 rte_free(flex_filter);
4125 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4127 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4128 struct e1000_5tuple_filter_info *filter_info)
4130 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4132 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4133 return -EINVAL; /* filter index is out of range. */
4134 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4135 return -EINVAL; /* flags is invalid. */
4137 switch (filter->dst_ip_mask) {
4139 filter_info->dst_ip_mask = 0;
4140 filter_info->dst_ip = filter->dst_ip;
4143 filter_info->dst_ip_mask = 1;
4146 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4150 switch (filter->src_ip_mask) {
4152 filter_info->src_ip_mask = 0;
4153 filter_info->src_ip = filter->src_ip;
4156 filter_info->src_ip_mask = 1;
4159 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4163 switch (filter->dst_port_mask) {
4165 filter_info->dst_port_mask = 0;
4166 filter_info->dst_port = filter->dst_port;
4169 filter_info->dst_port_mask = 1;
4172 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4176 switch (filter->src_port_mask) {
4178 filter_info->src_port_mask = 0;
4179 filter_info->src_port = filter->src_port;
4182 filter_info->src_port_mask = 1;
4185 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4189 switch (filter->proto_mask) {
4191 filter_info->proto_mask = 0;
4192 filter_info->proto = filter->proto;
4195 filter_info->proto_mask = 1;
4198 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4202 filter_info->priority = (uint8_t)filter->priority;
4203 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4204 filter_info->tcp_flags = filter->tcp_flags;
4206 filter_info->tcp_flags = 0;
4211 static inline struct e1000_5tuple_filter *
4212 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4213 struct e1000_5tuple_filter_info *key)
4215 struct e1000_5tuple_filter *it;
4217 TAILQ_FOREACH(it, filter_list, entries) {
4218 if (memcmp(key, &it->filter_info,
4219 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4226 /* inject a igb 5-tuple filter to HW */
4228 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4229 struct e1000_5tuple_filter *filter)
4231 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4232 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4233 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4237 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4238 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4239 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4240 if (filter->filter_info.dst_ip_mask == 0)
4241 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4242 if (filter->filter_info.src_port_mask == 0)
4243 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4244 if (filter->filter_info.proto_mask == 0)
4245 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4246 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4247 E1000_FTQF_QUEUE_MASK;
4248 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4249 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4250 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4251 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4253 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4254 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4256 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4257 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4258 imir |= E1000_IMIR_PORT_BP;
4260 imir &= ~E1000_IMIR_PORT_BP;
4261 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4263 /* tcp flags bits setting. */
4264 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4265 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4266 imir_ext |= E1000_IMIREXT_CTRL_URG;
4267 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4268 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4269 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4270 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4271 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4272 imir_ext |= E1000_IMIREXT_CTRL_RST;
4273 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4274 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4275 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4276 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4278 imir_ext |= E1000_IMIREXT_CTRL_BP;
4280 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4281 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4285 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4288 * dev: Pointer to struct rte_eth_dev.
4289 * ntuple_filter: ponter to the filter that will be added.
4292 * - On success, zero.
4293 * - On failure, a negative value.
4296 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4297 struct rte_eth_ntuple_filter *ntuple_filter)
4299 struct e1000_filter_info *filter_info =
4300 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4301 struct e1000_5tuple_filter *filter;
4305 filter = rte_zmalloc("e1000_5tuple_filter",
4306 sizeof(struct e1000_5tuple_filter), 0);
4310 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4311 &filter->filter_info);
4317 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4318 &filter->filter_info) != NULL) {
4319 PMD_DRV_LOG(ERR, "filter exists.");
4323 filter->queue = ntuple_filter->queue;
4326 * look for an unused 5tuple filter index,
4327 * and insert the filter to list.
4329 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4330 if (!(filter_info->fivetuple_mask & (1 << i))) {
4331 filter_info->fivetuple_mask |= 1 << i;
4333 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4339 if (i >= E1000_MAX_FTQF_FILTERS) {
4340 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4345 igb_inject_5tuple_filter_82576(dev, filter);
4350 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4351 struct e1000_5tuple_filter *filter)
4353 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4354 struct e1000_filter_info *filter_info =
4355 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4357 filter_info->fivetuple_mask &= ~(1 << filter->index);
4358 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4361 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4362 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4363 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4364 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4365 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4366 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4367 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4372 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4375 * dev: Pointer to struct rte_eth_dev.
4376 * ntuple_filter: ponter to the filter that will be removed.
4379 * - On success, zero.
4380 * - On failure, a negative value.
4383 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4384 struct rte_eth_ntuple_filter *ntuple_filter)
4386 struct e1000_filter_info *filter_info =
4387 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4388 struct e1000_5tuple_filter_info filter_5tuple;
4389 struct e1000_5tuple_filter *filter;
4392 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4393 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4398 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4400 if (filter == NULL) {
4401 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4405 igb_delete_5tuple_filter_82576(dev, filter);
4411 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4414 struct e1000_hw *hw;
4415 struct rte_eth_dev_info dev_info;
4416 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4419 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421 #ifdef RTE_LIBRTE_82571_SUPPORT
4422 /* XXX: not bigger than max_rx_pktlen */
4423 if (hw->mac.type == e1000_82571)
4426 ret = eth_igb_infos_get(dev, &dev_info);
4430 /* check that mtu is within the allowed range */
4431 if (mtu < RTE_ETHER_MIN_MTU ||
4432 frame_size > dev_info.max_rx_pktlen)
4435 /* refuse mtu that requires the support of scattered packets when this
4436 * feature has not been enabled before. */
4437 if (!dev->data->scattered_rx &&
4438 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4441 rctl = E1000_READ_REG(hw, E1000_RCTL);
4443 /* switch to jumbo mode if needed */
4444 if (frame_size > RTE_ETHER_MAX_LEN) {
4445 dev->data->dev_conf.rxmode.offloads |=
4446 DEV_RX_OFFLOAD_JUMBO_FRAME;
4447 rctl |= E1000_RCTL_LPE;
4449 dev->data->dev_conf.rxmode.offloads &=
4450 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4451 rctl &= ~E1000_RCTL_LPE;
4453 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4455 /* update max frame size */
4456 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4458 E1000_WRITE_REG(hw, E1000_RLPML,
4459 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4465 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4468 * dev: Pointer to struct rte_eth_dev.
4469 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4470 * add: if true, add filter, if false, remove filter
4473 * - On success, zero.
4474 * - On failure, a negative value.
4477 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4478 struct rte_eth_ntuple_filter *ntuple_filter,
4481 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484 switch (ntuple_filter->flags) {
4485 case RTE_5TUPLE_FLAGS:
4486 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4487 if (hw->mac.type != e1000_82576)
4490 ret = igb_add_5tuple_filter_82576(dev,
4493 ret = igb_remove_5tuple_filter_82576(dev,
4496 case RTE_2TUPLE_FLAGS:
4497 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4498 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4499 hw->mac.type != e1000_i210 &&
4500 hw->mac.type != e1000_i211)
4503 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4505 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4516 * igb_get_ntuple_filter - get a ntuple filter
4519 * dev: Pointer to struct rte_eth_dev.
4520 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4523 * - On success, zero.
4524 * - On failure, a negative value.
4527 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4528 struct rte_eth_ntuple_filter *ntuple_filter)
4530 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4531 struct e1000_filter_info *filter_info =
4532 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4533 struct e1000_5tuple_filter_info filter_5tuple;
4534 struct e1000_2tuple_filter_info filter_2tuple;
4535 struct e1000_5tuple_filter *p_5tuple_filter;
4536 struct e1000_2tuple_filter *p_2tuple_filter;
4539 switch (ntuple_filter->flags) {
4540 case RTE_5TUPLE_FLAGS:
4541 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4542 if (hw->mac.type != e1000_82576)
4544 memset(&filter_5tuple,
4546 sizeof(struct e1000_5tuple_filter_info));
4547 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4551 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4552 &filter_info->fivetuple_list,
4554 if (p_5tuple_filter == NULL) {
4555 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4558 ntuple_filter->queue = p_5tuple_filter->queue;
4560 case RTE_2TUPLE_FLAGS:
4561 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4562 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4564 memset(&filter_2tuple,
4566 sizeof(struct e1000_2tuple_filter_info));
4567 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4570 p_2tuple_filter = igb_2tuple_filter_lookup(
4571 &filter_info->twotuple_list,
4573 if (p_2tuple_filter == NULL) {
4574 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4577 ntuple_filter->queue = p_2tuple_filter->queue;
4588 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4589 * @dev: pointer to rte_eth_dev structure
4590 * @filter_op:operation will be taken.
4591 * @arg: a pointer to specific structure corresponding to the filter_op
4594 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4595 enum rte_filter_op filter_op,
4598 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4601 MAC_TYPE_FILTER_SUP(hw->mac.type);
4603 if (filter_op == RTE_ETH_FILTER_NOP)
4607 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4612 switch (filter_op) {
4613 case RTE_ETH_FILTER_ADD:
4614 ret = igb_add_del_ntuple_filter(dev,
4615 (struct rte_eth_ntuple_filter *)arg,
4618 case RTE_ETH_FILTER_DELETE:
4619 ret = igb_add_del_ntuple_filter(dev,
4620 (struct rte_eth_ntuple_filter *)arg,
4623 case RTE_ETH_FILTER_GET:
4624 ret = igb_get_ntuple_filter(dev,
4625 (struct rte_eth_ntuple_filter *)arg);
4628 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4636 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4641 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4642 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4643 (filter_info->ethertype_mask & (1 << i)))
4650 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4651 uint16_t ethertype, uint32_t etqf)
4655 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4656 if (!(filter_info->ethertype_mask & (1 << i))) {
4657 filter_info->ethertype_mask |= 1 << i;
4658 filter_info->ethertype_filters[i].ethertype = ethertype;
4659 filter_info->ethertype_filters[i].etqf = etqf;
4667 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4670 if (idx >= E1000_MAX_ETQF_FILTERS)
4672 filter_info->ethertype_mask &= ~(1 << idx);
4673 filter_info->ethertype_filters[idx].ethertype = 0;
4674 filter_info->ethertype_filters[idx].etqf = 0;
4680 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4681 struct rte_eth_ethertype_filter *filter,
4684 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685 struct e1000_filter_info *filter_info =
4686 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4690 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4691 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4692 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4693 " ethertype filter.", filter->ether_type);
4697 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4698 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4701 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4702 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4706 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4707 if (ret >= 0 && add) {
4708 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4709 filter->ether_type);
4712 if (ret < 0 && !add) {
4713 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4714 filter->ether_type);
4719 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4720 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4721 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4722 ret = igb_ethertype_filter_insert(filter_info,
4723 filter->ether_type, etqf);
4725 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4729 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4733 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4734 E1000_WRITE_FLUSH(hw);
4740 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4741 enum rte_filter_type filter_type,
4742 enum rte_filter_op filter_op,
4747 switch (filter_type) {
4748 case RTE_ETH_FILTER_NTUPLE:
4749 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4751 case RTE_ETH_FILTER_SYN:
4752 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4754 case RTE_ETH_FILTER_GENERIC:
4755 if (filter_op != RTE_ETH_FILTER_GET)
4757 *(const void **)arg = &igb_flow_ops;
4760 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4769 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4770 struct rte_ether_addr *mc_addr_set,
4771 uint32_t nb_mc_addr)
4773 struct e1000_hw *hw;
4775 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4776 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4781 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4783 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784 uint64_t systime_cycles;
4786 switch (hw->mac.type) {
4790 * Need to read System Time Residue Register to be able
4791 * to read the other two registers.
4793 E1000_READ_REG(hw, E1000_SYSTIMR);
4794 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4795 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4796 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4803 * Need to read System Time Residue Register to be able
4804 * to read the other two registers.
4806 E1000_READ_REG(hw, E1000_SYSTIMR);
4807 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4808 /* Only the 8 LSB are valid. */
4809 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4813 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4814 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4819 return systime_cycles;
4823 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4825 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4826 uint64_t rx_tstamp_cycles;
4828 switch (hw->mac.type) {
4831 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4832 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4833 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4839 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4840 /* Only the 8 LSB are valid. */
4841 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4845 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4846 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4851 return rx_tstamp_cycles;
4855 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4857 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4858 uint64_t tx_tstamp_cycles;
4860 switch (hw->mac.type) {
4863 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4864 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4865 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4871 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4872 /* Only the 8 LSB are valid. */
4873 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4877 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4878 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4883 return tx_tstamp_cycles;
4887 igb_start_timecounters(struct rte_eth_dev *dev)
4889 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4890 struct e1000_adapter *adapter = dev->data->dev_private;
4891 uint32_t incval = 1;
4893 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4895 switch (hw->mac.type) {
4899 /* 32 LSB bits + 8 MSB bits = 40 bits */
4900 mask = (1ULL << 40) - 1;
4905 * Start incrementing the register
4906 * used to timestamp PTP packets.
4908 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4911 incval = E1000_INCVALUE_82576;
4912 shift = IGB_82576_TSYNC_SHIFT;
4913 E1000_WRITE_REG(hw, E1000_TIMINCA,
4914 E1000_INCPERIOD_82576 | incval);
4921 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4922 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4923 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4925 adapter->systime_tc.cc_mask = mask;
4926 adapter->systime_tc.cc_shift = shift;
4927 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4929 adapter->rx_tstamp_tc.cc_mask = mask;
4930 adapter->rx_tstamp_tc.cc_shift = shift;
4931 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4933 adapter->tx_tstamp_tc.cc_mask = mask;
4934 adapter->tx_tstamp_tc.cc_shift = shift;
4935 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4939 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4941 struct e1000_adapter *adapter = dev->data->dev_private;
4943 adapter->systime_tc.nsec += delta;
4944 adapter->rx_tstamp_tc.nsec += delta;
4945 adapter->tx_tstamp_tc.nsec += delta;
4951 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4954 struct e1000_adapter *adapter = dev->data->dev_private;
4956 ns = rte_timespec_to_ns(ts);
4958 /* Set the timecounters to a new value. */
4959 adapter->systime_tc.nsec = ns;
4960 adapter->rx_tstamp_tc.nsec = ns;
4961 adapter->tx_tstamp_tc.nsec = ns;
4967 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4969 uint64_t ns, systime_cycles;
4970 struct e1000_adapter *adapter = dev->data->dev_private;
4972 systime_cycles = igb_read_systime_cyclecounter(dev);
4973 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4974 *ts = rte_ns_to_timespec(ns);
4980 igb_timesync_enable(struct rte_eth_dev *dev)
4982 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4986 /* Stop the timesync system time. */
4987 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4988 /* Reset the timesync system time value. */
4989 switch (hw->mac.type) {
4995 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4998 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4999 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5002 /* Not supported. */
5006 /* Enable system time for it isn't on by default. */
5007 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5008 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5009 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5011 igb_start_timecounters(dev);
5013 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5014 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5015 (RTE_ETHER_TYPE_1588 |
5016 E1000_ETQF_FILTER_ENABLE |
5019 /* Enable timestamping of received PTP packets. */
5020 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5021 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5022 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5024 /* Enable Timestamping of transmitted PTP packets. */
5025 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5026 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5027 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5033 igb_timesync_disable(struct rte_eth_dev *dev)
5035 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5038 /* Disable timestamping of transmitted PTP packets. */
5039 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5040 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5041 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5043 /* Disable timestamping of received PTP packets. */
5044 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5045 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5046 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5048 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5049 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5051 /* Stop incrementating the System Time registers. */
5052 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5058 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5059 struct timespec *timestamp,
5060 uint32_t flags __rte_unused)
5062 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5063 struct e1000_adapter *adapter = dev->data->dev_private;
5064 uint32_t tsync_rxctl;
5065 uint64_t rx_tstamp_cycles;
5068 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5069 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5072 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5073 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5074 *timestamp = rte_ns_to_timespec(ns);
5080 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5081 struct timespec *timestamp)
5083 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084 struct e1000_adapter *adapter = dev->data->dev_private;
5085 uint32_t tsync_txctl;
5086 uint64_t tx_tstamp_cycles;
5089 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5090 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5093 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5094 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5095 *timestamp = rte_ns_to_timespec(ns);
5101 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5105 const struct reg_info *reg_group;
5107 while ((reg_group = igb_regs[g_ind++]))
5108 count += igb_reg_group_count(reg_group);
5114 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5118 const struct reg_info *reg_group;
5120 while ((reg_group = igbvf_regs[g_ind++]))
5121 count += igb_reg_group_count(reg_group);
5127 eth_igb_get_regs(struct rte_eth_dev *dev,
5128 struct rte_dev_reg_info *regs)
5130 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131 uint32_t *data = regs->data;
5134 const struct reg_info *reg_group;
5137 regs->length = eth_igb_get_reg_length(dev);
5138 regs->width = sizeof(uint32_t);
5142 /* Support only full register dump */
5143 if ((regs->length == 0) ||
5144 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5145 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5147 while ((reg_group = igb_regs[g_ind++]))
5148 count += igb_read_regs_group(dev, &data[count],
5157 igbvf_get_regs(struct rte_eth_dev *dev,
5158 struct rte_dev_reg_info *regs)
5160 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5161 uint32_t *data = regs->data;
5164 const struct reg_info *reg_group;
5167 regs->length = igbvf_get_reg_length(dev);
5168 regs->width = sizeof(uint32_t);
5172 /* Support only full register dump */
5173 if ((regs->length == 0) ||
5174 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5175 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5177 while ((reg_group = igbvf_regs[g_ind++]))
5178 count += igb_read_regs_group(dev, &data[count],
5187 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5189 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5191 /* Return unit is byte count */
5192 return hw->nvm.word_size * 2;
5196 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5197 struct rte_dev_eeprom_info *in_eeprom)
5199 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200 struct e1000_nvm_info *nvm = &hw->nvm;
5201 uint16_t *data = in_eeprom->data;
5204 first = in_eeprom->offset >> 1;
5205 length = in_eeprom->length >> 1;
5206 if ((first >= hw->nvm.word_size) ||
5207 ((first + length) >= hw->nvm.word_size))
5210 in_eeprom->magic = hw->vendor_id |
5211 ((uint32_t)hw->device_id << 16);
5213 if ((nvm->ops.read) == NULL)
5216 return nvm->ops.read(hw, first, length, data);
5220 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5221 struct rte_dev_eeprom_info *in_eeprom)
5223 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5224 struct e1000_nvm_info *nvm = &hw->nvm;
5225 uint16_t *data = in_eeprom->data;
5228 first = in_eeprom->offset >> 1;
5229 length = in_eeprom->length >> 1;
5230 if ((first >= hw->nvm.word_size) ||
5231 ((first + length) >= hw->nvm.word_size))
5234 in_eeprom->magic = (uint32_t)hw->vendor_id |
5235 ((uint32_t)hw->device_id << 16);
5237 if ((nvm->ops.write) == NULL)
5239 return nvm->ops.write(hw, first, length, data);
5243 eth_igb_get_module_info(struct rte_eth_dev *dev,
5244 struct rte_eth_dev_module_info *modinfo)
5246 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5248 uint32_t status = 0;
5249 uint16_t sff8472_rev, addr_mode;
5250 bool page_swap = false;
5252 if (hw->phy.media_type == e1000_media_type_copper ||
5253 hw->phy.media_type == e1000_media_type_unknown)
5256 /* Check whether we support SFF-8472 or not */
5257 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5261 /* addressing mode is not supported */
5262 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5266 /* addressing mode is not supported */
5267 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5269 "Address change required to access page 0xA2, "
5270 "but not supported. Please report the module "
5271 "type to the driver maintainers.\n");
5275 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5276 /* We have an SFP, but it does not support SFF-8472 */
5277 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5278 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5280 /* We have an SFP which supports a revision of SFF-8472 */
5281 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5282 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5289 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5290 struct rte_dev_eeprom_info *info)
5292 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5294 uint32_t status = 0;
5295 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5296 u16 first_word, last_word;
5299 if (info->length == 0)
5302 first_word = info->offset >> 1;
5303 last_word = (info->offset + info->length - 1) >> 1;
5305 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5306 for (i = 0; i < last_word - first_word + 1; i++) {
5307 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5310 /* Error occurred while reading module */
5314 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5317 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5323 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5325 struct e1000_hw *hw =
5326 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5327 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5328 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5329 uint32_t vec = E1000_MISC_VEC_ID;
5331 if (rte_intr_allow_others(intr_handle))
5332 vec = E1000_RX_VEC_START;
5334 uint32_t mask = 1 << (queue_id + vec);
5336 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5337 E1000_WRITE_FLUSH(hw);
5343 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5345 struct e1000_hw *hw =
5346 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5347 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5348 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5349 uint32_t vec = E1000_MISC_VEC_ID;
5351 if (rte_intr_allow_others(intr_handle))
5352 vec = E1000_RX_VEC_START;
5354 uint32_t mask = 1 << (queue_id + vec);
5357 regval = E1000_READ_REG(hw, E1000_EIMS);
5358 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5359 E1000_WRITE_FLUSH(hw);
5361 rte_intr_ack(intr_handle);
5367 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5368 uint8_t index, uint8_t offset)
5370 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5373 val &= ~((uint32_t)0xFF << offset);
5375 /* write vector and valid bit */
5376 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5378 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5382 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5383 uint8_t queue, uint8_t msix_vector)
5387 if (hw->mac.type == e1000_82575) {
5389 tmp = E1000_EICR_RX_QUEUE0 << queue;
5390 else if (direction == 1)
5391 tmp = E1000_EICR_TX_QUEUE0 << queue;
5392 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5393 } else if (hw->mac.type == e1000_82576) {
5394 if ((direction == 0) || (direction == 1))
5395 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5396 ((queue & 0x8) << 1) +
5398 } else if ((hw->mac.type == e1000_82580) ||
5399 (hw->mac.type == e1000_i350) ||
5400 (hw->mac.type == e1000_i354) ||
5401 (hw->mac.type == e1000_i210) ||
5402 (hw->mac.type == e1000_i211)) {
5403 if ((direction == 0) || (direction == 1))
5404 eth_igb_write_ivar(hw, msix_vector,
5406 ((queue & 0x1) << 4) +
5411 /* Sets up the hardware to generate MSI-X interrupts properly
5413 * board private structure
5416 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5419 uint32_t tmpval, regval, intr_mask;
5420 struct e1000_hw *hw =
5421 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5422 uint32_t vec = E1000_MISC_VEC_ID;
5423 uint32_t base = E1000_MISC_VEC_ID;
5424 uint32_t misc_shift = 0;
5425 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5426 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5428 /* won't configure msix register if no mapping is done
5429 * between intr vector and event fd
5431 if (!rte_intr_dp_is_en(intr_handle))
5434 if (rte_intr_allow_others(intr_handle)) {
5435 vec = base = E1000_RX_VEC_START;
5439 /* set interrupt vector for other causes */
5440 if (hw->mac.type == e1000_82575) {
5441 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5442 /* enable MSI-X PBA support */
5443 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5445 /* Auto-Mask interrupts upon ICR read */
5446 tmpval |= E1000_CTRL_EXT_EIAME;
5447 tmpval |= E1000_CTRL_EXT_IRCA;
5449 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5451 /* enable msix_other interrupt */
5452 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5453 regval = E1000_READ_REG(hw, E1000_EIAC);
5454 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5455 regval = E1000_READ_REG(hw, E1000_EIAM);
5456 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5457 } else if ((hw->mac.type == e1000_82576) ||
5458 (hw->mac.type == e1000_82580) ||
5459 (hw->mac.type == e1000_i350) ||
5460 (hw->mac.type == e1000_i354) ||
5461 (hw->mac.type == e1000_i210) ||
5462 (hw->mac.type == e1000_i211)) {
5463 /* turn on MSI-X capability first */
5464 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5465 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5467 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5470 if (dev->data->dev_conf.intr_conf.lsc != 0)
5471 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5473 regval = E1000_READ_REG(hw, E1000_EIAC);
5474 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5476 /* enable msix_other interrupt */
5477 regval = E1000_READ_REG(hw, E1000_EIMS);
5478 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5479 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5480 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5483 /* use EIAM to auto-mask when MSI-X interrupt
5484 * is asserted, this saves a register write for every interrupt
5486 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5489 if (dev->data->dev_conf.intr_conf.lsc != 0)
5490 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5492 regval = E1000_READ_REG(hw, E1000_EIAM);
5493 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5495 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5496 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5497 intr_handle->intr_vec[queue_id] = vec;
5498 if (vec < base + intr_handle->nb_efd - 1)
5502 E1000_WRITE_FLUSH(hw);
5505 /* restore n-tuple filter */
5507 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5509 struct e1000_filter_info *filter_info =
5510 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5511 struct e1000_5tuple_filter *p_5tuple;
5512 struct e1000_2tuple_filter *p_2tuple;
5514 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5515 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5518 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5519 igb_inject_2uple_filter(dev, p_2tuple);
5523 /* restore SYN filter */
5525 igb_syn_filter_restore(struct rte_eth_dev *dev)
5527 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528 struct e1000_filter_info *filter_info =
5529 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5532 synqf = filter_info->syn_info;
5534 if (synqf & E1000_SYN_FILTER_ENABLE) {
5535 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5536 E1000_WRITE_FLUSH(hw);
5540 /* restore ethernet type filter */
5542 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5544 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5545 struct e1000_filter_info *filter_info =
5546 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5549 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5550 if (filter_info->ethertype_mask & (1 << i)) {
5551 E1000_WRITE_REG(hw, E1000_ETQF(i),
5552 filter_info->ethertype_filters[i].etqf);
5553 E1000_WRITE_FLUSH(hw);
5558 /* restore flex byte filter */
5560 igb_flex_filter_restore(struct rte_eth_dev *dev)
5562 struct e1000_filter_info *filter_info =
5563 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5564 struct e1000_flex_filter *flex_filter;
5566 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5567 igb_inject_flex_filter(dev, flex_filter);
5571 /* restore rss filter */
5573 igb_rss_filter_restore(struct rte_eth_dev *dev)
5575 struct e1000_filter_info *filter_info =
5576 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5578 if (filter_info->rss_info.conf.queue_num)
5579 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5582 /* restore all types filter */
5584 igb_filter_restore(struct rte_eth_dev *dev)
5586 igb_ntuple_filter_restore(dev);
5587 igb_ethertype_filter_restore(dev);
5588 igb_syn_filter_restore(dev);
5589 igb_flex_filter_restore(dev);
5590 igb_rss_filter_restore(dev);
5595 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5596 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5597 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5598 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5599 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5600 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5602 /* see e1000_logs.c */
5603 RTE_INIT(e1000_init_log)
5605 e1000_igb_init_log();