drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static int  eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static int eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static int  eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static int  eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static int  eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static int  eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static int igbvf_dev_close(struct rte_eth_dev *dev);
 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter);
 200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 201                         enum rte_filter_op filter_op,
 202                         void *arg);
 203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *filter);
 209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 213                      enum rte_filter_type filter_type,
 214                      enum rte_filter_op filter_op,
 215                      void *arg);
 216 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 217 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 218                 struct rte_dev_reg_info *regs);
 219 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 220 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 221                 struct rte_dev_eeprom_info *eeprom);
 222 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 223                 struct rte_dev_eeprom_info *eeprom);
 224 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 225                                    struct rte_eth_dev_module_info *modinfo);
 226 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 227                                      struct rte_dev_eeprom_info *info);
 228 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 229                                     struct rte_ether_addr *mc_addr_set,
 230                                     uint32_t nb_mc_addr);
 231 static int igb_timesync_enable(struct rte_eth_dev *dev);
 232 static int igb_timesync_disable(struct rte_eth_dev *dev);
 233 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 234                                           struct timespec *timestamp,
 235                                           uint32_t flags);
 236 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 237                                           struct timespec *timestamp);
 238 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 239 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 240                                   struct timespec *timestamp);
 241 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 242                                    const struct timespec *timestamp);
 243 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 244                                         uint16_t queue_id);
 245 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 246                                          uint16_t queue_id);
 247 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 248                                        uint8_t queue, uint8_t msix_vector);
 249 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 250                                uint8_t index, uint8_t offset);
 251 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 252 static void eth_igbvf_interrupt_handler(void *param);
 253 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 254 static int igb_filter_restore(struct rte_eth_dev *dev);
 255
 256 /*
 257  * Define VF Stats MACRO for Non "cleared on read" register
 258  */
 259 #define UPDATE_VF_STAT(reg, last, cur)            \
 260 {                                                 \
 261         u32 latest = E1000_READ_REG(hw, reg);     \
 262         cur += (latest - last) & UINT_MAX;        \
 263         last = latest;                            \
 264 }
 265
 266 #define IGB_FC_PAUSE_TIME 0x0680
 267 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 268 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 269
 270 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 271
 272 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 273
 274 /*
 275  * The set of PCI devices this driver supports
 276  */
 277 static const struct rte_pci_id pci_id_igb_map[] = {
 278         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 279         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 280         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 281         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 282         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 286
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 290
 291         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 295         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 297
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 302         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 319         { .vendor_id = 0, /* sentinel */ },
 320 };
 321
 322 /*
 323  * The set of PCI devices this driver supports (for 82576&I350 VF)
 324  */
 325 static const struct rte_pci_id pci_id_igbvf_map[] = {
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 330         { .vendor_id = 0, /* sentinel */ },
 331 };
 332
 333 static const struct rte_eth_desc_lim rx_desc_lim = {
 334         .nb_max = E1000_MAX_RING_DESC,
 335         .nb_min = E1000_MIN_RING_DESC,
 336         .nb_align = IGB_RXD_ALIGN,
 337 };
 338
 339 static const struct rte_eth_desc_lim tx_desc_lim = {
 340         .nb_max = E1000_MAX_RING_DESC,
 341         .nb_min = E1000_MIN_RING_DESC,
 342         .nb_align = IGB_RXD_ALIGN,
 343         .nb_seg_max = IGB_TX_MAX_SEG,
 344         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 345 };
 346
 347 static const struct eth_dev_ops eth_igb_ops = {
 348         .dev_configure        = eth_igb_configure,
 349         .dev_start            = eth_igb_start,
 350         .dev_stop             = eth_igb_stop,
 351         .dev_set_link_up      = eth_igb_dev_set_link_up,
 352         .dev_set_link_down    = eth_igb_dev_set_link_down,
 353         .dev_close            = eth_igb_close,
 354         .dev_reset            = eth_igb_reset,
 355         .promiscuous_enable   = eth_igb_promiscuous_enable,
 356         .promiscuous_disable  = eth_igb_promiscuous_disable,
 357         .allmulticast_enable  = eth_igb_allmulticast_enable,
 358         .allmulticast_disable = eth_igb_allmulticast_disable,
 359         .link_update          = eth_igb_link_update,
 360         .stats_get            = eth_igb_stats_get,
 361         .xstats_get           = eth_igb_xstats_get,
 362         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 363         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 364         .xstats_get_names     = eth_igb_xstats_get_names,
 365         .stats_reset          = eth_igb_stats_reset,
 366         .xstats_reset         = eth_igb_xstats_reset,
 367         .fw_version_get       = eth_igb_fw_version_get,
 368         .dev_infos_get        = eth_igb_infos_get,
 369         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 370         .mtu_set              = eth_igb_mtu_set,
 371         .vlan_filter_set      = eth_igb_vlan_filter_set,
 372         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 373         .vlan_offload_set     = eth_igb_vlan_offload_set,
 374         .rx_queue_setup       = eth_igb_rx_queue_setup,
 375         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 376         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 377         .rx_queue_release     = eth_igb_rx_queue_release,
 378         .tx_queue_setup       = eth_igb_tx_queue_setup,
 379         .tx_queue_release     = eth_igb_tx_queue_release,
 380         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 381         .dev_led_on           = eth_igb_led_on,
 382         .dev_led_off          = eth_igb_led_off,
 383         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 384         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 385         .mac_addr_add         = eth_igb_rar_set,
 386         .mac_addr_remove      = eth_igb_rar_clear,
 387         .mac_addr_set         = eth_igb_default_mac_addr_set,
 388         .reta_update          = eth_igb_rss_reta_update,
 389         .reta_query           = eth_igb_rss_reta_query,
 390         .rss_hash_update      = eth_igb_rss_hash_update,
 391         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 392         .filter_ctrl          = eth_igb_filter_ctrl,
 393         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 394         .rxq_info_get         = igb_rxq_info_get,
 395         .txq_info_get         = igb_txq_info_get,
 396         .timesync_enable      = igb_timesync_enable,
 397         .timesync_disable     = igb_timesync_disable,
 398         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 399         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 400         .get_reg              = eth_igb_get_regs,
 401         .get_eeprom_length    = eth_igb_get_eeprom_length,
 402         .get_eeprom           = eth_igb_get_eeprom,
 403         .set_eeprom           = eth_igb_set_eeprom,
 404         .get_module_info      = eth_igb_get_module_info,
 405         .get_module_eeprom    = eth_igb_get_module_eeprom,
 406         .timesync_adjust_time = igb_timesync_adjust_time,
 407         .timesync_read_time   = igb_timesync_read_time,
 408         .timesync_write_time  = igb_timesync_write_time,
 409 };
 410
 411 /*
 412  * dev_ops for virtual function, bare necessities for basic vf
 413  * operation have been implemented
 414  */
 415 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 416         .dev_configure        = igbvf_dev_configure,
 417         .dev_start            = igbvf_dev_start,
 418         .dev_stop             = igbvf_dev_stop,
 419         .dev_close            = igbvf_dev_close,
 420         .promiscuous_enable   = igbvf_promiscuous_enable,
 421         .promiscuous_disable  = igbvf_promiscuous_disable,
 422         .allmulticast_enable  = igbvf_allmulticast_enable,
 423         .allmulticast_disable = igbvf_allmulticast_disable,
 424         .link_update          = eth_igb_link_update,
 425         .stats_get            = eth_igbvf_stats_get,
 426         .xstats_get           = eth_igbvf_xstats_get,
 427         .xstats_get_names     = eth_igbvf_xstats_get_names,
 428         .stats_reset          = eth_igbvf_stats_reset,
 429         .xstats_reset         = eth_igbvf_stats_reset,
 430         .vlan_filter_set      = igbvf_vlan_filter_set,
 431         .dev_infos_get        = eth_igbvf_infos_get,
 432         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 433         .rx_queue_setup       = eth_igb_rx_queue_setup,
 434         .rx_queue_release     = eth_igb_rx_queue_release,
 435         .tx_queue_setup       = eth_igb_tx_queue_setup,
 436         .tx_queue_release     = eth_igb_tx_queue_release,
 437         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 438         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 439         .rxq_info_get         = igb_rxq_info_get,
 440         .txq_info_get         = igb_txq_info_get,
 441         .mac_addr_set         = igbvf_default_mac_addr_set,
 442         .get_reg              = igbvf_get_regs,
 443 };
 444
 445 /* store statistics names and its offset in stats structure */
 446 struct rte_igb_xstats_name_off {
 447         char name[RTE_ETH_XSTATS_NAME_SIZE];
 448         unsigned offset;
 449 };
 450
 451 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 452         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 453         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 454         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 455         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 456         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 457         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 458         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 459                 ecol)},
 460         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 461         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 462         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 463         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 464         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 465         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 466         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 467         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 468         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 469         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 470         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 471                 fcruc)},
 472         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 473         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 474         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 475         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 476         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 477                 prc1023)},
 478         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 479                 prc1522)},
 480         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 481         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 482         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 483         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 484         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 485         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 486         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 487         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 488         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 489         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 490         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 491         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 492         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 493         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 494         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 495         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 496         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 497         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 498                 ptc1023)},
 499         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 500                 ptc1522)},
 501         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 502         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 503         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 504         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 505         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 506         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 507         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 508
 509         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 510 };
 511
 512 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 513                 sizeof(rte_igb_stats_strings[0]))
 514
 515 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 516         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 517         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 518         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 519         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 520         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 521 };
 522
 523 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 524                 sizeof(rte_igbvf_stats_strings[0]))
 525
 526
 527 static inline void
 528 igb_intr_enable(struct rte_eth_dev *dev)
 529 {
 530         struct e1000_interrupt *intr =
 531                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 532         struct e1000_hw *hw =
 533                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 534         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 535         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 536
 537         if (rte_intr_allow_others(intr_handle) &&
 538                 dev->data->dev_conf.intr_conf.lsc != 0) {
 539                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 540         }
 541
 542         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 543         E1000_WRITE_FLUSH(hw);
 544 }
 545
 546 static void
 547 igb_intr_disable(struct rte_eth_dev *dev)
 548 {
 549         struct e1000_hw *hw =
 550                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 551         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 552         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 553
 554         if (rte_intr_allow_others(intr_handle) &&
 555                 dev->data->dev_conf.intr_conf.lsc != 0) {
 556                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 557         }
 558
 559         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 560         E1000_WRITE_FLUSH(hw);
 561 }
 562
 563 static inline void
 564 igbvf_intr_enable(struct rte_eth_dev *dev)
 565 {
 566         struct e1000_hw *hw =
 567                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 568
 569         /* only for mailbox */
 570         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 571         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 572         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 573         E1000_WRITE_FLUSH(hw);
 574 }
 575
 576 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 577 static void
 578 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 579 {
 580         uint32_t tmp = 0;
 581
 582         /* mailbox */
 583         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 584         tmp |= E1000_VTIVAR_VALID;
 585         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 586 }
 587
 588 static void
 589 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 590 {
 591         struct e1000_hw *hw =
 592                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 593
 594         /* Configure VF other cause ivar */
 595         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 596 }
 597
 598 static inline int32_t
 599 igb_pf_reset_hw(struct e1000_hw *hw)
 600 {
 601         uint32_t ctrl_ext;
 602         int32_t status;
 603
 604         status = e1000_reset_hw(hw);
 605
 606         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 607         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 608         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 609         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 610         E1000_WRITE_FLUSH(hw);
 611
 612         return status;
 613 }
 614
 615 static void
 616 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 617 {
 618         struct e1000_hw *hw =
 619                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 620
 621
 622         hw->vendor_id = pci_dev->id.vendor_id;
 623         hw->device_id = pci_dev->id.device_id;
 624         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 625         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 626
 627         e1000_set_mac_type(hw);
 628
 629         /* need to check if it is a vf device below */
 630 }
 631
 632 static int
 633 igb_reset_swfw_lock(struct e1000_hw *hw)
 634 {
 635         int ret_val;
 636
 637         /*
 638          * Do mac ops initialization manually here, since we will need
 639          * some function pointers set by this call.
 640          */
 641         ret_val = e1000_init_mac_params(hw);
 642         if (ret_val)
 643                 return ret_val;
 644
 645         /*
 646          * SMBI lock should not fail in this early stage. If this is the case,
 647          * it is due to an improper exit of the application.
 648          * So force the release of the faulty lock.
 649          */
 650         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 651                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 652         }
 653         e1000_put_hw_semaphore_generic(hw);
 654
 655         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 656                 uint16_t mask;
 657
 658                 /*
 659                  * Phy lock should not fail in this early stage. If this is the case,
 660                  * it is due to an improper exit of the application.
 661                  * So force the release of the faulty lock.
 662                  */
 663                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 664                 if (hw->bus.func > E1000_FUNC_1)
 665                         mask <<= 2;
 666                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 667                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 668                                     hw->bus.func);
 669                 }
 670                 hw->mac.ops.release_swfw_sync(hw, mask);
 671
 672                 /*
 673                  * This one is more tricky since it is common to all ports; but
 674                  * swfw_sync retries last long enough (1s) to be almost sure that if
 675                  * lock can not be taken it is due to an improper lock of the
 676                  * semaphore.
 677                  */
 678                 mask = E1000_SWFW_EEP_SM;
 679                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 680                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 681                 }
 682                 hw->mac.ops.release_swfw_sync(hw, mask);
 683         }
 684
 685         return E1000_SUCCESS;
 686 }
 687
 688 /* Remove all ntuple filters of the device */
 689 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 690 {
 691         struct e1000_filter_info *filter_info =
 692                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 693         struct e1000_5tuple_filter *p_5tuple;
 694         struct e1000_2tuple_filter *p_2tuple;
 695
 696         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 697                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 698                         p_5tuple, entries);
 699                         rte_free(p_5tuple);
 700         }
 701         filter_info->fivetuple_mask = 0;
 702         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 703                 TAILQ_REMOVE(&filter_info->twotuple_list,
 704                         p_2tuple, entries);
 705                         rte_free(p_2tuple);
 706         }
 707         filter_info->twotuple_mask = 0;
 708
 709         return 0;
 710 }
 711
 712 /* Remove all flex filters of the device */
 713 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 714 {
 715         struct e1000_filter_info *filter_info =
 716                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 717         struct e1000_flex_filter *p_flex;
 718
 719         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 720                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 721                 rte_free(p_flex);
 722         }
 723         filter_info->flex_mask = 0;
 724
 725         return 0;
 726 }
 727
 728 static int
 729 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 730 {
 731         int error = 0;
 732         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 733         struct e1000_hw *hw =
 734                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 735         struct e1000_vfta * shadow_vfta =
 736                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 737         struct e1000_filter_info *filter_info =
 738                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 739         struct e1000_adapter *adapter =
 740                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 741
 742         uint32_t ctrl_ext;
 743
 744         eth_dev->dev_ops = &eth_igb_ops;
 745         eth_dev->rx_queue_count = eth_igb_rx_queue_count;
 746         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 747         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 748         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 749         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 750         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 751         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 752
 753         /* for secondary processes, we don't initialise any further as primary
 754          * has already done this work. Only check we don't need a different
 755          * RX function */
 756         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 757                 if (eth_dev->data->scattered_rx)
 758                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 759                 return 0;
 760         }
 761
 762         rte_eth_copy_pci_info(eth_dev, pci_dev);
 763         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 764
 765         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 766
 767         igb_identify_hardware(eth_dev, pci_dev);
 768         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 769                 error = -EIO;
 770                 goto err_late;
 771         }
 772
 773         e1000_get_bus_info(hw);
 774
 775         /* Reset any pending lock */
 776         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 777                 error = -EIO;
 778                 goto err_late;
 779         }
 780
 781         /* Finish initialization */
 782         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 783                 error = -EIO;
 784                 goto err_late;
 785         }
 786
 787         hw->mac.autoneg = 1;
 788         hw->phy.autoneg_wait_to_complete = 0;
 789         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 790
 791         /* Copper options */
 792         if (hw->phy.media_type == e1000_media_type_copper) {
 793                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 794                 hw->phy.disable_polarity_correction = 0;
 795                 hw->phy.ms_type = e1000_ms_hw_default;
 796         }
 797
 798         /*
 799          * Start from a known state, this is important in reading the nvm
 800          * and mac from that.
 801          */
 802         igb_pf_reset_hw(hw);
 803
 804         /* Make sure we have a good EEPROM before we read from it */
 805         if (e1000_validate_nvm_checksum(hw) < 0) {
 806                 /*
 807                  * Some PCI-E parts fail the first check due to
 808                  * the link being in sleep state, call it again,
 809                  * if it fails a second time its a real issue.
 810                  */
 811                 if (e1000_validate_nvm_checksum(hw) < 0) {
 812                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 813                         error = -EIO;
 814                         goto err_late;
 815                 }
 816         }
 817
 818         /* Read the permanent MAC address out of the EEPROM */
 819         if (e1000_read_mac_addr(hw) != 0) {
 820                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 821                 error = -EIO;
 822                 goto err_late;
 823         }
 824
 825         /* Allocate memory for storing MAC addresses */
 826         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 827                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 828         if (eth_dev->data->mac_addrs == NULL) {
 829                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 830                                                 "store MAC addresses",
 831                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 832                 error = -ENOMEM;
 833                 goto err_late;
 834         }
 835
 836         /* Copy the permanent MAC address */
 837         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 838                         &eth_dev->data->mac_addrs[0]);
 839
 840         /* initialize the vfta */
 841         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 842
 843         /* Now initialize the hardware */
 844         if (igb_hardware_init(hw) != 0) {
 845                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 846                 rte_free(eth_dev->data->mac_addrs);
 847                 eth_dev->data->mac_addrs = NULL;
 848                 error = -ENODEV;
 849                 goto err_late;
 850         }
 851         hw->mac.get_link_status = 1;
 852         adapter->stopped = 0;
 853
 854         /* Indicate SOL/IDER usage */
 855         if (e1000_check_reset_block(hw) < 0) {
 856                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 857                                         "SOL/IDER session");
 858         }
 859
 860         /* initialize PF if max_vfs not zero */
 861         igb_pf_host_init(eth_dev);
 862
 863         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 864         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 865         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 866         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 867         E1000_WRITE_FLUSH(hw);
 868
 869         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 870                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 871                      pci_dev->id.device_id);
 872
 873         rte_intr_callback_register(&pci_dev->intr_handle,
 874                                    eth_igb_interrupt_handler,
 875                                    (void *)eth_dev);
 876
 877         /* enable uio/vfio intr/eventfd mapping */
 878         rte_intr_enable(&pci_dev->intr_handle);
 879
 880         /* enable support intr */
 881         igb_intr_enable(eth_dev);
 882
 883         eth_igb_dev_set_link_down(eth_dev);
 884
 885         /* initialize filter info */
 886         memset(filter_info, 0,
 887                sizeof(struct e1000_filter_info));
 888
 889         TAILQ_INIT(&filter_info->flex_list);
 890         TAILQ_INIT(&filter_info->twotuple_list);
 891         TAILQ_INIT(&filter_info->fivetuple_list);
 892
 893         TAILQ_INIT(&igb_filter_ntuple_list);
 894         TAILQ_INIT(&igb_filter_ethertype_list);
 895         TAILQ_INIT(&igb_filter_syn_list);
 896         TAILQ_INIT(&igb_filter_flex_list);
 897         TAILQ_INIT(&igb_filter_rss_list);
 898         TAILQ_INIT(&igb_flow_list);
 899
 900         return 0;
 901
 902 err_late:
 903         igb_hw_control_release(hw);
 904
 905         return error;
 906 }
 907
 908 static int
 909 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 910 {
 911         PMD_INIT_FUNC_TRACE();
 912
 913         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 914                 return 0;
 915
 916         eth_igb_close(eth_dev);
 917
 918         return 0;
 919 }
 920
 921 /*
 922  * Virtual Function device init
 923  */
 924 static int
 925 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 926 {
 927         struct rte_pci_device *pci_dev;
 928         struct rte_intr_handle *intr_handle;
 929         struct e1000_adapter *adapter =
 930                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 931         struct e1000_hw *hw =
 932                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 933         int diag;
 934         struct rte_ether_addr *perm_addr =
 935                 (struct rte_ether_addr *)hw->mac.perm_addr;
 936
 937         PMD_INIT_FUNC_TRACE();
 938
 939         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 940         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 941         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 942         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 943         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 944         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 945         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 946
 947         /* for secondary processes, we don't initialise any further as primary
 948          * has already done this work. Only check we don't need a different
 949          * RX function */
 950         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 951                 if (eth_dev->data->scattered_rx)
 952                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 953                 return 0;
 954         }
 955
 956         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 957         rte_eth_copy_pci_info(eth_dev, pci_dev);
 958         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 959
 960         hw->device_id = pci_dev->id.device_id;
 961         hw->vendor_id = pci_dev->id.vendor_id;
 962         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 963         adapter->stopped = 0;
 964
 965         /* Initialize the shared code (base driver) */
 966         diag = e1000_setup_init_funcs(hw, TRUE);
 967         if (diag != 0) {
 968                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 969                         diag);
 970                 return -EIO;
 971         }
 972
 973         /* init_mailbox_params */
 974         hw->mbx.ops.init_params(hw);
 975
 976         /* Disable the interrupts for VF */
 977         igbvf_intr_disable(hw);
 978
 979         diag = hw->mac.ops.reset_hw(hw);
 980
 981         /* Allocate memory for storing MAC addresses */
 982         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
 983                 hw->mac.rar_entry_count, 0);
 984         if (eth_dev->data->mac_addrs == NULL) {
 985                 PMD_INIT_LOG(ERR,
 986                         "Failed to allocate %d bytes needed to store MAC "
 987                         "addresses",
 988                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 989                 return -ENOMEM;
 990         }
 991
 992         /* Generate a random MAC address, if none was assigned by PF. */
 993         if (rte_is_zero_ether_addr(perm_addr)) {
 994                 rte_eth_random_addr(perm_addr->addr_bytes);
 995                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 996                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 997                              "%02x:%02x:%02x:%02x:%02x:%02x",
 998                              perm_addr->addr_bytes[0],
 999                              perm_addr->addr_bytes[1],
1000                              perm_addr->addr_bytes[2],
1001                              perm_addr->addr_bytes[3],
1002                              perm_addr->addr_bytes[4],
1003                              perm_addr->addr_bytes[5]);
1004         }
1005
1006         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1007         if (diag) {
1008                 rte_free(eth_dev->data->mac_addrs);
1009                 eth_dev->data->mac_addrs = NULL;
1010                 return diag;
1011         }
1012         /* Copy the permanent MAC address */
1013         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1014                         &eth_dev->data->mac_addrs[0]);
1015
1016         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1017                      "mac.type=%s",
1018                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1019                      pci_dev->id.device_id, "igb_mac_82576_vf");
1020
1021         intr_handle = &pci_dev->intr_handle;
1022         rte_intr_callback_register(intr_handle,
1023                                    eth_igbvf_interrupt_handler, eth_dev);
1024
1025         return 0;
1026 }
1027
1028 static int
1029 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1030 {
1031         PMD_INIT_FUNC_TRACE();
1032
1033         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1034                 return 0;
1035
1036         igbvf_dev_close(eth_dev);
1037
1038         return 0;
1039 }
1040
1041 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1042         struct rte_pci_device *pci_dev)
1043 {
1044         return rte_eth_dev_pci_generic_probe(pci_dev,
1045                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1046 }
1047
1048 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1049 {
1050         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1051 }
1052
1053 static struct rte_pci_driver rte_igb_pmd = {
1054         .id_table = pci_id_igb_map,
1055         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1056         .probe = eth_igb_pci_probe,
1057         .remove = eth_igb_pci_remove,
1058 };
1059
1060
1061 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1062         struct rte_pci_device *pci_dev)
1063 {
1064         return rte_eth_dev_pci_generic_probe(pci_dev,
1065                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1066 }
1067
1068 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1069 {
1070         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1071 }
1072
1073 /*
1074  * virtual function driver struct
1075  */
1076 static struct rte_pci_driver rte_igbvf_pmd = {
1077         .id_table = pci_id_igbvf_map,
1078         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1079         .probe = eth_igbvf_pci_probe,
1080         .remove = eth_igbvf_pci_remove,
1081 };
1082
1083 static void
1084 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1085 {
1086         struct e1000_hw *hw =
1087                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1088         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1089         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1090         rctl |= E1000_RCTL_VFE;
1091         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1092 }
1093
1094 static int
1095 igb_check_mq_mode(struct rte_eth_dev *dev)
1096 {
1097         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1098         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1099         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1100         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1101
1102         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1103             tx_mq_mode == ETH_MQ_TX_DCB ||
1104             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1105                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1106                 return -EINVAL;
1107         }
1108         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1109                 /* Check multi-queue mode.
1110                  * To no break software we accept ETH_MQ_RX_NONE as this might
1111                  * be used to turn off VLAN filter.
1112                  */
1113
1114                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1115                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1116                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1117                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1118                 } else {
1119                         /* Only support one queue on VFs.
1120                          * RSS together with SRIOV is not supported.
1121                          */
1122                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1123                                         " wrong mq_mode rx %d.",
1124                                         rx_mq_mode);
1125                         return -EINVAL;
1126                 }
1127                 /* TX mode is not used here, so mode might be ignored.*/
1128                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1129                         /* SRIOV only works in VMDq enable mode */
1130                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1131                                         " TX mode %d is not supported. "
1132                                         " Driver will behave as %d mode.",
1133                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1134                 }
1135
1136                 /* check valid queue number */
1137                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1138                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1139                                         " only support one queue on VFs.");
1140                         return -EINVAL;
1141                 }
1142         } else {
1143                 /* To no break software that set invalid mode, only display
1144                  * warning if invalid mode is used.
1145                  */
1146                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1147                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1148                     rx_mq_mode != ETH_MQ_RX_RSS) {
1149                         /* RSS together with VMDq not supported*/
1150                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1151                                      rx_mq_mode);
1152                         return -EINVAL;
1153                 }
1154
1155                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1156                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1157                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1158                                         " Due to txmode is meaningless in this"
1159                                         " driver, just ignore.",
1160                                         tx_mq_mode);
1161                 }
1162         }
1163         return 0;
1164 }
1165
1166 static int
1167 eth_igb_configure(struct rte_eth_dev *dev)
1168 {
1169         struct e1000_interrupt *intr =
1170                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1171         int ret;
1172
1173         PMD_INIT_FUNC_TRACE();
1174
1175         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1176                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1177
1178         /* multipe queue mode checking */
1179         ret  = igb_check_mq_mode(dev);
1180         if (ret != 0) {
1181                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1182                             ret);
1183                 return ret;
1184         }
1185
1186         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1187         PMD_INIT_FUNC_TRACE();
1188
1189         return 0;
1190 }
1191
1192 static void
1193 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1194                      bool enable)
1195 {
1196         struct e1000_hw *hw =
1197                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1198         uint32_t tctl, rctl;
1199
1200         tctl = E1000_READ_REG(hw, E1000_TCTL);
1201         rctl = E1000_READ_REG(hw, E1000_RCTL);
1202
1203         if (enable) {
1204                 /* enable Tx/Rx */
1205                 tctl |= E1000_TCTL_EN;
1206                 rctl |= E1000_RCTL_EN;
1207         } else {
1208                 /* disable Tx/Rx */
1209                 tctl &= ~E1000_TCTL_EN;
1210                 rctl &= ~E1000_RCTL_EN;
1211         }
1212         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1213         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1214         E1000_WRITE_FLUSH(hw);
1215 }
1216
1217 static int
1218 eth_igb_start(struct rte_eth_dev *dev)
1219 {
1220         struct e1000_hw *hw =
1221                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1222         struct e1000_adapter *adapter =
1223                 E1000_DEV_PRIVATE(dev->data->dev_private);
1224         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1225         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1226         int ret, mask;
1227         uint32_t intr_vector = 0;
1228         uint32_t ctrl_ext;
1229         uint32_t *speeds;
1230         int num_speeds;
1231         bool autoneg;
1232
1233         PMD_INIT_FUNC_TRACE();
1234
1235         /* disable uio/vfio intr/eventfd mapping */
1236         rte_intr_disable(intr_handle);
1237
1238         /* Power up the phy. Needed to make the link go Up */
1239         eth_igb_dev_set_link_up(dev);
1240
1241         /*
1242          * Packet Buffer Allocation (PBA)
1243          * Writing PBA sets the receive portion of the buffer
1244          * the remainder is used for the transmit buffer.
1245          */
1246         if (hw->mac.type == e1000_82575) {
1247                 uint32_t pba;
1248
1249                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1250                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1251         }
1252
1253         /* Put the address into the Receive Address Array */
1254         e1000_rar_set(hw, hw->mac.addr, 0);
1255
1256         /* Initialize the hardware */
1257         if (igb_hardware_init(hw)) {
1258                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1259                 return -EIO;
1260         }
1261         adapter->stopped = 0;
1262
1263         E1000_WRITE_REG(hw, E1000_VET,
1264                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1265
1266         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1267         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1268         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1269         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1270         E1000_WRITE_FLUSH(hw);
1271
1272         /* configure PF module if SRIOV enabled */
1273         igb_pf_host_configure(dev);
1274
1275         /* check and configure queue intr-vector mapping */
1276         if ((rte_intr_cap_multiple(intr_handle) ||
1277              !RTE_ETH_DEV_SRIOV(dev).active) &&
1278             dev->data->dev_conf.intr_conf.rxq != 0) {
1279                 intr_vector = dev->data->nb_rx_queues;
1280                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1281                         return -1;
1282         }
1283
1284         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1285                 intr_handle->intr_vec =
1286                         rte_zmalloc("intr_vec",
1287                                     dev->data->nb_rx_queues * sizeof(int), 0);
1288                 if (intr_handle->intr_vec == NULL) {
1289                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1290                                      " intr_vec", dev->data->nb_rx_queues);
1291                         return -ENOMEM;
1292                 }
1293         }
1294
1295         /* confiugre msix for rx interrupt */
1296         eth_igb_configure_msix_intr(dev);
1297
1298         /* Configure for OS presence */
1299         igb_init_manageability(hw);
1300
1301         eth_igb_tx_init(dev);
1302
1303         /* This can fail when allocating mbufs for descriptor rings */
1304         ret = eth_igb_rx_init(dev);
1305         if (ret) {
1306                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1307                 igb_dev_clear_queues(dev);
1308                 return ret;
1309         }
1310
1311         e1000_clear_hw_cntrs_base_generic(hw);
1312
1313         /*
1314          * VLAN Offload Settings
1315          */
1316         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1317                         ETH_VLAN_EXTEND_MASK;
1318         ret = eth_igb_vlan_offload_set(dev, mask);
1319         if (ret) {
1320                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1321                 igb_dev_clear_queues(dev);
1322                 return ret;
1323         }
1324
1325         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1326                 /* Enable VLAN filter since VMDq always use VLAN filter */
1327                 igb_vmdq_vlan_hw_filter_enable(dev);
1328         }
1329
1330         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1331                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1332                 (hw->mac.type == e1000_i211)) {
1333                 /* Configure EITR with the maximum possible value (0xFFFF) */
1334                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1335         }
1336
1337         /* Setup link speed and duplex */
1338         speeds = &dev->data->dev_conf.link_speeds;
1339         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1340                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1341                 hw->mac.autoneg = 1;
1342         } else {
1343                 num_speeds = 0;
1344                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1345
1346                 /* Reset */
1347                 hw->phy.autoneg_advertised = 0;
1348
1349                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1350                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1351                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1352                         num_speeds = -1;
1353                         goto error_invalid_config;
1354                 }
1355                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1356                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1357                         num_speeds++;
1358                 }
1359                 if (*speeds & ETH_LINK_SPEED_10M) {
1360                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1361                         num_speeds++;
1362                 }
1363                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1364                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1365                         num_speeds++;
1366                 }
1367                 if (*speeds & ETH_LINK_SPEED_100M) {
1368                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1369                         num_speeds++;
1370                 }
1371                 if (*speeds & ETH_LINK_SPEED_1G) {
1372                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1373                         num_speeds++;
1374                 }
1375                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1376                         goto error_invalid_config;
1377
1378                 /* Set/reset the mac.autoneg based on the link speed,
1379                  * fixed or not
1380                  */
1381                 if (!autoneg) {
1382                         hw->mac.autoneg = 0;
1383                         hw->mac.forced_speed_duplex =
1384                                         hw->phy.autoneg_advertised;
1385                 } else {
1386                         hw->mac.autoneg = 1;
1387                 }
1388         }
1389
1390         e1000_setup_link(hw);
1391
1392         if (rte_intr_allow_others(intr_handle)) {
1393                 /* check if lsc interrupt is enabled */
1394                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1395                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1396                 else
1397                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1398         } else {
1399                 rte_intr_callback_unregister(intr_handle,
1400                                              eth_igb_interrupt_handler,
1401                                              (void *)dev);
1402                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1403                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1404                                      " no intr multiplex");
1405         }
1406
1407         /* check if rxq interrupt is enabled */
1408         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1409             rte_intr_dp_is_en(intr_handle))
1410                 eth_igb_rxq_interrupt_setup(dev);
1411
1412         /* enable uio/vfio intr/eventfd mapping */
1413         rte_intr_enable(intr_handle);
1414
1415         /* resume enabled intr since hw reset */
1416         igb_intr_enable(dev);
1417
1418         /* restore all types filter */
1419         igb_filter_restore(dev);
1420
1421         eth_igb_rxtx_control(dev, true);
1422         eth_igb_link_update(dev, 0);
1423
1424         PMD_INIT_LOG(DEBUG, "<<");
1425
1426         return 0;
1427
1428 error_invalid_config:
1429         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1430                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1431         igb_dev_clear_queues(dev);
1432         return -EINVAL;
1433 }
1434
1435 /*********************************************************************
1436  *
1437  *  This routine disables all traffic on the adapter by issuing a
1438  *  global reset on the MAC.
1439  *
1440  **********************************************************************/
1441 static int
1442 eth_igb_stop(struct rte_eth_dev *dev)
1443 {
1444         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1446         struct rte_eth_link link;
1447         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1448         struct e1000_adapter *adapter =
1449                 E1000_DEV_PRIVATE(dev->data->dev_private);
1450
1451         if (adapter->stopped)
1452                 return 0;
1453
1454         eth_igb_rxtx_control(dev, false);
1455
1456         igb_intr_disable(dev);
1457
1458         /* disable intr eventfd mapping */
1459         rte_intr_disable(intr_handle);
1460
1461         igb_pf_reset_hw(hw);
1462         E1000_WRITE_REG(hw, E1000_WUC, 0);
1463
1464         /* Set bit for Go Link disconnect if PHY reset is not blocked */
1465         if (hw->mac.type >= e1000_82580 &&
1466             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1467                 uint32_t phpm_reg;
1468
1469                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1470                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1471                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1472         }
1473
1474         /* Power down the phy. Needed to make the link go Down */
1475         eth_igb_dev_set_link_down(dev);
1476
1477         igb_dev_clear_queues(dev);
1478
1479         /* clear the recorded link status */
1480         memset(&link, 0, sizeof(link));
1481         rte_eth_linkstatus_set(dev, &link);
1482
1483         if (!rte_intr_allow_others(intr_handle))
1484                 /* resume to the default handler */
1485                 rte_intr_callback_register(intr_handle,
1486                                            eth_igb_interrupt_handler,
1487                                            (void *)dev);
1488
1489         /* Clean datapath event and queue/vec mapping */
1490         rte_intr_efd_disable(intr_handle);
1491         if (intr_handle->intr_vec != NULL) {
1492                 rte_free(intr_handle->intr_vec);
1493                 intr_handle->intr_vec = NULL;
1494         }
1495
1496         adapter->stopped = true;
1497         dev->data->dev_started = 0;
1498
1499         return 0;
1500 }
1501
1502 static int
1503 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1504 {
1505         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506
1507         if (hw->phy.media_type == e1000_media_type_copper)
1508                 e1000_power_up_phy(hw);
1509         else
1510                 e1000_power_up_fiber_serdes_link(hw);
1511
1512         return 0;
1513 }
1514
1515 static int
1516 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1517 {
1518         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1519
1520         if (hw->phy.media_type == e1000_media_type_copper)
1521                 e1000_power_down_phy(hw);
1522         else
1523                 e1000_shutdown_fiber_serdes_link(hw);
1524
1525         return 0;
1526 }
1527
1528 static int
1529 eth_igb_close(struct rte_eth_dev *dev)
1530 {
1531         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1532         struct rte_eth_link link;
1533         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1534         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1535         struct e1000_filter_info *filter_info =
1536                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1537         int ret;
1538
1539         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1540                 return 0;
1541
1542         ret = eth_igb_stop(dev);
1543
1544         e1000_phy_hw_reset(hw);
1545         igb_release_manageability(hw);
1546         igb_hw_control_release(hw);
1547
1548         /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1549         if (hw->mac.type >= e1000_82580 &&
1550             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1551                 uint32_t phpm_reg;
1552
1553                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1554                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1555                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1556         }
1557
1558         igb_dev_free_queues(dev);
1559
1560         if (intr_handle->intr_vec) {
1561                 rte_free(intr_handle->intr_vec);
1562                 intr_handle->intr_vec = NULL;
1563         }
1564
1565         memset(&link, 0, sizeof(link));
1566         rte_eth_linkstatus_set(dev, &link);
1567
1568         /* Reset any pending lock */
1569         igb_reset_swfw_lock(hw);
1570
1571         /* uninitialize PF if max_vfs not zero */
1572         igb_pf_host_uninit(dev);
1573
1574         rte_intr_callback_unregister(intr_handle,
1575                                      eth_igb_interrupt_handler, dev);
1576
1577         /* clear the SYN filter info */
1578         filter_info->syn_info = 0;
1579
1580         /* clear the ethertype filters info */
1581         filter_info->ethertype_mask = 0;
1582         memset(filter_info->ethertype_filters, 0,
1583                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1584
1585         /* clear the rss filter info */
1586         memset(&filter_info->rss_info, 0,
1587                 sizeof(struct igb_rte_flow_rss_conf));
1588
1589         /* remove all ntuple filters of the device */
1590         igb_ntuple_filter_uninit(dev);
1591
1592         /* remove all flex filters of the device */
1593         igb_flex_filter_uninit(dev);
1594
1595         /* clear all the filters list */
1596         igb_filterlist_flush(dev);
1597
1598         return ret;
1599 }
1600
1601 /*
1602  * Reset PF device.
1603  */
1604 static int
1605 eth_igb_reset(struct rte_eth_dev *dev)
1606 {
1607         int ret;
1608
1609         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1610          * its VF to make them align with it. The detailed notification
1611          * mechanism is PMD specific and is currently not implemented.
1612          * To avoid unexpected behavior in VF, currently reset of PF with
1613          * SR-IOV activation is not supported. It might be supported later.
1614          */
1615         if (dev->data->sriov.active)
1616                 return -ENOTSUP;
1617
1618         ret = eth_igb_dev_uninit(dev);
1619         if (ret)
1620                 return ret;
1621
1622         ret = eth_igb_dev_init(dev);
1623
1624         return ret;
1625 }
1626
1627
1628 static int
1629 igb_get_rx_buffer_size(struct e1000_hw *hw)
1630 {
1631         uint32_t rx_buf_size;
1632         if (hw->mac.type == e1000_82576) {
1633                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1634         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1635                 /* PBS needs to be translated according to a lookup table */
1636                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1637                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1638                 rx_buf_size = (rx_buf_size << 10);
1639         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1640                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1641         } else {
1642                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1643         }
1644
1645         return rx_buf_size;
1646 }
1647
1648 /*********************************************************************
1649  *
1650  *  Initialize the hardware
1651  *
1652  **********************************************************************/
1653 static int
1654 igb_hardware_init(struct e1000_hw *hw)
1655 {
1656         uint32_t rx_buf_size;
1657         int diag;
1658
1659         /* Let the firmware know the OS is in control */
1660         igb_hw_control_acquire(hw);
1661
1662         /*
1663          * These parameters control the automatic generation (Tx) and
1664          * response (Rx) to Ethernet PAUSE frames.
1665          * - High water mark should allow for at least two standard size (1518)
1666          *   frames to be received after sending an XOFF.
1667          * - Low water mark works best when it is very near the high water mark.
1668          *   This allows the receiver to restart by sending XON when it has
1669          *   drained a bit. Here we use an arbitrary value of 1500 which will
1670          *   restart after one full frame is pulled from the buffer. There
1671          *   could be several smaller frames in the buffer and if so they will
1672          *   not trigger the XON until their total number reduces the buffer
1673          *   by 1500.
1674          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1675          */
1676         rx_buf_size = igb_get_rx_buffer_size(hw);
1677
1678         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1679         hw->fc.low_water = hw->fc.high_water - 1500;
1680         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1681         hw->fc.send_xon = 1;
1682
1683         /* Set Flow control, use the tunable location if sane */
1684         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1685                 hw->fc.requested_mode = igb_fc_setting;
1686         else
1687                 hw->fc.requested_mode = e1000_fc_none;
1688
1689         /* Issue a global reset */
1690         igb_pf_reset_hw(hw);
1691         E1000_WRITE_REG(hw, E1000_WUC, 0);
1692
1693         diag = e1000_init_hw(hw);
1694         if (diag < 0)
1695                 return diag;
1696
1697         E1000_WRITE_REG(hw, E1000_VET,
1698                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1699         e1000_get_phy_info(hw);
1700         e1000_check_for_link(hw);
1701
1702         return 0;
1703 }
1704
1705 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1706 static void
1707 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1708 {
1709         int pause_frames;
1710
1711         uint64_t old_gprc  = stats->gprc;
1712         uint64_t old_gptc  = stats->gptc;
1713         uint64_t old_tpr   = stats->tpr;
1714         uint64_t old_tpt   = stats->tpt;
1715         uint64_t old_rpthc = stats->rpthc;
1716         uint64_t old_hgptc = stats->hgptc;
1717
1718         if(hw->phy.media_type == e1000_media_type_copper ||
1719             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1720                 stats->symerrs +=
1721                     E1000_READ_REG(hw,E1000_SYMERRS);
1722                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1723         }
1724
1725         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1726         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1727         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1728         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1729
1730         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1731         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1732         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1733         stats->dc += E1000_READ_REG(hw, E1000_DC);
1734         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1735         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1736         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1737         /*
1738         ** For watchdog management we need to know if we have been
1739         ** paused during the last interval, so capture that here.
1740         */
1741         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1742         stats->xoffrxc += pause_frames;
1743         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1744         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1745         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1746         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1747         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1748         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1749         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1750         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1751         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1752         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1753         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1754         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1755
1756         /* For the 64-bit byte counters the low dword must be read first. */
1757         /* Both registers clear on the read of the high dword */
1758
1759         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1760         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1761         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1762         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1763         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1764         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1765         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1766
1767         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1768         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1769         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1770         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1771         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1772
1773         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1774         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1775
1776         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1777         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1778         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1779         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1780         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1781         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1782
1783         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1784         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1785         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1786         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1787         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1788         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1789         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1790         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1791
1792         /* Interrupt Counts */
1793
1794         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1795         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1796         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1797         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1798         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1799         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1800         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1801         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1802         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1803
1804         /* Host to Card Statistics */
1805
1806         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1807         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1808         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1809         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1810         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1811         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1812         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1813         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1814         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1815         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1816         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1817         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1818         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1819         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1820         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1821         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1822
1823         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1824         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1825         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1826         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1827         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1828         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1829 }
1830
1831 static int
1832 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1833 {
1834         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         struct e1000_hw_stats *stats =
1836                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1837
1838         igb_read_stats_registers(hw, stats);
1839
1840         if (rte_stats == NULL)
1841                 return -EINVAL;
1842
1843         /* Rx Errors */
1844         rte_stats->imissed = stats->mpc;
1845         rte_stats->ierrors = stats->crcerrs +
1846                              stats->rlec + stats->ruc + stats->roc +
1847                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1848
1849         /* Tx Errors */
1850         rte_stats->oerrors = stats->ecol + stats->latecol;
1851
1852         rte_stats->ipackets = stats->gprc;
1853         rte_stats->opackets = stats->gptc;
1854         rte_stats->ibytes   = stats->gorc;
1855         rte_stats->obytes   = stats->gotc;
1856         return 0;
1857 }
1858
1859 static int
1860 eth_igb_stats_reset(struct rte_eth_dev *dev)
1861 {
1862         struct e1000_hw_stats *hw_stats =
1863                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1864
1865         /* HW registers are cleared on read */
1866         eth_igb_stats_get(dev, NULL);
1867
1868         /* Reset software totals */
1869         memset(hw_stats, 0, sizeof(*hw_stats));
1870
1871         return 0;
1872 }
1873
1874 static int
1875 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1876 {
1877         struct e1000_hw_stats *stats =
1878                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1879
1880         /* HW registers are cleared on read */
1881         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1882
1883         /* Reset software totals */
1884         memset(stats, 0, sizeof(*stats));
1885
1886         return 0;
1887 }
1888
1889 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1890         struct rte_eth_xstat_name *xstats_names,
1891         __rte_unused unsigned int size)
1892 {
1893         unsigned i;
1894
1895         if (xstats_names == NULL)
1896                 return IGB_NB_XSTATS;
1897
1898         /* Note: limit checked in rte_eth_xstats_names() */
1899
1900         for (i = 0; i < IGB_NB_XSTATS; i++) {
1901                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1902                         sizeof(xstats_names[i].name));
1903         }
1904
1905         return IGB_NB_XSTATS;
1906 }
1907
1908 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1909                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1910                 unsigned int limit)
1911 {
1912         unsigned int i;
1913
1914         if (!ids) {
1915                 if (xstats_names == NULL)
1916                         return IGB_NB_XSTATS;
1917
1918                 for (i = 0; i < IGB_NB_XSTATS; i++)
1919                         strlcpy(xstats_names[i].name,
1920                                 rte_igb_stats_strings[i].name,
1921                                 sizeof(xstats_names[i].name));
1922
1923                 return IGB_NB_XSTATS;
1924
1925         } else {
1926                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1927
1928                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1929                                 IGB_NB_XSTATS);
1930
1931                 for (i = 0; i < limit; i++) {
1932                         if (ids[i] >= IGB_NB_XSTATS) {
1933                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1934                                 return -1;
1935                         }
1936                         strcpy(xstats_names[i].name,
1937                                         xstats_names_copy[ids[i]].name);
1938                 }
1939                 return limit;
1940         }
1941 }
1942
1943 static int
1944 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1945                    unsigned n)
1946 {
1947         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948         struct e1000_hw_stats *hw_stats =
1949                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1950         unsigned i;
1951
1952         if (n < IGB_NB_XSTATS)
1953                 return IGB_NB_XSTATS;
1954
1955         igb_read_stats_registers(hw, hw_stats);
1956
1957         /* If this is a reset xstats is NULL, and we have cleared the
1958          * registers by reading them.
1959          */
1960         if (!xstats)
1961                 return 0;
1962
1963         /* Extended stats */
1964         for (i = 0; i < IGB_NB_XSTATS; i++) {
1965                 xstats[i].id = i;
1966                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1967                         rte_igb_stats_strings[i].offset);
1968         }
1969
1970         return IGB_NB_XSTATS;
1971 }
1972
1973 static int
1974 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1975                 uint64_t *values, unsigned int n)
1976 {
1977         unsigned int i;
1978
1979         if (!ids) {
1980                 struct e1000_hw *hw =
1981                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1982                 struct e1000_hw_stats *hw_stats =
1983                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1984
1985                 if (n < IGB_NB_XSTATS)
1986                         return IGB_NB_XSTATS;
1987
1988                 igb_read_stats_registers(hw, hw_stats);
1989
1990                 /* If this is a reset xstats is NULL, and we have cleared the
1991                  * registers by reading them.
1992                  */
1993                 if (!values)
1994                         return 0;
1995
1996                 /* Extended stats */
1997                 for (i = 0; i < IGB_NB_XSTATS; i++)
1998                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1999                                         rte_igb_stats_strings[i].offset);
2000
2001                 return IGB_NB_XSTATS;
2002
2003         } else {
2004                 uint64_t values_copy[IGB_NB_XSTATS];
2005
2006                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2007                                 IGB_NB_XSTATS);
2008
2009                 for (i = 0; i < n; i++) {
2010                         if (ids[i] >= IGB_NB_XSTATS) {
2011                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2012                                 return -1;
2013                         }
2014                         values[i] = values_copy[ids[i]];
2015                 }
2016                 return n;
2017         }
2018 }
2019
2020 static void
2021 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2022 {
2023         /* Good Rx packets, include VF loopback */
2024         UPDATE_VF_STAT(E1000_VFGPRC,
2025             hw_stats->last_gprc, hw_stats->gprc);
2026
2027         /* Good Rx octets, include VF loopback */
2028         UPDATE_VF_STAT(E1000_VFGORC,
2029             hw_stats->last_gorc, hw_stats->gorc);
2030
2031         /* Good Tx packets, include VF loopback */
2032         UPDATE_VF_STAT(E1000_VFGPTC,
2033             hw_stats->last_gptc, hw_stats->gptc);
2034
2035         /* Good Tx octets, include VF loopback */
2036         UPDATE_VF_STAT(E1000_VFGOTC,
2037             hw_stats->last_gotc, hw_stats->gotc);
2038
2039         /* Rx Multicst packets */
2040         UPDATE_VF_STAT(E1000_VFMPRC,
2041             hw_stats->last_mprc, hw_stats->mprc);
2042
2043         /* Good Rx loopback packets */
2044         UPDATE_VF_STAT(E1000_VFGPRLBC,
2045             hw_stats->last_gprlbc, hw_stats->gprlbc);
2046
2047         /* Good Rx loopback octets */
2048         UPDATE_VF_STAT(E1000_VFGORLBC,
2049             hw_stats->last_gorlbc, hw_stats->gorlbc);
2050
2051         /* Good Tx loopback packets */
2052         UPDATE_VF_STAT(E1000_VFGPTLBC,
2053             hw_stats->last_gptlbc, hw_stats->gptlbc);
2054
2055         /* Good Tx loopback octets */
2056         UPDATE_VF_STAT(E1000_VFGOTLBC,
2057             hw_stats->last_gotlbc, hw_stats->gotlbc);
2058 }
2059
2060 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2061                                      struct rte_eth_xstat_name *xstats_names,
2062                                      __rte_unused unsigned limit)
2063 {
2064         unsigned i;
2065
2066         if (xstats_names != NULL)
2067                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2068                         strlcpy(xstats_names[i].name,
2069                                 rte_igbvf_stats_strings[i].name,
2070                                 sizeof(xstats_names[i].name));
2071                 }
2072         return IGBVF_NB_XSTATS;
2073 }
2074
2075 static int
2076 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2077                      unsigned n)
2078 {
2079         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2081                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2082         unsigned i;
2083
2084         if (n < IGBVF_NB_XSTATS)
2085                 return IGBVF_NB_XSTATS;
2086
2087         igbvf_read_stats_registers(hw, hw_stats);
2088
2089         if (!xstats)
2090                 return 0;
2091
2092         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2093                 xstats[i].id = i;
2094                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2095                         rte_igbvf_stats_strings[i].offset);
2096         }
2097
2098         return IGBVF_NB_XSTATS;
2099 }
2100
2101 static int
2102 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2103 {
2104         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2106                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2107
2108         igbvf_read_stats_registers(hw, hw_stats);
2109
2110         if (rte_stats == NULL)
2111                 return -EINVAL;
2112
2113         rte_stats->ipackets = hw_stats->gprc;
2114         rte_stats->ibytes = hw_stats->gorc;
2115         rte_stats->opackets = hw_stats->gptc;
2116         rte_stats->obytes = hw_stats->gotc;
2117         return 0;
2118 }
2119
2120 static int
2121 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2122 {
2123         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2124                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2125
2126         /* Sync HW register to the last stats */
2127         eth_igbvf_stats_get(dev, NULL);
2128
2129         /* reset HW current stats*/
2130         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2131                offsetof(struct e1000_vf_stats, gprc));
2132
2133         return 0;
2134 }
2135
2136 static int
2137 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2138                        size_t fw_size)
2139 {
2140         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141         struct e1000_fw_version fw;
2142         int ret;
2143
2144         e1000_get_fw_version(hw, &fw);
2145
2146         switch (hw->mac.type) {
2147         case e1000_i210:
2148         case e1000_i211:
2149                 if (!(e1000_get_flash_presence_i210(hw))) {
2150                         ret = snprintf(fw_version, fw_size,
2151                                  "%2d.%2d-%d",
2152                                  fw.invm_major, fw.invm_minor,
2153                                  fw.invm_img_type);
2154                         break;
2155                 }
2156                 /* fall through */
2157         default:
2158                 /* if option rom is valid, display its version too */
2159                 if (fw.or_valid) {
2160                         ret = snprintf(fw_version, fw_size,
2161                                  "%d.%d, 0x%08x, %d.%d.%d",
2162                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2163                                  fw.or_major, fw.or_build, fw.or_patch);
2164                 /* no option rom */
2165                 } else {
2166                         if (fw.etrack_id != 0X0000) {
2167                                 ret = snprintf(fw_version, fw_size,
2168                                          "%d.%d, 0x%08x",
2169                                          fw.eep_major, fw.eep_minor,
2170                                          fw.etrack_id);
2171                         } else {
2172                                 ret = snprintf(fw_version, fw_size,
2173                                          "%d.%d.%d",
2174                                          fw.eep_major, fw.eep_minor,
2175                                          fw.eep_build);
2176                         }
2177                 }
2178                 break;
2179         }
2180
2181         ret += 1; /* add the size of '\0' */
2182         if (fw_size < (u32)ret)
2183                 return ret;
2184         else
2185                 return 0;
2186 }
2187
2188 static int
2189 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2190 {
2191         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192
2193         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2194         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2195         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2196         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2197         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2198                                     dev_info->rx_queue_offload_capa;
2199         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2200         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2201                                     dev_info->tx_queue_offload_capa;
2202
2203         switch (hw->mac.type) {
2204         case e1000_82575:
2205                 dev_info->max_rx_queues = 4;
2206                 dev_info->max_tx_queues = 4;
2207                 dev_info->max_vmdq_pools = 0;
2208                 break;
2209
2210         case e1000_82576:
2211                 dev_info->max_rx_queues = 16;
2212                 dev_info->max_tx_queues = 16;
2213                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2214                 dev_info->vmdq_queue_num = 16;
2215                 break;
2216
2217         case e1000_82580:
2218                 dev_info->max_rx_queues = 8;
2219                 dev_info->max_tx_queues = 8;
2220                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2221                 dev_info->vmdq_queue_num = 8;
2222                 break;
2223
2224         case e1000_i350:
2225                 dev_info->max_rx_queues = 8;
2226                 dev_info->max_tx_queues = 8;
2227                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2228                 dev_info->vmdq_queue_num = 8;
2229                 break;
2230
2231         case e1000_i354:
2232                 dev_info->max_rx_queues = 8;
2233                 dev_info->max_tx_queues = 8;
2234                 break;
2235
2236         case e1000_i210:
2237                 dev_info->max_rx_queues = 4;
2238                 dev_info->max_tx_queues = 4;
2239                 dev_info->max_vmdq_pools = 0;
2240                 break;
2241
2242         case e1000_i211:
2243                 dev_info->max_rx_queues = 2;
2244                 dev_info->max_tx_queues = 2;
2245                 dev_info->max_vmdq_pools = 0;
2246                 break;
2247
2248         default:
2249                 /* Should not happen */
2250                 return -EINVAL;
2251         }
2252         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2253         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2254         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2255
2256         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2257                 .rx_thresh = {
2258                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2259                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2260                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2261                 },
2262                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2263                 .rx_drop_en = 0,
2264                 .offloads = 0,
2265         };
2266
2267         dev_info->default_txconf = (struct rte_eth_txconf) {
2268                 .tx_thresh = {
2269                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2270                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2271                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2272                 },
2273                 .offloads = 0,
2274         };
2275
2276         dev_info->rx_desc_lim = rx_desc_lim;
2277         dev_info->tx_desc_lim = tx_desc_lim;
2278
2279         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2280                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2281                         ETH_LINK_SPEED_1G;
2282
2283         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2284         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2285
2286         return 0;
2287 }
2288
2289 static const uint32_t *
2290 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2291 {
2292         static const uint32_t ptypes[] = {
2293                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2294                 RTE_PTYPE_L2_ETHER,
2295                 RTE_PTYPE_L3_IPV4,
2296                 RTE_PTYPE_L3_IPV4_EXT,
2297                 RTE_PTYPE_L3_IPV6,
2298                 RTE_PTYPE_L3_IPV6_EXT,
2299                 RTE_PTYPE_L4_TCP,
2300                 RTE_PTYPE_L4_UDP,
2301                 RTE_PTYPE_L4_SCTP,
2302                 RTE_PTYPE_TUNNEL_IP,
2303                 RTE_PTYPE_INNER_L3_IPV6,
2304                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2305                 RTE_PTYPE_INNER_L4_TCP,
2306                 RTE_PTYPE_INNER_L4_UDP,
2307                 RTE_PTYPE_UNKNOWN
2308         };
2309
2310         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2311             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2312                 return ptypes;
2313         return NULL;
2314 }
2315
2316 static int
2317 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2318 {
2319         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320
2321         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2322         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2323         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2324         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2325                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2326                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2327                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2328                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2329                                 DEV_TX_OFFLOAD_TCP_TSO;
2330         switch (hw->mac.type) {
2331         case e1000_vfadapt:
2332                 dev_info->max_rx_queues = 2;
2333                 dev_info->max_tx_queues = 2;
2334                 break;
2335         case e1000_vfadapt_i350:
2336                 dev_info->max_rx_queues = 1;
2337                 dev_info->max_tx_queues = 1;
2338                 break;
2339         default:
2340                 /* Should not happen */
2341                 return -EINVAL;
2342         }
2343
2344         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2345         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2346                                     dev_info->rx_queue_offload_capa;
2347         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2348         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2349                                     dev_info->tx_queue_offload_capa;
2350
2351         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2352                 .rx_thresh = {
2353                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2354                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2355                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2356                 },
2357                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2358                 .rx_drop_en = 0,
2359                 .offloads = 0,
2360         };
2361
2362         dev_info->default_txconf = (struct rte_eth_txconf) {
2363                 .tx_thresh = {
2364                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2365                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2366                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2367                 },
2368                 .offloads = 0,
2369         };
2370
2371         dev_info->rx_desc_lim = rx_desc_lim;
2372         dev_info->tx_desc_lim = tx_desc_lim;
2373
2374         return 0;
2375 }
2376
2377 /* return 0 means link status changed, -1 means not changed */
2378 static int
2379 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2380 {
2381         struct e1000_hw *hw =
2382                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383         struct rte_eth_link link;
2384         int link_check, count;
2385
2386         link_check = 0;
2387         hw->mac.get_link_status = 1;
2388
2389         /* possible wait-to-complete in up to 9 seconds */
2390         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2391                 /* Read the real link status */
2392                 switch (hw->phy.media_type) {
2393                 case e1000_media_type_copper:
2394                         /* Do the work to read phy */
2395                         e1000_check_for_link(hw);
2396                         link_check = !hw->mac.get_link_status;
2397                         break;
2398
2399                 case e1000_media_type_fiber:
2400                         e1000_check_for_link(hw);
2401                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2402                                       E1000_STATUS_LU);
2403                         break;
2404
2405                 case e1000_media_type_internal_serdes:
2406                         e1000_check_for_link(hw);
2407                         link_check = hw->mac.serdes_has_link;
2408                         break;
2409
2410                 /* VF device is type_unknown */
2411                 case e1000_media_type_unknown:
2412                         eth_igbvf_link_update(hw);
2413                         link_check = !hw->mac.get_link_status;
2414                         break;
2415
2416                 default:
2417                         break;
2418                 }
2419                 if (link_check || wait_to_complete == 0)
2420                         break;
2421                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2422         }
2423         memset(&link, 0, sizeof(link));
2424
2425         /* Now we check if a transition has happened */
2426         if (link_check) {
2427                 uint16_t duplex, speed;
2428                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2429                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2430                                 ETH_LINK_FULL_DUPLEX :
2431                                 ETH_LINK_HALF_DUPLEX;
2432                 link.link_speed = speed;
2433                 link.link_status = ETH_LINK_UP;
2434                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2435                                 ETH_LINK_SPEED_FIXED);
2436         } else if (!link_check) {
2437                 link.link_speed = 0;
2438                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2439                 link.link_status = ETH_LINK_DOWN;
2440                 link.link_autoneg = ETH_LINK_FIXED;
2441         }
2442
2443         return rte_eth_linkstatus_set(dev, &link);
2444 }
2445
2446 /*
2447  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2448  * For ASF and Pass Through versions of f/w this means
2449  * that the driver is loaded.
2450  */
2451 static void
2452 igb_hw_control_acquire(struct e1000_hw *hw)
2453 {
2454         uint32_t ctrl_ext;
2455
2456         /* Let firmware know the driver has taken over */
2457         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2458         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2459 }
2460
2461 /*
2462  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2463  * For ASF and Pass Through versions of f/w this means that the
2464  * driver is no longer loaded.
2465  */
2466 static void
2467 igb_hw_control_release(struct e1000_hw *hw)
2468 {
2469         uint32_t ctrl_ext;
2470
2471         /* Let firmware taken over control of h/w */
2472         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2473         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2474                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2475 }
2476
2477 /*
2478  * Bit of a misnomer, what this really means is
2479  * to enable OS management of the system... aka
2480  * to disable special hardware management features.
2481  */
2482 static void
2483 igb_init_manageability(struct e1000_hw *hw)
2484 {
2485         if (e1000_enable_mng_pass_thru(hw)) {
2486                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2487                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2488
2489                 /* disable hardware interception of ARP */
2490                 manc &= ~(E1000_MANC_ARP_EN);
2491
2492                 /* enable receiving management packets to the host */
2493                 manc |= E1000_MANC_EN_MNG2HOST;
2494                 manc2h |= 1 << 5;  /* Mng Port 623 */
2495                 manc2h |= 1 << 6;  /* Mng Port 664 */
2496                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2497                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2498         }
2499 }
2500
2501 static void
2502 igb_release_manageability(struct e1000_hw *hw)
2503 {
2504         if (e1000_enable_mng_pass_thru(hw)) {
2505                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2506
2507                 manc |= E1000_MANC_ARP_EN;
2508                 manc &= ~E1000_MANC_EN_MNG2HOST;
2509
2510                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2511         }
2512 }
2513
2514 static int
2515 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2516 {
2517         struct e1000_hw *hw =
2518                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519         uint32_t rctl;
2520
2521         rctl = E1000_READ_REG(hw, E1000_RCTL);
2522         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2523         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2524
2525         return 0;
2526 }
2527
2528 static int
2529 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2530 {
2531         struct e1000_hw *hw =
2532                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2533         uint32_t rctl;
2534
2535         rctl = E1000_READ_REG(hw, E1000_RCTL);
2536         rctl &= (~E1000_RCTL_UPE);
2537         if (dev->data->all_multicast == 1)
2538                 rctl |= E1000_RCTL_MPE;
2539         else
2540                 rctl &= (~E1000_RCTL_MPE);
2541         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2542
2543         return 0;
2544 }
2545
2546 static int
2547 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2548 {
2549         struct e1000_hw *hw =
2550                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2551         uint32_t rctl;
2552
2553         rctl = E1000_READ_REG(hw, E1000_RCTL);
2554         rctl |= E1000_RCTL_MPE;
2555         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2556
2557         return 0;
2558 }
2559
2560 static int
2561 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2562 {
2563         struct e1000_hw *hw =
2564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565         uint32_t rctl;
2566
2567         if (dev->data->promiscuous == 1)
2568                 return 0; /* must remain in all_multicast mode */
2569         rctl = E1000_READ_REG(hw, E1000_RCTL);
2570         rctl &= (~E1000_RCTL_MPE);
2571         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2572
2573         return 0;
2574 }
2575
2576 static int
2577 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2578 {
2579         struct e1000_hw *hw =
2580                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581         struct e1000_vfta * shadow_vfta =
2582                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2583         uint32_t vfta;
2584         uint32_t vid_idx;
2585         uint32_t vid_bit;
2586
2587         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2588                               E1000_VFTA_ENTRY_MASK);
2589         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2590         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2591         if (on)
2592                 vfta |= vid_bit;
2593         else
2594                 vfta &= ~vid_bit;
2595         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2596
2597         /* update local VFTA copy */
2598         shadow_vfta->vfta[vid_idx] = vfta;
2599
2600         return 0;
2601 }
2602
2603 static int
2604 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2605                       enum rte_vlan_type vlan_type,
2606                       uint16_t tpid)
2607 {
2608         struct e1000_hw *hw =
2609                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610         uint32_t reg, qinq;
2611
2612         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2613         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2614
2615         /* only outer TPID of double VLAN can be configured*/
2616         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2617                 reg = E1000_READ_REG(hw, E1000_VET);
2618                 reg = (reg & (~E1000_VET_VET_EXT)) |
2619                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2620                 E1000_WRITE_REG(hw, E1000_VET, reg);
2621
2622                 return 0;
2623         }
2624
2625         /* all other TPID values are read-only*/
2626         PMD_DRV_LOG(ERR, "Not supported");
2627
2628         return -ENOTSUP;
2629 }
2630
2631 static void
2632 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2633 {
2634         struct e1000_hw *hw =
2635                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636         uint32_t reg;
2637
2638         /* Filter Table Disable */
2639         reg = E1000_READ_REG(hw, E1000_RCTL);
2640         reg &= ~E1000_RCTL_CFIEN;
2641         reg &= ~E1000_RCTL_VFE;
2642         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2643 }
2644
2645 static void
2646 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2647 {
2648         struct e1000_hw *hw =
2649                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2650         struct e1000_vfta * shadow_vfta =
2651                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2652         uint32_t reg;
2653         int i;
2654
2655         /* Filter Table Enable, CFI not used for packet acceptance */
2656         reg = E1000_READ_REG(hw, E1000_RCTL);
2657         reg &= ~E1000_RCTL_CFIEN;
2658         reg |= E1000_RCTL_VFE;
2659         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2660
2661         /* restore VFTA table */
2662         for (i = 0; i < IGB_VFTA_SIZE; i++)
2663                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2664 }
2665
2666 static void
2667 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2668 {
2669         struct e1000_hw *hw =
2670                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671         uint32_t reg;
2672
2673         /* VLAN Mode Disable */
2674         reg = E1000_READ_REG(hw, E1000_CTRL);
2675         reg &= ~E1000_CTRL_VME;
2676         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2677 }
2678
2679 static void
2680 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2681 {
2682         struct e1000_hw *hw =
2683                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684         uint32_t reg;
2685
2686         /* VLAN Mode Enable */
2687         reg = E1000_READ_REG(hw, E1000_CTRL);
2688         reg |= E1000_CTRL_VME;
2689         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2690 }
2691
2692 static void
2693 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2694 {
2695         struct e1000_hw *hw =
2696                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697         uint32_t reg;
2698
2699         /* CTRL_EXT: Extended VLAN */
2700         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2701         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2702         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2703
2704         /* Update maximum packet length */
2705         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2706                 E1000_WRITE_REG(hw, E1000_RLPML,
2707                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2708                                                 VLAN_TAG_SIZE);
2709 }
2710
2711 static void
2712 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2713 {
2714         struct e1000_hw *hw =
2715                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2716         uint32_t reg;
2717
2718         /* CTRL_EXT: Extended VLAN */
2719         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2720         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2721         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2722
2723         /* Update maximum packet length */
2724         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2725                 E1000_WRITE_REG(hw, E1000_RLPML,
2726                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2727                                                 2 * VLAN_TAG_SIZE);
2728 }
2729
2730 static int
2731 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2732 {
2733         struct rte_eth_rxmode *rxmode;
2734
2735         rxmode = &dev->data->dev_conf.rxmode;
2736         if(mask & ETH_VLAN_STRIP_MASK){
2737                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2738                         igb_vlan_hw_strip_enable(dev);
2739                 else
2740                         igb_vlan_hw_strip_disable(dev);
2741         }
2742
2743         if(mask & ETH_VLAN_FILTER_MASK){
2744                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2745                         igb_vlan_hw_filter_enable(dev);
2746                 else
2747                         igb_vlan_hw_filter_disable(dev);
2748         }
2749
2750         if(mask & ETH_VLAN_EXTEND_MASK){
2751                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2752                         igb_vlan_hw_extend_enable(dev);
2753                 else
2754                         igb_vlan_hw_extend_disable(dev);
2755         }
2756
2757         return 0;
2758 }
2759
2760
2761 /**
2762  * It enables the interrupt mask and then enable the interrupt.
2763  *
2764  * @param dev
2765  *  Pointer to struct rte_eth_dev.
2766  * @param on
2767  *  Enable or Disable
2768  *
2769  * @return
2770  *  - On success, zero.
2771  *  - On failure, a negative value.
2772  */
2773 static int
2774 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2775 {
2776         struct e1000_interrupt *intr =
2777                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2778
2779         if (on)
2780                 intr->mask |= E1000_ICR_LSC;
2781         else
2782                 intr->mask &= ~E1000_ICR_LSC;
2783
2784         return 0;
2785 }
2786
2787 /* It clears the interrupt causes and enables the interrupt.
2788  * It will be called once only during nic initialized.
2789  *
2790  * @param dev
2791  *  Pointer to struct rte_eth_dev.
2792  *
2793  * @return
2794  *  - On success, zero.
2795  *  - On failure, a negative value.
2796  */
2797 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2798 {
2799         uint32_t mask, regval;
2800         int ret;
2801         struct e1000_hw *hw =
2802                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2804         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2805         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2806         struct rte_eth_dev_info dev_info;
2807
2808         memset(&dev_info, 0, sizeof(dev_info));
2809         ret = eth_igb_infos_get(dev, &dev_info);
2810         if (ret != 0)
2811                 return ret;
2812
2813         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2814         regval = E1000_READ_REG(hw, E1000_EIMS);
2815         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2816
2817         return 0;
2818 }
2819
2820 /*
2821  * It reads ICR and gets interrupt causes, check it and set a bit flag
2822  * to update link status.
2823  *
2824  * @param dev
2825  *  Pointer to struct rte_eth_dev.
2826  *
2827  * @return
2828  *  - On success, zero.
2829  *  - On failure, a negative value.
2830  */
2831 static int
2832 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2833 {
2834         uint32_t icr;
2835         struct e1000_hw *hw =
2836                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837         struct e1000_interrupt *intr =
2838                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2839
2840         igb_intr_disable(dev);
2841
2842         /* read-on-clear nic registers here */
2843         icr = E1000_READ_REG(hw, E1000_ICR);
2844
2845         intr->flags = 0;
2846         if (icr & E1000_ICR_LSC) {
2847                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2848         }
2849
2850         if (icr & E1000_ICR_VMMB)
2851                 intr->flags |= E1000_FLAG_MAILBOX;
2852
2853         return 0;
2854 }
2855
2856 /*
2857  * It executes link_update after knowing an interrupt is prsent.
2858  *
2859  * @param dev
2860  *  Pointer to struct rte_eth_dev.
2861  *
2862  * @return
2863  *  - On success, zero.
2864  *  - On failure, a negative value.
2865  */
2866 static int
2867 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2868                          struct rte_intr_handle *intr_handle)
2869 {
2870         struct e1000_hw *hw =
2871                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872         struct e1000_interrupt *intr =
2873                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2874         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2875         struct rte_eth_link link;
2876         int ret;
2877
2878         if (intr->flags & E1000_FLAG_MAILBOX) {
2879                 igb_pf_mbx_process(dev);
2880                 intr->flags &= ~E1000_FLAG_MAILBOX;
2881         }
2882
2883         igb_intr_enable(dev);
2884         rte_intr_ack(intr_handle);
2885
2886         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2887                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2888
2889                 /* set get_link_status to check register later */
2890                 hw->mac.get_link_status = 1;
2891                 ret = eth_igb_link_update(dev, 0);
2892
2893                 /* check if link has changed */
2894                 if (ret < 0)
2895                         return 0;
2896
2897                 rte_eth_linkstatus_get(dev, &link);
2898                 if (link.link_status) {
2899                         PMD_INIT_LOG(INFO,
2900                                      " Port %d: Link Up - speed %u Mbps - %s",
2901                                      dev->data->port_id,
2902                                      (unsigned)link.link_speed,
2903                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2904                                      "full-duplex" : "half-duplex");
2905                 } else {
2906                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2907                                      dev->data->port_id);
2908                 }
2909
2910                 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2911                              pci_dev->addr.domain,
2912                              pci_dev->addr.bus,
2913                              pci_dev->addr.devid,
2914                              pci_dev->addr.function);
2915                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2916         }
2917
2918         return 0;
2919 }
2920
2921 /**
2922  * Interrupt handler which shall be registered at first.
2923  *
2924  * @param handle
2925  *  Pointer to interrupt handle.
2926  * @param param
2927  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2928  *
2929  * @return
2930  *  void
2931  */
2932 static void
2933 eth_igb_interrupt_handler(void *param)
2934 {
2935         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2936
2937         eth_igb_interrupt_get_status(dev);
2938         eth_igb_interrupt_action(dev, dev->intr_handle);
2939 }
2940
2941 static int
2942 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2943 {
2944         uint32_t eicr;
2945         struct e1000_hw *hw =
2946                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947         struct e1000_interrupt *intr =
2948                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2949
2950         igbvf_intr_disable(hw);
2951
2952         /* read-on-clear nic registers here */
2953         eicr = E1000_READ_REG(hw, E1000_EICR);
2954         intr->flags = 0;
2955
2956         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2957                 intr->flags |= E1000_FLAG_MAILBOX;
2958
2959         return 0;
2960 }
2961
2962 void igbvf_mbx_process(struct rte_eth_dev *dev)
2963 {
2964         struct e1000_hw *hw =
2965                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2966         struct e1000_mbx_info *mbx = &hw->mbx;
2967         u32 in_msg = 0;
2968
2969         /* peek the message first */
2970         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2971
2972         /* PF reset VF event */
2973         if (in_msg == E1000_PF_CONTROL_MSG) {
2974                 /* dummy mbx read to ack pf */
2975                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2976                         return;
2977                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2978                                              NULL);
2979         }
2980 }
2981
2982 static int
2983 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2984 {
2985         struct e1000_interrupt *intr =
2986                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2987
2988         if (intr->flags & E1000_FLAG_MAILBOX) {
2989                 igbvf_mbx_process(dev);
2990                 intr->flags &= ~E1000_FLAG_MAILBOX;
2991         }
2992
2993         igbvf_intr_enable(dev);
2994         rte_intr_ack(intr_handle);
2995
2996         return 0;
2997 }
2998
2999 static void
3000 eth_igbvf_interrupt_handler(void *param)
3001 {
3002         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3003
3004         eth_igbvf_interrupt_get_status(dev);
3005         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3006 }
3007
3008 static int
3009 eth_igb_led_on(struct rte_eth_dev *dev)
3010 {
3011         struct e1000_hw *hw;
3012
3013         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3014         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3015 }
3016
3017 static int
3018 eth_igb_led_off(struct rte_eth_dev *dev)
3019 {
3020         struct e1000_hw *hw;
3021
3022         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3024 }
3025
3026 static int
3027 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3028 {
3029         struct e1000_hw *hw;
3030         uint32_t ctrl;
3031         int tx_pause;
3032         int rx_pause;
3033
3034         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3035         fc_conf->pause_time = hw->fc.pause_time;
3036         fc_conf->high_water = hw->fc.high_water;
3037         fc_conf->low_water = hw->fc.low_water;
3038         fc_conf->send_xon = hw->fc.send_xon;
3039         fc_conf->autoneg = hw->mac.autoneg;
3040
3041         /*
3042          * Return rx_pause and tx_pause status according to actual setting of
3043          * the TFCE and RFCE bits in the CTRL register.
3044          */
3045         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3046         if (ctrl & E1000_CTRL_TFCE)
3047                 tx_pause = 1;
3048         else
3049                 tx_pause = 0;
3050
3051         if (ctrl & E1000_CTRL_RFCE)
3052                 rx_pause = 1;
3053         else
3054                 rx_pause = 0;
3055
3056         if (rx_pause && tx_pause)
3057                 fc_conf->mode = RTE_FC_FULL;
3058         else if (rx_pause)
3059                 fc_conf->mode = RTE_FC_RX_PAUSE;
3060         else if (tx_pause)
3061                 fc_conf->mode = RTE_FC_TX_PAUSE;
3062         else
3063                 fc_conf->mode = RTE_FC_NONE;
3064
3065         return 0;
3066 }
3067
3068 static int
3069 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3070 {
3071         struct e1000_hw *hw;
3072         int err;
3073         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3074                 e1000_fc_none,
3075                 e1000_fc_rx_pause,
3076                 e1000_fc_tx_pause,
3077                 e1000_fc_full
3078         };
3079         uint32_t rx_buf_size;
3080         uint32_t max_high_water;
3081         uint32_t rctl;
3082
3083         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3084         if (fc_conf->autoneg != hw->mac.autoneg)
3085                 return -ENOTSUP;
3086         rx_buf_size = igb_get_rx_buffer_size(hw);
3087         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3088
3089         /* At least reserve one Ethernet frame for watermark */
3090         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3091         if ((fc_conf->high_water > max_high_water) ||
3092             (fc_conf->high_water < fc_conf->low_water)) {
3093                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3094                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3095                 return -EINVAL;
3096         }
3097
3098         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3099         hw->fc.pause_time     = fc_conf->pause_time;
3100         hw->fc.high_water     = fc_conf->high_water;
3101         hw->fc.low_water      = fc_conf->low_water;
3102         hw->fc.send_xon       = fc_conf->send_xon;
3103
3104         err = e1000_setup_link_generic(hw);
3105         if (err == E1000_SUCCESS) {
3106
3107                 /* check if we want to forward MAC frames - driver doesn't have native
3108                  * capability to do that, so we'll write the registers ourselves */
3109
3110                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3111
3112                 /* set or clear MFLCN.PMCF bit depending on configuration */
3113                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3114                         rctl |= E1000_RCTL_PMCF;
3115                 else
3116                         rctl &= ~E1000_RCTL_PMCF;
3117
3118                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3119                 E1000_WRITE_FLUSH(hw);
3120
3121                 return 0;
3122         }
3123
3124         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3125         return -EIO;
3126 }
3127
3128 #define E1000_RAH_POOLSEL_SHIFT      (18)
3129 static int
3130 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3131                 uint32_t index, uint32_t pool)
3132 {
3133         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3134         uint32_t rah;
3135
3136         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3137         rah = E1000_READ_REG(hw, E1000_RAH(index));
3138         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3139         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3140         return 0;
3141 }
3142
3143 static void
3144 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3145 {
3146         uint8_t addr[RTE_ETHER_ADDR_LEN];
3147         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3148
3149         memset(addr, 0, sizeof(addr));
3150
3151         e1000_rar_set(hw, addr, index);
3152 }
3153
3154 static int
3155 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3156                                 struct rte_ether_addr *addr)
3157 {
3158         eth_igb_rar_clear(dev, 0);
3159         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3160
3161         return 0;
3162 }
3163 /*
3164  * Virtual Function operations
3165  */
3166 static void
3167 igbvf_intr_disable(struct e1000_hw *hw)
3168 {
3169         PMD_INIT_FUNC_TRACE();
3170
3171         /* Clear interrupt mask to stop from interrupts being generated */
3172         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3173
3174         E1000_WRITE_FLUSH(hw);
3175 }
3176
3177 static void
3178 igbvf_stop_adapter(struct rte_eth_dev *dev)
3179 {
3180         u32 reg_val;
3181         u16 i;
3182         struct rte_eth_dev_info dev_info;
3183         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184         int ret;
3185
3186         memset(&dev_info, 0, sizeof(dev_info));
3187         ret = eth_igbvf_infos_get(dev, &dev_info);
3188         if (ret != 0)
3189                 return;
3190
3191         /* Clear interrupt mask to stop from interrupts being generated */
3192         igbvf_intr_disable(hw);
3193
3194         /* Clear any pending interrupts, flush previous writes */
3195         E1000_READ_REG(hw, E1000_EICR);
3196
3197         /* Disable the transmit unit.  Each queue must be disabled. */
3198         for (i = 0; i < dev_info.max_tx_queues; i++)
3199                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3200
3201         /* Disable the receive unit by stopping each queue */
3202         for (i = 0; i < dev_info.max_rx_queues; i++) {
3203                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3204                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3205                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3206                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3207                         ;
3208         }
3209
3210         /* flush all queues disables */
3211         E1000_WRITE_FLUSH(hw);
3212         msec_delay(2);
3213 }
3214
3215 static int eth_igbvf_link_update(struct e1000_hw *hw)
3216 {
3217         struct e1000_mbx_info *mbx = &hw->mbx;
3218         struct e1000_mac_info *mac = &hw->mac;
3219         int ret_val = E1000_SUCCESS;
3220
3221         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3222
3223         /*
3224          * We only want to run this if there has been a rst asserted.
3225          * in this case that could mean a link change, device reset,
3226          * or a virtual function reset
3227          */
3228
3229         /* If we were hit with a reset or timeout drop the link */
3230         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3231                 mac->get_link_status = TRUE;
3232
3233         if (!mac->get_link_status)
3234                 goto out;
3235
3236         /* if link status is down no point in checking to see if pf is up */
3237         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3238                 goto out;
3239
3240         /* if we passed all the tests above then the link is up and we no
3241          * longer need to check for link */
3242         mac->get_link_status = FALSE;
3243
3244 out:
3245         return ret_val;
3246 }
3247
3248
3249 static int
3250 igbvf_dev_configure(struct rte_eth_dev *dev)
3251 {
3252         struct rte_eth_conf* conf = &dev->data->dev_conf;
3253
3254         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3255                      dev->data->port_id);
3256
3257         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3258                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3259
3260         /*
3261          * VF has no ability to enable/disable HW CRC
3262          * Keep the persistent behavior the same as Host PF
3263          */
3264 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3265         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3266                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3267                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3268         }
3269 #else
3270         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3271                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3272                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3273         }
3274 #endif
3275
3276         return 0;
3277 }
3278
3279 static int
3280 igbvf_dev_start(struct rte_eth_dev *dev)
3281 {
3282         struct e1000_hw *hw =
3283                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3284         struct e1000_adapter *adapter =
3285                 E1000_DEV_PRIVATE(dev->data->dev_private);
3286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3288         int ret;
3289         uint32_t intr_vector = 0;
3290
3291         PMD_INIT_FUNC_TRACE();
3292
3293         hw->mac.ops.reset_hw(hw);
3294         adapter->stopped = 0;
3295
3296         /* Set all vfta */
3297         igbvf_set_vfta_all(dev,1);
3298
3299         eth_igbvf_tx_init(dev);
3300
3301         /* This can fail when allocating mbufs for descriptor rings */
3302         ret = eth_igbvf_rx_init(dev);
3303         if (ret) {
3304                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3305                 igb_dev_clear_queues(dev);
3306                 return ret;
3307         }
3308
3309         /* check and configure queue intr-vector mapping */
3310         if (rte_intr_cap_multiple(intr_handle) &&
3311             dev->data->dev_conf.intr_conf.rxq) {
3312                 intr_vector = dev->data->nb_rx_queues;
3313                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3314                 if (ret)
3315                         return ret;
3316         }
3317
3318         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3319                 intr_handle->intr_vec =
3320                         rte_zmalloc("intr_vec",
3321                                     dev->data->nb_rx_queues * sizeof(int), 0);
3322                 if (!intr_handle->intr_vec) {
3323                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3324                                      " intr_vec", dev->data->nb_rx_queues);
3325                         return -ENOMEM;
3326                 }
3327         }
3328
3329         eth_igbvf_configure_msix_intr(dev);
3330
3331         /* enable uio/vfio intr/eventfd mapping */
3332         rte_intr_enable(intr_handle);
3333
3334         /* resume enabled intr since hw reset */
3335         igbvf_intr_enable(dev);
3336
3337         return 0;
3338 }
3339
3340 static int
3341 igbvf_dev_stop(struct rte_eth_dev *dev)
3342 {
3343         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3344         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3345         struct e1000_adapter *adapter =
3346                 E1000_DEV_PRIVATE(dev->data->dev_private);
3347
3348         if (adapter->stopped)
3349                 return 0;
3350
3351         PMD_INIT_FUNC_TRACE();
3352
3353         igbvf_stop_adapter(dev);
3354
3355         /*
3356           * Clear what we set, but we still keep shadow_vfta to
3357           * restore after device starts
3358           */
3359         igbvf_set_vfta_all(dev,0);
3360
3361         igb_dev_clear_queues(dev);
3362
3363         /* disable intr eventfd mapping */
3364         rte_intr_disable(intr_handle);
3365
3366         /* Clean datapath event and queue/vec mapping */
3367         rte_intr_efd_disable(intr_handle);
3368         if (intr_handle->intr_vec) {
3369                 rte_free(intr_handle->intr_vec);
3370                 intr_handle->intr_vec = NULL;
3371         }
3372
3373         adapter->stopped = true;
3374         dev->data->dev_started = 0;
3375
3376         return 0;
3377 }
3378
3379 static int
3380 igbvf_dev_close(struct rte_eth_dev *dev)
3381 {
3382         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3383         struct rte_ether_addr addr;
3384         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3385         int ret;
3386
3387         PMD_INIT_FUNC_TRACE();
3388
3389         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3390                 return 0;
3391
3392         e1000_reset_hw(hw);
3393
3394         ret = igbvf_dev_stop(dev);
3395         if (ret != 0)
3396                 return ret;
3397
3398         igb_dev_free_queues(dev);
3399
3400         /**
3401          * reprogram the RAR with a zero mac address,
3402          * to ensure that the VF traffic goes to the PF
3403          * after stop, close and detach of the VF.
3404          **/
3405
3406         memset(&addr, 0, sizeof(addr));
3407         igbvf_default_mac_addr_set(dev, &addr);
3408
3409         rte_intr_callback_unregister(&pci_dev->intr_handle,
3410                                      eth_igbvf_interrupt_handler,
3411                                      (void *)dev);
3412
3413         return 0;
3414 }
3415
3416 static int
3417 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3418 {
3419         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3420
3421         /* Set both unicast and multicast promisc */
3422         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3423
3424         return 0;
3425 }
3426
3427 static int
3428 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3429 {
3430         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3431
3432         /* If in allmulticast mode leave multicast promisc */
3433         if (dev->data->all_multicast == 1)
3434                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3435         else
3436                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3437
3438         return 0;
3439 }
3440
3441 static int
3442 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3443 {
3444         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445
3446         /* In promiscuous mode multicast promisc already set */
3447         if (dev->data->promiscuous == 0)
3448                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3449
3450         return 0;
3451 }
3452
3453 static int
3454 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3455 {
3456         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3457
3458         /* In promiscuous mode leave multicast promisc enabled */
3459         if (dev->data->promiscuous == 0)
3460                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3461
3462         return 0;
3463 }
3464
3465 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3466 {
3467         struct e1000_mbx_info *mbx = &hw->mbx;
3468         uint32_t msgbuf[2];
3469         s32 err;
3470
3471         /* After set vlan, vlan strip will also be enabled in igb driver*/
3472         msgbuf[0] = E1000_VF_SET_VLAN;
3473         msgbuf[1] = vid;
3474         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3475         if (on)
3476                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3477
3478         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3479         if (err)
3480                 goto mbx_err;
3481
3482         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3483         if (err)
3484                 goto mbx_err;
3485
3486         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3487         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3488                 err = -EINVAL;
3489
3490 mbx_err:
3491         return err;
3492 }
3493
3494 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3495 {
3496         struct e1000_hw *hw =
3497                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3498         struct e1000_vfta * shadow_vfta =
3499                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3500         int i = 0, j = 0, vfta = 0, mask = 1;
3501
3502         for (i = 0; i < IGB_VFTA_SIZE; i++){
3503                 vfta = shadow_vfta->vfta[i];
3504                 if(vfta){
3505                         mask = 1;
3506                         for (j = 0; j < 32; j++){
3507                                 if(vfta & mask)
3508                                         igbvf_set_vfta(hw,
3509                                                 (uint16_t)((i<<5)+j), on);
3510                                 mask<<=1;
3511                         }
3512                 }
3513         }
3514
3515 }
3516
3517 static int
3518 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3519 {
3520         struct e1000_hw *hw =
3521                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3522         struct e1000_vfta * shadow_vfta =
3523                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3524         uint32_t vid_idx = 0;
3525         uint32_t vid_bit = 0;
3526         int ret = 0;
3527
3528         PMD_INIT_FUNC_TRACE();
3529
3530         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3531         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3532         if(ret){
3533                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3534                 return ret;
3535         }
3536         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3537         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3538
3539         /*Save what we set and retore it after device reset*/
3540         if (on)
3541                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3542         else
3543                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3544
3545         return 0;
3546 }
3547
3548 static int
3549 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3550 {
3551         struct e1000_hw *hw =
3552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3553
3554         /* index is not used by rar_set() */
3555         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3556         return 0;
3557 }
3558
3559
3560 static int
3561 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3562                         struct rte_eth_rss_reta_entry64 *reta_conf,
3563                         uint16_t reta_size)
3564 {
3565         uint8_t i, j, mask;
3566         uint32_t reta, r;
3567         uint16_t idx, shift;
3568         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3569
3570         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3571                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3572                         "(%d) doesn't match the number hardware can supported "
3573                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3574                 return -EINVAL;
3575         }
3576
3577         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3578                 idx = i / RTE_RETA_GROUP_SIZE;
3579                 shift = i % RTE_RETA_GROUP_SIZE;
3580                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3581                                                 IGB_4_BIT_MASK);
3582                 if (!mask)
3583                         continue;
3584                 if (mask == IGB_4_BIT_MASK)
3585                         r = 0;
3586                 else
3587                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3588                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3589                         if (mask & (0x1 << j))
3590                                 reta |= reta_conf[idx].reta[shift + j] <<
3591                                                         (CHAR_BIT * j);
3592                         else
3593                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3594                 }
3595                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3596         }
3597
3598         return 0;
3599 }
3600
3601 static int
3602 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3603                        struct rte_eth_rss_reta_entry64 *reta_conf,
3604                        uint16_t reta_size)
3605 {
3606         uint8_t i, j, mask;
3607         uint32_t reta;
3608         uint16_t idx, shift;
3609         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3610
3611         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3612                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3613                         "(%d) doesn't match the number hardware can supported "
3614                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3615                 return -EINVAL;
3616         }
3617
3618         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3619                 idx = i / RTE_RETA_GROUP_SIZE;
3620                 shift = i % RTE_RETA_GROUP_SIZE;
3621                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3622                                                 IGB_4_BIT_MASK);
3623                 if (!mask)
3624                         continue;
3625                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3626                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3627                         if (mask & (0x1 << j))
3628                                 reta_conf[idx].reta[shift + j] =
3629                                         ((reta >> (CHAR_BIT * j)) &
3630                                                 IGB_8_BIT_MASK);
3631                 }
3632         }
3633
3634         return 0;
3635 }
3636
3637 int
3638 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3639                         struct rte_eth_syn_filter *filter,
3640                         bool add)
3641 {
3642         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3643         struct e1000_filter_info *filter_info =
3644                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3645         uint32_t synqf, rfctl;
3646
3647         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3648                 return -EINVAL;
3649
3650         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3651
3652         if (add) {
3653                 if (synqf & E1000_SYN_FILTER_ENABLE)
3654                         return -EINVAL;
3655
3656                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3657                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3658
3659                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3660                 if (filter->hig_pri)
3661                         rfctl |= E1000_RFCTL_SYNQFP;
3662                 else
3663                         rfctl &= ~E1000_RFCTL_SYNQFP;
3664
3665                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3666         } else {
3667                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3668                         return -ENOENT;
3669                 synqf = 0;
3670         }
3671
3672         filter_info->syn_info = synqf;
3673         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3674         E1000_WRITE_FLUSH(hw);
3675         return 0;
3676 }
3677
3678 static int
3679 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3680                         struct rte_eth_syn_filter *filter)
3681 {
3682         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3683         uint32_t synqf, rfctl;
3684
3685         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3686         if (synqf & E1000_SYN_FILTER_ENABLE) {
3687                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3688                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3689                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3690                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3691                 return 0;
3692         }
3693
3694         return -ENOENT;
3695 }
3696
3697 static int
3698 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3699                         enum rte_filter_op filter_op,
3700                         void *arg)
3701 {
3702         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3703         int ret;
3704
3705         MAC_TYPE_FILTER_SUP(hw->mac.type);
3706
3707         if (filter_op == RTE_ETH_FILTER_NOP)
3708                 return 0;
3709
3710         if (arg == NULL) {
3711                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3712                             filter_op);
3713                 return -EINVAL;
3714         }
3715
3716         switch (filter_op) {
3717         case RTE_ETH_FILTER_ADD:
3718                 ret = eth_igb_syn_filter_set(dev,
3719                                 (struct rte_eth_syn_filter *)arg,
3720                                 TRUE);
3721                 break;
3722         case RTE_ETH_FILTER_DELETE:
3723                 ret = eth_igb_syn_filter_set(dev,
3724                                 (struct rte_eth_syn_filter *)arg,
3725                                 FALSE);
3726                 break;
3727         case RTE_ETH_FILTER_GET:
3728                 ret = eth_igb_syn_filter_get(dev,
3729                                 (struct rte_eth_syn_filter *)arg);
3730                 break;
3731         default:
3732                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3733                 ret = -EINVAL;
3734                 break;
3735         }
3736
3737         return ret;
3738 }
3739
3740 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3741 static inline int
3742 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3743                         struct e1000_2tuple_filter_info *filter_info)
3744 {
3745         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3746                 return -EINVAL;
3747         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3748                 return -EINVAL;  /* filter index is out of range. */
3749         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3750                 return -EINVAL;  /* flags is invalid. */
3751
3752         switch (filter->dst_port_mask) {
3753         case UINT16_MAX:
3754                 filter_info->dst_port_mask = 0;
3755                 filter_info->dst_port = filter->dst_port;
3756                 break;
3757         case 0:
3758                 filter_info->dst_port_mask = 1;
3759                 break;
3760         default:
3761                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3762                 return -EINVAL;
3763         }
3764
3765         switch (filter->proto_mask) {
3766         case UINT8_MAX:
3767                 filter_info->proto_mask = 0;
3768                 filter_info->proto = filter->proto;
3769                 break;
3770         case 0:
3771                 filter_info->proto_mask = 1;
3772                 break;
3773         default:
3774                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3775                 return -EINVAL;
3776         }
3777
3778         filter_info->priority = (uint8_t)filter->priority;
3779         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3780                 filter_info->tcp_flags = filter->tcp_flags;
3781         else
3782                 filter_info->tcp_flags = 0;
3783
3784         return 0;
3785 }
3786
3787 static inline struct e1000_2tuple_filter *
3788 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3789                         struct e1000_2tuple_filter_info *key)
3790 {
3791         struct e1000_2tuple_filter *it;
3792
3793         TAILQ_FOREACH(it, filter_list, entries) {
3794                 if (memcmp(key, &it->filter_info,
3795                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3796                         return it;
3797                 }
3798         }
3799         return NULL;
3800 }
3801
3802 /* inject a igb 2tuple filter to HW */
3803 static inline void
3804 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3805                            struct e1000_2tuple_filter *filter)
3806 {
3807         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3808         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3809         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3810         int i;
3811
3812         i = filter->index;
3813         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3814         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3815                 imir |= E1000_IMIR_PORT_BP;
3816         else
3817                 imir &= ~E1000_IMIR_PORT_BP;
3818
3819         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3820
3821         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3822         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3823         ttqf |= (uint32_t)(filter->filter_info.proto &
3824                                                 E1000_TTQF_PROTOCOL_MASK);
3825         if (filter->filter_info.proto_mask == 0)
3826                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3827
3828         /* tcp flags bits setting. */
3829         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3830                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3831                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3832                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3833                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3834                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3835                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3836                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3837                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3838                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3839                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3840                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3841                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3842         } else {
3843                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3844         }
3845         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3846         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3847         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3848 }
3849
3850 /*
3851  * igb_add_2tuple_filter - add a 2tuple filter
3852  *
3853  * @param
3854  * dev: Pointer to struct rte_eth_dev.
3855  * ntuple_filter: ponter to the filter that will be added.
3856  *
3857  * @return
3858  *    - On success, zero.
3859  *    - On failure, a negative value.
3860  */
3861 static int
3862 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3863                         struct rte_eth_ntuple_filter *ntuple_filter)
3864 {
3865         struct e1000_filter_info *filter_info =
3866                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3867         struct e1000_2tuple_filter *filter;
3868         int i, ret;
3869
3870         filter = rte_zmalloc("e1000_2tuple_filter",
3871                         sizeof(struct e1000_2tuple_filter), 0);
3872         if (filter == NULL)
3873                 return -ENOMEM;
3874
3875         ret = ntuple_filter_to_2tuple(ntuple_filter,
3876                                       &filter->filter_info);
3877         if (ret < 0) {
3878                 rte_free(filter);
3879                 return ret;
3880         }
3881         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3882                                          &filter->filter_info) != NULL) {
3883                 PMD_DRV_LOG(ERR, "filter exists.");
3884                 rte_free(filter);
3885                 return -EEXIST;
3886         }
3887         filter->queue = ntuple_filter->queue;
3888
3889         /*
3890          * look for an unused 2tuple filter index,
3891          * and insert the filter to list.
3892          */
3893         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3894                 if (!(filter_info->twotuple_mask & (1 << i))) {
3895                         filter_info->twotuple_mask |= 1 << i;
3896                         filter->index = i;
3897                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3898                                           filter,
3899                                           entries);
3900                         break;
3901                 }
3902         }
3903         if (i >= E1000_MAX_TTQF_FILTERS) {
3904                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3905                 rte_free(filter);
3906                 return -ENOSYS;
3907         }
3908
3909         igb_inject_2uple_filter(dev, filter);
3910         return 0;
3911 }
3912
3913 int
3914 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3915                         struct e1000_2tuple_filter *filter)
3916 {
3917         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3918         struct e1000_filter_info *filter_info =
3919                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3920
3921         filter_info->twotuple_mask &= ~(1 << filter->index);
3922         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3923         rte_free(filter);
3924
3925         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3926         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3927         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3928         return 0;
3929 }
3930
3931 /*
3932  * igb_remove_2tuple_filter - remove a 2tuple filter
3933  *
3934  * @param
3935  * dev: Pointer to struct rte_eth_dev.
3936  * ntuple_filter: ponter to the filter that will be removed.
3937  *
3938  * @return
3939  *    - On success, zero.
3940  *    - On failure, a negative value.
3941  */
3942 static int
3943 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3944                         struct rte_eth_ntuple_filter *ntuple_filter)
3945 {
3946         struct e1000_filter_info *filter_info =
3947                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3948         struct e1000_2tuple_filter_info filter_2tuple;
3949         struct e1000_2tuple_filter *filter;
3950         int ret;
3951
3952         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3953         ret = ntuple_filter_to_2tuple(ntuple_filter,
3954                                       &filter_2tuple);
3955         if (ret < 0)
3956                 return ret;
3957
3958         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3959                                          &filter_2tuple);
3960         if (filter == NULL) {
3961                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3962                 return -ENOENT;
3963         }
3964
3965         igb_delete_2tuple_filter(dev, filter);
3966
3967         return 0;
3968 }
3969
3970 /* inject a igb flex filter to HW */
3971 static inline void
3972 igb_inject_flex_filter(struct rte_eth_dev *dev,
3973                            struct e1000_flex_filter *filter)
3974 {
3975         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3976         uint32_t wufc, queueing;
3977         uint32_t reg_off;
3978         uint8_t i, j = 0;
3979
3980         wufc = E1000_READ_REG(hw, E1000_WUFC);
3981         if (filter->index < E1000_MAX_FHFT)
3982                 reg_off = E1000_FHFT(filter->index);
3983         else
3984                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3985
3986         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3987                         (E1000_WUFC_FLX0 << filter->index));
3988         queueing = filter->filter_info.len |
3989                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3990                 (filter->filter_info.priority <<
3991                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3992         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3993                         queueing);
3994
3995         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3996                 E1000_WRITE_REG(hw, reg_off,
3997                                 filter->filter_info.dwords[j]);
3998                 reg_off += sizeof(uint32_t);
3999                 E1000_WRITE_REG(hw, reg_off,
4000                                 filter->filter_info.dwords[++j]);
4001                 reg_off += sizeof(uint32_t);
4002                 E1000_WRITE_REG(hw, reg_off,
4003                         (uint32_t)filter->filter_info.mask[i]);
4004                 reg_off += sizeof(uint32_t) * 2;
4005                 ++j;
4006         }
4007 }
4008
4009 static inline struct e1000_flex_filter *
4010 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4011                         struct e1000_flex_filter_info *key)
4012 {
4013         struct e1000_flex_filter *it;
4014
4015         TAILQ_FOREACH(it, filter_list, entries) {
4016                 if (memcmp(key, &it->filter_info,
4017                         sizeof(struct e1000_flex_filter_info)) == 0)
4018                         return it;
4019         }
4020
4021         return NULL;
4022 }
4023
4024 /* remove a flex byte filter
4025  * @param
4026  * dev: Pointer to struct rte_eth_dev.
4027  * filter: the pointer of the filter will be removed.
4028  */
4029 void
4030 igb_remove_flex_filter(struct rte_eth_dev *dev,
4031                         struct e1000_flex_filter *filter)
4032 {
4033         struct e1000_filter_info *filter_info =
4034                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4036         uint32_t wufc, i;
4037         uint32_t reg_off;
4038
4039         wufc = E1000_READ_REG(hw, E1000_WUFC);
4040         if (filter->index < E1000_MAX_FHFT)
4041                 reg_off = E1000_FHFT(filter->index);
4042         else
4043                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4044
4045         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4046                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4047
4048         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4049                 (~(E1000_WUFC_FLX0 << filter->index)));
4050
4051         filter_info->flex_mask &= ~(1 << filter->index);
4052         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4053         rte_free(filter);
4054 }
4055
4056 int
4057 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4058                         struct rte_eth_flex_filter *filter,
4059                         bool add)
4060 {
4061         struct e1000_filter_info *filter_info =
4062                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4063         struct e1000_flex_filter *flex_filter, *it;
4064         uint32_t mask;
4065         uint8_t shift, i;
4066
4067         flex_filter = rte_zmalloc("e1000_flex_filter",
4068                         sizeof(struct e1000_flex_filter), 0);
4069         if (flex_filter == NULL)
4070                 return -ENOMEM;
4071
4072         flex_filter->filter_info.len = filter->len;
4073         flex_filter->filter_info.priority = filter->priority;
4074         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4075         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4076                 mask = 0;
4077                 /* reverse bits in flex filter's mask*/
4078                 for (shift = 0; shift < CHAR_BIT; shift++) {
4079                         if (filter->mask[i] & (0x01 << shift))
4080                                 mask |= (0x80 >> shift);
4081                 }
4082                 flex_filter->filter_info.mask[i] = mask;
4083         }
4084
4085         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4086                                 &flex_filter->filter_info);
4087         if (it == NULL && !add) {
4088                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4089                 rte_free(flex_filter);
4090                 return -ENOENT;
4091         }
4092         if (it != NULL && add) {
4093                 PMD_DRV_LOG(ERR, "filter exists.");
4094                 rte_free(flex_filter);
4095                 return -EEXIST;
4096         }
4097
4098         if (add) {
4099                 flex_filter->queue = filter->queue;
4100                 /*
4101                  * look for an unused flex filter index
4102                  * and insert the filter into the list.
4103                  */
4104                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4105                         if (!(filter_info->flex_mask & (1 << i))) {
4106                                 filter_info->flex_mask |= 1 << i;
4107                                 flex_filter->index = i;
4108                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4109                                         flex_filter,
4110                                         entries);
4111                                 break;
4112                         }
4113                 }
4114                 if (i >= E1000_MAX_FLEX_FILTERS) {
4115                         PMD_DRV_LOG(ERR, "flex filters are full.");
4116                         rte_free(flex_filter);
4117                         return -ENOSYS;
4118                 }
4119
4120                 igb_inject_flex_filter(dev, flex_filter);
4121
4122         } else {
4123                 igb_remove_flex_filter(dev, it);
4124                 rte_free(flex_filter);
4125         }
4126
4127         return 0;
4128 }
4129
4130 static int
4131 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4132                         struct rte_eth_flex_filter *filter)
4133 {
4134         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4135         struct e1000_filter_info *filter_info =
4136                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4137         struct e1000_flex_filter flex_filter, *it;
4138         uint32_t wufc, queueing, wufc_en = 0;
4139
4140         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4141         flex_filter.filter_info.len = filter->len;
4142         flex_filter.filter_info.priority = filter->priority;
4143         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4144         memcpy(flex_filter.filter_info.mask, filter->mask,
4145                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4146
4147         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4148                                 &flex_filter.filter_info);
4149         if (it == NULL) {
4150                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4151                 return -ENOENT;
4152         }
4153
4154         wufc = E1000_READ_REG(hw, E1000_WUFC);
4155         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4156
4157         if ((wufc & wufc_en) == wufc_en) {
4158                 uint32_t reg_off = 0;
4159                 if (it->index < E1000_MAX_FHFT)
4160                         reg_off = E1000_FHFT(it->index);
4161                 else
4162                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4163
4164                 queueing = E1000_READ_REG(hw,
4165                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4166                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4167                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4168                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4169                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4170                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4171                 return 0;
4172         }
4173         return -ENOENT;
4174 }
4175
4176 static int
4177 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4178                         enum rte_filter_op filter_op,
4179                         void *arg)
4180 {
4181         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182         struct rte_eth_flex_filter *filter;
4183         int ret = 0;
4184
4185         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4186
4187         if (filter_op == RTE_ETH_FILTER_NOP)
4188                 return ret;
4189
4190         if (arg == NULL) {
4191                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4192                             filter_op);
4193                 return -EINVAL;
4194         }
4195
4196         filter = (struct rte_eth_flex_filter *)arg;
4197         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4198             || filter->len % sizeof(uint64_t) != 0) {
4199                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4200                 return -EINVAL;
4201         }
4202         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4203                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4204                 return -EINVAL;
4205         }
4206
4207         switch (filter_op) {
4208         case RTE_ETH_FILTER_ADD:
4209                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4210                 break;
4211         case RTE_ETH_FILTER_DELETE:
4212                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4213                 break;
4214         case RTE_ETH_FILTER_GET:
4215                 ret = eth_igb_get_flex_filter(dev, filter);
4216                 break;
4217         default:
4218                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4219                 ret = -EINVAL;
4220                 break;
4221         }
4222
4223         return ret;
4224 }
4225
4226 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4227 static inline int
4228 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4229                         struct e1000_5tuple_filter_info *filter_info)
4230 {
4231         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4232                 return -EINVAL;
4233         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4234                 return -EINVAL;  /* filter index is out of range. */
4235         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4236                 return -EINVAL;  /* flags is invalid. */
4237
4238         switch (filter->dst_ip_mask) {
4239         case UINT32_MAX:
4240                 filter_info->dst_ip_mask = 0;
4241                 filter_info->dst_ip = filter->dst_ip;
4242                 break;
4243         case 0:
4244                 filter_info->dst_ip_mask = 1;
4245                 break;
4246         default:
4247                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4248                 return -EINVAL;
4249         }
4250
4251         switch (filter->src_ip_mask) {
4252         case UINT32_MAX:
4253                 filter_info->src_ip_mask = 0;
4254                 filter_info->src_ip = filter->src_ip;
4255                 break;
4256         case 0:
4257                 filter_info->src_ip_mask = 1;
4258                 break;
4259         default:
4260                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4261                 return -EINVAL;
4262         }
4263
4264         switch (filter->dst_port_mask) {
4265         case UINT16_MAX:
4266                 filter_info->dst_port_mask = 0;
4267                 filter_info->dst_port = filter->dst_port;
4268                 break;
4269         case 0:
4270                 filter_info->dst_port_mask = 1;
4271                 break;
4272         default:
4273                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4274                 return -EINVAL;
4275         }
4276
4277         switch (filter->src_port_mask) {
4278         case UINT16_MAX:
4279                 filter_info->src_port_mask = 0;
4280                 filter_info->src_port = filter->src_port;
4281                 break;
4282         case 0:
4283                 filter_info->src_port_mask = 1;
4284                 break;
4285         default:
4286                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4287                 return -EINVAL;
4288         }
4289
4290         switch (filter->proto_mask) {
4291         case UINT8_MAX:
4292                 filter_info->proto_mask = 0;
4293                 filter_info->proto = filter->proto;
4294                 break;
4295         case 0:
4296                 filter_info->proto_mask = 1;
4297                 break;
4298         default:
4299                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4300                 return -EINVAL;
4301         }
4302
4303         filter_info->priority = (uint8_t)filter->priority;
4304         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4305                 filter_info->tcp_flags = filter->tcp_flags;
4306         else
4307                 filter_info->tcp_flags = 0;
4308
4309         return 0;
4310 }
4311
4312 static inline struct e1000_5tuple_filter *
4313 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4314                         struct e1000_5tuple_filter_info *key)
4315 {
4316         struct e1000_5tuple_filter *it;
4317
4318         TAILQ_FOREACH(it, filter_list, entries) {
4319                 if (memcmp(key, &it->filter_info,
4320                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4321                         return it;
4322                 }
4323         }
4324         return NULL;
4325 }
4326
4327 /* inject a igb 5-tuple filter to HW */
4328 static inline void
4329 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4330                            struct e1000_5tuple_filter *filter)
4331 {
4332         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4333         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4334         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4335         uint8_t i;
4336
4337         i = filter->index;
4338         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4339         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4340                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4341         if (filter->filter_info.dst_ip_mask == 0)
4342                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4343         if (filter->filter_info.src_port_mask == 0)
4344                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4345         if (filter->filter_info.proto_mask == 0)
4346                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4347         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4348                 E1000_FTQF_QUEUE_MASK;
4349         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4350         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4351         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4352         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4353
4354         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4355         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4356
4357         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4358         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4359                 imir |= E1000_IMIR_PORT_BP;
4360         else
4361                 imir &= ~E1000_IMIR_PORT_BP;
4362         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4363
4364         /* tcp flags bits setting. */
4365         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4366                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4367                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4368                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4369                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4370                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4371                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4372                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4373                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4374                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4375                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4376                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4377                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4378         } else {
4379                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4380         }
4381         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4382         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4383 }
4384
4385 /*
4386  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4387  *
4388  * @param
4389  * dev: Pointer to struct rte_eth_dev.
4390  * ntuple_filter: ponter to the filter that will be added.
4391  *
4392  * @return
4393  *    - On success, zero.
4394  *    - On failure, a negative value.
4395  */
4396 static int
4397 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4398                         struct rte_eth_ntuple_filter *ntuple_filter)
4399 {
4400         struct e1000_filter_info *filter_info =
4401                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4402         struct e1000_5tuple_filter *filter;
4403         uint8_t i;
4404         int ret;
4405
4406         filter = rte_zmalloc("e1000_5tuple_filter",
4407                         sizeof(struct e1000_5tuple_filter), 0);
4408         if (filter == NULL)
4409                 return -ENOMEM;
4410
4411         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4412                                             &filter->filter_info);
4413         if (ret < 0) {
4414                 rte_free(filter);
4415                 return ret;
4416         }
4417
4418         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4419                                          &filter->filter_info) != NULL) {
4420                 PMD_DRV_LOG(ERR, "filter exists.");
4421                 rte_free(filter);
4422                 return -EEXIST;
4423         }
4424         filter->queue = ntuple_filter->queue;
4425
4426         /*
4427          * look for an unused 5tuple filter index,
4428          * and insert the filter to list.
4429          */
4430         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4431                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4432                         filter_info->fivetuple_mask |= 1 << i;
4433                         filter->index = i;
4434                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4435                                           filter,
4436                                           entries);
4437                         break;
4438                 }
4439         }
4440         if (i >= E1000_MAX_FTQF_FILTERS) {
4441                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4442                 rte_free(filter);
4443                 return -ENOSYS;
4444         }
4445
4446         igb_inject_5tuple_filter_82576(dev, filter);
4447         return 0;
4448 }
4449
4450 int
4451 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4452                                 struct e1000_5tuple_filter *filter)
4453 {
4454         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4455         struct e1000_filter_info *filter_info =
4456                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4457
4458         filter_info->fivetuple_mask &= ~(1 << filter->index);
4459         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4460         rte_free(filter);
4461
4462         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4463                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4464         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4465         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4466         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4467         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4468         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4469         return 0;
4470 }
4471
4472 /*
4473  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4474  *
4475  * @param
4476  * dev: Pointer to struct rte_eth_dev.
4477  * ntuple_filter: ponter to the filter that will be removed.
4478  *
4479  * @return
4480  *    - On success, zero.
4481  *    - On failure, a negative value.
4482  */
4483 static int
4484 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4485                                 struct rte_eth_ntuple_filter *ntuple_filter)
4486 {
4487         struct e1000_filter_info *filter_info =
4488                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4489         struct e1000_5tuple_filter_info filter_5tuple;
4490         struct e1000_5tuple_filter *filter;
4491         int ret;
4492
4493         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4494         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4495                                             &filter_5tuple);
4496         if (ret < 0)
4497                 return ret;
4498
4499         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4500                                          &filter_5tuple);
4501         if (filter == NULL) {
4502                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4503                 return -ENOENT;
4504         }
4505
4506         igb_delete_5tuple_filter_82576(dev, filter);
4507
4508         return 0;
4509 }
4510
4511 static int
4512 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4513 {
4514         uint32_t rctl;
4515         struct e1000_hw *hw;
4516         struct rte_eth_dev_info dev_info;
4517         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4518         int ret;
4519
4520         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4521
4522 #ifdef RTE_LIBRTE_82571_SUPPORT
4523         /* XXX: not bigger than max_rx_pktlen */
4524         if (hw->mac.type == e1000_82571)
4525                 return -ENOTSUP;
4526 #endif
4527         ret = eth_igb_infos_get(dev, &dev_info);
4528         if (ret != 0)
4529                 return ret;
4530
4531         /* check that mtu is within the allowed range */
4532         if (mtu < RTE_ETHER_MIN_MTU ||
4533                         frame_size > dev_info.max_rx_pktlen)
4534                 return -EINVAL;
4535
4536         /* refuse mtu that requires the support of scattered packets when this
4537          * feature has not been enabled before. */
4538         if (!dev->data->scattered_rx &&
4539             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4540                 return -EINVAL;
4541
4542         rctl = E1000_READ_REG(hw, E1000_RCTL);
4543
4544         /* switch to jumbo mode if needed */
4545         if (frame_size > RTE_ETHER_MAX_LEN) {
4546                 dev->data->dev_conf.rxmode.offloads |=
4547                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4548                 rctl |= E1000_RCTL_LPE;
4549         } else {
4550                 dev->data->dev_conf.rxmode.offloads &=
4551                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4552                 rctl &= ~E1000_RCTL_LPE;
4553         }
4554         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4555
4556         /* update max frame size */
4557         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4558
4559         E1000_WRITE_REG(hw, E1000_RLPML,
4560                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4561
4562         return 0;
4563 }
4564
4565 /*
4566  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4567  *
4568  * @param
4569  * dev: Pointer to struct rte_eth_dev.
4570  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4571  * add: if true, add filter, if false, remove filter
4572  *
4573  * @return
4574  *    - On success, zero.
4575  *    - On failure, a negative value.
4576  */
4577 int
4578 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4579                         struct rte_eth_ntuple_filter *ntuple_filter,
4580                         bool add)
4581 {
4582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4583         int ret;
4584
4585         switch (ntuple_filter->flags) {
4586         case RTE_5TUPLE_FLAGS:
4587         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4588                 if (hw->mac.type != e1000_82576)
4589                         return -ENOTSUP;
4590                 if (add)
4591                         ret = igb_add_5tuple_filter_82576(dev,
4592                                                           ntuple_filter);
4593                 else
4594                         ret = igb_remove_5tuple_filter_82576(dev,
4595                                                              ntuple_filter);
4596                 break;
4597         case RTE_2TUPLE_FLAGS:
4598         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4599                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4600                         hw->mac.type != e1000_i210 &&
4601                         hw->mac.type != e1000_i211)
4602                         return -ENOTSUP;
4603                 if (add)
4604                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4605                 else
4606                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4607                 break;
4608         default:
4609                 ret = -EINVAL;
4610                 break;
4611         }
4612
4613         return ret;
4614 }
4615
4616 /*
4617  * igb_get_ntuple_filter - get a ntuple filter
4618  *
4619  * @param
4620  * dev: Pointer to struct rte_eth_dev.
4621  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4622  *
4623  * @return
4624  *    - On success, zero.
4625  *    - On failure, a negative value.
4626  */
4627 static int
4628 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4629                         struct rte_eth_ntuple_filter *ntuple_filter)
4630 {
4631         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4632         struct e1000_filter_info *filter_info =
4633                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4634         struct e1000_5tuple_filter_info filter_5tuple;
4635         struct e1000_2tuple_filter_info filter_2tuple;
4636         struct e1000_5tuple_filter *p_5tuple_filter;
4637         struct e1000_2tuple_filter *p_2tuple_filter;
4638         int ret;
4639
4640         switch (ntuple_filter->flags) {
4641         case RTE_5TUPLE_FLAGS:
4642         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4643                 if (hw->mac.type != e1000_82576)
4644                         return -ENOTSUP;
4645                 memset(&filter_5tuple,
4646                         0,
4647                         sizeof(struct e1000_5tuple_filter_info));
4648                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4649                                                     &filter_5tuple);
4650                 if (ret < 0)
4651                         return ret;
4652                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4653                                         &filter_info->fivetuple_list,
4654                                         &filter_5tuple);
4655                 if (p_5tuple_filter == NULL) {
4656                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4657                         return -ENOENT;
4658                 }
4659                 ntuple_filter->queue = p_5tuple_filter->queue;
4660                 break;
4661         case RTE_2TUPLE_FLAGS:
4662         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4663                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4664                         return -ENOTSUP;
4665                 memset(&filter_2tuple,
4666                         0,
4667                         sizeof(struct e1000_2tuple_filter_info));
4668                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4669                 if (ret < 0)
4670                         return ret;
4671                 p_2tuple_filter = igb_2tuple_filter_lookup(
4672                                         &filter_info->twotuple_list,
4673                                         &filter_2tuple);
4674                 if (p_2tuple_filter == NULL) {
4675                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4676                         return -ENOENT;
4677                 }
4678                 ntuple_filter->queue = p_2tuple_filter->queue;
4679                 break;
4680         default:
4681                 ret = -EINVAL;
4682                 break;
4683         }
4684
4685         return 0;
4686 }
4687
4688 /*
4689  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4690  * @dev: pointer to rte_eth_dev structure
4691  * @filter_op:operation will be taken.
4692  * @arg: a pointer to specific structure corresponding to the filter_op
4693  */
4694 static int
4695 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4696                                 enum rte_filter_op filter_op,
4697                                 void *arg)
4698 {
4699         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700         int ret;
4701
4702         MAC_TYPE_FILTER_SUP(hw->mac.type);
4703
4704         if (filter_op == RTE_ETH_FILTER_NOP)
4705                 return 0;
4706
4707         if (arg == NULL) {
4708                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4709                             filter_op);
4710                 return -EINVAL;
4711         }
4712
4713         switch (filter_op) {
4714         case RTE_ETH_FILTER_ADD:
4715                 ret = igb_add_del_ntuple_filter(dev,
4716                         (struct rte_eth_ntuple_filter *)arg,
4717                         TRUE);
4718                 break;
4719         case RTE_ETH_FILTER_DELETE:
4720                 ret = igb_add_del_ntuple_filter(dev,
4721                         (struct rte_eth_ntuple_filter *)arg,
4722                         FALSE);
4723                 break;
4724         case RTE_ETH_FILTER_GET:
4725                 ret = igb_get_ntuple_filter(dev,
4726                         (struct rte_eth_ntuple_filter *)arg);
4727                 break;
4728         default:
4729                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4730                 ret = -EINVAL;
4731                 break;
4732         }
4733         return ret;
4734 }
4735
4736 static inline int
4737 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4738                         uint16_t ethertype)
4739 {
4740         int i;
4741
4742         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4743                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4744                     (filter_info->ethertype_mask & (1 << i)))
4745                         return i;
4746         }
4747         return -1;
4748 }
4749
4750 static inline int
4751 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4752                         uint16_t ethertype, uint32_t etqf)
4753 {
4754         int i;
4755
4756         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4757                 if (!(filter_info->ethertype_mask & (1 << i))) {
4758                         filter_info->ethertype_mask |= 1 << i;
4759                         filter_info->ethertype_filters[i].ethertype = ethertype;
4760                         filter_info->ethertype_filters[i].etqf = etqf;
4761                         return i;
4762                 }
4763         }
4764         return -1;
4765 }
4766
4767 int
4768 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4769                         uint8_t idx)
4770 {
4771         if (idx >= E1000_MAX_ETQF_FILTERS)
4772                 return -1;
4773         filter_info->ethertype_mask &= ~(1 << idx);
4774         filter_info->ethertype_filters[idx].ethertype = 0;
4775         filter_info->ethertype_filters[idx].etqf = 0;
4776         return idx;
4777 }
4778
4779
4780 int
4781 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4782                         struct rte_eth_ethertype_filter *filter,
4783                         bool add)
4784 {
4785         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4786         struct e1000_filter_info *filter_info =
4787                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4788         uint32_t etqf = 0;
4789         int ret;
4790
4791         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4792                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4793                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4794                         " ethertype filter.", filter->ether_type);
4795                 return -EINVAL;
4796         }
4797
4798         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4799                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4800                 return -EINVAL;
4801         }
4802         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4803                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4804                 return -EINVAL;
4805         }
4806
4807         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4808         if (ret >= 0 && add) {
4809                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4810                             filter->ether_type);
4811                 return -EEXIST;
4812         }
4813         if (ret < 0 && !add) {
4814                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4815                             filter->ether_type);
4816                 return -ENOENT;
4817         }
4818
4819         if (add) {
4820                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4821                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4822                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4823                 ret = igb_ethertype_filter_insert(filter_info,
4824                                 filter->ether_type, etqf);
4825                 if (ret < 0) {
4826                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4827                         return -ENOSYS;
4828                 }
4829         } else {
4830                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4831                 if (ret < 0)
4832                         return -ENOSYS;
4833         }
4834         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4835         E1000_WRITE_FLUSH(hw);
4836
4837         return 0;
4838 }
4839
4840 static int
4841 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4842                      enum rte_filter_type filter_type,
4843                      enum rte_filter_op filter_op,
4844                      void *arg)
4845 {
4846         int ret = 0;
4847
4848         switch (filter_type) {
4849         case RTE_ETH_FILTER_NTUPLE:
4850                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4851                 break;
4852         case RTE_ETH_FILTER_SYN:
4853                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4854                 break;
4855         case RTE_ETH_FILTER_FLEXIBLE:
4856                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4857                 break;
4858         case RTE_ETH_FILTER_GENERIC:
4859                 if (filter_op != RTE_ETH_FILTER_GET)
4860                         return -EINVAL;
4861                 *(const void **)arg = &igb_flow_ops;
4862                 break;
4863         default:
4864                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4865                                                         filter_type);
4866                 break;
4867         }
4868
4869         return ret;
4870 }
4871
4872 static int
4873 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4874                          struct rte_ether_addr *mc_addr_set,
4875                          uint32_t nb_mc_addr)
4876 {
4877         struct e1000_hw *hw;
4878
4879         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4880         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4881         return 0;
4882 }
4883
4884 static uint64_t
4885 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4886 {
4887         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4888         uint64_t systime_cycles;
4889
4890         switch (hw->mac.type) {
4891         case e1000_i210:
4892         case e1000_i211:
4893                 /*
4894                  * Need to read System Time Residue Register to be able
4895                  * to read the other two registers.
4896                  */
4897                 E1000_READ_REG(hw, E1000_SYSTIMR);
4898                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4899                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4900                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4901                                 * NSEC_PER_SEC;
4902                 break;
4903         case e1000_82580:
4904         case e1000_i350:
4905         case e1000_i354:
4906                 /*
4907                  * Need to read System Time Residue Register to be able
4908                  * to read the other two registers.
4909                  */
4910                 E1000_READ_REG(hw, E1000_SYSTIMR);
4911                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4912                 /* Only the 8 LSB are valid. */
4913                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4914                                 & 0xff) << 32;
4915                 break;
4916         default:
4917                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4918                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4919                                 << 32;
4920                 break;
4921         }
4922
4923         return systime_cycles;
4924 }
4925
4926 static uint64_t
4927 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4928 {
4929         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4930         uint64_t rx_tstamp_cycles;
4931
4932         switch (hw->mac.type) {
4933         case e1000_i210:
4934         case e1000_i211:
4935                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4936                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4937                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4938                                 * NSEC_PER_SEC;
4939                 break;
4940         case e1000_82580:
4941         case e1000_i350:
4942         case e1000_i354:
4943                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4944                 /* Only the 8 LSB are valid. */
4945                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4946                                 & 0xff) << 32;
4947                 break;
4948         default:
4949                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4950                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4951                                 << 32;
4952                 break;
4953         }
4954
4955         return rx_tstamp_cycles;
4956 }
4957
4958 static uint64_t
4959 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4960 {
4961         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4962         uint64_t tx_tstamp_cycles;
4963
4964         switch (hw->mac.type) {
4965         case e1000_i210:
4966         case e1000_i211:
4967                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4968                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4969                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4970                                 * NSEC_PER_SEC;
4971                 break;
4972         case e1000_82580:
4973         case e1000_i350:
4974         case e1000_i354:
4975                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4976                 /* Only the 8 LSB are valid. */
4977                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4978                                 & 0xff) << 32;
4979                 break;
4980         default:
4981                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4982                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4983                                 << 32;
4984                 break;
4985         }
4986
4987         return tx_tstamp_cycles;
4988 }
4989
4990 static void
4991 igb_start_timecounters(struct rte_eth_dev *dev)
4992 {
4993         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4994         struct e1000_adapter *adapter = dev->data->dev_private;
4995         uint32_t incval = 1;
4996         uint32_t shift = 0;
4997         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4998
4999         switch (hw->mac.type) {
5000         case e1000_82580:
5001         case e1000_i350:
5002         case e1000_i354:
5003                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5004                 mask = (1ULL << 40) - 1;
5005                 /* fall-through */
5006         case e1000_i210:
5007         case e1000_i211:
5008                 /*
5009                  * Start incrementing the register
5010                  * used to timestamp PTP packets.
5011                  */
5012                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5013                 break;
5014         case e1000_82576:
5015                 incval = E1000_INCVALUE_82576;
5016                 shift = IGB_82576_TSYNC_SHIFT;
5017                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5018                                 E1000_INCPERIOD_82576 | incval);
5019                 break;
5020         default:
5021                 /* Not supported */
5022                 return;
5023         }
5024
5025         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5026         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5027         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5028
5029         adapter->systime_tc.cc_mask = mask;
5030         adapter->systime_tc.cc_shift = shift;
5031         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5032
5033         adapter->rx_tstamp_tc.cc_mask = mask;
5034         adapter->rx_tstamp_tc.cc_shift = shift;
5035         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5036
5037         adapter->tx_tstamp_tc.cc_mask = mask;
5038         adapter->tx_tstamp_tc.cc_shift = shift;
5039         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5040 }
5041
5042 static int
5043 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5044 {
5045         struct e1000_adapter *adapter = dev->data->dev_private;
5046
5047         adapter->systime_tc.nsec += delta;
5048         adapter->rx_tstamp_tc.nsec += delta;
5049         adapter->tx_tstamp_tc.nsec += delta;
5050
5051         return 0;
5052 }
5053
5054 static int
5055 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5056 {
5057         uint64_t ns;
5058         struct e1000_adapter *adapter = dev->data->dev_private;
5059
5060         ns = rte_timespec_to_ns(ts);
5061
5062         /* Set the timecounters to a new value. */
5063         adapter->systime_tc.nsec = ns;
5064         adapter->rx_tstamp_tc.nsec = ns;
5065         adapter->tx_tstamp_tc.nsec = ns;
5066
5067         return 0;
5068 }
5069
5070 static int
5071 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5072 {
5073         uint64_t ns, systime_cycles;
5074         struct e1000_adapter *adapter = dev->data->dev_private;
5075
5076         systime_cycles = igb_read_systime_cyclecounter(dev);
5077         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5078         *ts = rte_ns_to_timespec(ns);
5079
5080         return 0;
5081 }
5082
5083 static int
5084 igb_timesync_enable(struct rte_eth_dev *dev)
5085 {
5086         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5087         uint32_t tsync_ctl;
5088         uint32_t tsauxc;
5089
5090         /* Stop the timesync system time. */
5091         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5092         /* Reset the timesync system time value. */
5093         switch (hw->mac.type) {
5094         case e1000_82580:
5095         case e1000_i350:
5096         case e1000_i354:
5097         case e1000_i210:
5098         case e1000_i211:
5099                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5100                 /* fall-through */
5101         case e1000_82576:
5102                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5103                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5104                 break;
5105         default:
5106                 /* Not supported. */
5107                 return -ENOTSUP;
5108         }
5109
5110         /* Enable system time for it isn't on by default. */
5111         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5112         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5113         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5114
5115         igb_start_timecounters(dev);
5116
5117         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5118         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5119                         (RTE_ETHER_TYPE_1588 |
5120                          E1000_ETQF_FILTER_ENABLE |
5121                          E1000_ETQF_1588));
5122
5123         /* Enable timestamping of received PTP packets. */
5124         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5125         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5126         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5127
5128         /* Enable Timestamping of transmitted PTP packets. */
5129         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5130         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5131         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5132
5133         return 0;
5134 }
5135
5136 static int
5137 igb_timesync_disable(struct rte_eth_dev *dev)
5138 {
5139         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140         uint32_t tsync_ctl;
5141
5142         /* Disable timestamping of transmitted PTP packets. */
5143         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5144         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5145         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5146
5147         /* Disable timestamping of received PTP packets. */
5148         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5149         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5150         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5151
5152         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5153         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5154
5155         /* Stop incrementating the System Time registers. */
5156         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5157
5158         return 0;
5159 }
5160
5161 static int
5162 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5163                                struct timespec *timestamp,
5164                                uint32_t flags __rte_unused)
5165 {
5166         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167         struct e1000_adapter *adapter = dev->data->dev_private;
5168         uint32_t tsync_rxctl;
5169         uint64_t rx_tstamp_cycles;
5170         uint64_t ns;
5171
5172         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5173         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5174                 return -EINVAL;
5175
5176         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5177         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5178         *timestamp = rte_ns_to_timespec(ns);
5179
5180         return  0;
5181 }
5182
5183 static int
5184 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5185                                struct timespec *timestamp)
5186 {
5187         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188         struct e1000_adapter *adapter = dev->data->dev_private;
5189         uint32_t tsync_txctl;
5190         uint64_t tx_tstamp_cycles;
5191         uint64_t ns;
5192
5193         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5194         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5195                 return -EINVAL;
5196
5197         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5198         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5199         *timestamp = rte_ns_to_timespec(ns);
5200
5201         return  0;
5202 }
5203
5204 static int
5205 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5206 {
5207         int count = 0;
5208         int g_ind = 0;
5209         const struct reg_info *reg_group;
5210
5211         while ((reg_group = igb_regs[g_ind++]))
5212                 count += igb_reg_group_count(reg_group);
5213
5214         return count;
5215 }
5216
5217 static int
5218 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5219 {
5220         int count = 0;
5221         int g_ind = 0;
5222         const struct reg_info *reg_group;
5223
5224         while ((reg_group = igbvf_regs[g_ind++]))
5225                 count += igb_reg_group_count(reg_group);
5226
5227         return count;
5228 }
5229
5230 static int
5231 eth_igb_get_regs(struct rte_eth_dev *dev,
5232         struct rte_dev_reg_info *regs)
5233 {
5234         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5235         uint32_t *data = regs->data;
5236         int g_ind = 0;
5237         int count = 0;
5238         const struct reg_info *reg_group;
5239
5240         if (data == NULL) {
5241                 regs->length = eth_igb_get_reg_length(dev);
5242                 regs->width = sizeof(uint32_t);
5243                 return 0;
5244         }
5245
5246         /* Support only full register dump */
5247         if ((regs->length == 0) ||
5248             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5249                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5250                         hw->device_id;
5251                 while ((reg_group = igb_regs[g_ind++]))
5252                         count += igb_read_regs_group(dev, &data[count],
5253                                                         reg_group);
5254                 return 0;
5255         }
5256
5257         return -ENOTSUP;
5258 }
5259
5260 static int
5261 igbvf_get_regs(struct rte_eth_dev *dev,
5262         struct rte_dev_reg_info *regs)
5263 {
5264         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5265         uint32_t *data = regs->data;
5266         int g_ind = 0;
5267         int count = 0;
5268         const struct reg_info *reg_group;
5269
5270         if (data == NULL) {
5271                 regs->length = igbvf_get_reg_length(dev);
5272                 regs->width = sizeof(uint32_t);
5273                 return 0;
5274         }
5275
5276         /* Support only full register dump */
5277         if ((regs->length == 0) ||
5278             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5279                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5280                         hw->device_id;
5281                 while ((reg_group = igbvf_regs[g_ind++]))
5282                         count += igb_read_regs_group(dev, &data[count],
5283                                                         reg_group);
5284                 return 0;
5285         }
5286
5287         return -ENOTSUP;
5288 }
5289
5290 static int
5291 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5292 {
5293         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5294
5295         /* Return unit is byte count */
5296         return hw->nvm.word_size * 2;
5297 }
5298
5299 static int
5300 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5301         struct rte_dev_eeprom_info *in_eeprom)
5302 {
5303         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5304         struct e1000_nvm_info *nvm = &hw->nvm;
5305         uint16_t *data = in_eeprom->data;
5306         int first, length;
5307
5308         first = in_eeprom->offset >> 1;
5309         length = in_eeprom->length >> 1;
5310         if ((first >= hw->nvm.word_size) ||
5311             ((first + length) >= hw->nvm.word_size))
5312                 return -EINVAL;
5313
5314         in_eeprom->magic = hw->vendor_id |
5315                 ((uint32_t)hw->device_id << 16);
5316
5317         if ((nvm->ops.read) == NULL)
5318                 return -ENOTSUP;
5319
5320         return nvm->ops.read(hw, first, length, data);
5321 }
5322
5323 static int
5324 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5325         struct rte_dev_eeprom_info *in_eeprom)
5326 {
5327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5328         struct e1000_nvm_info *nvm = &hw->nvm;
5329         uint16_t *data = in_eeprom->data;
5330         int first, length;
5331
5332         first = in_eeprom->offset >> 1;
5333         length = in_eeprom->length >> 1;
5334         if ((first >= hw->nvm.word_size) ||
5335             ((first + length) >= hw->nvm.word_size))
5336                 return -EINVAL;
5337
5338         in_eeprom->magic = (uint32_t)hw->vendor_id |
5339                 ((uint32_t)hw->device_id << 16);
5340
5341         if ((nvm->ops.write) == NULL)
5342                 return -ENOTSUP;
5343         return nvm->ops.write(hw,  first, length, data);
5344 }
5345
5346 static int
5347 eth_igb_get_module_info(struct rte_eth_dev *dev,
5348                         struct rte_eth_dev_module_info *modinfo)
5349 {
5350         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5351
5352         uint32_t status = 0;
5353         uint16_t sff8472_rev, addr_mode;
5354         bool page_swap = false;
5355
5356         if (hw->phy.media_type == e1000_media_type_copper ||
5357             hw->phy.media_type == e1000_media_type_unknown)
5358                 return -EOPNOTSUPP;
5359
5360         /* Check whether we support SFF-8472 or not */
5361         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5362         if (status)
5363                 return -EIO;
5364
5365         /* addressing mode is not supported */
5366         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5367         if (status)
5368                 return -EIO;
5369
5370         /* addressing mode is not supported */
5371         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5372                 PMD_DRV_LOG(ERR,
5373                             "Address change required to access page 0xA2, "
5374                             "but not supported. Please report the module "
5375                             "type to the driver maintainers.\n");
5376                 page_swap = true;
5377         }
5378
5379         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5380                 /* We have an SFP, but it does not support SFF-8472 */
5381                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5382                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5383         } else {
5384                 /* We have an SFP which supports a revision of SFF-8472 */
5385                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5386                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5387         }
5388
5389         return 0;
5390 }
5391
5392 static int
5393 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5394                           struct rte_dev_eeprom_info *info)
5395 {
5396         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5397
5398         uint32_t status = 0;
5399         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5400         u16 first_word, last_word;
5401         int i = 0;
5402
5403         if (info->length == 0)
5404                 return -EINVAL;
5405
5406         first_word = info->offset >> 1;
5407         last_word = (info->offset + info->length - 1) >> 1;
5408
5409         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5410         for (i = 0; i < last_word - first_word + 1; i++) {
5411                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5412                                                 &dataword[i]);
5413                 if (status) {
5414                         /* Error occurred while reading module */
5415                         return -EIO;
5416                 }
5417
5418                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5419         }
5420
5421         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5422
5423         return 0;
5424 }
5425
5426 static int
5427 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5428 {
5429         struct e1000_hw *hw =
5430                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5431         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5432         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5433         uint32_t vec = E1000_MISC_VEC_ID;
5434
5435         if (rte_intr_allow_others(intr_handle))
5436                 vec = E1000_RX_VEC_START;
5437
5438         uint32_t mask = 1 << (queue_id + vec);
5439
5440         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5441         E1000_WRITE_FLUSH(hw);
5442
5443         return 0;
5444 }
5445
5446 static int
5447 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5448 {
5449         struct e1000_hw *hw =
5450                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5451         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5452         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5453         uint32_t vec = E1000_MISC_VEC_ID;
5454
5455         if (rte_intr_allow_others(intr_handle))
5456                 vec = E1000_RX_VEC_START;
5457
5458         uint32_t mask = 1 << (queue_id + vec);
5459         uint32_t regval;
5460
5461         regval = E1000_READ_REG(hw, E1000_EIMS);
5462         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5463         E1000_WRITE_FLUSH(hw);
5464
5465         rte_intr_ack(intr_handle);
5466
5467         return 0;
5468 }
5469
5470 static void
5471 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5472                    uint8_t index, uint8_t offset)
5473 {
5474         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5475
5476         /* clear bits */
5477         val &= ~((uint32_t)0xFF << offset);
5478
5479         /* write vector and valid bit */
5480         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5481
5482         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5483 }
5484
5485 static void
5486 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5487                            uint8_t queue, uint8_t msix_vector)
5488 {
5489         uint32_t tmp = 0;
5490
5491         if (hw->mac.type == e1000_82575) {
5492                 if (direction == 0)
5493                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5494                 else if (direction == 1)
5495                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5496                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5497         } else if (hw->mac.type == e1000_82576) {
5498                 if ((direction == 0) || (direction == 1))
5499                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5500                                            ((queue & 0x8) << 1) +
5501                                            8 * direction);
5502         } else if ((hw->mac.type == e1000_82580) ||
5503                         (hw->mac.type == e1000_i350) ||
5504                         (hw->mac.type == e1000_i354) ||
5505                         (hw->mac.type == e1000_i210) ||
5506                         (hw->mac.type == e1000_i211)) {
5507                 if ((direction == 0) || (direction == 1))
5508                         eth_igb_write_ivar(hw, msix_vector,
5509                                            queue >> 1,
5510                                            ((queue & 0x1) << 4) +
5511                                            8 * direction);
5512         }
5513 }
5514
5515 /* Sets up the hardware to generate MSI-X interrupts properly
5516  * @hw
5517  *  board private structure
5518  */
5519 static void
5520 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5521 {
5522         int queue_id;
5523         uint32_t tmpval, regval, intr_mask;
5524         struct e1000_hw *hw =
5525                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5526         uint32_t vec = E1000_MISC_VEC_ID;
5527         uint32_t base = E1000_MISC_VEC_ID;
5528         uint32_t misc_shift = 0;
5529         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5530         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5531
5532         /* won't configure msix register if no mapping is done
5533          * between intr vector and event fd
5534          */
5535         if (!rte_intr_dp_is_en(intr_handle))
5536                 return;
5537
5538         if (rte_intr_allow_others(intr_handle)) {
5539                 vec = base = E1000_RX_VEC_START;
5540                 misc_shift = 1;
5541         }
5542
5543         /* set interrupt vector for other causes */
5544         if (hw->mac.type == e1000_82575) {
5545                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5546                 /* enable MSI-X PBA support */
5547                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5548
5549                 /* Auto-Mask interrupts upon ICR read */
5550                 tmpval |= E1000_CTRL_EXT_EIAME;
5551                 tmpval |= E1000_CTRL_EXT_IRCA;
5552
5553                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5554
5555                 /* enable msix_other interrupt */
5556                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5557                 regval = E1000_READ_REG(hw, E1000_EIAC);
5558                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5559                 regval = E1000_READ_REG(hw, E1000_EIAM);
5560                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5561         } else if ((hw->mac.type == e1000_82576) ||
5562                         (hw->mac.type == e1000_82580) ||
5563                         (hw->mac.type == e1000_i350) ||
5564                         (hw->mac.type == e1000_i354) ||
5565                         (hw->mac.type == e1000_i210) ||
5566                         (hw->mac.type == e1000_i211)) {
5567                 /* turn on MSI-X capability first */
5568                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5569                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5570                                         E1000_GPIE_NSICR);
5571                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5572                         misc_shift;
5573
5574                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5575                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5576
5577                 regval = E1000_READ_REG(hw, E1000_EIAC);
5578                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5579
5580                 /* enable msix_other interrupt */
5581                 regval = E1000_READ_REG(hw, E1000_EIMS);
5582                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5583                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5584                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5585         }
5586
5587         /* use EIAM to auto-mask when MSI-X interrupt
5588          * is asserted, this saves a register write for every interrupt
5589          */
5590         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5591                 misc_shift;
5592
5593         if (dev->data->dev_conf.intr_conf.lsc != 0)
5594                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5595
5596         regval = E1000_READ_REG(hw, E1000_EIAM);
5597         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5598
5599         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5600                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5601                 intr_handle->intr_vec[queue_id] = vec;
5602                 if (vec < base + intr_handle->nb_efd - 1)
5603                         vec++;
5604         }
5605
5606         E1000_WRITE_FLUSH(hw);
5607 }
5608
5609 /* restore n-tuple filter */
5610 static inline void
5611 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5612 {
5613         struct e1000_filter_info *filter_info =
5614                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5615         struct e1000_5tuple_filter *p_5tuple;
5616         struct e1000_2tuple_filter *p_2tuple;
5617
5618         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5619                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5620         }
5621
5622         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5623                 igb_inject_2uple_filter(dev, p_2tuple);
5624         }
5625 }
5626
5627 /* restore SYN filter */
5628 static inline void
5629 igb_syn_filter_restore(struct rte_eth_dev *dev)
5630 {
5631         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5632         struct e1000_filter_info *filter_info =
5633                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5634         uint32_t synqf;
5635
5636         synqf = filter_info->syn_info;
5637
5638         if (synqf & E1000_SYN_FILTER_ENABLE) {
5639                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5640                 E1000_WRITE_FLUSH(hw);
5641         }
5642 }
5643
5644 /* restore ethernet type filter */
5645 static inline void
5646 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5647 {
5648         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         struct e1000_filter_info *filter_info =
5650                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5651         int i;
5652
5653         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5654                 if (filter_info->ethertype_mask & (1 << i)) {
5655                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5656                                 filter_info->ethertype_filters[i].etqf);
5657                         E1000_WRITE_FLUSH(hw);
5658                 }
5659         }
5660 }
5661
5662 /* restore flex byte filter */
5663 static inline void
5664 igb_flex_filter_restore(struct rte_eth_dev *dev)
5665 {
5666         struct e1000_filter_info *filter_info =
5667                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5668         struct e1000_flex_filter *flex_filter;
5669
5670         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5671                 igb_inject_flex_filter(dev, flex_filter);
5672         }
5673 }
5674
5675 /* restore rss filter */
5676 static inline void
5677 igb_rss_filter_restore(struct rte_eth_dev *dev)
5678 {
5679         struct e1000_filter_info *filter_info =
5680                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5681
5682         if (filter_info->rss_info.conf.queue_num)
5683                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5684 }
5685
5686 /* restore all types filter */
5687 static int
5688 igb_filter_restore(struct rte_eth_dev *dev)
5689 {
5690         igb_ntuple_filter_restore(dev);
5691         igb_ethertype_filter_restore(dev);
5692         igb_syn_filter_restore(dev);
5693         igb_flex_filter_restore(dev);
5694         igb_rss_filter_restore(dev);
5695
5696         return 0;
5697 }
5698
5699 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5700 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5701 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5702 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5703 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5704 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5705
5706 /* see e1000_logs.c */
5707 RTE_INIT(e1000_init_log)
5708 {
5709         e1000_igb_init_log();
5710 }