1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
15 #include <rte_debug.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memory.h>
23 #include <rte_malloc.h>
26 #include "e1000_logs.h"
27 #include "base/e1000_api.h"
28 #include "e1000_ethdev.h"
32 * Default values for port configuration
34 #define IGB_DEFAULT_RX_FREE_THRESH 32
36 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
37 #define IGB_DEFAULT_RX_HTHRESH 8
38 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
40 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
41 #define IGB_DEFAULT_TX_HTHRESH 1
42 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
44 #define IGB_HKEY_MAX_INDEX 10
46 /* Bit shift and mask */
47 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
48 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
49 #define IGB_8_BIT_WIDTH CHAR_BIT
50 #define IGB_8_BIT_MASK UINT8_MAX
52 /* Additional timesync values. */
53 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
54 #define E1000_ETQF_FILTER_1588 3
55 #define IGB_82576_TSYNC_SHIFT 16
56 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
57 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
58 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
60 #define E1000_VTIVAR_MISC 0x01740
61 #define E1000_VTIVAR_MISC_MASK 0xFF
62 #define E1000_VTIVAR_VALID 0x80
63 #define E1000_VTIVAR_MISC_MAILBOX 0
64 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
66 /* External VLAN Enable bit mask */
67 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
69 /* External VLAN Ether Type bit mask and shift */
70 #define E1000_VET_VET_EXT 0xFFFF0000
71 #define E1000_VET_VET_EXT_SHIFT 16
73 static int eth_igb_configure(struct rte_eth_dev *dev);
74 static int eth_igb_start(struct rte_eth_dev *dev);
75 static void eth_igb_stop(struct rte_eth_dev *dev);
76 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
77 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
78 static void eth_igb_close(struct rte_eth_dev *dev);
79 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
80 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
81 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
82 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
83 static int eth_igb_link_update(struct rte_eth_dev *dev,
84 int wait_to_complete);
85 static int eth_igb_stats_get(struct rte_eth_dev *dev,
86 struct rte_eth_stats *rte_stats);
87 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
88 struct rte_eth_xstat *xstats, unsigned n);
89 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
91 uint64_t *values, unsigned int n);
92 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
93 struct rte_eth_xstat_name *xstats_names,
95 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
98 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
99 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
100 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
101 char *fw_version, size_t fw_size);
102 static void eth_igb_infos_get(struct rte_eth_dev *dev,
103 struct rte_eth_dev_info *dev_info);
104 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
105 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
108 struct rte_eth_fc_conf *fc_conf);
109 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
110 struct rte_eth_fc_conf *fc_conf);
111 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
112 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
113 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
114 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
115 struct rte_intr_handle *handle);
116 static void eth_igb_interrupt_handler(void *param);
117 static int igb_hardware_init(struct e1000_hw *hw);
118 static void igb_hw_control_acquire(struct e1000_hw *hw);
119 static void igb_hw_control_release(struct e1000_hw *hw);
120 static void igb_init_manageability(struct e1000_hw *hw);
121 static void igb_release_manageability(struct e1000_hw *hw);
123 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
126 uint16_t vlan_id, int on);
127 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
128 enum rte_vlan_type vlan_type,
130 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
132 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
133 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
134 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
135 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
139 static int eth_igb_led_on(struct rte_eth_dev *dev);
140 static int eth_igb_led_off(struct rte_eth_dev *dev);
142 static void igb_intr_disable(struct e1000_hw *hw);
143 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
144 static int eth_igb_rar_set(struct rte_eth_dev *dev,
145 struct ether_addr *mac_addr,
146 uint32_t index, uint32_t pool);
147 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
148 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
149 struct ether_addr *addr);
151 static void igbvf_intr_disable(struct e1000_hw *hw);
152 static int igbvf_dev_configure(struct rte_eth_dev *dev);
153 static int igbvf_dev_start(struct rte_eth_dev *dev);
154 static void igbvf_dev_stop(struct rte_eth_dev *dev);
155 static void igbvf_dev_close(struct rte_eth_dev *dev);
156 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
157 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
158 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
159 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
160 static int eth_igbvf_link_update(struct e1000_hw *hw);
161 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
162 struct rte_eth_stats *rte_stats);
163 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
164 struct rte_eth_xstat *xstats, unsigned n);
165 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
166 struct rte_eth_xstat_name *xstats_names,
168 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
169 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
170 uint16_t vlan_id, int on);
171 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
172 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
173 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
174 struct ether_addr *addr);
175 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
176 static int igbvf_get_regs(struct rte_eth_dev *dev,
177 struct rte_dev_reg_info *regs);
179 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
180 struct rte_eth_rss_reta_entry64 *reta_conf,
182 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
186 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
187 struct rte_eth_syn_filter *filter);
188 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
189 enum rte_filter_op filter_op,
191 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
194 struct rte_eth_ntuple_filter *ntuple_filter);
195 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
196 struct rte_eth_flex_filter *filter);
197 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
198 enum rte_filter_op filter_op,
200 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
201 struct rte_eth_ntuple_filter *ntuple_filter);
202 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
203 struct rte_eth_ntuple_filter *ntuple_filter);
204 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
205 struct rte_eth_ntuple_filter *filter);
206 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
207 enum rte_filter_op filter_op,
209 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
210 enum rte_filter_op filter_op,
212 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
213 struct rte_eth_ethertype_filter *filter);
214 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
215 enum rte_filter_type filter_type,
216 enum rte_filter_op filter_op,
218 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
219 static int eth_igb_get_regs(struct rte_eth_dev *dev,
220 struct rte_dev_reg_info *regs);
221 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
222 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
223 struct rte_dev_eeprom_info *eeprom);
224 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
225 struct rte_dev_eeprom_info *eeprom);
226 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
227 struct ether_addr *mc_addr_set,
228 uint32_t nb_mc_addr);
229 static int igb_timesync_enable(struct rte_eth_dev *dev);
230 static int igb_timesync_disable(struct rte_eth_dev *dev);
231 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
232 struct timespec *timestamp,
234 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
235 struct timespec *timestamp);
236 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
237 static int igb_timesync_read_time(struct rte_eth_dev *dev,
238 struct timespec *timestamp);
239 static int igb_timesync_write_time(struct rte_eth_dev *dev,
240 const struct timespec *timestamp);
241 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
243 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
245 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
246 uint8_t queue, uint8_t msix_vector);
247 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
248 uint8_t index, uint8_t offset);
249 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
250 static void eth_igbvf_interrupt_handler(void *param);
251 static void igbvf_mbx_process(struct rte_eth_dev *dev);
252 static int igb_filter_restore(struct rte_eth_dev *dev);
255 * Define VF Stats MACRO for Non "cleared on read" register
257 #define UPDATE_VF_STAT(reg, last, cur) \
259 u32 latest = E1000_READ_REG(hw, reg); \
260 cur += (latest - last) & UINT_MAX; \
264 #define IGB_FC_PAUSE_TIME 0x0680
265 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
266 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
268 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
270 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
273 * The set of PCI devices this driver supports
275 static const struct rte_pci_id pci_id_igb_map[] = {
276 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
280 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
302 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
317 { .vendor_id = 0, /* sentinel */ },
321 * The set of PCI devices this driver supports (for 82576&I350 VF)
323 static const struct rte_pci_id pci_id_igbvf_map[] = {
324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
325 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
328 { .vendor_id = 0, /* sentinel */ },
331 static const struct rte_eth_desc_lim rx_desc_lim = {
332 .nb_max = E1000_MAX_RING_DESC,
333 .nb_min = E1000_MIN_RING_DESC,
334 .nb_align = IGB_RXD_ALIGN,
337 static const struct rte_eth_desc_lim tx_desc_lim = {
338 .nb_max = E1000_MAX_RING_DESC,
339 .nb_min = E1000_MIN_RING_DESC,
340 .nb_align = IGB_RXD_ALIGN,
341 .nb_seg_max = IGB_TX_MAX_SEG,
342 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
345 static const struct eth_dev_ops eth_igb_ops = {
346 .dev_configure = eth_igb_configure,
347 .dev_start = eth_igb_start,
348 .dev_stop = eth_igb_stop,
349 .dev_set_link_up = eth_igb_dev_set_link_up,
350 .dev_set_link_down = eth_igb_dev_set_link_down,
351 .dev_close = eth_igb_close,
352 .promiscuous_enable = eth_igb_promiscuous_enable,
353 .promiscuous_disable = eth_igb_promiscuous_disable,
354 .allmulticast_enable = eth_igb_allmulticast_enable,
355 .allmulticast_disable = eth_igb_allmulticast_disable,
356 .link_update = eth_igb_link_update,
357 .stats_get = eth_igb_stats_get,
358 .xstats_get = eth_igb_xstats_get,
359 .xstats_get_by_id = eth_igb_xstats_get_by_id,
360 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
361 .xstats_get_names = eth_igb_xstats_get_names,
362 .stats_reset = eth_igb_stats_reset,
363 .xstats_reset = eth_igb_xstats_reset,
364 .fw_version_get = eth_igb_fw_version_get,
365 .dev_infos_get = eth_igb_infos_get,
366 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
367 .mtu_set = eth_igb_mtu_set,
368 .vlan_filter_set = eth_igb_vlan_filter_set,
369 .vlan_tpid_set = eth_igb_vlan_tpid_set,
370 .vlan_offload_set = eth_igb_vlan_offload_set,
371 .rx_queue_setup = eth_igb_rx_queue_setup,
372 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
373 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
374 .rx_queue_release = eth_igb_rx_queue_release,
375 .rx_queue_count = eth_igb_rx_queue_count,
376 .rx_descriptor_done = eth_igb_rx_descriptor_done,
377 .rx_descriptor_status = eth_igb_rx_descriptor_status,
378 .tx_descriptor_status = eth_igb_tx_descriptor_status,
379 .tx_queue_setup = eth_igb_tx_queue_setup,
380 .tx_queue_release = eth_igb_tx_queue_release,
381 .tx_done_cleanup = eth_igb_tx_done_cleanup,
382 .dev_led_on = eth_igb_led_on,
383 .dev_led_off = eth_igb_led_off,
384 .flow_ctrl_get = eth_igb_flow_ctrl_get,
385 .flow_ctrl_set = eth_igb_flow_ctrl_set,
386 .mac_addr_add = eth_igb_rar_set,
387 .mac_addr_remove = eth_igb_rar_clear,
388 .mac_addr_set = eth_igb_default_mac_addr_set,
389 .reta_update = eth_igb_rss_reta_update,
390 .reta_query = eth_igb_rss_reta_query,
391 .rss_hash_update = eth_igb_rss_hash_update,
392 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
393 .filter_ctrl = eth_igb_filter_ctrl,
394 .set_mc_addr_list = eth_igb_set_mc_addr_list,
395 .rxq_info_get = igb_rxq_info_get,
396 .txq_info_get = igb_txq_info_get,
397 .timesync_enable = igb_timesync_enable,
398 .timesync_disable = igb_timesync_disable,
399 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
400 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
401 .get_reg = eth_igb_get_regs,
402 .get_eeprom_length = eth_igb_get_eeprom_length,
403 .get_eeprom = eth_igb_get_eeprom,
404 .set_eeprom = eth_igb_set_eeprom,
405 .timesync_adjust_time = igb_timesync_adjust_time,
406 .timesync_read_time = igb_timesync_read_time,
407 .timesync_write_time = igb_timesync_write_time,
411 * dev_ops for virtual function, bare necessities for basic vf
412 * operation have been implemented
414 static const struct eth_dev_ops igbvf_eth_dev_ops = {
415 .dev_configure = igbvf_dev_configure,
416 .dev_start = igbvf_dev_start,
417 .dev_stop = igbvf_dev_stop,
418 .dev_close = igbvf_dev_close,
419 .promiscuous_enable = igbvf_promiscuous_enable,
420 .promiscuous_disable = igbvf_promiscuous_disable,
421 .allmulticast_enable = igbvf_allmulticast_enable,
422 .allmulticast_disable = igbvf_allmulticast_disable,
423 .link_update = eth_igb_link_update,
424 .stats_get = eth_igbvf_stats_get,
425 .xstats_get = eth_igbvf_xstats_get,
426 .xstats_get_names = eth_igbvf_xstats_get_names,
427 .stats_reset = eth_igbvf_stats_reset,
428 .xstats_reset = eth_igbvf_stats_reset,
429 .vlan_filter_set = igbvf_vlan_filter_set,
430 .dev_infos_get = eth_igbvf_infos_get,
431 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
432 .rx_queue_setup = eth_igb_rx_queue_setup,
433 .rx_queue_release = eth_igb_rx_queue_release,
434 .tx_queue_setup = eth_igb_tx_queue_setup,
435 .tx_queue_release = eth_igb_tx_queue_release,
436 .set_mc_addr_list = eth_igb_set_mc_addr_list,
437 .rxq_info_get = igb_rxq_info_get,
438 .txq_info_get = igb_txq_info_get,
439 .mac_addr_set = igbvf_default_mac_addr_set,
440 .get_reg = igbvf_get_regs,
443 /* store statistics names and its offset in stats structure */
444 struct rte_igb_xstats_name_off {
445 char name[RTE_ETH_XSTATS_NAME_SIZE];
449 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
450 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
451 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
452 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
453 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
454 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
455 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
456 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
458 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
459 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
460 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
461 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
462 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
463 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
464 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
465 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
466 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
467 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
468 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
470 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
471 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
472 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
473 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
474 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
476 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
478 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
479 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
480 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
481 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
482 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
483 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
484 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
485 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
486 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
487 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
488 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
489 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
490 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
491 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
492 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
493 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
494 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
495 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
497 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
499 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
500 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
501 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
502 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
503 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
504 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
505 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
507 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
510 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
511 sizeof(rte_igb_stats_strings[0]))
513 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
514 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
515 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
516 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
517 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
518 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
521 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
522 sizeof(rte_igbvf_stats_strings[0]))
526 igb_intr_enable(struct rte_eth_dev *dev)
528 struct e1000_interrupt *intr =
529 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
530 struct e1000_hw *hw =
531 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
533 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
534 E1000_WRITE_FLUSH(hw);
538 igb_intr_disable(struct e1000_hw *hw)
540 E1000_WRITE_REG(hw, E1000_IMC, ~0);
541 E1000_WRITE_FLUSH(hw);
545 igbvf_intr_enable(struct rte_eth_dev *dev)
547 struct e1000_hw *hw =
548 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
550 /* only for mailbox */
551 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
552 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
553 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
554 E1000_WRITE_FLUSH(hw);
557 /* only for mailbox now. If RX/TX needed, should extend this function. */
559 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
564 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
565 tmp |= E1000_VTIVAR_VALID;
566 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
570 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
572 struct e1000_hw *hw =
573 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
575 /* Configure VF other cause ivar */
576 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
579 static inline int32_t
580 igb_pf_reset_hw(struct e1000_hw *hw)
585 status = e1000_reset_hw(hw);
587 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
588 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
589 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
590 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
591 E1000_WRITE_FLUSH(hw);
597 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
599 struct e1000_hw *hw =
600 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
603 hw->vendor_id = pci_dev->id.vendor_id;
604 hw->device_id = pci_dev->id.device_id;
605 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
606 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
608 e1000_set_mac_type(hw);
610 /* need to check if it is a vf device below */
614 igb_reset_swfw_lock(struct e1000_hw *hw)
619 * Do mac ops initialization manually here, since we will need
620 * some function pointers set by this call.
622 ret_val = e1000_init_mac_params(hw);
627 * SMBI lock should not fail in this early stage. If this is the case,
628 * it is due to an improper exit of the application.
629 * So force the release of the faulty lock.
631 if (e1000_get_hw_semaphore_generic(hw) < 0) {
632 PMD_DRV_LOG(DEBUG, "SMBI lock released");
634 e1000_put_hw_semaphore_generic(hw);
636 if (hw->mac.ops.acquire_swfw_sync != NULL) {
640 * Phy lock should not fail in this early stage. If this is the case,
641 * it is due to an improper exit of the application.
642 * So force the release of the faulty lock.
644 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
645 if (hw->bus.func > E1000_FUNC_1)
647 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
648 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
651 hw->mac.ops.release_swfw_sync(hw, mask);
654 * This one is more tricky since it is common to all ports; but
655 * swfw_sync retries last long enough (1s) to be almost sure that if
656 * lock can not be taken it is due to an improper lock of the
659 mask = E1000_SWFW_EEP_SM;
660 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
661 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
663 hw->mac.ops.release_swfw_sync(hw, mask);
666 return E1000_SUCCESS;
669 /* Remove all ntuple filters of the device */
670 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
672 struct e1000_filter_info *filter_info =
673 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
674 struct e1000_5tuple_filter *p_5tuple;
675 struct e1000_2tuple_filter *p_2tuple;
677 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
678 TAILQ_REMOVE(&filter_info->fivetuple_list,
682 filter_info->fivetuple_mask = 0;
683 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
684 TAILQ_REMOVE(&filter_info->twotuple_list,
688 filter_info->twotuple_mask = 0;
693 /* Remove all flex filters of the device */
694 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
696 struct e1000_filter_info *filter_info =
697 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
698 struct e1000_flex_filter *p_flex;
700 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
701 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
704 filter_info->flex_mask = 0;
710 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
713 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
714 struct e1000_hw *hw =
715 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
716 struct e1000_vfta * shadow_vfta =
717 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
718 struct e1000_filter_info *filter_info =
719 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
720 struct e1000_adapter *adapter =
721 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
725 eth_dev->dev_ops = ð_igb_ops;
726 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
727 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
728 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
730 /* for secondary processes, we don't initialise any further as primary
731 * has already done this work. Only check we don't need a different
733 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
734 if (eth_dev->data->scattered_rx)
735 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
739 rte_eth_copy_pci_info(eth_dev, pci_dev);
741 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
743 igb_identify_hardware(eth_dev, pci_dev);
744 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
749 e1000_get_bus_info(hw);
751 /* Reset any pending lock */
752 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
757 /* Finish initialization */
758 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
764 hw->phy.autoneg_wait_to_complete = 0;
765 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
768 if (hw->phy.media_type == e1000_media_type_copper) {
769 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
770 hw->phy.disable_polarity_correction = 0;
771 hw->phy.ms_type = e1000_ms_hw_default;
775 * Start from a known state, this is important in reading the nvm
780 /* Make sure we have a good EEPROM before we read from it */
781 if (e1000_validate_nvm_checksum(hw) < 0) {
783 * Some PCI-E parts fail the first check due to
784 * the link being in sleep state, call it again,
785 * if it fails a second time its a real issue.
787 if (e1000_validate_nvm_checksum(hw) < 0) {
788 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
794 /* Read the permanent MAC address out of the EEPROM */
795 if (e1000_read_mac_addr(hw) != 0) {
796 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
801 /* Allocate memory for storing MAC addresses */
802 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
803 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
804 if (eth_dev->data->mac_addrs == NULL) {
805 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
806 "store MAC addresses",
807 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
812 /* Copy the permanent MAC address */
813 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
815 /* initialize the vfta */
816 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
818 /* Now initialize the hardware */
819 if (igb_hardware_init(hw) != 0) {
820 PMD_INIT_LOG(ERR, "Hardware initialization failed");
821 rte_free(eth_dev->data->mac_addrs);
822 eth_dev->data->mac_addrs = NULL;
826 hw->mac.get_link_status = 1;
827 adapter->stopped = 0;
829 /* Indicate SOL/IDER usage */
830 if (e1000_check_reset_block(hw) < 0) {
831 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
835 /* initialize PF if max_vfs not zero */
836 igb_pf_host_init(eth_dev);
838 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
839 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
840 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
841 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
842 E1000_WRITE_FLUSH(hw);
844 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
845 eth_dev->data->port_id, pci_dev->id.vendor_id,
846 pci_dev->id.device_id);
848 rte_intr_callback_register(&pci_dev->intr_handle,
849 eth_igb_interrupt_handler,
852 /* enable uio/vfio intr/eventfd mapping */
853 rte_intr_enable(&pci_dev->intr_handle);
855 /* enable support intr */
856 igb_intr_enable(eth_dev);
858 /* initialize filter info */
859 memset(filter_info, 0,
860 sizeof(struct e1000_filter_info));
862 TAILQ_INIT(&filter_info->flex_list);
863 TAILQ_INIT(&filter_info->twotuple_list);
864 TAILQ_INIT(&filter_info->fivetuple_list);
866 TAILQ_INIT(&igb_filter_ntuple_list);
867 TAILQ_INIT(&igb_filter_ethertype_list);
868 TAILQ_INIT(&igb_filter_syn_list);
869 TAILQ_INIT(&igb_filter_flex_list);
870 TAILQ_INIT(&igb_filter_rss_list);
871 TAILQ_INIT(&igb_flow_list);
876 igb_hw_control_release(hw);
882 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
884 struct rte_pci_device *pci_dev;
885 struct rte_intr_handle *intr_handle;
887 struct e1000_adapter *adapter =
888 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
889 struct e1000_filter_info *filter_info =
890 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
892 PMD_INIT_FUNC_TRACE();
894 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
897 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
898 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
899 intr_handle = &pci_dev->intr_handle;
901 if (adapter->stopped == 0)
902 eth_igb_close(eth_dev);
904 eth_dev->dev_ops = NULL;
905 eth_dev->rx_pkt_burst = NULL;
906 eth_dev->tx_pkt_burst = NULL;
908 /* Reset any pending lock */
909 igb_reset_swfw_lock(hw);
911 rte_free(eth_dev->data->mac_addrs);
912 eth_dev->data->mac_addrs = NULL;
914 /* uninitialize PF if max_vfs not zero */
915 igb_pf_host_uninit(eth_dev);
917 /* disable uio intr before callback unregister */
918 rte_intr_disable(intr_handle);
919 rte_intr_callback_unregister(intr_handle,
920 eth_igb_interrupt_handler, eth_dev);
922 /* clear the SYN filter info */
923 filter_info->syn_info = 0;
925 /* clear the ethertype filters info */
926 filter_info->ethertype_mask = 0;
927 memset(filter_info->ethertype_filters, 0,
928 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
930 /* clear the rss filter info */
931 memset(&filter_info->rss_info, 0,
932 sizeof(struct igb_rte_flow_rss_conf));
934 /* remove all ntuple filters of the device */
935 igb_ntuple_filter_uninit(eth_dev);
937 /* remove all flex filters of the device */
938 igb_flex_filter_uninit(eth_dev);
940 /* clear all the filters list */
941 igb_filterlist_flush(eth_dev);
947 * Virtual Function device init
950 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
952 struct rte_pci_device *pci_dev;
953 struct rte_intr_handle *intr_handle;
954 struct e1000_adapter *adapter =
955 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
956 struct e1000_hw *hw =
957 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
959 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
961 PMD_INIT_FUNC_TRACE();
963 eth_dev->dev_ops = &igbvf_eth_dev_ops;
964 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
965 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
966 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
968 /* for secondary processes, we don't initialise any further as primary
969 * has already done this work. Only check we don't need a different
971 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
972 if (eth_dev->data->scattered_rx)
973 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
977 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
978 rte_eth_copy_pci_info(eth_dev, pci_dev);
980 hw->device_id = pci_dev->id.device_id;
981 hw->vendor_id = pci_dev->id.vendor_id;
982 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
983 adapter->stopped = 0;
985 /* Initialize the shared code (base driver) */
986 diag = e1000_setup_init_funcs(hw, TRUE);
988 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
993 /* init_mailbox_params */
994 hw->mbx.ops.init_params(hw);
996 /* Disable the interrupts for VF */
997 igbvf_intr_disable(hw);
999 diag = hw->mac.ops.reset_hw(hw);
1001 /* Allocate memory for storing MAC addresses */
1002 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003 hw->mac.rar_entry_count, 0);
1004 if (eth_dev->data->mac_addrs == NULL) {
1006 "Failed to allocate %d bytes needed to store MAC "
1008 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1012 /* Generate a random MAC address, if none was assigned by PF. */
1013 if (is_zero_ether_addr(perm_addr)) {
1014 eth_random_addr(perm_addr->addr_bytes);
1015 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1016 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1017 "%02x:%02x:%02x:%02x:%02x:%02x",
1018 perm_addr->addr_bytes[0],
1019 perm_addr->addr_bytes[1],
1020 perm_addr->addr_bytes[2],
1021 perm_addr->addr_bytes[3],
1022 perm_addr->addr_bytes[4],
1023 perm_addr->addr_bytes[5]);
1026 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1028 rte_free(eth_dev->data->mac_addrs);
1029 eth_dev->data->mac_addrs = NULL;
1032 /* Copy the permanent MAC address */
1033 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034 ð_dev->data->mac_addrs[0]);
1036 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1038 eth_dev->data->port_id, pci_dev->id.vendor_id,
1039 pci_dev->id.device_id, "igb_mac_82576_vf");
1041 intr_handle = &pci_dev->intr_handle;
1042 rte_intr_callback_register(intr_handle,
1043 eth_igbvf_interrupt_handler, eth_dev);
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1051 struct e1000_adapter *adapter =
1052 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1055 PMD_INIT_FUNC_TRACE();
1057 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1060 if (adapter->stopped == 0)
1061 igbvf_dev_close(eth_dev);
1063 eth_dev->dev_ops = NULL;
1064 eth_dev->rx_pkt_burst = NULL;
1065 eth_dev->tx_pkt_burst = NULL;
1067 rte_free(eth_dev->data->mac_addrs);
1068 eth_dev->data->mac_addrs = NULL;
1070 /* disable uio intr before callback unregister */
1071 rte_intr_disable(&pci_dev->intr_handle);
1072 rte_intr_callback_unregister(&pci_dev->intr_handle,
1073 eth_igbvf_interrupt_handler,
1079 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1080 struct rte_pci_device *pci_dev)
1082 return rte_eth_dev_pci_generic_probe(pci_dev,
1083 sizeof(struct e1000_adapter), eth_igb_dev_init);
1086 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1088 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1091 static struct rte_pci_driver rte_igb_pmd = {
1092 .id_table = pci_id_igb_map,
1093 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1094 RTE_PCI_DRV_IOVA_AS_VA,
1095 .probe = eth_igb_pci_probe,
1096 .remove = eth_igb_pci_remove,
1100 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1101 struct rte_pci_device *pci_dev)
1103 return rte_eth_dev_pci_generic_probe(pci_dev,
1104 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1107 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1109 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1113 * virtual function driver struct
1115 static struct rte_pci_driver rte_igbvf_pmd = {
1116 .id_table = pci_id_igbvf_map,
1117 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1118 .probe = eth_igbvf_pci_probe,
1119 .remove = eth_igbvf_pci_remove,
1123 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1125 struct e1000_hw *hw =
1126 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1128 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1129 rctl |= E1000_RCTL_VFE;
1130 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1134 igb_check_mq_mode(struct rte_eth_dev *dev)
1136 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1137 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1138 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1139 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1141 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1142 tx_mq_mode == ETH_MQ_TX_DCB ||
1143 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1144 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1147 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1148 /* Check multi-queue mode.
1149 * To no break software we accept ETH_MQ_RX_NONE as this might
1150 * be used to turn off VLAN filter.
1153 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1154 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1155 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1156 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1158 /* Only support one queue on VFs.
1159 * RSS together with SRIOV is not supported.
1161 PMD_INIT_LOG(ERR, "SRIOV is active,"
1162 " wrong mq_mode rx %d.",
1166 /* TX mode is not used here, so mode might be ignored.*/
1167 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1168 /* SRIOV only works in VMDq enable mode */
1169 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1170 " TX mode %d is not supported. "
1171 " Driver will behave as %d mode.",
1172 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1175 /* check valid queue number */
1176 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1177 PMD_INIT_LOG(ERR, "SRIOV is active,"
1178 " only support one queue on VFs.");
1182 /* To no break software that set invalid mode, only display
1183 * warning if invalid mode is used.
1185 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1186 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1187 rx_mq_mode != ETH_MQ_RX_RSS) {
1188 /* RSS together with VMDq not supported*/
1189 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1194 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1195 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1196 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1197 " Due to txmode is meaningless in this"
1198 " driver, just ignore.",
1206 eth_igb_configure(struct rte_eth_dev *dev)
1208 struct e1000_interrupt *intr =
1209 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1212 PMD_INIT_FUNC_TRACE();
1214 /* multipe queue mode checking */
1215 ret = igb_check_mq_mode(dev);
1217 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1222 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1223 PMD_INIT_FUNC_TRACE();
1229 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1232 struct e1000_hw *hw =
1233 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234 uint32_t tctl, rctl;
1236 tctl = E1000_READ_REG(hw, E1000_TCTL);
1237 rctl = E1000_READ_REG(hw, E1000_RCTL);
1241 tctl |= E1000_TCTL_EN;
1242 rctl |= E1000_RCTL_EN;
1245 tctl &= ~E1000_TCTL_EN;
1246 rctl &= ~E1000_RCTL_EN;
1248 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1249 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1250 E1000_WRITE_FLUSH(hw);
1254 eth_igb_start(struct rte_eth_dev *dev)
1256 struct e1000_hw *hw =
1257 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1258 struct e1000_adapter *adapter =
1259 E1000_DEV_PRIVATE(dev->data->dev_private);
1260 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1261 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1263 uint32_t intr_vector = 0;
1269 PMD_INIT_FUNC_TRACE();
1271 /* disable uio/vfio intr/eventfd mapping */
1272 rte_intr_disable(intr_handle);
1274 /* Power up the phy. Needed to make the link go Up */
1275 eth_igb_dev_set_link_up(dev);
1278 * Packet Buffer Allocation (PBA)
1279 * Writing PBA sets the receive portion of the buffer
1280 * the remainder is used for the transmit buffer.
1282 if (hw->mac.type == e1000_82575) {
1285 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1286 E1000_WRITE_REG(hw, E1000_PBA, pba);
1289 /* Put the address into the Receive Address Array */
1290 e1000_rar_set(hw, hw->mac.addr, 0);
1292 /* Initialize the hardware */
1293 if (igb_hardware_init(hw)) {
1294 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1297 adapter->stopped = 0;
1299 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1301 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1302 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1303 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1304 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1305 E1000_WRITE_FLUSH(hw);
1307 /* configure PF module if SRIOV enabled */
1308 igb_pf_host_configure(dev);
1310 /* check and configure queue intr-vector mapping */
1311 if ((rte_intr_cap_multiple(intr_handle) ||
1312 !RTE_ETH_DEV_SRIOV(dev).active) &&
1313 dev->data->dev_conf.intr_conf.rxq != 0) {
1314 intr_vector = dev->data->nb_rx_queues;
1315 if (rte_intr_efd_enable(intr_handle, intr_vector))
1319 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1320 intr_handle->intr_vec =
1321 rte_zmalloc("intr_vec",
1322 dev->data->nb_rx_queues * sizeof(int), 0);
1323 if (intr_handle->intr_vec == NULL) {
1324 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1325 " intr_vec", dev->data->nb_rx_queues);
1330 /* confiugre msix for rx interrupt */
1331 eth_igb_configure_msix_intr(dev);
1333 /* Configure for OS presence */
1334 igb_init_manageability(hw);
1336 eth_igb_tx_init(dev);
1338 /* This can fail when allocating mbufs for descriptor rings */
1339 ret = eth_igb_rx_init(dev);
1341 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1342 igb_dev_clear_queues(dev);
1346 e1000_clear_hw_cntrs_base_generic(hw);
1349 * VLAN Offload Settings
1351 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1352 ETH_VLAN_EXTEND_MASK;
1353 ret = eth_igb_vlan_offload_set(dev, mask);
1355 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1356 igb_dev_clear_queues(dev);
1360 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1361 /* Enable VLAN filter since VMDq always use VLAN filter */
1362 igb_vmdq_vlan_hw_filter_enable(dev);
1365 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1366 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1367 (hw->mac.type == e1000_i211)) {
1368 /* Configure EITR with the maximum possible value (0xFFFF) */
1369 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1372 /* Setup link speed and duplex */
1373 speeds = &dev->data->dev_conf.link_speeds;
1374 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1375 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1376 hw->mac.autoneg = 1;
1379 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1382 hw->phy.autoneg_advertised = 0;
1384 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1385 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1386 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1388 goto error_invalid_config;
1390 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1391 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1394 if (*speeds & ETH_LINK_SPEED_10M) {
1395 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1398 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1399 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1402 if (*speeds & ETH_LINK_SPEED_100M) {
1403 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1406 if (*speeds & ETH_LINK_SPEED_1G) {
1407 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1410 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1411 goto error_invalid_config;
1413 /* Set/reset the mac.autoneg based on the link speed,
1417 hw->mac.autoneg = 0;
1418 hw->mac.forced_speed_duplex =
1419 hw->phy.autoneg_advertised;
1421 hw->mac.autoneg = 1;
1425 e1000_setup_link(hw);
1427 if (rte_intr_allow_others(intr_handle)) {
1428 /* check if lsc interrupt is enabled */
1429 if (dev->data->dev_conf.intr_conf.lsc != 0)
1430 eth_igb_lsc_interrupt_setup(dev, TRUE);
1432 eth_igb_lsc_interrupt_setup(dev, FALSE);
1434 rte_intr_callback_unregister(intr_handle,
1435 eth_igb_interrupt_handler,
1437 if (dev->data->dev_conf.intr_conf.lsc != 0)
1438 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1439 " no intr multiplex");
1442 /* check if rxq interrupt is enabled */
1443 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1444 rte_intr_dp_is_en(intr_handle))
1445 eth_igb_rxq_interrupt_setup(dev);
1447 /* enable uio/vfio intr/eventfd mapping */
1448 rte_intr_enable(intr_handle);
1450 /* resume enabled intr since hw reset */
1451 igb_intr_enable(dev);
1453 /* restore all types filter */
1454 igb_filter_restore(dev);
1456 eth_igb_rxtx_control(dev, true);
1457 eth_igb_link_update(dev, 0);
1459 PMD_INIT_LOG(DEBUG, "<<");
1463 error_invalid_config:
1464 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1465 dev->data->dev_conf.link_speeds, dev->data->port_id);
1466 igb_dev_clear_queues(dev);
1470 /*********************************************************************
1472 * This routine disables all traffic on the adapter by issuing a
1473 * global reset on the MAC.
1475 **********************************************************************/
1477 eth_igb_stop(struct rte_eth_dev *dev)
1479 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1480 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1481 struct rte_eth_link link;
1482 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1484 eth_igb_rxtx_control(dev, false);
1486 igb_intr_disable(hw);
1488 /* disable intr eventfd mapping */
1489 rte_intr_disable(intr_handle);
1491 igb_pf_reset_hw(hw);
1492 E1000_WRITE_REG(hw, E1000_WUC, 0);
1494 /* Set bit for Go Link disconnect */
1495 if (hw->mac.type >= e1000_82580) {
1498 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1499 phpm_reg |= E1000_82580_PM_GO_LINKD;
1500 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1503 /* Power down the phy. Needed to make the link go Down */
1504 eth_igb_dev_set_link_down(dev);
1506 igb_dev_clear_queues(dev);
1508 /* clear the recorded link status */
1509 memset(&link, 0, sizeof(link));
1510 rte_eth_linkstatus_set(dev, &link);
1512 if (!rte_intr_allow_others(intr_handle))
1513 /* resume to the default handler */
1514 rte_intr_callback_register(intr_handle,
1515 eth_igb_interrupt_handler,
1518 /* Clean datapath event and queue/vec mapping */
1519 rte_intr_efd_disable(intr_handle);
1520 if (intr_handle->intr_vec != NULL) {
1521 rte_free(intr_handle->intr_vec);
1522 intr_handle->intr_vec = NULL;
1527 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1529 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1531 if (hw->phy.media_type == e1000_media_type_copper)
1532 e1000_power_up_phy(hw);
1534 e1000_power_up_fiber_serdes_link(hw);
1540 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1542 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1544 if (hw->phy.media_type == e1000_media_type_copper)
1545 e1000_power_down_phy(hw);
1547 e1000_shutdown_fiber_serdes_link(hw);
1553 eth_igb_close(struct rte_eth_dev *dev)
1555 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556 struct e1000_adapter *adapter =
1557 E1000_DEV_PRIVATE(dev->data->dev_private);
1558 struct rte_eth_link link;
1559 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1560 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1563 adapter->stopped = 1;
1565 e1000_phy_hw_reset(hw);
1566 igb_release_manageability(hw);
1567 igb_hw_control_release(hw);
1569 /* Clear bit for Go Link disconnect */
1570 if (hw->mac.type >= e1000_82580) {
1573 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1574 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1575 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1578 igb_dev_free_queues(dev);
1580 if (intr_handle->intr_vec) {
1581 rte_free(intr_handle->intr_vec);
1582 intr_handle->intr_vec = NULL;
1585 memset(&link, 0, sizeof(link));
1586 rte_eth_linkstatus_set(dev, &link);
1590 igb_get_rx_buffer_size(struct e1000_hw *hw)
1592 uint32_t rx_buf_size;
1593 if (hw->mac.type == e1000_82576) {
1594 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1595 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1596 /* PBS needs to be translated according to a lookup table */
1597 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1598 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1599 rx_buf_size = (rx_buf_size << 10);
1600 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1601 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1603 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1609 /*********************************************************************
1611 * Initialize the hardware
1613 **********************************************************************/
1615 igb_hardware_init(struct e1000_hw *hw)
1617 uint32_t rx_buf_size;
1620 /* Let the firmware know the OS is in control */
1621 igb_hw_control_acquire(hw);
1624 * These parameters control the automatic generation (Tx) and
1625 * response (Rx) to Ethernet PAUSE frames.
1626 * - High water mark should allow for at least two standard size (1518)
1627 * frames to be received after sending an XOFF.
1628 * - Low water mark works best when it is very near the high water mark.
1629 * This allows the receiver to restart by sending XON when it has
1630 * drained a bit. Here we use an arbitrary value of 1500 which will
1631 * restart after one full frame is pulled from the buffer. There
1632 * could be several smaller frames in the buffer and if so they will
1633 * not trigger the XON until their total number reduces the buffer
1635 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1637 rx_buf_size = igb_get_rx_buffer_size(hw);
1639 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1640 hw->fc.low_water = hw->fc.high_water - 1500;
1641 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1642 hw->fc.send_xon = 1;
1644 /* Set Flow control, use the tunable location if sane */
1645 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1646 hw->fc.requested_mode = igb_fc_setting;
1648 hw->fc.requested_mode = e1000_fc_none;
1650 /* Issue a global reset */
1651 igb_pf_reset_hw(hw);
1652 E1000_WRITE_REG(hw, E1000_WUC, 0);
1654 diag = e1000_init_hw(hw);
1658 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1659 e1000_get_phy_info(hw);
1660 e1000_check_for_link(hw);
1665 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1667 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1671 uint64_t old_gprc = stats->gprc;
1672 uint64_t old_gptc = stats->gptc;
1673 uint64_t old_tpr = stats->tpr;
1674 uint64_t old_tpt = stats->tpt;
1675 uint64_t old_rpthc = stats->rpthc;
1676 uint64_t old_hgptc = stats->hgptc;
1678 if(hw->phy.media_type == e1000_media_type_copper ||
1679 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1681 E1000_READ_REG(hw,E1000_SYMERRS);
1682 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1685 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1686 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1687 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1688 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1690 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1691 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1692 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1693 stats->dc += E1000_READ_REG(hw, E1000_DC);
1694 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1695 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1696 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1698 ** For watchdog management we need to know if we have been
1699 ** paused during the last interval, so capture that here.
1701 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1702 stats->xoffrxc += pause_frames;
1703 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1704 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1705 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1706 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1707 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1708 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1709 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1710 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1711 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1712 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1713 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1714 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1716 /* For the 64-bit byte counters the low dword must be read first. */
1717 /* Both registers clear on the read of the high dword */
1719 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1720 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1721 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1722 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1723 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1724 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1725 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1727 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1728 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1729 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1730 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1731 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1733 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1734 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1736 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1737 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1738 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1739 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1740 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1741 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1743 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1744 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1745 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1746 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1747 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1748 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1749 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1750 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1752 /* Interrupt Counts */
1754 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1755 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1756 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1757 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1758 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1759 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1760 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1761 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1762 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1764 /* Host to Card Statistics */
1766 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1767 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1768 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1769 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1770 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1771 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1772 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1773 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1774 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1775 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1776 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1777 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1778 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1779 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1780 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1781 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1783 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1784 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1785 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1786 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1787 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1788 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1792 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1794 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795 struct e1000_hw_stats *stats =
1796 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1798 igb_read_stats_registers(hw, stats);
1800 if (rte_stats == NULL)
1804 rte_stats->imissed = stats->mpc;
1805 rte_stats->ierrors = stats->crcerrs +
1806 stats->rlec + stats->ruc + stats->roc +
1807 stats->rxerrc + stats->algnerrc + stats->cexterr;
1810 rte_stats->oerrors = stats->ecol + stats->latecol;
1812 rte_stats->ipackets = stats->gprc;
1813 rte_stats->opackets = stats->gptc;
1814 rte_stats->ibytes = stats->gorc;
1815 rte_stats->obytes = stats->gotc;
1820 eth_igb_stats_reset(struct rte_eth_dev *dev)
1822 struct e1000_hw_stats *hw_stats =
1823 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1825 /* HW registers are cleared on read */
1826 eth_igb_stats_get(dev, NULL);
1828 /* Reset software totals */
1829 memset(hw_stats, 0, sizeof(*hw_stats));
1833 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1835 struct e1000_hw_stats *stats =
1836 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1838 /* HW registers are cleared on read */
1839 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1841 /* Reset software totals */
1842 memset(stats, 0, sizeof(*stats));
1845 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1846 struct rte_eth_xstat_name *xstats_names,
1847 __rte_unused unsigned int size)
1851 if (xstats_names == NULL)
1852 return IGB_NB_XSTATS;
1854 /* Note: limit checked in rte_eth_xstats_names() */
1856 for (i = 0; i < IGB_NB_XSTATS; i++) {
1857 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1858 "%s", rte_igb_stats_strings[i].name);
1861 return IGB_NB_XSTATS;
1864 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1865 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1871 if (xstats_names == NULL)
1872 return IGB_NB_XSTATS;
1874 for (i = 0; i < IGB_NB_XSTATS; i++)
1875 snprintf(xstats_names[i].name,
1876 sizeof(xstats_names[i].name),
1877 "%s", rte_igb_stats_strings[i].name);
1879 return IGB_NB_XSTATS;
1882 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1884 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1887 for (i = 0; i < limit; i++) {
1888 if (ids[i] >= IGB_NB_XSTATS) {
1889 PMD_INIT_LOG(ERR, "id value isn't valid");
1892 strcpy(xstats_names[i].name,
1893 xstats_names_copy[ids[i]].name);
1900 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1903 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904 struct e1000_hw_stats *hw_stats =
1905 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1908 if (n < IGB_NB_XSTATS)
1909 return IGB_NB_XSTATS;
1911 igb_read_stats_registers(hw, hw_stats);
1913 /* If this is a reset xstats is NULL, and we have cleared the
1914 * registers by reading them.
1919 /* Extended stats */
1920 for (i = 0; i < IGB_NB_XSTATS; i++) {
1922 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1923 rte_igb_stats_strings[i].offset);
1926 return IGB_NB_XSTATS;
1930 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1931 uint64_t *values, unsigned int n)
1936 struct e1000_hw *hw =
1937 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938 struct e1000_hw_stats *hw_stats =
1939 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1941 if (n < IGB_NB_XSTATS)
1942 return IGB_NB_XSTATS;
1944 igb_read_stats_registers(hw, hw_stats);
1946 /* If this is a reset xstats is NULL, and we have cleared the
1947 * registers by reading them.
1952 /* Extended stats */
1953 for (i = 0; i < IGB_NB_XSTATS; i++)
1954 values[i] = *(uint64_t *)(((char *)hw_stats) +
1955 rte_igb_stats_strings[i].offset);
1957 return IGB_NB_XSTATS;
1960 uint64_t values_copy[IGB_NB_XSTATS];
1962 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1965 for (i = 0; i < n; i++) {
1966 if (ids[i] >= IGB_NB_XSTATS) {
1967 PMD_INIT_LOG(ERR, "id value isn't valid");
1970 values[i] = values_copy[ids[i]];
1977 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1979 /* Good Rx packets, include VF loopback */
1980 UPDATE_VF_STAT(E1000_VFGPRC,
1981 hw_stats->last_gprc, hw_stats->gprc);
1983 /* Good Rx octets, include VF loopback */
1984 UPDATE_VF_STAT(E1000_VFGORC,
1985 hw_stats->last_gorc, hw_stats->gorc);
1987 /* Good Tx packets, include VF loopback */
1988 UPDATE_VF_STAT(E1000_VFGPTC,
1989 hw_stats->last_gptc, hw_stats->gptc);
1991 /* Good Tx octets, include VF loopback */
1992 UPDATE_VF_STAT(E1000_VFGOTC,
1993 hw_stats->last_gotc, hw_stats->gotc);
1995 /* Rx Multicst packets */
1996 UPDATE_VF_STAT(E1000_VFMPRC,
1997 hw_stats->last_mprc, hw_stats->mprc);
1999 /* Good Rx loopback packets */
2000 UPDATE_VF_STAT(E1000_VFGPRLBC,
2001 hw_stats->last_gprlbc, hw_stats->gprlbc);
2003 /* Good Rx loopback octets */
2004 UPDATE_VF_STAT(E1000_VFGORLBC,
2005 hw_stats->last_gorlbc, hw_stats->gorlbc);
2007 /* Good Tx loopback packets */
2008 UPDATE_VF_STAT(E1000_VFGPTLBC,
2009 hw_stats->last_gptlbc, hw_stats->gptlbc);
2011 /* Good Tx loopback octets */
2012 UPDATE_VF_STAT(E1000_VFGOTLBC,
2013 hw_stats->last_gotlbc, hw_stats->gotlbc);
2016 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2017 struct rte_eth_xstat_name *xstats_names,
2018 __rte_unused unsigned limit)
2022 if (xstats_names != NULL)
2023 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2024 snprintf(xstats_names[i].name,
2025 sizeof(xstats_names[i].name), "%s",
2026 rte_igbvf_stats_strings[i].name);
2028 return IGBVF_NB_XSTATS;
2032 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2035 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2037 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2040 if (n < IGBVF_NB_XSTATS)
2041 return IGBVF_NB_XSTATS;
2043 igbvf_read_stats_registers(hw, hw_stats);
2048 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2050 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2051 rte_igbvf_stats_strings[i].offset);
2054 return IGBVF_NB_XSTATS;
2058 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2060 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2061 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2062 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2064 igbvf_read_stats_registers(hw, hw_stats);
2066 if (rte_stats == NULL)
2069 rte_stats->ipackets = hw_stats->gprc;
2070 rte_stats->ibytes = hw_stats->gorc;
2071 rte_stats->opackets = hw_stats->gptc;
2072 rte_stats->obytes = hw_stats->gotc;
2077 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2079 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2080 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2082 /* Sync HW register to the last stats */
2083 eth_igbvf_stats_get(dev, NULL);
2085 /* reset HW current stats*/
2086 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2087 offsetof(struct e1000_vf_stats, gprc));
2091 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2094 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095 struct e1000_fw_version fw;
2098 e1000_get_fw_version(hw, &fw);
2100 switch (hw->mac.type) {
2103 if (!(e1000_get_flash_presence_i210(hw))) {
2104 ret = snprintf(fw_version, fw_size,
2106 fw.invm_major, fw.invm_minor,
2112 /* if option rom is valid, display its version too */
2114 ret = snprintf(fw_version, fw_size,
2115 "%d.%d, 0x%08x, %d.%d.%d",
2116 fw.eep_major, fw.eep_minor, fw.etrack_id,
2117 fw.or_major, fw.or_build, fw.or_patch);
2120 if (fw.etrack_id != 0X0000) {
2121 ret = snprintf(fw_version, fw_size,
2123 fw.eep_major, fw.eep_minor,
2126 ret = snprintf(fw_version, fw_size,
2128 fw.eep_major, fw.eep_minor,
2135 ret += 1; /* add the size of '\0' */
2136 if (fw_size < (u32)ret)
2143 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2145 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2147 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2148 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2149 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2150 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2151 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2152 dev_info->rx_queue_offload_capa;
2153 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2154 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2155 dev_info->tx_queue_offload_capa;
2157 switch (hw->mac.type) {
2159 dev_info->max_rx_queues = 4;
2160 dev_info->max_tx_queues = 4;
2161 dev_info->max_vmdq_pools = 0;
2165 dev_info->max_rx_queues = 16;
2166 dev_info->max_tx_queues = 16;
2167 dev_info->max_vmdq_pools = ETH_8_POOLS;
2168 dev_info->vmdq_queue_num = 16;
2172 dev_info->max_rx_queues = 8;
2173 dev_info->max_tx_queues = 8;
2174 dev_info->max_vmdq_pools = ETH_8_POOLS;
2175 dev_info->vmdq_queue_num = 8;
2179 dev_info->max_rx_queues = 8;
2180 dev_info->max_tx_queues = 8;
2181 dev_info->max_vmdq_pools = ETH_8_POOLS;
2182 dev_info->vmdq_queue_num = 8;
2186 dev_info->max_rx_queues = 8;
2187 dev_info->max_tx_queues = 8;
2191 dev_info->max_rx_queues = 4;
2192 dev_info->max_tx_queues = 4;
2193 dev_info->max_vmdq_pools = 0;
2197 dev_info->max_rx_queues = 2;
2198 dev_info->max_tx_queues = 2;
2199 dev_info->max_vmdq_pools = 0;
2203 /* Should not happen */
2206 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2207 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2208 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2210 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2212 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2213 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2214 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2216 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2221 dev_info->default_txconf = (struct rte_eth_txconf) {
2223 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2224 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2225 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2231 dev_info->rx_desc_lim = rx_desc_lim;
2232 dev_info->tx_desc_lim = tx_desc_lim;
2234 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2235 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2239 static const uint32_t *
2240 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2242 static const uint32_t ptypes[] = {
2243 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2246 RTE_PTYPE_L3_IPV4_EXT,
2248 RTE_PTYPE_L3_IPV6_EXT,
2252 RTE_PTYPE_TUNNEL_IP,
2253 RTE_PTYPE_INNER_L3_IPV6,
2254 RTE_PTYPE_INNER_L3_IPV6_EXT,
2255 RTE_PTYPE_INNER_L4_TCP,
2256 RTE_PTYPE_INNER_L4_UDP,
2260 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2261 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2267 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2269 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2271 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2272 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2273 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2274 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2275 DEV_TX_OFFLOAD_IPV4_CKSUM |
2276 DEV_TX_OFFLOAD_UDP_CKSUM |
2277 DEV_TX_OFFLOAD_TCP_CKSUM |
2278 DEV_TX_OFFLOAD_SCTP_CKSUM |
2279 DEV_TX_OFFLOAD_TCP_TSO;
2280 switch (hw->mac.type) {
2282 dev_info->max_rx_queues = 2;
2283 dev_info->max_tx_queues = 2;
2285 case e1000_vfadapt_i350:
2286 dev_info->max_rx_queues = 1;
2287 dev_info->max_tx_queues = 1;
2290 /* Should not happen */
2294 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2295 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2296 dev_info->rx_queue_offload_capa;
2297 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2298 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2299 dev_info->tx_queue_offload_capa;
2301 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2303 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2304 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2305 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2307 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2312 dev_info->default_txconf = (struct rte_eth_txconf) {
2314 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2315 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2316 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2322 dev_info->rx_desc_lim = rx_desc_lim;
2323 dev_info->tx_desc_lim = tx_desc_lim;
2326 /* return 0 means link status changed, -1 means not changed */
2328 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2330 struct e1000_hw *hw =
2331 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2332 struct rte_eth_link link;
2333 int link_check, count;
2336 hw->mac.get_link_status = 1;
2338 /* possible wait-to-complete in up to 9 seconds */
2339 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2340 /* Read the real link status */
2341 switch (hw->phy.media_type) {
2342 case e1000_media_type_copper:
2343 /* Do the work to read phy */
2344 e1000_check_for_link(hw);
2345 link_check = !hw->mac.get_link_status;
2348 case e1000_media_type_fiber:
2349 e1000_check_for_link(hw);
2350 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2354 case e1000_media_type_internal_serdes:
2355 e1000_check_for_link(hw);
2356 link_check = hw->mac.serdes_has_link;
2359 /* VF device is type_unknown */
2360 case e1000_media_type_unknown:
2361 eth_igbvf_link_update(hw);
2362 link_check = !hw->mac.get_link_status;
2368 if (link_check || wait_to_complete == 0)
2370 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2372 memset(&link, 0, sizeof(link));
2374 /* Now we check if a transition has happened */
2376 uint16_t duplex, speed;
2377 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2378 link.link_duplex = (duplex == FULL_DUPLEX) ?
2379 ETH_LINK_FULL_DUPLEX :
2380 ETH_LINK_HALF_DUPLEX;
2381 link.link_speed = speed;
2382 link.link_status = ETH_LINK_UP;
2383 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2384 ETH_LINK_SPEED_FIXED);
2385 } else if (!link_check) {
2386 link.link_speed = 0;
2387 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2388 link.link_status = ETH_LINK_DOWN;
2389 link.link_autoneg = ETH_LINK_FIXED;
2392 return rte_eth_linkstatus_set(dev, &link);
2396 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2397 * For ASF and Pass Through versions of f/w this means
2398 * that the driver is loaded.
2401 igb_hw_control_acquire(struct e1000_hw *hw)
2405 /* Let firmware know the driver has taken over */
2406 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2407 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2411 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2412 * For ASF and Pass Through versions of f/w this means that the
2413 * driver is no longer loaded.
2416 igb_hw_control_release(struct e1000_hw *hw)
2420 /* Let firmware taken over control of h/w */
2421 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2422 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2423 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2427 * Bit of a misnomer, what this really means is
2428 * to enable OS management of the system... aka
2429 * to disable special hardware management features.
2432 igb_init_manageability(struct e1000_hw *hw)
2434 if (e1000_enable_mng_pass_thru(hw)) {
2435 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2436 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2438 /* disable hardware interception of ARP */
2439 manc &= ~(E1000_MANC_ARP_EN);
2441 /* enable receiving management packets to the host */
2442 manc |= E1000_MANC_EN_MNG2HOST;
2443 manc2h |= 1 << 5; /* Mng Port 623 */
2444 manc2h |= 1 << 6; /* Mng Port 664 */
2445 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2446 E1000_WRITE_REG(hw, E1000_MANC, manc);
2451 igb_release_manageability(struct e1000_hw *hw)
2453 if (e1000_enable_mng_pass_thru(hw)) {
2454 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2456 manc |= E1000_MANC_ARP_EN;
2457 manc &= ~E1000_MANC_EN_MNG2HOST;
2459 E1000_WRITE_REG(hw, E1000_MANC, manc);
2464 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2466 struct e1000_hw *hw =
2467 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2470 rctl = E1000_READ_REG(hw, E1000_RCTL);
2471 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2472 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2476 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2478 struct e1000_hw *hw =
2479 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2482 rctl = E1000_READ_REG(hw, E1000_RCTL);
2483 rctl &= (~E1000_RCTL_UPE);
2484 if (dev->data->all_multicast == 1)
2485 rctl |= E1000_RCTL_MPE;
2487 rctl &= (~E1000_RCTL_MPE);
2488 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2492 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2494 struct e1000_hw *hw =
2495 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498 rctl = E1000_READ_REG(hw, E1000_RCTL);
2499 rctl |= E1000_RCTL_MPE;
2500 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2504 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2506 struct e1000_hw *hw =
2507 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510 if (dev->data->promiscuous == 1)
2511 return; /* must remain in all_multicast mode */
2512 rctl = E1000_READ_REG(hw, E1000_RCTL);
2513 rctl &= (~E1000_RCTL_MPE);
2514 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2518 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2520 struct e1000_hw *hw =
2521 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522 struct e1000_vfta * shadow_vfta =
2523 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2528 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2529 E1000_VFTA_ENTRY_MASK);
2530 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2531 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2536 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2538 /* update local VFTA copy */
2539 shadow_vfta->vfta[vid_idx] = vfta;
2545 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2546 enum rte_vlan_type vlan_type,
2549 struct e1000_hw *hw =
2550 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2554 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2556 /* only outer TPID of double VLAN can be configured*/
2557 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2558 reg = E1000_READ_REG(hw, E1000_VET);
2559 reg = (reg & (~E1000_VET_VET_EXT)) |
2560 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2561 E1000_WRITE_REG(hw, E1000_VET, reg);
2566 /* all other TPID values are read-only*/
2567 PMD_DRV_LOG(ERR, "Not supported");
2573 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2575 struct e1000_hw *hw =
2576 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579 /* Filter Table Disable */
2580 reg = E1000_READ_REG(hw, E1000_RCTL);
2581 reg &= ~E1000_RCTL_CFIEN;
2582 reg &= ~E1000_RCTL_VFE;
2583 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2587 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2589 struct e1000_hw *hw =
2590 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591 struct e1000_vfta * shadow_vfta =
2592 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2596 /* Filter Table Enable, CFI not used for packet acceptance */
2597 reg = E1000_READ_REG(hw, E1000_RCTL);
2598 reg &= ~E1000_RCTL_CFIEN;
2599 reg |= E1000_RCTL_VFE;
2600 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2602 /* restore VFTA table */
2603 for (i = 0; i < IGB_VFTA_SIZE; i++)
2604 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2608 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2610 struct e1000_hw *hw =
2611 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614 /* VLAN Mode Disable */
2615 reg = E1000_READ_REG(hw, E1000_CTRL);
2616 reg &= ~E1000_CTRL_VME;
2617 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2621 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2623 struct e1000_hw *hw =
2624 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627 /* VLAN Mode Enable */
2628 reg = E1000_READ_REG(hw, E1000_CTRL);
2629 reg |= E1000_CTRL_VME;
2630 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2634 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2636 struct e1000_hw *hw =
2637 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640 /* CTRL_EXT: Extended VLAN */
2641 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2642 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2643 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2645 /* Update maximum packet length */
2646 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2647 E1000_WRITE_REG(hw, E1000_RLPML,
2648 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2653 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2655 struct e1000_hw *hw =
2656 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2659 /* CTRL_EXT: Extended VLAN */
2660 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2661 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2662 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2664 /* Update maximum packet length */
2665 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2666 E1000_WRITE_REG(hw, E1000_RLPML,
2667 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2672 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2674 struct rte_eth_rxmode *rxmode;
2676 rxmode = &dev->data->dev_conf.rxmode;
2677 if(mask & ETH_VLAN_STRIP_MASK){
2678 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2679 igb_vlan_hw_strip_enable(dev);
2681 igb_vlan_hw_strip_disable(dev);
2684 if(mask & ETH_VLAN_FILTER_MASK){
2685 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2686 igb_vlan_hw_filter_enable(dev);
2688 igb_vlan_hw_filter_disable(dev);
2691 if(mask & ETH_VLAN_EXTEND_MASK){
2692 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2693 igb_vlan_hw_extend_enable(dev);
2695 igb_vlan_hw_extend_disable(dev);
2703 * It enables the interrupt mask and then enable the interrupt.
2706 * Pointer to struct rte_eth_dev.
2711 * - On success, zero.
2712 * - On failure, a negative value.
2715 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2717 struct e1000_interrupt *intr =
2718 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2721 intr->mask |= E1000_ICR_LSC;
2723 intr->mask &= ~E1000_ICR_LSC;
2728 /* It clears the interrupt causes and enables the interrupt.
2729 * It will be called once only during nic initialized.
2732 * Pointer to struct rte_eth_dev.
2735 * - On success, zero.
2736 * - On failure, a negative value.
2738 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2740 uint32_t mask, regval;
2741 struct e1000_hw *hw =
2742 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743 struct rte_eth_dev_info dev_info;
2745 memset(&dev_info, 0, sizeof(dev_info));
2746 eth_igb_infos_get(dev, &dev_info);
2748 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2749 regval = E1000_READ_REG(hw, E1000_EIMS);
2750 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2756 * It reads ICR and gets interrupt causes, check it and set a bit flag
2757 * to update link status.
2760 * Pointer to struct rte_eth_dev.
2763 * - On success, zero.
2764 * - On failure, a negative value.
2767 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2770 struct e1000_hw *hw =
2771 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2772 struct e1000_interrupt *intr =
2773 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2775 igb_intr_disable(hw);
2777 /* read-on-clear nic registers here */
2778 icr = E1000_READ_REG(hw, E1000_ICR);
2781 if (icr & E1000_ICR_LSC) {
2782 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2785 if (icr & E1000_ICR_VMMB)
2786 intr->flags |= E1000_FLAG_MAILBOX;
2792 * It executes link_update after knowing an interrupt is prsent.
2795 * Pointer to struct rte_eth_dev.
2798 * - On success, zero.
2799 * - On failure, a negative value.
2802 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2803 struct rte_intr_handle *intr_handle)
2805 struct e1000_hw *hw =
2806 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807 struct e1000_interrupt *intr =
2808 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2809 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2810 struct rte_eth_link link;
2813 if (intr->flags & E1000_FLAG_MAILBOX) {
2814 igb_pf_mbx_process(dev);
2815 intr->flags &= ~E1000_FLAG_MAILBOX;
2818 igb_intr_enable(dev);
2819 rte_intr_enable(intr_handle);
2821 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2822 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2824 /* set get_link_status to check register later */
2825 hw->mac.get_link_status = 1;
2826 ret = eth_igb_link_update(dev, 0);
2828 /* check if link has changed */
2832 rte_eth_linkstatus_get(dev, &link);
2833 if (link.link_status) {
2835 " Port %d: Link Up - speed %u Mbps - %s",
2837 (unsigned)link.link_speed,
2838 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2839 "full-duplex" : "half-duplex");
2841 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2842 dev->data->port_id);
2845 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2846 pci_dev->addr.domain,
2848 pci_dev->addr.devid,
2849 pci_dev->addr.function);
2850 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2858 * Interrupt handler which shall be registered at first.
2861 * Pointer to interrupt handle.
2863 * The address of parameter (struct rte_eth_dev *) regsitered before.
2869 eth_igb_interrupt_handler(void *param)
2871 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2873 eth_igb_interrupt_get_status(dev);
2874 eth_igb_interrupt_action(dev, dev->intr_handle);
2878 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2881 struct e1000_hw *hw =
2882 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2883 struct e1000_interrupt *intr =
2884 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2886 igbvf_intr_disable(hw);
2888 /* read-on-clear nic registers here */
2889 eicr = E1000_READ_REG(hw, E1000_EICR);
2892 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2893 intr->flags |= E1000_FLAG_MAILBOX;
2898 void igbvf_mbx_process(struct rte_eth_dev *dev)
2900 struct e1000_hw *hw =
2901 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2902 struct e1000_mbx_info *mbx = &hw->mbx;
2905 /* peek the message first */
2906 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2908 /* PF reset VF event */
2909 if (in_msg == E1000_PF_CONTROL_MSG) {
2910 /* dummy mbx read to ack pf */
2911 if (mbx->ops.read(hw, &in_msg, 1, 0))
2913 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2919 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2921 struct e1000_interrupt *intr =
2922 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2924 if (intr->flags & E1000_FLAG_MAILBOX) {
2925 igbvf_mbx_process(dev);
2926 intr->flags &= ~E1000_FLAG_MAILBOX;
2929 igbvf_intr_enable(dev);
2930 rte_intr_enable(intr_handle);
2936 eth_igbvf_interrupt_handler(void *param)
2938 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2940 eth_igbvf_interrupt_get_status(dev);
2941 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2945 eth_igb_led_on(struct rte_eth_dev *dev)
2947 struct e1000_hw *hw;
2949 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2950 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2954 eth_igb_led_off(struct rte_eth_dev *dev)
2956 struct e1000_hw *hw;
2958 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2959 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2963 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2965 struct e1000_hw *hw;
2970 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971 fc_conf->pause_time = hw->fc.pause_time;
2972 fc_conf->high_water = hw->fc.high_water;
2973 fc_conf->low_water = hw->fc.low_water;
2974 fc_conf->send_xon = hw->fc.send_xon;
2975 fc_conf->autoneg = hw->mac.autoneg;
2978 * Return rx_pause and tx_pause status according to actual setting of
2979 * the TFCE and RFCE bits in the CTRL register.
2981 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2982 if (ctrl & E1000_CTRL_TFCE)
2987 if (ctrl & E1000_CTRL_RFCE)
2992 if (rx_pause && tx_pause)
2993 fc_conf->mode = RTE_FC_FULL;
2995 fc_conf->mode = RTE_FC_RX_PAUSE;
2997 fc_conf->mode = RTE_FC_TX_PAUSE;
2999 fc_conf->mode = RTE_FC_NONE;
3005 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3007 struct e1000_hw *hw;
3009 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3015 uint32_t rx_buf_size;
3016 uint32_t max_high_water;
3019 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3020 if (fc_conf->autoneg != hw->mac.autoneg)
3022 rx_buf_size = igb_get_rx_buffer_size(hw);
3023 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3025 /* At least reserve one Ethernet frame for watermark */
3026 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3027 if ((fc_conf->high_water > max_high_water) ||
3028 (fc_conf->high_water < fc_conf->low_water)) {
3029 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3030 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3034 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3035 hw->fc.pause_time = fc_conf->pause_time;
3036 hw->fc.high_water = fc_conf->high_water;
3037 hw->fc.low_water = fc_conf->low_water;
3038 hw->fc.send_xon = fc_conf->send_xon;
3040 err = e1000_setup_link_generic(hw);
3041 if (err == E1000_SUCCESS) {
3043 /* check if we want to forward MAC frames - driver doesn't have native
3044 * capability to do that, so we'll write the registers ourselves */
3046 rctl = E1000_READ_REG(hw, E1000_RCTL);
3048 /* set or clear MFLCN.PMCF bit depending on configuration */
3049 if (fc_conf->mac_ctrl_frame_fwd != 0)
3050 rctl |= E1000_RCTL_PMCF;
3052 rctl &= ~E1000_RCTL_PMCF;
3054 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3055 E1000_WRITE_FLUSH(hw);
3060 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3064 #define E1000_RAH_POOLSEL_SHIFT (18)
3066 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3067 uint32_t index, uint32_t pool)
3069 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3073 rah = E1000_READ_REG(hw, E1000_RAH(index));
3074 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3075 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3080 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3082 uint8_t addr[ETHER_ADDR_LEN];
3083 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3085 memset(addr, 0, sizeof(addr));
3087 e1000_rar_set(hw, addr, index);
3091 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3092 struct ether_addr *addr)
3094 eth_igb_rar_clear(dev, 0);
3095 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3100 * Virtual Function operations
3103 igbvf_intr_disable(struct e1000_hw *hw)
3105 PMD_INIT_FUNC_TRACE();
3107 /* Clear interrupt mask to stop from interrupts being generated */
3108 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3110 E1000_WRITE_FLUSH(hw);
3114 igbvf_stop_adapter(struct rte_eth_dev *dev)
3118 struct rte_eth_dev_info dev_info;
3119 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121 memset(&dev_info, 0, sizeof(dev_info));
3122 eth_igbvf_infos_get(dev, &dev_info);
3124 /* Clear interrupt mask to stop from interrupts being generated */
3125 igbvf_intr_disable(hw);
3127 /* Clear any pending interrupts, flush previous writes */
3128 E1000_READ_REG(hw, E1000_EICR);
3130 /* Disable the transmit unit. Each queue must be disabled. */
3131 for (i = 0; i < dev_info.max_tx_queues; i++)
3132 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3134 /* Disable the receive unit by stopping each queue */
3135 for (i = 0; i < dev_info.max_rx_queues; i++) {
3136 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3137 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3138 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3139 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3143 /* flush all queues disables */
3144 E1000_WRITE_FLUSH(hw);
3148 static int eth_igbvf_link_update(struct e1000_hw *hw)
3150 struct e1000_mbx_info *mbx = &hw->mbx;
3151 struct e1000_mac_info *mac = &hw->mac;
3152 int ret_val = E1000_SUCCESS;
3154 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3157 * We only want to run this if there has been a rst asserted.
3158 * in this case that could mean a link change, device reset,
3159 * or a virtual function reset
3162 /* If we were hit with a reset or timeout drop the link */
3163 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3164 mac->get_link_status = TRUE;
3166 if (!mac->get_link_status)
3169 /* if link status is down no point in checking to see if pf is up */
3170 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3173 /* if we passed all the tests above then the link is up and we no
3174 * longer need to check for link */
3175 mac->get_link_status = FALSE;
3183 igbvf_dev_configure(struct rte_eth_dev *dev)
3185 struct rte_eth_conf* conf = &dev->data->dev_conf;
3187 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3188 dev->data->port_id);
3191 * VF has no ability to enable/disable HW CRC
3192 * Keep the persistent behavior the same as Host PF
3194 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3195 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
3196 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3197 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
3200 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
3201 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3202 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
3210 igbvf_dev_start(struct rte_eth_dev *dev)
3212 struct e1000_hw *hw =
3213 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214 struct e1000_adapter *adapter =
3215 E1000_DEV_PRIVATE(dev->data->dev_private);
3216 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3217 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3219 uint32_t intr_vector = 0;
3221 PMD_INIT_FUNC_TRACE();
3223 hw->mac.ops.reset_hw(hw);
3224 adapter->stopped = 0;
3227 igbvf_set_vfta_all(dev,1);
3229 eth_igbvf_tx_init(dev);
3231 /* This can fail when allocating mbufs for descriptor rings */
3232 ret = eth_igbvf_rx_init(dev);
3234 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3235 igb_dev_clear_queues(dev);
3239 /* check and configure queue intr-vector mapping */
3240 if (rte_intr_cap_multiple(intr_handle) &&
3241 dev->data->dev_conf.intr_conf.rxq) {
3242 intr_vector = dev->data->nb_rx_queues;
3243 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3248 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3249 intr_handle->intr_vec =
3250 rte_zmalloc("intr_vec",
3251 dev->data->nb_rx_queues * sizeof(int), 0);
3252 if (!intr_handle->intr_vec) {
3253 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3254 " intr_vec", dev->data->nb_rx_queues);
3259 eth_igbvf_configure_msix_intr(dev);
3261 /* enable uio/vfio intr/eventfd mapping */
3262 rte_intr_enable(intr_handle);
3264 /* resume enabled intr since hw reset */
3265 igbvf_intr_enable(dev);
3271 igbvf_dev_stop(struct rte_eth_dev *dev)
3273 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3274 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3276 PMD_INIT_FUNC_TRACE();
3278 igbvf_stop_adapter(dev);
3281 * Clear what we set, but we still keep shadow_vfta to
3282 * restore after device starts
3284 igbvf_set_vfta_all(dev,0);
3286 igb_dev_clear_queues(dev);
3288 /* disable intr eventfd mapping */
3289 rte_intr_disable(intr_handle);
3291 /* Clean datapath event and queue/vec mapping */
3292 rte_intr_efd_disable(intr_handle);
3293 if (intr_handle->intr_vec) {
3294 rte_free(intr_handle->intr_vec);
3295 intr_handle->intr_vec = NULL;
3300 igbvf_dev_close(struct rte_eth_dev *dev)
3302 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3303 struct e1000_adapter *adapter =
3304 E1000_DEV_PRIVATE(dev->data->dev_private);
3305 struct ether_addr addr;
3307 PMD_INIT_FUNC_TRACE();
3311 igbvf_dev_stop(dev);
3312 adapter->stopped = 1;
3313 igb_dev_free_queues(dev);
3316 * reprogram the RAR with a zero mac address,
3317 * to ensure that the VF traffic goes to the PF
3318 * after stop, close and detach of the VF.
3321 memset(&addr, 0, sizeof(addr));
3322 igbvf_default_mac_addr_set(dev, &addr);
3326 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3328 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3330 /* Set both unicast and multicast promisc */
3331 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3335 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3337 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3339 /* If in allmulticast mode leave multicast promisc */
3340 if (dev->data->all_multicast == 1)
3341 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3343 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3347 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3349 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3351 /* In promiscuous mode multicast promisc already set */
3352 if (dev->data->promiscuous == 0)
3353 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3357 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3359 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361 /* In promiscuous mode leave multicast promisc enabled */
3362 if (dev->data->promiscuous == 0)
3363 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3366 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3368 struct e1000_mbx_info *mbx = &hw->mbx;
3372 /* After set vlan, vlan strip will also be enabled in igb driver*/
3373 msgbuf[0] = E1000_VF_SET_VLAN;
3375 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3377 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3379 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3383 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3387 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3388 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3395 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3397 struct e1000_hw *hw =
3398 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399 struct e1000_vfta * shadow_vfta =
3400 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3401 int i = 0, j = 0, vfta = 0, mask = 1;
3403 for (i = 0; i < IGB_VFTA_SIZE; i++){
3404 vfta = shadow_vfta->vfta[i];
3407 for (j = 0; j < 32; j++){
3410 (uint16_t)((i<<5)+j), on);
3419 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3421 struct e1000_hw *hw =
3422 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3423 struct e1000_vfta * shadow_vfta =
3424 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3425 uint32_t vid_idx = 0;
3426 uint32_t vid_bit = 0;
3429 PMD_INIT_FUNC_TRACE();
3431 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3432 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3434 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3437 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3438 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3440 /*Save what we set and retore it after device reset*/
3442 shadow_vfta->vfta[vid_idx] |= vid_bit;
3444 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3450 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3452 struct e1000_hw *hw =
3453 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3455 /* index is not used by rar_set() */
3456 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3462 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3463 struct rte_eth_rss_reta_entry64 *reta_conf,
3468 uint16_t idx, shift;
3469 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3471 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3472 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3473 "(%d) doesn't match the number hardware can supported "
3474 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3478 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3479 idx = i / RTE_RETA_GROUP_SIZE;
3480 shift = i % RTE_RETA_GROUP_SIZE;
3481 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3485 if (mask == IGB_4_BIT_MASK)
3488 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3489 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3490 if (mask & (0x1 << j))
3491 reta |= reta_conf[idx].reta[shift + j] <<
3494 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3496 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3503 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3504 struct rte_eth_rss_reta_entry64 *reta_conf,
3509 uint16_t idx, shift;
3510 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3513 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3514 "(%d) doesn't match the number hardware can supported "
3515 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3519 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3520 idx = i / RTE_RETA_GROUP_SIZE;
3521 shift = i % RTE_RETA_GROUP_SIZE;
3522 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3526 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3527 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3528 if (mask & (0x1 << j))
3529 reta_conf[idx].reta[shift + j] =
3530 ((reta >> (CHAR_BIT * j)) &
3539 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3540 struct rte_eth_syn_filter *filter,
3543 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3544 struct e1000_filter_info *filter_info =
3545 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3546 uint32_t synqf, rfctl;
3548 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3551 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3554 if (synqf & E1000_SYN_FILTER_ENABLE)
3557 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3558 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3560 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3561 if (filter->hig_pri)
3562 rfctl |= E1000_RFCTL_SYNQFP;
3564 rfctl &= ~E1000_RFCTL_SYNQFP;
3566 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3568 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3573 filter_info->syn_info = synqf;
3574 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3575 E1000_WRITE_FLUSH(hw);
3580 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3581 struct rte_eth_syn_filter *filter)
3583 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3584 uint32_t synqf, rfctl;
3586 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3587 if (synqf & E1000_SYN_FILTER_ENABLE) {
3588 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3589 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3590 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3591 E1000_SYN_FILTER_QUEUE_SHIFT);
3599 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3600 enum rte_filter_op filter_op,
3603 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3606 MAC_TYPE_FILTER_SUP(hw->mac.type);
3608 if (filter_op == RTE_ETH_FILTER_NOP)
3612 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3617 switch (filter_op) {
3618 case RTE_ETH_FILTER_ADD:
3619 ret = eth_igb_syn_filter_set(dev,
3620 (struct rte_eth_syn_filter *)arg,
3623 case RTE_ETH_FILTER_DELETE:
3624 ret = eth_igb_syn_filter_set(dev,
3625 (struct rte_eth_syn_filter *)arg,
3628 case RTE_ETH_FILTER_GET:
3629 ret = eth_igb_syn_filter_get(dev,
3630 (struct rte_eth_syn_filter *)arg);
3633 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3641 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3643 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3644 struct e1000_2tuple_filter_info *filter_info)
3646 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3648 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3649 return -EINVAL; /* filter index is out of range. */
3650 if (filter->tcp_flags > TCP_FLAG_ALL)
3651 return -EINVAL; /* flags is invalid. */
3653 switch (filter->dst_port_mask) {
3655 filter_info->dst_port_mask = 0;
3656 filter_info->dst_port = filter->dst_port;
3659 filter_info->dst_port_mask = 1;
3662 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3666 switch (filter->proto_mask) {
3668 filter_info->proto_mask = 0;
3669 filter_info->proto = filter->proto;
3672 filter_info->proto_mask = 1;
3675 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3679 filter_info->priority = (uint8_t)filter->priority;
3680 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3681 filter_info->tcp_flags = filter->tcp_flags;
3683 filter_info->tcp_flags = 0;
3688 static inline struct e1000_2tuple_filter *
3689 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3690 struct e1000_2tuple_filter_info *key)
3692 struct e1000_2tuple_filter *it;
3694 TAILQ_FOREACH(it, filter_list, entries) {
3695 if (memcmp(key, &it->filter_info,
3696 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3703 /* inject a igb 2tuple filter to HW */
3705 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3706 struct e1000_2tuple_filter *filter)
3708 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3710 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3714 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3715 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3716 imir |= E1000_IMIR_PORT_BP;
3718 imir &= ~E1000_IMIR_PORT_BP;
3720 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3722 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3723 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3724 ttqf |= (uint32_t)(filter->filter_info.proto &
3725 E1000_TTQF_PROTOCOL_MASK);
3726 if (filter->filter_info.proto_mask == 0)
3727 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3729 /* tcp flags bits setting. */
3730 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3731 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3732 imir_ext |= E1000_IMIREXT_CTRL_URG;
3733 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3734 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3735 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3736 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3737 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3738 imir_ext |= E1000_IMIREXT_CTRL_RST;
3739 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3740 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3741 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3742 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3744 imir_ext |= E1000_IMIREXT_CTRL_BP;
3746 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3747 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3748 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3752 * igb_add_2tuple_filter - add a 2tuple filter
3755 * dev: Pointer to struct rte_eth_dev.
3756 * ntuple_filter: ponter to the filter that will be added.
3759 * - On success, zero.
3760 * - On failure, a negative value.
3763 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3764 struct rte_eth_ntuple_filter *ntuple_filter)
3766 struct e1000_filter_info *filter_info =
3767 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3768 struct e1000_2tuple_filter *filter;
3771 filter = rte_zmalloc("e1000_2tuple_filter",
3772 sizeof(struct e1000_2tuple_filter), 0);
3776 ret = ntuple_filter_to_2tuple(ntuple_filter,
3777 &filter->filter_info);
3782 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3783 &filter->filter_info) != NULL) {
3784 PMD_DRV_LOG(ERR, "filter exists.");
3788 filter->queue = ntuple_filter->queue;
3791 * look for an unused 2tuple filter index,
3792 * and insert the filter to list.
3794 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3795 if (!(filter_info->twotuple_mask & (1 << i))) {
3796 filter_info->twotuple_mask |= 1 << i;
3798 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3804 if (i >= E1000_MAX_TTQF_FILTERS) {
3805 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3810 igb_inject_2uple_filter(dev, filter);
3815 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3816 struct e1000_2tuple_filter *filter)
3818 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3819 struct e1000_filter_info *filter_info =
3820 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3822 filter_info->twotuple_mask &= ~(1 << filter->index);
3823 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3826 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3827 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3828 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3833 * igb_remove_2tuple_filter - remove a 2tuple filter
3836 * dev: Pointer to struct rte_eth_dev.
3837 * ntuple_filter: ponter to the filter that will be removed.
3840 * - On success, zero.
3841 * - On failure, a negative value.
3844 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3845 struct rte_eth_ntuple_filter *ntuple_filter)
3847 struct e1000_filter_info *filter_info =
3848 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3849 struct e1000_2tuple_filter_info filter_2tuple;
3850 struct e1000_2tuple_filter *filter;
3853 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3854 ret = ntuple_filter_to_2tuple(ntuple_filter,
3859 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3861 if (filter == NULL) {
3862 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3866 igb_delete_2tuple_filter(dev, filter);
3871 /* inject a igb flex filter to HW */
3873 igb_inject_flex_filter(struct rte_eth_dev *dev,
3874 struct e1000_flex_filter *filter)
3876 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3877 uint32_t wufc, queueing;
3881 wufc = E1000_READ_REG(hw, E1000_WUFC);
3882 if (filter->index < E1000_MAX_FHFT)
3883 reg_off = E1000_FHFT(filter->index);
3885 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3887 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3888 (E1000_WUFC_FLX0 << filter->index));
3889 queueing = filter->filter_info.len |
3890 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3891 (filter->filter_info.priority <<
3892 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3893 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3896 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3897 E1000_WRITE_REG(hw, reg_off,
3898 filter->filter_info.dwords[j]);
3899 reg_off += sizeof(uint32_t);
3900 E1000_WRITE_REG(hw, reg_off,
3901 filter->filter_info.dwords[++j]);
3902 reg_off += sizeof(uint32_t);
3903 E1000_WRITE_REG(hw, reg_off,
3904 (uint32_t)filter->filter_info.mask[i]);
3905 reg_off += sizeof(uint32_t) * 2;
3910 static inline struct e1000_flex_filter *
3911 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3912 struct e1000_flex_filter_info *key)
3914 struct e1000_flex_filter *it;
3916 TAILQ_FOREACH(it, filter_list, entries) {
3917 if (memcmp(key, &it->filter_info,
3918 sizeof(struct e1000_flex_filter_info)) == 0)
3925 /* remove a flex byte filter
3927 * dev: Pointer to struct rte_eth_dev.
3928 * filter: the pointer of the filter will be removed.
3931 igb_remove_flex_filter(struct rte_eth_dev *dev,
3932 struct e1000_flex_filter *filter)
3934 struct e1000_filter_info *filter_info =
3935 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3936 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3940 wufc = E1000_READ_REG(hw, E1000_WUFC);
3941 if (filter->index < E1000_MAX_FHFT)
3942 reg_off = E1000_FHFT(filter->index);
3944 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3946 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3947 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3949 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3950 (~(E1000_WUFC_FLX0 << filter->index)));
3952 filter_info->flex_mask &= ~(1 << filter->index);
3953 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3958 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3959 struct rte_eth_flex_filter *filter,
3962 struct e1000_filter_info *filter_info =
3963 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3964 struct e1000_flex_filter *flex_filter, *it;
3968 flex_filter = rte_zmalloc("e1000_flex_filter",
3969 sizeof(struct e1000_flex_filter), 0);
3970 if (flex_filter == NULL)
3973 flex_filter->filter_info.len = filter->len;
3974 flex_filter->filter_info.priority = filter->priority;
3975 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3976 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3978 /* reverse bits in flex filter's mask*/
3979 for (shift = 0; shift < CHAR_BIT; shift++) {
3980 if (filter->mask[i] & (0x01 << shift))
3981 mask |= (0x80 >> shift);
3983 flex_filter->filter_info.mask[i] = mask;
3986 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3987 &flex_filter->filter_info);
3988 if (it == NULL && !add) {
3989 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3990 rte_free(flex_filter);
3993 if (it != NULL && add) {
3994 PMD_DRV_LOG(ERR, "filter exists.");
3995 rte_free(flex_filter);
4000 flex_filter->queue = filter->queue;
4002 * look for an unused flex filter index
4003 * and insert the filter into the list.
4005 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4006 if (!(filter_info->flex_mask & (1 << i))) {
4007 filter_info->flex_mask |= 1 << i;
4008 flex_filter->index = i;
4009 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4015 if (i >= E1000_MAX_FLEX_FILTERS) {
4016 PMD_DRV_LOG(ERR, "flex filters are full.");
4017 rte_free(flex_filter);
4021 igb_inject_flex_filter(dev, flex_filter);
4024 igb_remove_flex_filter(dev, it);
4025 rte_free(flex_filter);
4032 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4033 struct rte_eth_flex_filter *filter)
4035 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4036 struct e1000_filter_info *filter_info =
4037 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4038 struct e1000_flex_filter flex_filter, *it;
4039 uint32_t wufc, queueing, wufc_en = 0;
4041 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4042 flex_filter.filter_info.len = filter->len;
4043 flex_filter.filter_info.priority = filter->priority;
4044 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4045 memcpy(flex_filter.filter_info.mask, filter->mask,
4046 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4048 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4049 &flex_filter.filter_info);
4051 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4055 wufc = E1000_READ_REG(hw, E1000_WUFC);
4056 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4058 if ((wufc & wufc_en) == wufc_en) {
4059 uint32_t reg_off = 0;
4060 if (it->index < E1000_MAX_FHFT)
4061 reg_off = E1000_FHFT(it->index);
4063 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4065 queueing = E1000_READ_REG(hw,
4066 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4067 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4068 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4069 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4070 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4071 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4078 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4079 enum rte_filter_op filter_op,
4082 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4083 struct rte_eth_flex_filter *filter;
4086 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4088 if (filter_op == RTE_ETH_FILTER_NOP)
4092 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4097 filter = (struct rte_eth_flex_filter *)arg;
4098 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4099 || filter->len % sizeof(uint64_t) != 0) {
4100 PMD_DRV_LOG(ERR, "filter's length is out of range");
4103 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4104 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4108 switch (filter_op) {
4109 case RTE_ETH_FILTER_ADD:
4110 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4112 case RTE_ETH_FILTER_DELETE:
4113 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4115 case RTE_ETH_FILTER_GET:
4116 ret = eth_igb_get_flex_filter(dev, filter);
4119 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4127 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4129 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4130 struct e1000_5tuple_filter_info *filter_info)
4132 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4134 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4135 return -EINVAL; /* filter index is out of range. */
4136 if (filter->tcp_flags > TCP_FLAG_ALL)
4137 return -EINVAL; /* flags is invalid. */
4139 switch (filter->dst_ip_mask) {
4141 filter_info->dst_ip_mask = 0;
4142 filter_info->dst_ip = filter->dst_ip;
4145 filter_info->dst_ip_mask = 1;
4148 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4152 switch (filter->src_ip_mask) {
4154 filter_info->src_ip_mask = 0;
4155 filter_info->src_ip = filter->src_ip;
4158 filter_info->src_ip_mask = 1;
4161 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4165 switch (filter->dst_port_mask) {
4167 filter_info->dst_port_mask = 0;
4168 filter_info->dst_port = filter->dst_port;
4171 filter_info->dst_port_mask = 1;
4174 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4178 switch (filter->src_port_mask) {
4180 filter_info->src_port_mask = 0;
4181 filter_info->src_port = filter->src_port;
4184 filter_info->src_port_mask = 1;
4187 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4191 switch (filter->proto_mask) {
4193 filter_info->proto_mask = 0;
4194 filter_info->proto = filter->proto;
4197 filter_info->proto_mask = 1;
4200 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4204 filter_info->priority = (uint8_t)filter->priority;
4205 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4206 filter_info->tcp_flags = filter->tcp_flags;
4208 filter_info->tcp_flags = 0;
4213 static inline struct e1000_5tuple_filter *
4214 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4215 struct e1000_5tuple_filter_info *key)
4217 struct e1000_5tuple_filter *it;
4219 TAILQ_FOREACH(it, filter_list, entries) {
4220 if (memcmp(key, &it->filter_info,
4221 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4228 /* inject a igb 5-tuple filter to HW */
4230 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4231 struct e1000_5tuple_filter *filter)
4233 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4234 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4235 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4239 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4240 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4241 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4242 if (filter->filter_info.dst_ip_mask == 0)
4243 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4244 if (filter->filter_info.src_port_mask == 0)
4245 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4246 if (filter->filter_info.proto_mask == 0)
4247 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4248 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4249 E1000_FTQF_QUEUE_MASK;
4250 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4251 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4252 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4253 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4255 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4256 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4258 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4259 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4260 imir |= E1000_IMIR_PORT_BP;
4262 imir &= ~E1000_IMIR_PORT_BP;
4263 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4265 /* tcp flags bits setting. */
4266 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4267 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4268 imir_ext |= E1000_IMIREXT_CTRL_URG;
4269 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4270 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4271 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4272 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4273 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4274 imir_ext |= E1000_IMIREXT_CTRL_RST;
4275 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4276 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4277 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4278 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4280 imir_ext |= E1000_IMIREXT_CTRL_BP;
4282 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4283 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4287 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4290 * dev: Pointer to struct rte_eth_dev.
4291 * ntuple_filter: ponter to the filter that will be added.
4294 * - On success, zero.
4295 * - On failure, a negative value.
4298 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4299 struct rte_eth_ntuple_filter *ntuple_filter)
4301 struct e1000_filter_info *filter_info =
4302 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4303 struct e1000_5tuple_filter *filter;
4307 filter = rte_zmalloc("e1000_5tuple_filter",
4308 sizeof(struct e1000_5tuple_filter), 0);
4312 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4313 &filter->filter_info);
4319 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4320 &filter->filter_info) != NULL) {
4321 PMD_DRV_LOG(ERR, "filter exists.");
4325 filter->queue = ntuple_filter->queue;
4328 * look for an unused 5tuple filter index,
4329 * and insert the filter to list.
4331 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4332 if (!(filter_info->fivetuple_mask & (1 << i))) {
4333 filter_info->fivetuple_mask |= 1 << i;
4335 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4341 if (i >= E1000_MAX_FTQF_FILTERS) {
4342 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4347 igb_inject_5tuple_filter_82576(dev, filter);
4352 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4353 struct e1000_5tuple_filter *filter)
4355 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4356 struct e1000_filter_info *filter_info =
4357 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4359 filter_info->fivetuple_mask &= ~(1 << filter->index);
4360 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4363 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4364 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4365 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4366 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4367 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4368 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4369 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4374 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4377 * dev: Pointer to struct rte_eth_dev.
4378 * ntuple_filter: ponter to the filter that will be removed.
4381 * - On success, zero.
4382 * - On failure, a negative value.
4385 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4386 struct rte_eth_ntuple_filter *ntuple_filter)
4388 struct e1000_filter_info *filter_info =
4389 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4390 struct e1000_5tuple_filter_info filter_5tuple;
4391 struct e1000_5tuple_filter *filter;
4394 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4395 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4400 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4402 if (filter == NULL) {
4403 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4407 igb_delete_5tuple_filter_82576(dev, filter);
4413 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4416 struct e1000_hw *hw;
4417 struct rte_eth_dev_info dev_info;
4418 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4421 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4423 #ifdef RTE_LIBRTE_82571_SUPPORT
4424 /* XXX: not bigger than max_rx_pktlen */
4425 if (hw->mac.type == e1000_82571)
4428 eth_igb_infos_get(dev, &dev_info);
4430 /* check that mtu is within the allowed range */
4431 if ((mtu < ETHER_MIN_MTU) ||
4432 (frame_size > dev_info.max_rx_pktlen))
4435 /* refuse mtu that requires the support of scattered packets when this
4436 * feature has not been enabled before. */
4437 if (!dev->data->scattered_rx &&
4438 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4441 rctl = E1000_READ_REG(hw, E1000_RCTL);
4443 /* switch to jumbo mode if needed */
4444 if (frame_size > ETHER_MAX_LEN) {
4445 dev->data->dev_conf.rxmode.offloads |=
4446 DEV_RX_OFFLOAD_JUMBO_FRAME;
4447 rctl |= E1000_RCTL_LPE;
4449 dev->data->dev_conf.rxmode.offloads &=
4450 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4451 rctl &= ~E1000_RCTL_LPE;
4453 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4455 /* update max frame size */
4456 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4458 E1000_WRITE_REG(hw, E1000_RLPML,
4459 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4465 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4468 * dev: Pointer to struct rte_eth_dev.
4469 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4470 * add: if true, add filter, if false, remove filter
4473 * - On success, zero.
4474 * - On failure, a negative value.
4477 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4478 struct rte_eth_ntuple_filter *ntuple_filter,
4481 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484 switch (ntuple_filter->flags) {
4485 case RTE_5TUPLE_FLAGS:
4486 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4487 if (hw->mac.type != e1000_82576)
4490 ret = igb_add_5tuple_filter_82576(dev,
4493 ret = igb_remove_5tuple_filter_82576(dev,
4496 case RTE_2TUPLE_FLAGS:
4497 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4498 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4499 hw->mac.type != e1000_i210 &&
4500 hw->mac.type != e1000_i211)
4503 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4505 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4516 * igb_get_ntuple_filter - get a ntuple filter
4519 * dev: Pointer to struct rte_eth_dev.
4520 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4523 * - On success, zero.
4524 * - On failure, a negative value.
4527 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4528 struct rte_eth_ntuple_filter *ntuple_filter)
4530 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4531 struct e1000_filter_info *filter_info =
4532 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4533 struct e1000_5tuple_filter_info filter_5tuple;
4534 struct e1000_2tuple_filter_info filter_2tuple;
4535 struct e1000_5tuple_filter *p_5tuple_filter;
4536 struct e1000_2tuple_filter *p_2tuple_filter;
4539 switch (ntuple_filter->flags) {
4540 case RTE_5TUPLE_FLAGS:
4541 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4542 if (hw->mac.type != e1000_82576)
4544 memset(&filter_5tuple,
4546 sizeof(struct e1000_5tuple_filter_info));
4547 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4551 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4552 &filter_info->fivetuple_list,
4554 if (p_5tuple_filter == NULL) {
4555 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4558 ntuple_filter->queue = p_5tuple_filter->queue;
4560 case RTE_2TUPLE_FLAGS:
4561 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4562 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4564 memset(&filter_2tuple,
4566 sizeof(struct e1000_2tuple_filter_info));
4567 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4570 p_2tuple_filter = igb_2tuple_filter_lookup(
4571 &filter_info->twotuple_list,
4573 if (p_2tuple_filter == NULL) {
4574 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4577 ntuple_filter->queue = p_2tuple_filter->queue;
4588 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4589 * @dev: pointer to rte_eth_dev structure
4590 * @filter_op:operation will be taken.
4591 * @arg: a pointer to specific structure corresponding to the filter_op
4594 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4595 enum rte_filter_op filter_op,
4598 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4601 MAC_TYPE_FILTER_SUP(hw->mac.type);
4603 if (filter_op == RTE_ETH_FILTER_NOP)
4607 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4612 switch (filter_op) {
4613 case RTE_ETH_FILTER_ADD:
4614 ret = igb_add_del_ntuple_filter(dev,
4615 (struct rte_eth_ntuple_filter *)arg,
4618 case RTE_ETH_FILTER_DELETE:
4619 ret = igb_add_del_ntuple_filter(dev,
4620 (struct rte_eth_ntuple_filter *)arg,
4623 case RTE_ETH_FILTER_GET:
4624 ret = igb_get_ntuple_filter(dev,
4625 (struct rte_eth_ntuple_filter *)arg);
4628 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4636 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4641 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4642 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4643 (filter_info->ethertype_mask & (1 << i)))
4650 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4651 uint16_t ethertype, uint32_t etqf)
4655 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4656 if (!(filter_info->ethertype_mask & (1 << i))) {
4657 filter_info->ethertype_mask |= 1 << i;
4658 filter_info->ethertype_filters[i].ethertype = ethertype;
4659 filter_info->ethertype_filters[i].etqf = etqf;
4667 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4670 if (idx >= E1000_MAX_ETQF_FILTERS)
4672 filter_info->ethertype_mask &= ~(1 << idx);
4673 filter_info->ethertype_filters[idx].ethertype = 0;
4674 filter_info->ethertype_filters[idx].etqf = 0;
4680 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4681 struct rte_eth_ethertype_filter *filter,
4684 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685 struct e1000_filter_info *filter_info =
4686 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4690 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4691 filter->ether_type == ETHER_TYPE_IPv6) {
4692 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4693 " ethertype filter.", filter->ether_type);
4697 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4698 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4701 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4702 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4706 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4707 if (ret >= 0 && add) {
4708 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4709 filter->ether_type);
4712 if (ret < 0 && !add) {
4713 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4714 filter->ether_type);
4719 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4720 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4721 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4722 ret = igb_ethertype_filter_insert(filter_info,
4723 filter->ether_type, etqf);
4725 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4729 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4733 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4734 E1000_WRITE_FLUSH(hw);
4740 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4741 struct rte_eth_ethertype_filter *filter)
4743 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744 struct e1000_filter_info *filter_info =
4745 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4749 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4751 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4752 filter->ether_type);
4756 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4757 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4758 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4760 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4761 E1000_ETQF_QUEUE_SHIFT;
4769 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4770 * @dev: pointer to rte_eth_dev structure
4771 * @filter_op:operation will be taken.
4772 * @arg: a pointer to specific structure corresponding to the filter_op
4775 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4776 enum rte_filter_op filter_op,
4779 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4782 MAC_TYPE_FILTER_SUP(hw->mac.type);
4784 if (filter_op == RTE_ETH_FILTER_NOP)
4788 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4793 switch (filter_op) {
4794 case RTE_ETH_FILTER_ADD:
4795 ret = igb_add_del_ethertype_filter(dev,
4796 (struct rte_eth_ethertype_filter *)arg,
4799 case RTE_ETH_FILTER_DELETE:
4800 ret = igb_add_del_ethertype_filter(dev,
4801 (struct rte_eth_ethertype_filter *)arg,
4804 case RTE_ETH_FILTER_GET:
4805 ret = igb_get_ethertype_filter(dev,
4806 (struct rte_eth_ethertype_filter *)arg);
4809 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4817 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4818 enum rte_filter_type filter_type,
4819 enum rte_filter_op filter_op,
4824 switch (filter_type) {
4825 case RTE_ETH_FILTER_NTUPLE:
4826 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4828 case RTE_ETH_FILTER_ETHERTYPE:
4829 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4831 case RTE_ETH_FILTER_SYN:
4832 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4834 case RTE_ETH_FILTER_FLEXIBLE:
4835 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4837 case RTE_ETH_FILTER_GENERIC:
4838 if (filter_op != RTE_ETH_FILTER_GET)
4840 *(const void **)arg = &igb_flow_ops;
4843 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4852 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4853 struct ether_addr *mc_addr_set,
4854 uint32_t nb_mc_addr)
4856 struct e1000_hw *hw;
4858 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4859 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4864 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4866 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4867 uint64_t systime_cycles;
4869 switch (hw->mac.type) {
4873 * Need to read System Time Residue Register to be able
4874 * to read the other two registers.
4876 E1000_READ_REG(hw, E1000_SYSTIMR);
4877 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4878 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4879 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4886 * Need to read System Time Residue Register to be able
4887 * to read the other two registers.
4889 E1000_READ_REG(hw, E1000_SYSTIMR);
4890 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4891 /* Only the 8 LSB are valid. */
4892 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4896 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4897 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4902 return systime_cycles;
4906 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4908 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4909 uint64_t rx_tstamp_cycles;
4911 switch (hw->mac.type) {
4914 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4915 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4916 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4922 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4923 /* Only the 8 LSB are valid. */
4924 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4928 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4929 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4934 return rx_tstamp_cycles;
4938 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4940 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4941 uint64_t tx_tstamp_cycles;
4943 switch (hw->mac.type) {
4946 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4947 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4948 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4954 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4955 /* Only the 8 LSB are valid. */
4956 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4960 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4961 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4966 return tx_tstamp_cycles;
4970 igb_start_timecounters(struct rte_eth_dev *dev)
4972 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4973 struct e1000_adapter *adapter =
4974 (struct e1000_adapter *)dev->data->dev_private;
4975 uint32_t incval = 1;
4977 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4979 switch (hw->mac.type) {
4983 /* 32 LSB bits + 8 MSB bits = 40 bits */
4984 mask = (1ULL << 40) - 1;
4989 * Start incrementing the register
4990 * used to timestamp PTP packets.
4992 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4995 incval = E1000_INCVALUE_82576;
4996 shift = IGB_82576_TSYNC_SHIFT;
4997 E1000_WRITE_REG(hw, E1000_TIMINCA,
4998 E1000_INCPERIOD_82576 | incval);
5005 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5006 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5007 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5009 adapter->systime_tc.cc_mask = mask;
5010 adapter->systime_tc.cc_shift = shift;
5011 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5013 adapter->rx_tstamp_tc.cc_mask = mask;
5014 adapter->rx_tstamp_tc.cc_shift = shift;
5015 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5017 adapter->tx_tstamp_tc.cc_mask = mask;
5018 adapter->tx_tstamp_tc.cc_shift = shift;
5019 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5023 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5025 struct e1000_adapter *adapter =
5026 (struct e1000_adapter *)dev->data->dev_private;
5028 adapter->systime_tc.nsec += delta;
5029 adapter->rx_tstamp_tc.nsec += delta;
5030 adapter->tx_tstamp_tc.nsec += delta;
5036 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5039 struct e1000_adapter *adapter =
5040 (struct e1000_adapter *)dev->data->dev_private;
5042 ns = rte_timespec_to_ns(ts);
5044 /* Set the timecounters to a new value. */
5045 adapter->systime_tc.nsec = ns;
5046 adapter->rx_tstamp_tc.nsec = ns;
5047 adapter->tx_tstamp_tc.nsec = ns;
5053 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5055 uint64_t ns, systime_cycles;
5056 struct e1000_adapter *adapter =
5057 (struct e1000_adapter *)dev->data->dev_private;
5059 systime_cycles = igb_read_systime_cyclecounter(dev);
5060 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5061 *ts = rte_ns_to_timespec(ns);
5067 igb_timesync_enable(struct rte_eth_dev *dev)
5069 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073 /* Stop the timesync system time. */
5074 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5075 /* Reset the timesync system time value. */
5076 switch (hw->mac.type) {
5082 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5085 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5086 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5089 /* Not supported. */
5093 /* Enable system time for it isn't on by default. */
5094 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5095 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5096 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5098 igb_start_timecounters(dev);
5100 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5101 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5103 E1000_ETQF_FILTER_ENABLE |
5106 /* Enable timestamping of received PTP packets. */
5107 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5108 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5109 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5111 /* Enable Timestamping of transmitted PTP packets. */
5112 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5113 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5114 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5120 igb_timesync_disable(struct rte_eth_dev *dev)
5122 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5125 /* Disable timestamping of transmitted PTP packets. */
5126 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5127 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5128 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5130 /* Disable timestamping of received PTP packets. */
5131 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5132 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5133 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5135 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5136 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5138 /* Stop incrementating the System Time registers. */
5139 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5145 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5146 struct timespec *timestamp,
5147 uint32_t flags __rte_unused)
5149 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5150 struct e1000_adapter *adapter =
5151 (struct e1000_adapter *)dev->data->dev_private;
5152 uint32_t tsync_rxctl;
5153 uint64_t rx_tstamp_cycles;
5156 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5157 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5160 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5161 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5162 *timestamp = rte_ns_to_timespec(ns);
5168 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5169 struct timespec *timestamp)
5171 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5172 struct e1000_adapter *adapter =
5173 (struct e1000_adapter *)dev->data->dev_private;
5174 uint32_t tsync_txctl;
5175 uint64_t tx_tstamp_cycles;
5178 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5179 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5182 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5183 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5184 *timestamp = rte_ns_to_timespec(ns);
5190 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5194 const struct reg_info *reg_group;
5196 while ((reg_group = igb_regs[g_ind++]))
5197 count += igb_reg_group_count(reg_group);
5203 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5207 const struct reg_info *reg_group;
5209 while ((reg_group = igbvf_regs[g_ind++]))
5210 count += igb_reg_group_count(reg_group);
5216 eth_igb_get_regs(struct rte_eth_dev *dev,
5217 struct rte_dev_reg_info *regs)
5219 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5220 uint32_t *data = regs->data;
5223 const struct reg_info *reg_group;
5226 regs->length = eth_igb_get_reg_length(dev);
5227 regs->width = sizeof(uint32_t);
5231 /* Support only full register dump */
5232 if ((regs->length == 0) ||
5233 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5234 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5236 while ((reg_group = igb_regs[g_ind++]))
5237 count += igb_read_regs_group(dev, &data[count],
5246 igbvf_get_regs(struct rte_eth_dev *dev,
5247 struct rte_dev_reg_info *regs)
5249 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5250 uint32_t *data = regs->data;
5253 const struct reg_info *reg_group;
5256 regs->length = igbvf_get_reg_length(dev);
5257 regs->width = sizeof(uint32_t);
5261 /* Support only full register dump */
5262 if ((regs->length == 0) ||
5263 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5264 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5266 while ((reg_group = igbvf_regs[g_ind++]))
5267 count += igb_read_regs_group(dev, &data[count],
5276 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5278 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5280 /* Return unit is byte count */
5281 return hw->nvm.word_size * 2;
5285 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5286 struct rte_dev_eeprom_info *in_eeprom)
5288 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5289 struct e1000_nvm_info *nvm = &hw->nvm;
5290 uint16_t *data = in_eeprom->data;
5293 first = in_eeprom->offset >> 1;
5294 length = in_eeprom->length >> 1;
5295 if ((first >= hw->nvm.word_size) ||
5296 ((first + length) >= hw->nvm.word_size))
5299 in_eeprom->magic = hw->vendor_id |
5300 ((uint32_t)hw->device_id << 16);
5302 if ((nvm->ops.read) == NULL)
5305 return nvm->ops.read(hw, first, length, data);
5309 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5310 struct rte_dev_eeprom_info *in_eeprom)
5312 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5313 struct e1000_nvm_info *nvm = &hw->nvm;
5314 uint16_t *data = in_eeprom->data;
5317 first = in_eeprom->offset >> 1;
5318 length = in_eeprom->length >> 1;
5319 if ((first >= hw->nvm.word_size) ||
5320 ((first + length) >= hw->nvm.word_size))
5323 in_eeprom->magic = (uint32_t)hw->vendor_id |
5324 ((uint32_t)hw->device_id << 16);
5326 if ((nvm->ops.write) == NULL)
5328 return nvm->ops.write(hw, first, length, data);
5332 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5334 struct e1000_hw *hw =
5335 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5336 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5337 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5338 uint32_t vec = E1000_MISC_VEC_ID;
5340 if (rte_intr_allow_others(intr_handle))
5341 vec = E1000_RX_VEC_START;
5343 uint32_t mask = 1 << (queue_id + vec);
5345 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5346 E1000_WRITE_FLUSH(hw);
5352 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5354 struct e1000_hw *hw =
5355 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5356 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5357 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5358 uint32_t vec = E1000_MISC_VEC_ID;
5360 if (rte_intr_allow_others(intr_handle))
5361 vec = E1000_RX_VEC_START;
5363 uint32_t mask = 1 << (queue_id + vec);
5366 regval = E1000_READ_REG(hw, E1000_EIMS);
5367 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5368 E1000_WRITE_FLUSH(hw);
5370 rte_intr_enable(intr_handle);
5376 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5377 uint8_t index, uint8_t offset)
5379 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5382 val &= ~((uint32_t)0xFF << offset);
5384 /* write vector and valid bit */
5385 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5387 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5391 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5392 uint8_t queue, uint8_t msix_vector)
5396 if (hw->mac.type == e1000_82575) {
5398 tmp = E1000_EICR_RX_QUEUE0 << queue;
5399 else if (direction == 1)
5400 tmp = E1000_EICR_TX_QUEUE0 << queue;
5401 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5402 } else if (hw->mac.type == e1000_82576) {
5403 if ((direction == 0) || (direction == 1))
5404 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5405 ((queue & 0x8) << 1) +
5407 } else if ((hw->mac.type == e1000_82580) ||
5408 (hw->mac.type == e1000_i350) ||
5409 (hw->mac.type == e1000_i354) ||
5410 (hw->mac.type == e1000_i210) ||
5411 (hw->mac.type == e1000_i211)) {
5412 if ((direction == 0) || (direction == 1))
5413 eth_igb_write_ivar(hw, msix_vector,
5415 ((queue & 0x1) << 4) +
5420 /* Sets up the hardware to generate MSI-X interrupts properly
5422 * board private structure
5425 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5428 uint32_t tmpval, regval, intr_mask;
5429 struct e1000_hw *hw =
5430 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5431 uint32_t vec = E1000_MISC_VEC_ID;
5432 uint32_t base = E1000_MISC_VEC_ID;
5433 uint32_t misc_shift = 0;
5434 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5435 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5437 /* won't configure msix register if no mapping is done
5438 * between intr vector and event fd
5440 if (!rte_intr_dp_is_en(intr_handle))
5443 if (rte_intr_allow_others(intr_handle)) {
5444 vec = base = E1000_RX_VEC_START;
5448 /* set interrupt vector for other causes */
5449 if (hw->mac.type == e1000_82575) {
5450 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5451 /* enable MSI-X PBA support */
5452 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5454 /* Auto-Mask interrupts upon ICR read */
5455 tmpval |= E1000_CTRL_EXT_EIAME;
5456 tmpval |= E1000_CTRL_EXT_IRCA;
5458 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5460 /* enable msix_other interrupt */
5461 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5462 regval = E1000_READ_REG(hw, E1000_EIAC);
5463 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5464 regval = E1000_READ_REG(hw, E1000_EIAM);
5465 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5466 } else if ((hw->mac.type == e1000_82576) ||
5467 (hw->mac.type == e1000_82580) ||
5468 (hw->mac.type == e1000_i350) ||
5469 (hw->mac.type == e1000_i354) ||
5470 (hw->mac.type == e1000_i210) ||
5471 (hw->mac.type == e1000_i211)) {
5472 /* turn on MSI-X capability first */
5473 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5474 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5476 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5478 regval = E1000_READ_REG(hw, E1000_EIAC);
5479 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5481 /* enable msix_other interrupt */
5482 regval = E1000_READ_REG(hw, E1000_EIMS);
5483 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5484 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5485 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5488 /* use EIAM to auto-mask when MSI-X interrupt
5489 * is asserted, this saves a register write for every interrupt
5491 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5493 regval = E1000_READ_REG(hw, E1000_EIAM);
5494 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5496 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5497 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5498 intr_handle->intr_vec[queue_id] = vec;
5499 if (vec < base + intr_handle->nb_efd - 1)
5503 E1000_WRITE_FLUSH(hw);
5506 /* restore n-tuple filter */
5508 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5510 struct e1000_filter_info *filter_info =
5511 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5512 struct e1000_5tuple_filter *p_5tuple;
5513 struct e1000_2tuple_filter *p_2tuple;
5515 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5516 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5519 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5520 igb_inject_2uple_filter(dev, p_2tuple);
5524 /* restore SYN filter */
5526 igb_syn_filter_restore(struct rte_eth_dev *dev)
5528 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5529 struct e1000_filter_info *filter_info =
5530 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5533 synqf = filter_info->syn_info;
5535 if (synqf & E1000_SYN_FILTER_ENABLE) {
5536 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5537 E1000_WRITE_FLUSH(hw);
5541 /* restore ethernet type filter */
5543 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5545 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546 struct e1000_filter_info *filter_info =
5547 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5550 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5551 if (filter_info->ethertype_mask & (1 << i)) {
5552 E1000_WRITE_REG(hw, E1000_ETQF(i),
5553 filter_info->ethertype_filters[i].etqf);
5554 E1000_WRITE_FLUSH(hw);
5559 /* restore flex byte filter */
5561 igb_flex_filter_restore(struct rte_eth_dev *dev)
5563 struct e1000_filter_info *filter_info =
5564 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5565 struct e1000_flex_filter *flex_filter;
5567 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5568 igb_inject_flex_filter(dev, flex_filter);
5572 /* restore rss filter */
5574 igb_rss_filter_restore(struct rte_eth_dev *dev)
5576 struct e1000_filter_info *filter_info =
5577 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5579 if (filter_info->rss_info.num)
5580 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5583 /* restore all types filter */
5585 igb_filter_restore(struct rte_eth_dev *dev)
5587 igb_ntuple_filter_restore(dev);
5588 igb_ethertype_filter_restore(dev);
5589 igb_syn_filter_restore(dev);
5590 igb_flex_filter_restore(dev);
5591 igb_rss_filter_restore(dev);
5596 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5597 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5598 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5599 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5600 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5601 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");