drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 static int  eth_igb_configure(struct rte_eth_dev *dev);
  90 static int  eth_igb_start(struct rte_eth_dev *dev);
  91 static void eth_igb_stop(struct rte_eth_dev *dev);
  92 static void eth_igb_close(struct rte_eth_dev *dev);
  93 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  95 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  96 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  97 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  98                                 int wait_to_complete);
  99 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 100                                 struct rte_eth_stats *rte_stats);
 101 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 102                               struct rte_eth_xstat *xstats, unsigned n);
 103 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 104                                     struct rte_eth_xstat_name *xstats_names,
 105                                     unsigned limit);
 106 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 107 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 108 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 109                               struct rte_eth_dev_info *dev_info);
 110 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 111 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_dev_info *dev_info);
 113 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_fc_conf *fc_conf);
 115 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 116                                 struct rte_eth_fc_conf *fc_conf);
 117 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 118 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 119 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 120 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 121 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 122                                                         void *param);
 123 static int  igb_hardware_init(struct e1000_hw *hw);
 124 static void igb_hw_control_acquire(struct e1000_hw *hw);
 125 static void igb_hw_control_release(struct e1000_hw *hw);
 126 static void igb_init_manageability(struct e1000_hw *hw);
 127 static void igb_release_manageability(struct e1000_hw *hw);
 128
 129 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 130
 131 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 132                 uint16_t vlan_id, int on);
 133 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 134                                  enum rte_vlan_type vlan_type,
 135                                  uint16_t tpid_id);
 136 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 137
 138 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 141 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 142 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 143 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 144
 145 static int eth_igb_led_on(struct rte_eth_dev *dev);
 146 static int eth_igb_led_off(struct rte_eth_dev *dev);
 147
 148 static void igb_intr_disable(struct e1000_hw *hw);
 149 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 150 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 151                 struct ether_addr *mac_addr,
 152                 uint32_t index, uint32_t pool);
 153 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 154 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 155                 struct ether_addr *addr);
 156
 157 static void igbvf_intr_disable(struct e1000_hw *hw);
 158 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 159 static int igbvf_dev_start(struct rte_eth_dev *dev);
 160 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 161 static void igbvf_dev_close(struct rte_eth_dev *dev);
 162 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 163 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 164 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 165 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 166 static int eth_igbvf_link_update(struct e1000_hw *hw);
 167 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 168                                 struct rte_eth_stats *rte_stats);
 169 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 170                                 struct rte_eth_xstat *xstats, unsigned n);
 171 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 172                                       struct rte_eth_xstat_name *xstats_names,
 173                                       unsigned limit);
 174 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 175 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 176                 uint16_t vlan_id, int on);
 177 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 178 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 179 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 180                 struct ether_addr *addr);
 181 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 182 static int igbvf_get_regs(struct rte_eth_dev *dev,
 183                 struct rte_dev_reg_info *regs);
 184
 185 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 186                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                    uint16_t reta_size);
 188 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 189                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 190                                   uint16_t reta_size);
 191
 192 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 193                         struct rte_eth_syn_filter *filter,
 194                         bool add);
 195 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 196                         struct rte_eth_syn_filter *filter);
 197 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 198                         enum rte_filter_op filter_op,
 199                         void *arg);
 200 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 201                         struct rte_eth_ntuple_filter *ntuple_filter);
 202 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 203                         struct rte_eth_ntuple_filter *ntuple_filter);
 204 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 205                         struct rte_eth_flex_filter *filter,
 206                         bool add);
 207 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_flex_filter *filter);
 209 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 210                         enum rte_filter_op filter_op,
 211                         void *arg);
 212 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 213                         struct rte_eth_ntuple_filter *ntuple_filter);
 214 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 215                         struct rte_eth_ntuple_filter *ntuple_filter);
 216 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 217                         struct rte_eth_ntuple_filter *filter,
 218                         bool add);
 219 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 220                         struct rte_eth_ntuple_filter *filter);
 221 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 222                                 enum rte_filter_op filter_op,
 223                                 void *arg);
 224 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ethertype_filter *filter,
 226                         bool add);
 227 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 228                                 enum rte_filter_op filter_op,
 229                                 void *arg);
 230 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 231                         struct rte_eth_ethertype_filter *filter);
 232 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 233                      enum rte_filter_type filter_type,
 234                      enum rte_filter_op filter_op,
 235                      void *arg);
 236 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 237 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 238                 struct rte_dev_reg_info *regs);
 239 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 240 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 241                 struct rte_dev_eeprom_info *eeprom);
 242 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 243                 struct rte_dev_eeprom_info *eeprom);
 244 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 245                                     struct ether_addr *mc_addr_set,
 246                                     uint32_t nb_mc_addr);
 247 static int igb_timesync_enable(struct rte_eth_dev *dev);
 248 static int igb_timesync_disable(struct rte_eth_dev *dev);
 249 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 250                                           struct timespec *timestamp,
 251                                           uint32_t flags);
 252 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 253                                           struct timespec *timestamp);
 254 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 255 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 256                                   struct timespec *timestamp);
 257 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 258                                    const struct timespec *timestamp);
 259 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 260                                         uint16_t queue_id);
 261 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 262                                          uint16_t queue_id);
 263 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 264                                        uint8_t queue, uint8_t msix_vector);
 265 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 266                                uint8_t index, uint8_t offset);
 267 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 268
 269 /*
 270  * Define VF Stats MACRO for Non "cleared on read" register
 271  */
 272 #define UPDATE_VF_STAT(reg, last, cur)            \
 273 {                                                 \
 274         u32 latest = E1000_READ_REG(hw, reg);     \
 275         cur += (latest - last) & UINT_MAX;        \
 276         last = latest;                            \
 277 }
 278
 279 #define IGB_FC_PAUSE_TIME 0x0680
 280 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 281 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 282
 283 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 284
 285 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 286
 287 /*
 288  * The set of PCI devices this driver supports
 289  */
 290 static const struct rte_pci_id pci_id_igb_map[] = {
 291
 292 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 293 #include "rte_pci_dev_ids.h"
 294
 295 {0},
 296 };
 297
 298 /*
 299  * The set of PCI devices this driver supports (for 82576&I350 VF)
 300  */
 301 static const struct rte_pci_id pci_id_igbvf_map[] = {
 302
 303 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 304 #include "rte_pci_dev_ids.h"
 305
 306 {0},
 307 };
 308
 309 static const struct rte_eth_desc_lim rx_desc_lim = {
 310         .nb_max = E1000_MAX_RING_DESC,
 311         .nb_min = E1000_MIN_RING_DESC,
 312         .nb_align = IGB_RXD_ALIGN,
 313 };
 314
 315 static const struct rte_eth_desc_lim tx_desc_lim = {
 316         .nb_max = E1000_MAX_RING_DESC,
 317         .nb_min = E1000_MIN_RING_DESC,
 318         .nb_align = IGB_RXD_ALIGN,
 319 };
 320
 321 static const struct eth_dev_ops eth_igb_ops = {
 322         .dev_configure        = eth_igb_configure,
 323         .dev_start            = eth_igb_start,
 324         .dev_stop             = eth_igb_stop,
 325         .dev_close            = eth_igb_close,
 326         .promiscuous_enable   = eth_igb_promiscuous_enable,
 327         .promiscuous_disable  = eth_igb_promiscuous_disable,
 328         .allmulticast_enable  = eth_igb_allmulticast_enable,
 329         .allmulticast_disable = eth_igb_allmulticast_disable,
 330         .link_update          = eth_igb_link_update,
 331         .stats_get            = eth_igb_stats_get,
 332         .xstats_get           = eth_igb_xstats_get,
 333         .xstats_get_names     = eth_igb_xstats_get_names,
 334         .stats_reset          = eth_igb_stats_reset,
 335         .xstats_reset         = eth_igb_xstats_reset,
 336         .dev_infos_get        = eth_igb_infos_get,
 337         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 338         .mtu_set              = eth_igb_mtu_set,
 339         .vlan_filter_set      = eth_igb_vlan_filter_set,
 340         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 341         .vlan_offload_set     = eth_igb_vlan_offload_set,
 342         .rx_queue_setup       = eth_igb_rx_queue_setup,
 343         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 344         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 345         .rx_queue_release     = eth_igb_rx_queue_release,
 346         .rx_queue_count       = eth_igb_rx_queue_count,
 347         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 348         .tx_queue_setup       = eth_igb_tx_queue_setup,
 349         .tx_queue_release     = eth_igb_tx_queue_release,
 350         .dev_led_on           = eth_igb_led_on,
 351         .dev_led_off          = eth_igb_led_off,
 352         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 353         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 354         .mac_addr_add         = eth_igb_rar_set,
 355         .mac_addr_remove      = eth_igb_rar_clear,
 356         .mac_addr_set         = eth_igb_default_mac_addr_set,
 357         .reta_update          = eth_igb_rss_reta_update,
 358         .reta_query           = eth_igb_rss_reta_query,
 359         .rss_hash_update      = eth_igb_rss_hash_update,
 360         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 361         .filter_ctrl          = eth_igb_filter_ctrl,
 362         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 363         .rxq_info_get         = igb_rxq_info_get,
 364         .txq_info_get         = igb_txq_info_get,
 365         .timesync_enable      = igb_timesync_enable,
 366         .timesync_disable     = igb_timesync_disable,
 367         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 368         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 369         .get_reg_length       = eth_igb_get_reg_length,
 370         .get_reg              = eth_igb_get_regs,
 371         .get_eeprom_length    = eth_igb_get_eeprom_length,
 372         .get_eeprom           = eth_igb_get_eeprom,
 373         .set_eeprom           = eth_igb_set_eeprom,
 374         .timesync_adjust_time = igb_timesync_adjust_time,
 375         .timesync_read_time   = igb_timesync_read_time,
 376         .timesync_write_time  = igb_timesync_write_time,
 377 };
 378
 379 /*
 380  * dev_ops for virtual function, bare necessities for basic vf
 381  * operation have been implemented
 382  */
 383 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 384         .dev_configure        = igbvf_dev_configure,
 385         .dev_start            = igbvf_dev_start,
 386         .dev_stop             = igbvf_dev_stop,
 387         .dev_close            = igbvf_dev_close,
 388         .promiscuous_enable   = igbvf_promiscuous_enable,
 389         .promiscuous_disable  = igbvf_promiscuous_disable,
 390         .allmulticast_enable  = igbvf_allmulticast_enable,
 391         .allmulticast_disable = igbvf_allmulticast_disable,
 392         .link_update          = eth_igb_link_update,
 393         .stats_get            = eth_igbvf_stats_get,
 394         .xstats_get           = eth_igbvf_xstats_get,
 395         .xstats_get_names     = eth_igbvf_xstats_get_names,
 396         .stats_reset          = eth_igbvf_stats_reset,
 397         .xstats_reset         = eth_igbvf_stats_reset,
 398         .vlan_filter_set      = igbvf_vlan_filter_set,
 399         .dev_infos_get        = eth_igbvf_infos_get,
 400         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 401         .rx_queue_setup       = eth_igb_rx_queue_setup,
 402         .rx_queue_release     = eth_igb_rx_queue_release,
 403         .tx_queue_setup       = eth_igb_tx_queue_setup,
 404         .tx_queue_release     = eth_igb_tx_queue_release,
 405         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 406         .rxq_info_get         = igb_rxq_info_get,
 407         .txq_info_get         = igb_txq_info_get,
 408         .mac_addr_set         = igbvf_default_mac_addr_set,
 409         .get_reg_length       = igbvf_get_reg_length,
 410         .get_reg              = igbvf_get_regs,
 411 };
 412
 413 /* store statistics names and its offset in stats structure */
 414 struct rte_igb_xstats_name_off {
 415         char name[RTE_ETH_XSTATS_NAME_SIZE];
 416         unsigned offset;
 417 };
 418
 419 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 420         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 421         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 422         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 423         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 424         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 425         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 426         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 427                 ecol)},
 428         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 429         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 430         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 431         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 432         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 433         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 434         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 435         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 436         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 437         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 438         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 439                 fcruc)},
 440         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 441         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 442         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 443         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 444         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 445                 prc1023)},
 446         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 447                 prc1522)},
 448         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 449         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 450         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 451         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 452         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 453         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 454         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 455         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 456         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 457         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 458         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 459         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 460         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 461         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 462         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 463         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 464         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 465         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 466                 ptc1023)},
 467         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 468                 ptc1522)},
 469         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 470         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 471         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 472         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 473         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 474         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 475         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 476
 477         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 478 };
 479
 480 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 481                 sizeof(rte_igb_stats_strings[0]))
 482
 483 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 484         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 485         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 486         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 487         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 488         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 489 };
 490
 491 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 492                 sizeof(rte_igbvf_stats_strings[0]))
 493
 494 /**
 495  * Atomically reads the link status information from global
 496  * structure rte_eth_dev.
 497  *
 498  * @param dev
 499  *   - Pointer to the structure rte_eth_dev to read from.
 500  *   - Pointer to the buffer to be saved with the link status.
 501  *
 502  * @return
 503  *   - On success, zero.
 504  *   - On failure, negative value.
 505  */
 506 static inline int
 507 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 508                                 struct rte_eth_link *link)
 509 {
 510         struct rte_eth_link *dst = link;
 511         struct rte_eth_link *src = &(dev->data->dev_link);
 512
 513         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 514                                         *(uint64_t *)src) == 0)
 515                 return -1;
 516
 517         return 0;
 518 }
 519
 520 /**
 521  * Atomically writes the link status information into global
 522  * structure rte_eth_dev.
 523  *
 524  * @param dev
 525  *   - Pointer to the structure rte_eth_dev to read from.
 526  *   - Pointer to the buffer to be saved with the link status.
 527  *
 528  * @return
 529  *   - On success, zero.
 530  *   - On failure, negative value.
 531  */
 532 static inline int
 533 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 534                                 struct rte_eth_link *link)
 535 {
 536         struct rte_eth_link *dst = &(dev->data->dev_link);
 537         struct rte_eth_link *src = link;
 538
 539         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 540                                         *(uint64_t *)src) == 0)
 541                 return -1;
 542
 543         return 0;
 544 }
 545
 546 static inline void
 547 igb_intr_enable(struct rte_eth_dev *dev)
 548 {
 549         struct e1000_interrupt *intr =
 550                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 551         struct e1000_hw *hw =
 552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553
 554         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 555         E1000_WRITE_FLUSH(hw);
 556 }
 557
 558 static void
 559 igb_intr_disable(struct e1000_hw *hw)
 560 {
 561         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 562         E1000_WRITE_FLUSH(hw);
 563 }
 564
 565 static inline int32_t
 566 igb_pf_reset_hw(struct e1000_hw *hw)
 567 {
 568         uint32_t ctrl_ext;
 569         int32_t status;
 570
 571         status = e1000_reset_hw(hw);
 572
 573         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 574         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 575         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 576         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 577         E1000_WRITE_FLUSH(hw);
 578
 579         return status;
 580 }
 581
 582 static void
 583 igb_identify_hardware(struct rte_eth_dev *dev)
 584 {
 585         struct e1000_hw *hw =
 586                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 587
 588         hw->vendor_id = dev->pci_dev->id.vendor_id;
 589         hw->device_id = dev->pci_dev->id.device_id;
 590         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 591         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 592
 593         e1000_set_mac_type(hw);
 594
 595         /* need to check if it is a vf device below */
 596 }
 597
 598 static int
 599 igb_reset_swfw_lock(struct e1000_hw *hw)
 600 {
 601         int ret_val;
 602
 603         /*
 604          * Do mac ops initialization manually here, since we will need
 605          * some function pointers set by this call.
 606          */
 607         ret_val = e1000_init_mac_params(hw);
 608         if (ret_val)
 609                 return ret_val;
 610
 611         /*
 612          * SMBI lock should not fail in this early stage. If this is the case,
 613          * it is due to an improper exit of the application.
 614          * So force the release of the faulty lock.
 615          */
 616         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 617                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 618         }
 619         e1000_put_hw_semaphore_generic(hw);
 620
 621         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 622                 uint16_t mask;
 623
 624                 /*
 625                  * Phy lock should not fail in this early stage. If this is the case,
 626                  * it is due to an improper exit of the application.
 627                  * So force the release of the faulty lock.
 628                  */
 629                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 630                 if (hw->bus.func > E1000_FUNC_1)
 631                         mask <<= 2;
 632                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 633                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 634                                     hw->bus.func);
 635                 }
 636                 hw->mac.ops.release_swfw_sync(hw, mask);
 637
 638                 /*
 639                  * This one is more tricky since it is common to all ports; but
 640                  * swfw_sync retries last long enough (1s) to be almost sure that if
 641                  * lock can not be taken it is due to an improper lock of the
 642                  * semaphore.
 643                  */
 644                 mask = E1000_SWFW_EEP_SM;
 645                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 646                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 647                 }
 648                 hw->mac.ops.release_swfw_sync(hw, mask);
 649         }
 650
 651         return E1000_SUCCESS;
 652 }
 653
 654 static int
 655 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 656 {
 657         int error = 0;
 658         struct rte_pci_device *pci_dev;
 659         struct e1000_hw *hw =
 660                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 661         struct e1000_vfta * shadow_vfta =
 662                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 663         struct e1000_filter_info *filter_info =
 664                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 665         struct e1000_adapter *adapter =
 666                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 667
 668         uint32_t ctrl_ext;
 669
 670         pci_dev = eth_dev->pci_dev;
 671
 672         eth_dev->dev_ops = &eth_igb_ops;
 673         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 674         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 675
 676         /* for secondary processes, we don't initialise any further as primary
 677          * has already done this work. Only check we don't need a different
 678          * RX function */
 679         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 680                 if (eth_dev->data->scattered_rx)
 681                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 682                 return 0;
 683         }
 684
 685         rte_eth_copy_pci_info(eth_dev, pci_dev);
 686
 687         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 688
 689         igb_identify_hardware(eth_dev);
 690         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 691                 error = -EIO;
 692                 goto err_late;
 693         }
 694
 695         e1000_get_bus_info(hw);
 696
 697         /* Reset any pending lock */
 698         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 699                 error = -EIO;
 700                 goto err_late;
 701         }
 702
 703         /* Finish initialization */
 704         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 705                 error = -EIO;
 706                 goto err_late;
 707         }
 708
 709         hw->mac.autoneg = 1;
 710         hw->phy.autoneg_wait_to_complete = 0;
 711         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 712
 713         /* Copper options */
 714         if (hw->phy.media_type == e1000_media_type_copper) {
 715                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 716                 hw->phy.disable_polarity_correction = 0;
 717                 hw->phy.ms_type = e1000_ms_hw_default;
 718         }
 719
 720         /*
 721          * Start from a known state, this is important in reading the nvm
 722          * and mac from that.
 723          */
 724         igb_pf_reset_hw(hw);
 725
 726         /* Make sure we have a good EEPROM before we read from it */
 727         if (e1000_validate_nvm_checksum(hw) < 0) {
 728                 /*
 729                  * Some PCI-E parts fail the first check due to
 730                  * the link being in sleep state, call it again,
 731                  * if it fails a second time its a real issue.
 732                  */
 733                 if (e1000_validate_nvm_checksum(hw) < 0) {
 734                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 735                         error = -EIO;
 736                         goto err_late;
 737                 }
 738         }
 739
 740         /* Read the permanent MAC address out of the EEPROM */
 741         if (e1000_read_mac_addr(hw) != 0) {
 742                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 743                 error = -EIO;
 744                 goto err_late;
 745         }
 746
 747         /* Allocate memory for storing MAC addresses */
 748         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 749                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 750         if (eth_dev->data->mac_addrs == NULL) {
 751                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 752                                                 "store MAC addresses",
 753                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 754                 error = -ENOMEM;
 755                 goto err_late;
 756         }
 757
 758         /* Copy the permanent MAC address */
 759         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 760
 761         /* initialize the vfta */
 762         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 763
 764         /* Now initialize the hardware */
 765         if (igb_hardware_init(hw) != 0) {
 766                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 767                 rte_free(eth_dev->data->mac_addrs);
 768                 eth_dev->data->mac_addrs = NULL;
 769                 error = -ENODEV;
 770                 goto err_late;
 771         }
 772         hw->mac.get_link_status = 1;
 773         adapter->stopped = 0;
 774
 775         /* Indicate SOL/IDER usage */
 776         if (e1000_check_reset_block(hw) < 0) {
 777                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 778                                         "SOL/IDER session");
 779         }
 780
 781         /* initialize PF if max_vfs not zero */
 782         igb_pf_host_init(eth_dev);
 783
 784         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 785         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 786         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 787         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 788         E1000_WRITE_FLUSH(hw);
 789
 790         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 791                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 792                      pci_dev->id.device_id);
 793
 794         rte_intr_callback_register(&pci_dev->intr_handle,
 795                                    eth_igb_interrupt_handler,
 796                                    (void *)eth_dev);
 797
 798         /* enable uio/vfio intr/eventfd mapping */
 799         rte_intr_enable(&pci_dev->intr_handle);
 800
 801         /* enable support intr */
 802         igb_intr_enable(eth_dev);
 803
 804         TAILQ_INIT(&filter_info->flex_list);
 805         filter_info->flex_mask = 0;
 806         TAILQ_INIT(&filter_info->twotuple_list);
 807         filter_info->twotuple_mask = 0;
 808         TAILQ_INIT(&filter_info->fivetuple_list);
 809         filter_info->fivetuple_mask = 0;
 810
 811         return 0;
 812
 813 err_late:
 814         igb_hw_control_release(hw);
 815
 816         return error;
 817 }
 818
 819 static int
 820 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 821 {
 822         struct rte_pci_device *pci_dev;
 823         struct e1000_hw *hw;
 824         struct e1000_adapter *adapter =
 825                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 826
 827         PMD_INIT_FUNC_TRACE();
 828
 829         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 830                 return -EPERM;
 831
 832         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 833         pci_dev = eth_dev->pci_dev;
 834
 835         if (adapter->stopped == 0)
 836                 eth_igb_close(eth_dev);
 837
 838         eth_dev->dev_ops = NULL;
 839         eth_dev->rx_pkt_burst = NULL;
 840         eth_dev->tx_pkt_burst = NULL;
 841
 842         /* Reset any pending lock */
 843         igb_reset_swfw_lock(hw);
 844
 845         rte_free(eth_dev->data->mac_addrs);
 846         eth_dev->data->mac_addrs = NULL;
 847
 848         /* uninitialize PF if max_vfs not zero */
 849         igb_pf_host_uninit(eth_dev);
 850
 851         /* disable uio intr before callback unregister */
 852         rte_intr_disable(&(pci_dev->intr_handle));
 853         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 854                 eth_igb_interrupt_handler, (void *)eth_dev);
 855
 856         return 0;
 857 }
 858
 859 /*
 860  * Virtual Function device init
 861  */
 862 static int
 863 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 864 {
 865         struct rte_pci_device *pci_dev;
 866         struct e1000_adapter *adapter =
 867                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 868         struct e1000_hw *hw =
 869                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 870         int diag;
 871         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 872
 873         PMD_INIT_FUNC_TRACE();
 874
 875         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 876         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 877         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 878
 879         /* for secondary processes, we don't initialise any further as primary
 880          * has already done this work. Only check we don't need a different
 881          * RX function */
 882         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 883                 if (eth_dev->data->scattered_rx)
 884                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 885                 return 0;
 886         }
 887
 888         pci_dev = eth_dev->pci_dev;
 889
 890         rte_eth_copy_pci_info(eth_dev, pci_dev);
 891
 892         hw->device_id = pci_dev->id.device_id;
 893         hw->vendor_id = pci_dev->id.vendor_id;
 894         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 895         adapter->stopped = 0;
 896
 897         /* Initialize the shared code (base driver) */
 898         diag = e1000_setup_init_funcs(hw, TRUE);
 899         if (diag != 0) {
 900                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 901                         diag);
 902                 return -EIO;
 903         }
 904
 905         /* init_mailbox_params */
 906         hw->mbx.ops.init_params(hw);
 907
 908         /* Disable the interrupts for VF */
 909         igbvf_intr_disable(hw);
 910
 911         diag = hw->mac.ops.reset_hw(hw);
 912
 913         /* Allocate memory for storing MAC addresses */
 914         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 915                 hw->mac.rar_entry_count, 0);
 916         if (eth_dev->data->mac_addrs == NULL) {
 917                 PMD_INIT_LOG(ERR,
 918                         "Failed to allocate %d bytes needed to store MAC "
 919                         "addresses",
 920                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 921                 return -ENOMEM;
 922         }
 923
 924         /* Generate a random MAC address, if none was assigned by PF. */
 925         if (is_zero_ether_addr(perm_addr)) {
 926                 eth_random_addr(perm_addr->addr_bytes);
 927                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 928                 if (diag) {
 929                         rte_free(eth_dev->data->mac_addrs);
 930                         eth_dev->data->mac_addrs = NULL;
 931                         return diag;
 932                 }
 933                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 934                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 935                              "%02x:%02x:%02x:%02x:%02x:%02x",
 936                              perm_addr->addr_bytes[0],
 937                              perm_addr->addr_bytes[1],
 938                              perm_addr->addr_bytes[2],
 939                              perm_addr->addr_bytes[3],
 940                              perm_addr->addr_bytes[4],
 941                              perm_addr->addr_bytes[5]);
 942         }
 943
 944         /* Copy the permanent MAC address */
 945         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 946                         &eth_dev->data->mac_addrs[0]);
 947
 948         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 949                      "mac.type=%s",
 950                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 951                      pci_dev->id.device_id, "igb_mac_82576_vf");
 952
 953         return 0;
 954 }
 955
 956 static int
 957 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 958 {
 959         struct e1000_adapter *adapter =
 960                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 961
 962         PMD_INIT_FUNC_TRACE();
 963
 964         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 965                 return -EPERM;
 966
 967         if (adapter->stopped == 0)
 968                 igbvf_dev_close(eth_dev);
 969
 970         eth_dev->dev_ops = NULL;
 971         eth_dev->rx_pkt_burst = NULL;
 972         eth_dev->tx_pkt_burst = NULL;
 973
 974         rte_free(eth_dev->data->mac_addrs);
 975         eth_dev->data->mac_addrs = NULL;
 976
 977         return 0;
 978 }
 979
 980 static struct eth_driver rte_igb_pmd = {
 981         .pci_drv = {
 982                 .name = "rte_igb_pmd",
 983                 .id_table = pci_id_igb_map,
 984                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 985                         RTE_PCI_DRV_DETACHABLE,
 986         },
 987         .eth_dev_init = eth_igb_dev_init,
 988         .eth_dev_uninit = eth_igb_dev_uninit,
 989         .dev_private_size = sizeof(struct e1000_adapter),
 990 };
 991
 992 /*
 993  * virtual function driver struct
 994  */
 995 static struct eth_driver rte_igbvf_pmd = {
 996         .pci_drv = {
 997                 .name = "rte_igbvf_pmd",
 998                 .id_table = pci_id_igbvf_map,
 999                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1000         },
1001         .eth_dev_init = eth_igbvf_dev_init,
1002         .eth_dev_uninit = eth_igbvf_dev_uninit,
1003         .dev_private_size = sizeof(struct e1000_adapter),
1004 };
1005
1006 static int
1007 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1008 {
1009         rte_eth_driver_register(&rte_igb_pmd);
1010         return 0;
1011 }
1012
1013 static void
1014 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1015 {
1016         struct e1000_hw *hw =
1017                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1018         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1019         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1020         rctl |= E1000_RCTL_VFE;
1021         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1022 }
1023
1024 /*
1025  * VF Driver initialization routine.
1026  * Invoked one at EAL init time.
1027  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1028  */
1029 static int
1030 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1031 {
1032         PMD_INIT_FUNC_TRACE();
1033
1034         rte_eth_driver_register(&rte_igbvf_pmd);
1035         return 0;
1036 }
1037
1038 static int
1039 igb_check_mq_mode(struct rte_eth_dev *dev)
1040 {
1041         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1042         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1043         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1044         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1045
1046         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1047             tx_mq_mode == ETH_MQ_TX_DCB ||
1048             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1049                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1050                 return -EINVAL;
1051         }
1052         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1053                 /* Check multi-queue mode.
1054                  * To no break software we accept ETH_MQ_RX_NONE as this might
1055                  * be used to turn off VLAN filter.
1056                  */
1057
1058                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1059                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1060                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1061                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1062                 } else {
1063                         /* Only support one queue on VFs.
1064                          * RSS together with SRIOV is not supported.
1065                          */
1066                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1067                                         " wrong mq_mode rx %d.",
1068                                         rx_mq_mode);
1069                         return -EINVAL;
1070                 }
1071                 /* TX mode is not used here, so mode might be ignored.*/
1072                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1073                         /* SRIOV only works in VMDq enable mode */
1074                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1075                                         " TX mode %d is not supported. "
1076                                         " Driver will behave as %d mode.",
1077                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1078                 }
1079
1080                 /* check valid queue number */
1081                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1082                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1083                                         " only support one queue on VFs.");
1084                         return -EINVAL;
1085                 }
1086         } else {
1087                 /* To no break software that set invalid mode, only display
1088                  * warning if invalid mode is used.
1089                  */
1090                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1091                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1092                     rx_mq_mode != ETH_MQ_RX_RSS) {
1093                         /* RSS together with VMDq not supported*/
1094                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1095                                      rx_mq_mode);
1096                         return -EINVAL;
1097                 }
1098
1099                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1100                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1101                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1102                                         " Due to txmode is meaningless in this"
1103                                         " driver, just ignore.",
1104                                         tx_mq_mode);
1105                 }
1106         }
1107         return 0;
1108 }
1109
1110 static int
1111 eth_igb_configure(struct rte_eth_dev *dev)
1112 {
1113         struct e1000_interrupt *intr =
1114                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1115         int ret;
1116
1117         PMD_INIT_FUNC_TRACE();
1118
1119         /* multipe queue mode checking */
1120         ret  = igb_check_mq_mode(dev);
1121         if (ret != 0) {
1122                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1123                             ret);
1124                 return ret;
1125         }
1126
1127         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1128         PMD_INIT_FUNC_TRACE();
1129
1130         return 0;
1131 }
1132
1133 static int
1134 eth_igb_start(struct rte_eth_dev *dev)
1135 {
1136         struct e1000_hw *hw =
1137                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1138         struct e1000_adapter *adapter =
1139                 E1000_DEV_PRIVATE(dev->data->dev_private);
1140         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1141         int ret, mask;
1142         uint32_t intr_vector = 0;
1143         uint32_t ctrl_ext;
1144         uint32_t *speeds;
1145         int num_speeds;
1146         bool autoneg;
1147
1148         PMD_INIT_FUNC_TRACE();
1149
1150         /* disable uio/vfio intr/eventfd mapping */
1151         rte_intr_disable(intr_handle);
1152
1153         /* Power up the phy. Needed to make the link go Up */
1154         e1000_power_up_phy(hw);
1155
1156         /*
1157          * Packet Buffer Allocation (PBA)
1158          * Writing PBA sets the receive portion of the buffer
1159          * the remainder is used for the transmit buffer.
1160          */
1161         if (hw->mac.type == e1000_82575) {
1162                 uint32_t pba;
1163
1164                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1165                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1166         }
1167
1168         /* Put the address into the Receive Address Array */
1169         e1000_rar_set(hw, hw->mac.addr, 0);
1170
1171         /* Initialize the hardware */
1172         if (igb_hardware_init(hw)) {
1173                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1174                 return -EIO;
1175         }
1176         adapter->stopped = 0;
1177
1178         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1179
1180         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1181         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1182         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1183         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1184         E1000_WRITE_FLUSH(hw);
1185
1186         /* configure PF module if SRIOV enabled */
1187         igb_pf_host_configure(dev);
1188
1189         /* check and configure queue intr-vector mapping */
1190         if ((rte_intr_cap_multiple(intr_handle) ||
1191              !RTE_ETH_DEV_SRIOV(dev).active) &&
1192             dev->data->dev_conf.intr_conf.rxq != 0) {
1193                 intr_vector = dev->data->nb_rx_queues;
1194                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1195                         return -1;
1196         }
1197
1198         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1199                 intr_handle->intr_vec =
1200                         rte_zmalloc("intr_vec",
1201                                     dev->data->nb_rx_queues * sizeof(int), 0);
1202                 if (intr_handle->intr_vec == NULL) {
1203                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1204                                      " intr_vec\n", dev->data->nb_rx_queues);
1205                         return -ENOMEM;
1206                 }
1207         }
1208
1209         /* confiugre msix for rx interrupt */
1210         eth_igb_configure_msix_intr(dev);
1211
1212         /* Configure for OS presence */
1213         igb_init_manageability(hw);
1214
1215         eth_igb_tx_init(dev);
1216
1217         /* This can fail when allocating mbufs for descriptor rings */
1218         ret = eth_igb_rx_init(dev);
1219         if (ret) {
1220                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1221                 igb_dev_clear_queues(dev);
1222                 return ret;
1223         }
1224
1225         e1000_clear_hw_cntrs_base_generic(hw);
1226
1227         /*
1228          * VLAN Offload Settings
1229          */
1230         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1231                         ETH_VLAN_EXTEND_MASK;
1232         eth_igb_vlan_offload_set(dev, mask);
1233
1234         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1235                 /* Enable VLAN filter since VMDq always use VLAN filter */
1236                 igb_vmdq_vlan_hw_filter_enable(dev);
1237         }
1238
1239         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1240                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1241                 (hw->mac.type == e1000_i211)) {
1242                 /* Configure EITR with the maximum possible value (0xFFFF) */
1243                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1244         }
1245
1246         /* Setup link speed and duplex */
1247         speeds = &dev->data->dev_conf.link_speeds;
1248         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1249                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1250         } else {
1251                 num_speeds = 0;
1252                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1253
1254                 /* Reset */
1255                 hw->phy.autoneg_advertised = 0;
1256
1257                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1258                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1259                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1260                         num_speeds = -1;
1261                         goto error_invalid_config;
1262                 }
1263                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1264                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1265                         num_speeds++;
1266                 }
1267                 if (*speeds & ETH_LINK_SPEED_10M) {
1268                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1269                         num_speeds++;
1270                 }
1271                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1272                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1273                         num_speeds++;
1274                 }
1275                 if (*speeds & ETH_LINK_SPEED_100M) {
1276                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1277                         num_speeds++;
1278                 }
1279                 if (*speeds & ETH_LINK_SPEED_1G) {
1280                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1281                         num_speeds++;
1282                 }
1283                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1284                         goto error_invalid_config;
1285         }
1286
1287         e1000_setup_link(hw);
1288
1289         if (rte_intr_allow_others(intr_handle)) {
1290                 /* check if lsc interrupt is enabled */
1291                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1292                         eth_igb_lsc_interrupt_setup(dev);
1293         } else {
1294                 rte_intr_callback_unregister(intr_handle,
1295                                              eth_igb_interrupt_handler,
1296                                              (void *)dev);
1297                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1298                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1299                                      " no intr multiplex\n");
1300         }
1301
1302         /* check if rxq interrupt is enabled */
1303         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1304             rte_intr_dp_is_en(intr_handle))
1305                 eth_igb_rxq_interrupt_setup(dev);
1306
1307         /* enable uio/vfio intr/eventfd mapping */
1308         rte_intr_enable(intr_handle);
1309
1310         /* resume enabled intr since hw reset */
1311         igb_intr_enable(dev);
1312
1313         PMD_INIT_LOG(DEBUG, "<<");
1314
1315         return 0;
1316
1317 error_invalid_config:
1318         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1319                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1320         igb_dev_clear_queues(dev);
1321         return -EINVAL;
1322 }
1323
1324 /*********************************************************************
1325  *
1326  *  This routine disables all traffic on the adapter by issuing a
1327  *  global reset on the MAC.
1328  *
1329  **********************************************************************/
1330 static void
1331 eth_igb_stop(struct rte_eth_dev *dev)
1332 {
1333         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1334         struct e1000_filter_info *filter_info =
1335                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1336         struct rte_eth_link link;
1337         struct e1000_flex_filter *p_flex;
1338         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1339         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1340         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1341
1342         igb_intr_disable(hw);
1343
1344         /* disable intr eventfd mapping */
1345         rte_intr_disable(intr_handle);
1346
1347         igb_pf_reset_hw(hw);
1348         E1000_WRITE_REG(hw, E1000_WUC, 0);
1349
1350         /* Set bit for Go Link disconnect */
1351         if (hw->mac.type >= e1000_82580) {
1352                 uint32_t phpm_reg;
1353
1354                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1355                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1356                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1357         }
1358
1359         /* Power down the phy. Needed to make the link go Down */
1360         if (hw->phy.media_type == e1000_media_type_copper)
1361                 e1000_power_down_phy(hw);
1362         else
1363                 e1000_shutdown_fiber_serdes_link(hw);
1364
1365         igb_dev_clear_queues(dev);
1366
1367         /* clear the recorded link status */
1368         memset(&link, 0, sizeof(link));
1369         rte_igb_dev_atomic_write_link_status(dev, &link);
1370
1371         /* Remove all flex filters of the device */
1372         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1373                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1374                 rte_free(p_flex);
1375         }
1376         filter_info->flex_mask = 0;
1377
1378         /* Remove all ntuple filters of the device */
1379         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1380              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1381                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1382                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1383                              p_5tuple, entries);
1384                 rte_free(p_5tuple);
1385         }
1386         filter_info->fivetuple_mask = 0;
1387         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1388              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1389                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1390                 TAILQ_REMOVE(&filter_info->twotuple_list,
1391                              p_2tuple, entries);
1392                 rte_free(p_2tuple);
1393         }
1394         filter_info->twotuple_mask = 0;
1395
1396         if (!rte_intr_allow_others(intr_handle))
1397                 /* resume to the default handler */
1398                 rte_intr_callback_register(intr_handle,
1399                                            eth_igb_interrupt_handler,
1400                                            (void *)dev);
1401
1402         /* Clean datapath event and queue/vec mapping */
1403         rte_intr_efd_disable(intr_handle);
1404         if (intr_handle->intr_vec != NULL) {
1405                 rte_free(intr_handle->intr_vec);
1406                 intr_handle->intr_vec = NULL;
1407         }
1408 }
1409
1410 static void
1411 eth_igb_close(struct rte_eth_dev *dev)
1412 {
1413         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414         struct e1000_adapter *adapter =
1415                 E1000_DEV_PRIVATE(dev->data->dev_private);
1416         struct rte_eth_link link;
1417         struct rte_pci_device *pci_dev;
1418
1419         eth_igb_stop(dev);
1420         adapter->stopped = 1;
1421
1422         e1000_phy_hw_reset(hw);
1423         igb_release_manageability(hw);
1424         igb_hw_control_release(hw);
1425
1426         /* Clear bit for Go Link disconnect */
1427         if (hw->mac.type >= e1000_82580) {
1428                 uint32_t phpm_reg;
1429
1430                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1431                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1432                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1433         }
1434
1435         igb_dev_free_queues(dev);
1436
1437         pci_dev = dev->pci_dev;
1438         if (pci_dev->intr_handle.intr_vec) {
1439                 rte_free(pci_dev->intr_handle.intr_vec);
1440                 pci_dev->intr_handle.intr_vec = NULL;
1441         }
1442
1443         memset(&link, 0, sizeof(link));
1444         rte_igb_dev_atomic_write_link_status(dev, &link);
1445 }
1446
1447 static int
1448 igb_get_rx_buffer_size(struct e1000_hw *hw)
1449 {
1450         uint32_t rx_buf_size;
1451         if (hw->mac.type == e1000_82576) {
1452                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1453         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1454                 /* PBS needs to be translated according to a lookup table */
1455                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1456                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1457                 rx_buf_size = (rx_buf_size << 10);
1458         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1459                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1460         } else {
1461                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1462         }
1463
1464         return rx_buf_size;
1465 }
1466
1467 /*********************************************************************
1468  *
1469  *  Initialize the hardware
1470  *
1471  **********************************************************************/
1472 static int
1473 igb_hardware_init(struct e1000_hw *hw)
1474 {
1475         uint32_t rx_buf_size;
1476         int diag;
1477
1478         /* Let the firmware know the OS is in control */
1479         igb_hw_control_acquire(hw);
1480
1481         /*
1482          * These parameters control the automatic generation (Tx) and
1483          * response (Rx) to Ethernet PAUSE frames.
1484          * - High water mark should allow for at least two standard size (1518)
1485          *   frames to be received after sending an XOFF.
1486          * - Low water mark works best when it is very near the high water mark.
1487          *   This allows the receiver to restart by sending XON when it has
1488          *   drained a bit. Here we use an arbitrary value of 1500 which will
1489          *   restart after one full frame is pulled from the buffer. There
1490          *   could be several smaller frames in the buffer and if so they will
1491          *   not trigger the XON until their total number reduces the buffer
1492          *   by 1500.
1493          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1494          */
1495         rx_buf_size = igb_get_rx_buffer_size(hw);
1496
1497         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1498         hw->fc.low_water = hw->fc.high_water - 1500;
1499         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1500         hw->fc.send_xon = 1;
1501
1502         /* Set Flow control, use the tunable location if sane */
1503         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1504                 hw->fc.requested_mode = igb_fc_setting;
1505         else
1506                 hw->fc.requested_mode = e1000_fc_none;
1507
1508         /* Issue a global reset */
1509         igb_pf_reset_hw(hw);
1510         E1000_WRITE_REG(hw, E1000_WUC, 0);
1511
1512         diag = e1000_init_hw(hw);
1513         if (diag < 0)
1514                 return diag;
1515
1516         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1517         e1000_get_phy_info(hw);
1518         e1000_check_for_link(hw);
1519
1520         return 0;
1521 }
1522
1523 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1524 static void
1525 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1526 {
1527         int pause_frames;
1528
1529         uint64_t old_gprc  = stats->gprc;
1530         uint64_t old_gptc  = stats->gptc;
1531         uint64_t old_tpr   = stats->tpr;
1532         uint64_t old_tpt   = stats->tpt;
1533         uint64_t old_rpthc = stats->rpthc;
1534         uint64_t old_hgptc = stats->hgptc;
1535
1536         if(hw->phy.media_type == e1000_media_type_copper ||
1537             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1538                 stats->symerrs +=
1539                     E1000_READ_REG(hw,E1000_SYMERRS);
1540                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1541         }
1542
1543         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1544         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1545         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1546         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1547
1548         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1549         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1550         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1551         stats->dc += E1000_READ_REG(hw, E1000_DC);
1552         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1553         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1554         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1555         /*
1556         ** For watchdog management we need to know if we have been
1557         ** paused during the last interval, so capture that here.
1558         */
1559         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1560         stats->xoffrxc += pause_frames;
1561         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1562         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1563         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1564         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1565         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1566         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1567         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1568         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1569         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1570         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1571         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1572         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1573
1574         /* For the 64-bit byte counters the low dword must be read first. */
1575         /* Both registers clear on the read of the high dword */
1576
1577         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1578         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1579         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1580         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1581         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1582         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1583         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1584
1585         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1586         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1587         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1588         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1589         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1590
1591         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1592         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1593
1594         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1595         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1596         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1597         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1598         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1599         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1600
1601         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1602         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1603         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1604         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1605         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1606         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1607         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1608         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1609
1610         /* Interrupt Counts */
1611
1612         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1613         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1614         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1615         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1616         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1617         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1618         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1619         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1620         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1621
1622         /* Host to Card Statistics */
1623
1624         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1625         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1626         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1627         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1628         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1629         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1630         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1631         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1632         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1633         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1634         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1635         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1636         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1637         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1638         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1639         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1640
1641         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1642         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1643         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1644         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1645         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1646         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1647 }
1648
1649 static void
1650 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1651 {
1652         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         struct e1000_hw_stats *stats =
1654                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1655
1656         igb_read_stats_registers(hw, stats);
1657
1658         if (rte_stats == NULL)
1659                 return;
1660
1661         /* Rx Errors */
1662         rte_stats->imissed = stats->mpc;
1663         rte_stats->ierrors = stats->crcerrs +
1664                              stats->rlec + stats->ruc + stats->roc +
1665                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1666
1667         /* Tx Errors */
1668         rte_stats->oerrors = stats->ecol + stats->latecol;
1669
1670         rte_stats->ipackets = stats->gprc;
1671         rte_stats->opackets = stats->gptc;
1672         rte_stats->ibytes   = stats->gorc;
1673         rte_stats->obytes   = stats->gotc;
1674 }
1675
1676 static void
1677 eth_igb_stats_reset(struct rte_eth_dev *dev)
1678 {
1679         struct e1000_hw_stats *hw_stats =
1680                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1681
1682         /* HW registers are cleared on read */
1683         eth_igb_stats_get(dev, NULL);
1684
1685         /* Reset software totals */
1686         memset(hw_stats, 0, sizeof(*hw_stats));
1687 }
1688
1689 static void
1690 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1691 {
1692         struct e1000_hw_stats *stats =
1693                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1694
1695         /* HW registers are cleared on read */
1696         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1697
1698         /* Reset software totals */
1699         memset(stats, 0, sizeof(*stats));
1700 }
1701
1702 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1703         struct rte_eth_xstat_name *xstats_names,
1704         __rte_unused unsigned limit)
1705 {
1706         unsigned i;
1707
1708         if (xstats_names == NULL)
1709                 return IGB_NB_XSTATS;
1710
1711         /* Note: limit checked in rte_eth_xstats_names() */
1712
1713         for (i = 0; i < IGB_NB_XSTATS; i++) {
1714                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1715                          "%s", rte_igb_stats_strings[i].name);
1716                 xstats_names[i].id = i;
1717         }
1718
1719         return IGB_NB_XSTATS;
1720 }
1721
1722 static int
1723 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1724                    unsigned n)
1725 {
1726         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727         struct e1000_hw_stats *hw_stats =
1728                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1729         unsigned i;
1730
1731         if (n < IGB_NB_XSTATS)
1732                 return IGB_NB_XSTATS;
1733
1734         igb_read_stats_registers(hw, hw_stats);
1735
1736         /* If this is a reset xstats is NULL, and we have cleared the
1737          * registers by reading them.
1738          */
1739         if (!xstats)
1740                 return 0;
1741
1742         /* Extended stats */
1743         for (i = 0; i < IGB_NB_XSTATS; i++) {
1744                 xstats[i].id = i;
1745                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1746                         rte_igb_stats_strings[i].offset);
1747         }
1748
1749         return IGB_NB_XSTATS;
1750 }
1751
1752 static void
1753 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1754 {
1755         /* Good Rx packets, include VF loopback */
1756         UPDATE_VF_STAT(E1000_VFGPRC,
1757             hw_stats->last_gprc, hw_stats->gprc);
1758
1759         /* Good Rx octets, include VF loopback */
1760         UPDATE_VF_STAT(E1000_VFGORC,
1761             hw_stats->last_gorc, hw_stats->gorc);
1762
1763         /* Good Tx packets, include VF loopback */
1764         UPDATE_VF_STAT(E1000_VFGPTC,
1765             hw_stats->last_gptc, hw_stats->gptc);
1766
1767         /* Good Tx octets, include VF loopback */
1768         UPDATE_VF_STAT(E1000_VFGOTC,
1769             hw_stats->last_gotc, hw_stats->gotc);
1770
1771         /* Rx Multicst packets */
1772         UPDATE_VF_STAT(E1000_VFMPRC,
1773             hw_stats->last_mprc, hw_stats->mprc);
1774
1775         /* Good Rx loopback packets */
1776         UPDATE_VF_STAT(E1000_VFGPRLBC,
1777             hw_stats->last_gprlbc, hw_stats->gprlbc);
1778
1779         /* Good Rx loopback octets */
1780         UPDATE_VF_STAT(E1000_VFGORLBC,
1781             hw_stats->last_gorlbc, hw_stats->gorlbc);
1782
1783         /* Good Tx loopback packets */
1784         UPDATE_VF_STAT(E1000_VFGPTLBC,
1785             hw_stats->last_gptlbc, hw_stats->gptlbc);
1786
1787         /* Good Tx loopback octets */
1788         UPDATE_VF_STAT(E1000_VFGOTLBC,
1789             hw_stats->last_gotlbc, hw_stats->gotlbc);
1790 }
1791
1792 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1793                                      struct rte_eth_xstat_name *xstats_names,
1794                                      __rte_unused unsigned limit)
1795 {
1796         unsigned i;
1797
1798         if (xstats_names != NULL)
1799                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1800                         snprintf(xstats_names[i].name,
1801                                 sizeof(xstats_names[i].name), "%s",
1802                                 rte_igbvf_stats_strings[i].name);
1803                         xstats_names[i].id = i;
1804                 }
1805         return IGBVF_NB_XSTATS;
1806 }
1807
1808 static int
1809 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1810                      unsigned n)
1811 {
1812         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1813         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1814                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1815         unsigned i;
1816
1817         if (n < IGBVF_NB_XSTATS)
1818                 return IGBVF_NB_XSTATS;
1819
1820         igbvf_read_stats_registers(hw, hw_stats);
1821
1822         if (!xstats)
1823                 return 0;
1824
1825         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1826                 xstats[i].id = i;
1827                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1828                         rte_igbvf_stats_strings[i].offset);
1829         }
1830
1831         return IGBVF_NB_XSTATS;
1832 }
1833
1834 static void
1835 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1836 {
1837         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1839                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1840
1841         igbvf_read_stats_registers(hw, hw_stats);
1842
1843         if (rte_stats == NULL)
1844                 return;
1845
1846         rte_stats->ipackets = hw_stats->gprc;
1847         rte_stats->ibytes = hw_stats->gorc;
1848         rte_stats->opackets = hw_stats->gptc;
1849         rte_stats->obytes = hw_stats->gotc;
1850 }
1851
1852 static void
1853 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1854 {
1855         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1856                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1857
1858         /* Sync HW register to the last stats */
1859         eth_igbvf_stats_get(dev, NULL);
1860
1861         /* reset HW current stats*/
1862         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1863                offsetof(struct e1000_vf_stats, gprc));
1864 }
1865
1866 static void
1867 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1868 {
1869         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870
1871         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1872         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1873         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1874         dev_info->rx_offload_capa =
1875                 DEV_RX_OFFLOAD_VLAN_STRIP |
1876                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1877                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1878                 DEV_RX_OFFLOAD_TCP_CKSUM;
1879         dev_info->tx_offload_capa =
1880                 DEV_TX_OFFLOAD_VLAN_INSERT |
1881                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1882                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1883                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1884                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1885                 DEV_TX_OFFLOAD_TCP_TSO;
1886
1887         switch (hw->mac.type) {
1888         case e1000_82575:
1889                 dev_info->max_rx_queues = 4;
1890                 dev_info->max_tx_queues = 4;
1891                 dev_info->max_vmdq_pools = 0;
1892                 break;
1893
1894         case e1000_82576:
1895                 dev_info->max_rx_queues = 16;
1896                 dev_info->max_tx_queues = 16;
1897                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1898                 dev_info->vmdq_queue_num = 16;
1899                 break;
1900
1901         case e1000_82580:
1902                 dev_info->max_rx_queues = 8;
1903                 dev_info->max_tx_queues = 8;
1904                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1905                 dev_info->vmdq_queue_num = 8;
1906                 break;
1907
1908         case e1000_i350:
1909                 dev_info->max_rx_queues = 8;
1910                 dev_info->max_tx_queues = 8;
1911                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1912                 dev_info->vmdq_queue_num = 8;
1913                 break;
1914
1915         case e1000_i354:
1916                 dev_info->max_rx_queues = 8;
1917                 dev_info->max_tx_queues = 8;
1918                 break;
1919
1920         case e1000_i210:
1921                 dev_info->max_rx_queues = 4;
1922                 dev_info->max_tx_queues = 4;
1923                 dev_info->max_vmdq_pools = 0;
1924                 break;
1925
1926         case e1000_i211:
1927                 dev_info->max_rx_queues = 2;
1928                 dev_info->max_tx_queues = 2;
1929                 dev_info->max_vmdq_pools = 0;
1930                 break;
1931
1932         default:
1933                 /* Should not happen */
1934                 break;
1935         }
1936         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1937         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1938         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1939
1940         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1941                 .rx_thresh = {
1942                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1943                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1944                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1945                 },
1946                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1947                 .rx_drop_en = 0,
1948         };
1949
1950         dev_info->default_txconf = (struct rte_eth_txconf) {
1951                 .tx_thresh = {
1952                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1953                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1954                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1955                 },
1956                 .txq_flags = 0,
1957         };
1958
1959         dev_info->rx_desc_lim = rx_desc_lim;
1960         dev_info->tx_desc_lim = tx_desc_lim;
1961
1962         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1963                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1964                         ETH_LINK_SPEED_1G;
1965 }
1966
1967 static const uint32_t *
1968 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
1969 {
1970         static const uint32_t ptypes[] = {
1971                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
1972                 RTE_PTYPE_L2_ETHER,
1973                 RTE_PTYPE_L3_IPV4,
1974                 RTE_PTYPE_L3_IPV4_EXT,
1975                 RTE_PTYPE_L3_IPV6,
1976                 RTE_PTYPE_L3_IPV6_EXT,
1977                 RTE_PTYPE_L4_TCP,
1978                 RTE_PTYPE_L4_UDP,
1979                 RTE_PTYPE_L4_SCTP,
1980                 RTE_PTYPE_TUNNEL_IP,
1981                 RTE_PTYPE_INNER_L3_IPV6,
1982                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1983                 RTE_PTYPE_INNER_L4_TCP,
1984                 RTE_PTYPE_INNER_L4_UDP,
1985                 RTE_PTYPE_UNKNOWN
1986         };
1987
1988         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
1989             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
1990                 return ptypes;
1991         return NULL;
1992 }
1993
1994 static void
1995 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1996 {
1997         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998
1999         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2000         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2001         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2002         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2003                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2004                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2005                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2006         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2007                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2008                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2009                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2010                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2011                                 DEV_TX_OFFLOAD_TCP_TSO;
2012         switch (hw->mac.type) {
2013         case e1000_vfadapt:
2014                 dev_info->max_rx_queues = 2;
2015                 dev_info->max_tx_queues = 2;
2016                 break;
2017         case e1000_vfadapt_i350:
2018                 dev_info->max_rx_queues = 1;
2019                 dev_info->max_tx_queues = 1;
2020                 break;
2021         default:
2022                 /* Should not happen */
2023                 break;
2024         }
2025
2026         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2027                 .rx_thresh = {
2028                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2029                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2030                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2031                 },
2032                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2033                 .rx_drop_en = 0,
2034         };
2035
2036         dev_info->default_txconf = (struct rte_eth_txconf) {
2037                 .tx_thresh = {
2038                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2039                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2040                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2041                 },
2042                 .txq_flags = 0,
2043         };
2044
2045         dev_info->rx_desc_lim = rx_desc_lim;
2046         dev_info->tx_desc_lim = tx_desc_lim;
2047 }
2048
2049 /* return 0 means link status changed, -1 means not changed */
2050 static int
2051 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2052 {
2053         struct e1000_hw *hw =
2054                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         struct rte_eth_link link, old;
2056         int link_check, count;
2057
2058         link_check = 0;
2059         hw->mac.get_link_status = 1;
2060
2061         /* possible wait-to-complete in up to 9 seconds */
2062         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2063                 /* Read the real link status */
2064                 switch (hw->phy.media_type) {
2065                 case e1000_media_type_copper:
2066                         /* Do the work to read phy */
2067                         e1000_check_for_link(hw);
2068                         link_check = !hw->mac.get_link_status;
2069                         break;
2070
2071                 case e1000_media_type_fiber:
2072                         e1000_check_for_link(hw);
2073                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2074                                       E1000_STATUS_LU);
2075                         break;
2076
2077                 case e1000_media_type_internal_serdes:
2078                         e1000_check_for_link(hw);
2079                         link_check = hw->mac.serdes_has_link;
2080                         break;
2081
2082                 /* VF device is type_unknown */
2083                 case e1000_media_type_unknown:
2084                         eth_igbvf_link_update(hw);
2085                         link_check = !hw->mac.get_link_status;
2086                         break;
2087
2088                 default:
2089                         break;
2090                 }
2091                 if (link_check || wait_to_complete == 0)
2092                         break;
2093                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2094         }
2095         memset(&link, 0, sizeof(link));
2096         rte_igb_dev_atomic_read_link_status(dev, &link);
2097         old = link;
2098
2099         /* Now we check if a transition has happened */
2100         if (link_check) {
2101                 uint16_t duplex, speed;
2102                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2103                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2104                                 ETH_LINK_FULL_DUPLEX :
2105                                 ETH_LINK_HALF_DUPLEX;
2106                 link.link_speed = speed;
2107                 link.link_status = ETH_LINK_UP;
2108                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2109                                 ETH_LINK_SPEED_FIXED);
2110         } else if (!link_check) {
2111                 link.link_speed = 0;
2112                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2113                 link.link_status = ETH_LINK_DOWN;
2114                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2115         }
2116         rte_igb_dev_atomic_write_link_status(dev, &link);
2117
2118         /* not changed */
2119         if (old.link_status == link.link_status)
2120                 return -1;
2121
2122         /* changed */
2123         return 0;
2124 }
2125
2126 /*
2127  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2128  * For ASF and Pass Through versions of f/w this means
2129  * that the driver is loaded.
2130  */
2131 static void
2132 igb_hw_control_acquire(struct e1000_hw *hw)
2133 {
2134         uint32_t ctrl_ext;
2135
2136         /* Let firmware know the driver has taken over */
2137         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2138         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2139 }
2140
2141 /*
2142  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2143  * For ASF and Pass Through versions of f/w this means that the
2144  * driver is no longer loaded.
2145  */
2146 static void
2147 igb_hw_control_release(struct e1000_hw *hw)
2148 {
2149         uint32_t ctrl_ext;
2150
2151         /* Let firmware taken over control of h/w */
2152         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2153         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2154                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2155 }
2156
2157 /*
2158  * Bit of a misnomer, what this really means is
2159  * to enable OS management of the system... aka
2160  * to disable special hardware management features.
2161  */
2162 static void
2163 igb_init_manageability(struct e1000_hw *hw)
2164 {
2165         if (e1000_enable_mng_pass_thru(hw)) {
2166                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2167                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2168
2169                 /* disable hardware interception of ARP */
2170                 manc &= ~(E1000_MANC_ARP_EN);
2171
2172                 /* enable receiving management packets to the host */
2173                 manc |= E1000_MANC_EN_MNG2HOST;
2174                 manc2h |= 1 << 5;  /* Mng Port 623 */
2175                 manc2h |= 1 << 6;  /* Mng Port 664 */
2176                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2177                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2178         }
2179 }
2180
2181 static void
2182 igb_release_manageability(struct e1000_hw *hw)
2183 {
2184         if (e1000_enable_mng_pass_thru(hw)) {
2185                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2186
2187                 manc |= E1000_MANC_ARP_EN;
2188                 manc &= ~E1000_MANC_EN_MNG2HOST;
2189
2190                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2191         }
2192 }
2193
2194 static void
2195 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2196 {
2197         struct e1000_hw *hw =
2198                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2199         uint32_t rctl;
2200
2201         rctl = E1000_READ_REG(hw, E1000_RCTL);
2202         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2203         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2204 }
2205
2206 static void
2207 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2208 {
2209         struct e1000_hw *hw =
2210                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211         uint32_t rctl;
2212
2213         rctl = E1000_READ_REG(hw, E1000_RCTL);
2214         rctl &= (~E1000_RCTL_UPE);
2215         if (dev->data->all_multicast == 1)
2216                 rctl |= E1000_RCTL_MPE;
2217         else
2218                 rctl &= (~E1000_RCTL_MPE);
2219         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2220 }
2221
2222 static void
2223 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2224 {
2225         struct e1000_hw *hw =
2226                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227         uint32_t rctl;
2228
2229         rctl = E1000_READ_REG(hw, E1000_RCTL);
2230         rctl |= E1000_RCTL_MPE;
2231         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2232 }
2233
2234 static void
2235 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2236 {
2237         struct e1000_hw *hw =
2238                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239         uint32_t rctl;
2240
2241         if (dev->data->promiscuous == 1)
2242                 return; /* must remain in all_multicast mode */
2243         rctl = E1000_READ_REG(hw, E1000_RCTL);
2244         rctl &= (~E1000_RCTL_MPE);
2245         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2246 }
2247
2248 static int
2249 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2250 {
2251         struct e1000_hw *hw =
2252                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253         struct e1000_vfta * shadow_vfta =
2254                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2255         uint32_t vfta;
2256         uint32_t vid_idx;
2257         uint32_t vid_bit;
2258
2259         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2260                               E1000_VFTA_ENTRY_MASK);
2261         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2262         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2263         if (on)
2264                 vfta |= vid_bit;
2265         else
2266                 vfta &= ~vid_bit;
2267         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2268
2269         /* update local VFTA copy */
2270         shadow_vfta->vfta[vid_idx] = vfta;
2271
2272         return 0;
2273 }
2274
2275 static int
2276 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2277                       enum rte_vlan_type vlan_type,
2278                       uint16_t tpid)
2279 {
2280         struct e1000_hw *hw =
2281                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2282         uint32_t reg = ETHER_TYPE_VLAN;
2283         int ret = 0;
2284
2285         switch (vlan_type) {
2286         case ETH_VLAN_TYPE_INNER:
2287                 reg |= (tpid << 16);
2288                 E1000_WRITE_REG(hw, E1000_VET, reg);
2289                 break;
2290         default:
2291                 ret = -EINVAL;
2292                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
2293                 break;
2294         }
2295
2296         return ret;
2297 }
2298
2299 static void
2300 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2301 {
2302         struct e1000_hw *hw =
2303                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304         uint32_t reg;
2305
2306         /* Filter Table Disable */
2307         reg = E1000_READ_REG(hw, E1000_RCTL);
2308         reg &= ~E1000_RCTL_CFIEN;
2309         reg &= ~E1000_RCTL_VFE;
2310         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2311 }
2312
2313 static void
2314 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2315 {
2316         struct e1000_hw *hw =
2317                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2318         struct e1000_vfta * shadow_vfta =
2319                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2320         uint32_t reg;
2321         int i;
2322
2323         /* Filter Table Enable, CFI not used for packet acceptance */
2324         reg = E1000_READ_REG(hw, E1000_RCTL);
2325         reg &= ~E1000_RCTL_CFIEN;
2326         reg |= E1000_RCTL_VFE;
2327         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2328
2329         /* restore VFTA table */
2330         for (i = 0; i < IGB_VFTA_SIZE; i++)
2331                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2332 }
2333
2334 static void
2335 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2336 {
2337         struct e1000_hw *hw =
2338                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2339         uint32_t reg;
2340
2341         /* VLAN Mode Disable */
2342         reg = E1000_READ_REG(hw, E1000_CTRL);
2343         reg &= ~E1000_CTRL_VME;
2344         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2345 }
2346
2347 static void
2348 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2349 {
2350         struct e1000_hw *hw =
2351                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2352         uint32_t reg;
2353
2354         /* VLAN Mode Enable */
2355         reg = E1000_READ_REG(hw, E1000_CTRL);
2356         reg |= E1000_CTRL_VME;
2357         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2358 }
2359
2360 static void
2361 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2362 {
2363         struct e1000_hw *hw =
2364                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2365         uint32_t reg;
2366
2367         /* CTRL_EXT: Extended VLAN */
2368         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2369         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2370         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2371
2372         /* Update maximum packet length */
2373         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2374                 E1000_WRITE_REG(hw, E1000_RLPML,
2375                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2376                                                 VLAN_TAG_SIZE);
2377 }
2378
2379 static void
2380 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2381 {
2382         struct e1000_hw *hw =
2383                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384         uint32_t reg;
2385
2386         /* CTRL_EXT: Extended VLAN */
2387         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2388         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2389         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2390
2391         /* Update maximum packet length */
2392         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2393                 E1000_WRITE_REG(hw, E1000_RLPML,
2394                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2395                                                 2 * VLAN_TAG_SIZE);
2396 }
2397
2398 static void
2399 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2400 {
2401         if(mask & ETH_VLAN_STRIP_MASK){
2402                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2403                         igb_vlan_hw_strip_enable(dev);
2404                 else
2405                         igb_vlan_hw_strip_disable(dev);
2406         }
2407
2408         if(mask & ETH_VLAN_FILTER_MASK){
2409                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2410                         igb_vlan_hw_filter_enable(dev);
2411                 else
2412                         igb_vlan_hw_filter_disable(dev);
2413         }
2414
2415         if(mask & ETH_VLAN_EXTEND_MASK){
2416                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2417                         igb_vlan_hw_extend_enable(dev);
2418                 else
2419                         igb_vlan_hw_extend_disable(dev);
2420         }
2421 }
2422
2423
2424 /**
2425  * It enables the interrupt mask and then enable the interrupt.
2426  *
2427  * @param dev
2428  *  Pointer to struct rte_eth_dev.
2429  *
2430  * @return
2431  *  - On success, zero.
2432  *  - On failure, a negative value.
2433  */
2434 static int
2435 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2436 {
2437         struct e1000_interrupt *intr =
2438                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2439
2440         intr->mask |= E1000_ICR_LSC;
2441
2442         return 0;
2443 }
2444
2445 /* It clears the interrupt causes and enables the interrupt.
2446  * It will be called once only during nic initialized.
2447  *
2448  * @param dev
2449  *  Pointer to struct rte_eth_dev.
2450  *
2451  * @return
2452  *  - On success, zero.
2453  *  - On failure, a negative value.
2454  */
2455 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2456 {
2457         uint32_t mask, regval;
2458         struct e1000_hw *hw =
2459                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2460         struct rte_eth_dev_info dev_info;
2461
2462         memset(&dev_info, 0, sizeof(dev_info));
2463         eth_igb_infos_get(dev, &dev_info);
2464
2465         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2466         regval = E1000_READ_REG(hw, E1000_EIMS);
2467         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2468
2469         return 0;
2470 }
2471
2472 /*
2473  * It reads ICR and gets interrupt causes, check it and set a bit flag
2474  * to update link status.
2475  *
2476  * @param dev
2477  *  Pointer to struct rte_eth_dev.
2478  *
2479  * @return
2480  *  - On success, zero.
2481  *  - On failure, a negative value.
2482  */
2483 static int
2484 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2485 {
2486         uint32_t icr;
2487         struct e1000_hw *hw =
2488                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489         struct e1000_interrupt *intr =
2490                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2491
2492         igb_intr_disable(hw);
2493
2494         /* read-on-clear nic registers here */
2495         icr = E1000_READ_REG(hw, E1000_ICR);
2496
2497         intr->flags = 0;
2498         if (icr & E1000_ICR_LSC) {
2499                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2500         }
2501
2502         if (icr & E1000_ICR_VMMB)
2503                 intr->flags |= E1000_FLAG_MAILBOX;
2504
2505         return 0;
2506 }
2507
2508 /*
2509  * It executes link_update after knowing an interrupt is prsent.
2510  *
2511  * @param dev
2512  *  Pointer to struct rte_eth_dev.
2513  *
2514  * @return
2515  *  - On success, zero.
2516  *  - On failure, a negative value.
2517  */
2518 static int
2519 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2520 {
2521         struct e1000_hw *hw =
2522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         struct e1000_interrupt *intr =
2524                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2525         uint32_t tctl, rctl;
2526         struct rte_eth_link link;
2527         int ret;
2528
2529         if (intr->flags & E1000_FLAG_MAILBOX) {
2530                 igb_pf_mbx_process(dev);
2531                 intr->flags &= ~E1000_FLAG_MAILBOX;
2532         }
2533
2534         igb_intr_enable(dev);
2535         rte_intr_enable(&(dev->pci_dev->intr_handle));
2536
2537         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2538                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2539
2540                 /* set get_link_status to check register later */
2541                 hw->mac.get_link_status = 1;
2542                 ret = eth_igb_link_update(dev, 0);
2543
2544                 /* check if link has changed */
2545                 if (ret < 0)
2546                         return 0;
2547
2548                 memset(&link, 0, sizeof(link));
2549                 rte_igb_dev_atomic_read_link_status(dev, &link);
2550                 if (link.link_status) {
2551                         PMD_INIT_LOG(INFO,
2552                                      " Port %d: Link Up - speed %u Mbps - %s",
2553                                      dev->data->port_id,
2554                                      (unsigned)link.link_speed,
2555                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2556                                      "full-duplex" : "half-duplex");
2557                 } else {
2558                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2559                                      dev->data->port_id);
2560                 }
2561
2562                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2563                              dev->pci_dev->addr.domain,
2564                              dev->pci_dev->addr.bus,
2565                              dev->pci_dev->addr.devid,
2566                              dev->pci_dev->addr.function);
2567                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2568                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2569                 if (link.link_status) {
2570                         /* enable Tx/Rx */
2571                         tctl |= E1000_TCTL_EN;
2572                         rctl |= E1000_RCTL_EN;
2573                 } else {
2574                         /* disable Tx/Rx */
2575                         tctl &= ~E1000_TCTL_EN;
2576                         rctl &= ~E1000_RCTL_EN;
2577                 }
2578                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2579                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2580                 E1000_WRITE_FLUSH(hw);
2581                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2582         }
2583
2584         return 0;
2585 }
2586
2587 /**
2588  * Interrupt handler which shall be registered at first.
2589  *
2590  * @param handle
2591  *  Pointer to interrupt handle.
2592  * @param param
2593  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2594  *
2595  * @return
2596  *  void
2597  */
2598 static void
2599 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2600                                                         void *param)
2601 {
2602         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2603
2604         eth_igb_interrupt_get_status(dev);
2605         eth_igb_interrupt_action(dev);
2606 }
2607
2608 static int
2609 eth_igb_led_on(struct rte_eth_dev *dev)
2610 {
2611         struct e1000_hw *hw;
2612
2613         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2615 }
2616
2617 static int
2618 eth_igb_led_off(struct rte_eth_dev *dev)
2619 {
2620         struct e1000_hw *hw;
2621
2622         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2623         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2624 }
2625
2626 static int
2627 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2628 {
2629         struct e1000_hw *hw;
2630         uint32_t ctrl;
2631         int tx_pause;
2632         int rx_pause;
2633
2634         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2635         fc_conf->pause_time = hw->fc.pause_time;
2636         fc_conf->high_water = hw->fc.high_water;
2637         fc_conf->low_water = hw->fc.low_water;
2638         fc_conf->send_xon = hw->fc.send_xon;
2639         fc_conf->autoneg = hw->mac.autoneg;
2640
2641         /*
2642          * Return rx_pause and tx_pause status according to actual setting of
2643          * the TFCE and RFCE bits in the CTRL register.
2644          */
2645         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2646         if (ctrl & E1000_CTRL_TFCE)
2647                 tx_pause = 1;
2648         else
2649                 tx_pause = 0;
2650
2651         if (ctrl & E1000_CTRL_RFCE)
2652                 rx_pause = 1;
2653         else
2654                 rx_pause = 0;
2655
2656         if (rx_pause && tx_pause)
2657                 fc_conf->mode = RTE_FC_FULL;
2658         else if (rx_pause)
2659                 fc_conf->mode = RTE_FC_RX_PAUSE;
2660         else if (tx_pause)
2661                 fc_conf->mode = RTE_FC_TX_PAUSE;
2662         else
2663                 fc_conf->mode = RTE_FC_NONE;
2664
2665         return 0;
2666 }
2667
2668 static int
2669 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2670 {
2671         struct e1000_hw *hw;
2672         int err;
2673         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2674                 e1000_fc_none,
2675                 e1000_fc_rx_pause,
2676                 e1000_fc_tx_pause,
2677                 e1000_fc_full
2678         };
2679         uint32_t rx_buf_size;
2680         uint32_t max_high_water;
2681         uint32_t rctl;
2682
2683         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684         if (fc_conf->autoneg != hw->mac.autoneg)
2685                 return -ENOTSUP;
2686         rx_buf_size = igb_get_rx_buffer_size(hw);
2687         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2688
2689         /* At least reserve one Ethernet frame for watermark */
2690         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2691         if ((fc_conf->high_water > max_high_water) ||
2692             (fc_conf->high_water < fc_conf->low_water)) {
2693                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2694                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2695                 return -EINVAL;
2696         }
2697
2698         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2699         hw->fc.pause_time     = fc_conf->pause_time;
2700         hw->fc.high_water     = fc_conf->high_water;
2701         hw->fc.low_water      = fc_conf->low_water;
2702         hw->fc.send_xon       = fc_conf->send_xon;
2703
2704         err = e1000_setup_link_generic(hw);
2705         if (err == E1000_SUCCESS) {
2706
2707                 /* check if we want to forward MAC frames - driver doesn't have native
2708                  * capability to do that, so we'll write the registers ourselves */
2709
2710                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2711
2712                 /* set or clear MFLCN.PMCF bit depending on configuration */
2713                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2714                         rctl |= E1000_RCTL_PMCF;
2715                 else
2716                         rctl &= ~E1000_RCTL_PMCF;
2717
2718                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2719                 E1000_WRITE_FLUSH(hw);
2720
2721                 return 0;
2722         }
2723
2724         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2725         return -EIO;
2726 }
2727
2728 #define E1000_RAH_POOLSEL_SHIFT      (18)
2729 static void
2730 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2731                 uint32_t index, __rte_unused uint32_t pool)
2732 {
2733         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734         uint32_t rah;
2735
2736         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2737         rah = E1000_READ_REG(hw, E1000_RAH(index));
2738         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2739         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2740 }
2741
2742 static void
2743 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2744 {
2745         uint8_t addr[ETHER_ADDR_LEN];
2746         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2747
2748         memset(addr, 0, sizeof(addr));
2749
2750         e1000_rar_set(hw, addr, index);
2751 }
2752
2753 static void
2754 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2755                                 struct ether_addr *addr)
2756 {
2757         eth_igb_rar_clear(dev, 0);
2758
2759         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2760 }
2761 /*
2762  * Virtual Function operations
2763  */
2764 static void
2765 igbvf_intr_disable(struct e1000_hw *hw)
2766 {
2767         PMD_INIT_FUNC_TRACE();
2768
2769         /* Clear interrupt mask to stop from interrupts being generated */
2770         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2771
2772         E1000_WRITE_FLUSH(hw);
2773 }
2774
2775 static void
2776 igbvf_stop_adapter(struct rte_eth_dev *dev)
2777 {
2778         u32 reg_val;
2779         u16 i;
2780         struct rte_eth_dev_info dev_info;
2781         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782
2783         memset(&dev_info, 0, sizeof(dev_info));
2784         eth_igbvf_infos_get(dev, &dev_info);
2785
2786         /* Clear interrupt mask to stop from interrupts being generated */
2787         igbvf_intr_disable(hw);
2788
2789         /* Clear any pending interrupts, flush previous writes */
2790         E1000_READ_REG(hw, E1000_EICR);
2791
2792         /* Disable the transmit unit.  Each queue must be disabled. */
2793         for (i = 0; i < dev_info.max_tx_queues; i++)
2794                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2795
2796         /* Disable the receive unit by stopping each queue */
2797         for (i = 0; i < dev_info.max_rx_queues; i++) {
2798                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2799                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2800                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2801                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2802                         ;
2803         }
2804
2805         /* flush all queues disables */
2806         E1000_WRITE_FLUSH(hw);
2807         msec_delay(2);
2808 }
2809
2810 static int eth_igbvf_link_update(struct e1000_hw *hw)
2811 {
2812         struct e1000_mbx_info *mbx = &hw->mbx;
2813         struct e1000_mac_info *mac = &hw->mac;
2814         int ret_val = E1000_SUCCESS;
2815
2816         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2817
2818         /*
2819          * We only want to run this if there has been a rst asserted.
2820          * in this case that could mean a link change, device reset,
2821          * or a virtual function reset
2822          */
2823
2824         /* If we were hit with a reset or timeout drop the link */
2825         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2826                 mac->get_link_status = TRUE;
2827
2828         if (!mac->get_link_status)
2829                 goto out;
2830
2831         /* if link status is down no point in checking to see if pf is up */
2832         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2833                 goto out;
2834
2835         /* if we passed all the tests above then the link is up and we no
2836          * longer need to check for link */
2837         mac->get_link_status = FALSE;
2838
2839 out:
2840         return ret_val;
2841 }
2842
2843
2844 static int
2845 igbvf_dev_configure(struct rte_eth_dev *dev)
2846 {
2847         struct rte_eth_conf* conf = &dev->data->dev_conf;
2848
2849         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2850                      dev->data->port_id);
2851
2852         /*
2853          * VF has no ability to enable/disable HW CRC
2854          * Keep the persistent behavior the same as Host PF
2855          */
2856 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2857         if (!conf->rxmode.hw_strip_crc) {
2858                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2859                 conf->rxmode.hw_strip_crc = 1;
2860         }
2861 #else
2862         if (conf->rxmode.hw_strip_crc) {
2863                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2864                 conf->rxmode.hw_strip_crc = 0;
2865         }
2866 #endif
2867
2868         return 0;
2869 }
2870
2871 static int
2872 igbvf_dev_start(struct rte_eth_dev *dev)
2873 {
2874         struct e1000_hw *hw =
2875                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         struct e1000_adapter *adapter =
2877                 E1000_DEV_PRIVATE(dev->data->dev_private);
2878         int ret;
2879
2880         PMD_INIT_FUNC_TRACE();
2881
2882         hw->mac.ops.reset_hw(hw);
2883         adapter->stopped = 0;
2884
2885         /* Set all vfta */
2886         igbvf_set_vfta_all(dev,1);
2887
2888         eth_igbvf_tx_init(dev);
2889
2890         /* This can fail when allocating mbufs for descriptor rings */
2891         ret = eth_igbvf_rx_init(dev);
2892         if (ret) {
2893                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2894                 igb_dev_clear_queues(dev);
2895                 return ret;
2896         }
2897
2898         return 0;
2899 }
2900
2901 static void
2902 igbvf_dev_stop(struct rte_eth_dev *dev)
2903 {
2904         PMD_INIT_FUNC_TRACE();
2905
2906         igbvf_stop_adapter(dev);
2907
2908         /*
2909           * Clear what we set, but we still keep shadow_vfta to
2910           * restore after device starts
2911           */
2912         igbvf_set_vfta_all(dev,0);
2913
2914         igb_dev_clear_queues(dev);
2915 }
2916
2917 static void
2918 igbvf_dev_close(struct rte_eth_dev *dev)
2919 {
2920         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921         struct e1000_adapter *adapter =
2922                 E1000_DEV_PRIVATE(dev->data->dev_private);
2923         struct ether_addr addr;
2924
2925         PMD_INIT_FUNC_TRACE();
2926
2927         e1000_reset_hw(hw);
2928
2929         igbvf_dev_stop(dev);
2930         adapter->stopped = 1;
2931         igb_dev_free_queues(dev);
2932
2933         /**
2934          * reprogram the RAR with a zero mac address,
2935          * to ensure that the VF traffic goes to the PF
2936          * after stop, close and detach of the VF.
2937          **/
2938
2939         memset(&addr, 0, sizeof(addr));
2940         igbvf_default_mac_addr_set(dev, &addr);
2941 }
2942
2943 static void
2944 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
2945 {
2946         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947
2948         /* Set both unicast and multicast promisc */
2949         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
2950 }
2951
2952 static void
2953 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
2954 {
2955         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2956
2957         /* If in allmulticast mode leave multicast promisc */
2958         if (dev->data->all_multicast == 1)
2959                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2960         else
2961                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2962 }
2963
2964 static void
2965 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
2966 {
2967         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968
2969         /* In promiscuous mode multicast promisc already set */
2970         if (dev->data->promiscuous == 0)
2971                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2972 }
2973
2974 static void
2975 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
2976 {
2977         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2978
2979         /* In promiscuous mode leave multicast promisc enabled */
2980         if (dev->data->promiscuous == 0)
2981                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2982 }
2983
2984 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2985 {
2986         struct e1000_mbx_info *mbx = &hw->mbx;
2987         uint32_t msgbuf[2];
2988         s32 err;
2989
2990         /* After set vlan, vlan strip will also be enabled in igb driver*/
2991         msgbuf[0] = E1000_VF_SET_VLAN;
2992         msgbuf[1] = vid;
2993         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2994         if (on)
2995                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2996
2997         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2998         if (err)
2999                 goto mbx_err;
3000
3001         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3002         if (err)
3003                 goto mbx_err;
3004
3005         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3006         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3007                 err = -EINVAL;
3008
3009 mbx_err:
3010         return err;
3011 }
3012
3013 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3014 {
3015         struct e1000_hw *hw =
3016                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017         struct e1000_vfta * shadow_vfta =
3018                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3019         int i = 0, j = 0, vfta = 0, mask = 1;
3020
3021         for (i = 0; i < IGB_VFTA_SIZE; i++){
3022                 vfta = shadow_vfta->vfta[i];
3023                 if(vfta){
3024                         mask = 1;
3025                         for (j = 0; j < 32; j++){
3026                                 if(vfta & mask)
3027                                         igbvf_set_vfta(hw,
3028                                                 (uint16_t)((i<<5)+j), on);
3029                                 mask<<=1;
3030                         }
3031                 }
3032         }
3033
3034 }
3035
3036 static int
3037 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3038 {
3039         struct e1000_hw *hw =
3040                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3041         struct e1000_vfta * shadow_vfta =
3042                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3043         uint32_t vid_idx = 0;
3044         uint32_t vid_bit = 0;
3045         int ret = 0;
3046
3047         PMD_INIT_FUNC_TRACE();
3048
3049         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3050         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3051         if(ret){
3052                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3053                 return ret;
3054         }
3055         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3056         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3057
3058         /*Save what we set and retore it after device reset*/
3059         if (on)
3060                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3061         else
3062                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3063
3064         return 0;
3065 }
3066
3067 static void
3068 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3069 {
3070         struct e1000_hw *hw =
3071                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072
3073         /* index is not used by rar_set() */
3074         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3075 }
3076
3077
3078 static int
3079 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3080                         struct rte_eth_rss_reta_entry64 *reta_conf,
3081                         uint16_t reta_size)
3082 {
3083         uint8_t i, j, mask;
3084         uint32_t reta, r;
3085         uint16_t idx, shift;
3086         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3087
3088         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3089                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3090                         "(%d) doesn't match the number hardware can supported "
3091                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3092                 return -EINVAL;
3093         }
3094
3095         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3096                 idx = i / RTE_RETA_GROUP_SIZE;
3097                 shift = i % RTE_RETA_GROUP_SIZE;
3098                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3099                                                 IGB_4_BIT_MASK);
3100                 if (!mask)
3101                         continue;
3102                 if (mask == IGB_4_BIT_MASK)
3103                         r = 0;
3104                 else
3105                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3106                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3107                         if (mask & (0x1 << j))
3108                                 reta |= reta_conf[idx].reta[shift + j] <<
3109                                                         (CHAR_BIT * j);
3110                         else
3111                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3112                 }
3113                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3114         }
3115
3116         return 0;
3117 }
3118
3119 static int
3120 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3121                        struct rte_eth_rss_reta_entry64 *reta_conf,
3122                        uint16_t reta_size)
3123 {
3124         uint8_t i, j, mask;
3125         uint32_t reta;
3126         uint16_t idx, shift;
3127         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3128
3129         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3130                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3131                         "(%d) doesn't match the number hardware can supported "
3132                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3133                 return -EINVAL;
3134         }
3135
3136         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3137                 idx = i / RTE_RETA_GROUP_SIZE;
3138                 shift = i % RTE_RETA_GROUP_SIZE;
3139                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3140                                                 IGB_4_BIT_MASK);
3141                 if (!mask)
3142                         continue;
3143                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3144                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3145                         if (mask & (0x1 << j))
3146                                 reta_conf[idx].reta[shift + j] =
3147                                         ((reta >> (CHAR_BIT * j)) &
3148                                                 IGB_8_BIT_MASK);
3149                 }
3150         }
3151
3152         return 0;
3153 }
3154
3155 #define MAC_TYPE_FILTER_SUP(type)    do {\
3156         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3157                 (type) != e1000_82576)\
3158                 return -ENOTSUP;\
3159 } while (0)
3160
3161 static int
3162 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3163                         struct rte_eth_syn_filter *filter,
3164                         bool add)
3165 {
3166         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167         uint32_t synqf, rfctl;
3168
3169         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3170                 return -EINVAL;
3171
3172         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3173
3174         if (add) {
3175                 if (synqf & E1000_SYN_FILTER_ENABLE)
3176                         return -EINVAL;
3177
3178                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3179                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3180
3181                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3182                 if (filter->hig_pri)
3183                         rfctl |= E1000_RFCTL_SYNQFP;
3184                 else
3185                         rfctl &= ~E1000_RFCTL_SYNQFP;
3186
3187                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3188         } else {
3189                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3190                         return -ENOENT;
3191                 synqf = 0;
3192         }
3193
3194         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3195         E1000_WRITE_FLUSH(hw);
3196         return 0;
3197 }
3198
3199 static int
3200 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3201                         struct rte_eth_syn_filter *filter)
3202 {
3203         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3204         uint32_t synqf, rfctl;
3205
3206         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3207         if (synqf & E1000_SYN_FILTER_ENABLE) {
3208                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3209                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3210                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3211                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3212                 return 0;
3213         }
3214
3215         return -ENOENT;
3216 }
3217
3218 static int
3219 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3220                         enum rte_filter_op filter_op,
3221                         void *arg)
3222 {
3223         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3224         int ret;
3225
3226         MAC_TYPE_FILTER_SUP(hw->mac.type);
3227
3228         if (filter_op == RTE_ETH_FILTER_NOP)
3229                 return 0;
3230
3231         if (arg == NULL) {
3232                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3233                             filter_op);
3234                 return -EINVAL;
3235         }
3236
3237         switch (filter_op) {
3238         case RTE_ETH_FILTER_ADD:
3239                 ret = eth_igb_syn_filter_set(dev,
3240                                 (struct rte_eth_syn_filter *)arg,
3241                                 TRUE);
3242                 break;
3243         case RTE_ETH_FILTER_DELETE:
3244                 ret = eth_igb_syn_filter_set(dev,
3245                                 (struct rte_eth_syn_filter *)arg,
3246                                 FALSE);
3247                 break;
3248         case RTE_ETH_FILTER_GET:
3249                 ret = eth_igb_syn_filter_get(dev,
3250                                 (struct rte_eth_syn_filter *)arg);
3251                 break;
3252         default:
3253                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3254                 ret = -EINVAL;
3255                 break;
3256         }
3257
3258         return ret;
3259 }
3260
3261 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3262         if ((type) != e1000_82580 && (type) != e1000_i350)\
3263                 return -ENOSYS; \
3264 } while (0)
3265
3266 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3267 static inline int
3268 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3269                         struct e1000_2tuple_filter_info *filter_info)
3270 {
3271         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3272                 return -EINVAL;
3273         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3274                 return -EINVAL;  /* filter index is out of range. */
3275         if (filter->tcp_flags > TCP_FLAG_ALL)
3276                 return -EINVAL;  /* flags is invalid. */
3277
3278         switch (filter->dst_port_mask) {
3279         case UINT16_MAX:
3280                 filter_info->dst_port_mask = 0;
3281                 filter_info->dst_port = filter->dst_port;
3282                 break;
3283         case 0:
3284                 filter_info->dst_port_mask = 1;
3285                 break;
3286         default:
3287                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3288                 return -EINVAL;
3289         }
3290
3291         switch (filter->proto_mask) {
3292         case UINT8_MAX:
3293                 filter_info->proto_mask = 0;
3294                 filter_info->proto = filter->proto;
3295                 break;
3296         case 0:
3297                 filter_info->proto_mask = 1;
3298                 break;
3299         default:
3300                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3301                 return -EINVAL;
3302         }
3303
3304         filter_info->priority = (uint8_t)filter->priority;
3305         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3306                 filter_info->tcp_flags = filter->tcp_flags;
3307         else
3308                 filter_info->tcp_flags = 0;
3309
3310         return 0;
3311 }
3312
3313 static inline struct e1000_2tuple_filter *
3314 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3315                         struct e1000_2tuple_filter_info *key)
3316 {
3317         struct e1000_2tuple_filter *it;
3318
3319         TAILQ_FOREACH(it, filter_list, entries) {
3320                 if (memcmp(key, &it->filter_info,
3321                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3322                         return it;
3323                 }
3324         }
3325         return NULL;
3326 }
3327
3328 /*
3329  * igb_add_2tuple_filter - add a 2tuple filter
3330  *
3331  * @param
3332  * dev: Pointer to struct rte_eth_dev.
3333  * ntuple_filter: ponter to the filter that will be added.
3334  *
3335  * @return
3336  *    - On success, zero.
3337  *    - On failure, a negative value.
3338  */
3339 static int
3340 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3341                         struct rte_eth_ntuple_filter *ntuple_filter)
3342 {
3343         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3344         struct e1000_filter_info *filter_info =
3345                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3346         struct e1000_2tuple_filter *filter;
3347         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3348         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3349         int i, ret;
3350
3351         filter = rte_zmalloc("e1000_2tuple_filter",
3352                         sizeof(struct e1000_2tuple_filter), 0);
3353         if (filter == NULL)
3354                 return -ENOMEM;
3355
3356         ret = ntuple_filter_to_2tuple(ntuple_filter,
3357                                       &filter->filter_info);
3358         if (ret < 0) {
3359                 rte_free(filter);
3360                 return ret;
3361         }
3362         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3363                                          &filter->filter_info) != NULL) {
3364                 PMD_DRV_LOG(ERR, "filter exists.");
3365                 rte_free(filter);
3366                 return -EEXIST;
3367         }
3368         filter->queue = ntuple_filter->queue;
3369
3370         /*
3371          * look for an unused 2tuple filter index,
3372          * and insert the filter to list.
3373          */
3374         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3375                 if (!(filter_info->twotuple_mask & (1 << i))) {
3376                         filter_info->twotuple_mask |= 1 << i;
3377                         filter->index = i;
3378                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3379                                           filter,
3380                                           entries);
3381                         break;
3382                 }
3383         }
3384         if (i >= E1000_MAX_TTQF_FILTERS) {
3385                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3386                 rte_free(filter);
3387                 return -ENOSYS;
3388         }
3389
3390         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3391         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3392                 imir |= E1000_IMIR_PORT_BP;
3393         else
3394                 imir &= ~E1000_IMIR_PORT_BP;
3395
3396         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3397
3398         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3399         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3400         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3401         if (filter->filter_info.proto_mask == 0)
3402                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3403
3404         /* tcp flags bits setting. */
3405         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3406                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3407                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3408                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3409                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3410                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3411                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3412                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3413                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3414                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3415                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3416                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3417                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3418         } else
3419                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3420         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3421         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3422         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3423         return 0;
3424 }
3425
3426 /*
3427  * igb_remove_2tuple_filter - remove a 2tuple filter
3428  *
3429  * @param
3430  * dev: Pointer to struct rte_eth_dev.
3431  * ntuple_filter: ponter to the filter that will be removed.
3432  *
3433  * @return
3434  *    - On success, zero.
3435  *    - On failure, a negative value.
3436  */
3437 static int
3438 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3439                         struct rte_eth_ntuple_filter *ntuple_filter)
3440 {
3441         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442         struct e1000_filter_info *filter_info =
3443                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3444         struct e1000_2tuple_filter_info filter_2tuple;
3445         struct e1000_2tuple_filter *filter;
3446         int ret;
3447
3448         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3449         ret = ntuple_filter_to_2tuple(ntuple_filter,
3450                                       &filter_2tuple);
3451         if (ret < 0)
3452                 return ret;
3453
3454         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3455                                          &filter_2tuple);
3456         if (filter == NULL) {
3457                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3458                 return -ENOENT;
3459         }
3460
3461         filter_info->twotuple_mask &= ~(1 << filter->index);
3462         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3463         rte_free(filter);
3464
3465         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3466         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3467         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3468         return 0;
3469 }
3470
3471 static inline struct e1000_flex_filter *
3472 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3473                         struct e1000_flex_filter_info *key)
3474 {
3475         struct e1000_flex_filter *it;
3476
3477         TAILQ_FOREACH(it, filter_list, entries) {
3478                 if (memcmp(key, &it->filter_info,
3479                         sizeof(struct e1000_flex_filter_info)) == 0)
3480                         return it;
3481         }
3482
3483         return NULL;
3484 }
3485
3486 static int
3487 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3488                         struct rte_eth_flex_filter *filter,
3489                         bool add)
3490 {
3491         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3492         struct e1000_filter_info *filter_info =
3493                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3494         struct e1000_flex_filter *flex_filter, *it;
3495         uint32_t wufc, queueing, mask;
3496         uint32_t reg_off;
3497         uint8_t shift, i, j = 0;
3498
3499         flex_filter = rte_zmalloc("e1000_flex_filter",
3500                         sizeof(struct e1000_flex_filter), 0);
3501         if (flex_filter == NULL)
3502                 return -ENOMEM;
3503
3504         flex_filter->filter_info.len = filter->len;
3505         flex_filter->filter_info.priority = filter->priority;
3506         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3507         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3508                 mask = 0;
3509                 /* reverse bits in flex filter's mask*/
3510                 for (shift = 0; shift < CHAR_BIT; shift++) {
3511                         if (filter->mask[i] & (0x01 << shift))
3512                                 mask |= (0x80 >> shift);
3513                 }
3514                 flex_filter->filter_info.mask[i] = mask;
3515         }
3516
3517         wufc = E1000_READ_REG(hw, E1000_WUFC);
3518         if (flex_filter->index < E1000_MAX_FHFT)
3519                 reg_off = E1000_FHFT(flex_filter->index);
3520         else
3521                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3522
3523         if (add) {
3524                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3525                                 &flex_filter->filter_info) != NULL) {
3526                         PMD_DRV_LOG(ERR, "filter exists.");
3527                         rte_free(flex_filter);
3528                         return -EEXIST;
3529                 }
3530                 flex_filter->queue = filter->queue;
3531                 /*
3532                  * look for an unused flex filter index
3533                  * and insert the filter into the list.
3534                  */
3535                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3536                         if (!(filter_info->flex_mask & (1 << i))) {
3537                                 filter_info->flex_mask |= 1 << i;
3538                                 flex_filter->index = i;
3539                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3540                                         flex_filter,
3541                                         entries);
3542                                 break;
3543                         }
3544                 }
3545                 if (i >= E1000_MAX_FLEX_FILTERS) {
3546                         PMD_DRV_LOG(ERR, "flex filters are full.");
3547                         rte_free(flex_filter);
3548                         return -ENOSYS;
3549                 }
3550
3551                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3552                                 (E1000_WUFC_FLX0 << flex_filter->index));
3553                 queueing = filter->len |
3554                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3555                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3556                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3557                                 queueing);
3558                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3559                         E1000_WRITE_REG(hw, reg_off,
3560                                         flex_filter->filter_info.dwords[j]);
3561                         reg_off += sizeof(uint32_t);
3562                         E1000_WRITE_REG(hw, reg_off,
3563                                         flex_filter->filter_info.dwords[++j]);
3564                         reg_off += sizeof(uint32_t);
3565                         E1000_WRITE_REG(hw, reg_off,
3566                                 (uint32_t)flex_filter->filter_info.mask[i]);
3567                         reg_off += sizeof(uint32_t) * 2;
3568                         ++j;
3569                 }
3570         } else {
3571                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3572                                 &flex_filter->filter_info);
3573                 if (it == NULL) {
3574                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3575                         rte_free(flex_filter);
3576                         return -ENOENT;
3577                 }
3578
3579                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3580                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3581                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3582                         (~(E1000_WUFC_FLX0 << it->index)));
3583
3584                 filter_info->flex_mask &= ~(1 << it->index);
3585                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3586                 rte_free(it);
3587                 rte_free(flex_filter);
3588         }
3589
3590         return 0;
3591 }
3592
3593 static int
3594 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3595                         struct rte_eth_flex_filter *filter)
3596 {
3597         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3598         struct e1000_filter_info *filter_info =
3599                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3600         struct e1000_flex_filter flex_filter, *it;
3601         uint32_t wufc, queueing, wufc_en = 0;
3602
3603         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3604         flex_filter.filter_info.len = filter->len;
3605         flex_filter.filter_info.priority = filter->priority;
3606         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3607         memcpy(flex_filter.filter_info.mask, filter->mask,
3608                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3609
3610         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3611                                 &flex_filter.filter_info);
3612         if (it == NULL) {
3613                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3614                 return -ENOENT;
3615         }
3616
3617         wufc = E1000_READ_REG(hw, E1000_WUFC);
3618         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3619
3620         if ((wufc & wufc_en) == wufc_en) {
3621                 uint32_t reg_off = 0;
3622                 if (it->index < E1000_MAX_FHFT)
3623                         reg_off = E1000_FHFT(it->index);
3624                 else
3625                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3626
3627                 queueing = E1000_READ_REG(hw,
3628                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3629                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3630                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3631                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3632                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3633                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3634                 return 0;
3635         }
3636         return -ENOENT;
3637 }
3638
3639 static int
3640 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3641                         enum rte_filter_op filter_op,
3642                         void *arg)
3643 {
3644         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645         struct rte_eth_flex_filter *filter;
3646         int ret = 0;
3647
3648         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3649
3650         if (filter_op == RTE_ETH_FILTER_NOP)
3651                 return ret;
3652
3653         if (arg == NULL) {
3654                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3655                             filter_op);
3656                 return -EINVAL;
3657         }
3658
3659         filter = (struct rte_eth_flex_filter *)arg;
3660         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3661             || filter->len % sizeof(uint64_t) != 0) {
3662                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3663                 return -EINVAL;
3664         }
3665         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3666                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3667                 return -EINVAL;
3668         }
3669
3670         switch (filter_op) {
3671         case RTE_ETH_FILTER_ADD:
3672                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3673                 break;
3674         case RTE_ETH_FILTER_DELETE:
3675                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3676                 break;
3677         case RTE_ETH_FILTER_GET:
3678                 ret = eth_igb_get_flex_filter(dev, filter);
3679                 break;
3680         default:
3681                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3682                 ret = -EINVAL;
3683                 break;
3684         }
3685
3686         return ret;
3687 }
3688
3689 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3690 static inline int
3691 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3692                         struct e1000_5tuple_filter_info *filter_info)
3693 {
3694         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3695                 return -EINVAL;
3696         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3697                 return -EINVAL;  /* filter index is out of range. */
3698         if (filter->tcp_flags > TCP_FLAG_ALL)
3699                 return -EINVAL;  /* flags is invalid. */
3700
3701         switch (filter->dst_ip_mask) {
3702         case UINT32_MAX:
3703                 filter_info->dst_ip_mask = 0;
3704                 filter_info->dst_ip = filter->dst_ip;
3705                 break;
3706         case 0:
3707                 filter_info->dst_ip_mask = 1;
3708                 break;
3709         default:
3710                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3711                 return -EINVAL;
3712         }
3713
3714         switch (filter->src_ip_mask) {
3715         case UINT32_MAX:
3716                 filter_info->src_ip_mask = 0;
3717                 filter_info->src_ip = filter->src_ip;
3718                 break;
3719         case 0:
3720                 filter_info->src_ip_mask = 1;
3721                 break;
3722         default:
3723                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3724                 return -EINVAL;
3725         }
3726
3727         switch (filter->dst_port_mask) {
3728         case UINT16_MAX:
3729                 filter_info->dst_port_mask = 0;
3730                 filter_info->dst_port = filter->dst_port;
3731                 break;
3732         case 0:
3733                 filter_info->dst_port_mask = 1;
3734                 break;
3735         default:
3736                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3737                 return -EINVAL;
3738         }
3739
3740         switch (filter->src_port_mask) {
3741         case UINT16_MAX:
3742                 filter_info->src_port_mask = 0;
3743                 filter_info->src_port = filter->src_port;
3744                 break;
3745         case 0:
3746                 filter_info->src_port_mask = 1;
3747                 break;
3748         default:
3749                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3750                 return -EINVAL;
3751         }
3752
3753         switch (filter->proto_mask) {
3754         case UINT8_MAX:
3755                 filter_info->proto_mask = 0;
3756                 filter_info->proto = filter->proto;
3757                 break;
3758         case 0:
3759                 filter_info->proto_mask = 1;
3760                 break;
3761         default:
3762                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3763                 return -EINVAL;
3764         }
3765
3766         filter_info->priority = (uint8_t)filter->priority;
3767         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3768                 filter_info->tcp_flags = filter->tcp_flags;
3769         else
3770                 filter_info->tcp_flags = 0;
3771
3772         return 0;
3773 }
3774
3775 static inline struct e1000_5tuple_filter *
3776 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3777                         struct e1000_5tuple_filter_info *key)
3778 {
3779         struct e1000_5tuple_filter *it;
3780
3781         TAILQ_FOREACH(it, filter_list, entries) {
3782                 if (memcmp(key, &it->filter_info,
3783                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3784                         return it;
3785                 }
3786         }
3787         return NULL;
3788 }
3789
3790 /*
3791  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3792  *
3793  * @param
3794  * dev: Pointer to struct rte_eth_dev.
3795  * ntuple_filter: ponter to the filter that will be added.
3796  *
3797  * @return
3798  *    - On success, zero.
3799  *    - On failure, a negative value.
3800  */
3801 static int
3802 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3803                         struct rte_eth_ntuple_filter *ntuple_filter)
3804 {
3805         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3806         struct e1000_filter_info *filter_info =
3807                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3808         struct e1000_5tuple_filter *filter;
3809         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3810         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3811         uint8_t i;
3812         int ret;
3813
3814         filter = rte_zmalloc("e1000_5tuple_filter",
3815                         sizeof(struct e1000_5tuple_filter), 0);
3816         if (filter == NULL)
3817                 return -ENOMEM;
3818
3819         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3820                                             &filter->filter_info);
3821         if (ret < 0) {
3822                 rte_free(filter);
3823                 return ret;
3824         }
3825
3826         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3827                                          &filter->filter_info) != NULL) {
3828                 PMD_DRV_LOG(ERR, "filter exists.");
3829                 rte_free(filter);
3830                 return -EEXIST;
3831         }
3832         filter->queue = ntuple_filter->queue;
3833
3834         /*
3835          * look for an unused 5tuple filter index,
3836          * and insert the filter to list.
3837          */
3838         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3839                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3840                         filter_info->fivetuple_mask |= 1 << i;
3841                         filter->index = i;
3842                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3843                                           filter,
3844                                           entries);
3845                         break;
3846                 }
3847         }
3848         if (i >= E1000_MAX_FTQF_FILTERS) {
3849                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3850                 rte_free(filter);
3851                 return -ENOSYS;
3852         }
3853
3854         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3855         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3856                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3857         if (filter->filter_info.dst_ip_mask == 0)
3858                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3859         if (filter->filter_info.src_port_mask == 0)
3860                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3861         if (filter->filter_info.proto_mask == 0)
3862                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3863         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3864                 E1000_FTQF_QUEUE_MASK;
3865         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3866         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3867         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3868         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3869
3870         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3871         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3872
3873         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3874         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3875                 imir |= E1000_IMIR_PORT_BP;
3876         else
3877                 imir &= ~E1000_IMIR_PORT_BP;
3878         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3879
3880         /* tcp flags bits setting. */
3881         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3882                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3883                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3884                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3885                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3886                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3887                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3888                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3889                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3890                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3891                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3892                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3893                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3894         } else
3895                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3896         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3897         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3898         return 0;
3899 }
3900
3901 /*
3902  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3903  *
3904  * @param
3905  * dev: Pointer to struct rte_eth_dev.
3906  * ntuple_filter: ponter to the filter that will be removed.
3907  *
3908  * @return
3909  *    - On success, zero.
3910  *    - On failure, a negative value.
3911  */
3912 static int
3913 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3914                                 struct rte_eth_ntuple_filter *ntuple_filter)
3915 {
3916         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917         struct e1000_filter_info *filter_info =
3918                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3919         struct e1000_5tuple_filter_info filter_5tuple;
3920         struct e1000_5tuple_filter *filter;
3921         int ret;
3922
3923         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3924         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3925                                             &filter_5tuple);
3926         if (ret < 0)
3927                 return ret;
3928
3929         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3930                                          &filter_5tuple);
3931         if (filter == NULL) {
3932                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3933                 return -ENOENT;
3934         }
3935
3936         filter_info->fivetuple_mask &= ~(1 << filter->index);
3937         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3938         rte_free(filter);
3939
3940         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3941                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3942         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3943         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3944         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3945         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3946         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3947         return 0;
3948 }
3949
3950 static int
3951 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3952 {
3953         uint32_t rctl;
3954         struct e1000_hw *hw;
3955         struct rte_eth_dev_info dev_info;
3956         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3957                                      VLAN_TAG_SIZE);
3958
3959         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3960
3961 #ifdef RTE_LIBRTE_82571_SUPPORT
3962         /* XXX: not bigger than max_rx_pktlen */
3963         if (hw->mac.type == e1000_82571)
3964                 return -ENOTSUP;
3965 #endif
3966         eth_igb_infos_get(dev, &dev_info);
3967
3968         /* check that mtu is within the allowed range */
3969         if ((mtu < ETHER_MIN_MTU) ||
3970             (frame_size > dev_info.max_rx_pktlen))
3971                 return -EINVAL;
3972
3973         /* refuse mtu that requires the support of scattered packets when this
3974          * feature has not been enabled before. */
3975         if (!dev->data->scattered_rx &&
3976             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3977                 return -EINVAL;
3978
3979         rctl = E1000_READ_REG(hw, E1000_RCTL);
3980
3981         /* switch to jumbo mode if needed */
3982         if (frame_size > ETHER_MAX_LEN) {
3983                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3984                 rctl |= E1000_RCTL_LPE;
3985         } else {
3986                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3987                 rctl &= ~E1000_RCTL_LPE;
3988         }
3989         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3990
3991         /* update max frame size */
3992         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3993
3994         E1000_WRITE_REG(hw, E1000_RLPML,
3995                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3996
3997         return 0;
3998 }
3999
4000 /*
4001  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4002  *
4003  * @param
4004  * dev: Pointer to struct rte_eth_dev.
4005  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4006  * add: if true, add filter, if false, remove filter
4007  *
4008  * @return
4009  *    - On success, zero.
4010  *    - On failure, a negative value.
4011  */
4012 static int
4013 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4014                         struct rte_eth_ntuple_filter *ntuple_filter,
4015                         bool add)
4016 {
4017         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4018         int ret;
4019
4020         switch (ntuple_filter->flags) {
4021         case RTE_5TUPLE_FLAGS:
4022         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4023                 if (hw->mac.type != e1000_82576)
4024                         return -ENOTSUP;
4025                 if (add)
4026                         ret = igb_add_5tuple_filter_82576(dev,
4027                                                           ntuple_filter);
4028                 else
4029                         ret = igb_remove_5tuple_filter_82576(dev,
4030                                                              ntuple_filter);
4031                 break;
4032         case RTE_2TUPLE_FLAGS:
4033         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4034                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4035                         return -ENOTSUP;
4036                 if (add)
4037                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4038                 else
4039                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4040                 break;
4041         default:
4042                 ret = -EINVAL;
4043                 break;
4044         }
4045
4046         return ret;
4047 }
4048
4049 /*
4050  * igb_get_ntuple_filter - get a ntuple filter
4051  *
4052  * @param
4053  * dev: Pointer to struct rte_eth_dev.
4054  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4055  *
4056  * @return
4057  *    - On success, zero.
4058  *    - On failure, a negative value.
4059  */
4060 static int
4061 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4062                         struct rte_eth_ntuple_filter *ntuple_filter)
4063 {
4064         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065         struct e1000_filter_info *filter_info =
4066                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4067         struct e1000_5tuple_filter_info filter_5tuple;
4068         struct e1000_2tuple_filter_info filter_2tuple;
4069         struct e1000_5tuple_filter *p_5tuple_filter;
4070         struct e1000_2tuple_filter *p_2tuple_filter;
4071         int ret;
4072
4073         switch (ntuple_filter->flags) {
4074         case RTE_5TUPLE_FLAGS:
4075         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4076                 if (hw->mac.type != e1000_82576)
4077                         return -ENOTSUP;
4078                 memset(&filter_5tuple,
4079                         0,
4080                         sizeof(struct e1000_5tuple_filter_info));
4081                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4082                                                     &filter_5tuple);
4083                 if (ret < 0)
4084                         return ret;
4085                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4086                                         &filter_info->fivetuple_list,
4087                                         &filter_5tuple);
4088                 if (p_5tuple_filter == NULL) {
4089                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4090                         return -ENOENT;
4091                 }
4092                 ntuple_filter->queue = p_5tuple_filter->queue;
4093                 break;
4094         case RTE_2TUPLE_FLAGS:
4095         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4096                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4097                         return -ENOTSUP;
4098                 memset(&filter_2tuple,
4099                         0,
4100                         sizeof(struct e1000_2tuple_filter_info));
4101                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4102                 if (ret < 0)
4103                         return ret;
4104                 p_2tuple_filter = igb_2tuple_filter_lookup(
4105                                         &filter_info->twotuple_list,
4106                                         &filter_2tuple);
4107                 if (p_2tuple_filter == NULL) {
4108                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4109                         return -ENOENT;
4110                 }
4111                 ntuple_filter->queue = p_2tuple_filter->queue;
4112                 break;
4113         default:
4114                 ret = -EINVAL;
4115                 break;
4116         }
4117
4118         return 0;
4119 }
4120
4121 /*
4122  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4123  * @dev: pointer to rte_eth_dev structure
4124  * @filter_op:operation will be taken.
4125  * @arg: a pointer to specific structure corresponding to the filter_op
4126  */
4127 static int
4128 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4129                                 enum rte_filter_op filter_op,
4130                                 void *arg)
4131 {
4132         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4133         int ret;
4134
4135         MAC_TYPE_FILTER_SUP(hw->mac.type);
4136
4137         if (filter_op == RTE_ETH_FILTER_NOP)
4138                 return 0;
4139
4140         if (arg == NULL) {
4141                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4142                             filter_op);
4143                 return -EINVAL;
4144         }
4145
4146         switch (filter_op) {
4147         case RTE_ETH_FILTER_ADD:
4148                 ret = igb_add_del_ntuple_filter(dev,
4149                         (struct rte_eth_ntuple_filter *)arg,
4150                         TRUE);
4151                 break;
4152         case RTE_ETH_FILTER_DELETE:
4153                 ret = igb_add_del_ntuple_filter(dev,
4154                         (struct rte_eth_ntuple_filter *)arg,
4155                         FALSE);
4156                 break;
4157         case RTE_ETH_FILTER_GET:
4158                 ret = igb_get_ntuple_filter(dev,
4159                         (struct rte_eth_ntuple_filter *)arg);
4160                 break;
4161         default:
4162                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4163                 ret = -EINVAL;
4164                 break;
4165         }
4166         return ret;
4167 }
4168
4169 static inline int
4170 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4171                         uint16_t ethertype)
4172 {
4173         int i;
4174
4175         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4176                 if (filter_info->ethertype_filters[i] == ethertype &&
4177                     (filter_info->ethertype_mask & (1 << i)))
4178                         return i;
4179         }
4180         return -1;
4181 }
4182
4183 static inline int
4184 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4185                         uint16_t ethertype)
4186 {
4187         int i;
4188
4189         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4190                 if (!(filter_info->ethertype_mask & (1 << i))) {
4191                         filter_info->ethertype_mask |= 1 << i;
4192                         filter_info->ethertype_filters[i] = ethertype;
4193                         return i;
4194                 }
4195         }
4196         return -1;
4197 }
4198
4199 static inline int
4200 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4201                         uint8_t idx)
4202 {
4203         if (idx >= E1000_MAX_ETQF_FILTERS)
4204                 return -1;
4205         filter_info->ethertype_mask &= ~(1 << idx);
4206         filter_info->ethertype_filters[idx] = 0;
4207         return idx;
4208 }
4209
4210
4211 static int
4212 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4213                         struct rte_eth_ethertype_filter *filter,
4214                         bool add)
4215 {
4216         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4217         struct e1000_filter_info *filter_info =
4218                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4219         uint32_t etqf = 0;
4220         int ret;
4221
4222         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4223                 filter->ether_type == ETHER_TYPE_IPv6) {
4224                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4225                         " ethertype filter.", filter->ether_type);
4226                 return -EINVAL;
4227         }
4228
4229         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4230                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4231                 return -EINVAL;
4232         }
4233         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4234                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4235                 return -EINVAL;
4236         }
4237
4238         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4239         if (ret >= 0 && add) {
4240                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4241                             filter->ether_type);
4242                 return -EEXIST;
4243         }
4244         if (ret < 0 && !add) {
4245                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4246                             filter->ether_type);
4247                 return -ENOENT;
4248         }
4249
4250         if (add) {
4251                 ret = igb_ethertype_filter_insert(filter_info,
4252                         filter->ether_type);
4253                 if (ret < 0) {
4254                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4255                         return -ENOSYS;
4256                 }
4257
4258                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4259                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4260                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4261         } else {
4262                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4263                 if (ret < 0)
4264                         return -ENOSYS;
4265         }
4266         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4267         E1000_WRITE_FLUSH(hw);
4268
4269         return 0;
4270 }
4271
4272 static int
4273 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4274                         struct rte_eth_ethertype_filter *filter)
4275 {
4276         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4277         struct e1000_filter_info *filter_info =
4278                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4279         uint32_t etqf;
4280         int ret;
4281
4282         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4283         if (ret < 0) {
4284                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4285                             filter->ether_type);
4286                 return -ENOENT;
4287         }
4288
4289         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4290         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4291                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4292                 filter->flags = 0;
4293                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4294                                 E1000_ETQF_QUEUE_SHIFT;
4295                 return 0;
4296         }
4297
4298         return -ENOENT;
4299 }
4300
4301 /*
4302  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4303  * @dev: pointer to rte_eth_dev structure
4304  * @filter_op:operation will be taken.
4305  * @arg: a pointer to specific structure corresponding to the filter_op
4306  */
4307 static int
4308 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4309                                 enum rte_filter_op filter_op,
4310                                 void *arg)
4311 {
4312         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4313         int ret;
4314
4315         MAC_TYPE_FILTER_SUP(hw->mac.type);
4316
4317         if (filter_op == RTE_ETH_FILTER_NOP)
4318                 return 0;
4319
4320         if (arg == NULL) {
4321                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4322                             filter_op);
4323                 return -EINVAL;
4324         }
4325
4326         switch (filter_op) {
4327         case RTE_ETH_FILTER_ADD:
4328                 ret = igb_add_del_ethertype_filter(dev,
4329                         (struct rte_eth_ethertype_filter *)arg,
4330                         TRUE);
4331                 break;
4332         case RTE_ETH_FILTER_DELETE:
4333                 ret = igb_add_del_ethertype_filter(dev,
4334                         (struct rte_eth_ethertype_filter *)arg,
4335                         FALSE);
4336                 break;
4337         case RTE_ETH_FILTER_GET:
4338                 ret = igb_get_ethertype_filter(dev,
4339                         (struct rte_eth_ethertype_filter *)arg);
4340                 break;
4341         default:
4342                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4343                 ret = -EINVAL;
4344                 break;
4345         }
4346         return ret;
4347 }
4348
4349 static int
4350 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4351                      enum rte_filter_type filter_type,
4352                      enum rte_filter_op filter_op,
4353                      void *arg)
4354 {
4355         int ret = -EINVAL;
4356
4357         switch (filter_type) {
4358         case RTE_ETH_FILTER_NTUPLE:
4359                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4360                 break;
4361         case RTE_ETH_FILTER_ETHERTYPE:
4362                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4363                 break;
4364         case RTE_ETH_FILTER_SYN:
4365                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4366                 break;
4367         case RTE_ETH_FILTER_FLEXIBLE:
4368                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4369                 break;
4370         default:
4371                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4372                                                         filter_type);
4373                 break;
4374         }
4375
4376         return ret;
4377 }
4378
4379 static int
4380 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4381                          struct ether_addr *mc_addr_set,
4382                          uint32_t nb_mc_addr)
4383 {
4384         struct e1000_hw *hw;
4385
4386         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4387         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4388         return 0;
4389 }
4390
4391 static uint64_t
4392 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4393 {
4394         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4395         uint64_t systime_cycles;
4396
4397         switch (hw->mac.type) {
4398         case e1000_i210:
4399         case e1000_i211:
4400                 /*
4401                  * Need to read System Time Residue Register to be able
4402                  * to read the other two registers.
4403                  */
4404                 E1000_READ_REG(hw, E1000_SYSTIMR);
4405                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4406                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4407                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4408                                 * NSEC_PER_SEC;
4409                 break;
4410         case e1000_82580:
4411         case e1000_i350:
4412         case e1000_i354:
4413                 /*
4414                  * Need to read System Time Residue Register to be able
4415                  * to read the other two registers.
4416                  */
4417                 E1000_READ_REG(hw, E1000_SYSTIMR);
4418                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4419                 /* Only the 8 LSB are valid. */
4420                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4421                                 & 0xff) << 32;
4422                 break;
4423         default:
4424                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4425                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4426                                 << 32;
4427                 break;
4428         }
4429
4430         return systime_cycles;
4431 }
4432
4433 static uint64_t
4434 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4435 {
4436         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4437         uint64_t rx_tstamp_cycles;
4438
4439         switch (hw->mac.type) {
4440         case e1000_i210:
4441         case e1000_i211:
4442                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4443                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4444                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4445                                 * NSEC_PER_SEC;
4446                 break;
4447         case e1000_82580:
4448         case e1000_i350:
4449         case e1000_i354:
4450                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4451                 /* Only the 8 LSB are valid. */
4452                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4453                                 & 0xff) << 32;
4454                 break;
4455         default:
4456                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4457                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4458                                 << 32;
4459                 break;
4460         }
4461
4462         return rx_tstamp_cycles;
4463 }
4464
4465 static uint64_t
4466 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4467 {
4468         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4469         uint64_t tx_tstamp_cycles;
4470
4471         switch (hw->mac.type) {
4472         case e1000_i210:
4473         case e1000_i211:
4474                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4475                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4476                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4477                                 * NSEC_PER_SEC;
4478                 break;
4479         case e1000_82580:
4480         case e1000_i350:
4481         case e1000_i354:
4482                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4483                 /* Only the 8 LSB are valid. */
4484                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4485                                 & 0xff) << 32;
4486                 break;
4487         default:
4488                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4489                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4490                                 << 32;
4491                 break;
4492         }
4493
4494         return tx_tstamp_cycles;
4495 }
4496
4497 static void
4498 igb_start_timecounters(struct rte_eth_dev *dev)
4499 {
4500         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4501         struct e1000_adapter *adapter =
4502                 (struct e1000_adapter *)dev->data->dev_private;
4503         uint32_t incval = 1;
4504         uint32_t shift = 0;
4505         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4506
4507         switch (hw->mac.type) {
4508         case e1000_82580:
4509         case e1000_i350:
4510         case e1000_i354:
4511                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4512                 mask = (1ULL << 40) - 1;
4513                 /* fall-through */
4514         case e1000_i210:
4515         case e1000_i211:
4516                 /*
4517                  * Start incrementing the register
4518                  * used to timestamp PTP packets.
4519                  */
4520                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4521                 break;
4522         case e1000_82576:
4523                 incval = E1000_INCVALUE_82576;
4524                 shift = IGB_82576_TSYNC_SHIFT;
4525                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4526                                 E1000_INCPERIOD_82576 | incval);
4527                 break;
4528         default:
4529                 /* Not supported */
4530                 return;
4531         }
4532
4533         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4534         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4535         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4536
4537         adapter->systime_tc.cc_mask = mask;
4538         adapter->systime_tc.cc_shift = shift;
4539         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4540
4541         adapter->rx_tstamp_tc.cc_mask = mask;
4542         adapter->rx_tstamp_tc.cc_shift = shift;
4543         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4544
4545         adapter->tx_tstamp_tc.cc_mask = mask;
4546         adapter->tx_tstamp_tc.cc_shift = shift;
4547         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4548 }
4549
4550 static int
4551 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4552 {
4553         struct e1000_adapter *adapter =
4554                         (struct e1000_adapter *)dev->data->dev_private;
4555
4556         adapter->systime_tc.nsec += delta;
4557         adapter->rx_tstamp_tc.nsec += delta;
4558         adapter->tx_tstamp_tc.nsec += delta;
4559
4560         return 0;
4561 }
4562
4563 static int
4564 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4565 {
4566         uint64_t ns;
4567         struct e1000_adapter *adapter =
4568                         (struct e1000_adapter *)dev->data->dev_private;
4569
4570         ns = rte_timespec_to_ns(ts);
4571
4572         /* Set the timecounters to a new value. */
4573         adapter->systime_tc.nsec = ns;
4574         adapter->rx_tstamp_tc.nsec = ns;
4575         adapter->tx_tstamp_tc.nsec = ns;
4576
4577         return 0;
4578 }
4579
4580 static int
4581 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4582 {
4583         uint64_t ns, systime_cycles;
4584         struct e1000_adapter *adapter =
4585                         (struct e1000_adapter *)dev->data->dev_private;
4586
4587         systime_cycles = igb_read_systime_cyclecounter(dev);
4588         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4589         *ts = rte_ns_to_timespec(ns);
4590
4591         return 0;
4592 }
4593
4594 static int
4595 igb_timesync_enable(struct rte_eth_dev *dev)
4596 {
4597         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4598         uint32_t tsync_ctl;
4599         uint32_t tsauxc;
4600
4601         /* Stop the timesync system time. */
4602         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4603         /* Reset the timesync system time value. */
4604         switch (hw->mac.type) {
4605         case e1000_82580:
4606         case e1000_i350:
4607         case e1000_i354:
4608         case e1000_i210:
4609         case e1000_i211:
4610                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4611                 /* fall-through */
4612         case e1000_82576:
4613                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4614                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4615                 break;
4616         default:
4617                 /* Not supported. */
4618                 return -ENOTSUP;
4619         }
4620
4621         /* Enable system time for it isn't on by default. */
4622         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4623         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4624         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4625
4626         igb_start_timecounters(dev);
4627
4628         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4629         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4630                         (ETHER_TYPE_1588 |
4631                          E1000_ETQF_FILTER_ENABLE |
4632                          E1000_ETQF_1588));
4633
4634         /* Enable timestamping of received PTP packets. */
4635         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4636         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4637         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4638
4639         /* Enable Timestamping of transmitted PTP packets. */
4640         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4641         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4642         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4643
4644         return 0;
4645 }
4646
4647 static int
4648 igb_timesync_disable(struct rte_eth_dev *dev)
4649 {
4650         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4651         uint32_t tsync_ctl;
4652
4653         /* Disable timestamping of transmitted PTP packets. */
4654         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4655         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4656         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4657
4658         /* Disable timestamping of received PTP packets. */
4659         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4660         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4661         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4662
4663         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4664         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4665
4666         /* Stop incrementating the System Time registers. */
4667         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4668
4669         return 0;
4670 }
4671
4672 static int
4673 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4674                                struct timespec *timestamp,
4675                                uint32_t flags __rte_unused)
4676 {
4677         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4678         struct e1000_adapter *adapter =
4679                         (struct e1000_adapter *)dev->data->dev_private;
4680         uint32_t tsync_rxctl;
4681         uint64_t rx_tstamp_cycles;
4682         uint64_t ns;
4683
4684         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4685         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4686                 return -EINVAL;
4687
4688         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4689         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4690         *timestamp = rte_ns_to_timespec(ns);
4691
4692         return  0;
4693 }
4694
4695 static int
4696 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4697                                struct timespec *timestamp)
4698 {
4699         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700         struct e1000_adapter *adapter =
4701                         (struct e1000_adapter *)dev->data->dev_private;
4702         uint32_t tsync_txctl;
4703         uint64_t tx_tstamp_cycles;
4704         uint64_t ns;
4705
4706         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4707         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4708                 return -EINVAL;
4709
4710         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4711         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4712         *timestamp = rte_ns_to_timespec(ns);
4713
4714         return  0;
4715 }
4716
4717 static int
4718 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4719 {
4720         int count = 0;
4721         int g_ind = 0;
4722         const struct reg_info *reg_group;
4723
4724         while ((reg_group = igb_regs[g_ind++]))
4725                 count += igb_reg_group_count(reg_group);
4726
4727         return count;
4728 }
4729
4730 static int
4731 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4732 {
4733         int count = 0;
4734         int g_ind = 0;
4735         const struct reg_info *reg_group;
4736
4737         while ((reg_group = igbvf_regs[g_ind++]))
4738                 count += igb_reg_group_count(reg_group);
4739
4740         return count;
4741 }
4742
4743 static int
4744 eth_igb_get_regs(struct rte_eth_dev *dev,
4745         struct rte_dev_reg_info *regs)
4746 {
4747         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4748         uint32_t *data = regs->data;
4749         int g_ind = 0;
4750         int count = 0;
4751         const struct reg_info *reg_group;
4752
4753         /* Support only full register dump */
4754         if ((regs->length == 0) ||
4755             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4756                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4757                         hw->device_id;
4758                 while ((reg_group = igb_regs[g_ind++]))
4759                         count += igb_read_regs_group(dev, &data[count],
4760                                                         reg_group);
4761                 return 0;
4762         }
4763
4764         return -ENOTSUP;
4765 }
4766
4767 static int
4768 igbvf_get_regs(struct rte_eth_dev *dev,
4769         struct rte_dev_reg_info *regs)
4770 {
4771         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4772         uint32_t *data = regs->data;
4773         int g_ind = 0;
4774         int count = 0;
4775         const struct reg_info *reg_group;
4776
4777         /* Support only full register dump */
4778         if ((regs->length == 0) ||
4779             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4780                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4781                         hw->device_id;
4782                 while ((reg_group = igbvf_regs[g_ind++]))
4783                         count += igb_read_regs_group(dev, &data[count],
4784                                                         reg_group);
4785                 return 0;
4786         }
4787
4788         return -ENOTSUP;
4789 }
4790
4791 static int
4792 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4793 {
4794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4795
4796         /* Return unit is byte count */
4797         return hw->nvm.word_size * 2;
4798 }
4799
4800 static int
4801 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4802         struct rte_dev_eeprom_info *in_eeprom)
4803 {
4804         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4805         struct e1000_nvm_info *nvm = &hw->nvm;
4806         uint16_t *data = in_eeprom->data;
4807         int first, length;
4808
4809         first = in_eeprom->offset >> 1;
4810         length = in_eeprom->length >> 1;
4811         if ((first >= hw->nvm.word_size) ||
4812             ((first + length) >= hw->nvm.word_size))
4813                 return -EINVAL;
4814
4815         in_eeprom->magic = hw->vendor_id |
4816                 ((uint32_t)hw->device_id << 16);
4817
4818         if ((nvm->ops.read) == NULL)
4819                 return -ENOTSUP;
4820
4821         return nvm->ops.read(hw, first, length, data);
4822 }
4823
4824 static int
4825 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4826         struct rte_dev_eeprom_info *in_eeprom)
4827 {
4828         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829         struct e1000_nvm_info *nvm = &hw->nvm;
4830         uint16_t *data = in_eeprom->data;
4831         int first, length;
4832
4833         first = in_eeprom->offset >> 1;
4834         length = in_eeprom->length >> 1;
4835         if ((first >= hw->nvm.word_size) ||
4836             ((first + length) >= hw->nvm.word_size))
4837                 return -EINVAL;
4838
4839         in_eeprom->magic = (uint32_t)hw->vendor_id |
4840                 ((uint32_t)hw->device_id << 16);
4841
4842         if ((nvm->ops.write) == NULL)
4843                 return -ENOTSUP;
4844         return nvm->ops.write(hw,  first, length, data);
4845 }
4846
4847 static struct rte_driver pmd_igb_drv = {
4848         .type = PMD_PDEV,
4849         .init = rte_igb_pmd_init,
4850 };
4851
4852 static struct rte_driver pmd_igbvf_drv = {
4853         .type = PMD_PDEV,
4854         .init = rte_igbvf_pmd_init,
4855 };
4856
4857 static int
4858 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4859 {
4860         struct e1000_hw *hw =
4861                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4862         uint32_t mask = 1 << queue_id;
4863
4864         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4865         E1000_WRITE_FLUSH(hw);
4866
4867         return 0;
4868 }
4869
4870 static int
4871 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4872 {
4873         struct e1000_hw *hw =
4874                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4875         uint32_t mask = 1 << queue_id;
4876         uint32_t regval;
4877
4878         regval = E1000_READ_REG(hw, E1000_EIMS);
4879         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4880         E1000_WRITE_FLUSH(hw);
4881
4882         rte_intr_enable(&dev->pci_dev->intr_handle);
4883
4884         return 0;
4885 }
4886
4887 static void
4888 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4889                    uint8_t index, uint8_t offset)
4890 {
4891         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4892
4893         /* clear bits */
4894         val &= ~((uint32_t)0xFF << offset);
4895
4896         /* write vector and valid bit */
4897         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4898
4899         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4900 }
4901
4902 static void
4903 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4904                            uint8_t queue, uint8_t msix_vector)
4905 {
4906         uint32_t tmp = 0;
4907
4908         if (hw->mac.type == e1000_82575) {
4909                 if (direction == 0)
4910                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4911                 else if (direction == 1)
4912                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4913                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4914         } else if (hw->mac.type == e1000_82576) {
4915                 if ((direction == 0) || (direction == 1))
4916                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4917                                            ((queue & 0x8) << 1) +
4918                                            8 * direction);
4919         } else if ((hw->mac.type == e1000_82580) ||
4920                         (hw->mac.type == e1000_i350) ||
4921                         (hw->mac.type == e1000_i354) ||
4922                         (hw->mac.type == e1000_i210) ||
4923                         (hw->mac.type == e1000_i211)) {
4924                 if ((direction == 0) || (direction == 1))
4925                         eth_igb_write_ivar(hw, msix_vector,
4926                                            queue >> 1,
4927                                            ((queue & 0x1) << 4) +
4928                                            8 * direction);
4929         }
4930 }
4931
4932 /* Sets up the hardware to generate MSI-X interrupts properly
4933  * @hw
4934  *  board private structure
4935  */
4936 static void
4937 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4938 {
4939         int queue_id;
4940         uint32_t tmpval, regval, intr_mask;
4941         struct e1000_hw *hw =
4942                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943         uint32_t vec = E1000_MISC_VEC_ID;
4944         uint32_t base = E1000_MISC_VEC_ID;
4945         uint32_t misc_shift = 0;
4946
4947         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4948
4949         /* won't configure msix register if no mapping is done
4950          * between intr vector and event fd
4951          */
4952         if (!rte_intr_dp_is_en(intr_handle))
4953                 return;
4954
4955         if (rte_intr_allow_others(intr_handle)) {
4956                 vec = base = E1000_RX_VEC_START;
4957                 misc_shift = 1;
4958         }
4959
4960         /* set interrupt vector for other causes */
4961         if (hw->mac.type == e1000_82575) {
4962                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4963                 /* enable MSI-X PBA support */
4964                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4965
4966                 /* Auto-Mask interrupts upon ICR read */
4967                 tmpval |= E1000_CTRL_EXT_EIAME;
4968                 tmpval |= E1000_CTRL_EXT_IRCA;
4969
4970                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4971
4972                 /* enable msix_other interrupt */
4973                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4974                 regval = E1000_READ_REG(hw, E1000_EIAC);
4975                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4976                 regval = E1000_READ_REG(hw, E1000_EIAM);
4977                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4978         } else if ((hw->mac.type == e1000_82576) ||
4979                         (hw->mac.type == e1000_82580) ||
4980                         (hw->mac.type == e1000_i350) ||
4981                         (hw->mac.type == e1000_i354) ||
4982                         (hw->mac.type == e1000_i210) ||
4983                         (hw->mac.type == e1000_i211)) {
4984                 /* turn on MSI-X capability first */
4985                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4986                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4987                                         E1000_GPIE_NSICR);
4988                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4989                         misc_shift;
4990                 regval = E1000_READ_REG(hw, E1000_EIAC);
4991                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4992
4993                 /* enable msix_other interrupt */
4994                 regval = E1000_READ_REG(hw, E1000_EIMS);
4995                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4996                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4997                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4998         }
4999
5000         /* use EIAM to auto-mask when MSI-X interrupt
5001          * is asserted, this saves a register write for every interrupt
5002          */
5003         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5004                 misc_shift;
5005         regval = E1000_READ_REG(hw, E1000_EIAM);
5006         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5007
5008         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5009                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5010                 intr_handle->intr_vec[queue_id] = vec;
5011                 if (vec < base + intr_handle->nb_efd - 1)
5012                         vec++;
5013         }
5014
5015         E1000_WRITE_FLUSH(hw);
5016 }
5017
5018 PMD_REGISTER_DRIVER(pmd_igb_drv);
5019 PMD_REGISTER_DRIVER(pmd_igbvf_drv);