1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
15 #include <rte_debug.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memory.h>
23 #include <rte_malloc.h>
26 #include "e1000_logs.h"
27 #include "base/e1000_api.h"
28 #include "e1000_ethdev.h"
32 * Default values for port configuration
34 #define IGB_DEFAULT_RX_FREE_THRESH 32
36 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
37 #define IGB_DEFAULT_RX_HTHRESH 8
38 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
40 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
41 #define IGB_DEFAULT_TX_HTHRESH 1
42 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
44 #define IGB_HKEY_MAX_INDEX 10
46 /* Bit shift and mask */
47 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
48 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
49 #define IGB_8_BIT_WIDTH CHAR_BIT
50 #define IGB_8_BIT_MASK UINT8_MAX
52 /* Additional timesync values. */
53 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
54 #define E1000_ETQF_FILTER_1588 3
55 #define IGB_82576_TSYNC_SHIFT 16
56 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
57 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
58 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
60 #define E1000_VTIVAR_MISC 0x01740
61 #define E1000_VTIVAR_MISC_MASK 0xFF
62 #define E1000_VTIVAR_VALID 0x80
63 #define E1000_VTIVAR_MISC_MAILBOX 0
64 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
66 /* External VLAN Enable bit mask */
67 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
69 /* External VLAN Ether Type bit mask and shift */
70 #define E1000_VET_VET_EXT 0xFFFF0000
71 #define E1000_VET_VET_EXT_SHIFT 16
73 static int eth_igb_configure(struct rte_eth_dev *dev);
74 static int eth_igb_start(struct rte_eth_dev *dev);
75 static void eth_igb_stop(struct rte_eth_dev *dev);
76 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
77 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
78 static void eth_igb_close(struct rte_eth_dev *dev);
79 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
80 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
81 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
82 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
83 static int eth_igb_link_update(struct rte_eth_dev *dev,
84 int wait_to_complete);
85 static int eth_igb_stats_get(struct rte_eth_dev *dev,
86 struct rte_eth_stats *rte_stats);
87 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
88 struct rte_eth_xstat *xstats, unsigned n);
89 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
91 uint64_t *values, unsigned int n);
92 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
93 struct rte_eth_xstat_name *xstats_names,
95 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
98 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
99 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
100 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
101 char *fw_version, size_t fw_size);
102 static void eth_igb_infos_get(struct rte_eth_dev *dev,
103 struct rte_eth_dev_info *dev_info);
104 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
105 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
108 struct rte_eth_fc_conf *fc_conf);
109 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
110 struct rte_eth_fc_conf *fc_conf);
111 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
112 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
113 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
114 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
115 struct rte_intr_handle *handle);
116 static void eth_igb_interrupt_handler(void *param);
117 static int igb_hardware_init(struct e1000_hw *hw);
118 static void igb_hw_control_acquire(struct e1000_hw *hw);
119 static void igb_hw_control_release(struct e1000_hw *hw);
120 static void igb_init_manageability(struct e1000_hw *hw);
121 static void igb_release_manageability(struct e1000_hw *hw);
123 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
126 uint16_t vlan_id, int on);
127 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
128 enum rte_vlan_type vlan_type,
130 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
132 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
133 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
134 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
135 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
139 static int eth_igb_led_on(struct rte_eth_dev *dev);
140 static int eth_igb_led_off(struct rte_eth_dev *dev);
142 static void igb_intr_disable(struct e1000_hw *hw);
143 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
144 static int eth_igb_rar_set(struct rte_eth_dev *dev,
145 struct ether_addr *mac_addr,
146 uint32_t index, uint32_t pool);
147 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
148 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
149 struct ether_addr *addr);
151 static void igbvf_intr_disable(struct e1000_hw *hw);
152 static int igbvf_dev_configure(struct rte_eth_dev *dev);
153 static int igbvf_dev_start(struct rte_eth_dev *dev);
154 static void igbvf_dev_stop(struct rte_eth_dev *dev);
155 static void igbvf_dev_close(struct rte_eth_dev *dev);
156 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
157 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
158 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
159 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
160 static int eth_igbvf_link_update(struct e1000_hw *hw);
161 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
162 struct rte_eth_stats *rte_stats);
163 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
164 struct rte_eth_xstat *xstats, unsigned n);
165 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
166 struct rte_eth_xstat_name *xstats_names,
168 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
169 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
170 uint16_t vlan_id, int on);
171 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
172 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
173 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
174 struct ether_addr *addr);
175 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
176 static int igbvf_get_regs(struct rte_eth_dev *dev,
177 struct rte_dev_reg_info *regs);
179 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
180 struct rte_eth_rss_reta_entry64 *reta_conf,
182 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
186 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
187 struct rte_eth_syn_filter *filter);
188 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
189 enum rte_filter_op filter_op,
191 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
194 struct rte_eth_ntuple_filter *ntuple_filter);
195 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
196 struct rte_eth_flex_filter *filter);
197 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
198 enum rte_filter_op filter_op,
200 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
201 struct rte_eth_ntuple_filter *ntuple_filter);
202 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
203 struct rte_eth_ntuple_filter *ntuple_filter);
204 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
205 struct rte_eth_ntuple_filter *filter);
206 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
207 enum rte_filter_op filter_op,
209 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
210 enum rte_filter_op filter_op,
212 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
213 struct rte_eth_ethertype_filter *filter);
214 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
215 enum rte_filter_type filter_type,
216 enum rte_filter_op filter_op,
218 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
219 static int eth_igb_get_regs(struct rte_eth_dev *dev,
220 struct rte_dev_reg_info *regs);
221 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
222 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
223 struct rte_dev_eeprom_info *eeprom);
224 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
225 struct rte_dev_eeprom_info *eeprom);
226 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
227 struct rte_eth_dev_module_info *modinfo);
228 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
229 struct rte_dev_eeprom_info *info);
230 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
231 struct ether_addr *mc_addr_set,
232 uint32_t nb_mc_addr);
233 static int igb_timesync_enable(struct rte_eth_dev *dev);
234 static int igb_timesync_disable(struct rte_eth_dev *dev);
235 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
236 struct timespec *timestamp,
238 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
239 struct timespec *timestamp);
240 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
241 static int igb_timesync_read_time(struct rte_eth_dev *dev,
242 struct timespec *timestamp);
243 static int igb_timesync_write_time(struct rte_eth_dev *dev,
244 const struct timespec *timestamp);
245 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
247 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
249 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
250 uint8_t queue, uint8_t msix_vector);
251 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
252 uint8_t index, uint8_t offset);
253 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
254 static void eth_igbvf_interrupt_handler(void *param);
255 static void igbvf_mbx_process(struct rte_eth_dev *dev);
256 static int igb_filter_restore(struct rte_eth_dev *dev);
259 * Define VF Stats MACRO for Non "cleared on read" register
261 #define UPDATE_VF_STAT(reg, last, cur) \
263 u32 latest = E1000_READ_REG(hw, reg); \
264 cur += (latest - last) & UINT_MAX; \
268 #define IGB_FC_PAUSE_TIME 0x0680
269 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
270 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
272 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
274 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
277 * The set of PCI devices this driver supports
279 static const struct rte_pci_id pci_id_igb_map[] = {
280 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
302 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
321 { .vendor_id = 0, /* sentinel */ },
325 * The set of PCI devices this driver supports (for 82576&I350 VF)
327 static const struct rte_pci_id pci_id_igbvf_map[] = {
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
332 { .vendor_id = 0, /* sentinel */ },
335 static const struct rte_eth_desc_lim rx_desc_lim = {
336 .nb_max = E1000_MAX_RING_DESC,
337 .nb_min = E1000_MIN_RING_DESC,
338 .nb_align = IGB_RXD_ALIGN,
341 static const struct rte_eth_desc_lim tx_desc_lim = {
342 .nb_max = E1000_MAX_RING_DESC,
343 .nb_min = E1000_MIN_RING_DESC,
344 .nb_align = IGB_RXD_ALIGN,
345 .nb_seg_max = IGB_TX_MAX_SEG,
346 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
349 static const struct eth_dev_ops eth_igb_ops = {
350 .dev_configure = eth_igb_configure,
351 .dev_start = eth_igb_start,
352 .dev_stop = eth_igb_stop,
353 .dev_set_link_up = eth_igb_dev_set_link_up,
354 .dev_set_link_down = eth_igb_dev_set_link_down,
355 .dev_close = eth_igb_close,
356 .promiscuous_enable = eth_igb_promiscuous_enable,
357 .promiscuous_disable = eth_igb_promiscuous_disable,
358 .allmulticast_enable = eth_igb_allmulticast_enable,
359 .allmulticast_disable = eth_igb_allmulticast_disable,
360 .link_update = eth_igb_link_update,
361 .stats_get = eth_igb_stats_get,
362 .xstats_get = eth_igb_xstats_get,
363 .xstats_get_by_id = eth_igb_xstats_get_by_id,
364 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
365 .xstats_get_names = eth_igb_xstats_get_names,
366 .stats_reset = eth_igb_stats_reset,
367 .xstats_reset = eth_igb_xstats_reset,
368 .fw_version_get = eth_igb_fw_version_get,
369 .dev_infos_get = eth_igb_infos_get,
370 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
371 .mtu_set = eth_igb_mtu_set,
372 .vlan_filter_set = eth_igb_vlan_filter_set,
373 .vlan_tpid_set = eth_igb_vlan_tpid_set,
374 .vlan_offload_set = eth_igb_vlan_offload_set,
375 .rx_queue_setup = eth_igb_rx_queue_setup,
376 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
377 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
378 .rx_queue_release = eth_igb_rx_queue_release,
379 .rx_queue_count = eth_igb_rx_queue_count,
380 .rx_descriptor_done = eth_igb_rx_descriptor_done,
381 .rx_descriptor_status = eth_igb_rx_descriptor_status,
382 .tx_descriptor_status = eth_igb_tx_descriptor_status,
383 .tx_queue_setup = eth_igb_tx_queue_setup,
384 .tx_queue_release = eth_igb_tx_queue_release,
385 .tx_done_cleanup = eth_igb_tx_done_cleanup,
386 .dev_led_on = eth_igb_led_on,
387 .dev_led_off = eth_igb_led_off,
388 .flow_ctrl_get = eth_igb_flow_ctrl_get,
389 .flow_ctrl_set = eth_igb_flow_ctrl_set,
390 .mac_addr_add = eth_igb_rar_set,
391 .mac_addr_remove = eth_igb_rar_clear,
392 .mac_addr_set = eth_igb_default_mac_addr_set,
393 .reta_update = eth_igb_rss_reta_update,
394 .reta_query = eth_igb_rss_reta_query,
395 .rss_hash_update = eth_igb_rss_hash_update,
396 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
397 .filter_ctrl = eth_igb_filter_ctrl,
398 .set_mc_addr_list = eth_igb_set_mc_addr_list,
399 .rxq_info_get = igb_rxq_info_get,
400 .txq_info_get = igb_txq_info_get,
401 .timesync_enable = igb_timesync_enable,
402 .timesync_disable = igb_timesync_disable,
403 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
404 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
405 .get_reg = eth_igb_get_regs,
406 .get_eeprom_length = eth_igb_get_eeprom_length,
407 .get_eeprom = eth_igb_get_eeprom,
408 .set_eeprom = eth_igb_set_eeprom,
409 .get_module_info = eth_igb_get_module_info,
410 .get_module_eeprom = eth_igb_get_module_eeprom,
411 .timesync_adjust_time = igb_timesync_adjust_time,
412 .timesync_read_time = igb_timesync_read_time,
413 .timesync_write_time = igb_timesync_write_time,
417 * dev_ops for virtual function, bare necessities for basic vf
418 * operation have been implemented
420 static const struct eth_dev_ops igbvf_eth_dev_ops = {
421 .dev_configure = igbvf_dev_configure,
422 .dev_start = igbvf_dev_start,
423 .dev_stop = igbvf_dev_stop,
424 .dev_close = igbvf_dev_close,
425 .promiscuous_enable = igbvf_promiscuous_enable,
426 .promiscuous_disable = igbvf_promiscuous_disable,
427 .allmulticast_enable = igbvf_allmulticast_enable,
428 .allmulticast_disable = igbvf_allmulticast_disable,
429 .link_update = eth_igb_link_update,
430 .stats_get = eth_igbvf_stats_get,
431 .xstats_get = eth_igbvf_xstats_get,
432 .xstats_get_names = eth_igbvf_xstats_get_names,
433 .stats_reset = eth_igbvf_stats_reset,
434 .xstats_reset = eth_igbvf_stats_reset,
435 .vlan_filter_set = igbvf_vlan_filter_set,
436 .dev_infos_get = eth_igbvf_infos_get,
437 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
438 .rx_queue_setup = eth_igb_rx_queue_setup,
439 .rx_queue_release = eth_igb_rx_queue_release,
440 .tx_queue_setup = eth_igb_tx_queue_setup,
441 .tx_queue_release = eth_igb_tx_queue_release,
442 .set_mc_addr_list = eth_igb_set_mc_addr_list,
443 .rxq_info_get = igb_rxq_info_get,
444 .txq_info_get = igb_txq_info_get,
445 .mac_addr_set = igbvf_default_mac_addr_set,
446 .get_reg = igbvf_get_regs,
449 /* store statistics names and its offset in stats structure */
450 struct rte_igb_xstats_name_off {
451 char name[RTE_ETH_XSTATS_NAME_SIZE];
455 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
456 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
457 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
458 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
459 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
460 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
461 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
462 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
464 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
465 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
466 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
467 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
468 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
469 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
470 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
471 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
472 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
473 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
474 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
476 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
477 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
478 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
479 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
480 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
482 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
484 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
485 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
486 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
487 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
488 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
489 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
490 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
491 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
492 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
493 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
494 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
495 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
496 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
497 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
498 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
499 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
500 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
501 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
503 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
505 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
506 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
507 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
508 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
509 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
510 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
511 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
513 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
516 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
517 sizeof(rte_igb_stats_strings[0]))
519 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
520 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
521 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
522 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
523 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
524 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
527 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
528 sizeof(rte_igbvf_stats_strings[0]))
532 igb_intr_enable(struct rte_eth_dev *dev)
534 struct e1000_interrupt *intr =
535 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
536 struct e1000_hw *hw =
537 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
539 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
540 E1000_WRITE_FLUSH(hw);
544 igb_intr_disable(struct e1000_hw *hw)
546 E1000_WRITE_REG(hw, E1000_IMC, ~0);
547 E1000_WRITE_FLUSH(hw);
551 igbvf_intr_enable(struct rte_eth_dev *dev)
553 struct e1000_hw *hw =
554 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
556 /* only for mailbox */
557 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
558 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
559 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
560 E1000_WRITE_FLUSH(hw);
563 /* only for mailbox now. If RX/TX needed, should extend this function. */
565 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
570 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
571 tmp |= E1000_VTIVAR_VALID;
572 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
576 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
578 struct e1000_hw *hw =
579 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
581 /* Configure VF other cause ivar */
582 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
585 static inline int32_t
586 igb_pf_reset_hw(struct e1000_hw *hw)
591 status = e1000_reset_hw(hw);
593 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
594 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
595 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
596 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
597 E1000_WRITE_FLUSH(hw);
603 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
605 struct e1000_hw *hw =
606 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
609 hw->vendor_id = pci_dev->id.vendor_id;
610 hw->device_id = pci_dev->id.device_id;
611 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
612 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
614 e1000_set_mac_type(hw);
616 /* need to check if it is a vf device below */
620 igb_reset_swfw_lock(struct e1000_hw *hw)
625 * Do mac ops initialization manually here, since we will need
626 * some function pointers set by this call.
628 ret_val = e1000_init_mac_params(hw);
633 * SMBI lock should not fail in this early stage. If this is the case,
634 * it is due to an improper exit of the application.
635 * So force the release of the faulty lock.
637 if (e1000_get_hw_semaphore_generic(hw) < 0) {
638 PMD_DRV_LOG(DEBUG, "SMBI lock released");
640 e1000_put_hw_semaphore_generic(hw);
642 if (hw->mac.ops.acquire_swfw_sync != NULL) {
646 * Phy lock should not fail in this early stage. If this is the case,
647 * it is due to an improper exit of the application.
648 * So force the release of the faulty lock.
650 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
651 if (hw->bus.func > E1000_FUNC_1)
653 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
654 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
657 hw->mac.ops.release_swfw_sync(hw, mask);
660 * This one is more tricky since it is common to all ports; but
661 * swfw_sync retries last long enough (1s) to be almost sure that if
662 * lock can not be taken it is due to an improper lock of the
665 mask = E1000_SWFW_EEP_SM;
666 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
667 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
669 hw->mac.ops.release_swfw_sync(hw, mask);
672 return E1000_SUCCESS;
675 /* Remove all ntuple filters of the device */
676 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
678 struct e1000_filter_info *filter_info =
679 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
680 struct e1000_5tuple_filter *p_5tuple;
681 struct e1000_2tuple_filter *p_2tuple;
683 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
684 TAILQ_REMOVE(&filter_info->fivetuple_list,
688 filter_info->fivetuple_mask = 0;
689 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
690 TAILQ_REMOVE(&filter_info->twotuple_list,
694 filter_info->twotuple_mask = 0;
699 /* Remove all flex filters of the device */
700 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
702 struct e1000_filter_info *filter_info =
703 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
704 struct e1000_flex_filter *p_flex;
706 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
707 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
710 filter_info->flex_mask = 0;
716 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
719 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
720 struct e1000_hw *hw =
721 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
722 struct e1000_vfta * shadow_vfta =
723 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
724 struct e1000_filter_info *filter_info =
725 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
726 struct e1000_adapter *adapter =
727 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
731 eth_dev->dev_ops = ð_igb_ops;
732 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
733 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
734 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
736 /* for secondary processes, we don't initialise any further as primary
737 * has already done this work. Only check we don't need a different
739 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
740 if (eth_dev->data->scattered_rx)
741 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
745 rte_eth_copy_pci_info(eth_dev, pci_dev);
747 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
749 igb_identify_hardware(eth_dev, pci_dev);
750 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
755 e1000_get_bus_info(hw);
757 /* Reset any pending lock */
758 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
763 /* Finish initialization */
764 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
770 hw->phy.autoneg_wait_to_complete = 0;
771 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
774 if (hw->phy.media_type == e1000_media_type_copper) {
775 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
776 hw->phy.disable_polarity_correction = 0;
777 hw->phy.ms_type = e1000_ms_hw_default;
781 * Start from a known state, this is important in reading the nvm
786 /* Make sure we have a good EEPROM before we read from it */
787 if (e1000_validate_nvm_checksum(hw) < 0) {
789 * Some PCI-E parts fail the first check due to
790 * the link being in sleep state, call it again,
791 * if it fails a second time its a real issue.
793 if (e1000_validate_nvm_checksum(hw) < 0) {
794 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
800 /* Read the permanent MAC address out of the EEPROM */
801 if (e1000_read_mac_addr(hw) != 0) {
802 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
807 /* Allocate memory for storing MAC addresses */
808 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
809 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
810 if (eth_dev->data->mac_addrs == NULL) {
811 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
812 "store MAC addresses",
813 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
818 /* Copy the permanent MAC address */
819 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
821 /* initialize the vfta */
822 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
824 /* Now initialize the hardware */
825 if (igb_hardware_init(hw) != 0) {
826 PMD_INIT_LOG(ERR, "Hardware initialization failed");
827 rte_free(eth_dev->data->mac_addrs);
828 eth_dev->data->mac_addrs = NULL;
832 hw->mac.get_link_status = 1;
833 adapter->stopped = 0;
835 /* Indicate SOL/IDER usage */
836 if (e1000_check_reset_block(hw) < 0) {
837 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
841 /* initialize PF if max_vfs not zero */
842 igb_pf_host_init(eth_dev);
844 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
845 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
846 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
847 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
848 E1000_WRITE_FLUSH(hw);
850 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
851 eth_dev->data->port_id, pci_dev->id.vendor_id,
852 pci_dev->id.device_id);
854 rte_intr_callback_register(&pci_dev->intr_handle,
855 eth_igb_interrupt_handler,
858 /* enable uio/vfio intr/eventfd mapping */
859 rte_intr_enable(&pci_dev->intr_handle);
861 /* enable support intr */
862 igb_intr_enable(eth_dev);
864 /* initialize filter info */
865 memset(filter_info, 0,
866 sizeof(struct e1000_filter_info));
868 TAILQ_INIT(&filter_info->flex_list);
869 TAILQ_INIT(&filter_info->twotuple_list);
870 TAILQ_INIT(&filter_info->fivetuple_list);
872 TAILQ_INIT(&igb_filter_ntuple_list);
873 TAILQ_INIT(&igb_filter_ethertype_list);
874 TAILQ_INIT(&igb_filter_syn_list);
875 TAILQ_INIT(&igb_filter_flex_list);
876 TAILQ_INIT(&igb_filter_rss_list);
877 TAILQ_INIT(&igb_flow_list);
882 igb_hw_control_release(hw);
888 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
890 struct rte_pci_device *pci_dev;
891 struct rte_intr_handle *intr_handle;
893 struct e1000_adapter *adapter =
894 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
895 struct e1000_filter_info *filter_info =
896 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
898 PMD_INIT_FUNC_TRACE();
900 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
903 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
904 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
905 intr_handle = &pci_dev->intr_handle;
907 if (adapter->stopped == 0)
908 eth_igb_close(eth_dev);
910 eth_dev->dev_ops = NULL;
911 eth_dev->rx_pkt_burst = NULL;
912 eth_dev->tx_pkt_burst = NULL;
914 /* Reset any pending lock */
915 igb_reset_swfw_lock(hw);
917 rte_free(eth_dev->data->mac_addrs);
918 eth_dev->data->mac_addrs = NULL;
920 /* uninitialize PF if max_vfs not zero */
921 igb_pf_host_uninit(eth_dev);
923 /* disable uio intr before callback unregister */
924 rte_intr_disable(intr_handle);
925 rte_intr_callback_unregister(intr_handle,
926 eth_igb_interrupt_handler, eth_dev);
928 /* clear the SYN filter info */
929 filter_info->syn_info = 0;
931 /* clear the ethertype filters info */
932 filter_info->ethertype_mask = 0;
933 memset(filter_info->ethertype_filters, 0,
934 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
936 /* clear the rss filter info */
937 memset(&filter_info->rss_info, 0,
938 sizeof(struct igb_rte_flow_rss_conf));
940 /* remove all ntuple filters of the device */
941 igb_ntuple_filter_uninit(eth_dev);
943 /* remove all flex filters of the device */
944 igb_flex_filter_uninit(eth_dev);
946 /* clear all the filters list */
947 igb_filterlist_flush(eth_dev);
953 * Virtual Function device init
956 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
958 struct rte_pci_device *pci_dev;
959 struct rte_intr_handle *intr_handle;
960 struct e1000_adapter *adapter =
961 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
962 struct e1000_hw *hw =
963 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
965 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
967 PMD_INIT_FUNC_TRACE();
969 eth_dev->dev_ops = &igbvf_eth_dev_ops;
970 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
971 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
972 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
974 /* for secondary processes, we don't initialise any further as primary
975 * has already done this work. Only check we don't need a different
977 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
978 if (eth_dev->data->scattered_rx)
979 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
983 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
984 rte_eth_copy_pci_info(eth_dev, pci_dev);
986 hw->device_id = pci_dev->id.device_id;
987 hw->vendor_id = pci_dev->id.vendor_id;
988 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
989 adapter->stopped = 0;
991 /* Initialize the shared code (base driver) */
992 diag = e1000_setup_init_funcs(hw, TRUE);
994 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
999 /* init_mailbox_params */
1000 hw->mbx.ops.init_params(hw);
1002 /* Disable the interrupts for VF */
1003 igbvf_intr_disable(hw);
1005 diag = hw->mac.ops.reset_hw(hw);
1007 /* Allocate memory for storing MAC addresses */
1008 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1009 hw->mac.rar_entry_count, 0);
1010 if (eth_dev->data->mac_addrs == NULL) {
1012 "Failed to allocate %d bytes needed to store MAC "
1014 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1018 /* Generate a random MAC address, if none was assigned by PF. */
1019 if (is_zero_ether_addr(perm_addr)) {
1020 eth_random_addr(perm_addr->addr_bytes);
1021 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1022 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1023 "%02x:%02x:%02x:%02x:%02x:%02x",
1024 perm_addr->addr_bytes[0],
1025 perm_addr->addr_bytes[1],
1026 perm_addr->addr_bytes[2],
1027 perm_addr->addr_bytes[3],
1028 perm_addr->addr_bytes[4],
1029 perm_addr->addr_bytes[5]);
1032 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1034 rte_free(eth_dev->data->mac_addrs);
1035 eth_dev->data->mac_addrs = NULL;
1038 /* Copy the permanent MAC address */
1039 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1040 ð_dev->data->mac_addrs[0]);
1042 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1044 eth_dev->data->port_id, pci_dev->id.vendor_id,
1045 pci_dev->id.device_id, "igb_mac_82576_vf");
1047 intr_handle = &pci_dev->intr_handle;
1048 rte_intr_callback_register(intr_handle,
1049 eth_igbvf_interrupt_handler, eth_dev);
1055 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1057 struct e1000_adapter *adapter =
1058 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1059 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1061 PMD_INIT_FUNC_TRACE();
1063 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1066 if (adapter->stopped == 0)
1067 igbvf_dev_close(eth_dev);
1069 eth_dev->dev_ops = NULL;
1070 eth_dev->rx_pkt_burst = NULL;
1071 eth_dev->tx_pkt_burst = NULL;
1073 rte_free(eth_dev->data->mac_addrs);
1074 eth_dev->data->mac_addrs = NULL;
1076 /* disable uio intr before callback unregister */
1077 rte_intr_disable(&pci_dev->intr_handle);
1078 rte_intr_callback_unregister(&pci_dev->intr_handle,
1079 eth_igbvf_interrupt_handler,
1085 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1086 struct rte_pci_device *pci_dev)
1088 return rte_eth_dev_pci_generic_probe(pci_dev,
1089 sizeof(struct e1000_adapter), eth_igb_dev_init);
1092 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1094 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1097 static struct rte_pci_driver rte_igb_pmd = {
1098 .id_table = pci_id_igb_map,
1099 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1100 RTE_PCI_DRV_IOVA_AS_VA,
1101 .probe = eth_igb_pci_probe,
1102 .remove = eth_igb_pci_remove,
1106 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1107 struct rte_pci_device *pci_dev)
1109 return rte_eth_dev_pci_generic_probe(pci_dev,
1110 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1113 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1115 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1119 * virtual function driver struct
1121 static struct rte_pci_driver rte_igbvf_pmd = {
1122 .id_table = pci_id_igbvf_map,
1123 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1124 .probe = eth_igbvf_pci_probe,
1125 .remove = eth_igbvf_pci_remove,
1129 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1131 struct e1000_hw *hw =
1132 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1133 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1134 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1135 rctl |= E1000_RCTL_VFE;
1136 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1140 igb_check_mq_mode(struct rte_eth_dev *dev)
1142 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1143 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1144 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1145 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1147 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1148 tx_mq_mode == ETH_MQ_TX_DCB ||
1149 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1150 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1153 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1154 /* Check multi-queue mode.
1155 * To no break software we accept ETH_MQ_RX_NONE as this might
1156 * be used to turn off VLAN filter.
1159 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1160 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1161 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1162 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1164 /* Only support one queue on VFs.
1165 * RSS together with SRIOV is not supported.
1167 PMD_INIT_LOG(ERR, "SRIOV is active,"
1168 " wrong mq_mode rx %d.",
1172 /* TX mode is not used here, so mode might be ignored.*/
1173 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1174 /* SRIOV only works in VMDq enable mode */
1175 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1176 " TX mode %d is not supported. "
1177 " Driver will behave as %d mode.",
1178 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1181 /* check valid queue number */
1182 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1183 PMD_INIT_LOG(ERR, "SRIOV is active,"
1184 " only support one queue on VFs.");
1188 /* To no break software that set invalid mode, only display
1189 * warning if invalid mode is used.
1191 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1192 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1193 rx_mq_mode != ETH_MQ_RX_RSS) {
1194 /* RSS together with VMDq not supported*/
1195 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1200 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1201 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1202 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1203 " Due to txmode is meaningless in this"
1204 " driver, just ignore.",
1212 eth_igb_configure(struct rte_eth_dev *dev)
1214 struct e1000_interrupt *intr =
1215 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1218 PMD_INIT_FUNC_TRACE();
1220 /* multipe queue mode checking */
1221 ret = igb_check_mq_mode(dev);
1223 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1228 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1229 PMD_INIT_FUNC_TRACE();
1235 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1238 struct e1000_hw *hw =
1239 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1240 uint32_t tctl, rctl;
1242 tctl = E1000_READ_REG(hw, E1000_TCTL);
1243 rctl = E1000_READ_REG(hw, E1000_RCTL);
1247 tctl |= E1000_TCTL_EN;
1248 rctl |= E1000_RCTL_EN;
1251 tctl &= ~E1000_TCTL_EN;
1252 rctl &= ~E1000_RCTL_EN;
1254 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1255 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1256 E1000_WRITE_FLUSH(hw);
1260 eth_igb_start(struct rte_eth_dev *dev)
1262 struct e1000_hw *hw =
1263 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1264 struct e1000_adapter *adapter =
1265 E1000_DEV_PRIVATE(dev->data->dev_private);
1266 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1267 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1269 uint32_t intr_vector = 0;
1275 PMD_INIT_FUNC_TRACE();
1277 /* disable uio/vfio intr/eventfd mapping */
1278 rte_intr_disable(intr_handle);
1280 /* Power up the phy. Needed to make the link go Up */
1281 eth_igb_dev_set_link_up(dev);
1284 * Packet Buffer Allocation (PBA)
1285 * Writing PBA sets the receive portion of the buffer
1286 * the remainder is used for the transmit buffer.
1288 if (hw->mac.type == e1000_82575) {
1291 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1292 E1000_WRITE_REG(hw, E1000_PBA, pba);
1295 /* Put the address into the Receive Address Array */
1296 e1000_rar_set(hw, hw->mac.addr, 0);
1298 /* Initialize the hardware */
1299 if (igb_hardware_init(hw)) {
1300 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1303 adapter->stopped = 0;
1305 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1307 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1308 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1309 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1310 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1311 E1000_WRITE_FLUSH(hw);
1313 /* configure PF module if SRIOV enabled */
1314 igb_pf_host_configure(dev);
1316 /* check and configure queue intr-vector mapping */
1317 if ((rte_intr_cap_multiple(intr_handle) ||
1318 !RTE_ETH_DEV_SRIOV(dev).active) &&
1319 dev->data->dev_conf.intr_conf.rxq != 0) {
1320 intr_vector = dev->data->nb_rx_queues;
1321 if (rte_intr_efd_enable(intr_handle, intr_vector))
1325 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1326 intr_handle->intr_vec =
1327 rte_zmalloc("intr_vec",
1328 dev->data->nb_rx_queues * sizeof(int), 0);
1329 if (intr_handle->intr_vec == NULL) {
1330 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1331 " intr_vec", dev->data->nb_rx_queues);
1336 /* confiugre msix for rx interrupt */
1337 eth_igb_configure_msix_intr(dev);
1339 /* Configure for OS presence */
1340 igb_init_manageability(hw);
1342 eth_igb_tx_init(dev);
1344 /* This can fail when allocating mbufs for descriptor rings */
1345 ret = eth_igb_rx_init(dev);
1347 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1348 igb_dev_clear_queues(dev);
1352 e1000_clear_hw_cntrs_base_generic(hw);
1355 * VLAN Offload Settings
1357 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1358 ETH_VLAN_EXTEND_MASK;
1359 ret = eth_igb_vlan_offload_set(dev, mask);
1361 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1362 igb_dev_clear_queues(dev);
1366 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1367 /* Enable VLAN filter since VMDq always use VLAN filter */
1368 igb_vmdq_vlan_hw_filter_enable(dev);
1371 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1372 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1373 (hw->mac.type == e1000_i211)) {
1374 /* Configure EITR with the maximum possible value (0xFFFF) */
1375 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1378 /* Setup link speed and duplex */
1379 speeds = &dev->data->dev_conf.link_speeds;
1380 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1381 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1382 hw->mac.autoneg = 1;
1385 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1388 hw->phy.autoneg_advertised = 0;
1390 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1391 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1392 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1394 goto error_invalid_config;
1396 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1397 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1400 if (*speeds & ETH_LINK_SPEED_10M) {
1401 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1404 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1405 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1408 if (*speeds & ETH_LINK_SPEED_100M) {
1409 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1412 if (*speeds & ETH_LINK_SPEED_1G) {
1413 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1416 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1417 goto error_invalid_config;
1419 /* Set/reset the mac.autoneg based on the link speed,
1423 hw->mac.autoneg = 0;
1424 hw->mac.forced_speed_duplex =
1425 hw->phy.autoneg_advertised;
1427 hw->mac.autoneg = 1;
1431 e1000_setup_link(hw);
1433 if (rte_intr_allow_others(intr_handle)) {
1434 /* check if lsc interrupt is enabled */
1435 if (dev->data->dev_conf.intr_conf.lsc != 0)
1436 eth_igb_lsc_interrupt_setup(dev, TRUE);
1438 eth_igb_lsc_interrupt_setup(dev, FALSE);
1440 rte_intr_callback_unregister(intr_handle,
1441 eth_igb_interrupt_handler,
1443 if (dev->data->dev_conf.intr_conf.lsc != 0)
1444 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1445 " no intr multiplex");
1448 /* check if rxq interrupt is enabled */
1449 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1450 rte_intr_dp_is_en(intr_handle))
1451 eth_igb_rxq_interrupt_setup(dev);
1453 /* enable uio/vfio intr/eventfd mapping */
1454 rte_intr_enable(intr_handle);
1456 /* resume enabled intr since hw reset */
1457 igb_intr_enable(dev);
1459 /* restore all types filter */
1460 igb_filter_restore(dev);
1462 eth_igb_rxtx_control(dev, true);
1463 eth_igb_link_update(dev, 0);
1465 PMD_INIT_LOG(DEBUG, "<<");
1469 error_invalid_config:
1470 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1471 dev->data->dev_conf.link_speeds, dev->data->port_id);
1472 igb_dev_clear_queues(dev);
1476 /*********************************************************************
1478 * This routine disables all traffic on the adapter by issuing a
1479 * global reset on the MAC.
1481 **********************************************************************/
1483 eth_igb_stop(struct rte_eth_dev *dev)
1485 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1487 struct rte_eth_link link;
1488 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1490 eth_igb_rxtx_control(dev, false);
1492 igb_intr_disable(hw);
1494 /* disable intr eventfd mapping */
1495 rte_intr_disable(intr_handle);
1497 igb_pf_reset_hw(hw);
1498 E1000_WRITE_REG(hw, E1000_WUC, 0);
1500 /* Set bit for Go Link disconnect */
1501 if (hw->mac.type >= e1000_82580) {
1504 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1505 phpm_reg |= E1000_82580_PM_GO_LINKD;
1506 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1509 /* Power down the phy. Needed to make the link go Down */
1510 eth_igb_dev_set_link_down(dev);
1512 igb_dev_clear_queues(dev);
1514 /* clear the recorded link status */
1515 memset(&link, 0, sizeof(link));
1516 rte_eth_linkstatus_set(dev, &link);
1518 if (!rte_intr_allow_others(intr_handle))
1519 /* resume to the default handler */
1520 rte_intr_callback_register(intr_handle,
1521 eth_igb_interrupt_handler,
1524 /* Clean datapath event and queue/vec mapping */
1525 rte_intr_efd_disable(intr_handle);
1526 if (intr_handle->intr_vec != NULL) {
1527 rte_free(intr_handle->intr_vec);
1528 intr_handle->intr_vec = NULL;
1533 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1535 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537 if (hw->phy.media_type == e1000_media_type_copper)
1538 e1000_power_up_phy(hw);
1540 e1000_power_up_fiber_serdes_link(hw);
1546 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1548 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550 if (hw->phy.media_type == e1000_media_type_copper)
1551 e1000_power_down_phy(hw);
1553 e1000_shutdown_fiber_serdes_link(hw);
1559 eth_igb_close(struct rte_eth_dev *dev)
1561 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1562 struct e1000_adapter *adapter =
1563 E1000_DEV_PRIVATE(dev->data->dev_private);
1564 struct rte_eth_link link;
1565 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1566 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1569 adapter->stopped = 1;
1571 e1000_phy_hw_reset(hw);
1572 igb_release_manageability(hw);
1573 igb_hw_control_release(hw);
1575 /* Clear bit for Go Link disconnect */
1576 if (hw->mac.type >= e1000_82580) {
1579 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1580 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1581 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1584 igb_dev_free_queues(dev);
1586 if (intr_handle->intr_vec) {
1587 rte_free(intr_handle->intr_vec);
1588 intr_handle->intr_vec = NULL;
1591 memset(&link, 0, sizeof(link));
1592 rte_eth_linkstatus_set(dev, &link);
1596 igb_get_rx_buffer_size(struct e1000_hw *hw)
1598 uint32_t rx_buf_size;
1599 if (hw->mac.type == e1000_82576) {
1600 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1601 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1602 /* PBS needs to be translated according to a lookup table */
1603 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1604 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1605 rx_buf_size = (rx_buf_size << 10);
1606 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1607 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1609 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1615 /*********************************************************************
1617 * Initialize the hardware
1619 **********************************************************************/
1621 igb_hardware_init(struct e1000_hw *hw)
1623 uint32_t rx_buf_size;
1626 /* Let the firmware know the OS is in control */
1627 igb_hw_control_acquire(hw);
1630 * These parameters control the automatic generation (Tx) and
1631 * response (Rx) to Ethernet PAUSE frames.
1632 * - High water mark should allow for at least two standard size (1518)
1633 * frames to be received after sending an XOFF.
1634 * - Low water mark works best when it is very near the high water mark.
1635 * This allows the receiver to restart by sending XON when it has
1636 * drained a bit. Here we use an arbitrary value of 1500 which will
1637 * restart after one full frame is pulled from the buffer. There
1638 * could be several smaller frames in the buffer and if so they will
1639 * not trigger the XON until their total number reduces the buffer
1641 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1643 rx_buf_size = igb_get_rx_buffer_size(hw);
1645 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1646 hw->fc.low_water = hw->fc.high_water - 1500;
1647 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1648 hw->fc.send_xon = 1;
1650 /* Set Flow control, use the tunable location if sane */
1651 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1652 hw->fc.requested_mode = igb_fc_setting;
1654 hw->fc.requested_mode = e1000_fc_none;
1656 /* Issue a global reset */
1657 igb_pf_reset_hw(hw);
1658 E1000_WRITE_REG(hw, E1000_WUC, 0);
1660 diag = e1000_init_hw(hw);
1664 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1665 e1000_get_phy_info(hw);
1666 e1000_check_for_link(hw);
1671 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1673 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1677 uint64_t old_gprc = stats->gprc;
1678 uint64_t old_gptc = stats->gptc;
1679 uint64_t old_tpr = stats->tpr;
1680 uint64_t old_tpt = stats->tpt;
1681 uint64_t old_rpthc = stats->rpthc;
1682 uint64_t old_hgptc = stats->hgptc;
1684 if(hw->phy.media_type == e1000_media_type_copper ||
1685 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1687 E1000_READ_REG(hw,E1000_SYMERRS);
1688 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1691 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1692 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1693 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1694 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1696 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1697 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1698 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1699 stats->dc += E1000_READ_REG(hw, E1000_DC);
1700 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1701 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1702 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1704 ** For watchdog management we need to know if we have been
1705 ** paused during the last interval, so capture that here.
1707 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1708 stats->xoffrxc += pause_frames;
1709 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1710 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1711 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1712 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1713 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1714 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1715 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1716 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1717 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1718 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1719 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1720 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1722 /* For the 64-bit byte counters the low dword must be read first. */
1723 /* Both registers clear on the read of the high dword */
1725 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1726 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1727 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1728 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1729 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1730 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1731 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1733 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1734 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1735 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1736 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1737 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1739 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1740 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1742 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1743 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1744 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1745 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1746 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1747 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1749 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1750 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1751 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1752 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1753 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1754 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1755 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1756 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1758 /* Interrupt Counts */
1760 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1761 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1762 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1763 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1764 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1765 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1766 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1767 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1768 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1770 /* Host to Card Statistics */
1772 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1773 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1774 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1775 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1776 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1777 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1778 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1779 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1780 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1781 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1782 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1783 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1784 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1785 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1786 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1787 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1789 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1790 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1791 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1792 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1793 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1794 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1798 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1800 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1801 struct e1000_hw_stats *stats =
1802 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1804 igb_read_stats_registers(hw, stats);
1806 if (rte_stats == NULL)
1810 rte_stats->imissed = stats->mpc;
1811 rte_stats->ierrors = stats->crcerrs +
1812 stats->rlec + stats->ruc + stats->roc +
1813 stats->rxerrc + stats->algnerrc + stats->cexterr;
1816 rte_stats->oerrors = stats->ecol + stats->latecol;
1818 rte_stats->ipackets = stats->gprc;
1819 rte_stats->opackets = stats->gptc;
1820 rte_stats->ibytes = stats->gorc;
1821 rte_stats->obytes = stats->gotc;
1826 eth_igb_stats_reset(struct rte_eth_dev *dev)
1828 struct e1000_hw_stats *hw_stats =
1829 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1831 /* HW registers are cleared on read */
1832 eth_igb_stats_get(dev, NULL);
1834 /* Reset software totals */
1835 memset(hw_stats, 0, sizeof(*hw_stats));
1839 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1841 struct e1000_hw_stats *stats =
1842 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1844 /* HW registers are cleared on read */
1845 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1847 /* Reset software totals */
1848 memset(stats, 0, sizeof(*stats));
1851 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1852 struct rte_eth_xstat_name *xstats_names,
1853 __rte_unused unsigned int size)
1857 if (xstats_names == NULL)
1858 return IGB_NB_XSTATS;
1860 /* Note: limit checked in rte_eth_xstats_names() */
1862 for (i = 0; i < IGB_NB_XSTATS; i++) {
1863 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1864 "%s", rte_igb_stats_strings[i].name);
1867 return IGB_NB_XSTATS;
1870 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1871 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1877 if (xstats_names == NULL)
1878 return IGB_NB_XSTATS;
1880 for (i = 0; i < IGB_NB_XSTATS; i++)
1881 snprintf(xstats_names[i].name,
1882 sizeof(xstats_names[i].name),
1883 "%s", rte_igb_stats_strings[i].name);
1885 return IGB_NB_XSTATS;
1888 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1890 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1893 for (i = 0; i < limit; i++) {
1894 if (ids[i] >= IGB_NB_XSTATS) {
1895 PMD_INIT_LOG(ERR, "id value isn't valid");
1898 strcpy(xstats_names[i].name,
1899 xstats_names_copy[ids[i]].name);
1906 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1909 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910 struct e1000_hw_stats *hw_stats =
1911 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1914 if (n < IGB_NB_XSTATS)
1915 return IGB_NB_XSTATS;
1917 igb_read_stats_registers(hw, hw_stats);
1919 /* If this is a reset xstats is NULL, and we have cleared the
1920 * registers by reading them.
1925 /* Extended stats */
1926 for (i = 0; i < IGB_NB_XSTATS; i++) {
1928 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1929 rte_igb_stats_strings[i].offset);
1932 return IGB_NB_XSTATS;
1936 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1937 uint64_t *values, unsigned int n)
1942 struct e1000_hw *hw =
1943 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944 struct e1000_hw_stats *hw_stats =
1945 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1947 if (n < IGB_NB_XSTATS)
1948 return IGB_NB_XSTATS;
1950 igb_read_stats_registers(hw, hw_stats);
1952 /* If this is a reset xstats is NULL, and we have cleared the
1953 * registers by reading them.
1958 /* Extended stats */
1959 for (i = 0; i < IGB_NB_XSTATS; i++)
1960 values[i] = *(uint64_t *)(((char *)hw_stats) +
1961 rte_igb_stats_strings[i].offset);
1963 return IGB_NB_XSTATS;
1966 uint64_t values_copy[IGB_NB_XSTATS];
1968 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1971 for (i = 0; i < n; i++) {
1972 if (ids[i] >= IGB_NB_XSTATS) {
1973 PMD_INIT_LOG(ERR, "id value isn't valid");
1976 values[i] = values_copy[ids[i]];
1983 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1985 /* Good Rx packets, include VF loopback */
1986 UPDATE_VF_STAT(E1000_VFGPRC,
1987 hw_stats->last_gprc, hw_stats->gprc);
1989 /* Good Rx octets, include VF loopback */
1990 UPDATE_VF_STAT(E1000_VFGORC,
1991 hw_stats->last_gorc, hw_stats->gorc);
1993 /* Good Tx packets, include VF loopback */
1994 UPDATE_VF_STAT(E1000_VFGPTC,
1995 hw_stats->last_gptc, hw_stats->gptc);
1997 /* Good Tx octets, include VF loopback */
1998 UPDATE_VF_STAT(E1000_VFGOTC,
1999 hw_stats->last_gotc, hw_stats->gotc);
2001 /* Rx Multicst packets */
2002 UPDATE_VF_STAT(E1000_VFMPRC,
2003 hw_stats->last_mprc, hw_stats->mprc);
2005 /* Good Rx loopback packets */
2006 UPDATE_VF_STAT(E1000_VFGPRLBC,
2007 hw_stats->last_gprlbc, hw_stats->gprlbc);
2009 /* Good Rx loopback octets */
2010 UPDATE_VF_STAT(E1000_VFGORLBC,
2011 hw_stats->last_gorlbc, hw_stats->gorlbc);
2013 /* Good Tx loopback packets */
2014 UPDATE_VF_STAT(E1000_VFGPTLBC,
2015 hw_stats->last_gptlbc, hw_stats->gptlbc);
2017 /* Good Tx loopback octets */
2018 UPDATE_VF_STAT(E1000_VFGOTLBC,
2019 hw_stats->last_gotlbc, hw_stats->gotlbc);
2022 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2023 struct rte_eth_xstat_name *xstats_names,
2024 __rte_unused unsigned limit)
2028 if (xstats_names != NULL)
2029 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2030 snprintf(xstats_names[i].name,
2031 sizeof(xstats_names[i].name), "%s",
2032 rte_igbvf_stats_strings[i].name);
2034 return IGBVF_NB_XSTATS;
2038 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2041 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2042 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2043 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2046 if (n < IGBVF_NB_XSTATS)
2047 return IGBVF_NB_XSTATS;
2049 igbvf_read_stats_registers(hw, hw_stats);
2054 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2056 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2057 rte_igbvf_stats_strings[i].offset);
2060 return IGBVF_NB_XSTATS;
2064 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2066 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2068 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2070 igbvf_read_stats_registers(hw, hw_stats);
2072 if (rte_stats == NULL)
2075 rte_stats->ipackets = hw_stats->gprc;
2076 rte_stats->ibytes = hw_stats->gorc;
2077 rte_stats->opackets = hw_stats->gptc;
2078 rte_stats->obytes = hw_stats->gotc;
2083 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2085 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2086 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2088 /* Sync HW register to the last stats */
2089 eth_igbvf_stats_get(dev, NULL);
2091 /* reset HW current stats*/
2092 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2093 offsetof(struct e1000_vf_stats, gprc));
2097 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2100 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101 struct e1000_fw_version fw;
2104 e1000_get_fw_version(hw, &fw);
2106 switch (hw->mac.type) {
2109 if (!(e1000_get_flash_presence_i210(hw))) {
2110 ret = snprintf(fw_version, fw_size,
2112 fw.invm_major, fw.invm_minor,
2118 /* if option rom is valid, display its version too */
2120 ret = snprintf(fw_version, fw_size,
2121 "%d.%d, 0x%08x, %d.%d.%d",
2122 fw.eep_major, fw.eep_minor, fw.etrack_id,
2123 fw.or_major, fw.or_build, fw.or_patch);
2126 if (fw.etrack_id != 0X0000) {
2127 ret = snprintf(fw_version, fw_size,
2129 fw.eep_major, fw.eep_minor,
2132 ret = snprintf(fw_version, fw_size,
2134 fw.eep_major, fw.eep_minor,
2141 ret += 1; /* add the size of '\0' */
2142 if (fw_size < (u32)ret)
2149 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2151 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2153 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2154 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2155 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2156 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2157 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2158 dev_info->rx_queue_offload_capa;
2159 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2160 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2161 dev_info->tx_queue_offload_capa;
2163 switch (hw->mac.type) {
2165 dev_info->max_rx_queues = 4;
2166 dev_info->max_tx_queues = 4;
2167 dev_info->max_vmdq_pools = 0;
2171 dev_info->max_rx_queues = 16;
2172 dev_info->max_tx_queues = 16;
2173 dev_info->max_vmdq_pools = ETH_8_POOLS;
2174 dev_info->vmdq_queue_num = 16;
2178 dev_info->max_rx_queues = 8;
2179 dev_info->max_tx_queues = 8;
2180 dev_info->max_vmdq_pools = ETH_8_POOLS;
2181 dev_info->vmdq_queue_num = 8;
2185 dev_info->max_rx_queues = 8;
2186 dev_info->max_tx_queues = 8;
2187 dev_info->max_vmdq_pools = ETH_8_POOLS;
2188 dev_info->vmdq_queue_num = 8;
2192 dev_info->max_rx_queues = 8;
2193 dev_info->max_tx_queues = 8;
2197 dev_info->max_rx_queues = 4;
2198 dev_info->max_tx_queues = 4;
2199 dev_info->max_vmdq_pools = 0;
2203 dev_info->max_rx_queues = 2;
2204 dev_info->max_tx_queues = 2;
2205 dev_info->max_vmdq_pools = 0;
2209 /* Should not happen */
2212 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2213 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2214 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2216 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2218 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2219 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2220 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2222 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2227 dev_info->default_txconf = (struct rte_eth_txconf) {
2229 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2230 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2231 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2237 dev_info->rx_desc_lim = rx_desc_lim;
2238 dev_info->tx_desc_lim = tx_desc_lim;
2240 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2241 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2245 static const uint32_t *
2246 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2248 static const uint32_t ptypes[] = {
2249 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2252 RTE_PTYPE_L3_IPV4_EXT,
2254 RTE_PTYPE_L3_IPV6_EXT,
2258 RTE_PTYPE_TUNNEL_IP,
2259 RTE_PTYPE_INNER_L3_IPV6,
2260 RTE_PTYPE_INNER_L3_IPV6_EXT,
2261 RTE_PTYPE_INNER_L4_TCP,
2262 RTE_PTYPE_INNER_L4_UDP,
2266 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2267 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2273 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2275 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2278 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2279 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2280 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2281 DEV_TX_OFFLOAD_IPV4_CKSUM |
2282 DEV_TX_OFFLOAD_UDP_CKSUM |
2283 DEV_TX_OFFLOAD_TCP_CKSUM |
2284 DEV_TX_OFFLOAD_SCTP_CKSUM |
2285 DEV_TX_OFFLOAD_TCP_TSO;
2286 switch (hw->mac.type) {
2288 dev_info->max_rx_queues = 2;
2289 dev_info->max_tx_queues = 2;
2291 case e1000_vfadapt_i350:
2292 dev_info->max_rx_queues = 1;
2293 dev_info->max_tx_queues = 1;
2296 /* Should not happen */
2300 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2301 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2302 dev_info->rx_queue_offload_capa;
2303 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2304 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2305 dev_info->tx_queue_offload_capa;
2307 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2309 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2310 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2311 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2313 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2318 dev_info->default_txconf = (struct rte_eth_txconf) {
2320 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2321 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2322 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2328 dev_info->rx_desc_lim = rx_desc_lim;
2329 dev_info->tx_desc_lim = tx_desc_lim;
2332 /* return 0 means link status changed, -1 means not changed */
2334 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2336 struct e1000_hw *hw =
2337 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2338 struct rte_eth_link link;
2339 int link_check, count;
2342 hw->mac.get_link_status = 1;
2344 /* possible wait-to-complete in up to 9 seconds */
2345 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2346 /* Read the real link status */
2347 switch (hw->phy.media_type) {
2348 case e1000_media_type_copper:
2349 /* Do the work to read phy */
2350 e1000_check_for_link(hw);
2351 link_check = !hw->mac.get_link_status;
2354 case e1000_media_type_fiber:
2355 e1000_check_for_link(hw);
2356 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2360 case e1000_media_type_internal_serdes:
2361 e1000_check_for_link(hw);
2362 link_check = hw->mac.serdes_has_link;
2365 /* VF device is type_unknown */
2366 case e1000_media_type_unknown:
2367 eth_igbvf_link_update(hw);
2368 link_check = !hw->mac.get_link_status;
2374 if (link_check || wait_to_complete == 0)
2376 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2378 memset(&link, 0, sizeof(link));
2380 /* Now we check if a transition has happened */
2382 uint16_t duplex, speed;
2383 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2384 link.link_duplex = (duplex == FULL_DUPLEX) ?
2385 ETH_LINK_FULL_DUPLEX :
2386 ETH_LINK_HALF_DUPLEX;
2387 link.link_speed = speed;
2388 link.link_status = ETH_LINK_UP;
2389 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2390 ETH_LINK_SPEED_FIXED);
2391 } else if (!link_check) {
2392 link.link_speed = 0;
2393 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2394 link.link_status = ETH_LINK_DOWN;
2395 link.link_autoneg = ETH_LINK_FIXED;
2398 return rte_eth_linkstatus_set(dev, &link);
2402 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2403 * For ASF and Pass Through versions of f/w this means
2404 * that the driver is loaded.
2407 igb_hw_control_acquire(struct e1000_hw *hw)
2411 /* Let firmware know the driver has taken over */
2412 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2413 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2417 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2418 * For ASF and Pass Through versions of f/w this means that the
2419 * driver is no longer loaded.
2422 igb_hw_control_release(struct e1000_hw *hw)
2426 /* Let firmware taken over control of h/w */
2427 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2428 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2429 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2433 * Bit of a misnomer, what this really means is
2434 * to enable OS management of the system... aka
2435 * to disable special hardware management features.
2438 igb_init_manageability(struct e1000_hw *hw)
2440 if (e1000_enable_mng_pass_thru(hw)) {
2441 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2442 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2444 /* disable hardware interception of ARP */
2445 manc &= ~(E1000_MANC_ARP_EN);
2447 /* enable receiving management packets to the host */
2448 manc |= E1000_MANC_EN_MNG2HOST;
2449 manc2h |= 1 << 5; /* Mng Port 623 */
2450 manc2h |= 1 << 6; /* Mng Port 664 */
2451 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2452 E1000_WRITE_REG(hw, E1000_MANC, manc);
2457 igb_release_manageability(struct e1000_hw *hw)
2459 if (e1000_enable_mng_pass_thru(hw)) {
2460 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2462 manc |= E1000_MANC_ARP_EN;
2463 manc &= ~E1000_MANC_EN_MNG2HOST;
2465 E1000_WRITE_REG(hw, E1000_MANC, manc);
2470 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2472 struct e1000_hw *hw =
2473 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476 rctl = E1000_READ_REG(hw, E1000_RCTL);
2477 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2478 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2482 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2484 struct e1000_hw *hw =
2485 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2488 rctl = E1000_READ_REG(hw, E1000_RCTL);
2489 rctl &= (~E1000_RCTL_UPE);
2490 if (dev->data->all_multicast == 1)
2491 rctl |= E1000_RCTL_MPE;
2493 rctl &= (~E1000_RCTL_MPE);
2494 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2498 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2500 struct e1000_hw *hw =
2501 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2504 rctl = E1000_READ_REG(hw, E1000_RCTL);
2505 rctl |= E1000_RCTL_MPE;
2506 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2510 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2512 struct e1000_hw *hw =
2513 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2516 if (dev->data->promiscuous == 1)
2517 return; /* must remain in all_multicast mode */
2518 rctl = E1000_READ_REG(hw, E1000_RCTL);
2519 rctl &= (~E1000_RCTL_MPE);
2520 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2524 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2526 struct e1000_hw *hw =
2527 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2528 struct e1000_vfta * shadow_vfta =
2529 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2534 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2535 E1000_VFTA_ENTRY_MASK);
2536 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2537 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2542 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2544 /* update local VFTA copy */
2545 shadow_vfta->vfta[vid_idx] = vfta;
2551 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2552 enum rte_vlan_type vlan_type,
2555 struct e1000_hw *hw =
2556 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2559 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2560 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2562 /* only outer TPID of double VLAN can be configured*/
2563 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2564 reg = E1000_READ_REG(hw, E1000_VET);
2565 reg = (reg & (~E1000_VET_VET_EXT)) |
2566 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2567 E1000_WRITE_REG(hw, E1000_VET, reg);
2572 /* all other TPID values are read-only*/
2573 PMD_DRV_LOG(ERR, "Not supported");
2579 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2581 struct e1000_hw *hw =
2582 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585 /* Filter Table Disable */
2586 reg = E1000_READ_REG(hw, E1000_RCTL);
2587 reg &= ~E1000_RCTL_CFIEN;
2588 reg &= ~E1000_RCTL_VFE;
2589 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2593 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2595 struct e1000_hw *hw =
2596 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2597 struct e1000_vfta * shadow_vfta =
2598 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2602 /* Filter Table Enable, CFI not used for packet acceptance */
2603 reg = E1000_READ_REG(hw, E1000_RCTL);
2604 reg &= ~E1000_RCTL_CFIEN;
2605 reg |= E1000_RCTL_VFE;
2606 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2608 /* restore VFTA table */
2609 for (i = 0; i < IGB_VFTA_SIZE; i++)
2610 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2614 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2616 struct e1000_hw *hw =
2617 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2620 /* VLAN Mode Disable */
2621 reg = E1000_READ_REG(hw, E1000_CTRL);
2622 reg &= ~E1000_CTRL_VME;
2623 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2627 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2629 struct e1000_hw *hw =
2630 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2633 /* VLAN Mode Enable */
2634 reg = E1000_READ_REG(hw, E1000_CTRL);
2635 reg |= E1000_CTRL_VME;
2636 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2640 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2642 struct e1000_hw *hw =
2643 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646 /* CTRL_EXT: Extended VLAN */
2647 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2648 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2649 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2651 /* Update maximum packet length */
2652 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2653 E1000_WRITE_REG(hw, E1000_RLPML,
2654 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2659 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2661 struct e1000_hw *hw =
2662 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2665 /* CTRL_EXT: Extended VLAN */
2666 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2667 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2668 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2670 /* Update maximum packet length */
2671 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2672 E1000_WRITE_REG(hw, E1000_RLPML,
2673 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2678 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2680 struct rte_eth_rxmode *rxmode;
2682 rxmode = &dev->data->dev_conf.rxmode;
2683 if(mask & ETH_VLAN_STRIP_MASK){
2684 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2685 igb_vlan_hw_strip_enable(dev);
2687 igb_vlan_hw_strip_disable(dev);
2690 if(mask & ETH_VLAN_FILTER_MASK){
2691 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2692 igb_vlan_hw_filter_enable(dev);
2694 igb_vlan_hw_filter_disable(dev);
2697 if(mask & ETH_VLAN_EXTEND_MASK){
2698 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2699 igb_vlan_hw_extend_enable(dev);
2701 igb_vlan_hw_extend_disable(dev);
2709 * It enables the interrupt mask and then enable the interrupt.
2712 * Pointer to struct rte_eth_dev.
2717 * - On success, zero.
2718 * - On failure, a negative value.
2721 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2723 struct e1000_interrupt *intr =
2724 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2727 intr->mask |= E1000_ICR_LSC;
2729 intr->mask &= ~E1000_ICR_LSC;
2734 /* It clears the interrupt causes and enables the interrupt.
2735 * It will be called once only during nic initialized.
2738 * Pointer to struct rte_eth_dev.
2741 * - On success, zero.
2742 * - On failure, a negative value.
2744 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2746 uint32_t mask, regval;
2747 struct e1000_hw *hw =
2748 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2749 struct rte_eth_dev_info dev_info;
2751 memset(&dev_info, 0, sizeof(dev_info));
2752 eth_igb_infos_get(dev, &dev_info);
2754 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2755 regval = E1000_READ_REG(hw, E1000_EIMS);
2756 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2762 * It reads ICR and gets interrupt causes, check it and set a bit flag
2763 * to update link status.
2766 * Pointer to struct rte_eth_dev.
2769 * - On success, zero.
2770 * - On failure, a negative value.
2773 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2776 struct e1000_hw *hw =
2777 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778 struct e1000_interrupt *intr =
2779 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2781 igb_intr_disable(hw);
2783 /* read-on-clear nic registers here */
2784 icr = E1000_READ_REG(hw, E1000_ICR);
2787 if (icr & E1000_ICR_LSC) {
2788 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2791 if (icr & E1000_ICR_VMMB)
2792 intr->flags |= E1000_FLAG_MAILBOX;
2798 * It executes link_update after knowing an interrupt is prsent.
2801 * Pointer to struct rte_eth_dev.
2804 * - On success, zero.
2805 * - On failure, a negative value.
2808 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2809 struct rte_intr_handle *intr_handle)
2811 struct e1000_hw *hw =
2812 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813 struct e1000_interrupt *intr =
2814 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2815 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2816 struct rte_eth_link link;
2819 if (intr->flags & E1000_FLAG_MAILBOX) {
2820 igb_pf_mbx_process(dev);
2821 intr->flags &= ~E1000_FLAG_MAILBOX;
2824 igb_intr_enable(dev);
2825 rte_intr_enable(intr_handle);
2827 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2828 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2830 /* set get_link_status to check register later */
2831 hw->mac.get_link_status = 1;
2832 ret = eth_igb_link_update(dev, 0);
2834 /* check if link has changed */
2838 rte_eth_linkstatus_get(dev, &link);
2839 if (link.link_status) {
2841 " Port %d: Link Up - speed %u Mbps - %s",
2843 (unsigned)link.link_speed,
2844 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2845 "full-duplex" : "half-duplex");
2847 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2848 dev->data->port_id);
2851 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2852 pci_dev->addr.domain,
2854 pci_dev->addr.devid,
2855 pci_dev->addr.function);
2856 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2864 * Interrupt handler which shall be registered at first.
2867 * Pointer to interrupt handle.
2869 * The address of parameter (struct rte_eth_dev *) regsitered before.
2875 eth_igb_interrupt_handler(void *param)
2877 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2879 eth_igb_interrupt_get_status(dev);
2880 eth_igb_interrupt_action(dev, dev->intr_handle);
2884 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2887 struct e1000_hw *hw =
2888 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2889 struct e1000_interrupt *intr =
2890 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2892 igbvf_intr_disable(hw);
2894 /* read-on-clear nic registers here */
2895 eicr = E1000_READ_REG(hw, E1000_EICR);
2898 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2899 intr->flags |= E1000_FLAG_MAILBOX;
2904 void igbvf_mbx_process(struct rte_eth_dev *dev)
2906 struct e1000_hw *hw =
2907 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2908 struct e1000_mbx_info *mbx = &hw->mbx;
2911 /* peek the message first */
2912 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2914 /* PF reset VF event */
2915 if (in_msg == E1000_PF_CONTROL_MSG) {
2916 /* dummy mbx read to ack pf */
2917 if (mbx->ops.read(hw, &in_msg, 1, 0))
2919 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2925 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2927 struct e1000_interrupt *intr =
2928 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2930 if (intr->flags & E1000_FLAG_MAILBOX) {
2931 igbvf_mbx_process(dev);
2932 intr->flags &= ~E1000_FLAG_MAILBOX;
2935 igbvf_intr_enable(dev);
2936 rte_intr_enable(intr_handle);
2942 eth_igbvf_interrupt_handler(void *param)
2944 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2946 eth_igbvf_interrupt_get_status(dev);
2947 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2951 eth_igb_led_on(struct rte_eth_dev *dev)
2953 struct e1000_hw *hw;
2955 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2956 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2960 eth_igb_led_off(struct rte_eth_dev *dev)
2962 struct e1000_hw *hw;
2964 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2965 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2969 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2971 struct e1000_hw *hw;
2976 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2977 fc_conf->pause_time = hw->fc.pause_time;
2978 fc_conf->high_water = hw->fc.high_water;
2979 fc_conf->low_water = hw->fc.low_water;
2980 fc_conf->send_xon = hw->fc.send_xon;
2981 fc_conf->autoneg = hw->mac.autoneg;
2984 * Return rx_pause and tx_pause status according to actual setting of
2985 * the TFCE and RFCE bits in the CTRL register.
2987 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2988 if (ctrl & E1000_CTRL_TFCE)
2993 if (ctrl & E1000_CTRL_RFCE)
2998 if (rx_pause && tx_pause)
2999 fc_conf->mode = RTE_FC_FULL;
3001 fc_conf->mode = RTE_FC_RX_PAUSE;
3003 fc_conf->mode = RTE_FC_TX_PAUSE;
3005 fc_conf->mode = RTE_FC_NONE;
3011 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3013 struct e1000_hw *hw;
3015 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3021 uint32_t rx_buf_size;
3022 uint32_t max_high_water;
3025 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3026 if (fc_conf->autoneg != hw->mac.autoneg)
3028 rx_buf_size = igb_get_rx_buffer_size(hw);
3029 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3031 /* At least reserve one Ethernet frame for watermark */
3032 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3033 if ((fc_conf->high_water > max_high_water) ||
3034 (fc_conf->high_water < fc_conf->low_water)) {
3035 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3036 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3040 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3041 hw->fc.pause_time = fc_conf->pause_time;
3042 hw->fc.high_water = fc_conf->high_water;
3043 hw->fc.low_water = fc_conf->low_water;
3044 hw->fc.send_xon = fc_conf->send_xon;
3046 err = e1000_setup_link_generic(hw);
3047 if (err == E1000_SUCCESS) {
3049 /* check if we want to forward MAC frames - driver doesn't have native
3050 * capability to do that, so we'll write the registers ourselves */
3052 rctl = E1000_READ_REG(hw, E1000_RCTL);
3054 /* set or clear MFLCN.PMCF bit depending on configuration */
3055 if (fc_conf->mac_ctrl_frame_fwd != 0)
3056 rctl |= E1000_RCTL_PMCF;
3058 rctl &= ~E1000_RCTL_PMCF;
3060 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3061 E1000_WRITE_FLUSH(hw);
3066 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3070 #define E1000_RAH_POOLSEL_SHIFT (18)
3072 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3073 uint32_t index, uint32_t pool)
3075 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3079 rah = E1000_READ_REG(hw, E1000_RAH(index));
3080 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3081 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3086 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3088 uint8_t addr[ETHER_ADDR_LEN];
3089 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091 memset(addr, 0, sizeof(addr));
3093 e1000_rar_set(hw, addr, index);
3097 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3098 struct ether_addr *addr)
3100 eth_igb_rar_clear(dev, 0);
3101 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3106 * Virtual Function operations
3109 igbvf_intr_disable(struct e1000_hw *hw)
3111 PMD_INIT_FUNC_TRACE();
3113 /* Clear interrupt mask to stop from interrupts being generated */
3114 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3116 E1000_WRITE_FLUSH(hw);
3120 igbvf_stop_adapter(struct rte_eth_dev *dev)
3124 struct rte_eth_dev_info dev_info;
3125 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3127 memset(&dev_info, 0, sizeof(dev_info));
3128 eth_igbvf_infos_get(dev, &dev_info);
3130 /* Clear interrupt mask to stop from interrupts being generated */
3131 igbvf_intr_disable(hw);
3133 /* Clear any pending interrupts, flush previous writes */
3134 E1000_READ_REG(hw, E1000_EICR);
3136 /* Disable the transmit unit. Each queue must be disabled. */
3137 for (i = 0; i < dev_info.max_tx_queues; i++)
3138 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3140 /* Disable the receive unit by stopping each queue */
3141 for (i = 0; i < dev_info.max_rx_queues; i++) {
3142 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3143 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3144 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3145 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3149 /* flush all queues disables */
3150 E1000_WRITE_FLUSH(hw);
3154 static int eth_igbvf_link_update(struct e1000_hw *hw)
3156 struct e1000_mbx_info *mbx = &hw->mbx;
3157 struct e1000_mac_info *mac = &hw->mac;
3158 int ret_val = E1000_SUCCESS;
3160 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3163 * We only want to run this if there has been a rst asserted.
3164 * in this case that could mean a link change, device reset,
3165 * or a virtual function reset
3168 /* If we were hit with a reset or timeout drop the link */
3169 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3170 mac->get_link_status = TRUE;
3172 if (!mac->get_link_status)
3175 /* if link status is down no point in checking to see if pf is up */
3176 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3179 /* if we passed all the tests above then the link is up and we no
3180 * longer need to check for link */
3181 mac->get_link_status = FALSE;
3189 igbvf_dev_configure(struct rte_eth_dev *dev)
3191 struct rte_eth_conf* conf = &dev->data->dev_conf;
3193 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3194 dev->data->port_id);
3197 * VF has no ability to enable/disable HW CRC
3198 * Keep the persistent behavior the same as Host PF
3200 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3201 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
3202 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3203 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
3206 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
3207 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3208 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
3216 igbvf_dev_start(struct rte_eth_dev *dev)
3218 struct e1000_hw *hw =
3219 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3220 struct e1000_adapter *adapter =
3221 E1000_DEV_PRIVATE(dev->data->dev_private);
3222 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3223 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3225 uint32_t intr_vector = 0;
3227 PMD_INIT_FUNC_TRACE();
3229 hw->mac.ops.reset_hw(hw);
3230 adapter->stopped = 0;
3233 igbvf_set_vfta_all(dev,1);
3235 eth_igbvf_tx_init(dev);
3237 /* This can fail when allocating mbufs for descriptor rings */
3238 ret = eth_igbvf_rx_init(dev);
3240 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3241 igb_dev_clear_queues(dev);
3245 /* check and configure queue intr-vector mapping */
3246 if (rte_intr_cap_multiple(intr_handle) &&
3247 dev->data->dev_conf.intr_conf.rxq) {
3248 intr_vector = dev->data->nb_rx_queues;
3249 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3254 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3255 intr_handle->intr_vec =
3256 rte_zmalloc("intr_vec",
3257 dev->data->nb_rx_queues * sizeof(int), 0);
3258 if (!intr_handle->intr_vec) {
3259 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3260 " intr_vec", dev->data->nb_rx_queues);
3265 eth_igbvf_configure_msix_intr(dev);
3267 /* enable uio/vfio intr/eventfd mapping */
3268 rte_intr_enable(intr_handle);
3270 /* resume enabled intr since hw reset */
3271 igbvf_intr_enable(dev);
3277 igbvf_dev_stop(struct rte_eth_dev *dev)
3279 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3280 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3282 PMD_INIT_FUNC_TRACE();
3284 igbvf_stop_adapter(dev);
3287 * Clear what we set, but we still keep shadow_vfta to
3288 * restore after device starts
3290 igbvf_set_vfta_all(dev,0);
3292 igb_dev_clear_queues(dev);
3294 /* disable intr eventfd mapping */
3295 rte_intr_disable(intr_handle);
3297 /* Clean datapath event and queue/vec mapping */
3298 rte_intr_efd_disable(intr_handle);
3299 if (intr_handle->intr_vec) {
3300 rte_free(intr_handle->intr_vec);
3301 intr_handle->intr_vec = NULL;
3306 igbvf_dev_close(struct rte_eth_dev *dev)
3308 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3309 struct e1000_adapter *adapter =
3310 E1000_DEV_PRIVATE(dev->data->dev_private);
3311 struct ether_addr addr;
3313 PMD_INIT_FUNC_TRACE();
3317 igbvf_dev_stop(dev);
3318 adapter->stopped = 1;
3319 igb_dev_free_queues(dev);
3322 * reprogram the RAR with a zero mac address,
3323 * to ensure that the VF traffic goes to the PF
3324 * after stop, close and detach of the VF.
3327 memset(&addr, 0, sizeof(addr));
3328 igbvf_default_mac_addr_set(dev, &addr);
3332 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3334 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336 /* Set both unicast and multicast promisc */
3337 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3341 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3343 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3345 /* If in allmulticast mode leave multicast promisc */
3346 if (dev->data->all_multicast == 1)
3347 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3349 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3353 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3355 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3357 /* In promiscuous mode multicast promisc already set */
3358 if (dev->data->promiscuous == 0)
3359 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3363 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3365 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3367 /* In promiscuous mode leave multicast promisc enabled */
3368 if (dev->data->promiscuous == 0)
3369 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3372 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3374 struct e1000_mbx_info *mbx = &hw->mbx;
3378 /* After set vlan, vlan strip will also be enabled in igb driver*/
3379 msgbuf[0] = E1000_VF_SET_VLAN;
3381 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3383 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3385 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3389 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3393 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3394 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3401 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3403 struct e1000_hw *hw =
3404 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405 struct e1000_vfta * shadow_vfta =
3406 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3407 int i = 0, j = 0, vfta = 0, mask = 1;
3409 for (i = 0; i < IGB_VFTA_SIZE; i++){
3410 vfta = shadow_vfta->vfta[i];
3413 for (j = 0; j < 32; j++){
3416 (uint16_t)((i<<5)+j), on);
3425 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3427 struct e1000_hw *hw =
3428 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3429 struct e1000_vfta * shadow_vfta =
3430 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3431 uint32_t vid_idx = 0;
3432 uint32_t vid_bit = 0;
3435 PMD_INIT_FUNC_TRACE();
3437 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3438 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3440 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3443 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3444 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3446 /*Save what we set and retore it after device reset*/
3448 shadow_vfta->vfta[vid_idx] |= vid_bit;
3450 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3456 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3458 struct e1000_hw *hw =
3459 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3461 /* index is not used by rar_set() */
3462 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3468 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3469 struct rte_eth_rss_reta_entry64 *reta_conf,
3474 uint16_t idx, shift;
3475 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3477 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3478 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3479 "(%d) doesn't match the number hardware can supported "
3480 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3484 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3485 idx = i / RTE_RETA_GROUP_SIZE;
3486 shift = i % RTE_RETA_GROUP_SIZE;
3487 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3491 if (mask == IGB_4_BIT_MASK)
3494 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3495 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3496 if (mask & (0x1 << j))
3497 reta |= reta_conf[idx].reta[shift + j] <<
3500 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3502 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3509 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3510 struct rte_eth_rss_reta_entry64 *reta_conf,
3515 uint16_t idx, shift;
3516 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3519 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3520 "(%d) doesn't match the number hardware can supported "
3521 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3525 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3526 idx = i / RTE_RETA_GROUP_SIZE;
3527 shift = i % RTE_RETA_GROUP_SIZE;
3528 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3532 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3533 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3534 if (mask & (0x1 << j))
3535 reta_conf[idx].reta[shift + j] =
3536 ((reta >> (CHAR_BIT * j)) &
3545 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3546 struct rte_eth_syn_filter *filter,
3549 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3550 struct e1000_filter_info *filter_info =
3551 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3552 uint32_t synqf, rfctl;
3554 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3557 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3560 if (synqf & E1000_SYN_FILTER_ENABLE)
3563 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3564 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3566 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3567 if (filter->hig_pri)
3568 rfctl |= E1000_RFCTL_SYNQFP;
3570 rfctl &= ~E1000_RFCTL_SYNQFP;
3572 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3574 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3579 filter_info->syn_info = synqf;
3580 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3581 E1000_WRITE_FLUSH(hw);
3586 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3587 struct rte_eth_syn_filter *filter)
3589 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3590 uint32_t synqf, rfctl;
3592 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3593 if (synqf & E1000_SYN_FILTER_ENABLE) {
3594 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3595 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3596 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3597 E1000_SYN_FILTER_QUEUE_SHIFT);
3605 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3606 enum rte_filter_op filter_op,
3609 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612 MAC_TYPE_FILTER_SUP(hw->mac.type);
3614 if (filter_op == RTE_ETH_FILTER_NOP)
3618 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3623 switch (filter_op) {
3624 case RTE_ETH_FILTER_ADD:
3625 ret = eth_igb_syn_filter_set(dev,
3626 (struct rte_eth_syn_filter *)arg,
3629 case RTE_ETH_FILTER_DELETE:
3630 ret = eth_igb_syn_filter_set(dev,
3631 (struct rte_eth_syn_filter *)arg,
3634 case RTE_ETH_FILTER_GET:
3635 ret = eth_igb_syn_filter_get(dev,
3636 (struct rte_eth_syn_filter *)arg);
3639 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3647 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3649 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3650 struct e1000_2tuple_filter_info *filter_info)
3652 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3654 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3655 return -EINVAL; /* filter index is out of range. */
3656 if (filter->tcp_flags > TCP_FLAG_ALL)
3657 return -EINVAL; /* flags is invalid. */
3659 switch (filter->dst_port_mask) {
3661 filter_info->dst_port_mask = 0;
3662 filter_info->dst_port = filter->dst_port;
3665 filter_info->dst_port_mask = 1;
3668 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3672 switch (filter->proto_mask) {
3674 filter_info->proto_mask = 0;
3675 filter_info->proto = filter->proto;
3678 filter_info->proto_mask = 1;
3681 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3685 filter_info->priority = (uint8_t)filter->priority;
3686 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3687 filter_info->tcp_flags = filter->tcp_flags;
3689 filter_info->tcp_flags = 0;
3694 static inline struct e1000_2tuple_filter *
3695 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3696 struct e1000_2tuple_filter_info *key)
3698 struct e1000_2tuple_filter *it;
3700 TAILQ_FOREACH(it, filter_list, entries) {
3701 if (memcmp(key, &it->filter_info,
3702 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3709 /* inject a igb 2tuple filter to HW */
3711 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3712 struct e1000_2tuple_filter *filter)
3714 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3715 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3716 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3720 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3721 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3722 imir |= E1000_IMIR_PORT_BP;
3724 imir &= ~E1000_IMIR_PORT_BP;
3726 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3728 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3729 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3730 ttqf |= (uint32_t)(filter->filter_info.proto &
3731 E1000_TTQF_PROTOCOL_MASK);
3732 if (filter->filter_info.proto_mask == 0)
3733 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3735 /* tcp flags bits setting. */
3736 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3737 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3738 imir_ext |= E1000_IMIREXT_CTRL_URG;
3739 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3740 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3741 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3742 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3743 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3744 imir_ext |= E1000_IMIREXT_CTRL_RST;
3745 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3746 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3747 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3748 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3750 imir_ext |= E1000_IMIREXT_CTRL_BP;
3752 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3753 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3754 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3758 * igb_add_2tuple_filter - add a 2tuple filter
3761 * dev: Pointer to struct rte_eth_dev.
3762 * ntuple_filter: ponter to the filter that will be added.
3765 * - On success, zero.
3766 * - On failure, a negative value.
3769 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3770 struct rte_eth_ntuple_filter *ntuple_filter)
3772 struct e1000_filter_info *filter_info =
3773 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3774 struct e1000_2tuple_filter *filter;
3777 filter = rte_zmalloc("e1000_2tuple_filter",
3778 sizeof(struct e1000_2tuple_filter), 0);
3782 ret = ntuple_filter_to_2tuple(ntuple_filter,
3783 &filter->filter_info);
3788 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3789 &filter->filter_info) != NULL) {
3790 PMD_DRV_LOG(ERR, "filter exists.");
3794 filter->queue = ntuple_filter->queue;
3797 * look for an unused 2tuple filter index,
3798 * and insert the filter to list.
3800 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3801 if (!(filter_info->twotuple_mask & (1 << i))) {
3802 filter_info->twotuple_mask |= 1 << i;
3804 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3810 if (i >= E1000_MAX_TTQF_FILTERS) {
3811 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3816 igb_inject_2uple_filter(dev, filter);
3821 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3822 struct e1000_2tuple_filter *filter)
3824 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3825 struct e1000_filter_info *filter_info =
3826 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3828 filter_info->twotuple_mask &= ~(1 << filter->index);
3829 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3832 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3833 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3834 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3839 * igb_remove_2tuple_filter - remove a 2tuple filter
3842 * dev: Pointer to struct rte_eth_dev.
3843 * ntuple_filter: ponter to the filter that will be removed.
3846 * - On success, zero.
3847 * - On failure, a negative value.
3850 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3851 struct rte_eth_ntuple_filter *ntuple_filter)
3853 struct e1000_filter_info *filter_info =
3854 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3855 struct e1000_2tuple_filter_info filter_2tuple;
3856 struct e1000_2tuple_filter *filter;
3859 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3860 ret = ntuple_filter_to_2tuple(ntuple_filter,
3865 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3867 if (filter == NULL) {
3868 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3872 igb_delete_2tuple_filter(dev, filter);
3877 /* inject a igb flex filter to HW */
3879 igb_inject_flex_filter(struct rte_eth_dev *dev,
3880 struct e1000_flex_filter *filter)
3882 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3883 uint32_t wufc, queueing;
3887 wufc = E1000_READ_REG(hw, E1000_WUFC);
3888 if (filter->index < E1000_MAX_FHFT)
3889 reg_off = E1000_FHFT(filter->index);
3891 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3893 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3894 (E1000_WUFC_FLX0 << filter->index));
3895 queueing = filter->filter_info.len |
3896 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3897 (filter->filter_info.priority <<
3898 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3899 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3902 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3903 E1000_WRITE_REG(hw, reg_off,
3904 filter->filter_info.dwords[j]);
3905 reg_off += sizeof(uint32_t);
3906 E1000_WRITE_REG(hw, reg_off,
3907 filter->filter_info.dwords[++j]);
3908 reg_off += sizeof(uint32_t);
3909 E1000_WRITE_REG(hw, reg_off,
3910 (uint32_t)filter->filter_info.mask[i]);
3911 reg_off += sizeof(uint32_t) * 2;
3916 static inline struct e1000_flex_filter *
3917 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3918 struct e1000_flex_filter_info *key)
3920 struct e1000_flex_filter *it;
3922 TAILQ_FOREACH(it, filter_list, entries) {
3923 if (memcmp(key, &it->filter_info,
3924 sizeof(struct e1000_flex_filter_info)) == 0)
3931 /* remove a flex byte filter
3933 * dev: Pointer to struct rte_eth_dev.
3934 * filter: the pointer of the filter will be removed.
3937 igb_remove_flex_filter(struct rte_eth_dev *dev,
3938 struct e1000_flex_filter *filter)
3940 struct e1000_filter_info *filter_info =
3941 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3942 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946 wufc = E1000_READ_REG(hw, E1000_WUFC);
3947 if (filter->index < E1000_MAX_FHFT)
3948 reg_off = E1000_FHFT(filter->index);
3950 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3952 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3953 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3955 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3956 (~(E1000_WUFC_FLX0 << filter->index)));
3958 filter_info->flex_mask &= ~(1 << filter->index);
3959 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3964 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3965 struct rte_eth_flex_filter *filter,
3968 struct e1000_filter_info *filter_info =
3969 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3970 struct e1000_flex_filter *flex_filter, *it;
3974 flex_filter = rte_zmalloc("e1000_flex_filter",
3975 sizeof(struct e1000_flex_filter), 0);
3976 if (flex_filter == NULL)
3979 flex_filter->filter_info.len = filter->len;
3980 flex_filter->filter_info.priority = filter->priority;
3981 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3982 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3984 /* reverse bits in flex filter's mask*/
3985 for (shift = 0; shift < CHAR_BIT; shift++) {
3986 if (filter->mask[i] & (0x01 << shift))
3987 mask |= (0x80 >> shift);
3989 flex_filter->filter_info.mask[i] = mask;
3992 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3993 &flex_filter->filter_info);
3994 if (it == NULL && !add) {
3995 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3996 rte_free(flex_filter);
3999 if (it != NULL && add) {
4000 PMD_DRV_LOG(ERR, "filter exists.");
4001 rte_free(flex_filter);
4006 flex_filter->queue = filter->queue;
4008 * look for an unused flex filter index
4009 * and insert the filter into the list.
4011 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4012 if (!(filter_info->flex_mask & (1 << i))) {
4013 filter_info->flex_mask |= 1 << i;
4014 flex_filter->index = i;
4015 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4021 if (i >= E1000_MAX_FLEX_FILTERS) {
4022 PMD_DRV_LOG(ERR, "flex filters are full.");
4023 rte_free(flex_filter);
4027 igb_inject_flex_filter(dev, flex_filter);
4030 igb_remove_flex_filter(dev, it);
4031 rte_free(flex_filter);
4038 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4039 struct rte_eth_flex_filter *filter)
4041 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4042 struct e1000_filter_info *filter_info =
4043 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4044 struct e1000_flex_filter flex_filter, *it;
4045 uint32_t wufc, queueing, wufc_en = 0;
4047 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4048 flex_filter.filter_info.len = filter->len;
4049 flex_filter.filter_info.priority = filter->priority;
4050 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4051 memcpy(flex_filter.filter_info.mask, filter->mask,
4052 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4054 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4055 &flex_filter.filter_info);
4057 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4061 wufc = E1000_READ_REG(hw, E1000_WUFC);
4062 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4064 if ((wufc & wufc_en) == wufc_en) {
4065 uint32_t reg_off = 0;
4066 if (it->index < E1000_MAX_FHFT)
4067 reg_off = E1000_FHFT(it->index);
4069 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4071 queueing = E1000_READ_REG(hw,
4072 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4073 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4074 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4075 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4076 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4077 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4084 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4085 enum rte_filter_op filter_op,
4088 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4089 struct rte_eth_flex_filter *filter;
4092 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4094 if (filter_op == RTE_ETH_FILTER_NOP)
4098 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4103 filter = (struct rte_eth_flex_filter *)arg;
4104 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4105 || filter->len % sizeof(uint64_t) != 0) {
4106 PMD_DRV_LOG(ERR, "filter's length is out of range");
4109 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4110 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4114 switch (filter_op) {
4115 case RTE_ETH_FILTER_ADD:
4116 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4118 case RTE_ETH_FILTER_DELETE:
4119 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4121 case RTE_ETH_FILTER_GET:
4122 ret = eth_igb_get_flex_filter(dev, filter);
4125 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4133 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4135 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4136 struct e1000_5tuple_filter_info *filter_info)
4138 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4140 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4141 return -EINVAL; /* filter index is out of range. */
4142 if (filter->tcp_flags > TCP_FLAG_ALL)
4143 return -EINVAL; /* flags is invalid. */
4145 switch (filter->dst_ip_mask) {
4147 filter_info->dst_ip_mask = 0;
4148 filter_info->dst_ip = filter->dst_ip;
4151 filter_info->dst_ip_mask = 1;
4154 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4158 switch (filter->src_ip_mask) {
4160 filter_info->src_ip_mask = 0;
4161 filter_info->src_ip = filter->src_ip;
4164 filter_info->src_ip_mask = 1;
4167 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4171 switch (filter->dst_port_mask) {
4173 filter_info->dst_port_mask = 0;
4174 filter_info->dst_port = filter->dst_port;
4177 filter_info->dst_port_mask = 1;
4180 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4184 switch (filter->src_port_mask) {
4186 filter_info->src_port_mask = 0;
4187 filter_info->src_port = filter->src_port;
4190 filter_info->src_port_mask = 1;
4193 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4197 switch (filter->proto_mask) {
4199 filter_info->proto_mask = 0;
4200 filter_info->proto = filter->proto;
4203 filter_info->proto_mask = 1;
4206 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4210 filter_info->priority = (uint8_t)filter->priority;
4211 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4212 filter_info->tcp_flags = filter->tcp_flags;
4214 filter_info->tcp_flags = 0;
4219 static inline struct e1000_5tuple_filter *
4220 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4221 struct e1000_5tuple_filter_info *key)
4223 struct e1000_5tuple_filter *it;
4225 TAILQ_FOREACH(it, filter_list, entries) {
4226 if (memcmp(key, &it->filter_info,
4227 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4234 /* inject a igb 5-tuple filter to HW */
4236 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4237 struct e1000_5tuple_filter *filter)
4239 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4240 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4241 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4245 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4246 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4247 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4248 if (filter->filter_info.dst_ip_mask == 0)
4249 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4250 if (filter->filter_info.src_port_mask == 0)
4251 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4252 if (filter->filter_info.proto_mask == 0)
4253 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4254 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4255 E1000_FTQF_QUEUE_MASK;
4256 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4257 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4258 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4259 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4261 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4262 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4264 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4265 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4266 imir |= E1000_IMIR_PORT_BP;
4268 imir &= ~E1000_IMIR_PORT_BP;
4269 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4271 /* tcp flags bits setting. */
4272 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4273 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4274 imir_ext |= E1000_IMIREXT_CTRL_URG;
4275 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4276 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4277 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4278 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4279 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4280 imir_ext |= E1000_IMIREXT_CTRL_RST;
4281 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4282 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4283 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4284 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4286 imir_ext |= E1000_IMIREXT_CTRL_BP;
4288 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4289 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4293 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4296 * dev: Pointer to struct rte_eth_dev.
4297 * ntuple_filter: ponter to the filter that will be added.
4300 * - On success, zero.
4301 * - On failure, a negative value.
4304 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4305 struct rte_eth_ntuple_filter *ntuple_filter)
4307 struct e1000_filter_info *filter_info =
4308 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4309 struct e1000_5tuple_filter *filter;
4313 filter = rte_zmalloc("e1000_5tuple_filter",
4314 sizeof(struct e1000_5tuple_filter), 0);
4318 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4319 &filter->filter_info);
4325 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4326 &filter->filter_info) != NULL) {
4327 PMD_DRV_LOG(ERR, "filter exists.");
4331 filter->queue = ntuple_filter->queue;
4334 * look for an unused 5tuple filter index,
4335 * and insert the filter to list.
4337 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4338 if (!(filter_info->fivetuple_mask & (1 << i))) {
4339 filter_info->fivetuple_mask |= 1 << i;
4341 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4347 if (i >= E1000_MAX_FTQF_FILTERS) {
4348 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4353 igb_inject_5tuple_filter_82576(dev, filter);
4358 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4359 struct e1000_5tuple_filter *filter)
4361 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362 struct e1000_filter_info *filter_info =
4363 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4365 filter_info->fivetuple_mask &= ~(1 << filter->index);
4366 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4369 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4370 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4371 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4372 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4373 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4374 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4375 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4380 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4383 * dev: Pointer to struct rte_eth_dev.
4384 * ntuple_filter: ponter to the filter that will be removed.
4387 * - On success, zero.
4388 * - On failure, a negative value.
4391 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4392 struct rte_eth_ntuple_filter *ntuple_filter)
4394 struct e1000_filter_info *filter_info =
4395 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4396 struct e1000_5tuple_filter_info filter_5tuple;
4397 struct e1000_5tuple_filter *filter;
4400 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4401 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4406 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4408 if (filter == NULL) {
4409 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4413 igb_delete_5tuple_filter_82576(dev, filter);
4419 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4422 struct e1000_hw *hw;
4423 struct rte_eth_dev_info dev_info;
4424 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4427 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4429 #ifdef RTE_LIBRTE_82571_SUPPORT
4430 /* XXX: not bigger than max_rx_pktlen */
4431 if (hw->mac.type == e1000_82571)
4434 eth_igb_infos_get(dev, &dev_info);
4436 /* check that mtu is within the allowed range */
4437 if ((mtu < ETHER_MIN_MTU) ||
4438 (frame_size > dev_info.max_rx_pktlen))
4441 /* refuse mtu that requires the support of scattered packets when this
4442 * feature has not been enabled before. */
4443 if (!dev->data->scattered_rx &&
4444 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4447 rctl = E1000_READ_REG(hw, E1000_RCTL);
4449 /* switch to jumbo mode if needed */
4450 if (frame_size > ETHER_MAX_LEN) {
4451 dev->data->dev_conf.rxmode.offloads |=
4452 DEV_RX_OFFLOAD_JUMBO_FRAME;
4453 rctl |= E1000_RCTL_LPE;
4455 dev->data->dev_conf.rxmode.offloads &=
4456 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4457 rctl &= ~E1000_RCTL_LPE;
4459 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4461 /* update max frame size */
4462 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4464 E1000_WRITE_REG(hw, E1000_RLPML,
4465 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4471 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4474 * dev: Pointer to struct rte_eth_dev.
4475 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4476 * add: if true, add filter, if false, remove filter
4479 * - On success, zero.
4480 * - On failure, a negative value.
4483 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4484 struct rte_eth_ntuple_filter *ntuple_filter,
4487 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4490 switch (ntuple_filter->flags) {
4491 case RTE_5TUPLE_FLAGS:
4492 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4493 if (hw->mac.type != e1000_82576)
4496 ret = igb_add_5tuple_filter_82576(dev,
4499 ret = igb_remove_5tuple_filter_82576(dev,
4502 case RTE_2TUPLE_FLAGS:
4503 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4504 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4505 hw->mac.type != e1000_i210 &&
4506 hw->mac.type != e1000_i211)
4509 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4511 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4522 * igb_get_ntuple_filter - get a ntuple filter
4525 * dev: Pointer to struct rte_eth_dev.
4526 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4529 * - On success, zero.
4530 * - On failure, a negative value.
4533 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4534 struct rte_eth_ntuple_filter *ntuple_filter)
4536 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4537 struct e1000_filter_info *filter_info =
4538 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4539 struct e1000_5tuple_filter_info filter_5tuple;
4540 struct e1000_2tuple_filter_info filter_2tuple;
4541 struct e1000_5tuple_filter *p_5tuple_filter;
4542 struct e1000_2tuple_filter *p_2tuple_filter;
4545 switch (ntuple_filter->flags) {
4546 case RTE_5TUPLE_FLAGS:
4547 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4548 if (hw->mac.type != e1000_82576)
4550 memset(&filter_5tuple,
4552 sizeof(struct e1000_5tuple_filter_info));
4553 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4557 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4558 &filter_info->fivetuple_list,
4560 if (p_5tuple_filter == NULL) {
4561 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4564 ntuple_filter->queue = p_5tuple_filter->queue;
4566 case RTE_2TUPLE_FLAGS:
4567 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4568 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4570 memset(&filter_2tuple,
4572 sizeof(struct e1000_2tuple_filter_info));
4573 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4576 p_2tuple_filter = igb_2tuple_filter_lookup(
4577 &filter_info->twotuple_list,
4579 if (p_2tuple_filter == NULL) {
4580 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4583 ntuple_filter->queue = p_2tuple_filter->queue;
4594 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4595 * @dev: pointer to rte_eth_dev structure
4596 * @filter_op:operation will be taken.
4597 * @arg: a pointer to specific structure corresponding to the filter_op
4600 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4601 enum rte_filter_op filter_op,
4604 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4607 MAC_TYPE_FILTER_SUP(hw->mac.type);
4609 if (filter_op == RTE_ETH_FILTER_NOP)
4613 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4618 switch (filter_op) {
4619 case RTE_ETH_FILTER_ADD:
4620 ret = igb_add_del_ntuple_filter(dev,
4621 (struct rte_eth_ntuple_filter *)arg,
4624 case RTE_ETH_FILTER_DELETE:
4625 ret = igb_add_del_ntuple_filter(dev,
4626 (struct rte_eth_ntuple_filter *)arg,
4629 case RTE_ETH_FILTER_GET:
4630 ret = igb_get_ntuple_filter(dev,
4631 (struct rte_eth_ntuple_filter *)arg);
4634 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4642 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4647 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4648 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4649 (filter_info->ethertype_mask & (1 << i)))
4656 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4657 uint16_t ethertype, uint32_t etqf)
4661 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4662 if (!(filter_info->ethertype_mask & (1 << i))) {
4663 filter_info->ethertype_mask |= 1 << i;
4664 filter_info->ethertype_filters[i].ethertype = ethertype;
4665 filter_info->ethertype_filters[i].etqf = etqf;
4673 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4676 if (idx >= E1000_MAX_ETQF_FILTERS)
4678 filter_info->ethertype_mask &= ~(1 << idx);
4679 filter_info->ethertype_filters[idx].ethertype = 0;
4680 filter_info->ethertype_filters[idx].etqf = 0;
4686 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4687 struct rte_eth_ethertype_filter *filter,
4690 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4691 struct e1000_filter_info *filter_info =
4692 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4696 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4697 filter->ether_type == ETHER_TYPE_IPv6) {
4698 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4699 " ethertype filter.", filter->ether_type);
4703 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4704 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4707 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4708 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4712 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4713 if (ret >= 0 && add) {
4714 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4715 filter->ether_type);
4718 if (ret < 0 && !add) {
4719 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4720 filter->ether_type);
4725 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4726 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4727 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4728 ret = igb_ethertype_filter_insert(filter_info,
4729 filter->ether_type, etqf);
4731 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4735 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4739 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4740 E1000_WRITE_FLUSH(hw);
4746 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4747 struct rte_eth_ethertype_filter *filter)
4749 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4750 struct e1000_filter_info *filter_info =
4751 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4755 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4757 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4758 filter->ether_type);
4762 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4763 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4764 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4766 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4767 E1000_ETQF_QUEUE_SHIFT;
4775 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4776 * @dev: pointer to rte_eth_dev structure
4777 * @filter_op:operation will be taken.
4778 * @arg: a pointer to specific structure corresponding to the filter_op
4781 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4782 enum rte_filter_op filter_op,
4785 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4788 MAC_TYPE_FILTER_SUP(hw->mac.type);
4790 if (filter_op == RTE_ETH_FILTER_NOP)
4794 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4799 switch (filter_op) {
4800 case RTE_ETH_FILTER_ADD:
4801 ret = igb_add_del_ethertype_filter(dev,
4802 (struct rte_eth_ethertype_filter *)arg,
4805 case RTE_ETH_FILTER_DELETE:
4806 ret = igb_add_del_ethertype_filter(dev,
4807 (struct rte_eth_ethertype_filter *)arg,
4810 case RTE_ETH_FILTER_GET:
4811 ret = igb_get_ethertype_filter(dev,
4812 (struct rte_eth_ethertype_filter *)arg);
4815 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4823 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4824 enum rte_filter_type filter_type,
4825 enum rte_filter_op filter_op,
4830 switch (filter_type) {
4831 case RTE_ETH_FILTER_NTUPLE:
4832 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4834 case RTE_ETH_FILTER_ETHERTYPE:
4835 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4837 case RTE_ETH_FILTER_SYN:
4838 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4840 case RTE_ETH_FILTER_FLEXIBLE:
4841 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4843 case RTE_ETH_FILTER_GENERIC:
4844 if (filter_op != RTE_ETH_FILTER_GET)
4846 *(const void **)arg = &igb_flow_ops;
4849 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4858 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4859 struct ether_addr *mc_addr_set,
4860 uint32_t nb_mc_addr)
4862 struct e1000_hw *hw;
4864 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4865 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4870 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4872 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4873 uint64_t systime_cycles;
4875 switch (hw->mac.type) {
4879 * Need to read System Time Residue Register to be able
4880 * to read the other two registers.
4882 E1000_READ_REG(hw, E1000_SYSTIMR);
4883 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4884 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4885 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4892 * Need to read System Time Residue Register to be able
4893 * to read the other two registers.
4895 E1000_READ_REG(hw, E1000_SYSTIMR);
4896 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4897 /* Only the 8 LSB are valid. */
4898 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4902 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4903 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4908 return systime_cycles;
4912 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4914 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4915 uint64_t rx_tstamp_cycles;
4917 switch (hw->mac.type) {
4920 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4921 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4922 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4928 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4929 /* Only the 8 LSB are valid. */
4930 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4934 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4935 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4940 return rx_tstamp_cycles;
4944 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4946 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4947 uint64_t tx_tstamp_cycles;
4949 switch (hw->mac.type) {
4952 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4953 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4954 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4960 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4961 /* Only the 8 LSB are valid. */
4962 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4966 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4967 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4972 return tx_tstamp_cycles;
4976 igb_start_timecounters(struct rte_eth_dev *dev)
4978 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4979 struct e1000_adapter *adapter =
4980 (struct e1000_adapter *)dev->data->dev_private;
4981 uint32_t incval = 1;
4983 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4985 switch (hw->mac.type) {
4989 /* 32 LSB bits + 8 MSB bits = 40 bits */
4990 mask = (1ULL << 40) - 1;
4995 * Start incrementing the register
4996 * used to timestamp PTP packets.
4998 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5001 incval = E1000_INCVALUE_82576;
5002 shift = IGB_82576_TSYNC_SHIFT;
5003 E1000_WRITE_REG(hw, E1000_TIMINCA,
5004 E1000_INCPERIOD_82576 | incval);
5011 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5012 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5013 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5015 adapter->systime_tc.cc_mask = mask;
5016 adapter->systime_tc.cc_shift = shift;
5017 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5019 adapter->rx_tstamp_tc.cc_mask = mask;
5020 adapter->rx_tstamp_tc.cc_shift = shift;
5021 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5023 adapter->tx_tstamp_tc.cc_mask = mask;
5024 adapter->tx_tstamp_tc.cc_shift = shift;
5025 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5029 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5031 struct e1000_adapter *adapter =
5032 (struct e1000_adapter *)dev->data->dev_private;
5034 adapter->systime_tc.nsec += delta;
5035 adapter->rx_tstamp_tc.nsec += delta;
5036 adapter->tx_tstamp_tc.nsec += delta;
5042 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5045 struct e1000_adapter *adapter =
5046 (struct e1000_adapter *)dev->data->dev_private;
5048 ns = rte_timespec_to_ns(ts);
5050 /* Set the timecounters to a new value. */
5051 adapter->systime_tc.nsec = ns;
5052 adapter->rx_tstamp_tc.nsec = ns;
5053 adapter->tx_tstamp_tc.nsec = ns;
5059 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5061 uint64_t ns, systime_cycles;
5062 struct e1000_adapter *adapter =
5063 (struct e1000_adapter *)dev->data->dev_private;
5065 systime_cycles = igb_read_systime_cyclecounter(dev);
5066 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5067 *ts = rte_ns_to_timespec(ns);
5073 igb_timesync_enable(struct rte_eth_dev *dev)
5075 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5079 /* Stop the timesync system time. */
5080 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5081 /* Reset the timesync system time value. */
5082 switch (hw->mac.type) {
5088 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5091 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5092 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5095 /* Not supported. */
5099 /* Enable system time for it isn't on by default. */
5100 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5101 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5102 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5104 igb_start_timecounters(dev);
5106 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5107 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5109 E1000_ETQF_FILTER_ENABLE |
5112 /* Enable timestamping of received PTP packets. */
5113 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5114 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5115 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5117 /* Enable Timestamping of transmitted PTP packets. */
5118 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5119 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5120 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5126 igb_timesync_disable(struct rte_eth_dev *dev)
5128 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131 /* Disable timestamping of transmitted PTP packets. */
5132 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5133 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5134 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5136 /* Disable timestamping of received PTP packets. */
5137 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5138 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5139 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5141 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5142 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5144 /* Stop incrementating the System Time registers. */
5145 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5151 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5152 struct timespec *timestamp,
5153 uint32_t flags __rte_unused)
5155 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5156 struct e1000_adapter *adapter =
5157 (struct e1000_adapter *)dev->data->dev_private;
5158 uint32_t tsync_rxctl;
5159 uint64_t rx_tstamp_cycles;
5162 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5163 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5166 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5167 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5168 *timestamp = rte_ns_to_timespec(ns);
5174 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5175 struct timespec *timestamp)
5177 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5178 struct e1000_adapter *adapter =
5179 (struct e1000_adapter *)dev->data->dev_private;
5180 uint32_t tsync_txctl;
5181 uint64_t tx_tstamp_cycles;
5184 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5185 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5188 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5189 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5190 *timestamp = rte_ns_to_timespec(ns);
5196 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5200 const struct reg_info *reg_group;
5202 while ((reg_group = igb_regs[g_ind++]))
5203 count += igb_reg_group_count(reg_group);
5209 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5213 const struct reg_info *reg_group;
5215 while ((reg_group = igbvf_regs[g_ind++]))
5216 count += igb_reg_group_count(reg_group);
5222 eth_igb_get_regs(struct rte_eth_dev *dev,
5223 struct rte_dev_reg_info *regs)
5225 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5226 uint32_t *data = regs->data;
5229 const struct reg_info *reg_group;
5232 regs->length = eth_igb_get_reg_length(dev);
5233 regs->width = sizeof(uint32_t);
5237 /* Support only full register dump */
5238 if ((regs->length == 0) ||
5239 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5240 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5242 while ((reg_group = igb_regs[g_ind++]))
5243 count += igb_read_regs_group(dev, &data[count],
5252 igbvf_get_regs(struct rte_eth_dev *dev,
5253 struct rte_dev_reg_info *regs)
5255 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5256 uint32_t *data = regs->data;
5259 const struct reg_info *reg_group;
5262 regs->length = igbvf_get_reg_length(dev);
5263 regs->width = sizeof(uint32_t);
5267 /* Support only full register dump */
5268 if ((regs->length == 0) ||
5269 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5270 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5272 while ((reg_group = igbvf_regs[g_ind++]))
5273 count += igb_read_regs_group(dev, &data[count],
5282 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5284 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5286 /* Return unit is byte count */
5287 return hw->nvm.word_size * 2;
5291 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5292 struct rte_dev_eeprom_info *in_eeprom)
5294 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5295 struct e1000_nvm_info *nvm = &hw->nvm;
5296 uint16_t *data = in_eeprom->data;
5299 first = in_eeprom->offset >> 1;
5300 length = in_eeprom->length >> 1;
5301 if ((first >= hw->nvm.word_size) ||
5302 ((first + length) >= hw->nvm.word_size))
5305 in_eeprom->magic = hw->vendor_id |
5306 ((uint32_t)hw->device_id << 16);
5308 if ((nvm->ops.read) == NULL)
5311 return nvm->ops.read(hw, first, length, data);
5315 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5316 struct rte_dev_eeprom_info *in_eeprom)
5318 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5319 struct e1000_nvm_info *nvm = &hw->nvm;
5320 uint16_t *data = in_eeprom->data;
5323 first = in_eeprom->offset >> 1;
5324 length = in_eeprom->length >> 1;
5325 if ((first >= hw->nvm.word_size) ||
5326 ((first + length) >= hw->nvm.word_size))
5329 in_eeprom->magic = (uint32_t)hw->vendor_id |
5330 ((uint32_t)hw->device_id << 16);
5332 if ((nvm->ops.write) == NULL)
5334 return nvm->ops.write(hw, first, length, data);
5338 eth_igb_get_module_info(struct rte_eth_dev *dev,
5339 struct rte_eth_dev_module_info *modinfo)
5341 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343 uint32_t status = 0;
5344 uint16_t sff8472_rev, addr_mode;
5345 bool page_swap = false;
5347 if (hw->phy.media_type == e1000_media_type_copper ||
5348 hw->phy.media_type == e1000_media_type_unknown)
5351 /* Check whether we support SFF-8472 or not */
5352 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5356 /* addressing mode is not supported */
5357 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5361 /* addressing mode is not supported */
5362 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5364 "Address change required to access page 0xA2, "
5365 "but not supported. Please report the module "
5366 "type to the driver maintainers.\n");
5370 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5371 /* We have an SFP, but it does not support SFF-8472 */
5372 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5373 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5375 /* We have an SFP which supports a revision of SFF-8472 */
5376 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5377 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5384 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5385 struct rte_dev_eeprom_info *info)
5387 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5389 uint32_t status = 0;
5390 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5391 u16 first_word, last_word;
5394 if (info->length == 0)
5397 first_word = info->offset >> 1;
5398 last_word = (info->offset + info->length - 1) >> 1;
5400 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5401 for (i = 0; i < last_word - first_word + 1; i++) {
5402 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5405 /* Error occurred while reading module */
5409 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5412 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5418 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5420 struct e1000_hw *hw =
5421 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5422 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5423 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5424 uint32_t vec = E1000_MISC_VEC_ID;
5426 if (rte_intr_allow_others(intr_handle))
5427 vec = E1000_RX_VEC_START;
5429 uint32_t mask = 1 << (queue_id + vec);
5431 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5432 E1000_WRITE_FLUSH(hw);
5438 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5440 struct e1000_hw *hw =
5441 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5442 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5443 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5444 uint32_t vec = E1000_MISC_VEC_ID;
5446 if (rte_intr_allow_others(intr_handle))
5447 vec = E1000_RX_VEC_START;
5449 uint32_t mask = 1 << (queue_id + vec);
5452 regval = E1000_READ_REG(hw, E1000_EIMS);
5453 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5454 E1000_WRITE_FLUSH(hw);
5456 rte_intr_enable(intr_handle);
5462 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5463 uint8_t index, uint8_t offset)
5465 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5468 val &= ~((uint32_t)0xFF << offset);
5470 /* write vector and valid bit */
5471 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5473 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5477 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5478 uint8_t queue, uint8_t msix_vector)
5482 if (hw->mac.type == e1000_82575) {
5484 tmp = E1000_EICR_RX_QUEUE0 << queue;
5485 else if (direction == 1)
5486 tmp = E1000_EICR_TX_QUEUE0 << queue;
5487 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5488 } else if (hw->mac.type == e1000_82576) {
5489 if ((direction == 0) || (direction == 1))
5490 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5491 ((queue & 0x8) << 1) +
5493 } else if ((hw->mac.type == e1000_82580) ||
5494 (hw->mac.type == e1000_i350) ||
5495 (hw->mac.type == e1000_i354) ||
5496 (hw->mac.type == e1000_i210) ||
5497 (hw->mac.type == e1000_i211)) {
5498 if ((direction == 0) || (direction == 1))
5499 eth_igb_write_ivar(hw, msix_vector,
5501 ((queue & 0x1) << 4) +
5506 /* Sets up the hardware to generate MSI-X interrupts properly
5508 * board private structure
5511 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5514 uint32_t tmpval, regval, intr_mask;
5515 struct e1000_hw *hw =
5516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5517 uint32_t vec = E1000_MISC_VEC_ID;
5518 uint32_t base = E1000_MISC_VEC_ID;
5519 uint32_t misc_shift = 0;
5520 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5521 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5523 /* won't configure msix register if no mapping is done
5524 * between intr vector and event fd
5526 if (!rte_intr_dp_is_en(intr_handle))
5529 if (rte_intr_allow_others(intr_handle)) {
5530 vec = base = E1000_RX_VEC_START;
5534 /* set interrupt vector for other causes */
5535 if (hw->mac.type == e1000_82575) {
5536 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5537 /* enable MSI-X PBA support */
5538 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5540 /* Auto-Mask interrupts upon ICR read */
5541 tmpval |= E1000_CTRL_EXT_EIAME;
5542 tmpval |= E1000_CTRL_EXT_IRCA;
5544 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5546 /* enable msix_other interrupt */
5547 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5548 regval = E1000_READ_REG(hw, E1000_EIAC);
5549 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5550 regval = E1000_READ_REG(hw, E1000_EIAM);
5551 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5552 } else if ((hw->mac.type == e1000_82576) ||
5553 (hw->mac.type == e1000_82580) ||
5554 (hw->mac.type == e1000_i350) ||
5555 (hw->mac.type == e1000_i354) ||
5556 (hw->mac.type == e1000_i210) ||
5557 (hw->mac.type == e1000_i211)) {
5558 /* turn on MSI-X capability first */
5559 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5560 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5562 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5564 regval = E1000_READ_REG(hw, E1000_EIAC);
5565 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5567 /* enable msix_other interrupt */
5568 regval = E1000_READ_REG(hw, E1000_EIMS);
5569 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5570 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5571 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5574 /* use EIAM to auto-mask when MSI-X interrupt
5575 * is asserted, this saves a register write for every interrupt
5577 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5579 regval = E1000_READ_REG(hw, E1000_EIAM);
5580 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5582 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5583 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5584 intr_handle->intr_vec[queue_id] = vec;
5585 if (vec < base + intr_handle->nb_efd - 1)
5589 E1000_WRITE_FLUSH(hw);
5592 /* restore n-tuple filter */
5594 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5596 struct e1000_filter_info *filter_info =
5597 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5598 struct e1000_5tuple_filter *p_5tuple;
5599 struct e1000_2tuple_filter *p_2tuple;
5601 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5602 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5605 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5606 igb_inject_2uple_filter(dev, p_2tuple);
5610 /* restore SYN filter */
5612 igb_syn_filter_restore(struct rte_eth_dev *dev)
5614 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5615 struct e1000_filter_info *filter_info =
5616 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5619 synqf = filter_info->syn_info;
5621 if (synqf & E1000_SYN_FILTER_ENABLE) {
5622 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5623 E1000_WRITE_FLUSH(hw);
5627 /* restore ethernet type filter */
5629 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5631 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5632 struct e1000_filter_info *filter_info =
5633 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5636 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5637 if (filter_info->ethertype_mask & (1 << i)) {
5638 E1000_WRITE_REG(hw, E1000_ETQF(i),
5639 filter_info->ethertype_filters[i].etqf);
5640 E1000_WRITE_FLUSH(hw);
5645 /* restore flex byte filter */
5647 igb_flex_filter_restore(struct rte_eth_dev *dev)
5649 struct e1000_filter_info *filter_info =
5650 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5651 struct e1000_flex_filter *flex_filter;
5653 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5654 igb_inject_flex_filter(dev, flex_filter);
5658 /* restore rss filter */
5660 igb_rss_filter_restore(struct rte_eth_dev *dev)
5662 struct e1000_filter_info *filter_info =
5663 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5665 if (filter_info->rss_info.num)
5666 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5669 /* restore all types filter */
5671 igb_filter_restore(struct rte_eth_dev *dev)
5673 igb_ntuple_filter_restore(dev);
5674 igb_ethertype_filter_restore(dev);
5675 igb_syn_filter_restore(dev);
5676 igb_flex_filter_restore(dev);
5677 igb_rss_filter_restore(dev);
5682 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5683 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5684 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5685 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5686 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5687 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");