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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
64 #define IGB_DEFAULT_RX_PTHRESH 8
65 #define IGB_DEFAULT_RX_HTHRESH 8
66 #define IGB_DEFAULT_RX_WTHRESH 0
68 #define IGB_DEFAULT_TX_PTHRESH 32
69 #define IGB_DEFAULT_TX_HTHRESH 0
70 #define IGB_DEFAULT_TX_WTHRESH 0
72 #define IGB_HKEY_MAX_INDEX 10
74 /* Bit shift and mask */
75 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
76 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
77 #define IGB_8_BIT_WIDTH CHAR_BIT
78 #define IGB_8_BIT_MASK UINT8_MAX
80 /* Additional timesync values. */
81 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
82 #define E1000_ETQF_FILTER_1588 3
83 #define IGB_82576_TSYNC_SHIFT 16
84 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
85 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
86 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
88 static int eth_igb_configure(struct rte_eth_dev *dev);
89 static int eth_igb_start(struct rte_eth_dev *dev);
90 static void eth_igb_stop(struct rte_eth_dev *dev);
91 static void eth_igb_close(struct rte_eth_dev *dev);
92 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
93 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
94 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
95 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
96 static int eth_igb_link_update(struct rte_eth_dev *dev,
97 int wait_to_complete);
98 static void eth_igb_stats_get(struct rte_eth_dev *dev,
99 struct rte_eth_stats *rte_stats);
100 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
101 struct rte_eth_xstats *xstats, unsigned n);
102 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
103 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
104 static void eth_igb_infos_get(struct rte_eth_dev *dev,
105 struct rte_eth_dev_info *dev_info);
106 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
107 struct rte_eth_dev_info *dev_info);
108 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
109 struct rte_eth_fc_conf *fc_conf);
110 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
113 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
114 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
115 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
116 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
118 static int igb_hardware_init(struct e1000_hw *hw);
119 static void igb_hw_control_acquire(struct e1000_hw *hw);
120 static void igb_hw_control_release(struct e1000_hw *hw);
121 static void igb_init_manageability(struct e1000_hw *hw);
122 static void igb_release_manageability(struct e1000_hw *hw);
124 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
126 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
127 uint16_t vlan_id, int on);
128 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
129 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
131 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
132 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
133 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
134 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
135 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
138 static int eth_igb_led_on(struct rte_eth_dev *dev);
139 static int eth_igb_led_off(struct rte_eth_dev *dev);
141 static void igb_intr_disable(struct e1000_hw *hw);
142 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
143 static void eth_igb_rar_set(struct rte_eth_dev *dev,
144 struct ether_addr *mac_addr,
145 uint32_t index, uint32_t pool);
146 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
147 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
148 struct ether_addr *addr);
150 static void igbvf_intr_disable(struct e1000_hw *hw);
151 static int igbvf_dev_configure(struct rte_eth_dev *dev);
152 static int igbvf_dev_start(struct rte_eth_dev *dev);
153 static void igbvf_dev_stop(struct rte_eth_dev *dev);
154 static void igbvf_dev_close(struct rte_eth_dev *dev);
155 static int eth_igbvf_link_update(struct e1000_hw *hw);
156 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
157 struct rte_eth_stats *rte_stats);
158 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
159 struct rte_eth_xstats *xstats, unsigned n);
160 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
161 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
162 uint16_t vlan_id, int on);
163 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
164 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
165 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
166 struct ether_addr *addr);
167 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
168 static int igbvf_get_regs(struct rte_eth_dev *dev,
169 struct rte_dev_reg_info *regs);
171 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
172 struct rte_eth_rss_reta_entry64 *reta_conf,
174 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
175 struct rte_eth_rss_reta_entry64 *reta_conf,
178 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
179 struct rte_eth_syn_filter *filter,
181 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
182 struct rte_eth_syn_filter *filter);
183 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
184 enum rte_filter_op filter_op,
186 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
187 struct rte_eth_ntuple_filter *ntuple_filter);
188 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
189 struct rte_eth_ntuple_filter *ntuple_filter);
190 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
191 struct rte_eth_flex_filter *filter,
193 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
194 struct rte_eth_flex_filter *filter);
195 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
196 enum rte_filter_op filter_op,
198 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
199 struct rte_eth_ntuple_filter *ntuple_filter);
200 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
201 struct rte_eth_ntuple_filter *ntuple_filter);
202 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
203 struct rte_eth_ntuple_filter *filter,
205 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
206 struct rte_eth_ntuple_filter *filter);
207 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
208 enum rte_filter_op filter_op,
210 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
211 struct rte_eth_ethertype_filter *filter,
213 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
214 enum rte_filter_op filter_op,
216 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
217 struct rte_eth_ethertype_filter *filter);
218 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
219 enum rte_filter_type filter_type,
220 enum rte_filter_op filter_op,
222 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
223 static int eth_igb_get_regs(struct rte_eth_dev *dev,
224 struct rte_dev_reg_info *regs);
225 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
226 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
227 struct rte_dev_eeprom_info *eeprom);
228 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
229 struct rte_dev_eeprom_info *eeprom);
230 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
231 struct ether_addr *mc_addr_set,
232 uint32_t nb_mc_addr);
233 static int igb_timesync_enable(struct rte_eth_dev *dev);
234 static int igb_timesync_disable(struct rte_eth_dev *dev);
235 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
236 struct timespec *timestamp,
238 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
239 struct timespec *timestamp);
240 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
241 static int igb_timesync_read_time(struct rte_eth_dev *dev,
242 struct timespec *timestamp);
243 static int igb_timesync_write_time(struct rte_eth_dev *dev,
244 const struct timespec *timestamp);
245 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
247 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
249 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
250 uint8_t queue, uint8_t msix_vector);
251 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
252 uint8_t index, uint8_t offset);
253 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
256 * Define VF Stats MACRO for Non "cleared on read" register
258 #define UPDATE_VF_STAT(reg, last, cur) \
260 u32 latest = E1000_READ_REG(hw, reg); \
261 cur += (latest - last) & UINT_MAX; \
265 #define IGB_FC_PAUSE_TIME 0x0680
266 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
267 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
269 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
271 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
274 * The set of PCI devices this driver supports
276 static const struct rte_pci_id pci_id_igb_map[] = {
278 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
279 #include "rte_pci_dev_ids.h"
285 * The set of PCI devices this driver supports (for 82576&I350 VF)
287 static const struct rte_pci_id pci_id_igbvf_map[] = {
289 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
290 #include "rte_pci_dev_ids.h"
295 static const struct rte_eth_desc_lim rx_desc_lim = {
296 .nb_max = E1000_MAX_RING_DESC,
297 .nb_min = E1000_MIN_RING_DESC,
298 .nb_align = IGB_RXD_ALIGN,
301 static const struct rte_eth_desc_lim tx_desc_lim = {
302 .nb_max = E1000_MAX_RING_DESC,
303 .nb_min = E1000_MIN_RING_DESC,
304 .nb_align = IGB_RXD_ALIGN,
307 static const struct eth_dev_ops eth_igb_ops = {
308 .dev_configure = eth_igb_configure,
309 .dev_start = eth_igb_start,
310 .dev_stop = eth_igb_stop,
311 .dev_close = eth_igb_close,
312 .promiscuous_enable = eth_igb_promiscuous_enable,
313 .promiscuous_disable = eth_igb_promiscuous_disable,
314 .allmulticast_enable = eth_igb_allmulticast_enable,
315 .allmulticast_disable = eth_igb_allmulticast_disable,
316 .link_update = eth_igb_link_update,
317 .stats_get = eth_igb_stats_get,
318 .xstats_get = eth_igb_xstats_get,
319 .stats_reset = eth_igb_stats_reset,
320 .xstats_reset = eth_igb_xstats_reset,
321 .dev_infos_get = eth_igb_infos_get,
322 .mtu_set = eth_igb_mtu_set,
323 .vlan_filter_set = eth_igb_vlan_filter_set,
324 .vlan_tpid_set = eth_igb_vlan_tpid_set,
325 .vlan_offload_set = eth_igb_vlan_offload_set,
326 .rx_queue_setup = eth_igb_rx_queue_setup,
327 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
328 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
329 .rx_queue_release = eth_igb_rx_queue_release,
330 .rx_queue_count = eth_igb_rx_queue_count,
331 .rx_descriptor_done = eth_igb_rx_descriptor_done,
332 .tx_queue_setup = eth_igb_tx_queue_setup,
333 .tx_queue_release = eth_igb_tx_queue_release,
334 .dev_led_on = eth_igb_led_on,
335 .dev_led_off = eth_igb_led_off,
336 .flow_ctrl_get = eth_igb_flow_ctrl_get,
337 .flow_ctrl_set = eth_igb_flow_ctrl_set,
338 .mac_addr_add = eth_igb_rar_set,
339 .mac_addr_remove = eth_igb_rar_clear,
340 .mac_addr_set = eth_igb_default_mac_addr_set,
341 .reta_update = eth_igb_rss_reta_update,
342 .reta_query = eth_igb_rss_reta_query,
343 .rss_hash_update = eth_igb_rss_hash_update,
344 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
345 .filter_ctrl = eth_igb_filter_ctrl,
346 .set_mc_addr_list = eth_igb_set_mc_addr_list,
347 .rxq_info_get = igb_rxq_info_get,
348 .txq_info_get = igb_txq_info_get,
349 .timesync_enable = igb_timesync_enable,
350 .timesync_disable = igb_timesync_disable,
351 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
352 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
353 .get_reg_length = eth_igb_get_reg_length,
354 .get_reg = eth_igb_get_regs,
355 .get_eeprom_length = eth_igb_get_eeprom_length,
356 .get_eeprom = eth_igb_get_eeprom,
357 .set_eeprom = eth_igb_set_eeprom,
358 .timesync_adjust_time = igb_timesync_adjust_time,
359 .timesync_read_time = igb_timesync_read_time,
360 .timesync_write_time = igb_timesync_write_time,
364 * dev_ops for virtual function, bare necessities for basic vf
365 * operation have been implemented
367 static const struct eth_dev_ops igbvf_eth_dev_ops = {
368 .dev_configure = igbvf_dev_configure,
369 .dev_start = igbvf_dev_start,
370 .dev_stop = igbvf_dev_stop,
371 .dev_close = igbvf_dev_close,
372 .link_update = eth_igb_link_update,
373 .stats_get = eth_igbvf_stats_get,
374 .xstats_get = eth_igbvf_xstats_get,
375 .stats_reset = eth_igbvf_stats_reset,
376 .xstats_reset = eth_igbvf_stats_reset,
377 .vlan_filter_set = igbvf_vlan_filter_set,
378 .dev_infos_get = eth_igbvf_infos_get,
379 .rx_queue_setup = eth_igb_rx_queue_setup,
380 .rx_queue_release = eth_igb_rx_queue_release,
381 .tx_queue_setup = eth_igb_tx_queue_setup,
382 .tx_queue_release = eth_igb_tx_queue_release,
383 .set_mc_addr_list = eth_igb_set_mc_addr_list,
384 .rxq_info_get = igb_rxq_info_get,
385 .txq_info_get = igb_txq_info_get,
386 .mac_addr_set = igbvf_default_mac_addr_set,
387 .get_reg_length = igbvf_get_reg_length,
388 .get_reg = igbvf_get_regs,
391 /* store statistics names and its offset in stats structure */
392 struct rte_igb_xstats_name_off {
393 char name[RTE_ETH_XSTATS_NAME_SIZE];
397 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
398 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
399 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
400 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
401 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
402 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
403 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
404 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
406 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
407 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
408 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
409 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
410 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
411 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
412 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
413 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
414 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
415 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
416 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
418 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
419 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
420 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
421 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
422 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
424 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
426 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
427 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
428 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
429 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
430 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
431 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
432 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
433 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
434 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
435 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
436 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
437 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
438 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
439 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
440 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
441 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
442 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
443 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
445 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
447 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
448 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
449 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
450 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
451 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
452 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
453 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
455 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
458 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
459 sizeof(rte_igb_stats_strings[0]))
461 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
462 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
463 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
464 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
465 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
466 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
469 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
470 sizeof(rte_igbvf_stats_strings[0]))
473 * Atomically reads the link status information from global
474 * structure rte_eth_dev.
477 * - Pointer to the structure rte_eth_dev to read from.
478 * - Pointer to the buffer to be saved with the link status.
481 * - On success, zero.
482 * - On failure, negative value.
485 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
486 struct rte_eth_link *link)
488 struct rte_eth_link *dst = link;
489 struct rte_eth_link *src = &(dev->data->dev_link);
491 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
492 *(uint64_t *)src) == 0)
499 * Atomically writes the link status information into global
500 * structure rte_eth_dev.
503 * - Pointer to the structure rte_eth_dev to read from.
504 * - Pointer to the buffer to be saved with the link status.
507 * - On success, zero.
508 * - On failure, negative value.
511 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
512 struct rte_eth_link *link)
514 struct rte_eth_link *dst = &(dev->data->dev_link);
515 struct rte_eth_link *src = link;
517 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
518 *(uint64_t *)src) == 0)
525 igb_intr_enable(struct rte_eth_dev *dev)
527 struct e1000_interrupt *intr =
528 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
529 struct e1000_hw *hw =
530 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
532 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
533 E1000_WRITE_FLUSH(hw);
537 igb_intr_disable(struct e1000_hw *hw)
539 E1000_WRITE_REG(hw, E1000_IMC, ~0);
540 E1000_WRITE_FLUSH(hw);
543 static inline int32_t
544 igb_pf_reset_hw(struct e1000_hw *hw)
549 status = e1000_reset_hw(hw);
551 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
552 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
553 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
554 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
555 E1000_WRITE_FLUSH(hw);
561 igb_identify_hardware(struct rte_eth_dev *dev)
563 struct e1000_hw *hw =
564 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
566 hw->vendor_id = dev->pci_dev->id.vendor_id;
567 hw->device_id = dev->pci_dev->id.device_id;
568 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
569 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
571 e1000_set_mac_type(hw);
573 /* need to check if it is a vf device below */
577 igb_reset_swfw_lock(struct e1000_hw *hw)
582 * Do mac ops initialization manually here, since we will need
583 * some function pointers set by this call.
585 ret_val = e1000_init_mac_params(hw);
590 * SMBI lock should not fail in this early stage. If this is the case,
591 * it is due to an improper exit of the application.
592 * So force the release of the faulty lock.
594 if (e1000_get_hw_semaphore_generic(hw) < 0) {
595 PMD_DRV_LOG(DEBUG, "SMBI lock released");
597 e1000_put_hw_semaphore_generic(hw);
599 if (hw->mac.ops.acquire_swfw_sync != NULL) {
603 * Phy lock should not fail in this early stage. If this is the case,
604 * it is due to an improper exit of the application.
605 * So force the release of the faulty lock.
607 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
608 if (hw->bus.func > E1000_FUNC_1)
610 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
611 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
614 hw->mac.ops.release_swfw_sync(hw, mask);
617 * This one is more tricky since it is common to all ports; but
618 * swfw_sync retries last long enough (1s) to be almost sure that if
619 * lock can not be taken it is due to an improper lock of the
622 mask = E1000_SWFW_EEP_SM;
623 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
624 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
626 hw->mac.ops.release_swfw_sync(hw, mask);
629 return E1000_SUCCESS;
633 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
636 struct rte_pci_device *pci_dev;
637 struct e1000_hw *hw =
638 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
639 struct e1000_vfta * shadow_vfta =
640 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
641 struct e1000_filter_info *filter_info =
642 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
643 struct e1000_adapter *adapter =
644 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
648 pci_dev = eth_dev->pci_dev;
650 eth_dev->dev_ops = ð_igb_ops;
651 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
652 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
654 /* for secondary processes, we don't initialise any further as primary
655 * has already done this work. Only check we don't need a different
657 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
658 if (eth_dev->data->scattered_rx)
659 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
663 rte_eth_copy_pci_info(eth_dev, pci_dev);
665 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
667 igb_identify_hardware(eth_dev);
668 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
673 e1000_get_bus_info(hw);
675 /* Reset any pending lock */
676 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
681 /* Finish initialization */
682 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
688 hw->phy.autoneg_wait_to_complete = 0;
689 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
692 if (hw->phy.media_type == e1000_media_type_copper) {
693 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
694 hw->phy.disable_polarity_correction = 0;
695 hw->phy.ms_type = e1000_ms_hw_default;
699 * Start from a known state, this is important in reading the nvm
704 /* Make sure we have a good EEPROM before we read from it */
705 if (e1000_validate_nvm_checksum(hw) < 0) {
707 * Some PCI-E parts fail the first check due to
708 * the link being in sleep state, call it again,
709 * if it fails a second time its a real issue.
711 if (e1000_validate_nvm_checksum(hw) < 0) {
712 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
718 /* Read the permanent MAC address out of the EEPROM */
719 if (e1000_read_mac_addr(hw) != 0) {
720 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
725 /* Allocate memory for storing MAC addresses */
726 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
727 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
728 if (eth_dev->data->mac_addrs == NULL) {
729 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
730 "store MAC addresses",
731 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
736 /* Copy the permanent MAC address */
737 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
739 /* initialize the vfta */
740 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
742 /* Now initialize the hardware */
743 if (igb_hardware_init(hw) != 0) {
744 PMD_INIT_LOG(ERR, "Hardware initialization failed");
745 rte_free(eth_dev->data->mac_addrs);
746 eth_dev->data->mac_addrs = NULL;
750 hw->mac.get_link_status = 1;
751 adapter->stopped = 0;
753 /* Indicate SOL/IDER usage */
754 if (e1000_check_reset_block(hw) < 0) {
755 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
759 /* initialize PF if max_vfs not zero */
760 igb_pf_host_init(eth_dev);
762 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
763 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
764 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
765 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
766 E1000_WRITE_FLUSH(hw);
768 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
769 eth_dev->data->port_id, pci_dev->id.vendor_id,
770 pci_dev->id.device_id);
772 rte_intr_callback_register(&pci_dev->intr_handle,
773 eth_igb_interrupt_handler,
776 /* enable uio/vfio intr/eventfd mapping */
777 rte_intr_enable(&pci_dev->intr_handle);
779 /* enable support intr */
780 igb_intr_enable(eth_dev);
782 TAILQ_INIT(&filter_info->flex_list);
783 filter_info->flex_mask = 0;
784 TAILQ_INIT(&filter_info->twotuple_list);
785 filter_info->twotuple_mask = 0;
786 TAILQ_INIT(&filter_info->fivetuple_list);
787 filter_info->fivetuple_mask = 0;
792 igb_hw_control_release(hw);
798 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
800 struct rte_pci_device *pci_dev;
802 struct e1000_adapter *adapter =
803 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
805 PMD_INIT_FUNC_TRACE();
807 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
810 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
811 pci_dev = eth_dev->pci_dev;
813 if (adapter->stopped == 0)
814 eth_igb_close(eth_dev);
816 eth_dev->dev_ops = NULL;
817 eth_dev->rx_pkt_burst = NULL;
818 eth_dev->tx_pkt_burst = NULL;
820 /* Reset any pending lock */
821 igb_reset_swfw_lock(hw);
823 rte_free(eth_dev->data->mac_addrs);
824 eth_dev->data->mac_addrs = NULL;
826 /* uninitialize PF if max_vfs not zero */
827 igb_pf_host_uninit(eth_dev);
829 /* disable uio intr before callback unregister */
830 rte_intr_disable(&(pci_dev->intr_handle));
831 rte_intr_callback_unregister(&(pci_dev->intr_handle),
832 eth_igb_interrupt_handler, (void *)eth_dev);
838 * Virtual Function device init
841 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
843 struct rte_pci_device *pci_dev;
844 struct e1000_adapter *adapter =
845 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
846 struct e1000_hw *hw =
847 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
849 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
851 PMD_INIT_FUNC_TRACE();
853 eth_dev->dev_ops = &igbvf_eth_dev_ops;
854 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
855 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
857 /* for secondary processes, we don't initialise any further as primary
858 * has already done this work. Only check we don't need a different
860 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
861 if (eth_dev->data->scattered_rx)
862 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
866 pci_dev = eth_dev->pci_dev;
868 rte_eth_copy_pci_info(eth_dev, pci_dev);
870 hw->device_id = pci_dev->id.device_id;
871 hw->vendor_id = pci_dev->id.vendor_id;
872 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
873 adapter->stopped = 0;
875 /* Initialize the shared code (base driver) */
876 diag = e1000_setup_init_funcs(hw, TRUE);
878 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
883 /* init_mailbox_params */
884 hw->mbx.ops.init_params(hw);
886 /* Disable the interrupts for VF */
887 igbvf_intr_disable(hw);
889 diag = hw->mac.ops.reset_hw(hw);
891 /* Allocate memory for storing MAC addresses */
892 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
893 hw->mac.rar_entry_count, 0);
894 if (eth_dev->data->mac_addrs == NULL) {
896 "Failed to allocate %d bytes needed to store MAC "
898 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
902 /* Generate a random MAC address, if none was assigned by PF. */
903 if (is_zero_ether_addr(perm_addr)) {
904 eth_random_addr(perm_addr->addr_bytes);
905 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
907 rte_free(eth_dev->data->mac_addrs);
908 eth_dev->data->mac_addrs = NULL;
911 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
912 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
913 "%02x:%02x:%02x:%02x:%02x:%02x",
914 perm_addr->addr_bytes[0],
915 perm_addr->addr_bytes[1],
916 perm_addr->addr_bytes[2],
917 perm_addr->addr_bytes[3],
918 perm_addr->addr_bytes[4],
919 perm_addr->addr_bytes[5]);
922 /* Copy the permanent MAC address */
923 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
924 ð_dev->data->mac_addrs[0]);
926 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
928 eth_dev->data->port_id, pci_dev->id.vendor_id,
929 pci_dev->id.device_id, "igb_mac_82576_vf");
935 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
937 struct e1000_adapter *adapter =
938 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
940 PMD_INIT_FUNC_TRACE();
942 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
945 if (adapter->stopped == 0)
946 igbvf_dev_close(eth_dev);
948 eth_dev->dev_ops = NULL;
949 eth_dev->rx_pkt_burst = NULL;
950 eth_dev->tx_pkt_burst = NULL;
952 rte_free(eth_dev->data->mac_addrs);
953 eth_dev->data->mac_addrs = NULL;
958 static struct eth_driver rte_igb_pmd = {
960 .name = "rte_igb_pmd",
961 .id_table = pci_id_igb_map,
962 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
963 RTE_PCI_DRV_DETACHABLE,
965 .eth_dev_init = eth_igb_dev_init,
966 .eth_dev_uninit = eth_igb_dev_uninit,
967 .dev_private_size = sizeof(struct e1000_adapter),
971 * virtual function driver struct
973 static struct eth_driver rte_igbvf_pmd = {
975 .name = "rte_igbvf_pmd",
976 .id_table = pci_id_igbvf_map,
977 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
979 .eth_dev_init = eth_igbvf_dev_init,
980 .eth_dev_uninit = eth_igbvf_dev_uninit,
981 .dev_private_size = sizeof(struct e1000_adapter),
985 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
987 rte_eth_driver_register(&rte_igb_pmd);
992 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
994 struct e1000_hw *hw =
995 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
996 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
997 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
998 rctl |= E1000_RCTL_VFE;
999 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1003 * VF Driver initialization routine.
1004 * Invoked one at EAL init time.
1005 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1008 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1010 PMD_INIT_FUNC_TRACE();
1012 rte_eth_driver_register(&rte_igbvf_pmd);
1017 igb_check_mq_mode(struct rte_eth_dev *dev)
1019 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1020 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1021 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1022 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1024 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1025 tx_mq_mode == ETH_MQ_TX_DCB ||
1026 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1027 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1030 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1031 /* Check multi-queue mode.
1032 * To no break software we accept ETH_MQ_RX_NONE as this might
1033 * be used to turn off VLAN filter.
1036 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1037 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1038 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1039 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1041 /* Only support one queue on VFs.
1042 * RSS together with SRIOV is not supported.
1044 PMD_INIT_LOG(ERR, "SRIOV is active,"
1045 " wrong mq_mode rx %d.",
1049 /* TX mode is not used here, so mode might be ignored.*/
1050 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1051 /* SRIOV only works in VMDq enable mode */
1052 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1053 " TX mode %d is not supported. "
1054 " Driver will behave as %d mode.",
1055 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1058 /* check valid queue number */
1059 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1060 PMD_INIT_LOG(ERR, "SRIOV is active,"
1061 " only support one queue on VFs.");
1065 /* To no break software that set invalid mode, only display
1066 * warning if invalid mode is used.
1068 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1069 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1070 rx_mq_mode != ETH_MQ_RX_RSS) {
1071 /* RSS together with VMDq not supported*/
1072 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1077 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1078 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1079 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1080 " Due to txmode is meaningless in this"
1081 " driver, just ignore.",
1089 eth_igb_configure(struct rte_eth_dev *dev)
1091 struct e1000_interrupt *intr =
1092 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1095 PMD_INIT_FUNC_TRACE();
1097 /* multipe queue mode checking */
1098 ret = igb_check_mq_mode(dev);
1100 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1105 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1106 PMD_INIT_FUNC_TRACE();
1112 eth_igb_start(struct rte_eth_dev *dev)
1114 struct e1000_hw *hw =
1115 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1116 struct e1000_adapter *adapter =
1117 E1000_DEV_PRIVATE(dev->data->dev_private);
1118 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1120 uint32_t intr_vector = 0;
1123 PMD_INIT_FUNC_TRACE();
1125 /* disable uio/vfio intr/eventfd mapping */
1126 rte_intr_disable(intr_handle);
1128 /* Power up the phy. Needed to make the link go Up */
1129 e1000_power_up_phy(hw);
1132 * Packet Buffer Allocation (PBA)
1133 * Writing PBA sets the receive portion of the buffer
1134 * the remainder is used for the transmit buffer.
1136 if (hw->mac.type == e1000_82575) {
1139 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1140 E1000_WRITE_REG(hw, E1000_PBA, pba);
1143 /* Put the address into the Receive Address Array */
1144 e1000_rar_set(hw, hw->mac.addr, 0);
1146 /* Initialize the hardware */
1147 if (igb_hardware_init(hw)) {
1148 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1151 adapter->stopped = 0;
1153 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1155 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1156 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1157 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1158 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1159 E1000_WRITE_FLUSH(hw);
1161 /* configure PF module if SRIOV enabled */
1162 igb_pf_host_configure(dev);
1164 /* check and configure queue intr-vector mapping */
1165 if ((rte_intr_cap_multiple(intr_handle) ||
1166 !RTE_ETH_DEV_SRIOV(dev).active) &&
1167 dev->data->dev_conf.intr_conf.rxq != 0) {
1168 intr_vector = dev->data->nb_rx_queues;
1169 if (rte_intr_efd_enable(intr_handle, intr_vector))
1173 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1174 intr_handle->intr_vec =
1175 rte_zmalloc("intr_vec",
1176 dev->data->nb_rx_queues * sizeof(int), 0);
1177 if (intr_handle->intr_vec == NULL) {
1178 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1179 " intr_vec\n", dev->data->nb_rx_queues);
1184 /* confiugre msix for rx interrupt */
1185 eth_igb_configure_msix_intr(dev);
1187 /* Configure for OS presence */
1188 igb_init_manageability(hw);
1190 eth_igb_tx_init(dev);
1192 /* This can fail when allocating mbufs for descriptor rings */
1193 ret = eth_igb_rx_init(dev);
1195 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1196 igb_dev_clear_queues(dev);
1200 e1000_clear_hw_cntrs_base_generic(hw);
1203 * VLAN Offload Settings
1205 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1206 ETH_VLAN_EXTEND_MASK;
1207 eth_igb_vlan_offload_set(dev, mask);
1209 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1210 /* Enable VLAN filter since VMDq always use VLAN filter */
1211 igb_vmdq_vlan_hw_filter_enable(dev);
1214 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1215 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1216 (hw->mac.type == e1000_i211)) {
1217 /* Configure EITR with the maximum possible value (0xFFFF) */
1218 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1221 /* Setup link speed and duplex */
1222 switch (dev->data->dev_conf.link_speed) {
1223 case ETH_LINK_SPEED_AUTONEG:
1224 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1225 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1226 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1227 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1228 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1229 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1231 goto error_invalid_config;
1233 case ETH_LINK_SPEED_10:
1234 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1235 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1236 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1237 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1238 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1239 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1241 goto error_invalid_config;
1243 case ETH_LINK_SPEED_100:
1244 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1245 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1246 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1247 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1248 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1249 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1251 goto error_invalid_config;
1253 case ETH_LINK_SPEED_1000:
1254 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1255 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1256 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1258 goto error_invalid_config;
1260 case ETH_LINK_SPEED_10000:
1262 goto error_invalid_config;
1264 e1000_setup_link(hw);
1266 if (rte_intr_allow_others(intr_handle)) {
1267 /* check if lsc interrupt is enabled */
1268 if (dev->data->dev_conf.intr_conf.lsc != 0)
1269 eth_igb_lsc_interrupt_setup(dev);
1271 rte_intr_callback_unregister(intr_handle,
1272 eth_igb_interrupt_handler,
1274 if (dev->data->dev_conf.intr_conf.lsc != 0)
1275 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1276 " no intr multiplex\n");
1279 /* check if rxq interrupt is enabled */
1280 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1281 rte_intr_dp_is_en(intr_handle))
1282 eth_igb_rxq_interrupt_setup(dev);
1284 /* enable uio/vfio intr/eventfd mapping */
1285 rte_intr_enable(intr_handle);
1287 /* resume enabled intr since hw reset */
1288 igb_intr_enable(dev);
1290 PMD_INIT_LOG(DEBUG, "<<");
1294 error_invalid_config:
1295 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1296 dev->data->dev_conf.link_speed,
1297 dev->data->dev_conf.link_duplex, dev->data->port_id);
1298 igb_dev_clear_queues(dev);
1302 /*********************************************************************
1304 * This routine disables all traffic on the adapter by issuing a
1305 * global reset on the MAC.
1307 **********************************************************************/
1309 eth_igb_stop(struct rte_eth_dev *dev)
1311 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1312 struct e1000_filter_info *filter_info =
1313 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1314 struct rte_eth_link link;
1315 struct e1000_flex_filter *p_flex;
1316 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1317 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1318 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1320 igb_intr_disable(hw);
1322 /* disable intr eventfd mapping */
1323 rte_intr_disable(intr_handle);
1325 igb_pf_reset_hw(hw);
1326 E1000_WRITE_REG(hw, E1000_WUC, 0);
1328 /* Set bit for Go Link disconnect */
1329 if (hw->mac.type >= e1000_82580) {
1332 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1333 phpm_reg |= E1000_82580_PM_GO_LINKD;
1334 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1337 /* Power down the phy. Needed to make the link go Down */
1338 if (hw->phy.media_type == e1000_media_type_copper)
1339 e1000_power_down_phy(hw);
1341 e1000_shutdown_fiber_serdes_link(hw);
1343 igb_dev_clear_queues(dev);
1345 /* clear the recorded link status */
1346 memset(&link, 0, sizeof(link));
1347 rte_igb_dev_atomic_write_link_status(dev, &link);
1349 /* Remove all flex filters of the device */
1350 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1351 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1354 filter_info->flex_mask = 0;
1356 /* Remove all ntuple filters of the device */
1357 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1358 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1359 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1360 TAILQ_REMOVE(&filter_info->fivetuple_list,
1364 filter_info->fivetuple_mask = 0;
1365 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1366 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1367 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1368 TAILQ_REMOVE(&filter_info->twotuple_list,
1372 filter_info->twotuple_mask = 0;
1374 if (!rte_intr_allow_others(intr_handle))
1375 /* resume to the default handler */
1376 rte_intr_callback_register(intr_handle,
1377 eth_igb_interrupt_handler,
1380 /* Clean datapath event and queue/vec mapping */
1381 rte_intr_efd_disable(intr_handle);
1382 if (intr_handle->intr_vec != NULL) {
1383 rte_free(intr_handle->intr_vec);
1384 intr_handle->intr_vec = NULL;
1389 eth_igb_close(struct rte_eth_dev *dev)
1391 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1392 struct e1000_adapter *adapter =
1393 E1000_DEV_PRIVATE(dev->data->dev_private);
1394 struct rte_eth_link link;
1395 struct rte_pci_device *pci_dev;
1398 adapter->stopped = 1;
1400 e1000_phy_hw_reset(hw);
1401 igb_release_manageability(hw);
1402 igb_hw_control_release(hw);
1404 /* Clear bit for Go Link disconnect */
1405 if (hw->mac.type >= e1000_82580) {
1408 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1409 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1410 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1413 igb_dev_free_queues(dev);
1415 pci_dev = dev->pci_dev;
1416 if (pci_dev->intr_handle.intr_vec) {
1417 rte_free(pci_dev->intr_handle.intr_vec);
1418 pci_dev->intr_handle.intr_vec = NULL;
1421 memset(&link, 0, sizeof(link));
1422 rte_igb_dev_atomic_write_link_status(dev, &link);
1426 igb_get_rx_buffer_size(struct e1000_hw *hw)
1428 uint32_t rx_buf_size;
1429 if (hw->mac.type == e1000_82576) {
1430 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1431 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1432 /* PBS needs to be translated according to a lookup table */
1433 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1434 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1435 rx_buf_size = (rx_buf_size << 10);
1436 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1437 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1439 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1445 /*********************************************************************
1447 * Initialize the hardware
1449 **********************************************************************/
1451 igb_hardware_init(struct e1000_hw *hw)
1453 uint32_t rx_buf_size;
1456 /* Let the firmware know the OS is in control */
1457 igb_hw_control_acquire(hw);
1460 * These parameters control the automatic generation (Tx) and
1461 * response (Rx) to Ethernet PAUSE frames.
1462 * - High water mark should allow for at least two standard size (1518)
1463 * frames to be received after sending an XOFF.
1464 * - Low water mark works best when it is very near the high water mark.
1465 * This allows the receiver to restart by sending XON when it has
1466 * drained a bit. Here we use an arbitrary value of 1500 which will
1467 * restart after one full frame is pulled from the buffer. There
1468 * could be several smaller frames in the buffer and if so they will
1469 * not trigger the XON until their total number reduces the buffer
1471 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1473 rx_buf_size = igb_get_rx_buffer_size(hw);
1475 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1476 hw->fc.low_water = hw->fc.high_water - 1500;
1477 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1478 hw->fc.send_xon = 1;
1480 /* Set Flow control, use the tunable location if sane */
1481 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1482 hw->fc.requested_mode = igb_fc_setting;
1484 hw->fc.requested_mode = e1000_fc_none;
1486 /* Issue a global reset */
1487 igb_pf_reset_hw(hw);
1488 E1000_WRITE_REG(hw, E1000_WUC, 0);
1490 diag = e1000_init_hw(hw);
1494 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1495 e1000_get_phy_info(hw);
1496 e1000_check_for_link(hw);
1501 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1503 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1507 uint64_t old_gprc = stats->gprc;
1508 uint64_t old_gptc = stats->gptc;
1509 uint64_t old_tpr = stats->tpr;
1510 uint64_t old_tpt = stats->tpt;
1511 uint64_t old_rpthc = stats->rpthc;
1512 uint64_t old_hgptc = stats->hgptc;
1514 if(hw->phy.media_type == e1000_media_type_copper ||
1515 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1517 E1000_READ_REG(hw,E1000_SYMERRS);
1518 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1521 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1522 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1523 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1524 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1526 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1527 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1528 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1529 stats->dc += E1000_READ_REG(hw, E1000_DC);
1530 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1531 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1532 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1534 ** For watchdog management we need to know if we have been
1535 ** paused during the last interval, so capture that here.
1537 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1538 stats->xoffrxc += pause_frames;
1539 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1540 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1541 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1542 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1543 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1544 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1545 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1546 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1547 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1548 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1549 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1550 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1552 /* For the 64-bit byte counters the low dword must be read first. */
1553 /* Both registers clear on the read of the high dword */
1555 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1556 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1557 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1558 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1559 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1560 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1561 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1563 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1564 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1565 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1566 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1567 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1569 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1570 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1572 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1573 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1574 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1575 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1576 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1577 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1579 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1580 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1581 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1582 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1583 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1584 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1585 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1586 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1588 /* Interrupt Counts */
1590 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1591 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1592 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1593 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1594 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1595 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1596 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1597 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1598 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1600 /* Host to Card Statistics */
1602 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1603 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1604 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1605 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1606 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1607 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1608 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1609 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1610 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1611 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1612 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1613 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1614 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1615 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1616 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1617 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1619 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1620 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1621 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1622 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1623 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1624 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1628 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1630 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631 struct e1000_hw_stats *stats =
1632 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1634 igb_read_stats_registers(hw, stats);
1636 if (rte_stats == NULL)
1640 rte_stats->imissed = stats->mpc;
1641 rte_stats->ierrors = stats->crcerrs +
1642 stats->rlec + stats->ruc + stats->roc +
1643 rte_stats->imissed +
1644 stats->rxerrc + stats->algnerrc + stats->cexterr;
1647 rte_stats->oerrors = stats->ecol + stats->latecol;
1649 rte_stats->ipackets = stats->gprc;
1650 rte_stats->opackets = stats->gptc;
1651 rte_stats->ibytes = stats->gorc;
1652 rte_stats->obytes = stats->gotc;
1656 eth_igb_stats_reset(struct rte_eth_dev *dev)
1658 struct e1000_hw_stats *hw_stats =
1659 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1661 /* HW registers are cleared on read */
1662 eth_igb_stats_get(dev, NULL);
1664 /* Reset software totals */
1665 memset(hw_stats, 0, sizeof(*hw_stats));
1669 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1671 struct e1000_hw_stats *stats =
1672 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1674 /* HW registers are cleared on read */
1675 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1677 /* Reset software totals */
1678 memset(stats, 0, sizeof(*stats));
1682 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1685 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686 struct e1000_hw_stats *hw_stats =
1687 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1690 if (n < IGB_NB_XSTATS)
1691 return IGB_NB_XSTATS;
1693 igb_read_stats_registers(hw, hw_stats);
1695 /* If this is a reset xstats is NULL, and we have cleared the
1696 * registers by reading them.
1701 /* Extended stats */
1702 for (i = 0; i < IGB_NB_XSTATS; i++) {
1703 snprintf(xstats[i].name, sizeof(xstats[i].name),
1704 "%s", rte_igb_stats_strings[i].name);
1705 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1706 rte_igb_stats_strings[i].offset);
1709 return IGB_NB_XSTATS;
1713 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1715 /* Good Rx packets, include VF loopback */
1716 UPDATE_VF_STAT(E1000_VFGPRC,
1717 hw_stats->last_gprc, hw_stats->gprc);
1719 /* Good Rx octets, include VF loopback */
1720 UPDATE_VF_STAT(E1000_VFGORC,
1721 hw_stats->last_gorc, hw_stats->gorc);
1723 /* Good Tx packets, include VF loopback */
1724 UPDATE_VF_STAT(E1000_VFGPTC,
1725 hw_stats->last_gptc, hw_stats->gptc);
1727 /* Good Tx octets, include VF loopback */
1728 UPDATE_VF_STAT(E1000_VFGOTC,
1729 hw_stats->last_gotc, hw_stats->gotc);
1731 /* Rx Multicst packets */
1732 UPDATE_VF_STAT(E1000_VFMPRC,
1733 hw_stats->last_mprc, hw_stats->mprc);
1735 /* Good Rx loopback packets */
1736 UPDATE_VF_STAT(E1000_VFGPRLBC,
1737 hw_stats->last_gprlbc, hw_stats->gprlbc);
1739 /* Good Rx loopback octets */
1740 UPDATE_VF_STAT(E1000_VFGORLBC,
1741 hw_stats->last_gorlbc, hw_stats->gorlbc);
1743 /* Good Tx loopback packets */
1744 UPDATE_VF_STAT(E1000_VFGPTLBC,
1745 hw_stats->last_gptlbc, hw_stats->gptlbc);
1747 /* Good Tx loopback octets */
1748 UPDATE_VF_STAT(E1000_VFGOTLBC,
1749 hw_stats->last_gotlbc, hw_stats->gotlbc);
1753 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1756 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1758 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1761 if (n < IGBVF_NB_XSTATS)
1762 return IGBVF_NB_XSTATS;
1764 igbvf_read_stats_registers(hw, hw_stats);
1769 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1770 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1771 rte_igbvf_stats_strings[i].name);
1772 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1773 rte_igbvf_stats_strings[i].offset);
1776 return IGBVF_NB_XSTATS;
1780 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1782 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1784 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1786 igbvf_read_stats_registers(hw, hw_stats);
1788 if (rte_stats == NULL)
1791 rte_stats->ipackets = hw_stats->gprc;
1792 rte_stats->ibytes = hw_stats->gorc;
1793 rte_stats->opackets = hw_stats->gptc;
1794 rte_stats->obytes = hw_stats->gotc;
1795 rte_stats->imcasts = hw_stats->mprc;
1796 rte_stats->ilbpackets = hw_stats->gprlbc;
1797 rte_stats->ilbbytes = hw_stats->gorlbc;
1798 rte_stats->olbpackets = hw_stats->gptlbc;
1799 rte_stats->olbbytes = hw_stats->gotlbc;
1803 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1805 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1806 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1808 /* Sync HW register to the last stats */
1809 eth_igbvf_stats_get(dev, NULL);
1811 /* reset HW current stats*/
1812 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1813 offsetof(struct e1000_vf_stats, gprc));
1817 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1819 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1822 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1823 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1824 dev_info->rx_offload_capa =
1825 DEV_RX_OFFLOAD_VLAN_STRIP |
1826 DEV_RX_OFFLOAD_IPV4_CKSUM |
1827 DEV_RX_OFFLOAD_UDP_CKSUM |
1828 DEV_RX_OFFLOAD_TCP_CKSUM;
1829 dev_info->tx_offload_capa =
1830 DEV_TX_OFFLOAD_VLAN_INSERT |
1831 DEV_TX_OFFLOAD_IPV4_CKSUM |
1832 DEV_TX_OFFLOAD_UDP_CKSUM |
1833 DEV_TX_OFFLOAD_TCP_CKSUM |
1834 DEV_TX_OFFLOAD_SCTP_CKSUM |
1835 DEV_TX_OFFLOAD_TCP_TSO;
1837 switch (hw->mac.type) {
1839 dev_info->max_rx_queues = 4;
1840 dev_info->max_tx_queues = 4;
1841 dev_info->max_vmdq_pools = 0;
1845 dev_info->max_rx_queues = 16;
1846 dev_info->max_tx_queues = 16;
1847 dev_info->max_vmdq_pools = ETH_8_POOLS;
1848 dev_info->vmdq_queue_num = 16;
1852 dev_info->max_rx_queues = 8;
1853 dev_info->max_tx_queues = 8;
1854 dev_info->max_vmdq_pools = ETH_8_POOLS;
1855 dev_info->vmdq_queue_num = 8;
1859 dev_info->max_rx_queues = 8;
1860 dev_info->max_tx_queues = 8;
1861 dev_info->max_vmdq_pools = ETH_8_POOLS;
1862 dev_info->vmdq_queue_num = 8;
1866 dev_info->max_rx_queues = 8;
1867 dev_info->max_tx_queues = 8;
1871 dev_info->max_rx_queues = 4;
1872 dev_info->max_tx_queues = 4;
1873 dev_info->max_vmdq_pools = 0;
1877 dev_info->max_rx_queues = 2;
1878 dev_info->max_tx_queues = 2;
1879 dev_info->max_vmdq_pools = 0;
1883 /* Should not happen */
1886 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1887 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1888 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1890 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1892 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1893 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1894 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1896 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1900 dev_info->default_txconf = (struct rte_eth_txconf) {
1902 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1903 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1904 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1909 dev_info->rx_desc_lim = rx_desc_lim;
1910 dev_info->tx_desc_lim = tx_desc_lim;
1914 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1916 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1918 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1919 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1920 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1921 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1922 DEV_RX_OFFLOAD_IPV4_CKSUM |
1923 DEV_RX_OFFLOAD_UDP_CKSUM |
1924 DEV_RX_OFFLOAD_TCP_CKSUM;
1925 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1926 DEV_TX_OFFLOAD_IPV4_CKSUM |
1927 DEV_TX_OFFLOAD_UDP_CKSUM |
1928 DEV_TX_OFFLOAD_TCP_CKSUM |
1929 DEV_TX_OFFLOAD_SCTP_CKSUM |
1930 DEV_TX_OFFLOAD_TCP_TSO;
1931 switch (hw->mac.type) {
1933 dev_info->max_rx_queues = 2;
1934 dev_info->max_tx_queues = 2;
1936 case e1000_vfadapt_i350:
1937 dev_info->max_rx_queues = 1;
1938 dev_info->max_tx_queues = 1;
1941 /* Should not happen */
1945 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1947 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1948 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1949 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1951 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1955 dev_info->default_txconf = (struct rte_eth_txconf) {
1957 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1958 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1959 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1964 dev_info->rx_desc_lim = rx_desc_lim;
1965 dev_info->tx_desc_lim = tx_desc_lim;
1968 /* return 0 means link status changed, -1 means not changed */
1970 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1972 struct e1000_hw *hw =
1973 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974 struct rte_eth_link link, old;
1975 int link_check, count;
1978 hw->mac.get_link_status = 1;
1980 /* possible wait-to-complete in up to 9 seconds */
1981 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1982 /* Read the real link status */
1983 switch (hw->phy.media_type) {
1984 case e1000_media_type_copper:
1985 /* Do the work to read phy */
1986 e1000_check_for_link(hw);
1987 link_check = !hw->mac.get_link_status;
1990 case e1000_media_type_fiber:
1991 e1000_check_for_link(hw);
1992 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1996 case e1000_media_type_internal_serdes:
1997 e1000_check_for_link(hw);
1998 link_check = hw->mac.serdes_has_link;
2001 /* VF device is type_unknown */
2002 case e1000_media_type_unknown:
2003 eth_igbvf_link_update(hw);
2004 link_check = !hw->mac.get_link_status;
2010 if (link_check || wait_to_complete == 0)
2012 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2014 memset(&link, 0, sizeof(link));
2015 rte_igb_dev_atomic_read_link_status(dev, &link);
2018 /* Now we check if a transition has happened */
2020 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
2022 link.link_status = 1;
2023 } else if (!link_check) {
2024 link.link_speed = 0;
2025 link.link_duplex = 0;
2026 link.link_status = 0;
2028 rte_igb_dev_atomic_write_link_status(dev, &link);
2031 if (old.link_status == link.link_status)
2039 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2040 * For ASF and Pass Through versions of f/w this means
2041 * that the driver is loaded.
2044 igb_hw_control_acquire(struct e1000_hw *hw)
2048 /* Let firmware know the driver has taken over */
2049 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2050 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2054 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2055 * For ASF and Pass Through versions of f/w this means that the
2056 * driver is no longer loaded.
2059 igb_hw_control_release(struct e1000_hw *hw)
2063 /* Let firmware taken over control of h/w */
2064 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2065 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2066 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2070 * Bit of a misnomer, what this really means is
2071 * to enable OS management of the system... aka
2072 * to disable special hardware management features.
2075 igb_init_manageability(struct e1000_hw *hw)
2077 if (e1000_enable_mng_pass_thru(hw)) {
2078 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2079 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2081 /* disable hardware interception of ARP */
2082 manc &= ~(E1000_MANC_ARP_EN);
2084 /* enable receiving management packets to the host */
2085 manc |= E1000_MANC_EN_MNG2HOST;
2086 manc2h |= 1 << 5; /* Mng Port 623 */
2087 manc2h |= 1 << 6; /* Mng Port 664 */
2088 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2089 E1000_WRITE_REG(hw, E1000_MANC, manc);
2094 igb_release_manageability(struct e1000_hw *hw)
2096 if (e1000_enable_mng_pass_thru(hw)) {
2097 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2099 manc |= E1000_MANC_ARP_EN;
2100 manc &= ~E1000_MANC_EN_MNG2HOST;
2102 E1000_WRITE_REG(hw, E1000_MANC, manc);
2107 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2109 struct e1000_hw *hw =
2110 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113 rctl = E1000_READ_REG(hw, E1000_RCTL);
2114 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2115 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2119 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2121 struct e1000_hw *hw =
2122 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125 rctl = E1000_READ_REG(hw, E1000_RCTL);
2126 rctl &= (~E1000_RCTL_UPE);
2127 if (dev->data->all_multicast == 1)
2128 rctl |= E1000_RCTL_MPE;
2130 rctl &= (~E1000_RCTL_MPE);
2131 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2135 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2137 struct e1000_hw *hw =
2138 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141 rctl = E1000_READ_REG(hw, E1000_RCTL);
2142 rctl |= E1000_RCTL_MPE;
2143 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2147 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2149 struct e1000_hw *hw =
2150 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2153 if (dev->data->promiscuous == 1)
2154 return; /* must remain in all_multicast mode */
2155 rctl = E1000_READ_REG(hw, E1000_RCTL);
2156 rctl &= (~E1000_RCTL_MPE);
2157 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2161 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2163 struct e1000_hw *hw =
2164 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165 struct e1000_vfta * shadow_vfta =
2166 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2171 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2172 E1000_VFTA_ENTRY_MASK);
2173 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2174 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2179 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2181 /* update local VFTA copy */
2182 shadow_vfta->vfta[vid_idx] = vfta;
2188 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
2190 struct e1000_hw *hw =
2191 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192 uint32_t reg = ETHER_TYPE_VLAN ;
2194 reg |= (tpid << 16);
2195 E1000_WRITE_REG(hw, E1000_VET, reg);
2199 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2201 struct e1000_hw *hw =
2202 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2205 /* Filter Table Disable */
2206 reg = E1000_READ_REG(hw, E1000_RCTL);
2207 reg &= ~E1000_RCTL_CFIEN;
2208 reg &= ~E1000_RCTL_VFE;
2209 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2213 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2215 struct e1000_hw *hw =
2216 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217 struct e1000_vfta * shadow_vfta =
2218 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2222 /* Filter Table Enable, CFI not used for packet acceptance */
2223 reg = E1000_READ_REG(hw, E1000_RCTL);
2224 reg &= ~E1000_RCTL_CFIEN;
2225 reg |= E1000_RCTL_VFE;
2226 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2228 /* restore VFTA table */
2229 for (i = 0; i < IGB_VFTA_SIZE; i++)
2230 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2234 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2236 struct e1000_hw *hw =
2237 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240 /* VLAN Mode Disable */
2241 reg = E1000_READ_REG(hw, E1000_CTRL);
2242 reg &= ~E1000_CTRL_VME;
2243 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2247 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2249 struct e1000_hw *hw =
2250 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253 /* VLAN Mode Enable */
2254 reg = E1000_READ_REG(hw, E1000_CTRL);
2255 reg |= E1000_CTRL_VME;
2256 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2260 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2262 struct e1000_hw *hw =
2263 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2266 /* CTRL_EXT: Extended VLAN */
2267 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2268 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2269 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2271 /* Update maximum packet length */
2272 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2273 E1000_WRITE_REG(hw, E1000_RLPML,
2274 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2279 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2281 struct e1000_hw *hw =
2282 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2285 /* CTRL_EXT: Extended VLAN */
2286 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2287 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2288 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2290 /* Update maximum packet length */
2291 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2292 E1000_WRITE_REG(hw, E1000_RLPML,
2293 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2298 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2300 if(mask & ETH_VLAN_STRIP_MASK){
2301 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2302 igb_vlan_hw_strip_enable(dev);
2304 igb_vlan_hw_strip_disable(dev);
2307 if(mask & ETH_VLAN_FILTER_MASK){
2308 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2309 igb_vlan_hw_filter_enable(dev);
2311 igb_vlan_hw_filter_disable(dev);
2314 if(mask & ETH_VLAN_EXTEND_MASK){
2315 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2316 igb_vlan_hw_extend_enable(dev);
2318 igb_vlan_hw_extend_disable(dev);
2324 * It enables the interrupt mask and then enable the interrupt.
2327 * Pointer to struct rte_eth_dev.
2330 * - On success, zero.
2331 * - On failure, a negative value.
2334 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2336 struct e1000_interrupt *intr =
2337 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2339 intr->mask |= E1000_ICR_LSC;
2344 /* It clears the interrupt causes and enables the interrupt.
2345 * It will be called once only during nic initialized.
2348 * Pointer to struct rte_eth_dev.
2351 * - On success, zero.
2352 * - On failure, a negative value.
2354 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2356 uint32_t mask, regval;
2357 struct e1000_hw *hw =
2358 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359 struct rte_eth_dev_info dev_info;
2361 memset(&dev_info, 0, sizeof(dev_info));
2362 eth_igb_infos_get(dev, &dev_info);
2364 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2365 regval = E1000_READ_REG(hw, E1000_EIMS);
2366 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2372 * It reads ICR and gets interrupt causes, check it and set a bit flag
2373 * to update link status.
2376 * Pointer to struct rte_eth_dev.
2379 * - On success, zero.
2380 * - On failure, a negative value.
2383 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2386 struct e1000_hw *hw =
2387 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388 struct e1000_interrupt *intr =
2389 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391 igb_intr_disable(hw);
2393 /* read-on-clear nic registers here */
2394 icr = E1000_READ_REG(hw, E1000_ICR);
2397 if (icr & E1000_ICR_LSC) {
2398 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2401 if (icr & E1000_ICR_VMMB)
2402 intr->flags |= E1000_FLAG_MAILBOX;
2408 * It executes link_update after knowing an interrupt is prsent.
2411 * Pointer to struct rte_eth_dev.
2414 * - On success, zero.
2415 * - On failure, a negative value.
2418 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2420 struct e1000_hw *hw =
2421 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2422 struct e1000_interrupt *intr =
2423 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2424 uint32_t tctl, rctl;
2425 struct rte_eth_link link;
2428 if (intr->flags & E1000_FLAG_MAILBOX) {
2429 igb_pf_mbx_process(dev);
2430 intr->flags &= ~E1000_FLAG_MAILBOX;
2433 igb_intr_enable(dev);
2434 rte_intr_enable(&(dev->pci_dev->intr_handle));
2436 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2437 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2439 /* set get_link_status to check register later */
2440 hw->mac.get_link_status = 1;
2441 ret = eth_igb_link_update(dev, 0);
2443 /* check if link has changed */
2447 memset(&link, 0, sizeof(link));
2448 rte_igb_dev_atomic_read_link_status(dev, &link);
2449 if (link.link_status) {
2451 " Port %d: Link Up - speed %u Mbps - %s",
2453 (unsigned)link.link_speed,
2454 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2455 "full-duplex" : "half-duplex");
2457 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2458 dev->data->port_id);
2461 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2462 dev->pci_dev->addr.domain,
2463 dev->pci_dev->addr.bus,
2464 dev->pci_dev->addr.devid,
2465 dev->pci_dev->addr.function);
2466 tctl = E1000_READ_REG(hw, E1000_TCTL);
2467 rctl = E1000_READ_REG(hw, E1000_RCTL);
2468 if (link.link_status) {
2470 tctl |= E1000_TCTL_EN;
2471 rctl |= E1000_RCTL_EN;
2474 tctl &= ~E1000_TCTL_EN;
2475 rctl &= ~E1000_RCTL_EN;
2477 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2478 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2479 E1000_WRITE_FLUSH(hw);
2480 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2487 * Interrupt handler which shall be registered at first.
2490 * Pointer to interrupt handle.
2492 * The address of parameter (struct rte_eth_dev *) regsitered before.
2498 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2501 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2503 eth_igb_interrupt_get_status(dev);
2504 eth_igb_interrupt_action(dev);
2508 eth_igb_led_on(struct rte_eth_dev *dev)
2510 struct e1000_hw *hw;
2512 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2517 eth_igb_led_off(struct rte_eth_dev *dev)
2519 struct e1000_hw *hw;
2521 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2526 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2528 struct e1000_hw *hw;
2533 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534 fc_conf->pause_time = hw->fc.pause_time;
2535 fc_conf->high_water = hw->fc.high_water;
2536 fc_conf->low_water = hw->fc.low_water;
2537 fc_conf->send_xon = hw->fc.send_xon;
2538 fc_conf->autoneg = hw->mac.autoneg;
2541 * Return rx_pause and tx_pause status according to actual setting of
2542 * the TFCE and RFCE bits in the CTRL register.
2544 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2545 if (ctrl & E1000_CTRL_TFCE)
2550 if (ctrl & E1000_CTRL_RFCE)
2555 if (rx_pause && tx_pause)
2556 fc_conf->mode = RTE_FC_FULL;
2558 fc_conf->mode = RTE_FC_RX_PAUSE;
2560 fc_conf->mode = RTE_FC_TX_PAUSE;
2562 fc_conf->mode = RTE_FC_NONE;
2568 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2570 struct e1000_hw *hw;
2572 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2578 uint32_t rx_buf_size;
2579 uint32_t max_high_water;
2582 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2583 if (fc_conf->autoneg != hw->mac.autoneg)
2585 rx_buf_size = igb_get_rx_buffer_size(hw);
2586 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2588 /* At least reserve one Ethernet frame for watermark */
2589 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2590 if ((fc_conf->high_water > max_high_water) ||
2591 (fc_conf->high_water < fc_conf->low_water)) {
2592 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2593 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2597 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2598 hw->fc.pause_time = fc_conf->pause_time;
2599 hw->fc.high_water = fc_conf->high_water;
2600 hw->fc.low_water = fc_conf->low_water;
2601 hw->fc.send_xon = fc_conf->send_xon;
2603 err = e1000_setup_link_generic(hw);
2604 if (err == E1000_SUCCESS) {
2606 /* check if we want to forward MAC frames - driver doesn't have native
2607 * capability to do that, so we'll write the registers ourselves */
2609 rctl = E1000_READ_REG(hw, E1000_RCTL);
2611 /* set or clear MFLCN.PMCF bit depending on configuration */
2612 if (fc_conf->mac_ctrl_frame_fwd != 0)
2613 rctl |= E1000_RCTL_PMCF;
2615 rctl &= ~E1000_RCTL_PMCF;
2617 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2618 E1000_WRITE_FLUSH(hw);
2623 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2627 #define E1000_RAH_POOLSEL_SHIFT (18)
2629 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2630 uint32_t index, __rte_unused uint32_t pool)
2632 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2635 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2636 rah = E1000_READ_REG(hw, E1000_RAH(index));
2637 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2638 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2642 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2644 uint8_t addr[ETHER_ADDR_LEN];
2645 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647 memset(addr, 0, sizeof(addr));
2649 e1000_rar_set(hw, addr, index);
2653 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2654 struct ether_addr *addr)
2656 eth_igb_rar_clear(dev, 0);
2658 eth_igb_rar_set(dev, (void *)addr, 0, 0);
2661 * Virtual Function operations
2664 igbvf_intr_disable(struct e1000_hw *hw)
2666 PMD_INIT_FUNC_TRACE();
2668 /* Clear interrupt mask to stop from interrupts being generated */
2669 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2671 E1000_WRITE_FLUSH(hw);
2675 igbvf_stop_adapter(struct rte_eth_dev *dev)
2679 struct rte_eth_dev_info dev_info;
2680 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2682 memset(&dev_info, 0, sizeof(dev_info));
2683 eth_igbvf_infos_get(dev, &dev_info);
2685 /* Clear interrupt mask to stop from interrupts being generated */
2686 igbvf_intr_disable(hw);
2688 /* Clear any pending interrupts, flush previous writes */
2689 E1000_READ_REG(hw, E1000_EICR);
2691 /* Disable the transmit unit. Each queue must be disabled. */
2692 for (i = 0; i < dev_info.max_tx_queues; i++)
2693 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2695 /* Disable the receive unit by stopping each queue */
2696 for (i = 0; i < dev_info.max_rx_queues; i++) {
2697 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2698 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2699 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2700 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2704 /* flush all queues disables */
2705 E1000_WRITE_FLUSH(hw);
2709 static int eth_igbvf_link_update(struct e1000_hw *hw)
2711 struct e1000_mbx_info *mbx = &hw->mbx;
2712 struct e1000_mac_info *mac = &hw->mac;
2713 int ret_val = E1000_SUCCESS;
2715 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2718 * We only want to run this if there has been a rst asserted.
2719 * in this case that could mean a link change, device reset,
2720 * or a virtual function reset
2723 /* If we were hit with a reset or timeout drop the link */
2724 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2725 mac->get_link_status = TRUE;
2727 if (!mac->get_link_status)
2730 /* if link status is down no point in checking to see if pf is up */
2731 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2734 /* if we passed all the tests above then the link is up and we no
2735 * longer need to check for link */
2736 mac->get_link_status = FALSE;
2744 igbvf_dev_configure(struct rte_eth_dev *dev)
2746 struct rte_eth_conf* conf = &dev->data->dev_conf;
2748 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2749 dev->data->port_id);
2752 * VF has no ability to enable/disable HW CRC
2753 * Keep the persistent behavior the same as Host PF
2755 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2756 if (!conf->rxmode.hw_strip_crc) {
2757 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2758 conf->rxmode.hw_strip_crc = 1;
2761 if (conf->rxmode.hw_strip_crc) {
2762 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2763 conf->rxmode.hw_strip_crc = 0;
2771 igbvf_dev_start(struct rte_eth_dev *dev)
2773 struct e1000_hw *hw =
2774 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2775 struct e1000_adapter *adapter =
2776 E1000_DEV_PRIVATE(dev->data->dev_private);
2779 PMD_INIT_FUNC_TRACE();
2781 hw->mac.ops.reset_hw(hw);
2782 adapter->stopped = 0;
2785 igbvf_set_vfta_all(dev,1);
2787 eth_igbvf_tx_init(dev);
2789 /* This can fail when allocating mbufs for descriptor rings */
2790 ret = eth_igbvf_rx_init(dev);
2792 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2793 igb_dev_clear_queues(dev);
2801 igbvf_dev_stop(struct rte_eth_dev *dev)
2803 PMD_INIT_FUNC_TRACE();
2805 igbvf_stop_adapter(dev);
2808 * Clear what we set, but we still keep shadow_vfta to
2809 * restore after device starts
2811 igbvf_set_vfta_all(dev,0);
2813 igb_dev_clear_queues(dev);
2817 igbvf_dev_close(struct rte_eth_dev *dev)
2819 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820 struct e1000_adapter *adapter =
2821 E1000_DEV_PRIVATE(dev->data->dev_private);
2823 PMD_INIT_FUNC_TRACE();
2827 igbvf_dev_stop(dev);
2828 adapter->stopped = 1;
2829 igb_dev_free_queues(dev);
2832 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2834 struct e1000_mbx_info *mbx = &hw->mbx;
2838 /* After set vlan, vlan strip will also be enabled in igb driver*/
2839 msgbuf[0] = E1000_VF_SET_VLAN;
2841 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2843 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2845 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2849 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2853 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2854 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2861 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2863 struct e1000_hw *hw =
2864 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865 struct e1000_vfta * shadow_vfta =
2866 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2867 int i = 0, j = 0, vfta = 0, mask = 1;
2869 for (i = 0; i < IGB_VFTA_SIZE; i++){
2870 vfta = shadow_vfta->vfta[i];
2873 for (j = 0; j < 32; j++){
2876 (uint16_t)((i<<5)+j), on);
2885 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2887 struct e1000_hw *hw =
2888 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2889 struct e1000_vfta * shadow_vfta =
2890 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2891 uint32_t vid_idx = 0;
2892 uint32_t vid_bit = 0;
2895 PMD_INIT_FUNC_TRACE();
2897 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2898 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2900 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2903 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2904 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2906 /*Save what we set and retore it after device reset*/
2908 shadow_vfta->vfta[vid_idx] |= vid_bit;
2910 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2916 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2918 struct e1000_hw *hw =
2919 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921 /* index is not used by rar_set() */
2922 hw->mac.ops.rar_set(hw, (void *)addr, 0);
2927 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2928 struct rte_eth_rss_reta_entry64 *reta_conf,
2933 uint16_t idx, shift;
2934 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2937 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2938 "(%d) doesn't match the number hardware can supported "
2939 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2943 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2944 idx = i / RTE_RETA_GROUP_SIZE;
2945 shift = i % RTE_RETA_GROUP_SIZE;
2946 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2950 if (mask == IGB_4_BIT_MASK)
2953 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2954 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2955 if (mask & (0x1 << j))
2956 reta |= reta_conf[idx].reta[shift + j] <<
2959 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2961 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2968 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2969 struct rte_eth_rss_reta_entry64 *reta_conf,
2974 uint16_t idx, shift;
2975 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2977 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2978 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2979 "(%d) doesn't match the number hardware can supported "
2980 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2984 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2985 idx = i / RTE_RETA_GROUP_SIZE;
2986 shift = i % RTE_RETA_GROUP_SIZE;
2987 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2991 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2992 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2993 if (mask & (0x1 << j))
2994 reta_conf[idx].reta[shift + j] =
2995 ((reta >> (CHAR_BIT * j)) &
3003 #define MAC_TYPE_FILTER_SUP(type) do {\
3004 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3005 (type) != e1000_82576)\
3010 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3011 struct rte_eth_syn_filter *filter,
3014 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015 uint32_t synqf, rfctl;
3017 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3020 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3023 if (synqf & E1000_SYN_FILTER_ENABLE)
3026 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3027 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3029 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3030 if (filter->hig_pri)
3031 rfctl |= E1000_RFCTL_SYNQFP;
3033 rfctl &= ~E1000_RFCTL_SYNQFP;
3035 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3037 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3042 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3043 E1000_WRITE_FLUSH(hw);
3048 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3049 struct rte_eth_syn_filter *filter)
3051 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3052 uint32_t synqf, rfctl;
3054 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3055 if (synqf & E1000_SYN_FILTER_ENABLE) {
3056 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3057 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3058 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3059 E1000_SYN_FILTER_QUEUE_SHIFT);
3067 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3068 enum rte_filter_op filter_op,
3071 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074 MAC_TYPE_FILTER_SUP(hw->mac.type);
3076 if (filter_op == RTE_ETH_FILTER_NOP)
3080 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3085 switch (filter_op) {
3086 case RTE_ETH_FILTER_ADD:
3087 ret = eth_igb_syn_filter_set(dev,
3088 (struct rte_eth_syn_filter *)arg,
3091 case RTE_ETH_FILTER_DELETE:
3092 ret = eth_igb_syn_filter_set(dev,
3093 (struct rte_eth_syn_filter *)arg,
3096 case RTE_ETH_FILTER_GET:
3097 ret = eth_igb_syn_filter_get(dev,
3098 (struct rte_eth_syn_filter *)arg);
3101 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3109 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3110 if ((type) != e1000_82580 && (type) != e1000_i350)\
3114 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3116 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3117 struct e1000_2tuple_filter_info *filter_info)
3119 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3121 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3122 return -EINVAL; /* filter index is out of range. */
3123 if (filter->tcp_flags > TCP_FLAG_ALL)
3124 return -EINVAL; /* flags is invalid. */
3126 switch (filter->dst_port_mask) {
3128 filter_info->dst_port_mask = 0;
3129 filter_info->dst_port = filter->dst_port;
3132 filter_info->dst_port_mask = 1;
3135 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3139 switch (filter->proto_mask) {
3141 filter_info->proto_mask = 0;
3142 filter_info->proto = filter->proto;
3145 filter_info->proto_mask = 1;
3148 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3152 filter_info->priority = (uint8_t)filter->priority;
3153 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3154 filter_info->tcp_flags = filter->tcp_flags;
3156 filter_info->tcp_flags = 0;
3161 static inline struct e1000_2tuple_filter *
3162 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3163 struct e1000_2tuple_filter_info *key)
3165 struct e1000_2tuple_filter *it;
3167 TAILQ_FOREACH(it, filter_list, entries) {
3168 if (memcmp(key, &it->filter_info,
3169 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3177 * igb_add_2tuple_filter - add a 2tuple filter
3180 * dev: Pointer to struct rte_eth_dev.
3181 * ntuple_filter: ponter to the filter that will be added.
3184 * - On success, zero.
3185 * - On failure, a negative value.
3188 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3189 struct rte_eth_ntuple_filter *ntuple_filter)
3191 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3192 struct e1000_filter_info *filter_info =
3193 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3194 struct e1000_2tuple_filter *filter;
3195 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3196 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3199 filter = rte_zmalloc("e1000_2tuple_filter",
3200 sizeof(struct e1000_2tuple_filter), 0);
3204 ret = ntuple_filter_to_2tuple(ntuple_filter,
3205 &filter->filter_info);
3210 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3211 &filter->filter_info) != NULL) {
3212 PMD_DRV_LOG(ERR, "filter exists.");
3216 filter->queue = ntuple_filter->queue;
3219 * look for an unused 2tuple filter index,
3220 * and insert the filter to list.
3222 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3223 if (!(filter_info->twotuple_mask & (1 << i))) {
3224 filter_info->twotuple_mask |= 1 << i;
3226 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3232 if (i >= E1000_MAX_TTQF_FILTERS) {
3233 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3238 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3239 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3240 imir |= E1000_IMIR_PORT_BP;
3242 imir &= ~E1000_IMIR_PORT_BP;
3244 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3246 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3247 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3248 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3249 if (filter->filter_info.proto_mask == 0)
3250 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3252 /* tcp flags bits setting. */
3253 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3254 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3255 imir_ext |= E1000_IMIREXT_CTRL_URG;
3256 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3257 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3258 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3259 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3260 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3261 imir_ext |= E1000_IMIREXT_CTRL_RST;
3262 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3263 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3264 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3265 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3267 imir_ext |= E1000_IMIREXT_CTRL_BP;
3268 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3269 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3270 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3275 * igb_remove_2tuple_filter - remove a 2tuple filter
3278 * dev: Pointer to struct rte_eth_dev.
3279 * ntuple_filter: ponter to the filter that will be removed.
3282 * - On success, zero.
3283 * - On failure, a negative value.
3286 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3287 struct rte_eth_ntuple_filter *ntuple_filter)
3289 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3290 struct e1000_filter_info *filter_info =
3291 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3292 struct e1000_2tuple_filter_info filter_2tuple;
3293 struct e1000_2tuple_filter *filter;
3296 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3297 ret = ntuple_filter_to_2tuple(ntuple_filter,
3302 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3304 if (filter == NULL) {
3305 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3309 filter_info->twotuple_mask &= ~(1 << filter->index);
3310 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3313 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3314 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3315 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3319 static inline struct e1000_flex_filter *
3320 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3321 struct e1000_flex_filter_info *key)
3323 struct e1000_flex_filter *it;
3325 TAILQ_FOREACH(it, filter_list, entries) {
3326 if (memcmp(key, &it->filter_info,
3327 sizeof(struct e1000_flex_filter_info)) == 0)
3335 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3336 struct rte_eth_flex_filter *filter,
3339 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340 struct e1000_filter_info *filter_info =
3341 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3342 struct e1000_flex_filter *flex_filter, *it;
3343 uint32_t wufc, queueing, mask;
3345 uint8_t shift, i, j = 0;
3347 flex_filter = rte_zmalloc("e1000_flex_filter",
3348 sizeof(struct e1000_flex_filter), 0);
3349 if (flex_filter == NULL)
3352 flex_filter->filter_info.len = filter->len;
3353 flex_filter->filter_info.priority = filter->priority;
3354 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3355 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3357 /* reverse bits in flex filter's mask*/
3358 for (shift = 0; shift < CHAR_BIT; shift++) {
3359 if (filter->mask[i] & (0x01 << shift))
3360 mask |= (0x80 >> shift);
3362 flex_filter->filter_info.mask[i] = mask;
3365 wufc = E1000_READ_REG(hw, E1000_WUFC);
3366 if (flex_filter->index < E1000_MAX_FHFT)
3367 reg_off = E1000_FHFT(flex_filter->index);
3369 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3372 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3373 &flex_filter->filter_info) != NULL) {
3374 PMD_DRV_LOG(ERR, "filter exists.");
3375 rte_free(flex_filter);
3378 flex_filter->queue = filter->queue;
3380 * look for an unused flex filter index
3381 * and insert the filter into the list.
3383 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3384 if (!(filter_info->flex_mask & (1 << i))) {
3385 filter_info->flex_mask |= 1 << i;
3386 flex_filter->index = i;
3387 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3393 if (i >= E1000_MAX_FLEX_FILTERS) {
3394 PMD_DRV_LOG(ERR, "flex filters are full.");
3395 rte_free(flex_filter);
3399 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3400 (E1000_WUFC_FLX0 << flex_filter->index));
3401 queueing = filter->len |
3402 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3403 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3404 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3406 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3407 E1000_WRITE_REG(hw, reg_off,
3408 flex_filter->filter_info.dwords[j]);
3409 reg_off += sizeof(uint32_t);
3410 E1000_WRITE_REG(hw, reg_off,
3411 flex_filter->filter_info.dwords[++j]);
3412 reg_off += sizeof(uint32_t);
3413 E1000_WRITE_REG(hw, reg_off,
3414 (uint32_t)flex_filter->filter_info.mask[i]);
3415 reg_off += sizeof(uint32_t) * 2;
3419 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3420 &flex_filter->filter_info);
3422 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3423 rte_free(flex_filter);
3427 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3428 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3429 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3430 (~(E1000_WUFC_FLX0 << it->index)));
3432 filter_info->flex_mask &= ~(1 << it->index);
3433 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3435 rte_free(flex_filter);
3442 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3443 struct rte_eth_flex_filter *filter)
3445 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3446 struct e1000_filter_info *filter_info =
3447 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3448 struct e1000_flex_filter flex_filter, *it;
3449 uint32_t wufc, queueing, wufc_en = 0;
3451 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3452 flex_filter.filter_info.len = filter->len;
3453 flex_filter.filter_info.priority = filter->priority;
3454 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3455 memcpy(flex_filter.filter_info.mask, filter->mask,
3456 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3458 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3459 &flex_filter.filter_info);
3461 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3465 wufc = E1000_READ_REG(hw, E1000_WUFC);
3466 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3468 if ((wufc & wufc_en) == wufc_en) {
3469 uint32_t reg_off = 0;
3470 if (it->index < E1000_MAX_FHFT)
3471 reg_off = E1000_FHFT(it->index);
3473 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3475 queueing = E1000_READ_REG(hw,
3476 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3477 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3478 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3479 E1000_FHFT_QUEUEING_PRIO_SHIFT;
3480 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3481 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3488 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3489 enum rte_filter_op filter_op,
3492 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3493 struct rte_eth_flex_filter *filter;
3496 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3498 if (filter_op == RTE_ETH_FILTER_NOP)
3502 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3507 filter = (struct rte_eth_flex_filter *)arg;
3508 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3509 || filter->len % sizeof(uint64_t) != 0) {
3510 PMD_DRV_LOG(ERR, "filter's length is out of range");
3513 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3514 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3518 switch (filter_op) {
3519 case RTE_ETH_FILTER_ADD:
3520 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3522 case RTE_ETH_FILTER_DELETE:
3523 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3525 case RTE_ETH_FILTER_GET:
3526 ret = eth_igb_get_flex_filter(dev, filter);
3529 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3537 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3539 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3540 struct e1000_5tuple_filter_info *filter_info)
3542 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3544 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3545 return -EINVAL; /* filter index is out of range. */
3546 if (filter->tcp_flags > TCP_FLAG_ALL)
3547 return -EINVAL; /* flags is invalid. */
3549 switch (filter->dst_ip_mask) {
3551 filter_info->dst_ip_mask = 0;
3552 filter_info->dst_ip = filter->dst_ip;
3555 filter_info->dst_ip_mask = 1;
3558 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3562 switch (filter->src_ip_mask) {
3564 filter_info->src_ip_mask = 0;
3565 filter_info->src_ip = filter->src_ip;
3568 filter_info->src_ip_mask = 1;
3571 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3575 switch (filter->dst_port_mask) {
3577 filter_info->dst_port_mask = 0;
3578 filter_info->dst_port = filter->dst_port;
3581 filter_info->dst_port_mask = 1;
3584 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3588 switch (filter->src_port_mask) {
3590 filter_info->src_port_mask = 0;
3591 filter_info->src_port = filter->src_port;
3594 filter_info->src_port_mask = 1;
3597 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3601 switch (filter->proto_mask) {
3603 filter_info->proto_mask = 0;
3604 filter_info->proto = filter->proto;
3607 filter_info->proto_mask = 1;
3610 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3614 filter_info->priority = (uint8_t)filter->priority;
3615 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3616 filter_info->tcp_flags = filter->tcp_flags;
3618 filter_info->tcp_flags = 0;
3623 static inline struct e1000_5tuple_filter *
3624 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3625 struct e1000_5tuple_filter_info *key)
3627 struct e1000_5tuple_filter *it;
3629 TAILQ_FOREACH(it, filter_list, entries) {
3630 if (memcmp(key, &it->filter_info,
3631 sizeof(struct e1000_5tuple_filter_info)) == 0) {
3639 * igb_add_5tuple_filter_82576 - add a 5tuple filter
3642 * dev: Pointer to struct rte_eth_dev.
3643 * ntuple_filter: ponter to the filter that will be added.
3646 * - On success, zero.
3647 * - On failure, a negative value.
3650 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3651 struct rte_eth_ntuple_filter *ntuple_filter)
3653 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3654 struct e1000_filter_info *filter_info =
3655 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3656 struct e1000_5tuple_filter *filter;
3657 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3658 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3662 filter = rte_zmalloc("e1000_5tuple_filter",
3663 sizeof(struct e1000_5tuple_filter), 0);
3667 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3668 &filter->filter_info);
3674 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3675 &filter->filter_info) != NULL) {
3676 PMD_DRV_LOG(ERR, "filter exists.");
3680 filter->queue = ntuple_filter->queue;
3683 * look for an unused 5tuple filter index,
3684 * and insert the filter to list.
3686 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3687 if (!(filter_info->fivetuple_mask & (1 << i))) {
3688 filter_info->fivetuple_mask |= 1 << i;
3690 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3696 if (i >= E1000_MAX_FTQF_FILTERS) {
3697 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3702 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3703 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3704 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3705 if (filter->filter_info.dst_ip_mask == 0)
3706 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3707 if (filter->filter_info.src_port_mask == 0)
3708 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3709 if (filter->filter_info.proto_mask == 0)
3710 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3711 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3712 E1000_FTQF_QUEUE_MASK;
3713 ftqf |= E1000_FTQF_QUEUE_ENABLE;
3714 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3715 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3716 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3718 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3719 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3721 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3722 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3723 imir |= E1000_IMIR_PORT_BP;
3725 imir &= ~E1000_IMIR_PORT_BP;
3726 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3728 /* tcp flags bits setting. */
3729 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3730 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3731 imir_ext |= E1000_IMIREXT_CTRL_URG;
3732 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3733 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3734 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3735 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3736 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3737 imir_ext |= E1000_IMIREXT_CTRL_RST;
3738 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3739 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3740 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3741 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3743 imir_ext |= E1000_IMIREXT_CTRL_BP;
3744 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3745 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3750 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3753 * dev: Pointer to struct rte_eth_dev.
3754 * ntuple_filter: ponter to the filter that will be removed.
3757 * - On success, zero.
3758 * - On failure, a negative value.
3761 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3762 struct rte_eth_ntuple_filter *ntuple_filter)
3764 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3765 struct e1000_filter_info *filter_info =
3766 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3767 struct e1000_5tuple_filter_info filter_5tuple;
3768 struct e1000_5tuple_filter *filter;
3771 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3772 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3777 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3779 if (filter == NULL) {
3780 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3784 filter_info->fivetuple_mask &= ~(1 << filter->index);
3785 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3788 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3789 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3790 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3791 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3792 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3793 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3794 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3799 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3802 struct e1000_hw *hw;
3803 struct rte_eth_dev_info dev_info;
3804 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3807 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3809 #ifdef RTE_LIBRTE_82571_SUPPORT
3810 /* XXX: not bigger than max_rx_pktlen */
3811 if (hw->mac.type == e1000_82571)
3814 eth_igb_infos_get(dev, &dev_info);
3816 /* check that mtu is within the allowed range */
3817 if ((mtu < ETHER_MIN_MTU) ||
3818 (frame_size > dev_info.max_rx_pktlen))
3821 /* refuse mtu that requires the support of scattered packets when this
3822 * feature has not been enabled before. */
3823 if (!dev->data->scattered_rx &&
3824 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3827 rctl = E1000_READ_REG(hw, E1000_RCTL);
3829 /* switch to jumbo mode if needed */
3830 if (frame_size > ETHER_MAX_LEN) {
3831 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3832 rctl |= E1000_RCTL_LPE;
3834 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3835 rctl &= ~E1000_RCTL_LPE;
3837 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3839 /* update max frame size */
3840 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3842 E1000_WRITE_REG(hw, E1000_RLPML,
3843 dev->data->dev_conf.rxmode.max_rx_pkt_len);
3849 * igb_add_del_ntuple_filter - add or delete a ntuple filter
3852 * dev: Pointer to struct rte_eth_dev.
3853 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3854 * add: if true, add filter, if false, remove filter
3857 * - On success, zero.
3858 * - On failure, a negative value.
3861 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3862 struct rte_eth_ntuple_filter *ntuple_filter,
3865 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3868 switch (ntuple_filter->flags) {
3869 case RTE_5TUPLE_FLAGS:
3870 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3871 if (hw->mac.type != e1000_82576)
3874 ret = igb_add_5tuple_filter_82576(dev,
3877 ret = igb_remove_5tuple_filter_82576(dev,
3880 case RTE_2TUPLE_FLAGS:
3881 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3882 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3885 ret = igb_add_2tuple_filter(dev, ntuple_filter);
3887 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3898 * igb_get_ntuple_filter - get a ntuple filter
3901 * dev: Pointer to struct rte_eth_dev.
3902 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3905 * - On success, zero.
3906 * - On failure, a negative value.
3909 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3910 struct rte_eth_ntuple_filter *ntuple_filter)
3912 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3913 struct e1000_filter_info *filter_info =
3914 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3915 struct e1000_5tuple_filter_info filter_5tuple;
3916 struct e1000_2tuple_filter_info filter_2tuple;
3917 struct e1000_5tuple_filter *p_5tuple_filter;
3918 struct e1000_2tuple_filter *p_2tuple_filter;
3921 switch (ntuple_filter->flags) {
3922 case RTE_5TUPLE_FLAGS:
3923 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3924 if (hw->mac.type != e1000_82576)
3926 memset(&filter_5tuple,
3928 sizeof(struct e1000_5tuple_filter_info));
3929 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3933 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3934 &filter_info->fivetuple_list,
3936 if (p_5tuple_filter == NULL) {
3937 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3940 ntuple_filter->queue = p_5tuple_filter->queue;
3942 case RTE_2TUPLE_FLAGS:
3943 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3944 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3946 memset(&filter_2tuple,
3948 sizeof(struct e1000_2tuple_filter_info));
3949 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3952 p_2tuple_filter = igb_2tuple_filter_lookup(
3953 &filter_info->twotuple_list,
3955 if (p_2tuple_filter == NULL) {
3956 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3959 ntuple_filter->queue = p_2tuple_filter->queue;
3970 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3971 * @dev: pointer to rte_eth_dev structure
3972 * @filter_op:operation will be taken.
3973 * @arg: a pointer to specific structure corresponding to the filter_op
3976 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3977 enum rte_filter_op filter_op,
3980 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3983 MAC_TYPE_FILTER_SUP(hw->mac.type);
3985 if (filter_op == RTE_ETH_FILTER_NOP)
3989 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3994 switch (filter_op) {
3995 case RTE_ETH_FILTER_ADD:
3996 ret = igb_add_del_ntuple_filter(dev,
3997 (struct rte_eth_ntuple_filter *)arg,
4000 case RTE_ETH_FILTER_DELETE:
4001 ret = igb_add_del_ntuple_filter(dev,
4002 (struct rte_eth_ntuple_filter *)arg,
4005 case RTE_ETH_FILTER_GET:
4006 ret = igb_get_ntuple_filter(dev,
4007 (struct rte_eth_ntuple_filter *)arg);
4010 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4018 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4023 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4024 if (filter_info->ethertype_filters[i] == ethertype &&
4025 (filter_info->ethertype_mask & (1 << i)))
4032 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4037 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4038 if (!(filter_info->ethertype_mask & (1 << i))) {
4039 filter_info->ethertype_mask |= 1 << i;
4040 filter_info->ethertype_filters[i] = ethertype;
4048 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4051 if (idx >= E1000_MAX_ETQF_FILTERS)
4053 filter_info->ethertype_mask &= ~(1 << idx);
4054 filter_info->ethertype_filters[idx] = 0;
4060 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4061 struct rte_eth_ethertype_filter *filter,
4064 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065 struct e1000_filter_info *filter_info =
4066 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4070 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4071 filter->ether_type == ETHER_TYPE_IPv6) {
4072 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4073 " ethertype filter.", filter->ether_type);
4077 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4078 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4081 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4082 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4086 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4087 if (ret >= 0 && add) {
4088 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4089 filter->ether_type);
4092 if (ret < 0 && !add) {
4093 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4094 filter->ether_type);
4099 ret = igb_ethertype_filter_insert(filter_info,
4100 filter->ether_type);
4102 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4106 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4107 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4108 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4110 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4114 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4115 E1000_WRITE_FLUSH(hw);
4121 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4122 struct rte_eth_ethertype_filter *filter)
4124 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4125 struct e1000_filter_info *filter_info =
4126 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4130 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4132 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4133 filter->ether_type);
4137 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4138 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4139 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4141 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4142 E1000_ETQF_QUEUE_SHIFT;
4150 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4151 * @dev: pointer to rte_eth_dev structure
4152 * @filter_op:operation will be taken.
4153 * @arg: a pointer to specific structure corresponding to the filter_op
4156 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4157 enum rte_filter_op filter_op,
4160 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4163 MAC_TYPE_FILTER_SUP(hw->mac.type);
4165 if (filter_op == RTE_ETH_FILTER_NOP)
4169 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4174 switch (filter_op) {
4175 case RTE_ETH_FILTER_ADD:
4176 ret = igb_add_del_ethertype_filter(dev,
4177 (struct rte_eth_ethertype_filter *)arg,
4180 case RTE_ETH_FILTER_DELETE:
4181 ret = igb_add_del_ethertype_filter(dev,
4182 (struct rte_eth_ethertype_filter *)arg,
4185 case RTE_ETH_FILTER_GET:
4186 ret = igb_get_ethertype_filter(dev,
4187 (struct rte_eth_ethertype_filter *)arg);
4190 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4198 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4199 enum rte_filter_type filter_type,
4200 enum rte_filter_op filter_op,
4205 switch (filter_type) {
4206 case RTE_ETH_FILTER_NTUPLE:
4207 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4209 case RTE_ETH_FILTER_ETHERTYPE:
4210 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4212 case RTE_ETH_FILTER_SYN:
4213 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4215 case RTE_ETH_FILTER_FLEXIBLE:
4216 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4219 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4228 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4229 struct ether_addr *mc_addr_set,
4230 uint32_t nb_mc_addr)
4232 struct e1000_hw *hw;
4234 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4240 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4242 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4243 uint64_t systime_cycles;
4245 switch (hw->mac.type) {
4249 * Need to read System Time Residue Register to be able
4250 * to read the other two registers.
4252 E1000_READ_REG(hw, E1000_SYSTIMR);
4253 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4254 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4255 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4262 * Need to read System Time Residue Register to be able
4263 * to read the other two registers.
4265 E1000_READ_REG(hw, E1000_SYSTIMR);
4266 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4267 /* Only the 8 LSB are valid. */
4268 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4272 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4273 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4278 return systime_cycles;
4282 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4284 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4285 uint64_t rx_tstamp_cycles;
4287 switch (hw->mac.type) {
4290 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4291 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4292 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4298 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4299 /* Only the 8 LSB are valid. */
4300 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4304 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4305 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4310 return rx_tstamp_cycles;
4314 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4316 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4317 uint64_t tx_tstamp_cycles;
4319 switch (hw->mac.type) {
4322 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4323 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4324 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4330 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4331 /* Only the 8 LSB are valid. */
4332 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4336 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4337 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4342 return tx_tstamp_cycles;
4346 igb_start_timecounters(struct rte_eth_dev *dev)
4348 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4349 struct e1000_adapter *adapter =
4350 (struct e1000_adapter *)dev->data->dev_private;
4351 uint32_t incval = 1;
4353 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4355 switch (hw->mac.type) {
4359 /* 32 LSB bits + 8 MSB bits = 40 bits */
4360 mask = (1ULL << 40) - 1;
4365 * Start incrementing the register
4366 * used to timestamp PTP packets.
4368 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4371 incval = E1000_INCVALUE_82576;
4372 shift = IGB_82576_TSYNC_SHIFT;
4373 E1000_WRITE_REG(hw, E1000_TIMINCA,
4374 E1000_INCPERIOD_82576 | incval);
4381 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4382 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4383 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4385 adapter->systime_tc.cc_mask = mask;
4386 adapter->systime_tc.cc_shift = shift;
4387 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4389 adapter->rx_tstamp_tc.cc_mask = mask;
4390 adapter->rx_tstamp_tc.cc_shift = shift;
4391 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4393 adapter->tx_tstamp_tc.cc_mask = mask;
4394 adapter->tx_tstamp_tc.cc_shift = shift;
4395 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4399 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4401 struct e1000_adapter *adapter =
4402 (struct e1000_adapter *)dev->data->dev_private;
4404 adapter->systime_tc.nsec += delta;
4405 adapter->rx_tstamp_tc.nsec += delta;
4406 adapter->tx_tstamp_tc.nsec += delta;
4412 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4415 struct e1000_adapter *adapter =
4416 (struct e1000_adapter *)dev->data->dev_private;
4418 ns = rte_timespec_to_ns(ts);
4420 /* Set the timecounters to a new value. */
4421 adapter->systime_tc.nsec = ns;
4422 adapter->rx_tstamp_tc.nsec = ns;
4423 adapter->tx_tstamp_tc.nsec = ns;
4429 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4431 uint64_t ns, systime_cycles;
4432 struct e1000_adapter *adapter =
4433 (struct e1000_adapter *)dev->data->dev_private;
4435 systime_cycles = igb_read_systime_cyclecounter(dev);
4436 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4437 *ts = rte_ns_to_timespec(ns);
4443 igb_timesync_enable(struct rte_eth_dev *dev)
4445 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4449 /* Stop the timesync system time. */
4450 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4451 /* Reset the timesync system time value. */
4452 switch (hw->mac.type) {
4458 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4461 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4462 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4465 /* Not supported. */
4469 /* Enable system time for it isn't on by default. */
4470 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4471 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4472 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4474 igb_start_timecounters(dev);
4476 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4477 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4479 E1000_ETQF_FILTER_ENABLE |
4482 /* Enable timestamping of received PTP packets. */
4483 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4484 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4485 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4487 /* Enable Timestamping of transmitted PTP packets. */
4488 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4489 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4490 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4496 igb_timesync_disable(struct rte_eth_dev *dev)
4498 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4501 /* Disable timestamping of transmitted PTP packets. */
4502 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4503 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4504 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4506 /* Disable timestamping of received PTP packets. */
4507 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4508 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4509 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4511 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4512 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4514 /* Stop incrementating the System Time registers. */
4515 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4521 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4522 struct timespec *timestamp,
4523 uint32_t flags __rte_unused)
4525 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4526 struct e1000_adapter *adapter =
4527 (struct e1000_adapter *)dev->data->dev_private;
4528 uint32_t tsync_rxctl;
4529 uint64_t rx_tstamp_cycles;
4532 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4533 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4536 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4537 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4538 *timestamp = rte_ns_to_timespec(ns);
4544 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4545 struct timespec *timestamp)
4547 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4548 struct e1000_adapter *adapter =
4549 (struct e1000_adapter *)dev->data->dev_private;
4550 uint32_t tsync_txctl;
4551 uint64_t tx_tstamp_cycles;
4554 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4555 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4558 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4559 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4560 *timestamp = rte_ns_to_timespec(ns);
4566 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4570 const struct reg_info *reg_group;
4572 while ((reg_group = igb_regs[g_ind++]))
4573 count += igb_reg_group_count(reg_group);
4579 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4583 const struct reg_info *reg_group;
4585 while ((reg_group = igbvf_regs[g_ind++]))
4586 count += igb_reg_group_count(reg_group);
4592 eth_igb_get_regs(struct rte_eth_dev *dev,
4593 struct rte_dev_reg_info *regs)
4595 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4596 uint32_t *data = regs->data;
4599 const struct reg_info *reg_group;
4601 /* Support only full register dump */
4602 if ((regs->length == 0) ||
4603 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4604 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4606 while ((reg_group = igb_regs[g_ind++]))
4607 count += igb_read_regs_group(dev, &data[count],
4616 igbvf_get_regs(struct rte_eth_dev *dev,
4617 struct rte_dev_reg_info *regs)
4619 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4620 uint32_t *data = regs->data;
4623 const struct reg_info *reg_group;
4625 /* Support only full register dump */
4626 if ((regs->length == 0) ||
4627 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4628 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4630 while ((reg_group = igbvf_regs[g_ind++]))
4631 count += igb_read_regs_group(dev, &data[count],
4640 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4642 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4644 /* Return unit is byte count */
4645 return hw->nvm.word_size * 2;
4649 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4650 struct rte_dev_eeprom_info *in_eeprom)
4652 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4653 struct e1000_nvm_info *nvm = &hw->nvm;
4654 uint16_t *data = in_eeprom->data;
4657 first = in_eeprom->offset >> 1;
4658 length = in_eeprom->length >> 1;
4659 if ((first >= hw->nvm.word_size) ||
4660 ((first + length) >= hw->nvm.word_size))
4663 in_eeprom->magic = hw->vendor_id |
4664 ((uint32_t)hw->device_id << 16);
4666 if ((nvm->ops.read) == NULL)
4669 return nvm->ops.read(hw, first, length, data);
4673 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4674 struct rte_dev_eeprom_info *in_eeprom)
4676 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677 struct e1000_nvm_info *nvm = &hw->nvm;
4678 uint16_t *data = in_eeprom->data;
4681 first = in_eeprom->offset >> 1;
4682 length = in_eeprom->length >> 1;
4683 if ((first >= hw->nvm.word_size) ||
4684 ((first + length) >= hw->nvm.word_size))
4687 in_eeprom->magic = (uint32_t)hw->vendor_id |
4688 ((uint32_t)hw->device_id << 16);
4690 if ((nvm->ops.write) == NULL)
4692 return nvm->ops.write(hw, first, length, data);
4695 static struct rte_driver pmd_igb_drv = {
4697 .init = rte_igb_pmd_init,
4700 static struct rte_driver pmd_igbvf_drv = {
4702 .init = rte_igbvf_pmd_init,
4706 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4708 struct e1000_hw *hw =
4709 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4710 uint32_t mask = 1 << queue_id;
4712 E1000_WRITE_REG(hw, E1000_EIMC, mask);
4713 E1000_WRITE_FLUSH(hw);
4719 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4721 struct e1000_hw *hw =
4722 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4723 uint32_t mask = 1 << queue_id;
4726 regval = E1000_READ_REG(hw, E1000_EIMS);
4727 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4728 E1000_WRITE_FLUSH(hw);
4730 rte_intr_enable(&dev->pci_dev->intr_handle);
4736 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
4737 uint8_t index, uint8_t offset)
4739 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4742 val &= ~((uint32_t)0xFF << offset);
4744 /* write vector and valid bit */
4745 val |= (msix_vector | E1000_IVAR_VALID) << offset;
4747 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4751 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4752 uint8_t queue, uint8_t msix_vector)
4756 if (hw->mac.type == e1000_82575) {
4758 tmp = E1000_EICR_RX_QUEUE0 << queue;
4759 else if (direction == 1)
4760 tmp = E1000_EICR_TX_QUEUE0 << queue;
4761 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4762 } else if (hw->mac.type == e1000_82576) {
4763 if ((direction == 0) || (direction == 1))
4764 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4765 ((queue & 0x8) << 1) +
4767 } else if ((hw->mac.type == e1000_82580) ||
4768 (hw->mac.type == e1000_i350) ||
4769 (hw->mac.type == e1000_i354) ||
4770 (hw->mac.type == e1000_i210) ||
4771 (hw->mac.type == e1000_i211)) {
4772 if ((direction == 0) || (direction == 1))
4773 eth_igb_write_ivar(hw, msix_vector,
4775 ((queue & 0x1) << 4) +
4780 /* Sets up the hardware to generate MSI-X interrupts properly
4782 * board private structure
4785 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4788 uint32_t tmpval, regval, intr_mask;
4789 struct e1000_hw *hw =
4790 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791 uint32_t vec = E1000_MISC_VEC_ID;
4792 uint32_t base = E1000_MISC_VEC_ID;
4793 uint32_t misc_shift = 0;
4795 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4797 /* won't configure msix register if no mapping is done
4798 * between intr vector and event fd
4800 if (!rte_intr_dp_is_en(intr_handle))
4803 if (rte_intr_allow_others(intr_handle)) {
4804 vec = base = E1000_RX_VEC_START;
4808 /* set interrupt vector for other causes */
4809 if (hw->mac.type == e1000_82575) {
4810 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4811 /* enable MSI-X PBA support */
4812 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4814 /* Auto-Mask interrupts upon ICR read */
4815 tmpval |= E1000_CTRL_EXT_EIAME;
4816 tmpval |= E1000_CTRL_EXT_IRCA;
4818 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4820 /* enable msix_other interrupt */
4821 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4822 regval = E1000_READ_REG(hw, E1000_EIAC);
4823 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4824 regval = E1000_READ_REG(hw, E1000_EIAM);
4825 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4826 } else if ((hw->mac.type == e1000_82576) ||
4827 (hw->mac.type == e1000_82580) ||
4828 (hw->mac.type == e1000_i350) ||
4829 (hw->mac.type == e1000_i354) ||
4830 (hw->mac.type == e1000_i210) ||
4831 (hw->mac.type == e1000_i211)) {
4832 /* turn on MSI-X capability first */
4833 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4834 E1000_GPIE_PBA | E1000_GPIE_EIAME |
4836 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4838 regval = E1000_READ_REG(hw, E1000_EIAC);
4839 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4841 /* enable msix_other interrupt */
4842 regval = E1000_READ_REG(hw, E1000_EIMS);
4843 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4844 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4845 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4848 /* use EIAM to auto-mask when MSI-X interrupt
4849 * is asserted, this saves a register write for every interrupt
4851 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4853 regval = E1000_READ_REG(hw, E1000_EIAM);
4854 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4856 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4857 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4858 intr_handle->intr_vec[queue_id] = vec;
4859 if (vec < base + intr_handle->nb_efd - 1)
4863 E1000_WRITE_FLUSH(hw);
4866 PMD_REGISTER_DRIVER(pmd_igb_drv);
4867 PMD_REGISTER_DRIVER(pmd_igbvf_drv);