1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static int eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static int eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
158 static int igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
190 struct rte_eth_ntuple_filter *ntuple_filter);
191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
194 struct rte_eth_ntuple_filter *ntuple_filter);
195 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
196 struct rte_eth_ntuple_filter *ntuple_filter);
197 static int eth_igb_flow_ops_get(struct rte_eth_dev *dev,
198 const struct rte_flow_ops **ops);
199 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
200 static int eth_igb_get_regs(struct rte_eth_dev *dev,
201 struct rte_dev_reg_info *regs);
202 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
203 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
204 struct rte_dev_eeprom_info *eeprom);
205 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
206 struct rte_dev_eeprom_info *eeprom);
207 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
208 struct rte_eth_dev_module_info *modinfo);
209 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
210 struct rte_dev_eeprom_info *info);
211 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
212 struct rte_ether_addr *mc_addr_set,
213 uint32_t nb_mc_addr);
214 static int igb_timesync_enable(struct rte_eth_dev *dev);
215 static int igb_timesync_disable(struct rte_eth_dev *dev);
216 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
217 struct timespec *timestamp,
219 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
220 struct timespec *timestamp);
221 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
222 static int igb_timesync_read_time(struct rte_eth_dev *dev,
223 struct timespec *timestamp);
224 static int igb_timesync_write_time(struct rte_eth_dev *dev,
225 const struct timespec *timestamp);
226 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
228 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
230 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
231 uint8_t queue, uint8_t msix_vector);
232 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
233 uint8_t index, uint8_t offset);
234 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
235 static void eth_igbvf_interrupt_handler(void *param);
236 static void igbvf_mbx_process(struct rte_eth_dev *dev);
237 static int igb_filter_restore(struct rte_eth_dev *dev);
240 * Define VF Stats MACRO for Non "cleared on read" register
242 #define UPDATE_VF_STAT(reg, last, cur) \
244 u32 latest = E1000_READ_REG(hw, reg); \
245 cur += (latest - last) & UINT_MAX; \
249 #define IGB_FC_PAUSE_TIME 0x0680
250 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
251 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
253 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
255 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
258 * The set of PCI devices this driver supports
260 static const struct rte_pci_id pci_id_igb_map[] = {
261 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
262 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
263 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
264 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
265 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
266 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
267 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
268 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
270 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
271 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
272 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
274 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
275 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
276 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
302 { .vendor_id = 0, /* sentinel */ },
306 * The set of PCI devices this driver supports (for 82576&I350 VF)
308 static const struct rte_pci_id pci_id_igbvf_map[] = {
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
313 { .vendor_id = 0, /* sentinel */ },
316 static const struct rte_eth_desc_lim rx_desc_lim = {
317 .nb_max = E1000_MAX_RING_DESC,
318 .nb_min = E1000_MIN_RING_DESC,
319 .nb_align = IGB_RXD_ALIGN,
322 static const struct rte_eth_desc_lim tx_desc_lim = {
323 .nb_max = E1000_MAX_RING_DESC,
324 .nb_min = E1000_MIN_RING_DESC,
325 .nb_align = IGB_RXD_ALIGN,
326 .nb_seg_max = IGB_TX_MAX_SEG,
327 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
330 static const struct eth_dev_ops eth_igb_ops = {
331 .dev_configure = eth_igb_configure,
332 .dev_start = eth_igb_start,
333 .dev_stop = eth_igb_stop,
334 .dev_set_link_up = eth_igb_dev_set_link_up,
335 .dev_set_link_down = eth_igb_dev_set_link_down,
336 .dev_close = eth_igb_close,
337 .dev_reset = eth_igb_reset,
338 .promiscuous_enable = eth_igb_promiscuous_enable,
339 .promiscuous_disable = eth_igb_promiscuous_disable,
340 .allmulticast_enable = eth_igb_allmulticast_enable,
341 .allmulticast_disable = eth_igb_allmulticast_disable,
342 .link_update = eth_igb_link_update,
343 .stats_get = eth_igb_stats_get,
344 .xstats_get = eth_igb_xstats_get,
345 .xstats_get_by_id = eth_igb_xstats_get_by_id,
346 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
347 .xstats_get_names = eth_igb_xstats_get_names,
348 .stats_reset = eth_igb_stats_reset,
349 .xstats_reset = eth_igb_xstats_reset,
350 .fw_version_get = eth_igb_fw_version_get,
351 .dev_infos_get = eth_igb_infos_get,
352 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
353 .mtu_set = eth_igb_mtu_set,
354 .vlan_filter_set = eth_igb_vlan_filter_set,
355 .vlan_tpid_set = eth_igb_vlan_tpid_set,
356 .vlan_offload_set = eth_igb_vlan_offload_set,
357 .rx_queue_setup = eth_igb_rx_queue_setup,
358 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
359 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
360 .rx_queue_release = eth_igb_rx_queue_release,
361 .tx_queue_setup = eth_igb_tx_queue_setup,
362 .tx_queue_release = eth_igb_tx_queue_release,
363 .tx_done_cleanup = eth_igb_tx_done_cleanup,
364 .dev_led_on = eth_igb_led_on,
365 .dev_led_off = eth_igb_led_off,
366 .flow_ctrl_get = eth_igb_flow_ctrl_get,
367 .flow_ctrl_set = eth_igb_flow_ctrl_set,
368 .mac_addr_add = eth_igb_rar_set,
369 .mac_addr_remove = eth_igb_rar_clear,
370 .mac_addr_set = eth_igb_default_mac_addr_set,
371 .reta_update = eth_igb_rss_reta_update,
372 .reta_query = eth_igb_rss_reta_query,
373 .rss_hash_update = eth_igb_rss_hash_update,
374 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
375 .flow_ops_get = eth_igb_flow_ops_get,
376 .set_mc_addr_list = eth_igb_set_mc_addr_list,
377 .rxq_info_get = igb_rxq_info_get,
378 .txq_info_get = igb_txq_info_get,
379 .timesync_enable = igb_timesync_enable,
380 .timesync_disable = igb_timesync_disable,
381 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
382 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
383 .get_reg = eth_igb_get_regs,
384 .get_eeprom_length = eth_igb_get_eeprom_length,
385 .get_eeprom = eth_igb_get_eeprom,
386 .set_eeprom = eth_igb_set_eeprom,
387 .get_module_info = eth_igb_get_module_info,
388 .get_module_eeprom = eth_igb_get_module_eeprom,
389 .timesync_adjust_time = igb_timesync_adjust_time,
390 .timesync_read_time = igb_timesync_read_time,
391 .timesync_write_time = igb_timesync_write_time,
395 * dev_ops for virtual function, bare necessities for basic vf
396 * operation have been implemented
398 static const struct eth_dev_ops igbvf_eth_dev_ops = {
399 .dev_configure = igbvf_dev_configure,
400 .dev_start = igbvf_dev_start,
401 .dev_stop = igbvf_dev_stop,
402 .dev_close = igbvf_dev_close,
403 .promiscuous_enable = igbvf_promiscuous_enable,
404 .promiscuous_disable = igbvf_promiscuous_disable,
405 .allmulticast_enable = igbvf_allmulticast_enable,
406 .allmulticast_disable = igbvf_allmulticast_disable,
407 .link_update = eth_igb_link_update,
408 .stats_get = eth_igbvf_stats_get,
409 .xstats_get = eth_igbvf_xstats_get,
410 .xstats_get_names = eth_igbvf_xstats_get_names,
411 .stats_reset = eth_igbvf_stats_reset,
412 .xstats_reset = eth_igbvf_stats_reset,
413 .vlan_filter_set = igbvf_vlan_filter_set,
414 .dev_infos_get = eth_igbvf_infos_get,
415 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
416 .rx_queue_setup = eth_igb_rx_queue_setup,
417 .rx_queue_release = eth_igb_rx_queue_release,
418 .tx_queue_setup = eth_igb_tx_queue_setup,
419 .tx_queue_release = eth_igb_tx_queue_release,
420 .tx_done_cleanup = eth_igb_tx_done_cleanup,
421 .set_mc_addr_list = eth_igb_set_mc_addr_list,
422 .rxq_info_get = igb_rxq_info_get,
423 .txq_info_get = igb_txq_info_get,
424 .mac_addr_set = igbvf_default_mac_addr_set,
425 .get_reg = igbvf_get_regs,
428 /* store statistics names and its offset in stats structure */
429 struct rte_igb_xstats_name_off {
430 char name[RTE_ETH_XSTATS_NAME_SIZE];
434 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
435 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
436 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
437 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
438 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
439 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
440 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
441 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
443 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
444 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
445 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
446 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
447 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
448 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
449 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
450 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
451 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
452 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
453 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
455 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
456 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
457 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
458 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
459 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
461 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
463 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
464 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
465 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
466 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
467 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
468 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
469 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
470 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
471 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
472 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
473 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
474 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
475 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
476 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
477 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
478 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
479 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
480 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
482 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
484 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
485 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
486 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
487 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
488 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
489 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
490 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
492 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
495 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
496 sizeof(rte_igb_stats_strings[0]))
498 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
499 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
500 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
501 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
502 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
503 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
506 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
507 sizeof(rte_igbvf_stats_strings[0]))
511 igb_intr_enable(struct rte_eth_dev *dev)
513 struct e1000_interrupt *intr =
514 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
515 struct e1000_hw *hw =
516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
517 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
518 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
520 if (rte_intr_allow_others(intr_handle) &&
521 dev->data->dev_conf.intr_conf.lsc != 0) {
522 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
525 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
526 E1000_WRITE_FLUSH(hw);
530 igb_intr_disable(struct rte_eth_dev *dev)
532 struct e1000_hw *hw =
533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
535 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
537 if (rte_intr_allow_others(intr_handle) &&
538 dev->data->dev_conf.intr_conf.lsc != 0) {
539 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
542 E1000_WRITE_REG(hw, E1000_IMC, ~0);
543 E1000_WRITE_FLUSH(hw);
547 igbvf_intr_enable(struct rte_eth_dev *dev)
549 struct e1000_hw *hw =
550 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 /* only for mailbox */
553 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
554 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
555 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
556 E1000_WRITE_FLUSH(hw);
559 /* only for mailbox now. If RX/TX needed, should extend this function. */
561 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
566 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
567 tmp |= E1000_VTIVAR_VALID;
568 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
572 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
574 struct e1000_hw *hw =
575 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
577 /* Configure VF other cause ivar */
578 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
581 static inline int32_t
582 igb_pf_reset_hw(struct e1000_hw *hw)
587 status = e1000_reset_hw(hw);
589 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
590 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
591 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
592 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
593 E1000_WRITE_FLUSH(hw);
599 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
601 struct e1000_hw *hw =
602 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 hw->vendor_id = pci_dev->id.vendor_id;
606 hw->device_id = pci_dev->id.device_id;
607 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
608 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
610 e1000_set_mac_type(hw);
612 /* need to check if it is a vf device below */
616 igb_reset_swfw_lock(struct e1000_hw *hw)
621 * Do mac ops initialization manually here, since we will need
622 * some function pointers set by this call.
624 ret_val = e1000_init_mac_params(hw);
629 * SMBI lock should not fail in this early stage. If this is the case,
630 * it is due to an improper exit of the application.
631 * So force the release of the faulty lock.
633 if (e1000_get_hw_semaphore_generic(hw) < 0) {
634 PMD_DRV_LOG(DEBUG, "SMBI lock released");
636 e1000_put_hw_semaphore_generic(hw);
638 if (hw->mac.ops.acquire_swfw_sync != NULL) {
642 * Phy lock should not fail in this early stage. If this is the case,
643 * it is due to an improper exit of the application.
644 * So force the release of the faulty lock.
646 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
647 if (hw->bus.func > E1000_FUNC_1)
649 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
650 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
653 hw->mac.ops.release_swfw_sync(hw, mask);
656 * This one is more tricky since it is common to all ports; but
657 * swfw_sync retries last long enough (1s) to be almost sure that if
658 * lock can not be taken it is due to an improper lock of the
661 mask = E1000_SWFW_EEP_SM;
662 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
663 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
665 hw->mac.ops.release_swfw_sync(hw, mask);
668 return E1000_SUCCESS;
671 /* Remove all ntuple filters of the device */
672 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
674 struct e1000_filter_info *filter_info =
675 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
676 struct e1000_5tuple_filter *p_5tuple;
677 struct e1000_2tuple_filter *p_2tuple;
679 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
680 TAILQ_REMOVE(&filter_info->fivetuple_list,
684 filter_info->fivetuple_mask = 0;
685 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
686 TAILQ_REMOVE(&filter_info->twotuple_list,
690 filter_info->twotuple_mask = 0;
695 /* Remove all flex filters of the device */
696 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
698 struct e1000_filter_info *filter_info =
699 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
700 struct e1000_flex_filter *p_flex;
702 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
703 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
706 filter_info->flex_mask = 0;
712 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
716 struct e1000_hw *hw =
717 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
718 struct e1000_vfta * shadow_vfta =
719 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
720 struct e1000_filter_info *filter_info =
721 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
722 struct e1000_adapter *adapter =
723 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
727 eth_dev->dev_ops = ð_igb_ops;
728 eth_dev->rx_queue_count = eth_igb_rx_queue_count;
729 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
730 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
731 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
732 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
733 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
734 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
736 /* for secondary processes, we don't initialise any further as primary
737 * has already done this work. Only check we don't need a different
739 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
740 if (eth_dev->data->scattered_rx)
741 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
745 rte_eth_copy_pci_info(eth_dev, pci_dev);
746 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
748 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
750 igb_identify_hardware(eth_dev, pci_dev);
751 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
756 e1000_get_bus_info(hw);
758 /* Reset any pending lock */
759 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
764 /* Finish initialization */
765 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
771 hw->phy.autoneg_wait_to_complete = 0;
772 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
775 if (hw->phy.media_type == e1000_media_type_copper) {
776 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
777 hw->phy.disable_polarity_correction = 0;
778 hw->phy.ms_type = e1000_ms_hw_default;
782 * Start from a known state, this is important in reading the nvm
787 /* Make sure we have a good EEPROM before we read from it */
788 if (e1000_validate_nvm_checksum(hw) < 0) {
790 * Some PCI-E parts fail the first check due to
791 * the link being in sleep state, call it again,
792 * if it fails a second time its a real issue.
794 if (e1000_validate_nvm_checksum(hw) < 0) {
795 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
801 /* Read the permanent MAC address out of the EEPROM */
802 if (e1000_read_mac_addr(hw) != 0) {
803 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
808 /* Allocate memory for storing MAC addresses */
809 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
810 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
811 if (eth_dev->data->mac_addrs == NULL) {
812 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
813 "store MAC addresses",
814 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
819 /* Copy the permanent MAC address */
820 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
821 ð_dev->data->mac_addrs[0]);
823 /* initialize the vfta */
824 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
826 /* Now initialize the hardware */
827 if (igb_hardware_init(hw) != 0) {
828 PMD_INIT_LOG(ERR, "Hardware initialization failed");
829 rte_free(eth_dev->data->mac_addrs);
830 eth_dev->data->mac_addrs = NULL;
834 hw->mac.get_link_status = 1;
835 adapter->stopped = 0;
837 /* Indicate SOL/IDER usage */
838 if (e1000_check_reset_block(hw) < 0) {
839 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
843 /* initialize PF if max_vfs not zero */
844 igb_pf_host_init(eth_dev);
846 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
847 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
848 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
849 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
850 E1000_WRITE_FLUSH(hw);
852 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
853 eth_dev->data->port_id, pci_dev->id.vendor_id,
854 pci_dev->id.device_id);
856 rte_intr_callback_register(&pci_dev->intr_handle,
857 eth_igb_interrupt_handler,
860 /* enable uio/vfio intr/eventfd mapping */
861 rte_intr_enable(&pci_dev->intr_handle);
863 /* enable support intr */
864 igb_intr_enable(eth_dev);
866 eth_igb_dev_set_link_down(eth_dev);
868 /* initialize filter info */
869 memset(filter_info, 0,
870 sizeof(struct e1000_filter_info));
872 TAILQ_INIT(&filter_info->flex_list);
873 TAILQ_INIT(&filter_info->twotuple_list);
874 TAILQ_INIT(&filter_info->fivetuple_list);
876 TAILQ_INIT(&igb_filter_ntuple_list);
877 TAILQ_INIT(&igb_filter_ethertype_list);
878 TAILQ_INIT(&igb_filter_syn_list);
879 TAILQ_INIT(&igb_filter_flex_list);
880 TAILQ_INIT(&igb_filter_rss_list);
881 TAILQ_INIT(&igb_flow_list);
886 igb_hw_control_release(hw);
892 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
894 PMD_INIT_FUNC_TRACE();
896 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
899 eth_igb_close(eth_dev);
905 * Virtual Function device init
908 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
910 struct rte_pci_device *pci_dev;
911 struct rte_intr_handle *intr_handle;
912 struct e1000_adapter *adapter =
913 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
914 struct e1000_hw *hw =
915 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
917 struct rte_ether_addr *perm_addr =
918 (struct rte_ether_addr *)hw->mac.perm_addr;
920 PMD_INIT_FUNC_TRACE();
922 eth_dev->dev_ops = &igbvf_eth_dev_ops;
923 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
924 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
925 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
926 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
927 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
928 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
930 /* for secondary processes, we don't initialise any further as primary
931 * has already done this work. Only check we don't need a different
933 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
934 if (eth_dev->data->scattered_rx)
935 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
939 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
940 rte_eth_copy_pci_info(eth_dev, pci_dev);
941 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
943 hw->device_id = pci_dev->id.device_id;
944 hw->vendor_id = pci_dev->id.vendor_id;
945 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
946 adapter->stopped = 0;
948 /* Initialize the shared code (base driver) */
949 diag = e1000_setup_init_funcs(hw, TRUE);
951 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
956 /* init_mailbox_params */
957 hw->mbx.ops.init_params(hw);
959 /* Disable the interrupts for VF */
960 igbvf_intr_disable(hw);
962 diag = hw->mac.ops.reset_hw(hw);
964 /* Allocate memory for storing MAC addresses */
965 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
966 hw->mac.rar_entry_count, 0);
967 if (eth_dev->data->mac_addrs == NULL) {
969 "Failed to allocate %d bytes needed to store MAC "
971 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
975 /* Generate a random MAC address, if none was assigned by PF. */
976 if (rte_is_zero_ether_addr(perm_addr)) {
977 rte_eth_random_addr(perm_addr->addr_bytes);
978 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
979 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
980 RTE_ETHER_ADDR_PRT_FMT,
981 RTE_ETHER_ADDR_BYTES(perm_addr));
984 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
986 rte_free(eth_dev->data->mac_addrs);
987 eth_dev->data->mac_addrs = NULL;
990 /* Copy the permanent MAC address */
991 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
992 ð_dev->data->mac_addrs[0]);
994 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
996 eth_dev->data->port_id, pci_dev->id.vendor_id,
997 pci_dev->id.device_id, "igb_mac_82576_vf");
999 intr_handle = &pci_dev->intr_handle;
1000 rte_intr_callback_register(intr_handle,
1001 eth_igbvf_interrupt_handler, eth_dev);
1007 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1009 PMD_INIT_FUNC_TRACE();
1011 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1014 igbvf_dev_close(eth_dev);
1019 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1020 struct rte_pci_device *pci_dev)
1022 return rte_eth_dev_pci_generic_probe(pci_dev,
1023 sizeof(struct e1000_adapter), eth_igb_dev_init);
1026 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1028 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1031 static struct rte_pci_driver rte_igb_pmd = {
1032 .id_table = pci_id_igb_map,
1033 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1034 .probe = eth_igb_pci_probe,
1035 .remove = eth_igb_pci_remove,
1039 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1040 struct rte_pci_device *pci_dev)
1042 return rte_eth_dev_pci_generic_probe(pci_dev,
1043 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1046 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1048 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1052 * virtual function driver struct
1054 static struct rte_pci_driver rte_igbvf_pmd = {
1055 .id_table = pci_id_igbvf_map,
1056 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1057 .probe = eth_igbvf_pci_probe,
1058 .remove = eth_igbvf_pci_remove,
1062 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1064 struct e1000_hw *hw =
1065 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1066 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1067 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1068 rctl |= E1000_RCTL_VFE;
1069 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1073 igb_check_mq_mode(struct rte_eth_dev *dev)
1075 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1076 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1077 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1078 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1080 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1081 tx_mq_mode == ETH_MQ_TX_DCB ||
1082 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1083 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1086 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1087 /* Check multi-queue mode.
1088 * To no break software we accept ETH_MQ_RX_NONE as this might
1089 * be used to turn off VLAN filter.
1092 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1093 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1094 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1095 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1097 /* Only support one queue on VFs.
1098 * RSS together with SRIOV is not supported.
1100 PMD_INIT_LOG(ERR, "SRIOV is active,"
1101 " wrong mq_mode rx %d.",
1105 /* TX mode is not used here, so mode might be ignored.*/
1106 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1107 /* SRIOV only works in VMDq enable mode */
1108 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1109 " TX mode %d is not supported. "
1110 " Driver will behave as %d mode.",
1111 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1114 /* check valid queue number */
1115 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1116 PMD_INIT_LOG(ERR, "SRIOV is active,"
1117 " only support one queue on VFs.");
1121 /* To no break software that set invalid mode, only display
1122 * warning if invalid mode is used.
1124 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1125 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1126 rx_mq_mode != ETH_MQ_RX_RSS) {
1127 /* RSS together with VMDq not supported*/
1128 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1133 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1134 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1135 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1136 " Due to txmode is meaningless in this"
1137 " driver, just ignore.",
1145 eth_igb_configure(struct rte_eth_dev *dev)
1147 struct e1000_interrupt *intr =
1148 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1151 PMD_INIT_FUNC_TRACE();
1153 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1154 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1156 /* multipe queue mode checking */
1157 ret = igb_check_mq_mode(dev);
1159 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1164 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1165 PMD_INIT_FUNC_TRACE();
1171 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1174 struct e1000_hw *hw =
1175 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1176 uint32_t tctl, rctl;
1178 tctl = E1000_READ_REG(hw, E1000_TCTL);
1179 rctl = E1000_READ_REG(hw, E1000_RCTL);
1183 tctl |= E1000_TCTL_EN;
1184 rctl |= E1000_RCTL_EN;
1187 tctl &= ~E1000_TCTL_EN;
1188 rctl &= ~E1000_RCTL_EN;
1190 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1191 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1192 E1000_WRITE_FLUSH(hw);
1196 eth_igb_start(struct rte_eth_dev *dev)
1198 struct e1000_hw *hw =
1199 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200 struct e1000_adapter *adapter =
1201 E1000_DEV_PRIVATE(dev->data->dev_private);
1202 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1203 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1205 uint32_t intr_vector = 0;
1211 PMD_INIT_FUNC_TRACE();
1213 /* disable uio/vfio intr/eventfd mapping */
1214 rte_intr_disable(intr_handle);
1216 /* Power up the phy. Needed to make the link go Up */
1217 eth_igb_dev_set_link_up(dev);
1220 * Packet Buffer Allocation (PBA)
1221 * Writing PBA sets the receive portion of the buffer
1222 * the remainder is used for the transmit buffer.
1224 if (hw->mac.type == e1000_82575) {
1227 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1228 E1000_WRITE_REG(hw, E1000_PBA, pba);
1231 /* Put the address into the Receive Address Array */
1232 e1000_rar_set(hw, hw->mac.addr, 0);
1234 /* Initialize the hardware */
1235 if (igb_hardware_init(hw)) {
1236 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1239 adapter->stopped = 0;
1241 E1000_WRITE_REG(hw, E1000_VET,
1242 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1244 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1245 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1246 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1247 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1248 E1000_WRITE_FLUSH(hw);
1250 /* configure PF module if SRIOV enabled */
1251 igb_pf_host_configure(dev);
1253 /* check and configure queue intr-vector mapping */
1254 if ((rte_intr_cap_multiple(intr_handle) ||
1255 !RTE_ETH_DEV_SRIOV(dev).active) &&
1256 dev->data->dev_conf.intr_conf.rxq != 0) {
1257 intr_vector = dev->data->nb_rx_queues;
1258 if (rte_intr_efd_enable(intr_handle, intr_vector))
1262 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1263 intr_handle->intr_vec =
1264 rte_zmalloc("intr_vec",
1265 dev->data->nb_rx_queues * sizeof(int), 0);
1266 if (intr_handle->intr_vec == NULL) {
1267 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1268 " intr_vec", dev->data->nb_rx_queues);
1273 /* confiugre msix for rx interrupt */
1274 eth_igb_configure_msix_intr(dev);
1276 /* Configure for OS presence */
1277 igb_init_manageability(hw);
1279 eth_igb_tx_init(dev);
1281 /* This can fail when allocating mbufs for descriptor rings */
1282 ret = eth_igb_rx_init(dev);
1284 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1285 igb_dev_clear_queues(dev);
1289 e1000_clear_hw_cntrs_base_generic(hw);
1292 * VLAN Offload Settings
1294 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1295 ETH_VLAN_EXTEND_MASK;
1296 ret = eth_igb_vlan_offload_set(dev, mask);
1298 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1299 igb_dev_clear_queues(dev);
1303 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1304 /* Enable VLAN filter since VMDq always use VLAN filter */
1305 igb_vmdq_vlan_hw_filter_enable(dev);
1308 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1309 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1310 (hw->mac.type == e1000_i211)) {
1311 /* Configure EITR with the maximum possible value (0xFFFF) */
1312 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1315 /* Setup link speed and duplex */
1316 speeds = &dev->data->dev_conf.link_speeds;
1317 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1318 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1319 hw->mac.autoneg = 1;
1322 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1325 hw->phy.autoneg_advertised = 0;
1327 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1328 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1329 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1331 goto error_invalid_config;
1333 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1334 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1337 if (*speeds & ETH_LINK_SPEED_10M) {
1338 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1341 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1342 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1345 if (*speeds & ETH_LINK_SPEED_100M) {
1346 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1349 if (*speeds & ETH_LINK_SPEED_1G) {
1350 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1353 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1354 goto error_invalid_config;
1356 /* Set/reset the mac.autoneg based on the link speed,
1360 hw->mac.autoneg = 0;
1361 hw->mac.forced_speed_duplex =
1362 hw->phy.autoneg_advertised;
1364 hw->mac.autoneg = 1;
1368 e1000_setup_link(hw);
1370 if (rte_intr_allow_others(intr_handle)) {
1371 /* check if lsc interrupt is enabled */
1372 if (dev->data->dev_conf.intr_conf.lsc != 0)
1373 eth_igb_lsc_interrupt_setup(dev, TRUE);
1375 eth_igb_lsc_interrupt_setup(dev, FALSE);
1377 rte_intr_callback_unregister(intr_handle,
1378 eth_igb_interrupt_handler,
1380 if (dev->data->dev_conf.intr_conf.lsc != 0)
1381 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1382 " no intr multiplex");
1385 /* check if rxq interrupt is enabled */
1386 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1387 rte_intr_dp_is_en(intr_handle))
1388 eth_igb_rxq_interrupt_setup(dev);
1390 /* enable uio/vfio intr/eventfd mapping */
1391 rte_intr_enable(intr_handle);
1393 /* resume enabled intr since hw reset */
1394 igb_intr_enable(dev);
1396 /* restore all types filter */
1397 igb_filter_restore(dev);
1399 eth_igb_rxtx_control(dev, true);
1400 eth_igb_link_update(dev, 0);
1402 PMD_INIT_LOG(DEBUG, "<<");
1406 error_invalid_config:
1407 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1408 dev->data->dev_conf.link_speeds, dev->data->port_id);
1409 igb_dev_clear_queues(dev);
1413 /*********************************************************************
1415 * This routine disables all traffic on the adapter by issuing a
1416 * global reset on the MAC.
1418 **********************************************************************/
1420 eth_igb_stop(struct rte_eth_dev *dev)
1422 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1423 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1424 struct rte_eth_link link;
1425 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1426 struct e1000_adapter *adapter =
1427 E1000_DEV_PRIVATE(dev->data->dev_private);
1429 if (adapter->stopped)
1432 eth_igb_rxtx_control(dev, false);
1434 igb_intr_disable(dev);
1436 /* disable intr eventfd mapping */
1437 rte_intr_disable(intr_handle);
1439 igb_pf_reset_hw(hw);
1440 E1000_WRITE_REG(hw, E1000_WUC, 0);
1442 /* Set bit for Go Link disconnect if PHY reset is not blocked */
1443 if (hw->mac.type >= e1000_82580 &&
1444 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1447 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1448 phpm_reg |= E1000_82580_PM_GO_LINKD;
1449 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1452 /* Power down the phy. Needed to make the link go Down */
1453 eth_igb_dev_set_link_down(dev);
1455 igb_dev_clear_queues(dev);
1457 /* clear the recorded link status */
1458 memset(&link, 0, sizeof(link));
1459 rte_eth_linkstatus_set(dev, &link);
1461 if (!rte_intr_allow_others(intr_handle))
1462 /* resume to the default handler */
1463 rte_intr_callback_register(intr_handle,
1464 eth_igb_interrupt_handler,
1467 /* Clean datapath event and queue/vec mapping */
1468 rte_intr_efd_disable(intr_handle);
1469 if (intr_handle->intr_vec != NULL) {
1470 rte_free(intr_handle->intr_vec);
1471 intr_handle->intr_vec = NULL;
1474 adapter->stopped = true;
1475 dev->data->dev_started = 0;
1481 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1483 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485 if (hw->phy.media_type == e1000_media_type_copper)
1486 e1000_power_up_phy(hw);
1488 e1000_power_up_fiber_serdes_link(hw);
1494 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1496 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1498 if (hw->phy.media_type == e1000_media_type_copper)
1499 e1000_power_down_phy(hw);
1501 e1000_shutdown_fiber_serdes_link(hw);
1507 eth_igb_close(struct rte_eth_dev *dev)
1509 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510 struct rte_eth_link link;
1511 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1512 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1513 struct e1000_filter_info *filter_info =
1514 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1517 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1520 ret = eth_igb_stop(dev);
1522 e1000_phy_hw_reset(hw);
1523 igb_release_manageability(hw);
1524 igb_hw_control_release(hw);
1526 /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1527 if (hw->mac.type >= e1000_82580 &&
1528 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1531 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1532 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1533 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1536 igb_dev_free_queues(dev);
1538 if (intr_handle->intr_vec) {
1539 rte_free(intr_handle->intr_vec);
1540 intr_handle->intr_vec = NULL;
1543 memset(&link, 0, sizeof(link));
1544 rte_eth_linkstatus_set(dev, &link);
1546 /* Reset any pending lock */
1547 igb_reset_swfw_lock(hw);
1549 /* uninitialize PF if max_vfs not zero */
1550 igb_pf_host_uninit(dev);
1552 rte_intr_callback_unregister(intr_handle,
1553 eth_igb_interrupt_handler, dev);
1555 /* clear the SYN filter info */
1556 filter_info->syn_info = 0;
1558 /* clear the ethertype filters info */
1559 filter_info->ethertype_mask = 0;
1560 memset(filter_info->ethertype_filters, 0,
1561 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1563 /* clear the rss filter info */
1564 memset(&filter_info->rss_info, 0,
1565 sizeof(struct igb_rte_flow_rss_conf));
1567 /* remove all ntuple filters of the device */
1568 igb_ntuple_filter_uninit(dev);
1570 /* remove all flex filters of the device */
1571 igb_flex_filter_uninit(dev);
1573 /* clear all the filters list */
1574 igb_filterlist_flush(dev);
1583 eth_igb_reset(struct rte_eth_dev *dev)
1587 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1588 * its VF to make them align with it. The detailed notification
1589 * mechanism is PMD specific and is currently not implemented.
1590 * To avoid unexpected behavior in VF, currently reset of PF with
1591 * SR-IOV activation is not supported. It might be supported later.
1593 if (dev->data->sriov.active)
1596 ret = eth_igb_dev_uninit(dev);
1600 ret = eth_igb_dev_init(dev);
1607 igb_get_rx_buffer_size(struct e1000_hw *hw)
1609 uint32_t rx_buf_size;
1610 if (hw->mac.type == e1000_82576) {
1611 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1612 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1613 /* PBS needs to be translated according to a lookup table */
1614 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1615 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1616 rx_buf_size = (rx_buf_size << 10);
1617 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1618 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1620 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1626 /*********************************************************************
1628 * Initialize the hardware
1630 **********************************************************************/
1632 igb_hardware_init(struct e1000_hw *hw)
1634 uint32_t rx_buf_size;
1637 /* Let the firmware know the OS is in control */
1638 igb_hw_control_acquire(hw);
1641 * These parameters control the automatic generation (Tx) and
1642 * response (Rx) to Ethernet PAUSE frames.
1643 * - High water mark should allow for at least two standard size (1518)
1644 * frames to be received after sending an XOFF.
1645 * - Low water mark works best when it is very near the high water mark.
1646 * This allows the receiver to restart by sending XON when it has
1647 * drained a bit. Here we use an arbitrary value of 1500 which will
1648 * restart after one full frame is pulled from the buffer. There
1649 * could be several smaller frames in the buffer and if so they will
1650 * not trigger the XON until their total number reduces the buffer
1652 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1654 rx_buf_size = igb_get_rx_buffer_size(hw);
1656 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1657 hw->fc.low_water = hw->fc.high_water - 1500;
1658 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1659 hw->fc.send_xon = 1;
1661 /* Set Flow control, use the tunable location if sane */
1662 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1663 hw->fc.requested_mode = igb_fc_setting;
1665 hw->fc.requested_mode = e1000_fc_none;
1667 /* Issue a global reset */
1668 igb_pf_reset_hw(hw);
1669 E1000_WRITE_REG(hw, E1000_WUC, 0);
1671 diag = e1000_init_hw(hw);
1675 E1000_WRITE_REG(hw, E1000_VET,
1676 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1677 e1000_get_phy_info(hw);
1678 e1000_check_for_link(hw);
1683 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1685 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1689 uint64_t old_gprc = stats->gprc;
1690 uint64_t old_gptc = stats->gptc;
1691 uint64_t old_tpr = stats->tpr;
1692 uint64_t old_tpt = stats->tpt;
1693 uint64_t old_rpthc = stats->rpthc;
1694 uint64_t old_hgptc = stats->hgptc;
1696 if(hw->phy.media_type == e1000_media_type_copper ||
1697 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1699 E1000_READ_REG(hw,E1000_SYMERRS);
1700 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1703 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1704 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1705 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1706 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1708 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1709 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1710 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1711 stats->dc += E1000_READ_REG(hw, E1000_DC);
1712 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1713 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1714 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1716 ** For watchdog management we need to know if we have been
1717 ** paused during the last interval, so capture that here.
1719 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1720 stats->xoffrxc += pause_frames;
1721 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1722 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1723 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1724 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1725 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1726 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1727 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1728 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1729 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1730 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1731 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1732 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1734 /* For the 64-bit byte counters the low dword must be read first. */
1735 /* Both registers clear on the read of the high dword */
1737 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1738 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1739 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1740 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1741 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1742 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1743 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1745 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1746 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1747 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1748 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1749 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1751 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1752 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1754 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1755 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1756 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1757 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1758 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1759 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1761 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1762 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1763 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1764 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1765 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1766 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1767 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1768 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1770 /* Interrupt Counts */
1772 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1773 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1774 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1775 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1776 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1777 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1778 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1779 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1780 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1782 /* Host to Card Statistics */
1784 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1785 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1786 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1787 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1788 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1789 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1790 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1791 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1792 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1793 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1794 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1795 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1796 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1797 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1798 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1799 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1801 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1802 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1803 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1804 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1805 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1806 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1810 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1812 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1813 struct e1000_hw_stats *stats =
1814 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1816 igb_read_stats_registers(hw, stats);
1818 if (rte_stats == NULL)
1822 rte_stats->imissed = stats->mpc;
1823 rte_stats->ierrors = stats->crcerrs + stats->rlec +
1824 stats->rxerrc + stats->algnerrc + stats->cexterr;
1827 rte_stats->oerrors = stats->ecol + stats->latecol;
1829 rte_stats->ipackets = stats->gprc;
1830 rte_stats->opackets = stats->gptc;
1831 rte_stats->ibytes = stats->gorc;
1832 rte_stats->obytes = stats->gotc;
1837 eth_igb_stats_reset(struct rte_eth_dev *dev)
1839 struct e1000_hw_stats *hw_stats =
1840 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1842 /* HW registers are cleared on read */
1843 eth_igb_stats_get(dev, NULL);
1845 /* Reset software totals */
1846 memset(hw_stats, 0, sizeof(*hw_stats));
1852 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1854 struct e1000_hw_stats *stats =
1855 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1857 /* HW registers are cleared on read */
1858 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1860 /* Reset software totals */
1861 memset(stats, 0, sizeof(*stats));
1866 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1867 struct rte_eth_xstat_name *xstats_names,
1868 __rte_unused unsigned int size)
1872 if (xstats_names == NULL)
1873 return IGB_NB_XSTATS;
1875 /* Note: limit checked in rte_eth_xstats_names() */
1877 for (i = 0; i < IGB_NB_XSTATS; i++) {
1878 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1879 sizeof(xstats_names[i].name));
1882 return IGB_NB_XSTATS;
1885 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1886 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1892 if (xstats_names == NULL)
1893 return IGB_NB_XSTATS;
1895 for (i = 0; i < IGB_NB_XSTATS; i++)
1896 strlcpy(xstats_names[i].name,
1897 rte_igb_stats_strings[i].name,
1898 sizeof(xstats_names[i].name));
1900 return IGB_NB_XSTATS;
1903 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1905 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1908 for (i = 0; i < limit; i++) {
1909 if (ids[i] >= IGB_NB_XSTATS) {
1910 PMD_INIT_LOG(ERR, "id value isn't valid");
1913 strcpy(xstats_names[i].name,
1914 xstats_names_copy[ids[i]].name);
1921 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1924 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925 struct e1000_hw_stats *hw_stats =
1926 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1929 if (n < IGB_NB_XSTATS)
1930 return IGB_NB_XSTATS;
1932 igb_read_stats_registers(hw, hw_stats);
1934 /* If this is a reset xstats is NULL, and we have cleared the
1935 * registers by reading them.
1940 /* Extended stats */
1941 for (i = 0; i < IGB_NB_XSTATS; i++) {
1943 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1944 rte_igb_stats_strings[i].offset);
1947 return IGB_NB_XSTATS;
1951 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1952 uint64_t *values, unsigned int n)
1957 struct e1000_hw *hw =
1958 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959 struct e1000_hw_stats *hw_stats =
1960 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1962 if (n < IGB_NB_XSTATS)
1963 return IGB_NB_XSTATS;
1965 igb_read_stats_registers(hw, hw_stats);
1967 /* If this is a reset xstats is NULL, and we have cleared the
1968 * registers by reading them.
1973 /* Extended stats */
1974 for (i = 0; i < IGB_NB_XSTATS; i++)
1975 values[i] = *(uint64_t *)(((char *)hw_stats) +
1976 rte_igb_stats_strings[i].offset);
1978 return IGB_NB_XSTATS;
1981 uint64_t values_copy[IGB_NB_XSTATS];
1983 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1986 for (i = 0; i < n; i++) {
1987 if (ids[i] >= IGB_NB_XSTATS) {
1988 PMD_INIT_LOG(ERR, "id value isn't valid");
1991 values[i] = values_copy[ids[i]];
1998 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2000 /* Good Rx packets, include VF loopback */
2001 UPDATE_VF_STAT(E1000_VFGPRC,
2002 hw_stats->last_gprc, hw_stats->gprc);
2004 /* Good Rx octets, include VF loopback */
2005 UPDATE_VF_STAT(E1000_VFGORC,
2006 hw_stats->last_gorc, hw_stats->gorc);
2008 /* Good Tx packets, include VF loopback */
2009 UPDATE_VF_STAT(E1000_VFGPTC,
2010 hw_stats->last_gptc, hw_stats->gptc);
2012 /* Good Tx octets, include VF loopback */
2013 UPDATE_VF_STAT(E1000_VFGOTC,
2014 hw_stats->last_gotc, hw_stats->gotc);
2016 /* Rx Multicst packets */
2017 UPDATE_VF_STAT(E1000_VFMPRC,
2018 hw_stats->last_mprc, hw_stats->mprc);
2020 /* Good Rx loopback packets */
2021 UPDATE_VF_STAT(E1000_VFGPRLBC,
2022 hw_stats->last_gprlbc, hw_stats->gprlbc);
2024 /* Good Rx loopback octets */
2025 UPDATE_VF_STAT(E1000_VFGORLBC,
2026 hw_stats->last_gorlbc, hw_stats->gorlbc);
2028 /* Good Tx loopback packets */
2029 UPDATE_VF_STAT(E1000_VFGPTLBC,
2030 hw_stats->last_gptlbc, hw_stats->gptlbc);
2032 /* Good Tx loopback octets */
2033 UPDATE_VF_STAT(E1000_VFGOTLBC,
2034 hw_stats->last_gotlbc, hw_stats->gotlbc);
2037 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2038 struct rte_eth_xstat_name *xstats_names,
2039 __rte_unused unsigned limit)
2043 if (xstats_names != NULL)
2044 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2045 strlcpy(xstats_names[i].name,
2046 rte_igbvf_stats_strings[i].name,
2047 sizeof(xstats_names[i].name));
2049 return IGBVF_NB_XSTATS;
2053 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2056 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2058 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2061 if (n < IGBVF_NB_XSTATS)
2062 return IGBVF_NB_XSTATS;
2064 igbvf_read_stats_registers(hw, hw_stats);
2069 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2071 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2072 rte_igbvf_stats_strings[i].offset);
2075 return IGBVF_NB_XSTATS;
2079 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2081 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2083 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2085 igbvf_read_stats_registers(hw, hw_stats);
2087 if (rte_stats == NULL)
2090 rte_stats->ipackets = hw_stats->gprc;
2091 rte_stats->ibytes = hw_stats->gorc;
2092 rte_stats->opackets = hw_stats->gptc;
2093 rte_stats->obytes = hw_stats->gotc;
2098 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2100 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2101 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2103 /* Sync HW register to the last stats */
2104 eth_igbvf_stats_get(dev, NULL);
2106 /* reset HW current stats*/
2107 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2108 offsetof(struct e1000_vf_stats, gprc));
2114 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2117 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2118 struct e1000_fw_version fw;
2121 e1000_get_fw_version(hw, &fw);
2123 switch (hw->mac.type) {
2126 if (!(e1000_get_flash_presence_i210(hw))) {
2127 ret = snprintf(fw_version, fw_size,
2129 fw.invm_major, fw.invm_minor,
2135 /* if option rom is valid, display its version too */
2137 ret = snprintf(fw_version, fw_size,
2138 "%d.%d, 0x%08x, %d.%d.%d",
2139 fw.eep_major, fw.eep_minor, fw.etrack_id,
2140 fw.or_major, fw.or_build, fw.or_patch);
2143 if (fw.etrack_id != 0X0000) {
2144 ret = snprintf(fw_version, fw_size,
2146 fw.eep_major, fw.eep_minor,
2149 ret = snprintf(fw_version, fw_size,
2151 fw.eep_major, fw.eep_minor,
2160 ret += 1; /* add the size of '\0' */
2161 if (fw_size < (size_t)ret)
2168 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2170 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2172 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2173 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2174 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2175 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2176 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2177 dev_info->rx_queue_offload_capa;
2178 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2179 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2180 dev_info->tx_queue_offload_capa;
2182 switch (hw->mac.type) {
2184 dev_info->max_rx_queues = 4;
2185 dev_info->max_tx_queues = 4;
2186 dev_info->max_vmdq_pools = 0;
2190 dev_info->max_rx_queues = 16;
2191 dev_info->max_tx_queues = 16;
2192 dev_info->max_vmdq_pools = ETH_8_POOLS;
2193 dev_info->vmdq_queue_num = 16;
2197 dev_info->max_rx_queues = 8;
2198 dev_info->max_tx_queues = 8;
2199 dev_info->max_vmdq_pools = ETH_8_POOLS;
2200 dev_info->vmdq_queue_num = 8;
2204 dev_info->max_rx_queues = 8;
2205 dev_info->max_tx_queues = 8;
2206 dev_info->max_vmdq_pools = ETH_8_POOLS;
2207 dev_info->vmdq_queue_num = 8;
2211 dev_info->max_rx_queues = 8;
2212 dev_info->max_tx_queues = 8;
2216 dev_info->max_rx_queues = 4;
2217 dev_info->max_tx_queues = 4;
2218 dev_info->max_vmdq_pools = 0;
2222 dev_info->max_rx_queues = 2;
2223 dev_info->max_tx_queues = 2;
2224 dev_info->max_vmdq_pools = 0;
2228 /* Should not happen */
2231 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2232 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2233 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2235 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2237 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2238 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2239 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2241 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2246 dev_info->default_txconf = (struct rte_eth_txconf) {
2248 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2249 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2250 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2255 dev_info->rx_desc_lim = rx_desc_lim;
2256 dev_info->tx_desc_lim = tx_desc_lim;
2258 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2259 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2262 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2263 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2268 static const uint32_t *
2269 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2271 static const uint32_t ptypes[] = {
2272 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2275 RTE_PTYPE_L3_IPV4_EXT,
2277 RTE_PTYPE_L3_IPV6_EXT,
2281 RTE_PTYPE_TUNNEL_IP,
2282 RTE_PTYPE_INNER_L3_IPV6,
2283 RTE_PTYPE_INNER_L3_IPV6_EXT,
2284 RTE_PTYPE_INNER_L4_TCP,
2285 RTE_PTYPE_INNER_L4_UDP,
2289 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2290 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2296 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2298 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2301 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2302 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2303 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2304 DEV_TX_OFFLOAD_IPV4_CKSUM |
2305 DEV_TX_OFFLOAD_UDP_CKSUM |
2306 DEV_TX_OFFLOAD_TCP_CKSUM |
2307 DEV_TX_OFFLOAD_SCTP_CKSUM |
2308 DEV_TX_OFFLOAD_TCP_TSO;
2309 switch (hw->mac.type) {
2311 dev_info->max_rx_queues = 2;
2312 dev_info->max_tx_queues = 2;
2314 case e1000_vfadapt_i350:
2315 dev_info->max_rx_queues = 1;
2316 dev_info->max_tx_queues = 1;
2319 /* Should not happen */
2323 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2324 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2325 dev_info->rx_queue_offload_capa;
2326 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2327 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2328 dev_info->tx_queue_offload_capa;
2330 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2332 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2333 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2334 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2336 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2341 dev_info->default_txconf = (struct rte_eth_txconf) {
2343 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2344 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2345 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2350 dev_info->rx_desc_lim = rx_desc_lim;
2351 dev_info->tx_desc_lim = tx_desc_lim;
2356 /* return 0 means link status changed, -1 means not changed */
2358 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2360 struct e1000_hw *hw =
2361 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2362 struct rte_eth_link link;
2363 int link_check, count;
2366 hw->mac.get_link_status = 1;
2368 /* possible wait-to-complete in up to 9 seconds */
2369 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2370 /* Read the real link status */
2371 switch (hw->phy.media_type) {
2372 case e1000_media_type_copper:
2373 /* Do the work to read phy */
2374 e1000_check_for_link(hw);
2375 link_check = !hw->mac.get_link_status;
2378 case e1000_media_type_fiber:
2379 e1000_check_for_link(hw);
2380 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2384 case e1000_media_type_internal_serdes:
2385 e1000_check_for_link(hw);
2386 link_check = hw->mac.serdes_has_link;
2389 /* VF device is type_unknown */
2390 case e1000_media_type_unknown:
2391 eth_igbvf_link_update(hw);
2392 link_check = !hw->mac.get_link_status;
2398 if (link_check || wait_to_complete == 0)
2400 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2402 memset(&link, 0, sizeof(link));
2404 /* Now we check if a transition has happened */
2406 uint16_t duplex, speed;
2407 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2408 link.link_duplex = (duplex == FULL_DUPLEX) ?
2409 ETH_LINK_FULL_DUPLEX :
2410 ETH_LINK_HALF_DUPLEX;
2411 link.link_speed = speed;
2412 link.link_status = ETH_LINK_UP;
2413 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2414 ETH_LINK_SPEED_FIXED);
2415 } else if (!link_check) {
2416 link.link_speed = 0;
2417 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2418 link.link_status = ETH_LINK_DOWN;
2419 link.link_autoneg = ETH_LINK_FIXED;
2422 return rte_eth_linkstatus_set(dev, &link);
2426 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2427 * For ASF and Pass Through versions of f/w this means
2428 * that the driver is loaded.
2431 igb_hw_control_acquire(struct e1000_hw *hw)
2435 /* Let firmware know the driver has taken over */
2436 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2437 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2441 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2442 * For ASF and Pass Through versions of f/w this means that the
2443 * driver is no longer loaded.
2446 igb_hw_control_release(struct e1000_hw *hw)
2450 /* Let firmware taken over control of h/w */
2451 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2452 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2453 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2457 * Bit of a misnomer, what this really means is
2458 * to enable OS management of the system... aka
2459 * to disable special hardware management features.
2462 igb_init_manageability(struct e1000_hw *hw)
2464 if (e1000_enable_mng_pass_thru(hw)) {
2465 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2466 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2468 /* disable hardware interception of ARP */
2469 manc &= ~(E1000_MANC_ARP_EN);
2471 /* enable receiving management packets to the host */
2472 manc |= E1000_MANC_EN_MNG2HOST;
2473 manc2h |= 1 << 5; /* Mng Port 623 */
2474 manc2h |= 1 << 6; /* Mng Port 664 */
2475 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2476 E1000_WRITE_REG(hw, E1000_MANC, manc);
2481 igb_release_manageability(struct e1000_hw *hw)
2483 if (e1000_enable_mng_pass_thru(hw)) {
2484 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2486 manc |= E1000_MANC_ARP_EN;
2487 manc &= ~E1000_MANC_EN_MNG2HOST;
2489 E1000_WRITE_REG(hw, E1000_MANC, manc);
2494 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2496 struct e1000_hw *hw =
2497 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2500 rctl = E1000_READ_REG(hw, E1000_RCTL);
2501 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2502 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2508 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2510 struct e1000_hw *hw =
2511 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2514 rctl = E1000_READ_REG(hw, E1000_RCTL);
2515 rctl &= (~E1000_RCTL_UPE);
2516 if (dev->data->all_multicast == 1)
2517 rctl |= E1000_RCTL_MPE;
2519 rctl &= (~E1000_RCTL_MPE);
2520 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2526 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2528 struct e1000_hw *hw =
2529 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2532 rctl = E1000_READ_REG(hw, E1000_RCTL);
2533 rctl |= E1000_RCTL_MPE;
2534 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2540 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2542 struct e1000_hw *hw =
2543 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2546 if (dev->data->promiscuous == 1)
2547 return 0; /* must remain in all_multicast mode */
2548 rctl = E1000_READ_REG(hw, E1000_RCTL);
2549 rctl &= (~E1000_RCTL_MPE);
2550 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2556 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2558 struct e1000_hw *hw =
2559 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2560 struct e1000_vfta * shadow_vfta =
2561 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2566 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2567 E1000_VFTA_ENTRY_MASK);
2568 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2569 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2574 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2576 /* update local VFTA copy */
2577 shadow_vfta->vfta[vid_idx] = vfta;
2583 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2584 enum rte_vlan_type vlan_type,
2587 struct e1000_hw *hw =
2588 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2592 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2594 /* only outer TPID of double VLAN can be configured*/
2595 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2596 reg = E1000_READ_REG(hw, E1000_VET);
2597 reg = (reg & (~E1000_VET_VET_EXT)) |
2598 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2599 E1000_WRITE_REG(hw, E1000_VET, reg);
2604 /* all other TPID values are read-only*/
2605 PMD_DRV_LOG(ERR, "Not supported");
2611 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2613 struct e1000_hw *hw =
2614 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2617 /* Filter Table Disable */
2618 reg = E1000_READ_REG(hw, E1000_RCTL);
2619 reg &= ~E1000_RCTL_CFIEN;
2620 reg &= ~E1000_RCTL_VFE;
2621 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2625 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2627 struct e1000_hw *hw =
2628 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629 struct e1000_vfta * shadow_vfta =
2630 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2634 /* Filter Table Enable, CFI not used for packet acceptance */
2635 reg = E1000_READ_REG(hw, E1000_RCTL);
2636 reg &= ~E1000_RCTL_CFIEN;
2637 reg |= E1000_RCTL_VFE;
2638 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2640 /* restore VFTA table */
2641 for (i = 0; i < IGB_VFTA_SIZE; i++)
2642 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2646 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2648 struct e1000_hw *hw =
2649 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2652 /* VLAN Mode Disable */
2653 reg = E1000_READ_REG(hw, E1000_CTRL);
2654 reg &= ~E1000_CTRL_VME;
2655 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2659 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2661 struct e1000_hw *hw =
2662 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2665 /* VLAN Mode Enable */
2666 reg = E1000_READ_REG(hw, E1000_CTRL);
2667 reg |= E1000_CTRL_VME;
2668 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2672 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2674 struct e1000_hw *hw =
2675 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2678 /* CTRL_EXT: Extended VLAN */
2679 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2680 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2681 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2683 /* Update maximum packet length */
2684 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2685 E1000_WRITE_REG(hw, E1000_RLPML,
2686 dev->data->dev_conf.rxmode.max_rx_pkt_len);
2690 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2692 struct e1000_hw *hw =
2693 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2696 /* CTRL_EXT: Extended VLAN */
2697 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2698 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2699 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2701 /* Update maximum packet length */
2702 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2703 E1000_WRITE_REG(hw, E1000_RLPML,
2704 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2709 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2711 struct rte_eth_rxmode *rxmode;
2713 rxmode = &dev->data->dev_conf.rxmode;
2714 if(mask & ETH_VLAN_STRIP_MASK){
2715 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2716 igb_vlan_hw_strip_enable(dev);
2718 igb_vlan_hw_strip_disable(dev);
2721 if(mask & ETH_VLAN_FILTER_MASK){
2722 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2723 igb_vlan_hw_filter_enable(dev);
2725 igb_vlan_hw_filter_disable(dev);
2728 if(mask & ETH_VLAN_EXTEND_MASK){
2729 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2730 igb_vlan_hw_extend_enable(dev);
2732 igb_vlan_hw_extend_disable(dev);
2740 * It enables the interrupt mask and then enable the interrupt.
2743 * Pointer to struct rte_eth_dev.
2748 * - On success, zero.
2749 * - On failure, a negative value.
2752 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2754 struct e1000_interrupt *intr =
2755 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2758 intr->mask |= E1000_ICR_LSC;
2760 intr->mask &= ~E1000_ICR_LSC;
2765 /* It clears the interrupt causes and enables the interrupt.
2766 * It will be called once only during nic initialized.
2769 * Pointer to struct rte_eth_dev.
2772 * - On success, zero.
2773 * - On failure, a negative value.
2775 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2777 uint32_t mask, regval;
2779 struct e1000_hw *hw =
2780 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2781 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2782 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2783 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2784 struct rte_eth_dev_info dev_info;
2786 memset(&dev_info, 0, sizeof(dev_info));
2787 ret = eth_igb_infos_get(dev, &dev_info);
2791 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2792 regval = E1000_READ_REG(hw, E1000_EIMS);
2793 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2799 * It reads ICR and gets interrupt causes, check it and set a bit flag
2800 * to update link status.
2803 * Pointer to struct rte_eth_dev.
2806 * - On success, zero.
2807 * - On failure, a negative value.
2810 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2813 struct e1000_hw *hw =
2814 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815 struct e1000_interrupt *intr =
2816 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2818 igb_intr_disable(dev);
2820 /* read-on-clear nic registers here */
2821 icr = E1000_READ_REG(hw, E1000_ICR);
2824 if (icr & E1000_ICR_LSC) {
2825 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2828 if (icr & E1000_ICR_VMMB)
2829 intr->flags |= E1000_FLAG_MAILBOX;
2835 * It executes link_update after knowing an interrupt is prsent.
2838 * Pointer to struct rte_eth_dev.
2841 * - On success, zero.
2842 * - On failure, a negative value.
2845 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2846 struct rte_intr_handle *intr_handle)
2848 struct e1000_hw *hw =
2849 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850 struct e1000_interrupt *intr =
2851 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2852 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2853 struct rte_eth_link link;
2856 if (intr->flags & E1000_FLAG_MAILBOX) {
2857 igb_pf_mbx_process(dev);
2858 intr->flags &= ~E1000_FLAG_MAILBOX;
2861 igb_intr_enable(dev);
2862 rte_intr_ack(intr_handle);
2864 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2865 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2867 /* set get_link_status to check register later */
2868 hw->mac.get_link_status = 1;
2869 ret = eth_igb_link_update(dev, 0);
2871 /* check if link has changed */
2875 rte_eth_linkstatus_get(dev, &link);
2876 if (link.link_status) {
2878 " Port %d: Link Up - speed %u Mbps - %s",
2880 (unsigned)link.link_speed,
2881 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2882 "full-duplex" : "half-duplex");
2884 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2885 dev->data->port_id);
2888 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2889 pci_dev->addr.domain,
2891 pci_dev->addr.devid,
2892 pci_dev->addr.function);
2893 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2900 * Interrupt handler which shall be registered at first.
2903 * Pointer to interrupt handle.
2905 * The address of parameter (struct rte_eth_dev *) regsitered before.
2911 eth_igb_interrupt_handler(void *param)
2913 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2915 eth_igb_interrupt_get_status(dev);
2916 eth_igb_interrupt_action(dev, dev->intr_handle);
2920 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2923 struct e1000_hw *hw =
2924 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2925 struct e1000_interrupt *intr =
2926 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2928 igbvf_intr_disable(hw);
2930 /* read-on-clear nic registers here */
2931 eicr = E1000_READ_REG(hw, E1000_EICR);
2934 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2935 intr->flags |= E1000_FLAG_MAILBOX;
2940 void igbvf_mbx_process(struct rte_eth_dev *dev)
2942 struct e1000_hw *hw =
2943 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2944 struct e1000_mbx_info *mbx = &hw->mbx;
2947 /* peek the message first */
2948 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2950 /* PF reset VF event */
2951 if (in_msg == E1000_PF_CONTROL_MSG) {
2952 /* dummy mbx read to ack pf */
2953 if (mbx->ops.read(hw, &in_msg, 1, 0))
2955 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2961 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2963 struct e1000_interrupt *intr =
2964 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2966 if (intr->flags & E1000_FLAG_MAILBOX) {
2967 igbvf_mbx_process(dev);
2968 intr->flags &= ~E1000_FLAG_MAILBOX;
2971 igbvf_intr_enable(dev);
2972 rte_intr_ack(intr_handle);
2978 eth_igbvf_interrupt_handler(void *param)
2980 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2982 eth_igbvf_interrupt_get_status(dev);
2983 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2987 eth_igb_led_on(struct rte_eth_dev *dev)
2989 struct e1000_hw *hw;
2991 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2992 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2996 eth_igb_led_off(struct rte_eth_dev *dev)
2998 struct e1000_hw *hw;
3000 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3001 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3005 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3007 struct e1000_hw *hw;
3012 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3013 fc_conf->pause_time = hw->fc.pause_time;
3014 fc_conf->high_water = hw->fc.high_water;
3015 fc_conf->low_water = hw->fc.low_water;
3016 fc_conf->send_xon = hw->fc.send_xon;
3017 fc_conf->autoneg = hw->mac.autoneg;
3020 * Return rx_pause and tx_pause status according to actual setting of
3021 * the TFCE and RFCE bits in the CTRL register.
3023 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3024 if (ctrl & E1000_CTRL_TFCE)
3029 if (ctrl & E1000_CTRL_RFCE)
3034 if (rx_pause && tx_pause)
3035 fc_conf->mode = RTE_FC_FULL;
3037 fc_conf->mode = RTE_FC_RX_PAUSE;
3039 fc_conf->mode = RTE_FC_TX_PAUSE;
3041 fc_conf->mode = RTE_FC_NONE;
3047 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3049 struct e1000_hw *hw;
3051 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3057 uint32_t rx_buf_size;
3058 uint32_t max_high_water;
3062 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3063 if (fc_conf->autoneg != hw->mac.autoneg)
3065 rx_buf_size = igb_get_rx_buffer_size(hw);
3066 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3068 /* At least reserve one Ethernet frame for watermark */
3069 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3070 if ((fc_conf->high_water > max_high_water) ||
3071 (fc_conf->high_water < fc_conf->low_water)) {
3072 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3073 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3077 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3078 hw->fc.pause_time = fc_conf->pause_time;
3079 hw->fc.high_water = fc_conf->high_water;
3080 hw->fc.low_water = fc_conf->low_water;
3081 hw->fc.send_xon = fc_conf->send_xon;
3083 err = e1000_setup_link_generic(hw);
3084 if (err == E1000_SUCCESS) {
3086 /* check if we want to forward MAC frames - driver doesn't have native
3087 * capability to do that, so we'll write the registers ourselves */
3089 rctl = E1000_READ_REG(hw, E1000_RCTL);
3091 /* set or clear MFLCN.PMCF bit depending on configuration */
3092 if (fc_conf->mac_ctrl_frame_fwd != 0)
3093 rctl |= E1000_RCTL_PMCF;
3095 rctl &= ~E1000_RCTL_PMCF;
3097 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3100 * check if we want to change flow control mode - driver doesn't have native
3101 * capability to do that, so we'll write the registers ourselves
3103 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3106 * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits depending
3109 switch (fc_conf->mode) {
3111 ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE;
3113 case RTE_FC_RX_PAUSE:
3114 ctrl |= E1000_CTRL_RFCE;
3115 ctrl &= ~E1000_CTRL_TFCE;
3117 case RTE_FC_TX_PAUSE:
3118 ctrl |= E1000_CTRL_TFCE;
3119 ctrl &= ~E1000_CTRL_RFCE;
3122 ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE;
3125 PMD_INIT_LOG(ERR, "invalid flow control mode");
3129 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3131 E1000_WRITE_FLUSH(hw);
3136 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3140 #define E1000_RAH_POOLSEL_SHIFT (18)
3142 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3143 uint32_t index, uint32_t pool)
3145 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3148 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3149 rah = E1000_READ_REG(hw, E1000_RAH(index));
3150 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3151 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3156 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3158 uint8_t addr[RTE_ETHER_ADDR_LEN];
3159 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161 memset(addr, 0, sizeof(addr));
3163 e1000_rar_set(hw, addr, index);
3167 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3168 struct rte_ether_addr *addr)
3170 eth_igb_rar_clear(dev, 0);
3171 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3176 * Virtual Function operations
3179 igbvf_intr_disable(struct e1000_hw *hw)
3181 PMD_INIT_FUNC_TRACE();
3183 /* Clear interrupt mask to stop from interrupts being generated */
3184 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3186 E1000_WRITE_FLUSH(hw);
3190 igbvf_stop_adapter(struct rte_eth_dev *dev)
3194 struct rte_eth_dev_info dev_info;
3195 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3198 memset(&dev_info, 0, sizeof(dev_info));
3199 ret = eth_igbvf_infos_get(dev, &dev_info);
3203 /* Clear interrupt mask to stop from interrupts being generated */
3204 igbvf_intr_disable(hw);
3206 /* Clear any pending interrupts, flush previous writes */
3207 E1000_READ_REG(hw, E1000_EICR);
3209 /* Disable the transmit unit. Each queue must be disabled. */
3210 for (i = 0; i < dev_info.max_tx_queues; i++)
3211 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3213 /* Disable the receive unit by stopping each queue */
3214 for (i = 0; i < dev_info.max_rx_queues; i++) {
3215 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3216 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3217 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3218 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3222 /* flush all queues disables */
3223 E1000_WRITE_FLUSH(hw);
3227 static int eth_igbvf_link_update(struct e1000_hw *hw)
3229 struct e1000_mbx_info *mbx = &hw->mbx;
3230 struct e1000_mac_info *mac = &hw->mac;
3231 int ret_val = E1000_SUCCESS;
3233 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3236 * We only want to run this if there has been a rst asserted.
3237 * in this case that could mean a link change, device reset,
3238 * or a virtual function reset
3241 /* If we were hit with a reset or timeout drop the link */
3242 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3243 mac->get_link_status = TRUE;
3245 if (!mac->get_link_status)
3248 /* if link status is down no point in checking to see if pf is up */
3249 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3252 /* if we passed all the tests above then the link is up and we no
3253 * longer need to check for link */
3254 mac->get_link_status = FALSE;
3262 igbvf_dev_configure(struct rte_eth_dev *dev)
3264 struct rte_eth_conf* conf = &dev->data->dev_conf;
3266 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3267 dev->data->port_id);
3269 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3270 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3273 * VF has no ability to enable/disable HW CRC
3274 * Keep the persistent behavior the same as Host PF
3276 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3277 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3278 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3279 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3282 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3283 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3284 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3292 igbvf_dev_start(struct rte_eth_dev *dev)
3294 struct e1000_hw *hw =
3295 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296 struct e1000_adapter *adapter =
3297 E1000_DEV_PRIVATE(dev->data->dev_private);
3298 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3299 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3301 uint32_t intr_vector = 0;
3303 PMD_INIT_FUNC_TRACE();
3305 hw->mac.ops.reset_hw(hw);
3306 adapter->stopped = 0;
3309 igbvf_set_vfta_all(dev,1);
3311 eth_igbvf_tx_init(dev);
3313 /* This can fail when allocating mbufs for descriptor rings */
3314 ret = eth_igbvf_rx_init(dev);
3316 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3317 igb_dev_clear_queues(dev);
3321 /* check and configure queue intr-vector mapping */
3322 if (rte_intr_cap_multiple(intr_handle) &&
3323 dev->data->dev_conf.intr_conf.rxq) {
3324 intr_vector = dev->data->nb_rx_queues;
3325 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3330 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3331 intr_handle->intr_vec =
3332 rte_zmalloc("intr_vec",
3333 dev->data->nb_rx_queues * sizeof(int), 0);
3334 if (!intr_handle->intr_vec) {
3335 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3336 " intr_vec", dev->data->nb_rx_queues);
3341 eth_igbvf_configure_msix_intr(dev);
3343 /* enable uio/vfio intr/eventfd mapping */
3344 rte_intr_enable(intr_handle);
3346 /* resume enabled intr since hw reset */
3347 igbvf_intr_enable(dev);
3353 igbvf_dev_stop(struct rte_eth_dev *dev)
3355 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3356 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3357 struct e1000_adapter *adapter =
3358 E1000_DEV_PRIVATE(dev->data->dev_private);
3360 if (adapter->stopped)
3363 PMD_INIT_FUNC_TRACE();
3365 igbvf_stop_adapter(dev);
3368 * Clear what we set, but we still keep shadow_vfta to
3369 * restore after device starts
3371 igbvf_set_vfta_all(dev,0);
3373 igb_dev_clear_queues(dev);
3375 /* disable intr eventfd mapping */
3376 rte_intr_disable(intr_handle);
3378 /* Clean datapath event and queue/vec mapping */
3379 rte_intr_efd_disable(intr_handle);
3380 if (intr_handle->intr_vec) {
3381 rte_free(intr_handle->intr_vec);
3382 intr_handle->intr_vec = NULL;
3385 adapter->stopped = true;
3386 dev->data->dev_started = 0;
3392 igbvf_dev_close(struct rte_eth_dev *dev)
3394 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3395 struct rte_ether_addr addr;
3396 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3399 PMD_INIT_FUNC_TRACE();
3401 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3406 ret = igbvf_dev_stop(dev);
3410 igb_dev_free_queues(dev);
3413 * reprogram the RAR with a zero mac address,
3414 * to ensure that the VF traffic goes to the PF
3415 * after stop, close and detach of the VF.
3418 memset(&addr, 0, sizeof(addr));
3419 igbvf_default_mac_addr_set(dev, &addr);
3421 rte_intr_callback_unregister(&pci_dev->intr_handle,
3422 eth_igbvf_interrupt_handler,
3429 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3431 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3433 /* Set both unicast and multicast promisc */
3434 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3440 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3442 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444 /* If in allmulticast mode leave multicast promisc */
3445 if (dev->data->all_multicast == 1)
3446 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3448 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3454 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3456 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458 /* In promiscuous mode multicast promisc already set */
3459 if (dev->data->promiscuous == 0)
3460 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3466 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3468 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3470 /* In promiscuous mode leave multicast promisc enabled */
3471 if (dev->data->promiscuous == 0)
3472 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3477 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3479 struct e1000_mbx_info *mbx = &hw->mbx;
3483 /* After set vlan, vlan strip will also be enabled in igb driver*/
3484 msgbuf[0] = E1000_VF_SET_VLAN;
3486 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3488 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3490 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3494 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3498 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3499 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3506 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3508 struct e1000_hw *hw =
3509 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510 struct e1000_vfta * shadow_vfta =
3511 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3512 int i = 0, j = 0, vfta = 0, mask = 1;
3514 for (i = 0; i < IGB_VFTA_SIZE; i++){
3515 vfta = shadow_vfta->vfta[i];
3518 for (j = 0; j < 32; j++){
3521 (uint16_t)((i<<5)+j), on);
3530 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3532 struct e1000_hw *hw =
3533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3534 struct e1000_vfta * shadow_vfta =
3535 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3536 uint32_t vid_idx = 0;
3537 uint32_t vid_bit = 0;
3540 PMD_INIT_FUNC_TRACE();
3542 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3543 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3545 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3548 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3549 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3551 /*Save what we set and retore it after device reset*/
3553 shadow_vfta->vfta[vid_idx] |= vid_bit;
3555 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3561 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3563 struct e1000_hw *hw =
3564 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3566 /* index is not used by rar_set() */
3567 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3573 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3574 struct rte_eth_rss_reta_entry64 *reta_conf,
3579 uint16_t idx, shift;
3580 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3582 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3583 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3584 "(%d) doesn't match the number hardware can supported "
3585 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3589 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3590 idx = i / RTE_RETA_GROUP_SIZE;
3591 shift = i % RTE_RETA_GROUP_SIZE;
3592 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3596 if (mask == IGB_4_BIT_MASK)
3599 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3600 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3601 if (mask & (0x1 << j))
3602 reta |= reta_conf[idx].reta[shift + j] <<
3605 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3607 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3614 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3615 struct rte_eth_rss_reta_entry64 *reta_conf,
3620 uint16_t idx, shift;
3621 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3624 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3625 "(%d) doesn't match the number hardware can supported "
3626 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3630 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3631 idx = i / RTE_RETA_GROUP_SIZE;
3632 shift = i % RTE_RETA_GROUP_SIZE;
3633 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3637 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3638 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3639 if (mask & (0x1 << j))
3640 reta_conf[idx].reta[shift + j] =
3641 ((reta >> (CHAR_BIT * j)) &
3650 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3651 struct rte_eth_syn_filter *filter,
3654 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3655 struct e1000_filter_info *filter_info =
3656 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3657 uint32_t synqf, rfctl;
3659 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3662 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3665 if (synqf & E1000_SYN_FILTER_ENABLE)
3668 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3669 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3671 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3672 if (filter->hig_pri)
3673 rfctl |= E1000_RFCTL_SYNQFP;
3675 rfctl &= ~E1000_RFCTL_SYNQFP;
3677 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3679 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3684 filter_info->syn_info = synqf;
3685 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3686 E1000_WRITE_FLUSH(hw);
3690 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3692 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3693 struct e1000_2tuple_filter_info *filter_info)
3695 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3697 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3698 return -EINVAL; /* filter index is out of range. */
3699 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3700 return -EINVAL; /* flags is invalid. */
3702 switch (filter->dst_port_mask) {
3704 filter_info->dst_port_mask = 0;
3705 filter_info->dst_port = filter->dst_port;
3708 filter_info->dst_port_mask = 1;
3711 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3715 switch (filter->proto_mask) {
3717 filter_info->proto_mask = 0;
3718 filter_info->proto = filter->proto;
3721 filter_info->proto_mask = 1;
3724 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3728 filter_info->priority = (uint8_t)filter->priority;
3729 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3730 filter_info->tcp_flags = filter->tcp_flags;
3732 filter_info->tcp_flags = 0;
3737 static inline struct e1000_2tuple_filter *
3738 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3739 struct e1000_2tuple_filter_info *key)
3741 struct e1000_2tuple_filter *it;
3743 TAILQ_FOREACH(it, filter_list, entries) {
3744 if (memcmp(key, &it->filter_info,
3745 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3752 /* inject a igb 2tuple filter to HW */
3754 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3755 struct e1000_2tuple_filter *filter)
3757 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3758 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3759 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3763 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3764 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3765 imir |= E1000_IMIR_PORT_BP;
3767 imir &= ~E1000_IMIR_PORT_BP;
3769 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3771 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3772 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3773 ttqf |= (uint32_t)(filter->filter_info.proto &
3774 E1000_TTQF_PROTOCOL_MASK);
3775 if (filter->filter_info.proto_mask == 0)
3776 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3778 /* tcp flags bits setting. */
3779 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3780 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3781 imir_ext |= E1000_IMIREXT_CTRL_URG;
3782 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3783 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3784 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3785 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3786 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3787 imir_ext |= E1000_IMIREXT_CTRL_RST;
3788 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3789 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3790 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3791 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3793 imir_ext |= E1000_IMIREXT_CTRL_BP;
3795 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3796 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3797 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3801 * igb_add_2tuple_filter - add a 2tuple filter
3804 * dev: Pointer to struct rte_eth_dev.
3805 * ntuple_filter: ponter to the filter that will be added.
3808 * - On success, zero.
3809 * - On failure, a negative value.
3812 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3813 struct rte_eth_ntuple_filter *ntuple_filter)
3815 struct e1000_filter_info *filter_info =
3816 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3817 struct e1000_2tuple_filter *filter;
3820 filter = rte_zmalloc("e1000_2tuple_filter",
3821 sizeof(struct e1000_2tuple_filter), 0);
3825 ret = ntuple_filter_to_2tuple(ntuple_filter,
3826 &filter->filter_info);
3831 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3832 &filter->filter_info) != NULL) {
3833 PMD_DRV_LOG(ERR, "filter exists.");
3837 filter->queue = ntuple_filter->queue;
3840 * look for an unused 2tuple filter index,
3841 * and insert the filter to list.
3843 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3844 if (!(filter_info->twotuple_mask & (1 << i))) {
3845 filter_info->twotuple_mask |= 1 << i;
3847 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3853 if (i >= E1000_MAX_TTQF_FILTERS) {
3854 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3859 igb_inject_2uple_filter(dev, filter);
3864 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3865 struct e1000_2tuple_filter *filter)
3867 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3868 struct e1000_filter_info *filter_info =
3869 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3871 filter_info->twotuple_mask &= ~(1 << filter->index);
3872 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3875 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3876 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3877 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3882 * igb_remove_2tuple_filter - remove a 2tuple filter
3885 * dev: Pointer to struct rte_eth_dev.
3886 * ntuple_filter: ponter to the filter that will be removed.
3889 * - On success, zero.
3890 * - On failure, a negative value.
3893 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3894 struct rte_eth_ntuple_filter *ntuple_filter)
3896 struct e1000_filter_info *filter_info =
3897 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3898 struct e1000_2tuple_filter_info filter_2tuple;
3899 struct e1000_2tuple_filter *filter;
3902 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3903 ret = ntuple_filter_to_2tuple(ntuple_filter,
3908 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3910 if (filter == NULL) {
3911 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3915 igb_delete_2tuple_filter(dev, filter);
3920 /* inject a igb flex filter to HW */
3922 igb_inject_flex_filter(struct rte_eth_dev *dev,
3923 struct e1000_flex_filter *filter)
3925 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3926 uint32_t wufc, queueing;
3930 wufc = E1000_READ_REG(hw, E1000_WUFC);
3931 if (filter->index < E1000_MAX_FHFT)
3932 reg_off = E1000_FHFT(filter->index);
3934 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3936 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3937 (E1000_WUFC_FLX0 << filter->index));
3938 queueing = filter->filter_info.len |
3939 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3940 (filter->filter_info.priority <<
3941 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3942 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3945 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3946 E1000_WRITE_REG(hw, reg_off,
3947 filter->filter_info.dwords[j]);
3948 reg_off += sizeof(uint32_t);
3949 E1000_WRITE_REG(hw, reg_off,
3950 filter->filter_info.dwords[++j]);
3951 reg_off += sizeof(uint32_t);
3952 E1000_WRITE_REG(hw, reg_off,
3953 (uint32_t)filter->filter_info.mask[i]);
3954 reg_off += sizeof(uint32_t) * 2;
3959 static inline struct e1000_flex_filter *
3960 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3961 struct e1000_flex_filter_info *key)
3963 struct e1000_flex_filter *it;
3965 TAILQ_FOREACH(it, filter_list, entries) {
3966 if (memcmp(key, &it->filter_info,
3967 sizeof(struct e1000_flex_filter_info)) == 0)
3974 /* remove a flex byte filter
3976 * dev: Pointer to struct rte_eth_dev.
3977 * filter: the pointer of the filter will be removed.
3980 igb_remove_flex_filter(struct rte_eth_dev *dev,
3981 struct e1000_flex_filter *filter)
3983 struct e1000_filter_info *filter_info =
3984 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3985 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3989 wufc = E1000_READ_REG(hw, E1000_WUFC);
3990 if (filter->index < E1000_MAX_FHFT)
3991 reg_off = E1000_FHFT(filter->index);
3993 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3995 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3996 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3998 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3999 (~(E1000_WUFC_FLX0 << filter->index)));
4001 filter_info->flex_mask &= ~(1 << filter->index);
4002 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4007 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4008 struct igb_flex_filter *filter,
4011 struct e1000_filter_info *filter_info =
4012 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4013 struct e1000_flex_filter *flex_filter, *it;
4017 flex_filter = rte_zmalloc("e1000_flex_filter",
4018 sizeof(struct e1000_flex_filter), 0);
4019 if (flex_filter == NULL)
4022 flex_filter->filter_info.len = filter->len;
4023 flex_filter->filter_info.priority = filter->priority;
4024 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4025 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4027 /* reverse bits in flex filter's mask*/
4028 for (shift = 0; shift < CHAR_BIT; shift++) {
4029 if (filter->mask[i] & (0x01 << shift))
4030 mask |= (0x80 >> shift);
4032 flex_filter->filter_info.mask[i] = mask;
4035 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4036 &flex_filter->filter_info);
4037 if (it == NULL && !add) {
4038 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4039 rte_free(flex_filter);
4042 if (it != NULL && add) {
4043 PMD_DRV_LOG(ERR, "filter exists.");
4044 rte_free(flex_filter);
4049 flex_filter->queue = filter->queue;
4051 * look for an unused flex filter index
4052 * and insert the filter into the list.
4054 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4055 if (!(filter_info->flex_mask & (1 << i))) {
4056 filter_info->flex_mask |= 1 << i;
4057 flex_filter->index = i;
4058 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4064 if (i >= E1000_MAX_FLEX_FILTERS) {
4065 PMD_DRV_LOG(ERR, "flex filters are full.");
4066 rte_free(flex_filter);
4070 igb_inject_flex_filter(dev, flex_filter);
4073 igb_remove_flex_filter(dev, it);
4074 rte_free(flex_filter);
4080 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4082 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4083 struct e1000_5tuple_filter_info *filter_info)
4085 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4087 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4088 return -EINVAL; /* filter index is out of range. */
4089 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4090 return -EINVAL; /* flags is invalid. */
4092 switch (filter->dst_ip_mask) {
4094 filter_info->dst_ip_mask = 0;
4095 filter_info->dst_ip = filter->dst_ip;
4098 filter_info->dst_ip_mask = 1;
4101 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4105 switch (filter->src_ip_mask) {
4107 filter_info->src_ip_mask = 0;
4108 filter_info->src_ip = filter->src_ip;
4111 filter_info->src_ip_mask = 1;
4114 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4118 switch (filter->dst_port_mask) {
4120 filter_info->dst_port_mask = 0;
4121 filter_info->dst_port = filter->dst_port;
4124 filter_info->dst_port_mask = 1;
4127 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4131 switch (filter->src_port_mask) {
4133 filter_info->src_port_mask = 0;
4134 filter_info->src_port = filter->src_port;
4137 filter_info->src_port_mask = 1;
4140 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4144 switch (filter->proto_mask) {
4146 filter_info->proto_mask = 0;
4147 filter_info->proto = filter->proto;
4150 filter_info->proto_mask = 1;
4153 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4157 filter_info->priority = (uint8_t)filter->priority;
4158 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4159 filter_info->tcp_flags = filter->tcp_flags;
4161 filter_info->tcp_flags = 0;
4166 static inline struct e1000_5tuple_filter *
4167 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4168 struct e1000_5tuple_filter_info *key)
4170 struct e1000_5tuple_filter *it;
4172 TAILQ_FOREACH(it, filter_list, entries) {
4173 if (memcmp(key, &it->filter_info,
4174 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4181 /* inject a igb 5-tuple filter to HW */
4183 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4184 struct e1000_5tuple_filter *filter)
4186 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4187 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4188 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4192 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4193 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4194 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4195 if (filter->filter_info.dst_ip_mask == 0)
4196 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4197 if (filter->filter_info.src_port_mask == 0)
4198 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4199 if (filter->filter_info.proto_mask == 0)
4200 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4201 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4202 E1000_FTQF_QUEUE_MASK;
4203 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4204 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4205 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4206 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4208 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4209 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4211 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4212 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4213 imir |= E1000_IMIR_PORT_BP;
4215 imir &= ~E1000_IMIR_PORT_BP;
4216 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4218 /* tcp flags bits setting. */
4219 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4220 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4221 imir_ext |= E1000_IMIREXT_CTRL_URG;
4222 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4223 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4224 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4225 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4226 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4227 imir_ext |= E1000_IMIREXT_CTRL_RST;
4228 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4229 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4230 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4231 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4233 imir_ext |= E1000_IMIREXT_CTRL_BP;
4235 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4236 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4240 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4243 * dev: Pointer to struct rte_eth_dev.
4244 * ntuple_filter: ponter to the filter that will be added.
4247 * - On success, zero.
4248 * - On failure, a negative value.
4251 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4252 struct rte_eth_ntuple_filter *ntuple_filter)
4254 struct e1000_filter_info *filter_info =
4255 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4256 struct e1000_5tuple_filter *filter;
4260 filter = rte_zmalloc("e1000_5tuple_filter",
4261 sizeof(struct e1000_5tuple_filter), 0);
4265 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4266 &filter->filter_info);
4272 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4273 &filter->filter_info) != NULL) {
4274 PMD_DRV_LOG(ERR, "filter exists.");
4278 filter->queue = ntuple_filter->queue;
4281 * look for an unused 5tuple filter index,
4282 * and insert the filter to list.
4284 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4285 if (!(filter_info->fivetuple_mask & (1 << i))) {
4286 filter_info->fivetuple_mask |= 1 << i;
4288 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4294 if (i >= E1000_MAX_FTQF_FILTERS) {
4295 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4300 igb_inject_5tuple_filter_82576(dev, filter);
4305 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4306 struct e1000_5tuple_filter *filter)
4308 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4309 struct e1000_filter_info *filter_info =
4310 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4312 filter_info->fivetuple_mask &= ~(1 << filter->index);
4313 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4316 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4317 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4318 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4319 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4320 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4321 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4322 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4327 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4330 * dev: Pointer to struct rte_eth_dev.
4331 * ntuple_filter: ponter to the filter that will be removed.
4334 * - On success, zero.
4335 * - On failure, a negative value.
4338 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4339 struct rte_eth_ntuple_filter *ntuple_filter)
4341 struct e1000_filter_info *filter_info =
4342 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4343 struct e1000_5tuple_filter_info filter_5tuple;
4344 struct e1000_5tuple_filter *filter;
4347 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4348 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4353 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4355 if (filter == NULL) {
4356 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4360 igb_delete_5tuple_filter_82576(dev, filter);
4366 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4369 struct e1000_hw *hw;
4370 struct rte_eth_dev_info dev_info;
4371 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4374 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4376 #ifdef RTE_LIBRTE_82571_SUPPORT
4377 /* XXX: not bigger than max_rx_pktlen */
4378 if (hw->mac.type == e1000_82571)
4381 ret = eth_igb_infos_get(dev, &dev_info);
4385 /* check that mtu is within the allowed range */
4386 if (mtu < RTE_ETHER_MIN_MTU ||
4387 frame_size > dev_info.max_rx_pktlen)
4391 * If device is started, refuse mtu that requires the support of
4392 * scattered packets when this feature has not been enabled before.
4394 if (dev->data->dev_started && !dev->data->scattered_rx &&
4395 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
4396 PMD_INIT_LOG(ERR, "Stop port first.");
4400 rctl = E1000_READ_REG(hw, E1000_RCTL);
4402 /* switch to jumbo mode if needed */
4403 if (frame_size > E1000_ETH_MAX_LEN) {
4404 dev->data->dev_conf.rxmode.offloads |=
4405 DEV_RX_OFFLOAD_JUMBO_FRAME;
4406 rctl |= E1000_RCTL_LPE;
4408 dev->data->dev_conf.rxmode.offloads &=
4409 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4410 rctl &= ~E1000_RCTL_LPE;
4412 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4414 /* update max frame size */
4415 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4417 E1000_WRITE_REG(hw, E1000_RLPML,
4418 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4424 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4427 * dev: Pointer to struct rte_eth_dev.
4428 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4429 * add: if true, add filter, if false, remove filter
4432 * - On success, zero.
4433 * - On failure, a negative value.
4436 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4437 struct rte_eth_ntuple_filter *ntuple_filter,
4440 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4443 switch (ntuple_filter->flags) {
4444 case RTE_5TUPLE_FLAGS:
4445 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4446 if (hw->mac.type != e1000_82576)
4449 ret = igb_add_5tuple_filter_82576(dev,
4452 ret = igb_remove_5tuple_filter_82576(dev,
4455 case RTE_2TUPLE_FLAGS:
4456 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4457 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4458 hw->mac.type != e1000_i210 &&
4459 hw->mac.type != e1000_i211)
4462 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4464 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4475 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4480 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4481 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4482 (filter_info->ethertype_mask & (1 << i)))
4489 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4490 uint16_t ethertype, uint32_t etqf)
4494 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4495 if (!(filter_info->ethertype_mask & (1 << i))) {
4496 filter_info->ethertype_mask |= 1 << i;
4497 filter_info->ethertype_filters[i].ethertype = ethertype;
4498 filter_info->ethertype_filters[i].etqf = etqf;
4506 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4509 if (idx >= E1000_MAX_ETQF_FILTERS)
4511 filter_info->ethertype_mask &= ~(1 << idx);
4512 filter_info->ethertype_filters[idx].ethertype = 0;
4513 filter_info->ethertype_filters[idx].etqf = 0;
4519 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4520 struct rte_eth_ethertype_filter *filter,
4523 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524 struct e1000_filter_info *filter_info =
4525 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4529 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4530 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4531 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4532 " ethertype filter.", filter->ether_type);
4536 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4537 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4540 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4541 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4545 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4546 if (ret >= 0 && add) {
4547 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4548 filter->ether_type);
4551 if (ret < 0 && !add) {
4552 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4553 filter->ether_type);
4558 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4559 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4560 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4561 ret = igb_ethertype_filter_insert(filter_info,
4562 filter->ether_type, etqf);
4564 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4568 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4572 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4573 E1000_WRITE_FLUSH(hw);
4579 eth_igb_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
4580 const struct rte_flow_ops **ops)
4582 *ops = &igb_flow_ops;
4587 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4588 struct rte_ether_addr *mc_addr_set,
4589 uint32_t nb_mc_addr)
4591 struct e1000_hw *hw;
4593 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4594 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4599 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4601 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4602 uint64_t systime_cycles;
4604 switch (hw->mac.type) {
4608 * Need to read System Time Residue Register to be able
4609 * to read the other two registers.
4611 E1000_READ_REG(hw, E1000_SYSTIMR);
4612 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4613 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4614 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4621 * Need to read System Time Residue Register to be able
4622 * to read the other two registers.
4624 E1000_READ_REG(hw, E1000_SYSTIMR);
4625 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4626 /* Only the 8 LSB are valid. */
4627 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4631 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4632 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4637 return systime_cycles;
4641 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4643 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4644 uint64_t rx_tstamp_cycles;
4646 switch (hw->mac.type) {
4649 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4650 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4651 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4657 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4658 /* Only the 8 LSB are valid. */
4659 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4663 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4664 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4669 return rx_tstamp_cycles;
4673 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4675 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4676 uint64_t tx_tstamp_cycles;
4678 switch (hw->mac.type) {
4681 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4682 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4683 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4689 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4690 /* Only the 8 LSB are valid. */
4691 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4695 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4696 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4701 return tx_tstamp_cycles;
4705 igb_start_timecounters(struct rte_eth_dev *dev)
4707 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4708 struct e1000_adapter *adapter = dev->data->dev_private;
4709 uint32_t incval = 1;
4711 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4713 switch (hw->mac.type) {
4717 /* 32 LSB bits + 8 MSB bits = 40 bits */
4718 mask = (1ULL << 40) - 1;
4723 * Start incrementing the register
4724 * used to timestamp PTP packets.
4726 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4729 incval = E1000_INCVALUE_82576;
4730 shift = IGB_82576_TSYNC_SHIFT;
4731 E1000_WRITE_REG(hw, E1000_TIMINCA,
4732 E1000_INCPERIOD_82576 | incval);
4739 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4740 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4741 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4743 adapter->systime_tc.cc_mask = mask;
4744 adapter->systime_tc.cc_shift = shift;
4745 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4747 adapter->rx_tstamp_tc.cc_mask = mask;
4748 adapter->rx_tstamp_tc.cc_shift = shift;
4749 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4751 adapter->tx_tstamp_tc.cc_mask = mask;
4752 adapter->tx_tstamp_tc.cc_shift = shift;
4753 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4757 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4759 struct e1000_adapter *adapter = dev->data->dev_private;
4761 adapter->systime_tc.nsec += delta;
4762 adapter->rx_tstamp_tc.nsec += delta;
4763 adapter->tx_tstamp_tc.nsec += delta;
4769 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4772 struct e1000_adapter *adapter = dev->data->dev_private;
4774 ns = rte_timespec_to_ns(ts);
4776 /* Set the timecounters to a new value. */
4777 adapter->systime_tc.nsec = ns;
4778 adapter->rx_tstamp_tc.nsec = ns;
4779 adapter->tx_tstamp_tc.nsec = ns;
4785 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4787 uint64_t ns, systime_cycles;
4788 struct e1000_adapter *adapter = dev->data->dev_private;
4790 systime_cycles = igb_read_systime_cyclecounter(dev);
4791 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4792 *ts = rte_ns_to_timespec(ns);
4798 igb_timesync_enable(struct rte_eth_dev *dev)
4800 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804 /* Stop the timesync system time. */
4805 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4806 /* Reset the timesync system time value. */
4807 switch (hw->mac.type) {
4813 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4816 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4817 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4820 /* Not supported. */
4824 /* Enable system time for it isn't on by default. */
4825 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4826 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4827 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4829 igb_start_timecounters(dev);
4831 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4832 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4833 (RTE_ETHER_TYPE_1588 |
4834 E1000_ETQF_FILTER_ENABLE |
4837 /* Enable timestamping of received PTP packets. */
4838 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4839 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4840 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4842 /* Enable Timestamping of transmitted PTP packets. */
4843 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4844 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4845 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4851 igb_timesync_disable(struct rte_eth_dev *dev)
4853 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4856 /* Disable timestamping of transmitted PTP packets. */
4857 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4858 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4859 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4861 /* Disable timestamping of received PTP packets. */
4862 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4863 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4864 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4866 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4867 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4869 /* Stop incrementating the System Time registers. */
4870 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4876 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4877 struct timespec *timestamp,
4878 uint32_t flags __rte_unused)
4880 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4881 struct e1000_adapter *adapter = dev->data->dev_private;
4882 uint32_t tsync_rxctl;
4883 uint64_t rx_tstamp_cycles;
4886 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4887 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4890 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4891 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4892 *timestamp = rte_ns_to_timespec(ns);
4898 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4899 struct timespec *timestamp)
4901 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4902 struct e1000_adapter *adapter = dev->data->dev_private;
4903 uint32_t tsync_txctl;
4904 uint64_t tx_tstamp_cycles;
4907 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4908 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4911 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4912 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4913 *timestamp = rte_ns_to_timespec(ns);
4919 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4923 const struct reg_info *reg_group;
4925 while ((reg_group = igb_regs[g_ind++]))
4926 count += igb_reg_group_count(reg_group);
4932 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4936 const struct reg_info *reg_group;
4938 while ((reg_group = igbvf_regs[g_ind++]))
4939 count += igb_reg_group_count(reg_group);
4945 eth_igb_get_regs(struct rte_eth_dev *dev,
4946 struct rte_dev_reg_info *regs)
4948 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4949 uint32_t *data = regs->data;
4952 const struct reg_info *reg_group;
4955 regs->length = eth_igb_get_reg_length(dev);
4956 regs->width = sizeof(uint32_t);
4960 /* Support only full register dump */
4961 if ((regs->length == 0) ||
4962 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4963 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4965 while ((reg_group = igb_regs[g_ind++]))
4966 count += igb_read_regs_group(dev, &data[count],
4975 igbvf_get_regs(struct rte_eth_dev *dev,
4976 struct rte_dev_reg_info *regs)
4978 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4979 uint32_t *data = regs->data;
4982 const struct reg_info *reg_group;
4985 regs->length = igbvf_get_reg_length(dev);
4986 regs->width = sizeof(uint32_t);
4990 /* Support only full register dump */
4991 if ((regs->length == 0) ||
4992 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4993 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4995 while ((reg_group = igbvf_regs[g_ind++]))
4996 count += igb_read_regs_group(dev, &data[count],
5005 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5007 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5009 /* Return unit is byte count */
5010 return hw->nvm.word_size * 2;
5014 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5015 struct rte_dev_eeprom_info *in_eeprom)
5017 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5018 struct e1000_nvm_info *nvm = &hw->nvm;
5019 uint16_t *data = in_eeprom->data;
5022 first = in_eeprom->offset >> 1;
5023 length = in_eeprom->length >> 1;
5024 if ((first >= hw->nvm.word_size) ||
5025 ((first + length) >= hw->nvm.word_size))
5028 in_eeprom->magic = hw->vendor_id |
5029 ((uint32_t)hw->device_id << 16);
5031 if ((nvm->ops.read) == NULL)
5034 return nvm->ops.read(hw, first, length, data);
5038 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5039 struct rte_dev_eeprom_info *in_eeprom)
5041 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5042 struct e1000_nvm_info *nvm = &hw->nvm;
5043 uint16_t *data = in_eeprom->data;
5046 first = in_eeprom->offset >> 1;
5047 length = in_eeprom->length >> 1;
5048 if ((first >= hw->nvm.word_size) ||
5049 ((first + length) >= hw->nvm.word_size))
5052 in_eeprom->magic = (uint32_t)hw->vendor_id |
5053 ((uint32_t)hw->device_id << 16);
5055 if ((nvm->ops.write) == NULL)
5057 return nvm->ops.write(hw, first, length, data);
5061 eth_igb_get_module_info(struct rte_eth_dev *dev,
5062 struct rte_eth_dev_module_info *modinfo)
5064 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5066 uint32_t status = 0;
5067 uint16_t sff8472_rev, addr_mode;
5068 bool page_swap = false;
5070 if (hw->phy.media_type == e1000_media_type_copper ||
5071 hw->phy.media_type == e1000_media_type_unknown)
5074 /* Check whether we support SFF-8472 or not */
5075 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5079 /* addressing mode is not supported */
5080 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5084 /* addressing mode is not supported */
5085 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5087 "Address change required to access page 0xA2, "
5088 "but not supported. Please report the module "
5089 "type to the driver maintainers.\n");
5093 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5094 /* We have an SFP, but it does not support SFF-8472 */
5095 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5096 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5098 /* We have an SFP which supports a revision of SFF-8472 */
5099 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5100 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5107 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5108 struct rte_dev_eeprom_info *info)
5110 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5112 uint32_t status = 0;
5113 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5114 u16 first_word, last_word;
5117 first_word = info->offset >> 1;
5118 last_word = (info->offset + info->length - 1) >> 1;
5120 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5121 for (i = 0; i < last_word - first_word + 1; i++) {
5122 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5125 /* Error occurred while reading module */
5129 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5132 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5138 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5140 struct e1000_hw *hw =
5141 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5142 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5143 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5144 uint32_t vec = E1000_MISC_VEC_ID;
5146 if (rte_intr_allow_others(intr_handle))
5147 vec = E1000_RX_VEC_START;
5149 uint32_t mask = 1 << (queue_id + vec);
5151 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5152 E1000_WRITE_FLUSH(hw);
5158 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5160 struct e1000_hw *hw =
5161 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5162 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5163 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5164 uint32_t vec = E1000_MISC_VEC_ID;
5166 if (rte_intr_allow_others(intr_handle))
5167 vec = E1000_RX_VEC_START;
5169 uint32_t mask = 1 << (queue_id + vec);
5172 regval = E1000_READ_REG(hw, E1000_EIMS);
5173 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5174 E1000_WRITE_FLUSH(hw);
5176 rte_intr_ack(intr_handle);
5182 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5183 uint8_t index, uint8_t offset)
5185 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5188 val &= ~((uint32_t)0xFF << offset);
5190 /* write vector and valid bit */
5191 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5193 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5197 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5198 uint8_t queue, uint8_t msix_vector)
5202 if (hw->mac.type == e1000_82575) {
5204 tmp = E1000_EICR_RX_QUEUE0 << queue;
5205 else if (direction == 1)
5206 tmp = E1000_EICR_TX_QUEUE0 << queue;
5207 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5208 } else if (hw->mac.type == e1000_82576) {
5209 if ((direction == 0) || (direction == 1))
5210 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5211 ((queue & 0x8) << 1) +
5213 } else if ((hw->mac.type == e1000_82580) ||
5214 (hw->mac.type == e1000_i350) ||
5215 (hw->mac.type == e1000_i354) ||
5216 (hw->mac.type == e1000_i210) ||
5217 (hw->mac.type == e1000_i211)) {
5218 if ((direction == 0) || (direction == 1))
5219 eth_igb_write_ivar(hw, msix_vector,
5221 ((queue & 0x1) << 4) +
5226 /* Sets up the hardware to generate MSI-X interrupts properly
5228 * board private structure
5231 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5234 uint32_t tmpval, regval, intr_mask;
5235 struct e1000_hw *hw =
5236 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5237 uint32_t vec = E1000_MISC_VEC_ID;
5238 uint32_t base = E1000_MISC_VEC_ID;
5239 uint32_t misc_shift = 0;
5240 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5241 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5243 /* won't configure msix register if no mapping is done
5244 * between intr vector and event fd
5246 if (!rte_intr_dp_is_en(intr_handle))
5249 if (rte_intr_allow_others(intr_handle)) {
5250 vec = base = E1000_RX_VEC_START;
5254 /* set interrupt vector for other causes */
5255 if (hw->mac.type == e1000_82575) {
5256 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5257 /* enable MSI-X PBA support */
5258 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5260 /* Auto-Mask interrupts upon ICR read */
5261 tmpval |= E1000_CTRL_EXT_EIAME;
5262 tmpval |= E1000_CTRL_EXT_IRCA;
5264 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5266 /* enable msix_other interrupt */
5267 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5268 regval = E1000_READ_REG(hw, E1000_EIAC);
5269 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5270 regval = E1000_READ_REG(hw, E1000_EIAM);
5271 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5272 } else if ((hw->mac.type == e1000_82576) ||
5273 (hw->mac.type == e1000_82580) ||
5274 (hw->mac.type == e1000_i350) ||
5275 (hw->mac.type == e1000_i354) ||
5276 (hw->mac.type == e1000_i210) ||
5277 (hw->mac.type == e1000_i211)) {
5278 /* turn on MSI-X capability first */
5279 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5280 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5282 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5285 if (dev->data->dev_conf.intr_conf.lsc != 0)
5286 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5288 regval = E1000_READ_REG(hw, E1000_EIAC);
5289 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5291 /* enable msix_other interrupt */
5292 regval = E1000_READ_REG(hw, E1000_EIMS);
5293 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5294 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5295 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5298 /* use EIAM to auto-mask when MSI-X interrupt
5299 * is asserted, this saves a register write for every interrupt
5301 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5304 if (dev->data->dev_conf.intr_conf.lsc != 0)
5305 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5307 regval = E1000_READ_REG(hw, E1000_EIAM);
5308 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5310 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5311 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5312 intr_handle->intr_vec[queue_id] = vec;
5313 if (vec < base + intr_handle->nb_efd - 1)
5317 E1000_WRITE_FLUSH(hw);
5320 /* restore n-tuple filter */
5322 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5324 struct e1000_filter_info *filter_info =
5325 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5326 struct e1000_5tuple_filter *p_5tuple;
5327 struct e1000_2tuple_filter *p_2tuple;
5329 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5330 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5333 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5334 igb_inject_2uple_filter(dev, p_2tuple);
5338 /* restore SYN filter */
5340 igb_syn_filter_restore(struct rte_eth_dev *dev)
5342 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343 struct e1000_filter_info *filter_info =
5344 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5347 synqf = filter_info->syn_info;
5349 if (synqf & E1000_SYN_FILTER_ENABLE) {
5350 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5351 E1000_WRITE_FLUSH(hw);
5355 /* restore ethernet type filter */
5357 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5359 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5360 struct e1000_filter_info *filter_info =
5361 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5364 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5365 if (filter_info->ethertype_mask & (1 << i)) {
5366 E1000_WRITE_REG(hw, E1000_ETQF(i),
5367 filter_info->ethertype_filters[i].etqf);
5368 E1000_WRITE_FLUSH(hw);
5373 /* restore flex byte filter */
5375 igb_flex_filter_restore(struct rte_eth_dev *dev)
5377 struct e1000_filter_info *filter_info =
5378 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5379 struct e1000_flex_filter *flex_filter;
5381 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5382 igb_inject_flex_filter(dev, flex_filter);
5386 /* restore rss filter */
5388 igb_rss_filter_restore(struct rte_eth_dev *dev)
5390 struct e1000_filter_info *filter_info =
5391 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5393 if (filter_info->rss_info.conf.queue_num)
5394 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5397 /* restore all types filter */
5399 igb_filter_restore(struct rte_eth_dev *dev)
5401 igb_ntuple_filter_restore(dev);
5402 igb_ethertype_filter_restore(dev);
5403 igb_syn_filter_restore(dev);
5404 igb_flex_filter_restore(dev);
5405 igb_rss_filter_restore(dev);
5410 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5411 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5412 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5413 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5414 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5415 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");