4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
64 #define IGB_DEFAULT_RX_PTHRESH 8
65 #define IGB_DEFAULT_RX_HTHRESH 8
66 #define IGB_DEFAULT_RX_WTHRESH 0
68 #define IGB_DEFAULT_TX_PTHRESH 32
69 #define IGB_DEFAULT_TX_HTHRESH 0
70 #define IGB_DEFAULT_TX_WTHRESH 0
72 #define IGB_HKEY_MAX_INDEX 10
74 /* Bit shift and mask */
75 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
76 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
77 #define IGB_8_BIT_WIDTH CHAR_BIT
78 #define IGB_8_BIT_MASK UINT8_MAX
80 /* Additional timesync values. */
81 #define E1000_ETQF_FILTER_1588 3
82 #define E1000_TIMINCA_INCVALUE 16000000
83 #define E1000_TIMINCA_INIT ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
84 | E1000_TIMINCA_INCVALUE)
86 static int eth_igb_configure(struct rte_eth_dev *dev);
87 static int eth_igb_start(struct rte_eth_dev *dev);
88 static void eth_igb_stop(struct rte_eth_dev *dev);
89 static void eth_igb_close(struct rte_eth_dev *dev);
90 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
91 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
92 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
93 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
94 static int eth_igb_link_update(struct rte_eth_dev *dev,
95 int wait_to_complete);
96 static void eth_igb_stats_get(struct rte_eth_dev *dev,
97 struct rte_eth_stats *rte_stats);
98 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
99 static void eth_igb_infos_get(struct rte_eth_dev *dev,
100 struct rte_eth_dev_info *dev_info);
101 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
102 struct rte_eth_dev_info *dev_info);
103 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
104 struct rte_eth_fc_conf *fc_conf);
105 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
106 struct rte_eth_fc_conf *fc_conf);
107 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
108 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
109 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
110 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
112 static int igb_hardware_init(struct e1000_hw *hw);
113 static void igb_hw_control_acquire(struct e1000_hw *hw);
114 static void igb_hw_control_release(struct e1000_hw *hw);
115 static void igb_init_manageability(struct e1000_hw *hw);
116 static void igb_release_manageability(struct e1000_hw *hw);
118 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
120 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
121 uint16_t vlan_id, int on);
122 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
123 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
125 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
126 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
127 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
128 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
129 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
130 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
132 static int eth_igb_led_on(struct rte_eth_dev *dev);
133 static int eth_igb_led_off(struct rte_eth_dev *dev);
135 static void igb_intr_disable(struct e1000_hw *hw);
136 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
137 static void eth_igb_rar_set(struct rte_eth_dev *dev,
138 struct ether_addr *mac_addr,
139 uint32_t index, uint32_t pool);
140 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
141 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
142 struct ether_addr *addr);
144 static void igbvf_intr_disable(struct e1000_hw *hw);
145 static int igbvf_dev_configure(struct rte_eth_dev *dev);
146 static int igbvf_dev_start(struct rte_eth_dev *dev);
147 static void igbvf_dev_stop(struct rte_eth_dev *dev);
148 static void igbvf_dev_close(struct rte_eth_dev *dev);
149 static int eth_igbvf_link_update(struct e1000_hw *hw);
150 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
151 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
152 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
153 uint16_t vlan_id, int on);
154 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
155 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
156 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
157 struct ether_addr *addr);
158 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
159 static int igbvf_get_regs(struct rte_eth_dev *dev,
160 struct rte_dev_reg_info *regs);
162 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
163 struct rte_eth_rss_reta_entry64 *reta_conf,
165 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
166 struct rte_eth_rss_reta_entry64 *reta_conf,
169 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
170 struct rte_eth_syn_filter *filter,
172 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
173 struct rte_eth_syn_filter *filter);
174 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
175 enum rte_filter_op filter_op,
177 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
178 struct rte_eth_ntuple_filter *ntuple_filter);
179 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
180 struct rte_eth_ntuple_filter *ntuple_filter);
181 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
182 struct rte_eth_flex_filter *filter,
184 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
185 struct rte_eth_flex_filter *filter);
186 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
187 enum rte_filter_op filter_op,
189 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
190 struct rte_eth_ntuple_filter *ntuple_filter);
191 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
194 struct rte_eth_ntuple_filter *filter,
196 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
197 struct rte_eth_ntuple_filter *filter);
198 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
199 enum rte_filter_op filter_op,
201 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
202 struct rte_eth_ethertype_filter *filter,
204 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
205 enum rte_filter_op filter_op,
207 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
208 struct rte_eth_ethertype_filter *filter);
209 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
210 enum rte_filter_type filter_type,
211 enum rte_filter_op filter_op,
213 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
214 static int eth_igb_get_regs(struct rte_eth_dev *dev,
215 struct rte_dev_reg_info *regs);
216 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
217 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
218 struct rte_dev_eeprom_info *eeprom);
219 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
220 struct rte_dev_eeprom_info *eeprom);
222 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
223 struct ether_addr *mc_addr_set,
224 uint32_t nb_mc_addr);
225 static int igb_timesync_enable(struct rte_eth_dev *dev);
226 static int igb_timesync_disable(struct rte_eth_dev *dev);
227 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
228 struct timespec *timestamp,
230 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
231 struct timespec *timestamp);
234 * Define VF Stats MACRO for Non "cleared on read" register
236 #define UPDATE_VF_STAT(reg, last, cur) \
238 u32 latest = E1000_READ_REG(hw, reg); \
239 cur += latest - last; \
244 #define IGB_FC_PAUSE_TIME 0x0680
245 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
246 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
248 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
250 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
253 * The set of PCI devices this driver supports
255 static const struct rte_pci_id pci_id_igb_map[] = {
257 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
258 #include "rte_pci_dev_ids.h"
264 * The set of PCI devices this driver supports (for 82576&I350 VF)
266 static const struct rte_pci_id pci_id_igbvf_map[] = {
268 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
269 #include "rte_pci_dev_ids.h"
274 static const struct eth_dev_ops eth_igb_ops = {
275 .dev_configure = eth_igb_configure,
276 .dev_start = eth_igb_start,
277 .dev_stop = eth_igb_stop,
278 .dev_close = eth_igb_close,
279 .promiscuous_enable = eth_igb_promiscuous_enable,
280 .promiscuous_disable = eth_igb_promiscuous_disable,
281 .allmulticast_enable = eth_igb_allmulticast_enable,
282 .allmulticast_disable = eth_igb_allmulticast_disable,
283 .link_update = eth_igb_link_update,
284 .stats_get = eth_igb_stats_get,
285 .stats_reset = eth_igb_stats_reset,
286 .dev_infos_get = eth_igb_infos_get,
287 .mtu_set = eth_igb_mtu_set,
288 .vlan_filter_set = eth_igb_vlan_filter_set,
289 .vlan_tpid_set = eth_igb_vlan_tpid_set,
290 .vlan_offload_set = eth_igb_vlan_offload_set,
291 .rx_queue_setup = eth_igb_rx_queue_setup,
292 .rx_queue_release = eth_igb_rx_queue_release,
293 .rx_queue_count = eth_igb_rx_queue_count,
294 .rx_descriptor_done = eth_igb_rx_descriptor_done,
295 .tx_queue_setup = eth_igb_tx_queue_setup,
296 .tx_queue_release = eth_igb_tx_queue_release,
297 .dev_led_on = eth_igb_led_on,
298 .dev_led_off = eth_igb_led_off,
299 .flow_ctrl_get = eth_igb_flow_ctrl_get,
300 .flow_ctrl_set = eth_igb_flow_ctrl_set,
301 .mac_addr_add = eth_igb_rar_set,
302 .mac_addr_remove = eth_igb_rar_clear,
303 .mac_addr_set = eth_igb_default_mac_addr_set,
304 .reta_update = eth_igb_rss_reta_update,
305 .reta_query = eth_igb_rss_reta_query,
306 .rss_hash_update = eth_igb_rss_hash_update,
307 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
308 .filter_ctrl = eth_igb_filter_ctrl,
309 .set_mc_addr_list = eth_igb_set_mc_addr_list,
310 .timesync_enable = igb_timesync_enable,
311 .timesync_disable = igb_timesync_disable,
312 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
313 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
314 .get_reg_length = eth_igb_get_reg_length,
315 .get_reg = eth_igb_get_regs,
316 .get_eeprom_length = eth_igb_get_eeprom_length,
317 .get_eeprom = eth_igb_get_eeprom,
318 .set_eeprom = eth_igb_set_eeprom,
322 * dev_ops for virtual function, bare necessities for basic vf
323 * operation have been implemented
325 static const struct eth_dev_ops igbvf_eth_dev_ops = {
326 .dev_configure = igbvf_dev_configure,
327 .dev_start = igbvf_dev_start,
328 .dev_stop = igbvf_dev_stop,
329 .dev_close = igbvf_dev_close,
330 .link_update = eth_igb_link_update,
331 .stats_get = eth_igbvf_stats_get,
332 .stats_reset = eth_igbvf_stats_reset,
333 .vlan_filter_set = igbvf_vlan_filter_set,
334 .dev_infos_get = eth_igbvf_infos_get,
335 .rx_queue_setup = eth_igb_rx_queue_setup,
336 .rx_queue_release = eth_igb_rx_queue_release,
337 .tx_queue_setup = eth_igb_tx_queue_setup,
338 .tx_queue_release = eth_igb_tx_queue_release,
339 .set_mc_addr_list = eth_igb_set_mc_addr_list,
340 .mac_addr_set = igbvf_default_mac_addr_set,
341 .get_reg_length = igbvf_get_reg_length,
342 .get_reg = igbvf_get_regs,
346 * Atomically reads the link status information from global
347 * structure rte_eth_dev.
350 * - Pointer to the structure rte_eth_dev to read from.
351 * - Pointer to the buffer to be saved with the link status.
354 * - On success, zero.
355 * - On failure, negative value.
358 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
359 struct rte_eth_link *link)
361 struct rte_eth_link *dst = link;
362 struct rte_eth_link *src = &(dev->data->dev_link);
364 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
365 *(uint64_t *)src) == 0)
372 * Atomically writes the link status information into global
373 * structure rte_eth_dev.
376 * - Pointer to the structure rte_eth_dev to read from.
377 * - Pointer to the buffer to be saved with the link status.
380 * - On success, zero.
381 * - On failure, negative value.
384 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
385 struct rte_eth_link *link)
387 struct rte_eth_link *dst = &(dev->data->dev_link);
388 struct rte_eth_link *src = link;
390 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
391 *(uint64_t *)src) == 0)
398 igb_intr_enable(struct rte_eth_dev *dev)
400 struct e1000_interrupt *intr =
401 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
402 struct e1000_hw *hw =
403 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
405 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
406 E1000_WRITE_FLUSH(hw);
410 igb_intr_disable(struct e1000_hw *hw)
412 E1000_WRITE_REG(hw, E1000_IMC, ~0);
413 E1000_WRITE_FLUSH(hw);
416 static inline int32_t
417 igb_pf_reset_hw(struct e1000_hw *hw)
422 status = e1000_reset_hw(hw);
424 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
425 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
426 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
427 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
428 E1000_WRITE_FLUSH(hw);
434 igb_identify_hardware(struct rte_eth_dev *dev)
436 struct e1000_hw *hw =
437 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
439 hw->vendor_id = dev->pci_dev->id.vendor_id;
440 hw->device_id = dev->pci_dev->id.device_id;
441 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
442 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
444 e1000_set_mac_type(hw);
446 /* need to check if it is a vf device below */
450 igb_reset_swfw_lock(struct e1000_hw *hw)
455 * Do mac ops initialization manually here, since we will need
456 * some function pointers set by this call.
458 ret_val = e1000_init_mac_params(hw);
463 * SMBI lock should not fail in this early stage. If this is the case,
464 * it is due to an improper exit of the application.
465 * So force the release of the faulty lock.
467 if (e1000_get_hw_semaphore_generic(hw) < 0) {
468 PMD_DRV_LOG(DEBUG, "SMBI lock released");
470 e1000_put_hw_semaphore_generic(hw);
472 if (hw->mac.ops.acquire_swfw_sync != NULL) {
476 * Phy lock should not fail in this early stage. If this is the case,
477 * it is due to an improper exit of the application.
478 * So force the release of the faulty lock.
480 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
481 if (hw->bus.func > E1000_FUNC_1)
483 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
484 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
487 hw->mac.ops.release_swfw_sync(hw, mask);
490 * This one is more tricky since it is common to all ports; but
491 * swfw_sync retries last long enough (1s) to be almost sure that if
492 * lock can not be taken it is due to an improper lock of the
495 mask = E1000_SWFW_EEP_SM;
496 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
497 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
499 hw->mac.ops.release_swfw_sync(hw, mask);
502 return E1000_SUCCESS;
506 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
509 struct rte_pci_device *pci_dev;
510 struct e1000_hw *hw =
511 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
512 struct e1000_vfta * shadow_vfta =
513 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
514 struct e1000_filter_info *filter_info =
515 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
516 struct e1000_adapter *adapter =
517 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
521 pci_dev = eth_dev->pci_dev;
522 eth_dev->dev_ops = ð_igb_ops;
523 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
524 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
526 /* for secondary processes, we don't initialise any further as primary
527 * has already done this work. Only check we don't need a different
529 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
530 if (eth_dev->data->scattered_rx)
531 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
535 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
537 igb_identify_hardware(eth_dev);
538 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
543 e1000_get_bus_info(hw);
545 /* Reset any pending lock */
546 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
551 /* Finish initialization */
552 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
558 hw->phy.autoneg_wait_to_complete = 0;
559 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
562 if (hw->phy.media_type == e1000_media_type_copper) {
563 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
564 hw->phy.disable_polarity_correction = 0;
565 hw->phy.ms_type = e1000_ms_hw_default;
569 * Start from a known state, this is important in reading the nvm
574 /* Make sure we have a good EEPROM before we read from it */
575 if (e1000_validate_nvm_checksum(hw) < 0) {
577 * Some PCI-E parts fail the first check due to
578 * the link being in sleep state, call it again,
579 * if it fails a second time its a real issue.
581 if (e1000_validate_nvm_checksum(hw) < 0) {
582 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
588 /* Read the permanent MAC address out of the EEPROM */
589 if (e1000_read_mac_addr(hw) != 0) {
590 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
595 /* Allocate memory for storing MAC addresses */
596 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
597 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
598 if (eth_dev->data->mac_addrs == NULL) {
599 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
600 "store MAC addresses",
601 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
606 /* Copy the permanent MAC address */
607 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
609 /* initialize the vfta */
610 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
612 /* Now initialize the hardware */
613 if (igb_hardware_init(hw) != 0) {
614 PMD_INIT_LOG(ERR, "Hardware initialization failed");
615 rte_free(eth_dev->data->mac_addrs);
616 eth_dev->data->mac_addrs = NULL;
620 hw->mac.get_link_status = 1;
621 adapter->stopped = 0;
623 /* Indicate SOL/IDER usage */
624 if (e1000_check_reset_block(hw) < 0) {
625 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
629 /* initialize PF if max_vfs not zero */
630 igb_pf_host_init(eth_dev);
632 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
633 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
634 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
635 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
636 E1000_WRITE_FLUSH(hw);
638 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
639 eth_dev->data->port_id, pci_dev->id.vendor_id,
640 pci_dev->id.device_id);
642 rte_intr_callback_register(&(pci_dev->intr_handle),
643 eth_igb_interrupt_handler, (void *)eth_dev);
645 /* enable uio intr after callback register */
646 rte_intr_enable(&(pci_dev->intr_handle));
648 /* enable support intr */
649 igb_intr_enable(eth_dev);
651 TAILQ_INIT(&filter_info->flex_list);
652 filter_info->flex_mask = 0;
653 TAILQ_INIT(&filter_info->twotuple_list);
654 filter_info->twotuple_mask = 0;
655 TAILQ_INIT(&filter_info->fivetuple_list);
656 filter_info->fivetuple_mask = 0;
661 igb_hw_control_release(hw);
667 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
669 struct rte_pci_device *pci_dev;
671 struct e1000_adapter *adapter =
672 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
674 PMD_INIT_FUNC_TRACE();
676 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
679 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
680 pci_dev = eth_dev->pci_dev;
682 if (adapter->stopped == 0)
683 eth_igb_close(eth_dev);
685 eth_dev->dev_ops = NULL;
686 eth_dev->rx_pkt_burst = NULL;
687 eth_dev->tx_pkt_burst = NULL;
689 /* Reset any pending lock */
690 igb_reset_swfw_lock(hw);
692 rte_free(eth_dev->data->mac_addrs);
693 eth_dev->data->mac_addrs = NULL;
695 /* uninitialize PF if max_vfs not zero */
696 igb_pf_host_uninit(eth_dev);
698 /* disable uio intr before callback unregister */
699 rte_intr_disable(&(pci_dev->intr_handle));
700 rte_intr_callback_unregister(&(pci_dev->intr_handle),
701 eth_igb_interrupt_handler, (void *)eth_dev);
707 * Virtual Function device init
710 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
712 struct rte_pci_device *pci_dev;
713 struct e1000_adapter *adapter =
714 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
715 struct e1000_hw *hw =
716 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
719 PMD_INIT_FUNC_TRACE();
721 eth_dev->dev_ops = &igbvf_eth_dev_ops;
722 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
723 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
725 /* for secondary processes, we don't initialise any further as primary
726 * has already done this work. Only check we don't need a different
728 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
729 if (eth_dev->data->scattered_rx)
730 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
734 pci_dev = eth_dev->pci_dev;
736 hw->device_id = pci_dev->id.device_id;
737 hw->vendor_id = pci_dev->id.vendor_id;
738 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
739 adapter->stopped = 0;
741 /* Initialize the shared code (base driver) */
742 diag = e1000_setup_init_funcs(hw, TRUE);
744 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
749 /* init_mailbox_params */
750 hw->mbx.ops.init_params(hw);
752 /* Disable the interrupts for VF */
753 igbvf_intr_disable(hw);
755 diag = hw->mac.ops.reset_hw(hw);
757 /* Allocate memory for storing MAC addresses */
758 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
759 hw->mac.rar_entry_count, 0);
760 if (eth_dev->data->mac_addrs == NULL) {
762 "Failed to allocate %d bytes needed to store MAC "
764 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
768 /* Copy the permanent MAC address */
769 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
770 ð_dev->data->mac_addrs[0]);
772 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
774 eth_dev->data->port_id, pci_dev->id.vendor_id,
775 pci_dev->id.device_id, "igb_mac_82576_vf");
781 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
783 struct e1000_adapter *adapter =
784 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
786 PMD_INIT_FUNC_TRACE();
788 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
791 if (adapter->stopped == 0)
792 igbvf_dev_close(eth_dev);
794 eth_dev->dev_ops = NULL;
795 eth_dev->rx_pkt_burst = NULL;
796 eth_dev->tx_pkt_burst = NULL;
798 rte_free(eth_dev->data->mac_addrs);
799 eth_dev->data->mac_addrs = NULL;
804 static struct eth_driver rte_igb_pmd = {
806 .name = "rte_igb_pmd",
807 .id_table = pci_id_igb_map,
808 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
809 RTE_PCI_DRV_DETACHABLE,
811 .eth_dev_init = eth_igb_dev_init,
812 .eth_dev_uninit = eth_igb_dev_uninit,
813 .dev_private_size = sizeof(struct e1000_adapter),
817 * virtual function driver struct
819 static struct eth_driver rte_igbvf_pmd = {
821 .name = "rte_igbvf_pmd",
822 .id_table = pci_id_igbvf_map,
823 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
825 .eth_dev_init = eth_igbvf_dev_init,
826 .eth_dev_uninit = eth_igbvf_dev_uninit,
827 .dev_private_size = sizeof(struct e1000_adapter),
831 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
833 rte_eth_driver_register(&rte_igb_pmd);
838 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
840 struct e1000_hw *hw =
841 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
842 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
843 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
844 rctl |= E1000_RCTL_VFE;
845 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
849 * VF Driver initialization routine.
850 * Invoked one at EAL init time.
851 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
854 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
856 PMD_INIT_FUNC_TRACE();
858 rte_eth_driver_register(&rte_igbvf_pmd);
863 eth_igb_configure(struct rte_eth_dev *dev)
865 struct e1000_interrupt *intr =
866 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
868 PMD_INIT_FUNC_TRACE();
869 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
870 PMD_INIT_FUNC_TRACE();
876 eth_igb_start(struct rte_eth_dev *dev)
878 struct e1000_hw *hw =
879 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
880 struct e1000_adapter *adapter =
881 E1000_DEV_PRIVATE(dev->data->dev_private);
885 PMD_INIT_FUNC_TRACE();
887 /* Power up the phy. Needed to make the link go Up */
888 e1000_power_up_phy(hw);
891 * Packet Buffer Allocation (PBA)
892 * Writing PBA sets the receive portion of the buffer
893 * the remainder is used for the transmit buffer.
895 if (hw->mac.type == e1000_82575) {
898 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
899 E1000_WRITE_REG(hw, E1000_PBA, pba);
902 /* Put the address into the Receive Address Array */
903 e1000_rar_set(hw, hw->mac.addr, 0);
905 /* Initialize the hardware */
906 if (igb_hardware_init(hw)) {
907 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
910 adapter->stopped = 0;
912 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
914 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
915 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
916 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
917 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
918 E1000_WRITE_FLUSH(hw);
920 /* configure PF module if SRIOV enabled */
921 igb_pf_host_configure(dev);
923 /* Configure for OS presence */
924 igb_init_manageability(hw);
926 eth_igb_tx_init(dev);
928 /* This can fail when allocating mbufs for descriptor rings */
929 ret = eth_igb_rx_init(dev);
931 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
932 igb_dev_clear_queues(dev);
936 e1000_clear_hw_cntrs_base_generic(hw);
939 * VLAN Offload Settings
941 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
942 ETH_VLAN_EXTEND_MASK;
943 eth_igb_vlan_offload_set(dev, mask);
945 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
946 /* Enable VLAN filter since VMDq always use VLAN filter */
947 igb_vmdq_vlan_hw_filter_enable(dev);
951 * Configure the Interrupt Moderation register (EITR) with the maximum
952 * possible value (0xFFFF) to minimize "System Partial Write" issued by
953 * spurious [DMA] memory updates of RX and TX ring descriptors.
955 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
956 * spurious memory updates per second should be expected.
957 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
959 * Because interrupts are not used at all, the MSI-X is not activated
960 * and interrupt moderation is controlled by EITR[0].
962 * Note that having [almost] disabled memory updates of RX and TX ring
963 * descriptors through the Interrupt Moderation mechanism, memory
964 * updates of ring descriptors are now moderated by the configurable
965 * value of Write-Back Threshold registers.
967 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
968 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
969 (hw->mac.type == e1000_i211)) {
972 /* Enable all RX & TX queues in the IVAR registers */
973 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
974 for (i = 0; i < 8; i++)
975 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
977 /* Configure EITR with the maximum possible value (0xFFFF) */
978 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
981 /* Setup link speed and duplex */
982 switch (dev->data->dev_conf.link_speed) {
983 case ETH_LINK_SPEED_AUTONEG:
984 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
985 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
986 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
987 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
988 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
989 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
991 goto error_invalid_config;
993 case ETH_LINK_SPEED_10:
994 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
995 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
996 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
997 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
998 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
999 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1001 goto error_invalid_config;
1003 case ETH_LINK_SPEED_100:
1004 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1005 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1006 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1007 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1008 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1009 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1011 goto error_invalid_config;
1013 case ETH_LINK_SPEED_1000:
1014 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1015 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1016 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1018 goto error_invalid_config;
1020 case ETH_LINK_SPEED_10000:
1022 goto error_invalid_config;
1024 e1000_setup_link(hw);
1026 /* check if lsc interrupt feature is enabled */
1027 if (dev->data->dev_conf.intr_conf.lsc != 0)
1028 ret = eth_igb_lsc_interrupt_setup(dev);
1030 /* resume enabled intr since hw reset */
1031 igb_intr_enable(dev);
1033 PMD_INIT_LOG(DEBUG, "<<");
1037 error_invalid_config:
1038 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1039 dev->data->dev_conf.link_speed,
1040 dev->data->dev_conf.link_duplex, dev->data->port_id);
1041 igb_dev_clear_queues(dev);
1045 /*********************************************************************
1047 * This routine disables all traffic on the adapter by issuing a
1048 * global reset on the MAC.
1050 **********************************************************************/
1052 eth_igb_stop(struct rte_eth_dev *dev)
1054 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1055 struct e1000_filter_info *filter_info =
1056 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1057 struct rte_eth_link link;
1058 struct e1000_flex_filter *p_flex;
1059 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1060 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1062 igb_intr_disable(hw);
1063 igb_pf_reset_hw(hw);
1064 E1000_WRITE_REG(hw, E1000_WUC, 0);
1066 /* Set bit for Go Link disconnect */
1067 if (hw->mac.type >= e1000_82580) {
1070 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1071 phpm_reg |= E1000_82580_PM_GO_LINKD;
1072 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1075 /* Power down the phy. Needed to make the link go Down */
1076 if (hw->phy.media_type == e1000_media_type_copper)
1077 e1000_power_down_phy(hw);
1079 e1000_shutdown_fiber_serdes_link(hw);
1081 igb_dev_clear_queues(dev);
1083 /* clear the recorded link status */
1084 memset(&link, 0, sizeof(link));
1085 rte_igb_dev_atomic_write_link_status(dev, &link);
1087 /* Remove all flex filters of the device */
1088 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1089 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1092 filter_info->flex_mask = 0;
1094 /* Remove all ntuple filters of the device */
1095 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1096 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1097 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1098 TAILQ_REMOVE(&filter_info->fivetuple_list,
1102 filter_info->fivetuple_mask = 0;
1103 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1104 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1105 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1106 TAILQ_REMOVE(&filter_info->twotuple_list,
1110 filter_info->twotuple_mask = 0;
1114 eth_igb_close(struct rte_eth_dev *dev)
1116 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1117 struct e1000_adapter *adapter =
1118 E1000_DEV_PRIVATE(dev->data->dev_private);
1119 struct rte_eth_link link;
1122 adapter->stopped = 1;
1124 e1000_phy_hw_reset(hw);
1125 igb_release_manageability(hw);
1126 igb_hw_control_release(hw);
1128 /* Clear bit for Go Link disconnect */
1129 if (hw->mac.type >= e1000_82580) {
1132 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1133 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1134 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1137 igb_dev_free_queues(dev);
1139 memset(&link, 0, sizeof(link));
1140 rte_igb_dev_atomic_write_link_status(dev, &link);
1144 igb_get_rx_buffer_size(struct e1000_hw *hw)
1146 uint32_t rx_buf_size;
1147 if (hw->mac.type == e1000_82576) {
1148 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1149 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1150 /* PBS needs to be translated according to a lookup table */
1151 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1152 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1153 rx_buf_size = (rx_buf_size << 10);
1154 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1155 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1157 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1163 /*********************************************************************
1165 * Initialize the hardware
1167 **********************************************************************/
1169 igb_hardware_init(struct e1000_hw *hw)
1171 uint32_t rx_buf_size;
1174 /* Let the firmware know the OS is in control */
1175 igb_hw_control_acquire(hw);
1178 * These parameters control the automatic generation (Tx) and
1179 * response (Rx) to Ethernet PAUSE frames.
1180 * - High water mark should allow for at least two standard size (1518)
1181 * frames to be received after sending an XOFF.
1182 * - Low water mark works best when it is very near the high water mark.
1183 * This allows the receiver to restart by sending XON when it has
1184 * drained a bit. Here we use an arbitrary value of 1500 which will
1185 * restart after one full frame is pulled from the buffer. There
1186 * could be several smaller frames in the buffer and if so they will
1187 * not trigger the XON until their total number reduces the buffer
1189 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1191 rx_buf_size = igb_get_rx_buffer_size(hw);
1193 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1194 hw->fc.low_water = hw->fc.high_water - 1500;
1195 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1196 hw->fc.send_xon = 1;
1198 /* Set Flow control, use the tunable location if sane */
1199 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1200 hw->fc.requested_mode = igb_fc_setting;
1202 hw->fc.requested_mode = e1000_fc_none;
1204 /* Issue a global reset */
1205 igb_pf_reset_hw(hw);
1206 E1000_WRITE_REG(hw, E1000_WUC, 0);
1208 diag = e1000_init_hw(hw);
1212 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1213 e1000_get_phy_info(hw);
1214 e1000_check_for_link(hw);
1219 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1221 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1223 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 struct e1000_hw_stats *stats =
1225 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1228 if(hw->phy.media_type == e1000_media_type_copper ||
1229 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1231 E1000_READ_REG(hw,E1000_SYMERRS);
1232 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1235 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1236 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1237 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1238 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1240 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1241 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1242 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1243 stats->dc += E1000_READ_REG(hw, E1000_DC);
1244 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1245 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1246 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1248 ** For watchdog management we need to know if we have been
1249 ** paused during the last interval, so capture that here.
1251 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1252 stats->xoffrxc += pause_frames;
1253 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1254 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1255 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1256 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1257 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1258 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1259 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1260 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1261 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1262 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1263 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1264 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1266 /* For the 64-bit byte counters the low dword must be read first. */
1267 /* Both registers clear on the read of the high dword */
1269 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1270 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1271 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1272 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1274 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1275 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1276 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1277 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1278 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1280 stats->tor += E1000_READ_REG(hw, E1000_TORH);
1281 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1283 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1284 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1285 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1286 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1287 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1288 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1289 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1290 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1291 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1292 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1294 /* Interrupt Counts */
1296 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1297 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1298 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1299 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1300 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1301 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1302 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1303 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1304 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1306 /* Host to Card Statistics */
1308 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1309 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1310 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1311 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1312 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1313 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1314 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1315 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1316 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1317 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1318 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1319 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1320 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1321 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1323 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1324 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1325 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1326 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1327 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1328 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1330 if (rte_stats == NULL)
1334 rte_stats->ibadcrc = stats->crcerrs;
1335 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1336 rte_stats->imissed = stats->mpc;
1337 rte_stats->ierrors = rte_stats->ibadcrc +
1338 rte_stats->ibadlen +
1339 rte_stats->imissed +
1340 stats->rxerrc + stats->algnerrc + stats->cexterr;
1343 rte_stats->oerrors = stats->ecol + stats->latecol;
1345 /* XON/XOFF pause frames */
1346 rte_stats->tx_pause_xon = stats->xontxc;
1347 rte_stats->rx_pause_xon = stats->xonrxc;
1348 rte_stats->tx_pause_xoff = stats->xofftxc;
1349 rte_stats->rx_pause_xoff = stats->xoffrxc;
1351 rte_stats->ipackets = stats->gprc;
1352 rte_stats->opackets = stats->gptc;
1353 rte_stats->ibytes = stats->gorc;
1354 rte_stats->obytes = stats->gotc;
1358 eth_igb_stats_reset(struct rte_eth_dev *dev)
1360 struct e1000_hw_stats *hw_stats =
1361 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1363 /* HW registers are cleared on read */
1364 eth_igb_stats_get(dev, NULL);
1366 /* Reset software totals */
1367 memset(hw_stats, 0, sizeof(*hw_stats));
1371 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1373 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1374 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1375 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1377 /* Good Rx packets, include VF loopback */
1378 UPDATE_VF_STAT(E1000_VFGPRC,
1379 hw_stats->last_gprc, hw_stats->gprc);
1381 /* Good Rx octets, include VF loopback */
1382 UPDATE_VF_STAT(E1000_VFGORC,
1383 hw_stats->last_gorc, hw_stats->gorc);
1385 /* Good Tx packets, include VF loopback */
1386 UPDATE_VF_STAT(E1000_VFGPTC,
1387 hw_stats->last_gptc, hw_stats->gptc);
1389 /* Good Tx octets, include VF loopback */
1390 UPDATE_VF_STAT(E1000_VFGOTC,
1391 hw_stats->last_gotc, hw_stats->gotc);
1393 /* Rx Multicst packets */
1394 UPDATE_VF_STAT(E1000_VFMPRC,
1395 hw_stats->last_mprc, hw_stats->mprc);
1397 /* Good Rx loopback packets */
1398 UPDATE_VF_STAT(E1000_VFGPRLBC,
1399 hw_stats->last_gprlbc, hw_stats->gprlbc);
1401 /* Good Rx loopback octets */
1402 UPDATE_VF_STAT(E1000_VFGORLBC,
1403 hw_stats->last_gorlbc, hw_stats->gorlbc);
1405 /* Good Tx loopback packets */
1406 UPDATE_VF_STAT(E1000_VFGPTLBC,
1407 hw_stats->last_gptlbc, hw_stats->gptlbc);
1409 /* Good Tx loopback octets */
1410 UPDATE_VF_STAT(E1000_VFGOTLBC,
1411 hw_stats->last_gotlbc, hw_stats->gotlbc);
1413 if (rte_stats == NULL)
1416 rte_stats->ipackets = hw_stats->gprc;
1417 rte_stats->ibytes = hw_stats->gorc;
1418 rte_stats->opackets = hw_stats->gptc;
1419 rte_stats->obytes = hw_stats->gotc;
1420 rte_stats->imcasts = hw_stats->mprc;
1421 rte_stats->ilbpackets = hw_stats->gprlbc;
1422 rte_stats->ilbbytes = hw_stats->gorlbc;
1423 rte_stats->olbpackets = hw_stats->gptlbc;
1424 rte_stats->olbbytes = hw_stats->gotlbc;
1429 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1431 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1432 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1434 /* Sync HW register to the last stats */
1435 eth_igbvf_stats_get(dev, NULL);
1437 /* reset HW current stats*/
1438 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1439 offsetof(struct e1000_vf_stats, gprc));
1444 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1446 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1448 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1449 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1450 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1451 dev_info->rx_offload_capa =
1452 DEV_RX_OFFLOAD_VLAN_STRIP |
1453 DEV_RX_OFFLOAD_IPV4_CKSUM |
1454 DEV_RX_OFFLOAD_UDP_CKSUM |
1455 DEV_RX_OFFLOAD_TCP_CKSUM;
1456 dev_info->tx_offload_capa =
1457 DEV_TX_OFFLOAD_VLAN_INSERT |
1458 DEV_TX_OFFLOAD_IPV4_CKSUM |
1459 DEV_TX_OFFLOAD_UDP_CKSUM |
1460 DEV_TX_OFFLOAD_TCP_CKSUM |
1461 DEV_TX_OFFLOAD_SCTP_CKSUM;
1463 switch (hw->mac.type) {
1465 dev_info->max_rx_queues = 4;
1466 dev_info->max_tx_queues = 4;
1467 dev_info->max_vmdq_pools = 0;
1471 dev_info->max_rx_queues = 16;
1472 dev_info->max_tx_queues = 16;
1473 dev_info->max_vmdq_pools = ETH_8_POOLS;
1474 dev_info->vmdq_queue_num = 16;
1478 dev_info->max_rx_queues = 8;
1479 dev_info->max_tx_queues = 8;
1480 dev_info->max_vmdq_pools = ETH_8_POOLS;
1481 dev_info->vmdq_queue_num = 8;
1485 dev_info->max_rx_queues = 8;
1486 dev_info->max_tx_queues = 8;
1487 dev_info->max_vmdq_pools = ETH_8_POOLS;
1488 dev_info->vmdq_queue_num = 8;
1492 dev_info->max_rx_queues = 8;
1493 dev_info->max_tx_queues = 8;
1497 dev_info->max_rx_queues = 4;
1498 dev_info->max_tx_queues = 4;
1499 dev_info->max_vmdq_pools = 0;
1503 dev_info->max_rx_queues = 2;
1504 dev_info->max_tx_queues = 2;
1505 dev_info->max_vmdq_pools = 0;
1509 /* Should not happen */
1512 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1513 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1514 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1516 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1518 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1519 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1520 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1522 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1526 dev_info->default_txconf = (struct rte_eth_txconf) {
1528 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1529 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1530 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1537 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1539 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1541 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1542 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1543 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1544 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1545 DEV_RX_OFFLOAD_IPV4_CKSUM |
1546 DEV_RX_OFFLOAD_UDP_CKSUM |
1547 DEV_RX_OFFLOAD_TCP_CKSUM;
1548 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1549 DEV_TX_OFFLOAD_IPV4_CKSUM |
1550 DEV_TX_OFFLOAD_UDP_CKSUM |
1551 DEV_TX_OFFLOAD_TCP_CKSUM |
1552 DEV_TX_OFFLOAD_SCTP_CKSUM;
1553 switch (hw->mac.type) {
1555 dev_info->max_rx_queues = 2;
1556 dev_info->max_tx_queues = 2;
1558 case e1000_vfadapt_i350:
1559 dev_info->max_rx_queues = 1;
1560 dev_info->max_tx_queues = 1;
1563 /* Should not happen */
1567 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1569 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1570 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1571 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1573 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1577 dev_info->default_txconf = (struct rte_eth_txconf) {
1579 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1580 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1581 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1587 /* return 0 means link status changed, -1 means not changed */
1589 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1591 struct e1000_hw *hw =
1592 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1593 struct rte_eth_link link, old;
1594 int link_check, count;
1597 hw->mac.get_link_status = 1;
1599 /* possible wait-to-complete in up to 9 seconds */
1600 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1601 /* Read the real link status */
1602 switch (hw->phy.media_type) {
1603 case e1000_media_type_copper:
1604 /* Do the work to read phy */
1605 e1000_check_for_link(hw);
1606 link_check = !hw->mac.get_link_status;
1609 case e1000_media_type_fiber:
1610 e1000_check_for_link(hw);
1611 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1615 case e1000_media_type_internal_serdes:
1616 e1000_check_for_link(hw);
1617 link_check = hw->mac.serdes_has_link;
1620 /* VF device is type_unknown */
1621 case e1000_media_type_unknown:
1622 eth_igbvf_link_update(hw);
1623 link_check = !hw->mac.get_link_status;
1629 if (link_check || wait_to_complete == 0)
1631 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1633 memset(&link, 0, sizeof(link));
1634 rte_igb_dev_atomic_read_link_status(dev, &link);
1637 /* Now we check if a transition has happened */
1639 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1641 link.link_status = 1;
1642 } else if (!link_check) {
1643 link.link_speed = 0;
1644 link.link_duplex = 0;
1645 link.link_status = 0;
1647 rte_igb_dev_atomic_write_link_status(dev, &link);
1650 if (old.link_status == link.link_status)
1658 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1659 * For ASF and Pass Through versions of f/w this means
1660 * that the driver is loaded.
1663 igb_hw_control_acquire(struct e1000_hw *hw)
1667 /* Let firmware know the driver has taken over */
1668 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1669 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1673 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1674 * For ASF and Pass Through versions of f/w this means that the
1675 * driver is no longer loaded.
1678 igb_hw_control_release(struct e1000_hw *hw)
1682 /* Let firmware taken over control of h/w */
1683 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1684 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1685 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1689 * Bit of a misnomer, what this really means is
1690 * to enable OS management of the system... aka
1691 * to disable special hardware management features.
1694 igb_init_manageability(struct e1000_hw *hw)
1696 if (e1000_enable_mng_pass_thru(hw)) {
1697 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1698 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1700 /* disable hardware interception of ARP */
1701 manc &= ~(E1000_MANC_ARP_EN);
1703 /* enable receiving management packets to the host */
1704 manc |= E1000_MANC_EN_MNG2HOST;
1705 manc2h |= 1 << 5; /* Mng Port 623 */
1706 manc2h |= 1 << 6; /* Mng Port 664 */
1707 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1708 E1000_WRITE_REG(hw, E1000_MANC, manc);
1713 igb_release_manageability(struct e1000_hw *hw)
1715 if (e1000_enable_mng_pass_thru(hw)) {
1716 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1718 manc |= E1000_MANC_ARP_EN;
1719 manc &= ~E1000_MANC_EN_MNG2HOST;
1721 E1000_WRITE_REG(hw, E1000_MANC, manc);
1726 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1728 struct e1000_hw *hw =
1729 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732 rctl = E1000_READ_REG(hw, E1000_RCTL);
1733 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1734 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1738 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1740 struct e1000_hw *hw =
1741 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1744 rctl = E1000_READ_REG(hw, E1000_RCTL);
1745 rctl &= (~E1000_RCTL_UPE);
1746 if (dev->data->all_multicast == 1)
1747 rctl |= E1000_RCTL_MPE;
1749 rctl &= (~E1000_RCTL_MPE);
1750 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1754 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1756 struct e1000_hw *hw =
1757 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1760 rctl = E1000_READ_REG(hw, E1000_RCTL);
1761 rctl |= E1000_RCTL_MPE;
1762 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1766 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1768 struct e1000_hw *hw =
1769 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772 if (dev->data->promiscuous == 1)
1773 return; /* must remain in all_multicast mode */
1774 rctl = E1000_READ_REG(hw, E1000_RCTL);
1775 rctl &= (~E1000_RCTL_MPE);
1776 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1780 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1782 struct e1000_hw *hw =
1783 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784 struct e1000_vfta * shadow_vfta =
1785 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1790 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1791 E1000_VFTA_ENTRY_MASK);
1792 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1793 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1798 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1800 /* update local VFTA copy */
1801 shadow_vfta->vfta[vid_idx] = vfta;
1807 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1809 struct e1000_hw *hw =
1810 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1811 uint32_t reg = ETHER_TYPE_VLAN ;
1813 reg |= (tpid << 16);
1814 E1000_WRITE_REG(hw, E1000_VET, reg);
1818 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1820 struct e1000_hw *hw =
1821 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1824 /* Filter Table Disable */
1825 reg = E1000_READ_REG(hw, E1000_RCTL);
1826 reg &= ~E1000_RCTL_CFIEN;
1827 reg &= ~E1000_RCTL_VFE;
1828 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1832 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1834 struct e1000_hw *hw =
1835 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836 struct e1000_vfta * shadow_vfta =
1837 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1841 /* Filter Table Enable, CFI not used for packet acceptance */
1842 reg = E1000_READ_REG(hw, E1000_RCTL);
1843 reg &= ~E1000_RCTL_CFIEN;
1844 reg |= E1000_RCTL_VFE;
1845 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1847 /* restore VFTA table */
1848 for (i = 0; i < IGB_VFTA_SIZE; i++)
1849 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1853 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1855 struct e1000_hw *hw =
1856 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859 /* VLAN Mode Disable */
1860 reg = E1000_READ_REG(hw, E1000_CTRL);
1861 reg &= ~E1000_CTRL_VME;
1862 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1866 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1868 struct e1000_hw *hw =
1869 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872 /* VLAN Mode Enable */
1873 reg = E1000_READ_REG(hw, E1000_CTRL);
1874 reg |= E1000_CTRL_VME;
1875 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1879 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1881 struct e1000_hw *hw =
1882 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885 /* CTRL_EXT: Extended VLAN */
1886 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1887 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1888 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1890 /* Update maximum packet length */
1891 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1892 E1000_WRITE_REG(hw, E1000_RLPML,
1893 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1898 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1900 struct e1000_hw *hw =
1901 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904 /* CTRL_EXT: Extended VLAN */
1905 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1906 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1907 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1909 /* Update maximum packet length */
1910 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1911 E1000_WRITE_REG(hw, E1000_RLPML,
1912 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1917 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1919 if(mask & ETH_VLAN_STRIP_MASK){
1920 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1921 igb_vlan_hw_strip_enable(dev);
1923 igb_vlan_hw_strip_disable(dev);
1926 if(mask & ETH_VLAN_FILTER_MASK){
1927 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1928 igb_vlan_hw_filter_enable(dev);
1930 igb_vlan_hw_filter_disable(dev);
1933 if(mask & ETH_VLAN_EXTEND_MASK){
1934 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1935 igb_vlan_hw_extend_enable(dev);
1937 igb_vlan_hw_extend_disable(dev);
1943 * It enables the interrupt mask and then enable the interrupt.
1946 * Pointer to struct rte_eth_dev.
1949 * - On success, zero.
1950 * - On failure, a negative value.
1953 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1955 struct e1000_interrupt *intr =
1956 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1958 intr->mask |= E1000_ICR_LSC;
1964 * It reads ICR and gets interrupt causes, check it and set a bit flag
1965 * to update link status.
1968 * Pointer to struct rte_eth_dev.
1971 * - On success, zero.
1972 * - On failure, a negative value.
1975 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1978 struct e1000_hw *hw =
1979 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1980 struct e1000_interrupt *intr =
1981 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1983 igb_intr_disable(hw);
1985 /* read-on-clear nic registers here */
1986 icr = E1000_READ_REG(hw, E1000_ICR);
1989 if (icr & E1000_ICR_LSC) {
1990 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1993 if (icr & E1000_ICR_VMMB)
1994 intr->flags |= E1000_FLAG_MAILBOX;
2000 * It executes link_update after knowing an interrupt is prsent.
2003 * Pointer to struct rte_eth_dev.
2006 * - On success, zero.
2007 * - On failure, a negative value.
2010 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2012 struct e1000_hw *hw =
2013 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014 struct e1000_interrupt *intr =
2015 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2016 uint32_t tctl, rctl;
2017 struct rte_eth_link link;
2020 if (intr->flags & E1000_FLAG_MAILBOX) {
2021 igb_pf_mbx_process(dev);
2022 intr->flags &= ~E1000_FLAG_MAILBOX;
2025 igb_intr_enable(dev);
2026 rte_intr_enable(&(dev->pci_dev->intr_handle));
2028 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2029 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2031 /* set get_link_status to check register later */
2032 hw->mac.get_link_status = 1;
2033 ret = eth_igb_link_update(dev, 0);
2035 /* check if link has changed */
2039 memset(&link, 0, sizeof(link));
2040 rte_igb_dev_atomic_read_link_status(dev, &link);
2041 if (link.link_status) {
2043 " Port %d: Link Up - speed %u Mbps - %s",
2045 (unsigned)link.link_speed,
2046 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2047 "full-duplex" : "half-duplex");
2049 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2050 dev->data->port_id);
2052 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2053 dev->pci_dev->addr.domain,
2054 dev->pci_dev->addr.bus,
2055 dev->pci_dev->addr.devid,
2056 dev->pci_dev->addr.function);
2057 tctl = E1000_READ_REG(hw, E1000_TCTL);
2058 rctl = E1000_READ_REG(hw, E1000_RCTL);
2059 if (link.link_status) {
2061 tctl |= E1000_TCTL_EN;
2062 rctl |= E1000_RCTL_EN;
2065 tctl &= ~E1000_TCTL_EN;
2066 rctl &= ~E1000_RCTL_EN;
2068 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2069 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2070 E1000_WRITE_FLUSH(hw);
2071 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2078 * Interrupt handler which shall be registered at first.
2081 * Pointer to interrupt handle.
2083 * The address of parameter (struct rte_eth_dev *) regsitered before.
2089 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2092 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2094 eth_igb_interrupt_get_status(dev);
2095 eth_igb_interrupt_action(dev);
2099 eth_igb_led_on(struct rte_eth_dev *dev)
2101 struct e1000_hw *hw;
2103 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2104 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2108 eth_igb_led_off(struct rte_eth_dev *dev)
2110 struct e1000_hw *hw;
2112 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2117 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2119 struct e1000_hw *hw;
2124 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125 fc_conf->pause_time = hw->fc.pause_time;
2126 fc_conf->high_water = hw->fc.high_water;
2127 fc_conf->low_water = hw->fc.low_water;
2128 fc_conf->send_xon = hw->fc.send_xon;
2129 fc_conf->autoneg = hw->mac.autoneg;
2132 * Return rx_pause and tx_pause status according to actual setting of
2133 * the TFCE and RFCE bits in the CTRL register.
2135 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2136 if (ctrl & E1000_CTRL_TFCE)
2141 if (ctrl & E1000_CTRL_RFCE)
2146 if (rx_pause && tx_pause)
2147 fc_conf->mode = RTE_FC_FULL;
2149 fc_conf->mode = RTE_FC_RX_PAUSE;
2151 fc_conf->mode = RTE_FC_TX_PAUSE;
2153 fc_conf->mode = RTE_FC_NONE;
2159 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2161 struct e1000_hw *hw;
2163 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2169 uint32_t rx_buf_size;
2170 uint32_t max_high_water;
2173 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174 if (fc_conf->autoneg != hw->mac.autoneg)
2176 rx_buf_size = igb_get_rx_buffer_size(hw);
2177 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2179 /* At least reserve one Ethernet frame for watermark */
2180 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2181 if ((fc_conf->high_water > max_high_water) ||
2182 (fc_conf->high_water < fc_conf->low_water)) {
2183 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2184 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2188 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2189 hw->fc.pause_time = fc_conf->pause_time;
2190 hw->fc.high_water = fc_conf->high_water;
2191 hw->fc.low_water = fc_conf->low_water;
2192 hw->fc.send_xon = fc_conf->send_xon;
2194 err = e1000_setup_link_generic(hw);
2195 if (err == E1000_SUCCESS) {
2197 /* check if we want to forward MAC frames - driver doesn't have native
2198 * capability to do that, so we'll write the registers ourselves */
2200 rctl = E1000_READ_REG(hw, E1000_RCTL);
2202 /* set or clear MFLCN.PMCF bit depending on configuration */
2203 if (fc_conf->mac_ctrl_frame_fwd != 0)
2204 rctl |= E1000_RCTL_PMCF;
2206 rctl &= ~E1000_RCTL_PMCF;
2208 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2209 E1000_WRITE_FLUSH(hw);
2214 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2218 #define E1000_RAH_POOLSEL_SHIFT (18)
2220 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2221 uint32_t index, __rte_unused uint32_t pool)
2223 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2226 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2227 rah = E1000_READ_REG(hw, E1000_RAH(index));
2228 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2229 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2233 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2235 uint8_t addr[ETHER_ADDR_LEN];
2236 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238 memset(addr, 0, sizeof(addr));
2240 e1000_rar_set(hw, addr, index);
2244 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2245 struct ether_addr *addr)
2247 eth_igb_rar_clear(dev, 0);
2249 eth_igb_rar_set(dev, (void *)addr, 0, 0);
2252 * Virtual Function operations
2255 igbvf_intr_disable(struct e1000_hw *hw)
2257 PMD_INIT_FUNC_TRACE();
2259 /* Clear interrupt mask to stop from interrupts being generated */
2260 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2262 E1000_WRITE_FLUSH(hw);
2266 igbvf_stop_adapter(struct rte_eth_dev *dev)
2270 struct rte_eth_dev_info dev_info;
2271 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2273 memset(&dev_info, 0, sizeof(dev_info));
2274 eth_igbvf_infos_get(dev, &dev_info);
2276 /* Clear interrupt mask to stop from interrupts being generated */
2277 igbvf_intr_disable(hw);
2279 /* Clear any pending interrupts, flush previous writes */
2280 E1000_READ_REG(hw, E1000_EICR);
2282 /* Disable the transmit unit. Each queue must be disabled. */
2283 for (i = 0; i < dev_info.max_tx_queues; i++)
2284 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2286 /* Disable the receive unit by stopping each queue */
2287 for (i = 0; i < dev_info.max_rx_queues; i++) {
2288 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2289 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2290 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2291 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2295 /* flush all queues disables */
2296 E1000_WRITE_FLUSH(hw);
2300 static int eth_igbvf_link_update(struct e1000_hw *hw)
2302 struct e1000_mbx_info *mbx = &hw->mbx;
2303 struct e1000_mac_info *mac = &hw->mac;
2304 int ret_val = E1000_SUCCESS;
2306 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2309 * We only want to run this if there has been a rst asserted.
2310 * in this case that could mean a link change, device reset,
2311 * or a virtual function reset
2314 /* If we were hit with a reset or timeout drop the link */
2315 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2316 mac->get_link_status = TRUE;
2318 if (!mac->get_link_status)
2321 /* if link status is down no point in checking to see if pf is up */
2322 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2325 /* if we passed all the tests above then the link is up and we no
2326 * longer need to check for link */
2327 mac->get_link_status = FALSE;
2335 igbvf_dev_configure(struct rte_eth_dev *dev)
2337 struct rte_eth_conf* conf = &dev->data->dev_conf;
2339 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2340 dev->data->port_id);
2343 * VF has no ability to enable/disable HW CRC
2344 * Keep the persistent behavior the same as Host PF
2346 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2347 if (!conf->rxmode.hw_strip_crc) {
2348 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2349 conf->rxmode.hw_strip_crc = 1;
2352 if (conf->rxmode.hw_strip_crc) {
2353 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2354 conf->rxmode.hw_strip_crc = 0;
2362 igbvf_dev_start(struct rte_eth_dev *dev)
2364 struct e1000_hw *hw =
2365 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366 struct e1000_adapter *adapter =
2367 E1000_DEV_PRIVATE(dev->data->dev_private);
2370 PMD_INIT_FUNC_TRACE();
2372 hw->mac.ops.reset_hw(hw);
2373 adapter->stopped = 0;
2376 igbvf_set_vfta_all(dev,1);
2378 eth_igbvf_tx_init(dev);
2380 /* This can fail when allocating mbufs for descriptor rings */
2381 ret = eth_igbvf_rx_init(dev);
2383 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2384 igb_dev_clear_queues(dev);
2392 igbvf_dev_stop(struct rte_eth_dev *dev)
2394 PMD_INIT_FUNC_TRACE();
2396 igbvf_stop_adapter(dev);
2399 * Clear what we set, but we still keep shadow_vfta to
2400 * restore after device starts
2402 igbvf_set_vfta_all(dev,0);
2404 igb_dev_clear_queues(dev);
2408 igbvf_dev_close(struct rte_eth_dev *dev)
2410 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411 struct e1000_adapter *adapter =
2412 E1000_DEV_PRIVATE(dev->data->dev_private);
2414 PMD_INIT_FUNC_TRACE();
2418 igbvf_dev_stop(dev);
2419 adapter->stopped = 1;
2420 igb_dev_free_queues(dev);
2423 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2425 struct e1000_mbx_info *mbx = &hw->mbx;
2428 /* After set vlan, vlan strip will also be enabled in igb driver*/
2429 msgbuf[0] = E1000_VF_SET_VLAN;
2431 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2433 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2435 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2438 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2440 struct e1000_hw *hw =
2441 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442 struct e1000_vfta * shadow_vfta =
2443 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2444 int i = 0, j = 0, vfta = 0, mask = 1;
2446 for (i = 0; i < IGB_VFTA_SIZE; i++){
2447 vfta = shadow_vfta->vfta[i];
2450 for (j = 0; j < 32; j++){
2453 (uint16_t)((i<<5)+j), on);
2462 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2464 struct e1000_hw *hw =
2465 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466 struct e1000_vfta * shadow_vfta =
2467 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2468 uint32_t vid_idx = 0;
2469 uint32_t vid_bit = 0;
2472 PMD_INIT_FUNC_TRACE();
2474 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2475 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2477 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2480 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2481 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2483 /*Save what we set and retore it after device reset*/
2485 shadow_vfta->vfta[vid_idx] |= vid_bit;
2487 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2493 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2495 struct e1000_hw *hw =
2496 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498 /* index is not used by rar_set() */
2499 hw->mac.ops.rar_set(hw, (void *)addr, 0);
2504 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2505 struct rte_eth_rss_reta_entry64 *reta_conf,
2510 uint16_t idx, shift;
2511 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2514 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2515 "(%d) doesn't match the number hardware can supported "
2516 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2520 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2521 idx = i / RTE_RETA_GROUP_SIZE;
2522 shift = i % RTE_RETA_GROUP_SIZE;
2523 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2527 if (mask == IGB_4_BIT_MASK)
2530 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2531 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2532 if (mask & (0x1 << j))
2533 reta |= reta_conf[idx].reta[shift + j] <<
2536 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2538 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2545 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2546 struct rte_eth_rss_reta_entry64 *reta_conf,
2551 uint16_t idx, shift;
2552 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2554 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2555 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2556 "(%d) doesn't match the number hardware can supported "
2557 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2561 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2562 idx = i / RTE_RETA_GROUP_SIZE;
2563 shift = i % RTE_RETA_GROUP_SIZE;
2564 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2568 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2569 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2570 if (mask & (0x1 << j))
2571 reta_conf[idx].reta[shift + j] =
2572 ((reta >> (CHAR_BIT * j)) &
2580 #define MAC_TYPE_FILTER_SUP(type) do {\
2581 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2582 (type) != e1000_82576)\
2587 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2588 struct rte_eth_syn_filter *filter,
2591 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2592 uint32_t synqf, rfctl;
2594 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2597 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2600 if (synqf & E1000_SYN_FILTER_ENABLE)
2603 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2604 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2606 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2607 if (filter->hig_pri)
2608 rfctl |= E1000_RFCTL_SYNQFP;
2610 rfctl &= ~E1000_RFCTL_SYNQFP;
2612 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2614 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2619 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2620 E1000_WRITE_FLUSH(hw);
2625 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2626 struct rte_eth_syn_filter *filter)
2628 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629 uint32_t synqf, rfctl;
2631 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2632 if (synqf & E1000_SYN_FILTER_ENABLE) {
2633 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2634 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2635 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2636 E1000_SYN_FILTER_QUEUE_SHIFT);
2644 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2645 enum rte_filter_op filter_op,
2648 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2651 MAC_TYPE_FILTER_SUP(hw->mac.type);
2653 if (filter_op == RTE_ETH_FILTER_NOP)
2657 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2662 switch (filter_op) {
2663 case RTE_ETH_FILTER_ADD:
2664 ret = eth_igb_syn_filter_set(dev,
2665 (struct rte_eth_syn_filter *)arg,
2668 case RTE_ETH_FILTER_DELETE:
2669 ret = eth_igb_syn_filter_set(dev,
2670 (struct rte_eth_syn_filter *)arg,
2673 case RTE_ETH_FILTER_GET:
2674 ret = eth_igb_syn_filter_get(dev,
2675 (struct rte_eth_syn_filter *)arg);
2678 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2686 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
2687 if ((type) != e1000_82580 && (type) != e1000_i350)\
2691 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2693 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2694 struct e1000_2tuple_filter_info *filter_info)
2696 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2698 if (filter->priority > E1000_2TUPLE_MAX_PRI)
2699 return -EINVAL; /* filter index is out of range. */
2700 if (filter->tcp_flags > TCP_FLAG_ALL)
2701 return -EINVAL; /* flags is invalid. */
2703 switch (filter->dst_port_mask) {
2705 filter_info->dst_port_mask = 0;
2706 filter_info->dst_port = filter->dst_port;
2709 filter_info->dst_port_mask = 1;
2712 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2716 switch (filter->proto_mask) {
2718 filter_info->proto_mask = 0;
2719 filter_info->proto = filter->proto;
2722 filter_info->proto_mask = 1;
2725 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2729 filter_info->priority = (uint8_t)filter->priority;
2730 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
2731 filter_info->tcp_flags = filter->tcp_flags;
2733 filter_info->tcp_flags = 0;
2738 static inline struct e1000_2tuple_filter *
2739 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
2740 struct e1000_2tuple_filter_info *key)
2742 struct e1000_2tuple_filter *it;
2744 TAILQ_FOREACH(it, filter_list, entries) {
2745 if (memcmp(key, &it->filter_info,
2746 sizeof(struct e1000_2tuple_filter_info)) == 0) {
2754 * igb_add_2tuple_filter - add a 2tuple filter
2757 * dev: Pointer to struct rte_eth_dev.
2758 * ntuple_filter: ponter to the filter that will be added.
2761 * - On success, zero.
2762 * - On failure, a negative value.
2765 igb_add_2tuple_filter(struct rte_eth_dev *dev,
2766 struct rte_eth_ntuple_filter *ntuple_filter)
2768 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2769 struct e1000_filter_info *filter_info =
2770 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2771 struct e1000_2tuple_filter *filter;
2772 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
2773 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
2776 filter = rte_zmalloc("e1000_2tuple_filter",
2777 sizeof(struct e1000_2tuple_filter), 0);
2781 ret = ntuple_filter_to_2tuple(ntuple_filter,
2782 &filter->filter_info);
2787 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2788 &filter->filter_info) != NULL) {
2789 PMD_DRV_LOG(ERR, "filter exists.");
2793 filter->queue = ntuple_filter->queue;
2796 * look for an unused 2tuple filter index,
2797 * and insert the filter to list.
2799 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
2800 if (!(filter_info->twotuple_mask & (1 << i))) {
2801 filter_info->twotuple_mask |= 1 << i;
2803 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
2809 if (i >= E1000_MAX_TTQF_FILTERS) {
2810 PMD_DRV_LOG(ERR, "2tuple filters are full.");
2815 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
2816 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
2817 imir |= E1000_IMIR_PORT_BP;
2819 imir &= ~E1000_IMIR_PORT_BP;
2821 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
2823 ttqf |= E1000_TTQF_QUEUE_ENABLE;
2824 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
2825 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
2826 if (filter->filter_info.proto_mask == 0)
2827 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2829 /* tcp flags bits setting. */
2830 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
2831 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
2832 imir_ext |= E1000_IMIREXT_CTRL_URG;
2833 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
2834 imir_ext |= E1000_IMIREXT_CTRL_ACK;
2835 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
2836 imir_ext |= E1000_IMIREXT_CTRL_PSH;
2837 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
2838 imir_ext |= E1000_IMIREXT_CTRL_RST;
2839 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
2840 imir_ext |= E1000_IMIREXT_CTRL_SYN;
2841 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
2842 imir_ext |= E1000_IMIREXT_CTRL_FIN;
2844 imir_ext |= E1000_IMIREXT_CTRL_BP;
2845 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
2846 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
2847 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
2852 * igb_remove_2tuple_filter - remove a 2tuple filter
2855 * dev: Pointer to struct rte_eth_dev.
2856 * ntuple_filter: ponter to the filter that will be removed.
2859 * - On success, zero.
2860 * - On failure, a negative value.
2863 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2864 struct rte_eth_ntuple_filter *ntuple_filter)
2866 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2867 struct e1000_filter_info *filter_info =
2868 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2869 struct e1000_2tuple_filter_info filter_2tuple;
2870 struct e1000_2tuple_filter *filter;
2873 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
2874 ret = ntuple_filter_to_2tuple(ntuple_filter,
2879 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2881 if (filter == NULL) {
2882 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2886 filter_info->twotuple_mask &= ~(1 << filter->index);
2887 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
2890 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
2891 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
2892 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
2896 static inline struct e1000_flex_filter *
2897 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
2898 struct e1000_flex_filter_info *key)
2900 struct e1000_flex_filter *it;
2902 TAILQ_FOREACH(it, filter_list, entries) {
2903 if (memcmp(key, &it->filter_info,
2904 sizeof(struct e1000_flex_filter_info)) == 0)
2912 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
2913 struct rte_eth_flex_filter *filter,
2916 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2917 struct e1000_filter_info *filter_info =
2918 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2919 struct e1000_flex_filter *flex_filter, *it;
2920 uint32_t wufc, queueing, mask;
2922 uint8_t shift, i, j = 0;
2924 flex_filter = rte_zmalloc("e1000_flex_filter",
2925 sizeof(struct e1000_flex_filter), 0);
2926 if (flex_filter == NULL)
2929 flex_filter->filter_info.len = filter->len;
2930 flex_filter->filter_info.priority = filter->priority;
2931 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
2932 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
2934 /* reverse bits in flex filter's mask*/
2935 for (shift = 0; shift < CHAR_BIT; shift++) {
2936 if (filter->mask[i] & (0x01 << shift))
2937 mask |= (0x80 >> shift);
2939 flex_filter->filter_info.mask[i] = mask;
2942 wufc = E1000_READ_REG(hw, E1000_WUFC);
2943 if (flex_filter->index < E1000_MAX_FHFT)
2944 reg_off = E1000_FHFT(flex_filter->index);
2946 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
2949 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
2950 &flex_filter->filter_info) != NULL) {
2951 PMD_DRV_LOG(ERR, "filter exists.");
2952 rte_free(flex_filter);
2955 flex_filter->queue = filter->queue;
2957 * look for an unused flex filter index
2958 * and insert the filter into the list.
2960 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
2961 if (!(filter_info->flex_mask & (1 << i))) {
2962 filter_info->flex_mask |= 1 << i;
2963 flex_filter->index = i;
2964 TAILQ_INSERT_TAIL(&filter_info->flex_list,
2970 if (i >= E1000_MAX_FLEX_FILTERS) {
2971 PMD_DRV_LOG(ERR, "flex filters are full.");
2972 rte_free(flex_filter);
2976 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
2977 (E1000_WUFC_FLX0 << flex_filter->index));
2978 queueing = filter->len |
2979 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2980 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2981 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
2983 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
2984 E1000_WRITE_REG(hw, reg_off,
2985 flex_filter->filter_info.dwords[j]);
2986 reg_off += sizeof(uint32_t);
2987 E1000_WRITE_REG(hw, reg_off,
2988 flex_filter->filter_info.dwords[++j]);
2989 reg_off += sizeof(uint32_t);
2990 E1000_WRITE_REG(hw, reg_off,
2991 (uint32_t)flex_filter->filter_info.mask[i]);
2992 reg_off += sizeof(uint32_t) * 2;
2996 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2997 &flex_filter->filter_info);
2999 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3000 rte_free(flex_filter);
3004 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3005 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3006 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3007 (~(E1000_WUFC_FLX0 << it->index)));
3009 filter_info->flex_mask &= ~(1 << it->index);
3010 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3012 rte_free(flex_filter);
3019 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3020 struct rte_eth_flex_filter *filter)
3022 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023 struct e1000_filter_info *filter_info =
3024 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3025 struct e1000_flex_filter flex_filter, *it;
3026 uint32_t wufc, queueing, wufc_en = 0;
3028 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3029 flex_filter.filter_info.len = filter->len;
3030 flex_filter.filter_info.priority = filter->priority;
3031 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3032 memcpy(flex_filter.filter_info.mask, filter->mask,
3033 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3035 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3036 &flex_filter.filter_info);
3038 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3042 wufc = E1000_READ_REG(hw, E1000_WUFC);
3043 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3045 if ((wufc & wufc_en) == wufc_en) {
3046 uint32_t reg_off = 0;
3047 if (it->index < E1000_MAX_FHFT)
3048 reg_off = E1000_FHFT(it->index);
3050 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3052 queueing = E1000_READ_REG(hw,
3053 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3054 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3055 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3056 E1000_FHFT_QUEUEING_PRIO_SHIFT;
3057 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3058 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3065 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3066 enum rte_filter_op filter_op,
3069 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3070 struct rte_eth_flex_filter *filter;
3073 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3075 if (filter_op == RTE_ETH_FILTER_NOP)
3079 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3084 filter = (struct rte_eth_flex_filter *)arg;
3085 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3086 || filter->len % sizeof(uint64_t) != 0) {
3087 PMD_DRV_LOG(ERR, "filter's length is out of range");
3090 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3091 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3095 switch (filter_op) {
3096 case RTE_ETH_FILTER_ADD:
3097 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3099 case RTE_ETH_FILTER_DELETE:
3100 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3102 case RTE_ETH_FILTER_GET:
3103 ret = eth_igb_get_flex_filter(dev, filter);
3106 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3114 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3116 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3117 struct e1000_5tuple_filter_info *filter_info)
3119 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3121 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3122 return -EINVAL; /* filter index is out of range. */
3123 if (filter->tcp_flags > TCP_FLAG_ALL)
3124 return -EINVAL; /* flags is invalid. */
3126 switch (filter->dst_ip_mask) {
3128 filter_info->dst_ip_mask = 0;
3129 filter_info->dst_ip = filter->dst_ip;
3132 filter_info->dst_ip_mask = 1;
3135 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3139 switch (filter->src_ip_mask) {
3141 filter_info->src_ip_mask = 0;
3142 filter_info->src_ip = filter->src_ip;
3145 filter_info->src_ip_mask = 1;
3148 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3152 switch (filter->dst_port_mask) {
3154 filter_info->dst_port_mask = 0;
3155 filter_info->dst_port = filter->dst_port;
3158 filter_info->dst_port_mask = 1;
3161 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3165 switch (filter->src_port_mask) {
3167 filter_info->src_port_mask = 0;
3168 filter_info->src_port = filter->src_port;
3171 filter_info->src_port_mask = 1;
3174 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3178 switch (filter->proto_mask) {
3180 filter_info->proto_mask = 0;
3181 filter_info->proto = filter->proto;
3184 filter_info->proto_mask = 1;
3187 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3191 filter_info->priority = (uint8_t)filter->priority;
3192 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3193 filter_info->tcp_flags = filter->tcp_flags;
3195 filter_info->tcp_flags = 0;
3200 static inline struct e1000_5tuple_filter *
3201 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3202 struct e1000_5tuple_filter_info *key)
3204 struct e1000_5tuple_filter *it;
3206 TAILQ_FOREACH(it, filter_list, entries) {
3207 if (memcmp(key, &it->filter_info,
3208 sizeof(struct e1000_5tuple_filter_info)) == 0) {
3216 * igb_add_5tuple_filter_82576 - add a 5tuple filter
3219 * dev: Pointer to struct rte_eth_dev.
3220 * ntuple_filter: ponter to the filter that will be added.
3223 * - On success, zero.
3224 * - On failure, a negative value.
3227 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3228 struct rte_eth_ntuple_filter *ntuple_filter)
3230 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3231 struct e1000_filter_info *filter_info =
3232 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3233 struct e1000_5tuple_filter *filter;
3234 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3235 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3239 filter = rte_zmalloc("e1000_5tuple_filter",
3240 sizeof(struct e1000_5tuple_filter), 0);
3244 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3245 &filter->filter_info);
3251 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3252 &filter->filter_info) != NULL) {
3253 PMD_DRV_LOG(ERR, "filter exists.");
3257 filter->queue = ntuple_filter->queue;
3260 * look for an unused 5tuple filter index,
3261 * and insert the filter to list.
3263 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3264 if (!(filter_info->fivetuple_mask & (1 << i))) {
3265 filter_info->fivetuple_mask |= 1 << i;
3267 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3273 if (i >= E1000_MAX_FTQF_FILTERS) {
3274 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3279 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3280 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3281 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3282 if (filter->filter_info.dst_ip_mask == 0)
3283 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3284 if (filter->filter_info.src_port_mask == 0)
3285 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3286 if (filter->filter_info.proto_mask == 0)
3287 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3288 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3289 E1000_FTQF_QUEUE_MASK;
3290 ftqf |= E1000_FTQF_QUEUE_ENABLE;
3291 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3292 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3293 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3295 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3296 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3298 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3299 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3300 imir |= E1000_IMIR_PORT_BP;
3302 imir &= ~E1000_IMIR_PORT_BP;
3303 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3305 /* tcp flags bits setting. */
3306 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3307 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3308 imir_ext |= E1000_IMIREXT_CTRL_URG;
3309 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3310 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3311 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3312 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3313 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3314 imir_ext |= E1000_IMIREXT_CTRL_RST;
3315 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3316 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3317 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3318 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3320 imir_ext |= E1000_IMIREXT_CTRL_BP;
3321 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3322 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3327 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3330 * dev: Pointer to struct rte_eth_dev.
3331 * ntuple_filter: ponter to the filter that will be removed.
3334 * - On success, zero.
3335 * - On failure, a negative value.
3338 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3339 struct rte_eth_ntuple_filter *ntuple_filter)
3341 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3342 struct e1000_filter_info *filter_info =
3343 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3344 struct e1000_5tuple_filter_info filter_5tuple;
3345 struct e1000_5tuple_filter *filter;
3348 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3349 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3354 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3356 if (filter == NULL) {
3357 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3361 filter_info->fivetuple_mask &= ~(1 << filter->index);
3362 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3365 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3366 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3367 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3368 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3369 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3370 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3371 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3376 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3379 struct e1000_hw *hw;
3380 struct rte_eth_dev_info dev_info;
3381 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3384 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3386 #ifdef RTE_LIBRTE_82571_SUPPORT
3387 /* XXX: not bigger than max_rx_pktlen */
3388 if (hw->mac.type == e1000_82571)
3391 eth_igb_infos_get(dev, &dev_info);
3393 /* check that mtu is within the allowed range */
3394 if ((mtu < ETHER_MIN_MTU) ||
3395 (frame_size > dev_info.max_rx_pktlen))
3398 /* refuse mtu that requires the support of scattered packets when this
3399 * feature has not been enabled before. */
3400 if (!dev->data->scattered_rx &&
3401 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3404 rctl = E1000_READ_REG(hw, E1000_RCTL);
3406 /* switch to jumbo mode if needed */
3407 if (frame_size > ETHER_MAX_LEN) {
3408 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3409 rctl |= E1000_RCTL_LPE;
3411 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3412 rctl &= ~E1000_RCTL_LPE;
3414 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3416 /* update max frame size */
3417 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3419 E1000_WRITE_REG(hw, E1000_RLPML,
3420 dev->data->dev_conf.rxmode.max_rx_pkt_len);
3426 * igb_add_del_ntuple_filter - add or delete a ntuple filter
3429 * dev: Pointer to struct rte_eth_dev.
3430 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3431 * add: if true, add filter, if false, remove filter
3434 * - On success, zero.
3435 * - On failure, a negative value.
3438 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3439 struct rte_eth_ntuple_filter *ntuple_filter,
3442 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445 switch (ntuple_filter->flags) {
3446 case RTE_5TUPLE_FLAGS:
3447 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3448 if (hw->mac.type != e1000_82576)
3451 ret = igb_add_5tuple_filter_82576(dev,
3454 ret = igb_remove_5tuple_filter_82576(dev,
3457 case RTE_2TUPLE_FLAGS:
3458 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3459 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3462 ret = igb_add_2tuple_filter(dev, ntuple_filter);
3464 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3475 * igb_get_ntuple_filter - get a ntuple filter
3478 * dev: Pointer to struct rte_eth_dev.
3479 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3482 * - On success, zero.
3483 * - On failure, a negative value.
3486 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3487 struct rte_eth_ntuple_filter *ntuple_filter)
3489 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3490 struct e1000_filter_info *filter_info =
3491 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3492 struct e1000_5tuple_filter_info filter_5tuple;
3493 struct e1000_2tuple_filter_info filter_2tuple;
3494 struct e1000_5tuple_filter *p_5tuple_filter;
3495 struct e1000_2tuple_filter *p_2tuple_filter;
3498 switch (ntuple_filter->flags) {
3499 case RTE_5TUPLE_FLAGS:
3500 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3501 if (hw->mac.type != e1000_82576)
3503 memset(&filter_5tuple,
3505 sizeof(struct e1000_5tuple_filter_info));
3506 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3510 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3511 &filter_info->fivetuple_list,
3513 if (p_5tuple_filter == NULL) {
3514 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3517 ntuple_filter->queue = p_5tuple_filter->queue;
3519 case RTE_2TUPLE_FLAGS:
3520 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3521 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3523 memset(&filter_2tuple,
3525 sizeof(struct e1000_2tuple_filter_info));
3526 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3529 p_2tuple_filter = igb_2tuple_filter_lookup(
3530 &filter_info->twotuple_list,
3532 if (p_2tuple_filter == NULL) {
3533 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3536 ntuple_filter->queue = p_2tuple_filter->queue;
3547 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3548 * @dev: pointer to rte_eth_dev structure
3549 * @filter_op:operation will be taken.
3550 * @arg: a pointer to specific structure corresponding to the filter_op
3553 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3554 enum rte_filter_op filter_op,
3557 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3560 MAC_TYPE_FILTER_SUP(hw->mac.type);
3562 if (filter_op == RTE_ETH_FILTER_NOP)
3566 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3571 switch (filter_op) {
3572 case RTE_ETH_FILTER_ADD:
3573 ret = igb_add_del_ntuple_filter(dev,
3574 (struct rte_eth_ntuple_filter *)arg,
3577 case RTE_ETH_FILTER_DELETE:
3578 ret = igb_add_del_ntuple_filter(dev,
3579 (struct rte_eth_ntuple_filter *)arg,
3582 case RTE_ETH_FILTER_GET:
3583 ret = igb_get_ntuple_filter(dev,
3584 (struct rte_eth_ntuple_filter *)arg);
3587 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3595 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3600 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3601 if (filter_info->ethertype_filters[i] == ethertype &&
3602 (filter_info->ethertype_mask & (1 << i)))
3609 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3614 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3615 if (!(filter_info->ethertype_mask & (1 << i))) {
3616 filter_info->ethertype_mask |= 1 << i;
3617 filter_info->ethertype_filters[i] = ethertype;
3625 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3628 if (idx >= E1000_MAX_ETQF_FILTERS)
3630 filter_info->ethertype_mask &= ~(1 << idx);
3631 filter_info->ethertype_filters[idx] = 0;
3637 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3638 struct rte_eth_ethertype_filter *filter,
3641 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3642 struct e1000_filter_info *filter_info =
3643 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3647 if (filter->ether_type == ETHER_TYPE_IPv4 ||
3648 filter->ether_type == ETHER_TYPE_IPv6) {
3649 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3650 " ethertype filter.", filter->ether_type);
3654 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3655 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3658 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3659 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3663 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3664 if (ret >= 0 && add) {
3665 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3666 filter->ether_type);
3669 if (ret < 0 && !add) {
3670 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3671 filter->ether_type);
3676 ret = igb_ethertype_filter_insert(filter_info,
3677 filter->ether_type);
3679 PMD_DRV_LOG(ERR, "ethertype filters are full.");
3683 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3684 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3685 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3687 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3691 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3692 E1000_WRITE_FLUSH(hw);
3698 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3699 struct rte_eth_ethertype_filter *filter)
3701 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702 struct e1000_filter_info *filter_info =
3703 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3707 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3709 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3710 filter->ether_type);
3714 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3715 if (etqf & E1000_ETQF_FILTER_ENABLE) {
3716 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3718 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3719 E1000_ETQF_QUEUE_SHIFT;
3727 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3728 * @dev: pointer to rte_eth_dev structure
3729 * @filter_op:operation will be taken.
3730 * @arg: a pointer to specific structure corresponding to the filter_op
3733 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3734 enum rte_filter_op filter_op,
3737 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740 MAC_TYPE_FILTER_SUP(hw->mac.type);
3742 if (filter_op == RTE_ETH_FILTER_NOP)
3746 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3751 switch (filter_op) {
3752 case RTE_ETH_FILTER_ADD:
3753 ret = igb_add_del_ethertype_filter(dev,
3754 (struct rte_eth_ethertype_filter *)arg,
3757 case RTE_ETH_FILTER_DELETE:
3758 ret = igb_add_del_ethertype_filter(dev,
3759 (struct rte_eth_ethertype_filter *)arg,
3762 case RTE_ETH_FILTER_GET:
3763 ret = igb_get_ethertype_filter(dev,
3764 (struct rte_eth_ethertype_filter *)arg);
3767 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3775 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3776 enum rte_filter_type filter_type,
3777 enum rte_filter_op filter_op,
3782 switch (filter_type) {
3783 case RTE_ETH_FILTER_NTUPLE:
3784 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
3786 case RTE_ETH_FILTER_ETHERTYPE:
3787 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3789 case RTE_ETH_FILTER_SYN:
3790 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3792 case RTE_ETH_FILTER_FLEXIBLE:
3793 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3796 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3805 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
3806 struct ether_addr *mc_addr_set,
3807 uint32_t nb_mc_addr)
3809 struct e1000_hw *hw;
3811 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3812 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
3817 igb_timesync_enable(struct rte_eth_dev *dev)
3819 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3822 /* Start incrementing the register used to timestamp PTP packets. */
3823 E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
3825 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3826 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
3828 E1000_ETQF_FILTER_ENABLE |
3831 /* Enable timestamping of received PTP packets. */
3832 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3833 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
3834 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
3836 /* Enable Timestamping of transmitted PTP packets. */
3837 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3838 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
3839 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
3845 igb_timesync_disable(struct rte_eth_dev *dev)
3847 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850 /* Disable timestamping of transmitted PTP packets. */
3851 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3852 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
3853 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
3855 /* Disable timestamping of received PTP packets. */
3856 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3857 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
3858 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
3860 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3861 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
3863 /* Stop incrementating the System Time registers. */
3864 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
3870 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3871 struct timespec *timestamp,
3872 uint32_t flags __rte_unused)
3874 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3875 uint32_t tsync_rxctl;
3879 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3880 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
3883 rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
3884 rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
3886 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
3887 timestamp->tv_nsec = 0;
3893 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3894 struct timespec *timestamp)
3896 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3897 uint32_t tsync_txctl;
3901 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3902 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
3905 tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
3906 tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
3908 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
3909 timestamp->tv_nsec = 0;
3915 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
3919 const struct reg_info *reg_group;
3921 while ((reg_group = igb_regs[g_ind++]))
3922 count += igb_reg_group_count(reg_group);
3928 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
3932 const struct reg_info *reg_group;
3934 while ((reg_group = igbvf_regs[g_ind++]))
3935 count += igb_reg_group_count(reg_group);
3941 eth_igb_get_regs(struct rte_eth_dev *dev,
3942 struct rte_dev_reg_info *regs)
3944 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3945 uint32_t *data = regs->data;
3948 const struct reg_info *reg_group;
3950 /* Support only full register dump */
3951 if ((regs->length == 0) ||
3952 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
3953 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
3955 while ((reg_group = igb_regs[g_ind++]))
3956 count += igb_read_regs_group(dev, &data[count],
3965 igbvf_get_regs(struct rte_eth_dev *dev,
3966 struct rte_dev_reg_info *regs)
3968 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3969 uint32_t *data = regs->data;
3972 const struct reg_info *reg_group;
3974 /* Support only full register dump */
3975 if ((regs->length == 0) ||
3976 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
3977 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
3979 while ((reg_group = igbvf_regs[g_ind++]))
3980 count += igb_read_regs_group(dev, &data[count],
3989 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
3991 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993 /* Return unit is byte count */
3994 return hw->nvm.word_size * 2;
3998 eth_igb_get_eeprom(struct rte_eth_dev *dev,
3999 struct rte_dev_eeprom_info *in_eeprom)
4001 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4002 struct e1000_nvm_info *nvm = &hw->nvm;
4003 uint16_t *data = in_eeprom->data;
4006 first = in_eeprom->offset >> 1;
4007 length = in_eeprom->length >> 1;
4008 if ((first >= hw->nvm.word_size) ||
4009 ((first + length) >= hw->nvm.word_size))
4012 in_eeprom->magic = hw->vendor_id |
4013 ((uint32_t)hw->device_id << 16);
4015 if ((nvm->ops.read) == NULL)
4018 return nvm->ops.read(hw, first, length, data);
4022 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4023 struct rte_dev_eeprom_info *in_eeprom)
4025 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4026 struct e1000_nvm_info *nvm = &hw->nvm;
4027 uint16_t *data = in_eeprom->data;
4030 first = in_eeprom->offset >> 1;
4031 length = in_eeprom->length >> 1;
4032 if ((first >= hw->nvm.word_size) ||
4033 ((first + length) >= hw->nvm.word_size))
4036 in_eeprom->magic = (uint32_t)hw->vendor_id |
4037 ((uint32_t)hw->device_id << 16);
4039 if ((nvm->ops.write) == NULL)
4041 return nvm->ops.write(hw, first, length, data);
4044 static struct rte_driver pmd_igb_drv = {
4046 .init = rte_igb_pmd_init,
4049 static struct rte_driver pmd_igbvf_drv = {
4051 .init = rte_igbvf_pmd_init,
4054 PMD_REGISTER_DRIVER(pmd_igb_drv);
4055 PMD_REGISTER_DRIVER(pmd_igbvf_drv);