4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
65 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
66 #define IGB_DEFAULT_RX_HTHRESH 8
67 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
69 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
70 #define IGB_DEFAULT_TX_HTHRESH 1
71 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
73 #define IGB_HKEY_MAX_INDEX 10
75 /* Bit shift and mask */
76 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
77 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
78 #define IGB_8_BIT_WIDTH CHAR_BIT
79 #define IGB_8_BIT_MASK UINT8_MAX
81 /* Additional timesync values. */
82 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
83 #define E1000_ETQF_FILTER_1588 3
84 #define IGB_82576_TSYNC_SHIFT 16
85 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
86 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
89 static int eth_igb_configure(struct rte_eth_dev *dev);
90 static int eth_igb_start(struct rte_eth_dev *dev);
91 static void eth_igb_stop(struct rte_eth_dev *dev);
92 static void eth_igb_close(struct rte_eth_dev *dev);
93 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
94 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
95 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
96 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
97 static int eth_igb_link_update(struct rte_eth_dev *dev,
98 int wait_to_complete);
99 static void eth_igb_stats_get(struct rte_eth_dev *dev,
100 struct rte_eth_stats *rte_stats);
101 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
102 struct rte_eth_xstats *xstats, unsigned n);
103 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
104 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
105 static void eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
118 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct e1000_hw *hw);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static void eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
158 static void igbvf_dev_close(struct rte_eth_dev *dev);
159 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstats *xstats, unsigned n);
168 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
169 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
170 uint16_t vlan_id, int on);
171 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
172 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
173 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
174 struct ether_addr *addr);
175 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
176 static int igbvf_get_regs(struct rte_eth_dev *dev,
177 struct rte_dev_reg_info *regs);
179 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
180 struct rte_eth_rss_reta_entry64 *reta_conf,
182 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
186 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
187 struct rte_eth_syn_filter *filter,
189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
190 struct rte_eth_syn_filter *filter);
191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
192 enum rte_filter_op filter_op,
194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
197 struct rte_eth_ntuple_filter *ntuple_filter);
198 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
199 struct rte_eth_flex_filter *filter,
201 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
202 struct rte_eth_flex_filter *filter);
203 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
204 enum rte_filter_op filter_op,
206 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
207 struct rte_eth_ntuple_filter *ntuple_filter);
208 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
209 struct rte_eth_ntuple_filter *ntuple_filter);
210 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
211 struct rte_eth_ntuple_filter *filter,
213 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
214 struct rte_eth_ntuple_filter *filter);
215 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
216 enum rte_filter_op filter_op,
218 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
219 struct rte_eth_ethertype_filter *filter,
221 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
222 enum rte_filter_op filter_op,
224 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
225 struct rte_eth_ethertype_filter *filter);
226 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
227 enum rte_filter_type filter_type,
228 enum rte_filter_op filter_op,
230 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
231 static int eth_igb_get_regs(struct rte_eth_dev *dev,
232 struct rte_dev_reg_info *regs);
233 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
234 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
235 struct rte_dev_eeprom_info *eeprom);
236 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
237 struct rte_dev_eeprom_info *eeprom);
238 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
239 struct ether_addr *mc_addr_set,
240 uint32_t nb_mc_addr);
241 static int igb_timesync_enable(struct rte_eth_dev *dev);
242 static int igb_timesync_disable(struct rte_eth_dev *dev);
243 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
244 struct timespec *timestamp,
246 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
247 struct timespec *timestamp);
248 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
249 static int igb_timesync_read_time(struct rte_eth_dev *dev,
250 struct timespec *timestamp);
251 static int igb_timesync_write_time(struct rte_eth_dev *dev,
252 const struct timespec *timestamp);
253 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
255 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
257 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
258 uint8_t queue, uint8_t msix_vector);
259 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
260 uint8_t index, uint8_t offset);
261 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
264 * Define VF Stats MACRO for Non "cleared on read" register
266 #define UPDATE_VF_STAT(reg, last, cur) \
268 u32 latest = E1000_READ_REG(hw, reg); \
269 cur += (latest - last) & UINT_MAX; \
273 #define IGB_FC_PAUSE_TIME 0x0680
274 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
275 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
277 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
279 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
282 * The set of PCI devices this driver supports
284 static const struct rte_pci_id pci_id_igb_map[] = {
286 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
287 #include "rte_pci_dev_ids.h"
293 * The set of PCI devices this driver supports (for 82576&I350 VF)
295 static const struct rte_pci_id pci_id_igbvf_map[] = {
297 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
298 #include "rte_pci_dev_ids.h"
303 static const struct rte_eth_desc_lim rx_desc_lim = {
304 .nb_max = E1000_MAX_RING_DESC,
305 .nb_min = E1000_MIN_RING_DESC,
306 .nb_align = IGB_RXD_ALIGN,
309 static const struct rte_eth_desc_lim tx_desc_lim = {
310 .nb_max = E1000_MAX_RING_DESC,
311 .nb_min = E1000_MIN_RING_DESC,
312 .nb_align = IGB_RXD_ALIGN,
315 static const struct eth_dev_ops eth_igb_ops = {
316 .dev_configure = eth_igb_configure,
317 .dev_start = eth_igb_start,
318 .dev_stop = eth_igb_stop,
319 .dev_close = eth_igb_close,
320 .promiscuous_enable = eth_igb_promiscuous_enable,
321 .promiscuous_disable = eth_igb_promiscuous_disable,
322 .allmulticast_enable = eth_igb_allmulticast_enable,
323 .allmulticast_disable = eth_igb_allmulticast_disable,
324 .link_update = eth_igb_link_update,
325 .stats_get = eth_igb_stats_get,
326 .xstats_get = eth_igb_xstats_get,
327 .stats_reset = eth_igb_stats_reset,
328 .xstats_reset = eth_igb_xstats_reset,
329 .dev_infos_get = eth_igb_infos_get,
330 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
331 .mtu_set = eth_igb_mtu_set,
332 .vlan_filter_set = eth_igb_vlan_filter_set,
333 .vlan_tpid_set = eth_igb_vlan_tpid_set,
334 .vlan_offload_set = eth_igb_vlan_offload_set,
335 .rx_queue_setup = eth_igb_rx_queue_setup,
336 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
337 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
338 .rx_queue_release = eth_igb_rx_queue_release,
339 .rx_queue_count = eth_igb_rx_queue_count,
340 .rx_descriptor_done = eth_igb_rx_descriptor_done,
341 .tx_queue_setup = eth_igb_tx_queue_setup,
342 .tx_queue_release = eth_igb_tx_queue_release,
343 .dev_led_on = eth_igb_led_on,
344 .dev_led_off = eth_igb_led_off,
345 .flow_ctrl_get = eth_igb_flow_ctrl_get,
346 .flow_ctrl_set = eth_igb_flow_ctrl_set,
347 .mac_addr_add = eth_igb_rar_set,
348 .mac_addr_remove = eth_igb_rar_clear,
349 .mac_addr_set = eth_igb_default_mac_addr_set,
350 .reta_update = eth_igb_rss_reta_update,
351 .reta_query = eth_igb_rss_reta_query,
352 .rss_hash_update = eth_igb_rss_hash_update,
353 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
354 .filter_ctrl = eth_igb_filter_ctrl,
355 .set_mc_addr_list = eth_igb_set_mc_addr_list,
356 .rxq_info_get = igb_rxq_info_get,
357 .txq_info_get = igb_txq_info_get,
358 .timesync_enable = igb_timesync_enable,
359 .timesync_disable = igb_timesync_disable,
360 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
361 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
362 .get_reg_length = eth_igb_get_reg_length,
363 .get_reg = eth_igb_get_regs,
364 .get_eeprom_length = eth_igb_get_eeprom_length,
365 .get_eeprom = eth_igb_get_eeprom,
366 .set_eeprom = eth_igb_set_eeprom,
367 .timesync_adjust_time = igb_timesync_adjust_time,
368 .timesync_read_time = igb_timesync_read_time,
369 .timesync_write_time = igb_timesync_write_time,
373 * dev_ops for virtual function, bare necessities for basic vf
374 * operation have been implemented
376 static const struct eth_dev_ops igbvf_eth_dev_ops = {
377 .dev_configure = igbvf_dev_configure,
378 .dev_start = igbvf_dev_start,
379 .dev_stop = igbvf_dev_stop,
380 .dev_close = igbvf_dev_close,
381 .promiscuous_enable = igbvf_promiscuous_enable,
382 .promiscuous_disable = igbvf_promiscuous_disable,
383 .allmulticast_enable = igbvf_allmulticast_enable,
384 .allmulticast_disable = igbvf_allmulticast_disable,
385 .link_update = eth_igb_link_update,
386 .stats_get = eth_igbvf_stats_get,
387 .xstats_get = eth_igbvf_xstats_get,
388 .stats_reset = eth_igbvf_stats_reset,
389 .xstats_reset = eth_igbvf_stats_reset,
390 .vlan_filter_set = igbvf_vlan_filter_set,
391 .dev_infos_get = eth_igbvf_infos_get,
392 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
393 .rx_queue_setup = eth_igb_rx_queue_setup,
394 .rx_queue_release = eth_igb_rx_queue_release,
395 .tx_queue_setup = eth_igb_tx_queue_setup,
396 .tx_queue_release = eth_igb_tx_queue_release,
397 .set_mc_addr_list = eth_igb_set_mc_addr_list,
398 .rxq_info_get = igb_rxq_info_get,
399 .txq_info_get = igb_txq_info_get,
400 .mac_addr_set = igbvf_default_mac_addr_set,
401 .get_reg_length = igbvf_get_reg_length,
402 .get_reg = igbvf_get_regs,
405 /* store statistics names and its offset in stats structure */
406 struct rte_igb_xstats_name_off {
407 char name[RTE_ETH_XSTATS_NAME_SIZE];
411 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
412 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
413 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
414 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
415 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
416 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
417 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
418 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
420 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
421 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
422 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
423 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
424 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
425 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
426 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
427 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
428 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
429 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
430 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
432 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
433 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
434 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
435 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
436 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
438 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
440 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
441 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
442 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
443 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
444 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
445 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
446 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
447 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
448 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
449 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
450 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
451 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
452 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
453 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
454 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
455 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
456 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
457 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
459 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
461 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
462 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
463 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
464 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
465 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
466 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
467 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
469 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
472 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
473 sizeof(rte_igb_stats_strings[0]))
475 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
476 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
477 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
478 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
479 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
480 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
483 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
484 sizeof(rte_igbvf_stats_strings[0]))
487 * Atomically reads the link status information from global
488 * structure rte_eth_dev.
491 * - Pointer to the structure rte_eth_dev to read from.
492 * - Pointer to the buffer to be saved with the link status.
495 * - On success, zero.
496 * - On failure, negative value.
499 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
500 struct rte_eth_link *link)
502 struct rte_eth_link *dst = link;
503 struct rte_eth_link *src = &(dev->data->dev_link);
505 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
506 *(uint64_t *)src) == 0)
513 * Atomically writes the link status information into global
514 * structure rte_eth_dev.
517 * - Pointer to the structure rte_eth_dev to read from.
518 * - Pointer to the buffer to be saved with the link status.
521 * - On success, zero.
522 * - On failure, negative value.
525 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
526 struct rte_eth_link *link)
528 struct rte_eth_link *dst = &(dev->data->dev_link);
529 struct rte_eth_link *src = link;
531 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
532 *(uint64_t *)src) == 0)
539 igb_intr_enable(struct rte_eth_dev *dev)
541 struct e1000_interrupt *intr =
542 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
543 struct e1000_hw *hw =
544 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
546 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
547 E1000_WRITE_FLUSH(hw);
551 igb_intr_disable(struct e1000_hw *hw)
553 E1000_WRITE_REG(hw, E1000_IMC, ~0);
554 E1000_WRITE_FLUSH(hw);
557 static inline int32_t
558 igb_pf_reset_hw(struct e1000_hw *hw)
563 status = e1000_reset_hw(hw);
565 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
566 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
567 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
568 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
569 E1000_WRITE_FLUSH(hw);
575 igb_identify_hardware(struct rte_eth_dev *dev)
577 struct e1000_hw *hw =
578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
580 hw->vendor_id = dev->pci_dev->id.vendor_id;
581 hw->device_id = dev->pci_dev->id.device_id;
582 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
583 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
585 e1000_set_mac_type(hw);
587 /* need to check if it is a vf device below */
591 igb_reset_swfw_lock(struct e1000_hw *hw)
596 * Do mac ops initialization manually here, since we will need
597 * some function pointers set by this call.
599 ret_val = e1000_init_mac_params(hw);
604 * SMBI lock should not fail in this early stage. If this is the case,
605 * it is due to an improper exit of the application.
606 * So force the release of the faulty lock.
608 if (e1000_get_hw_semaphore_generic(hw) < 0) {
609 PMD_DRV_LOG(DEBUG, "SMBI lock released");
611 e1000_put_hw_semaphore_generic(hw);
613 if (hw->mac.ops.acquire_swfw_sync != NULL) {
617 * Phy lock should not fail in this early stage. If this is the case,
618 * it is due to an improper exit of the application.
619 * So force the release of the faulty lock.
621 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
622 if (hw->bus.func > E1000_FUNC_1)
624 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
625 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
628 hw->mac.ops.release_swfw_sync(hw, mask);
631 * This one is more tricky since it is common to all ports; but
632 * swfw_sync retries last long enough (1s) to be almost sure that if
633 * lock can not be taken it is due to an improper lock of the
636 mask = E1000_SWFW_EEP_SM;
637 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
638 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
640 hw->mac.ops.release_swfw_sync(hw, mask);
643 return E1000_SUCCESS;
647 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
650 struct rte_pci_device *pci_dev;
651 struct e1000_hw *hw =
652 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
653 struct e1000_vfta * shadow_vfta =
654 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
655 struct e1000_filter_info *filter_info =
656 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
657 struct e1000_adapter *adapter =
658 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
662 pci_dev = eth_dev->pci_dev;
664 eth_dev->dev_ops = ð_igb_ops;
665 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
666 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
668 /* for secondary processes, we don't initialise any further as primary
669 * has already done this work. Only check we don't need a different
671 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
672 if (eth_dev->data->scattered_rx)
673 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
677 rte_eth_copy_pci_info(eth_dev, pci_dev);
679 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
681 igb_identify_hardware(eth_dev);
682 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
687 e1000_get_bus_info(hw);
689 /* Reset any pending lock */
690 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
695 /* Finish initialization */
696 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
702 hw->phy.autoneg_wait_to_complete = 0;
703 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
706 if (hw->phy.media_type == e1000_media_type_copper) {
707 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
708 hw->phy.disable_polarity_correction = 0;
709 hw->phy.ms_type = e1000_ms_hw_default;
713 * Start from a known state, this is important in reading the nvm
718 /* Make sure we have a good EEPROM before we read from it */
719 if (e1000_validate_nvm_checksum(hw) < 0) {
721 * Some PCI-E parts fail the first check due to
722 * the link being in sleep state, call it again,
723 * if it fails a second time its a real issue.
725 if (e1000_validate_nvm_checksum(hw) < 0) {
726 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
732 /* Read the permanent MAC address out of the EEPROM */
733 if (e1000_read_mac_addr(hw) != 0) {
734 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
739 /* Allocate memory for storing MAC addresses */
740 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
741 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
742 if (eth_dev->data->mac_addrs == NULL) {
743 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
744 "store MAC addresses",
745 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
750 /* Copy the permanent MAC address */
751 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
753 /* initialize the vfta */
754 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
756 /* Now initialize the hardware */
757 if (igb_hardware_init(hw) != 0) {
758 PMD_INIT_LOG(ERR, "Hardware initialization failed");
759 rte_free(eth_dev->data->mac_addrs);
760 eth_dev->data->mac_addrs = NULL;
764 hw->mac.get_link_status = 1;
765 adapter->stopped = 0;
767 /* Indicate SOL/IDER usage */
768 if (e1000_check_reset_block(hw) < 0) {
769 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
773 /* initialize PF if max_vfs not zero */
774 igb_pf_host_init(eth_dev);
776 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
777 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
778 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
779 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
780 E1000_WRITE_FLUSH(hw);
782 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
783 eth_dev->data->port_id, pci_dev->id.vendor_id,
784 pci_dev->id.device_id);
786 rte_intr_callback_register(&pci_dev->intr_handle,
787 eth_igb_interrupt_handler,
790 /* enable uio/vfio intr/eventfd mapping */
791 rte_intr_enable(&pci_dev->intr_handle);
793 /* enable support intr */
794 igb_intr_enable(eth_dev);
796 TAILQ_INIT(&filter_info->flex_list);
797 filter_info->flex_mask = 0;
798 TAILQ_INIT(&filter_info->twotuple_list);
799 filter_info->twotuple_mask = 0;
800 TAILQ_INIT(&filter_info->fivetuple_list);
801 filter_info->fivetuple_mask = 0;
806 igb_hw_control_release(hw);
812 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
814 struct rte_pci_device *pci_dev;
816 struct e1000_adapter *adapter =
817 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
819 PMD_INIT_FUNC_TRACE();
821 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
824 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
825 pci_dev = eth_dev->pci_dev;
827 if (adapter->stopped == 0)
828 eth_igb_close(eth_dev);
830 eth_dev->dev_ops = NULL;
831 eth_dev->rx_pkt_burst = NULL;
832 eth_dev->tx_pkt_burst = NULL;
834 /* Reset any pending lock */
835 igb_reset_swfw_lock(hw);
837 rte_free(eth_dev->data->mac_addrs);
838 eth_dev->data->mac_addrs = NULL;
840 /* uninitialize PF if max_vfs not zero */
841 igb_pf_host_uninit(eth_dev);
843 /* disable uio intr before callback unregister */
844 rte_intr_disable(&(pci_dev->intr_handle));
845 rte_intr_callback_unregister(&(pci_dev->intr_handle),
846 eth_igb_interrupt_handler, (void *)eth_dev);
852 * Virtual Function device init
855 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
857 struct rte_pci_device *pci_dev;
858 struct e1000_adapter *adapter =
859 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
860 struct e1000_hw *hw =
861 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
863 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
865 PMD_INIT_FUNC_TRACE();
867 eth_dev->dev_ops = &igbvf_eth_dev_ops;
868 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
869 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
871 /* for secondary processes, we don't initialise any further as primary
872 * has already done this work. Only check we don't need a different
874 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
875 if (eth_dev->data->scattered_rx)
876 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
880 pci_dev = eth_dev->pci_dev;
882 rte_eth_copy_pci_info(eth_dev, pci_dev);
884 hw->device_id = pci_dev->id.device_id;
885 hw->vendor_id = pci_dev->id.vendor_id;
886 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
887 adapter->stopped = 0;
889 /* Initialize the shared code (base driver) */
890 diag = e1000_setup_init_funcs(hw, TRUE);
892 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
897 /* init_mailbox_params */
898 hw->mbx.ops.init_params(hw);
900 /* Disable the interrupts for VF */
901 igbvf_intr_disable(hw);
903 diag = hw->mac.ops.reset_hw(hw);
905 /* Allocate memory for storing MAC addresses */
906 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
907 hw->mac.rar_entry_count, 0);
908 if (eth_dev->data->mac_addrs == NULL) {
910 "Failed to allocate %d bytes needed to store MAC "
912 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
916 /* Generate a random MAC address, if none was assigned by PF. */
917 if (is_zero_ether_addr(perm_addr)) {
918 eth_random_addr(perm_addr->addr_bytes);
919 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
921 rte_free(eth_dev->data->mac_addrs);
922 eth_dev->data->mac_addrs = NULL;
925 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
926 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
927 "%02x:%02x:%02x:%02x:%02x:%02x",
928 perm_addr->addr_bytes[0],
929 perm_addr->addr_bytes[1],
930 perm_addr->addr_bytes[2],
931 perm_addr->addr_bytes[3],
932 perm_addr->addr_bytes[4],
933 perm_addr->addr_bytes[5]);
936 /* Copy the permanent MAC address */
937 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
938 ð_dev->data->mac_addrs[0]);
940 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
942 eth_dev->data->port_id, pci_dev->id.vendor_id,
943 pci_dev->id.device_id, "igb_mac_82576_vf");
949 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
951 struct e1000_adapter *adapter =
952 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
954 PMD_INIT_FUNC_TRACE();
956 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
959 if (adapter->stopped == 0)
960 igbvf_dev_close(eth_dev);
962 eth_dev->dev_ops = NULL;
963 eth_dev->rx_pkt_burst = NULL;
964 eth_dev->tx_pkt_burst = NULL;
966 rte_free(eth_dev->data->mac_addrs);
967 eth_dev->data->mac_addrs = NULL;
972 static struct eth_driver rte_igb_pmd = {
974 .name = "rte_igb_pmd",
975 .id_table = pci_id_igb_map,
976 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
977 RTE_PCI_DRV_DETACHABLE,
979 .eth_dev_init = eth_igb_dev_init,
980 .eth_dev_uninit = eth_igb_dev_uninit,
981 .dev_private_size = sizeof(struct e1000_adapter),
985 * virtual function driver struct
987 static struct eth_driver rte_igbvf_pmd = {
989 .name = "rte_igbvf_pmd",
990 .id_table = pci_id_igbvf_map,
991 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
993 .eth_dev_init = eth_igbvf_dev_init,
994 .eth_dev_uninit = eth_igbvf_dev_uninit,
995 .dev_private_size = sizeof(struct e1000_adapter),
999 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1001 rte_eth_driver_register(&rte_igb_pmd);
1006 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1008 struct e1000_hw *hw =
1009 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1010 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1011 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1012 rctl |= E1000_RCTL_VFE;
1013 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1017 * VF Driver initialization routine.
1018 * Invoked one at EAL init time.
1019 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1022 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1024 PMD_INIT_FUNC_TRACE();
1026 rte_eth_driver_register(&rte_igbvf_pmd);
1031 igb_check_mq_mode(struct rte_eth_dev *dev)
1033 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1034 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1035 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1036 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1038 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1039 tx_mq_mode == ETH_MQ_TX_DCB ||
1040 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1041 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1044 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1045 /* Check multi-queue mode.
1046 * To no break software we accept ETH_MQ_RX_NONE as this might
1047 * be used to turn off VLAN filter.
1050 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1051 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1052 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1053 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1055 /* Only support one queue on VFs.
1056 * RSS together with SRIOV is not supported.
1058 PMD_INIT_LOG(ERR, "SRIOV is active,"
1059 " wrong mq_mode rx %d.",
1063 /* TX mode is not used here, so mode might be ignored.*/
1064 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1065 /* SRIOV only works in VMDq enable mode */
1066 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1067 " TX mode %d is not supported. "
1068 " Driver will behave as %d mode.",
1069 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1072 /* check valid queue number */
1073 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1074 PMD_INIT_LOG(ERR, "SRIOV is active,"
1075 " only support one queue on VFs.");
1079 /* To no break software that set invalid mode, only display
1080 * warning if invalid mode is used.
1082 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1083 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1084 rx_mq_mode != ETH_MQ_RX_RSS) {
1085 /* RSS together with VMDq not supported*/
1086 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1091 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1092 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1093 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1094 " Due to txmode is meaningless in this"
1095 " driver, just ignore.",
1103 eth_igb_configure(struct rte_eth_dev *dev)
1105 struct e1000_interrupt *intr =
1106 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1109 PMD_INIT_FUNC_TRACE();
1111 /* multipe queue mode checking */
1112 ret = igb_check_mq_mode(dev);
1114 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1119 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1120 PMD_INIT_FUNC_TRACE();
1126 eth_igb_start(struct rte_eth_dev *dev)
1128 struct e1000_hw *hw =
1129 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130 struct e1000_adapter *adapter =
1131 E1000_DEV_PRIVATE(dev->data->dev_private);
1132 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1134 uint32_t intr_vector = 0;
1140 PMD_INIT_FUNC_TRACE();
1142 /* disable uio/vfio intr/eventfd mapping */
1143 rte_intr_disable(intr_handle);
1145 /* Power up the phy. Needed to make the link go Up */
1146 e1000_power_up_phy(hw);
1149 * Packet Buffer Allocation (PBA)
1150 * Writing PBA sets the receive portion of the buffer
1151 * the remainder is used for the transmit buffer.
1153 if (hw->mac.type == e1000_82575) {
1156 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1157 E1000_WRITE_REG(hw, E1000_PBA, pba);
1160 /* Put the address into the Receive Address Array */
1161 e1000_rar_set(hw, hw->mac.addr, 0);
1163 /* Initialize the hardware */
1164 if (igb_hardware_init(hw)) {
1165 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1168 adapter->stopped = 0;
1170 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1172 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1173 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1174 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1175 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1176 E1000_WRITE_FLUSH(hw);
1178 /* configure PF module if SRIOV enabled */
1179 igb_pf_host_configure(dev);
1181 /* check and configure queue intr-vector mapping */
1182 if ((rte_intr_cap_multiple(intr_handle) ||
1183 !RTE_ETH_DEV_SRIOV(dev).active) &&
1184 dev->data->dev_conf.intr_conf.rxq != 0) {
1185 intr_vector = dev->data->nb_rx_queues;
1186 if (rte_intr_efd_enable(intr_handle, intr_vector))
1190 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1191 intr_handle->intr_vec =
1192 rte_zmalloc("intr_vec",
1193 dev->data->nb_rx_queues * sizeof(int), 0);
1194 if (intr_handle->intr_vec == NULL) {
1195 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1196 " intr_vec\n", dev->data->nb_rx_queues);
1201 /* confiugre msix for rx interrupt */
1202 eth_igb_configure_msix_intr(dev);
1204 /* Configure for OS presence */
1205 igb_init_manageability(hw);
1207 eth_igb_tx_init(dev);
1209 /* This can fail when allocating mbufs for descriptor rings */
1210 ret = eth_igb_rx_init(dev);
1212 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1213 igb_dev_clear_queues(dev);
1217 e1000_clear_hw_cntrs_base_generic(hw);
1220 * VLAN Offload Settings
1222 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1223 ETH_VLAN_EXTEND_MASK;
1224 eth_igb_vlan_offload_set(dev, mask);
1226 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1227 /* Enable VLAN filter since VMDq always use VLAN filter */
1228 igb_vmdq_vlan_hw_filter_enable(dev);
1231 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1232 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1233 (hw->mac.type == e1000_i211)) {
1234 /* Configure EITR with the maximum possible value (0xFFFF) */
1235 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1238 /* Setup link speed and duplex */
1239 speeds = &dev->data->dev_conf.link_speeds;
1240 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1241 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1244 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1247 hw->phy.autoneg_advertised = 0;
1249 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1250 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1251 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1253 goto error_invalid_config;
1255 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1256 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1259 if (*speeds & ETH_LINK_SPEED_10M) {
1260 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1263 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1264 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1267 if (*speeds & ETH_LINK_SPEED_100M) {
1268 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1271 if (*speeds & ETH_LINK_SPEED_1G) {
1272 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1275 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1276 goto error_invalid_config;
1279 e1000_setup_link(hw);
1281 if (rte_intr_allow_others(intr_handle)) {
1282 /* check if lsc interrupt is enabled */
1283 if (dev->data->dev_conf.intr_conf.lsc != 0)
1284 eth_igb_lsc_interrupt_setup(dev);
1286 rte_intr_callback_unregister(intr_handle,
1287 eth_igb_interrupt_handler,
1289 if (dev->data->dev_conf.intr_conf.lsc != 0)
1290 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1291 " no intr multiplex\n");
1294 /* check if rxq interrupt is enabled */
1295 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1296 rte_intr_dp_is_en(intr_handle))
1297 eth_igb_rxq_interrupt_setup(dev);
1299 /* enable uio/vfio intr/eventfd mapping */
1300 rte_intr_enable(intr_handle);
1302 /* resume enabled intr since hw reset */
1303 igb_intr_enable(dev);
1305 PMD_INIT_LOG(DEBUG, "<<");
1309 error_invalid_config:
1310 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1311 dev->data->dev_conf.link_speeds, dev->data->port_id);
1312 igb_dev_clear_queues(dev);
1316 /*********************************************************************
1318 * This routine disables all traffic on the adapter by issuing a
1319 * global reset on the MAC.
1321 **********************************************************************/
1323 eth_igb_stop(struct rte_eth_dev *dev)
1325 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326 struct e1000_filter_info *filter_info =
1327 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1328 struct rte_eth_link link;
1329 struct e1000_flex_filter *p_flex;
1330 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1331 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1332 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1334 igb_intr_disable(hw);
1336 /* disable intr eventfd mapping */
1337 rte_intr_disable(intr_handle);
1339 igb_pf_reset_hw(hw);
1340 E1000_WRITE_REG(hw, E1000_WUC, 0);
1342 /* Set bit for Go Link disconnect */
1343 if (hw->mac.type >= e1000_82580) {
1346 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1347 phpm_reg |= E1000_82580_PM_GO_LINKD;
1348 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1351 /* Power down the phy. Needed to make the link go Down */
1352 if (hw->phy.media_type == e1000_media_type_copper)
1353 e1000_power_down_phy(hw);
1355 e1000_shutdown_fiber_serdes_link(hw);
1357 igb_dev_clear_queues(dev);
1359 /* clear the recorded link status */
1360 memset(&link, 0, sizeof(link));
1361 rte_igb_dev_atomic_write_link_status(dev, &link);
1363 /* Remove all flex filters of the device */
1364 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1365 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1368 filter_info->flex_mask = 0;
1370 /* Remove all ntuple filters of the device */
1371 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1372 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1373 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1374 TAILQ_REMOVE(&filter_info->fivetuple_list,
1378 filter_info->fivetuple_mask = 0;
1379 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1380 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1381 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1382 TAILQ_REMOVE(&filter_info->twotuple_list,
1386 filter_info->twotuple_mask = 0;
1388 if (!rte_intr_allow_others(intr_handle))
1389 /* resume to the default handler */
1390 rte_intr_callback_register(intr_handle,
1391 eth_igb_interrupt_handler,
1394 /* Clean datapath event and queue/vec mapping */
1395 rte_intr_efd_disable(intr_handle);
1396 if (intr_handle->intr_vec != NULL) {
1397 rte_free(intr_handle->intr_vec);
1398 intr_handle->intr_vec = NULL;
1403 eth_igb_close(struct rte_eth_dev *dev)
1405 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406 struct e1000_adapter *adapter =
1407 E1000_DEV_PRIVATE(dev->data->dev_private);
1408 struct rte_eth_link link;
1409 struct rte_pci_device *pci_dev;
1412 adapter->stopped = 1;
1414 e1000_phy_hw_reset(hw);
1415 igb_release_manageability(hw);
1416 igb_hw_control_release(hw);
1418 /* Clear bit for Go Link disconnect */
1419 if (hw->mac.type >= e1000_82580) {
1422 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1423 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1424 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1427 igb_dev_free_queues(dev);
1429 pci_dev = dev->pci_dev;
1430 if (pci_dev->intr_handle.intr_vec) {
1431 rte_free(pci_dev->intr_handle.intr_vec);
1432 pci_dev->intr_handle.intr_vec = NULL;
1435 memset(&link, 0, sizeof(link));
1436 rte_igb_dev_atomic_write_link_status(dev, &link);
1440 igb_get_rx_buffer_size(struct e1000_hw *hw)
1442 uint32_t rx_buf_size;
1443 if (hw->mac.type == e1000_82576) {
1444 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1445 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1446 /* PBS needs to be translated according to a lookup table */
1447 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1448 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1449 rx_buf_size = (rx_buf_size << 10);
1450 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1451 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1453 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1459 /*********************************************************************
1461 * Initialize the hardware
1463 **********************************************************************/
1465 igb_hardware_init(struct e1000_hw *hw)
1467 uint32_t rx_buf_size;
1470 /* Let the firmware know the OS is in control */
1471 igb_hw_control_acquire(hw);
1474 * These parameters control the automatic generation (Tx) and
1475 * response (Rx) to Ethernet PAUSE frames.
1476 * - High water mark should allow for at least two standard size (1518)
1477 * frames to be received after sending an XOFF.
1478 * - Low water mark works best when it is very near the high water mark.
1479 * This allows the receiver to restart by sending XON when it has
1480 * drained a bit. Here we use an arbitrary value of 1500 which will
1481 * restart after one full frame is pulled from the buffer. There
1482 * could be several smaller frames in the buffer and if so they will
1483 * not trigger the XON until their total number reduces the buffer
1485 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1487 rx_buf_size = igb_get_rx_buffer_size(hw);
1489 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1490 hw->fc.low_water = hw->fc.high_water - 1500;
1491 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1492 hw->fc.send_xon = 1;
1494 /* Set Flow control, use the tunable location if sane */
1495 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1496 hw->fc.requested_mode = igb_fc_setting;
1498 hw->fc.requested_mode = e1000_fc_none;
1500 /* Issue a global reset */
1501 igb_pf_reset_hw(hw);
1502 E1000_WRITE_REG(hw, E1000_WUC, 0);
1504 diag = e1000_init_hw(hw);
1508 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1509 e1000_get_phy_info(hw);
1510 e1000_check_for_link(hw);
1515 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1517 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1521 uint64_t old_gprc = stats->gprc;
1522 uint64_t old_gptc = stats->gptc;
1523 uint64_t old_tpr = stats->tpr;
1524 uint64_t old_tpt = stats->tpt;
1525 uint64_t old_rpthc = stats->rpthc;
1526 uint64_t old_hgptc = stats->hgptc;
1528 if(hw->phy.media_type == e1000_media_type_copper ||
1529 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1531 E1000_READ_REG(hw,E1000_SYMERRS);
1532 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1535 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1536 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1537 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1538 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1540 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1541 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1542 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1543 stats->dc += E1000_READ_REG(hw, E1000_DC);
1544 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1545 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1546 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1548 ** For watchdog management we need to know if we have been
1549 ** paused during the last interval, so capture that here.
1551 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1552 stats->xoffrxc += pause_frames;
1553 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1554 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1555 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1556 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1557 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1558 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1559 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1560 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1561 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1562 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1563 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1564 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1566 /* For the 64-bit byte counters the low dword must be read first. */
1567 /* Both registers clear on the read of the high dword */
1569 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1570 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1571 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1572 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1573 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1574 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1575 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1577 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1578 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1579 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1580 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1581 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1583 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1584 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1586 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1587 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1588 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1589 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1590 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1591 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1593 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1594 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1595 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1596 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1597 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1598 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1599 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1600 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1602 /* Interrupt Counts */
1604 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1605 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1606 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1607 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1608 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1609 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1610 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1611 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1612 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1614 /* Host to Card Statistics */
1616 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1617 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1618 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1619 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1620 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1621 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1622 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1623 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1624 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1625 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1626 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1627 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1628 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1629 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1630 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1631 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1633 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1634 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1635 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1636 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1637 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1638 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1642 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1644 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645 struct e1000_hw_stats *stats =
1646 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1648 igb_read_stats_registers(hw, stats);
1650 if (rte_stats == NULL)
1654 rte_stats->imissed = stats->mpc;
1655 rte_stats->ierrors = stats->crcerrs +
1656 stats->rlec + stats->ruc + stats->roc +
1657 stats->rxerrc + stats->algnerrc + stats->cexterr;
1660 rte_stats->oerrors = stats->ecol + stats->latecol;
1662 rte_stats->ipackets = stats->gprc;
1663 rte_stats->opackets = stats->gptc;
1664 rte_stats->ibytes = stats->gorc;
1665 rte_stats->obytes = stats->gotc;
1669 eth_igb_stats_reset(struct rte_eth_dev *dev)
1671 struct e1000_hw_stats *hw_stats =
1672 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1674 /* HW registers are cleared on read */
1675 eth_igb_stats_get(dev, NULL);
1677 /* Reset software totals */
1678 memset(hw_stats, 0, sizeof(*hw_stats));
1682 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1684 struct e1000_hw_stats *stats =
1685 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1687 /* HW registers are cleared on read */
1688 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1690 /* Reset software totals */
1691 memset(stats, 0, sizeof(*stats));
1695 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1698 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699 struct e1000_hw_stats *hw_stats =
1700 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1703 if (n < IGB_NB_XSTATS)
1704 return IGB_NB_XSTATS;
1706 igb_read_stats_registers(hw, hw_stats);
1708 /* If this is a reset xstats is NULL, and we have cleared the
1709 * registers by reading them.
1714 /* Extended stats */
1715 for (i = 0; i < IGB_NB_XSTATS; i++) {
1716 snprintf(xstats[i].name, sizeof(xstats[i].name),
1717 "%s", rte_igb_stats_strings[i].name);
1718 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1719 rte_igb_stats_strings[i].offset);
1722 return IGB_NB_XSTATS;
1726 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1728 /* Good Rx packets, include VF loopback */
1729 UPDATE_VF_STAT(E1000_VFGPRC,
1730 hw_stats->last_gprc, hw_stats->gprc);
1732 /* Good Rx octets, include VF loopback */
1733 UPDATE_VF_STAT(E1000_VFGORC,
1734 hw_stats->last_gorc, hw_stats->gorc);
1736 /* Good Tx packets, include VF loopback */
1737 UPDATE_VF_STAT(E1000_VFGPTC,
1738 hw_stats->last_gptc, hw_stats->gptc);
1740 /* Good Tx octets, include VF loopback */
1741 UPDATE_VF_STAT(E1000_VFGOTC,
1742 hw_stats->last_gotc, hw_stats->gotc);
1744 /* Rx Multicst packets */
1745 UPDATE_VF_STAT(E1000_VFMPRC,
1746 hw_stats->last_mprc, hw_stats->mprc);
1748 /* Good Rx loopback packets */
1749 UPDATE_VF_STAT(E1000_VFGPRLBC,
1750 hw_stats->last_gprlbc, hw_stats->gprlbc);
1752 /* Good Rx loopback octets */
1753 UPDATE_VF_STAT(E1000_VFGORLBC,
1754 hw_stats->last_gorlbc, hw_stats->gorlbc);
1756 /* Good Tx loopback packets */
1757 UPDATE_VF_STAT(E1000_VFGPTLBC,
1758 hw_stats->last_gptlbc, hw_stats->gptlbc);
1760 /* Good Tx loopback octets */
1761 UPDATE_VF_STAT(E1000_VFGOTLBC,
1762 hw_stats->last_gotlbc, hw_stats->gotlbc);
1766 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1769 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1771 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1774 if (n < IGBVF_NB_XSTATS)
1775 return IGBVF_NB_XSTATS;
1777 igbvf_read_stats_registers(hw, hw_stats);
1782 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1783 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1784 rte_igbvf_stats_strings[i].name);
1785 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1786 rte_igbvf_stats_strings[i].offset);
1789 return IGBVF_NB_XSTATS;
1793 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1795 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1797 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1799 igbvf_read_stats_registers(hw, hw_stats);
1801 if (rte_stats == NULL)
1804 rte_stats->ipackets = hw_stats->gprc;
1805 rte_stats->ibytes = hw_stats->gorc;
1806 rte_stats->opackets = hw_stats->gptc;
1807 rte_stats->obytes = hw_stats->gotc;
1808 rte_stats->imcasts = hw_stats->mprc;
1809 rte_stats->ilbpackets = hw_stats->gprlbc;
1810 rte_stats->ilbbytes = hw_stats->gorlbc;
1811 rte_stats->olbpackets = hw_stats->gptlbc;
1812 rte_stats->olbbytes = hw_stats->gotlbc;
1816 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1818 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1819 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1821 /* Sync HW register to the last stats */
1822 eth_igbvf_stats_get(dev, NULL);
1824 /* reset HW current stats*/
1825 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1826 offsetof(struct e1000_vf_stats, gprc));
1830 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1832 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1835 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1836 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1837 dev_info->rx_offload_capa =
1838 DEV_RX_OFFLOAD_VLAN_STRIP |
1839 DEV_RX_OFFLOAD_IPV4_CKSUM |
1840 DEV_RX_OFFLOAD_UDP_CKSUM |
1841 DEV_RX_OFFLOAD_TCP_CKSUM;
1842 dev_info->tx_offload_capa =
1843 DEV_TX_OFFLOAD_VLAN_INSERT |
1844 DEV_TX_OFFLOAD_IPV4_CKSUM |
1845 DEV_TX_OFFLOAD_UDP_CKSUM |
1846 DEV_TX_OFFLOAD_TCP_CKSUM |
1847 DEV_TX_OFFLOAD_SCTP_CKSUM |
1848 DEV_TX_OFFLOAD_TCP_TSO;
1850 switch (hw->mac.type) {
1852 dev_info->max_rx_queues = 4;
1853 dev_info->max_tx_queues = 4;
1854 dev_info->max_vmdq_pools = 0;
1858 dev_info->max_rx_queues = 16;
1859 dev_info->max_tx_queues = 16;
1860 dev_info->max_vmdq_pools = ETH_8_POOLS;
1861 dev_info->vmdq_queue_num = 16;
1865 dev_info->max_rx_queues = 8;
1866 dev_info->max_tx_queues = 8;
1867 dev_info->max_vmdq_pools = ETH_8_POOLS;
1868 dev_info->vmdq_queue_num = 8;
1872 dev_info->max_rx_queues = 8;
1873 dev_info->max_tx_queues = 8;
1874 dev_info->max_vmdq_pools = ETH_8_POOLS;
1875 dev_info->vmdq_queue_num = 8;
1879 dev_info->max_rx_queues = 8;
1880 dev_info->max_tx_queues = 8;
1884 dev_info->max_rx_queues = 4;
1885 dev_info->max_tx_queues = 4;
1886 dev_info->max_vmdq_pools = 0;
1890 dev_info->max_rx_queues = 2;
1891 dev_info->max_tx_queues = 2;
1892 dev_info->max_vmdq_pools = 0;
1896 /* Should not happen */
1899 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1900 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1901 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1903 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1905 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1906 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1907 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1909 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1913 dev_info->default_txconf = (struct rte_eth_txconf) {
1915 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1916 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1917 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1922 dev_info->rx_desc_lim = rx_desc_lim;
1923 dev_info->tx_desc_lim = tx_desc_lim;
1925 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1926 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1930 static const uint32_t *
1931 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
1933 static const uint32_t ptypes[] = {
1934 /* refers to igb_rxd_pkt_info_to_pkt_type() */
1937 RTE_PTYPE_L3_IPV4_EXT,
1939 RTE_PTYPE_L3_IPV6_EXT,
1943 RTE_PTYPE_TUNNEL_IP,
1944 RTE_PTYPE_INNER_L3_IPV6,
1945 RTE_PTYPE_INNER_L3_IPV6_EXT,
1946 RTE_PTYPE_INNER_L4_TCP,
1947 RTE_PTYPE_INNER_L4_UDP,
1951 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
1952 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
1958 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1960 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1963 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1964 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1965 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1966 DEV_RX_OFFLOAD_IPV4_CKSUM |
1967 DEV_RX_OFFLOAD_UDP_CKSUM |
1968 DEV_RX_OFFLOAD_TCP_CKSUM;
1969 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1970 DEV_TX_OFFLOAD_IPV4_CKSUM |
1971 DEV_TX_OFFLOAD_UDP_CKSUM |
1972 DEV_TX_OFFLOAD_TCP_CKSUM |
1973 DEV_TX_OFFLOAD_SCTP_CKSUM |
1974 DEV_TX_OFFLOAD_TCP_TSO;
1975 switch (hw->mac.type) {
1977 dev_info->max_rx_queues = 2;
1978 dev_info->max_tx_queues = 2;
1980 case e1000_vfadapt_i350:
1981 dev_info->max_rx_queues = 1;
1982 dev_info->max_tx_queues = 1;
1985 /* Should not happen */
1989 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1991 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1992 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1993 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1995 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1999 dev_info->default_txconf = (struct rte_eth_txconf) {
2001 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2002 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2003 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2008 dev_info->rx_desc_lim = rx_desc_lim;
2009 dev_info->tx_desc_lim = tx_desc_lim;
2012 /* return 0 means link status changed, -1 means not changed */
2014 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2016 struct e1000_hw *hw =
2017 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018 struct rte_eth_link link, old;
2019 int link_check, count;
2022 hw->mac.get_link_status = 1;
2024 /* possible wait-to-complete in up to 9 seconds */
2025 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2026 /* Read the real link status */
2027 switch (hw->phy.media_type) {
2028 case e1000_media_type_copper:
2029 /* Do the work to read phy */
2030 e1000_check_for_link(hw);
2031 link_check = !hw->mac.get_link_status;
2034 case e1000_media_type_fiber:
2035 e1000_check_for_link(hw);
2036 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2040 case e1000_media_type_internal_serdes:
2041 e1000_check_for_link(hw);
2042 link_check = hw->mac.serdes_has_link;
2045 /* VF device is type_unknown */
2046 case e1000_media_type_unknown:
2047 eth_igbvf_link_update(hw);
2048 link_check = !hw->mac.get_link_status;
2054 if (link_check || wait_to_complete == 0)
2056 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2058 memset(&link, 0, sizeof(link));
2059 rte_igb_dev_atomic_read_link_status(dev, &link);
2062 /* Now we check if a transition has happened */
2064 uint16_t duplex, speed;
2065 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2066 link.link_duplex = (duplex == FULL_DUPLEX) ?
2067 ETH_LINK_FULL_DUPLEX :
2068 ETH_LINK_HALF_DUPLEX;
2069 link.link_speed = speed;
2070 link.link_status = ETH_LINK_UP;
2071 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2072 ETH_LINK_SPEED_FIXED);
2073 } else if (!link_check) {
2074 link.link_speed = 0;
2075 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2076 link.link_status = ETH_LINK_DOWN;
2077 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2079 rte_igb_dev_atomic_write_link_status(dev, &link);
2082 if (old.link_status == link.link_status)
2090 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2091 * For ASF and Pass Through versions of f/w this means
2092 * that the driver is loaded.
2095 igb_hw_control_acquire(struct e1000_hw *hw)
2099 /* Let firmware know the driver has taken over */
2100 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2101 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2105 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2106 * For ASF and Pass Through versions of f/w this means that the
2107 * driver is no longer loaded.
2110 igb_hw_control_release(struct e1000_hw *hw)
2114 /* Let firmware taken over control of h/w */
2115 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2116 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2117 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2121 * Bit of a misnomer, what this really means is
2122 * to enable OS management of the system... aka
2123 * to disable special hardware management features.
2126 igb_init_manageability(struct e1000_hw *hw)
2128 if (e1000_enable_mng_pass_thru(hw)) {
2129 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2130 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2132 /* disable hardware interception of ARP */
2133 manc &= ~(E1000_MANC_ARP_EN);
2135 /* enable receiving management packets to the host */
2136 manc |= E1000_MANC_EN_MNG2HOST;
2137 manc2h |= 1 << 5; /* Mng Port 623 */
2138 manc2h |= 1 << 6; /* Mng Port 664 */
2139 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2140 E1000_WRITE_REG(hw, E1000_MANC, manc);
2145 igb_release_manageability(struct e1000_hw *hw)
2147 if (e1000_enable_mng_pass_thru(hw)) {
2148 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2150 manc |= E1000_MANC_ARP_EN;
2151 manc &= ~E1000_MANC_EN_MNG2HOST;
2153 E1000_WRITE_REG(hw, E1000_MANC, manc);
2158 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2160 struct e1000_hw *hw =
2161 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 rctl = E1000_READ_REG(hw, E1000_RCTL);
2165 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2166 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2170 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2172 struct e1000_hw *hw =
2173 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2176 rctl = E1000_READ_REG(hw, E1000_RCTL);
2177 rctl &= (~E1000_RCTL_UPE);
2178 if (dev->data->all_multicast == 1)
2179 rctl |= E1000_RCTL_MPE;
2181 rctl &= (~E1000_RCTL_MPE);
2182 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2186 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2188 struct e1000_hw *hw =
2189 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192 rctl = E1000_READ_REG(hw, E1000_RCTL);
2193 rctl |= E1000_RCTL_MPE;
2194 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2198 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2200 struct e1000_hw *hw =
2201 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204 if (dev->data->promiscuous == 1)
2205 return; /* must remain in all_multicast mode */
2206 rctl = E1000_READ_REG(hw, E1000_RCTL);
2207 rctl &= (~E1000_RCTL_MPE);
2208 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2212 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2214 struct e1000_hw *hw =
2215 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 struct e1000_vfta * shadow_vfta =
2217 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2222 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2223 E1000_VFTA_ENTRY_MASK);
2224 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2225 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2230 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2232 /* update local VFTA copy */
2233 shadow_vfta->vfta[vid_idx] = vfta;
2239 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2240 enum rte_vlan_type vlan_type,
2243 struct e1000_hw *hw =
2244 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245 uint32_t reg = ETHER_TYPE_VLAN;
2248 switch (vlan_type) {
2249 case ETH_VLAN_TYPE_INNER:
2250 reg |= (tpid << 16);
2251 E1000_WRITE_REG(hw, E1000_VET, reg);
2255 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
2263 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2265 struct e1000_hw *hw =
2266 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2269 /* Filter Table Disable */
2270 reg = E1000_READ_REG(hw, E1000_RCTL);
2271 reg &= ~E1000_RCTL_CFIEN;
2272 reg &= ~E1000_RCTL_VFE;
2273 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2277 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2279 struct e1000_hw *hw =
2280 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2281 struct e1000_vfta * shadow_vfta =
2282 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2286 /* Filter Table Enable, CFI not used for packet acceptance */
2287 reg = E1000_READ_REG(hw, E1000_RCTL);
2288 reg &= ~E1000_RCTL_CFIEN;
2289 reg |= E1000_RCTL_VFE;
2290 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2292 /* restore VFTA table */
2293 for (i = 0; i < IGB_VFTA_SIZE; i++)
2294 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2298 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2300 struct e1000_hw *hw =
2301 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304 /* VLAN Mode Disable */
2305 reg = E1000_READ_REG(hw, E1000_CTRL);
2306 reg &= ~E1000_CTRL_VME;
2307 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2311 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2313 struct e1000_hw *hw =
2314 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317 /* VLAN Mode Enable */
2318 reg = E1000_READ_REG(hw, E1000_CTRL);
2319 reg |= E1000_CTRL_VME;
2320 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2324 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2326 struct e1000_hw *hw =
2327 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2330 /* CTRL_EXT: Extended VLAN */
2331 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2332 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2333 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2335 /* Update maximum packet length */
2336 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2337 E1000_WRITE_REG(hw, E1000_RLPML,
2338 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2343 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2345 struct e1000_hw *hw =
2346 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2349 /* CTRL_EXT: Extended VLAN */
2350 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2351 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2352 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2354 /* Update maximum packet length */
2355 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2356 E1000_WRITE_REG(hw, E1000_RLPML,
2357 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2362 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2364 if(mask & ETH_VLAN_STRIP_MASK){
2365 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2366 igb_vlan_hw_strip_enable(dev);
2368 igb_vlan_hw_strip_disable(dev);
2371 if(mask & ETH_VLAN_FILTER_MASK){
2372 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2373 igb_vlan_hw_filter_enable(dev);
2375 igb_vlan_hw_filter_disable(dev);
2378 if(mask & ETH_VLAN_EXTEND_MASK){
2379 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2380 igb_vlan_hw_extend_enable(dev);
2382 igb_vlan_hw_extend_disable(dev);
2388 * It enables the interrupt mask and then enable the interrupt.
2391 * Pointer to struct rte_eth_dev.
2394 * - On success, zero.
2395 * - On failure, a negative value.
2398 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2400 struct e1000_interrupt *intr =
2401 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2403 intr->mask |= E1000_ICR_LSC;
2408 /* It clears the interrupt causes and enables the interrupt.
2409 * It will be called once only during nic initialized.
2412 * Pointer to struct rte_eth_dev.
2415 * - On success, zero.
2416 * - On failure, a negative value.
2418 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2420 uint32_t mask, regval;
2421 struct e1000_hw *hw =
2422 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423 struct rte_eth_dev_info dev_info;
2425 memset(&dev_info, 0, sizeof(dev_info));
2426 eth_igb_infos_get(dev, &dev_info);
2428 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2429 regval = E1000_READ_REG(hw, E1000_EIMS);
2430 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2436 * It reads ICR and gets interrupt causes, check it and set a bit flag
2437 * to update link status.
2440 * Pointer to struct rte_eth_dev.
2443 * - On success, zero.
2444 * - On failure, a negative value.
2447 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2450 struct e1000_hw *hw =
2451 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2452 struct e1000_interrupt *intr =
2453 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2455 igb_intr_disable(hw);
2457 /* read-on-clear nic registers here */
2458 icr = E1000_READ_REG(hw, E1000_ICR);
2461 if (icr & E1000_ICR_LSC) {
2462 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2465 if (icr & E1000_ICR_VMMB)
2466 intr->flags |= E1000_FLAG_MAILBOX;
2472 * It executes link_update after knowing an interrupt is prsent.
2475 * Pointer to struct rte_eth_dev.
2478 * - On success, zero.
2479 * - On failure, a negative value.
2482 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2484 struct e1000_hw *hw =
2485 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486 struct e1000_interrupt *intr =
2487 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2488 uint32_t tctl, rctl;
2489 struct rte_eth_link link;
2492 if (intr->flags & E1000_FLAG_MAILBOX) {
2493 igb_pf_mbx_process(dev);
2494 intr->flags &= ~E1000_FLAG_MAILBOX;
2497 igb_intr_enable(dev);
2498 rte_intr_enable(&(dev->pci_dev->intr_handle));
2500 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2501 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2503 /* set get_link_status to check register later */
2504 hw->mac.get_link_status = 1;
2505 ret = eth_igb_link_update(dev, 0);
2507 /* check if link has changed */
2511 memset(&link, 0, sizeof(link));
2512 rte_igb_dev_atomic_read_link_status(dev, &link);
2513 if (link.link_status) {
2515 " Port %d: Link Up - speed %u Mbps - %s",
2517 (unsigned)link.link_speed,
2518 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2519 "full-duplex" : "half-duplex");
2521 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2522 dev->data->port_id);
2525 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2526 dev->pci_dev->addr.domain,
2527 dev->pci_dev->addr.bus,
2528 dev->pci_dev->addr.devid,
2529 dev->pci_dev->addr.function);
2530 tctl = E1000_READ_REG(hw, E1000_TCTL);
2531 rctl = E1000_READ_REG(hw, E1000_RCTL);
2532 if (link.link_status) {
2534 tctl |= E1000_TCTL_EN;
2535 rctl |= E1000_RCTL_EN;
2538 tctl &= ~E1000_TCTL_EN;
2539 rctl &= ~E1000_RCTL_EN;
2541 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2542 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2543 E1000_WRITE_FLUSH(hw);
2544 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2551 * Interrupt handler which shall be registered at first.
2554 * Pointer to interrupt handle.
2556 * The address of parameter (struct rte_eth_dev *) regsitered before.
2562 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2565 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2567 eth_igb_interrupt_get_status(dev);
2568 eth_igb_interrupt_action(dev);
2572 eth_igb_led_on(struct rte_eth_dev *dev)
2574 struct e1000_hw *hw;
2576 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2577 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2581 eth_igb_led_off(struct rte_eth_dev *dev)
2583 struct e1000_hw *hw;
2585 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2590 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2592 struct e1000_hw *hw;
2597 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2598 fc_conf->pause_time = hw->fc.pause_time;
2599 fc_conf->high_water = hw->fc.high_water;
2600 fc_conf->low_water = hw->fc.low_water;
2601 fc_conf->send_xon = hw->fc.send_xon;
2602 fc_conf->autoneg = hw->mac.autoneg;
2605 * Return rx_pause and tx_pause status according to actual setting of
2606 * the TFCE and RFCE bits in the CTRL register.
2608 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2609 if (ctrl & E1000_CTRL_TFCE)
2614 if (ctrl & E1000_CTRL_RFCE)
2619 if (rx_pause && tx_pause)
2620 fc_conf->mode = RTE_FC_FULL;
2622 fc_conf->mode = RTE_FC_RX_PAUSE;
2624 fc_conf->mode = RTE_FC_TX_PAUSE;
2626 fc_conf->mode = RTE_FC_NONE;
2632 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2634 struct e1000_hw *hw;
2636 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2642 uint32_t rx_buf_size;
2643 uint32_t max_high_water;
2646 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647 if (fc_conf->autoneg != hw->mac.autoneg)
2649 rx_buf_size = igb_get_rx_buffer_size(hw);
2650 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2652 /* At least reserve one Ethernet frame for watermark */
2653 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2654 if ((fc_conf->high_water > max_high_water) ||
2655 (fc_conf->high_water < fc_conf->low_water)) {
2656 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2657 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2661 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2662 hw->fc.pause_time = fc_conf->pause_time;
2663 hw->fc.high_water = fc_conf->high_water;
2664 hw->fc.low_water = fc_conf->low_water;
2665 hw->fc.send_xon = fc_conf->send_xon;
2667 err = e1000_setup_link_generic(hw);
2668 if (err == E1000_SUCCESS) {
2670 /* check if we want to forward MAC frames - driver doesn't have native
2671 * capability to do that, so we'll write the registers ourselves */
2673 rctl = E1000_READ_REG(hw, E1000_RCTL);
2675 /* set or clear MFLCN.PMCF bit depending on configuration */
2676 if (fc_conf->mac_ctrl_frame_fwd != 0)
2677 rctl |= E1000_RCTL_PMCF;
2679 rctl &= ~E1000_RCTL_PMCF;
2681 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2682 E1000_WRITE_FLUSH(hw);
2687 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2691 #define E1000_RAH_POOLSEL_SHIFT (18)
2693 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2694 uint32_t index, __rte_unused uint32_t pool)
2696 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2699 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2700 rah = E1000_READ_REG(hw, E1000_RAH(index));
2701 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2702 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2706 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2708 uint8_t addr[ETHER_ADDR_LEN];
2709 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2711 memset(addr, 0, sizeof(addr));
2713 e1000_rar_set(hw, addr, index);
2717 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2718 struct ether_addr *addr)
2720 eth_igb_rar_clear(dev, 0);
2722 eth_igb_rar_set(dev, (void *)addr, 0, 0);
2725 * Virtual Function operations
2728 igbvf_intr_disable(struct e1000_hw *hw)
2730 PMD_INIT_FUNC_TRACE();
2732 /* Clear interrupt mask to stop from interrupts being generated */
2733 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2735 E1000_WRITE_FLUSH(hw);
2739 igbvf_stop_adapter(struct rte_eth_dev *dev)
2743 struct rte_eth_dev_info dev_info;
2744 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2746 memset(&dev_info, 0, sizeof(dev_info));
2747 eth_igbvf_infos_get(dev, &dev_info);
2749 /* Clear interrupt mask to stop from interrupts being generated */
2750 igbvf_intr_disable(hw);
2752 /* Clear any pending interrupts, flush previous writes */
2753 E1000_READ_REG(hw, E1000_EICR);
2755 /* Disable the transmit unit. Each queue must be disabled. */
2756 for (i = 0; i < dev_info.max_tx_queues; i++)
2757 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2759 /* Disable the receive unit by stopping each queue */
2760 for (i = 0; i < dev_info.max_rx_queues; i++) {
2761 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2762 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2763 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2764 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2768 /* flush all queues disables */
2769 E1000_WRITE_FLUSH(hw);
2773 static int eth_igbvf_link_update(struct e1000_hw *hw)
2775 struct e1000_mbx_info *mbx = &hw->mbx;
2776 struct e1000_mac_info *mac = &hw->mac;
2777 int ret_val = E1000_SUCCESS;
2779 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2782 * We only want to run this if there has been a rst asserted.
2783 * in this case that could mean a link change, device reset,
2784 * or a virtual function reset
2787 /* If we were hit with a reset or timeout drop the link */
2788 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2789 mac->get_link_status = TRUE;
2791 if (!mac->get_link_status)
2794 /* if link status is down no point in checking to see if pf is up */
2795 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2798 /* if we passed all the tests above then the link is up and we no
2799 * longer need to check for link */
2800 mac->get_link_status = FALSE;
2808 igbvf_dev_configure(struct rte_eth_dev *dev)
2810 struct rte_eth_conf* conf = &dev->data->dev_conf;
2812 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2813 dev->data->port_id);
2816 * VF has no ability to enable/disable HW CRC
2817 * Keep the persistent behavior the same as Host PF
2819 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2820 if (!conf->rxmode.hw_strip_crc) {
2821 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2822 conf->rxmode.hw_strip_crc = 1;
2825 if (conf->rxmode.hw_strip_crc) {
2826 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2827 conf->rxmode.hw_strip_crc = 0;
2835 igbvf_dev_start(struct rte_eth_dev *dev)
2837 struct e1000_hw *hw =
2838 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839 struct e1000_adapter *adapter =
2840 E1000_DEV_PRIVATE(dev->data->dev_private);
2843 PMD_INIT_FUNC_TRACE();
2845 hw->mac.ops.reset_hw(hw);
2846 adapter->stopped = 0;
2849 igbvf_set_vfta_all(dev,1);
2851 eth_igbvf_tx_init(dev);
2853 /* This can fail when allocating mbufs for descriptor rings */
2854 ret = eth_igbvf_rx_init(dev);
2856 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2857 igb_dev_clear_queues(dev);
2865 igbvf_dev_stop(struct rte_eth_dev *dev)
2867 PMD_INIT_FUNC_TRACE();
2869 igbvf_stop_adapter(dev);
2872 * Clear what we set, but we still keep shadow_vfta to
2873 * restore after device starts
2875 igbvf_set_vfta_all(dev,0);
2877 igb_dev_clear_queues(dev);
2881 igbvf_dev_close(struct rte_eth_dev *dev)
2883 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884 struct e1000_adapter *adapter =
2885 E1000_DEV_PRIVATE(dev->data->dev_private);
2886 struct ether_addr addr;
2888 PMD_INIT_FUNC_TRACE();
2892 igbvf_dev_stop(dev);
2893 adapter->stopped = 1;
2894 igb_dev_free_queues(dev);
2897 * reprogram the RAR with a zero mac address,
2898 * to ensure that the VF traffic goes to the PF
2899 * after stop, close and detach of the VF.
2902 memset(&addr, 0, sizeof(addr));
2903 igbvf_default_mac_addr_set(dev, &addr);
2907 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
2909 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2911 /* Set both unicast and multicast promisc */
2912 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
2916 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
2918 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920 /* If in allmulticast mode leave multicast promisc */
2921 if (dev->data->all_multicast == 1)
2922 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2924 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2928 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
2930 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2932 /* In promiscuous mode multicast promisc already set */
2933 if (dev->data->promiscuous == 0)
2934 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2938 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
2940 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942 /* In promiscuous mode leave multicast promisc enabled */
2943 if (dev->data->promiscuous == 0)
2944 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2947 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2949 struct e1000_mbx_info *mbx = &hw->mbx;
2953 /* After set vlan, vlan strip will also be enabled in igb driver*/
2954 msgbuf[0] = E1000_VF_SET_VLAN;
2956 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2958 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2960 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2964 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2968 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2969 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2976 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2978 struct e1000_hw *hw =
2979 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2980 struct e1000_vfta * shadow_vfta =
2981 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2982 int i = 0, j = 0, vfta = 0, mask = 1;
2984 for (i = 0; i < IGB_VFTA_SIZE; i++){
2985 vfta = shadow_vfta->vfta[i];
2988 for (j = 0; j < 32; j++){
2991 (uint16_t)((i<<5)+j), on);
3000 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3002 struct e1000_hw *hw =
3003 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004 struct e1000_vfta * shadow_vfta =
3005 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3006 uint32_t vid_idx = 0;
3007 uint32_t vid_bit = 0;
3010 PMD_INIT_FUNC_TRACE();
3012 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3013 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3015 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3018 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3019 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3021 /*Save what we set and retore it after device reset*/
3023 shadow_vfta->vfta[vid_idx] |= vid_bit;
3025 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3031 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3033 struct e1000_hw *hw =
3034 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3036 /* index is not used by rar_set() */
3037 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3042 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3043 struct rte_eth_rss_reta_entry64 *reta_conf,
3048 uint16_t idx, shift;
3049 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3051 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3052 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3053 "(%d) doesn't match the number hardware can supported "
3054 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3058 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3059 idx = i / RTE_RETA_GROUP_SIZE;
3060 shift = i % RTE_RETA_GROUP_SIZE;
3061 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3065 if (mask == IGB_4_BIT_MASK)
3068 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3069 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3070 if (mask & (0x1 << j))
3071 reta |= reta_conf[idx].reta[shift + j] <<
3074 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3076 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3083 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3084 struct rte_eth_rss_reta_entry64 *reta_conf,
3089 uint16_t idx, shift;
3090 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3092 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3093 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3094 "(%d) doesn't match the number hardware can supported "
3095 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3099 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3100 idx = i / RTE_RETA_GROUP_SIZE;
3101 shift = i % RTE_RETA_GROUP_SIZE;
3102 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3106 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3107 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3108 if (mask & (0x1 << j))
3109 reta_conf[idx].reta[shift + j] =
3110 ((reta >> (CHAR_BIT * j)) &
3118 #define MAC_TYPE_FILTER_SUP(type) do {\
3119 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3120 (type) != e1000_82576)\
3125 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3126 struct rte_eth_syn_filter *filter,
3129 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130 uint32_t synqf, rfctl;
3132 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3135 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3138 if (synqf & E1000_SYN_FILTER_ENABLE)
3141 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3142 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3144 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3145 if (filter->hig_pri)
3146 rfctl |= E1000_RFCTL_SYNQFP;
3148 rfctl &= ~E1000_RFCTL_SYNQFP;
3150 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3152 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3157 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3158 E1000_WRITE_FLUSH(hw);
3163 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3164 struct rte_eth_syn_filter *filter)
3166 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167 uint32_t synqf, rfctl;
3169 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3170 if (synqf & E1000_SYN_FILTER_ENABLE) {
3171 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3172 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3173 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3174 E1000_SYN_FILTER_QUEUE_SHIFT);
3182 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3183 enum rte_filter_op filter_op,
3186 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3189 MAC_TYPE_FILTER_SUP(hw->mac.type);
3191 if (filter_op == RTE_ETH_FILTER_NOP)
3195 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3200 switch (filter_op) {
3201 case RTE_ETH_FILTER_ADD:
3202 ret = eth_igb_syn_filter_set(dev,
3203 (struct rte_eth_syn_filter *)arg,
3206 case RTE_ETH_FILTER_DELETE:
3207 ret = eth_igb_syn_filter_set(dev,
3208 (struct rte_eth_syn_filter *)arg,
3211 case RTE_ETH_FILTER_GET:
3212 ret = eth_igb_syn_filter_get(dev,
3213 (struct rte_eth_syn_filter *)arg);
3216 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3224 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3225 if ((type) != e1000_82580 && (type) != e1000_i350)\
3229 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3231 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3232 struct e1000_2tuple_filter_info *filter_info)
3234 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3236 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3237 return -EINVAL; /* filter index is out of range. */
3238 if (filter->tcp_flags > TCP_FLAG_ALL)
3239 return -EINVAL; /* flags is invalid. */
3241 switch (filter->dst_port_mask) {
3243 filter_info->dst_port_mask = 0;
3244 filter_info->dst_port = filter->dst_port;
3247 filter_info->dst_port_mask = 1;
3250 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3254 switch (filter->proto_mask) {
3256 filter_info->proto_mask = 0;
3257 filter_info->proto = filter->proto;
3260 filter_info->proto_mask = 1;
3263 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3267 filter_info->priority = (uint8_t)filter->priority;
3268 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3269 filter_info->tcp_flags = filter->tcp_flags;
3271 filter_info->tcp_flags = 0;
3276 static inline struct e1000_2tuple_filter *
3277 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3278 struct e1000_2tuple_filter_info *key)
3280 struct e1000_2tuple_filter *it;
3282 TAILQ_FOREACH(it, filter_list, entries) {
3283 if (memcmp(key, &it->filter_info,
3284 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3292 * igb_add_2tuple_filter - add a 2tuple filter
3295 * dev: Pointer to struct rte_eth_dev.
3296 * ntuple_filter: ponter to the filter that will be added.
3299 * - On success, zero.
3300 * - On failure, a negative value.
3303 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3304 struct rte_eth_ntuple_filter *ntuple_filter)
3306 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307 struct e1000_filter_info *filter_info =
3308 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3309 struct e1000_2tuple_filter *filter;
3310 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3311 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3314 filter = rte_zmalloc("e1000_2tuple_filter",
3315 sizeof(struct e1000_2tuple_filter), 0);
3319 ret = ntuple_filter_to_2tuple(ntuple_filter,
3320 &filter->filter_info);
3325 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3326 &filter->filter_info) != NULL) {
3327 PMD_DRV_LOG(ERR, "filter exists.");
3331 filter->queue = ntuple_filter->queue;
3334 * look for an unused 2tuple filter index,
3335 * and insert the filter to list.
3337 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3338 if (!(filter_info->twotuple_mask & (1 << i))) {
3339 filter_info->twotuple_mask |= 1 << i;
3341 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3347 if (i >= E1000_MAX_TTQF_FILTERS) {
3348 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3353 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3354 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3355 imir |= E1000_IMIR_PORT_BP;
3357 imir &= ~E1000_IMIR_PORT_BP;
3359 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3361 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3362 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3363 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3364 if (filter->filter_info.proto_mask == 0)
3365 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3367 /* tcp flags bits setting. */
3368 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3369 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3370 imir_ext |= E1000_IMIREXT_CTRL_URG;
3371 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3372 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3373 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3374 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3375 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3376 imir_ext |= E1000_IMIREXT_CTRL_RST;
3377 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3378 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3379 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3380 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3382 imir_ext |= E1000_IMIREXT_CTRL_BP;
3383 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3384 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3385 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3390 * igb_remove_2tuple_filter - remove a 2tuple filter
3393 * dev: Pointer to struct rte_eth_dev.
3394 * ntuple_filter: ponter to the filter that will be removed.
3397 * - On success, zero.
3398 * - On failure, a negative value.
3401 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3402 struct rte_eth_ntuple_filter *ntuple_filter)
3404 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405 struct e1000_filter_info *filter_info =
3406 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3407 struct e1000_2tuple_filter_info filter_2tuple;
3408 struct e1000_2tuple_filter *filter;
3411 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3412 ret = ntuple_filter_to_2tuple(ntuple_filter,
3417 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3419 if (filter == NULL) {
3420 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3424 filter_info->twotuple_mask &= ~(1 << filter->index);
3425 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3428 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3429 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3430 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3434 static inline struct e1000_flex_filter *
3435 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3436 struct e1000_flex_filter_info *key)
3438 struct e1000_flex_filter *it;
3440 TAILQ_FOREACH(it, filter_list, entries) {
3441 if (memcmp(key, &it->filter_info,
3442 sizeof(struct e1000_flex_filter_info)) == 0)
3450 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3451 struct rte_eth_flex_filter *filter,
3454 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3455 struct e1000_filter_info *filter_info =
3456 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3457 struct e1000_flex_filter *flex_filter, *it;
3458 uint32_t wufc, queueing, mask;
3460 uint8_t shift, i, j = 0;
3462 flex_filter = rte_zmalloc("e1000_flex_filter",
3463 sizeof(struct e1000_flex_filter), 0);
3464 if (flex_filter == NULL)
3467 flex_filter->filter_info.len = filter->len;
3468 flex_filter->filter_info.priority = filter->priority;
3469 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3470 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3472 /* reverse bits in flex filter's mask*/
3473 for (shift = 0; shift < CHAR_BIT; shift++) {
3474 if (filter->mask[i] & (0x01 << shift))
3475 mask |= (0x80 >> shift);
3477 flex_filter->filter_info.mask[i] = mask;
3480 wufc = E1000_READ_REG(hw, E1000_WUFC);
3481 if (flex_filter->index < E1000_MAX_FHFT)
3482 reg_off = E1000_FHFT(flex_filter->index);
3484 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3487 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3488 &flex_filter->filter_info) != NULL) {
3489 PMD_DRV_LOG(ERR, "filter exists.");
3490 rte_free(flex_filter);
3493 flex_filter->queue = filter->queue;
3495 * look for an unused flex filter index
3496 * and insert the filter into the list.
3498 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3499 if (!(filter_info->flex_mask & (1 << i))) {
3500 filter_info->flex_mask |= 1 << i;
3501 flex_filter->index = i;
3502 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3508 if (i >= E1000_MAX_FLEX_FILTERS) {
3509 PMD_DRV_LOG(ERR, "flex filters are full.");
3510 rte_free(flex_filter);
3514 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3515 (E1000_WUFC_FLX0 << flex_filter->index));
3516 queueing = filter->len |
3517 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3518 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3519 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3521 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3522 E1000_WRITE_REG(hw, reg_off,
3523 flex_filter->filter_info.dwords[j]);
3524 reg_off += sizeof(uint32_t);
3525 E1000_WRITE_REG(hw, reg_off,
3526 flex_filter->filter_info.dwords[++j]);
3527 reg_off += sizeof(uint32_t);
3528 E1000_WRITE_REG(hw, reg_off,
3529 (uint32_t)flex_filter->filter_info.mask[i]);
3530 reg_off += sizeof(uint32_t) * 2;
3534 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3535 &flex_filter->filter_info);
3537 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3538 rte_free(flex_filter);
3542 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3543 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3544 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3545 (~(E1000_WUFC_FLX0 << it->index)));
3547 filter_info->flex_mask &= ~(1 << it->index);
3548 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3550 rte_free(flex_filter);
3557 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3558 struct rte_eth_flex_filter *filter)
3560 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561 struct e1000_filter_info *filter_info =
3562 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3563 struct e1000_flex_filter flex_filter, *it;
3564 uint32_t wufc, queueing, wufc_en = 0;
3566 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3567 flex_filter.filter_info.len = filter->len;
3568 flex_filter.filter_info.priority = filter->priority;
3569 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3570 memcpy(flex_filter.filter_info.mask, filter->mask,
3571 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3573 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3574 &flex_filter.filter_info);
3576 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3580 wufc = E1000_READ_REG(hw, E1000_WUFC);
3581 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3583 if ((wufc & wufc_en) == wufc_en) {
3584 uint32_t reg_off = 0;
3585 if (it->index < E1000_MAX_FHFT)
3586 reg_off = E1000_FHFT(it->index);
3588 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3590 queueing = E1000_READ_REG(hw,
3591 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3592 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3593 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3594 E1000_FHFT_QUEUEING_PRIO_SHIFT;
3595 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3596 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3603 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3604 enum rte_filter_op filter_op,
3607 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608 struct rte_eth_flex_filter *filter;
3611 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3613 if (filter_op == RTE_ETH_FILTER_NOP)
3617 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3622 filter = (struct rte_eth_flex_filter *)arg;
3623 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3624 || filter->len % sizeof(uint64_t) != 0) {
3625 PMD_DRV_LOG(ERR, "filter's length is out of range");
3628 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3629 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3633 switch (filter_op) {
3634 case RTE_ETH_FILTER_ADD:
3635 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3637 case RTE_ETH_FILTER_DELETE:
3638 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3640 case RTE_ETH_FILTER_GET:
3641 ret = eth_igb_get_flex_filter(dev, filter);
3644 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3652 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3654 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3655 struct e1000_5tuple_filter_info *filter_info)
3657 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3659 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3660 return -EINVAL; /* filter index is out of range. */
3661 if (filter->tcp_flags > TCP_FLAG_ALL)
3662 return -EINVAL; /* flags is invalid. */
3664 switch (filter->dst_ip_mask) {
3666 filter_info->dst_ip_mask = 0;
3667 filter_info->dst_ip = filter->dst_ip;
3670 filter_info->dst_ip_mask = 1;
3673 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3677 switch (filter->src_ip_mask) {
3679 filter_info->src_ip_mask = 0;
3680 filter_info->src_ip = filter->src_ip;
3683 filter_info->src_ip_mask = 1;
3686 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3690 switch (filter->dst_port_mask) {
3692 filter_info->dst_port_mask = 0;
3693 filter_info->dst_port = filter->dst_port;
3696 filter_info->dst_port_mask = 1;
3699 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3703 switch (filter->src_port_mask) {
3705 filter_info->src_port_mask = 0;
3706 filter_info->src_port = filter->src_port;
3709 filter_info->src_port_mask = 1;
3712 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3716 switch (filter->proto_mask) {
3718 filter_info->proto_mask = 0;
3719 filter_info->proto = filter->proto;
3722 filter_info->proto_mask = 1;
3725 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3729 filter_info->priority = (uint8_t)filter->priority;
3730 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3731 filter_info->tcp_flags = filter->tcp_flags;
3733 filter_info->tcp_flags = 0;
3738 static inline struct e1000_5tuple_filter *
3739 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3740 struct e1000_5tuple_filter_info *key)
3742 struct e1000_5tuple_filter *it;
3744 TAILQ_FOREACH(it, filter_list, entries) {
3745 if (memcmp(key, &it->filter_info,
3746 sizeof(struct e1000_5tuple_filter_info)) == 0) {
3754 * igb_add_5tuple_filter_82576 - add a 5tuple filter
3757 * dev: Pointer to struct rte_eth_dev.
3758 * ntuple_filter: ponter to the filter that will be added.
3761 * - On success, zero.
3762 * - On failure, a negative value.
3765 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3766 struct rte_eth_ntuple_filter *ntuple_filter)
3768 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3769 struct e1000_filter_info *filter_info =
3770 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3771 struct e1000_5tuple_filter *filter;
3772 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3773 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3777 filter = rte_zmalloc("e1000_5tuple_filter",
3778 sizeof(struct e1000_5tuple_filter), 0);
3782 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3783 &filter->filter_info);
3789 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3790 &filter->filter_info) != NULL) {
3791 PMD_DRV_LOG(ERR, "filter exists.");
3795 filter->queue = ntuple_filter->queue;
3798 * look for an unused 5tuple filter index,
3799 * and insert the filter to list.
3801 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3802 if (!(filter_info->fivetuple_mask & (1 << i))) {
3803 filter_info->fivetuple_mask |= 1 << i;
3805 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3811 if (i >= E1000_MAX_FTQF_FILTERS) {
3812 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3817 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3818 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3819 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3820 if (filter->filter_info.dst_ip_mask == 0)
3821 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3822 if (filter->filter_info.src_port_mask == 0)
3823 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3824 if (filter->filter_info.proto_mask == 0)
3825 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3826 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3827 E1000_FTQF_QUEUE_MASK;
3828 ftqf |= E1000_FTQF_QUEUE_ENABLE;
3829 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3830 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3831 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3833 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3834 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3836 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3837 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3838 imir |= E1000_IMIR_PORT_BP;
3840 imir &= ~E1000_IMIR_PORT_BP;
3841 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3843 /* tcp flags bits setting. */
3844 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3845 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3846 imir_ext |= E1000_IMIREXT_CTRL_URG;
3847 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3848 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3849 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3850 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3851 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3852 imir_ext |= E1000_IMIREXT_CTRL_RST;
3853 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3854 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3855 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3856 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3858 imir_ext |= E1000_IMIREXT_CTRL_BP;
3859 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3860 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3865 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3868 * dev: Pointer to struct rte_eth_dev.
3869 * ntuple_filter: ponter to the filter that will be removed.
3872 * - On success, zero.
3873 * - On failure, a negative value.
3876 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3877 struct rte_eth_ntuple_filter *ntuple_filter)
3879 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3880 struct e1000_filter_info *filter_info =
3881 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3882 struct e1000_5tuple_filter_info filter_5tuple;
3883 struct e1000_5tuple_filter *filter;
3886 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3887 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3892 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3894 if (filter == NULL) {
3895 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3899 filter_info->fivetuple_mask &= ~(1 << filter->index);
3900 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3903 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3904 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3905 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3906 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3907 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3908 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3909 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3914 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3917 struct e1000_hw *hw;
3918 struct rte_eth_dev_info dev_info;
3919 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3922 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3924 #ifdef RTE_LIBRTE_82571_SUPPORT
3925 /* XXX: not bigger than max_rx_pktlen */
3926 if (hw->mac.type == e1000_82571)
3929 eth_igb_infos_get(dev, &dev_info);
3931 /* check that mtu is within the allowed range */
3932 if ((mtu < ETHER_MIN_MTU) ||
3933 (frame_size > dev_info.max_rx_pktlen))
3936 /* refuse mtu that requires the support of scattered packets when this
3937 * feature has not been enabled before. */
3938 if (!dev->data->scattered_rx &&
3939 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3942 rctl = E1000_READ_REG(hw, E1000_RCTL);
3944 /* switch to jumbo mode if needed */
3945 if (frame_size > ETHER_MAX_LEN) {
3946 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3947 rctl |= E1000_RCTL_LPE;
3949 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3950 rctl &= ~E1000_RCTL_LPE;
3952 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3954 /* update max frame size */
3955 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3957 E1000_WRITE_REG(hw, E1000_RLPML,
3958 dev->data->dev_conf.rxmode.max_rx_pkt_len);
3964 * igb_add_del_ntuple_filter - add or delete a ntuple filter
3967 * dev: Pointer to struct rte_eth_dev.
3968 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3969 * add: if true, add filter, if false, remove filter
3972 * - On success, zero.
3973 * - On failure, a negative value.
3976 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3977 struct rte_eth_ntuple_filter *ntuple_filter,
3980 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3983 switch (ntuple_filter->flags) {
3984 case RTE_5TUPLE_FLAGS:
3985 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3986 if (hw->mac.type != e1000_82576)
3989 ret = igb_add_5tuple_filter_82576(dev,
3992 ret = igb_remove_5tuple_filter_82576(dev,
3995 case RTE_2TUPLE_FLAGS:
3996 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3997 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4000 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4002 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4013 * igb_get_ntuple_filter - get a ntuple filter
4016 * dev: Pointer to struct rte_eth_dev.
4017 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4020 * - On success, zero.
4021 * - On failure, a negative value.
4024 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4025 struct rte_eth_ntuple_filter *ntuple_filter)
4027 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4028 struct e1000_filter_info *filter_info =
4029 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4030 struct e1000_5tuple_filter_info filter_5tuple;
4031 struct e1000_2tuple_filter_info filter_2tuple;
4032 struct e1000_5tuple_filter *p_5tuple_filter;
4033 struct e1000_2tuple_filter *p_2tuple_filter;
4036 switch (ntuple_filter->flags) {
4037 case RTE_5TUPLE_FLAGS:
4038 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4039 if (hw->mac.type != e1000_82576)
4041 memset(&filter_5tuple,
4043 sizeof(struct e1000_5tuple_filter_info));
4044 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4048 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4049 &filter_info->fivetuple_list,
4051 if (p_5tuple_filter == NULL) {
4052 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4055 ntuple_filter->queue = p_5tuple_filter->queue;
4057 case RTE_2TUPLE_FLAGS:
4058 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4059 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4061 memset(&filter_2tuple,
4063 sizeof(struct e1000_2tuple_filter_info));
4064 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4067 p_2tuple_filter = igb_2tuple_filter_lookup(
4068 &filter_info->twotuple_list,
4070 if (p_2tuple_filter == NULL) {
4071 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4074 ntuple_filter->queue = p_2tuple_filter->queue;
4085 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4086 * @dev: pointer to rte_eth_dev structure
4087 * @filter_op:operation will be taken.
4088 * @arg: a pointer to specific structure corresponding to the filter_op
4091 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4092 enum rte_filter_op filter_op,
4095 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4098 MAC_TYPE_FILTER_SUP(hw->mac.type);
4100 if (filter_op == RTE_ETH_FILTER_NOP)
4104 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4109 switch (filter_op) {
4110 case RTE_ETH_FILTER_ADD:
4111 ret = igb_add_del_ntuple_filter(dev,
4112 (struct rte_eth_ntuple_filter *)arg,
4115 case RTE_ETH_FILTER_DELETE:
4116 ret = igb_add_del_ntuple_filter(dev,
4117 (struct rte_eth_ntuple_filter *)arg,
4120 case RTE_ETH_FILTER_GET:
4121 ret = igb_get_ntuple_filter(dev,
4122 (struct rte_eth_ntuple_filter *)arg);
4125 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4133 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4138 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4139 if (filter_info->ethertype_filters[i] == ethertype &&
4140 (filter_info->ethertype_mask & (1 << i)))
4147 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4152 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4153 if (!(filter_info->ethertype_mask & (1 << i))) {
4154 filter_info->ethertype_mask |= 1 << i;
4155 filter_info->ethertype_filters[i] = ethertype;
4163 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4166 if (idx >= E1000_MAX_ETQF_FILTERS)
4168 filter_info->ethertype_mask &= ~(1 << idx);
4169 filter_info->ethertype_filters[idx] = 0;
4175 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4176 struct rte_eth_ethertype_filter *filter,
4179 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4180 struct e1000_filter_info *filter_info =
4181 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4185 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4186 filter->ether_type == ETHER_TYPE_IPv6) {
4187 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4188 " ethertype filter.", filter->ether_type);
4192 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4193 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4196 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4197 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4201 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4202 if (ret >= 0 && add) {
4203 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4204 filter->ether_type);
4207 if (ret < 0 && !add) {
4208 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4209 filter->ether_type);
4214 ret = igb_ethertype_filter_insert(filter_info,
4215 filter->ether_type);
4217 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4221 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4222 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4223 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4225 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4229 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4230 E1000_WRITE_FLUSH(hw);
4236 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4237 struct rte_eth_ethertype_filter *filter)
4239 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4240 struct e1000_filter_info *filter_info =
4241 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4245 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4247 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4248 filter->ether_type);
4252 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4253 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4254 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4256 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4257 E1000_ETQF_QUEUE_SHIFT;
4265 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4266 * @dev: pointer to rte_eth_dev structure
4267 * @filter_op:operation will be taken.
4268 * @arg: a pointer to specific structure corresponding to the filter_op
4271 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4272 enum rte_filter_op filter_op,
4275 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4278 MAC_TYPE_FILTER_SUP(hw->mac.type);
4280 if (filter_op == RTE_ETH_FILTER_NOP)
4284 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4289 switch (filter_op) {
4290 case RTE_ETH_FILTER_ADD:
4291 ret = igb_add_del_ethertype_filter(dev,
4292 (struct rte_eth_ethertype_filter *)arg,
4295 case RTE_ETH_FILTER_DELETE:
4296 ret = igb_add_del_ethertype_filter(dev,
4297 (struct rte_eth_ethertype_filter *)arg,
4300 case RTE_ETH_FILTER_GET:
4301 ret = igb_get_ethertype_filter(dev,
4302 (struct rte_eth_ethertype_filter *)arg);
4305 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4313 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4314 enum rte_filter_type filter_type,
4315 enum rte_filter_op filter_op,
4320 switch (filter_type) {
4321 case RTE_ETH_FILTER_NTUPLE:
4322 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4324 case RTE_ETH_FILTER_ETHERTYPE:
4325 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4327 case RTE_ETH_FILTER_SYN:
4328 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4330 case RTE_ETH_FILTER_FLEXIBLE:
4331 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4334 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4343 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4344 struct ether_addr *mc_addr_set,
4345 uint32_t nb_mc_addr)
4347 struct e1000_hw *hw;
4349 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4350 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4355 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4357 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358 uint64_t systime_cycles;
4360 switch (hw->mac.type) {
4364 * Need to read System Time Residue Register to be able
4365 * to read the other two registers.
4367 E1000_READ_REG(hw, E1000_SYSTIMR);
4368 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4369 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4370 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4377 * Need to read System Time Residue Register to be able
4378 * to read the other two registers.
4380 E1000_READ_REG(hw, E1000_SYSTIMR);
4381 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4382 /* Only the 8 LSB are valid. */
4383 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4387 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4388 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4393 return systime_cycles;
4397 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4399 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400 uint64_t rx_tstamp_cycles;
4402 switch (hw->mac.type) {
4405 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4406 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4407 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4413 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4414 /* Only the 8 LSB are valid. */
4415 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4419 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4420 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4425 return rx_tstamp_cycles;
4429 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4431 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4432 uint64_t tx_tstamp_cycles;
4434 switch (hw->mac.type) {
4437 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4438 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4439 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4445 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4446 /* Only the 8 LSB are valid. */
4447 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4451 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4452 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4457 return tx_tstamp_cycles;
4461 igb_start_timecounters(struct rte_eth_dev *dev)
4463 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4464 struct e1000_adapter *adapter =
4465 (struct e1000_adapter *)dev->data->dev_private;
4466 uint32_t incval = 1;
4468 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4470 switch (hw->mac.type) {
4474 /* 32 LSB bits + 8 MSB bits = 40 bits */
4475 mask = (1ULL << 40) - 1;
4480 * Start incrementing the register
4481 * used to timestamp PTP packets.
4483 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4486 incval = E1000_INCVALUE_82576;
4487 shift = IGB_82576_TSYNC_SHIFT;
4488 E1000_WRITE_REG(hw, E1000_TIMINCA,
4489 E1000_INCPERIOD_82576 | incval);
4496 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4497 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4498 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4500 adapter->systime_tc.cc_mask = mask;
4501 adapter->systime_tc.cc_shift = shift;
4502 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4504 adapter->rx_tstamp_tc.cc_mask = mask;
4505 adapter->rx_tstamp_tc.cc_shift = shift;
4506 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4508 adapter->tx_tstamp_tc.cc_mask = mask;
4509 adapter->tx_tstamp_tc.cc_shift = shift;
4510 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4514 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4516 struct e1000_adapter *adapter =
4517 (struct e1000_adapter *)dev->data->dev_private;
4519 adapter->systime_tc.nsec += delta;
4520 adapter->rx_tstamp_tc.nsec += delta;
4521 adapter->tx_tstamp_tc.nsec += delta;
4527 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4530 struct e1000_adapter *adapter =
4531 (struct e1000_adapter *)dev->data->dev_private;
4533 ns = rte_timespec_to_ns(ts);
4535 /* Set the timecounters to a new value. */
4536 adapter->systime_tc.nsec = ns;
4537 adapter->rx_tstamp_tc.nsec = ns;
4538 adapter->tx_tstamp_tc.nsec = ns;
4544 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4546 uint64_t ns, systime_cycles;
4547 struct e1000_adapter *adapter =
4548 (struct e1000_adapter *)dev->data->dev_private;
4550 systime_cycles = igb_read_systime_cyclecounter(dev);
4551 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4552 *ts = rte_ns_to_timespec(ns);
4558 igb_timesync_enable(struct rte_eth_dev *dev)
4560 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564 /* Stop the timesync system time. */
4565 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4566 /* Reset the timesync system time value. */
4567 switch (hw->mac.type) {
4573 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4576 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4577 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4580 /* Not supported. */
4584 /* Enable system time for it isn't on by default. */
4585 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4586 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4587 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4589 igb_start_timecounters(dev);
4591 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4592 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4594 E1000_ETQF_FILTER_ENABLE |
4597 /* Enable timestamping of received PTP packets. */
4598 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4599 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4600 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4602 /* Enable Timestamping of transmitted PTP packets. */
4603 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4604 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4605 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4611 igb_timesync_disable(struct rte_eth_dev *dev)
4613 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616 /* Disable timestamping of transmitted PTP packets. */
4617 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4618 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4619 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4621 /* Disable timestamping of received PTP packets. */
4622 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4623 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4624 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4626 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4627 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4629 /* Stop incrementating the System Time registers. */
4630 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4636 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4637 struct timespec *timestamp,
4638 uint32_t flags __rte_unused)
4640 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641 struct e1000_adapter *adapter =
4642 (struct e1000_adapter *)dev->data->dev_private;
4643 uint32_t tsync_rxctl;
4644 uint64_t rx_tstamp_cycles;
4647 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4648 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4651 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4652 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4653 *timestamp = rte_ns_to_timespec(ns);
4659 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4660 struct timespec *timestamp)
4662 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663 struct e1000_adapter *adapter =
4664 (struct e1000_adapter *)dev->data->dev_private;
4665 uint32_t tsync_txctl;
4666 uint64_t tx_tstamp_cycles;
4669 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4670 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4673 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4674 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4675 *timestamp = rte_ns_to_timespec(ns);
4681 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4685 const struct reg_info *reg_group;
4687 while ((reg_group = igb_regs[g_ind++]))
4688 count += igb_reg_group_count(reg_group);
4694 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4698 const struct reg_info *reg_group;
4700 while ((reg_group = igbvf_regs[g_ind++]))
4701 count += igb_reg_group_count(reg_group);
4707 eth_igb_get_regs(struct rte_eth_dev *dev,
4708 struct rte_dev_reg_info *regs)
4710 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4711 uint32_t *data = regs->data;
4714 const struct reg_info *reg_group;
4716 /* Support only full register dump */
4717 if ((regs->length == 0) ||
4718 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4719 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4721 while ((reg_group = igb_regs[g_ind++]))
4722 count += igb_read_regs_group(dev, &data[count],
4731 igbvf_get_regs(struct rte_eth_dev *dev,
4732 struct rte_dev_reg_info *regs)
4734 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735 uint32_t *data = regs->data;
4738 const struct reg_info *reg_group;
4740 /* Support only full register dump */
4741 if ((regs->length == 0) ||
4742 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4743 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4745 while ((reg_group = igbvf_regs[g_ind++]))
4746 count += igb_read_regs_group(dev, &data[count],
4755 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4757 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4759 /* Return unit is byte count */
4760 return hw->nvm.word_size * 2;
4764 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4765 struct rte_dev_eeprom_info *in_eeprom)
4767 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4768 struct e1000_nvm_info *nvm = &hw->nvm;
4769 uint16_t *data = in_eeprom->data;
4772 first = in_eeprom->offset >> 1;
4773 length = in_eeprom->length >> 1;
4774 if ((first >= hw->nvm.word_size) ||
4775 ((first + length) >= hw->nvm.word_size))
4778 in_eeprom->magic = hw->vendor_id |
4779 ((uint32_t)hw->device_id << 16);
4781 if ((nvm->ops.read) == NULL)
4784 return nvm->ops.read(hw, first, length, data);
4788 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4789 struct rte_dev_eeprom_info *in_eeprom)
4791 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4792 struct e1000_nvm_info *nvm = &hw->nvm;
4793 uint16_t *data = in_eeprom->data;
4796 first = in_eeprom->offset >> 1;
4797 length = in_eeprom->length >> 1;
4798 if ((first >= hw->nvm.word_size) ||
4799 ((first + length) >= hw->nvm.word_size))
4802 in_eeprom->magic = (uint32_t)hw->vendor_id |
4803 ((uint32_t)hw->device_id << 16);
4805 if ((nvm->ops.write) == NULL)
4807 return nvm->ops.write(hw, first, length, data);
4810 static struct rte_driver pmd_igb_drv = {
4812 .init = rte_igb_pmd_init,
4815 static struct rte_driver pmd_igbvf_drv = {
4817 .init = rte_igbvf_pmd_init,
4821 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4823 struct e1000_hw *hw =
4824 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4825 uint32_t mask = 1 << queue_id;
4827 E1000_WRITE_REG(hw, E1000_EIMC, mask);
4828 E1000_WRITE_FLUSH(hw);
4834 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4836 struct e1000_hw *hw =
4837 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4838 uint32_t mask = 1 << queue_id;
4841 regval = E1000_READ_REG(hw, E1000_EIMS);
4842 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4843 E1000_WRITE_FLUSH(hw);
4845 rte_intr_enable(&dev->pci_dev->intr_handle);
4851 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
4852 uint8_t index, uint8_t offset)
4854 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4857 val &= ~((uint32_t)0xFF << offset);
4859 /* write vector and valid bit */
4860 val |= (msix_vector | E1000_IVAR_VALID) << offset;
4862 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4866 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4867 uint8_t queue, uint8_t msix_vector)
4871 if (hw->mac.type == e1000_82575) {
4873 tmp = E1000_EICR_RX_QUEUE0 << queue;
4874 else if (direction == 1)
4875 tmp = E1000_EICR_TX_QUEUE0 << queue;
4876 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4877 } else if (hw->mac.type == e1000_82576) {
4878 if ((direction == 0) || (direction == 1))
4879 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4880 ((queue & 0x8) << 1) +
4882 } else if ((hw->mac.type == e1000_82580) ||
4883 (hw->mac.type == e1000_i350) ||
4884 (hw->mac.type == e1000_i354) ||
4885 (hw->mac.type == e1000_i210) ||
4886 (hw->mac.type == e1000_i211)) {
4887 if ((direction == 0) || (direction == 1))
4888 eth_igb_write_ivar(hw, msix_vector,
4890 ((queue & 0x1) << 4) +
4895 /* Sets up the hardware to generate MSI-X interrupts properly
4897 * board private structure
4900 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4903 uint32_t tmpval, regval, intr_mask;
4904 struct e1000_hw *hw =
4905 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906 uint32_t vec = E1000_MISC_VEC_ID;
4907 uint32_t base = E1000_MISC_VEC_ID;
4908 uint32_t misc_shift = 0;
4910 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4912 /* won't configure msix register if no mapping is done
4913 * between intr vector and event fd
4915 if (!rte_intr_dp_is_en(intr_handle))
4918 if (rte_intr_allow_others(intr_handle)) {
4919 vec = base = E1000_RX_VEC_START;
4923 /* set interrupt vector for other causes */
4924 if (hw->mac.type == e1000_82575) {
4925 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4926 /* enable MSI-X PBA support */
4927 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4929 /* Auto-Mask interrupts upon ICR read */
4930 tmpval |= E1000_CTRL_EXT_EIAME;
4931 tmpval |= E1000_CTRL_EXT_IRCA;
4933 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4935 /* enable msix_other interrupt */
4936 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4937 regval = E1000_READ_REG(hw, E1000_EIAC);
4938 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4939 regval = E1000_READ_REG(hw, E1000_EIAM);
4940 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4941 } else if ((hw->mac.type == e1000_82576) ||
4942 (hw->mac.type == e1000_82580) ||
4943 (hw->mac.type == e1000_i350) ||
4944 (hw->mac.type == e1000_i354) ||
4945 (hw->mac.type == e1000_i210) ||
4946 (hw->mac.type == e1000_i211)) {
4947 /* turn on MSI-X capability first */
4948 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4949 E1000_GPIE_PBA | E1000_GPIE_EIAME |
4951 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4953 regval = E1000_READ_REG(hw, E1000_EIAC);
4954 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4956 /* enable msix_other interrupt */
4957 regval = E1000_READ_REG(hw, E1000_EIMS);
4958 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4959 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4960 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4963 /* use EIAM to auto-mask when MSI-X interrupt
4964 * is asserted, this saves a register write for every interrupt
4966 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4968 regval = E1000_READ_REG(hw, E1000_EIAM);
4969 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4971 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4972 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4973 intr_handle->intr_vec[queue_id] = vec;
4974 if (vec < base + intr_handle->nb_efd - 1)
4978 E1000_WRITE_FLUSH(hw);
4981 PMD_REGISTER_DRIVER(pmd_igb_drv);
4982 PMD_REGISTER_DRIVER(pmd_igbvf_drv);