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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
60 * Default values for port configuration
62 #define IGB_DEFAULT_RX_FREE_THRESH 32
63 #define IGB_DEFAULT_RX_PTHRESH 8
64 #define IGB_DEFAULT_RX_HTHRESH 8
65 #define IGB_DEFAULT_RX_WTHRESH 0
67 #define IGB_DEFAULT_TX_PTHRESH 32
68 #define IGB_DEFAULT_TX_HTHRESH 0
69 #define IGB_DEFAULT_TX_WTHRESH 0
71 #define IGB_HKEY_MAX_INDEX 10
73 /* Bit shift and mask */
74 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
75 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
76 #define IGB_8_BIT_WIDTH CHAR_BIT
77 #define IGB_8_BIT_MASK UINT8_MAX
79 /* Additional timesync values. */
80 #define E1000_ETQF_FILTER_1588 3
81 #define E1000_TIMINCA_INCVALUE 16000000
82 #define E1000_TIMINCA_INIT ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
83 | E1000_TIMINCA_INCVALUE)
85 static int eth_igb_configure(struct rte_eth_dev *dev);
86 static int eth_igb_start(struct rte_eth_dev *dev);
87 static void eth_igb_stop(struct rte_eth_dev *dev);
88 static void eth_igb_close(struct rte_eth_dev *dev);
89 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
90 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
91 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
92 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
93 static int eth_igb_link_update(struct rte_eth_dev *dev,
94 int wait_to_complete);
95 static void eth_igb_stats_get(struct rte_eth_dev *dev,
96 struct rte_eth_stats *rte_stats);
97 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
98 static void eth_igb_infos_get(struct rte_eth_dev *dev,
99 struct rte_eth_dev_info *dev_info);
100 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
101 struct rte_eth_dev_info *dev_info);
102 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
103 struct rte_eth_fc_conf *fc_conf);
104 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
105 struct rte_eth_fc_conf *fc_conf);
106 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
107 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
108 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
109 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
111 static int igb_hardware_init(struct e1000_hw *hw);
112 static void igb_hw_control_acquire(struct e1000_hw *hw);
113 static void igb_hw_control_release(struct e1000_hw *hw);
114 static void igb_init_manageability(struct e1000_hw *hw);
115 static void igb_release_manageability(struct e1000_hw *hw);
117 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
119 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
120 uint16_t vlan_id, int on);
121 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
122 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
124 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
125 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
126 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
127 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
128 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
129 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
131 static int eth_igb_led_on(struct rte_eth_dev *dev);
132 static int eth_igb_led_off(struct rte_eth_dev *dev);
134 static void igb_intr_disable(struct e1000_hw *hw);
135 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
136 static void eth_igb_rar_set(struct rte_eth_dev *dev,
137 struct ether_addr *mac_addr,
138 uint32_t index, uint32_t pool);
139 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
141 static void igbvf_intr_disable(struct e1000_hw *hw);
142 static int igbvf_dev_configure(struct rte_eth_dev *dev);
143 static int igbvf_dev_start(struct rte_eth_dev *dev);
144 static void igbvf_dev_stop(struct rte_eth_dev *dev);
145 static void igbvf_dev_close(struct rte_eth_dev *dev);
146 static int eth_igbvf_link_update(struct e1000_hw *hw);
147 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
148 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
149 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
150 uint16_t vlan_id, int on);
151 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
152 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
153 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
154 struct rte_eth_rss_reta_entry64 *reta_conf,
156 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
157 struct rte_eth_rss_reta_entry64 *reta_conf,
160 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
161 struct rte_eth_syn_filter *filter,
163 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
164 struct rte_eth_syn_filter *filter);
165 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
166 enum rte_filter_op filter_op,
168 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
169 struct rte_eth_ntuple_filter *ntuple_filter);
170 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
171 struct rte_eth_ntuple_filter *ntuple_filter);
172 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
173 struct rte_eth_flex_filter *filter,
175 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
176 struct rte_eth_flex_filter *filter);
177 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
178 enum rte_filter_op filter_op,
180 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
181 struct rte_eth_ntuple_filter *ntuple_filter);
182 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
183 struct rte_eth_ntuple_filter *ntuple_filter);
184 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
185 struct rte_eth_ntuple_filter *filter,
187 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
188 struct rte_eth_ntuple_filter *filter);
189 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
190 enum rte_filter_op filter_op,
192 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
193 struct rte_eth_ethertype_filter *filter,
195 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
196 enum rte_filter_op filter_op,
198 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
199 struct rte_eth_ethertype_filter *filter);
200 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
201 enum rte_filter_type filter_type,
202 enum rte_filter_op filter_op,
205 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
206 struct ether_addr *mc_addr_set,
207 uint32_t nb_mc_addr);
208 static int igb_timesync_enable(struct rte_eth_dev *dev);
209 static int igb_timesync_disable(struct rte_eth_dev *dev);
210 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
211 struct timespec *timestamp,
213 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
214 struct timespec *timestamp);
217 * Define VF Stats MACRO for Non "cleared on read" register
219 #define UPDATE_VF_STAT(reg, last, cur) \
221 u32 latest = E1000_READ_REG(hw, reg); \
222 cur += latest - last; \
227 #define IGB_FC_PAUSE_TIME 0x0680
228 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
229 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
231 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
233 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
236 * The set of PCI devices this driver supports
238 static const struct rte_pci_id pci_id_igb_map[] = {
240 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
241 #include "rte_pci_dev_ids.h"
247 * The set of PCI devices this driver supports (for 82576&I350 VF)
249 static const struct rte_pci_id pci_id_igbvf_map[] = {
251 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
252 #include "rte_pci_dev_ids.h"
257 static const struct eth_dev_ops eth_igb_ops = {
258 .dev_configure = eth_igb_configure,
259 .dev_start = eth_igb_start,
260 .dev_stop = eth_igb_stop,
261 .dev_close = eth_igb_close,
262 .promiscuous_enable = eth_igb_promiscuous_enable,
263 .promiscuous_disable = eth_igb_promiscuous_disable,
264 .allmulticast_enable = eth_igb_allmulticast_enable,
265 .allmulticast_disable = eth_igb_allmulticast_disable,
266 .link_update = eth_igb_link_update,
267 .stats_get = eth_igb_stats_get,
268 .stats_reset = eth_igb_stats_reset,
269 .dev_infos_get = eth_igb_infos_get,
270 .mtu_set = eth_igb_mtu_set,
271 .vlan_filter_set = eth_igb_vlan_filter_set,
272 .vlan_tpid_set = eth_igb_vlan_tpid_set,
273 .vlan_offload_set = eth_igb_vlan_offload_set,
274 .rx_queue_setup = eth_igb_rx_queue_setup,
275 .rx_queue_release = eth_igb_rx_queue_release,
276 .rx_queue_count = eth_igb_rx_queue_count,
277 .rx_descriptor_done = eth_igb_rx_descriptor_done,
278 .tx_queue_setup = eth_igb_tx_queue_setup,
279 .tx_queue_release = eth_igb_tx_queue_release,
280 .dev_led_on = eth_igb_led_on,
281 .dev_led_off = eth_igb_led_off,
282 .flow_ctrl_get = eth_igb_flow_ctrl_get,
283 .flow_ctrl_set = eth_igb_flow_ctrl_set,
284 .mac_addr_add = eth_igb_rar_set,
285 .mac_addr_remove = eth_igb_rar_clear,
286 .reta_update = eth_igb_rss_reta_update,
287 .reta_query = eth_igb_rss_reta_query,
288 .rss_hash_update = eth_igb_rss_hash_update,
289 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
290 .filter_ctrl = eth_igb_filter_ctrl,
291 .set_mc_addr_list = eth_igb_set_mc_addr_list,
292 .timesync_enable = igb_timesync_enable,
293 .timesync_disable = igb_timesync_disable,
294 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
295 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
299 * dev_ops for virtual function, bare necessities for basic vf
300 * operation have been implemented
302 static const struct eth_dev_ops igbvf_eth_dev_ops = {
303 .dev_configure = igbvf_dev_configure,
304 .dev_start = igbvf_dev_start,
305 .dev_stop = igbvf_dev_stop,
306 .dev_close = igbvf_dev_close,
307 .link_update = eth_igb_link_update,
308 .stats_get = eth_igbvf_stats_get,
309 .stats_reset = eth_igbvf_stats_reset,
310 .vlan_filter_set = igbvf_vlan_filter_set,
311 .dev_infos_get = eth_igbvf_infos_get,
312 .rx_queue_setup = eth_igb_rx_queue_setup,
313 .rx_queue_release = eth_igb_rx_queue_release,
314 .tx_queue_setup = eth_igb_tx_queue_setup,
315 .tx_queue_release = eth_igb_tx_queue_release,
316 .set_mc_addr_list = eth_igb_set_mc_addr_list,
320 * Atomically reads the link status information from global
321 * structure rte_eth_dev.
324 * - Pointer to the structure rte_eth_dev to read from.
325 * - Pointer to the buffer to be saved with the link status.
328 * - On success, zero.
329 * - On failure, negative value.
332 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
333 struct rte_eth_link *link)
335 struct rte_eth_link *dst = link;
336 struct rte_eth_link *src = &(dev->data->dev_link);
338 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
339 *(uint64_t *)src) == 0)
346 * Atomically writes the link status information into global
347 * structure rte_eth_dev.
350 * - Pointer to the structure rte_eth_dev to read from.
351 * - Pointer to the buffer to be saved with the link status.
354 * - On success, zero.
355 * - On failure, negative value.
358 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
359 struct rte_eth_link *link)
361 struct rte_eth_link *dst = &(dev->data->dev_link);
362 struct rte_eth_link *src = link;
364 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
365 *(uint64_t *)src) == 0)
372 igb_intr_enable(struct rte_eth_dev *dev)
374 struct e1000_interrupt *intr =
375 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
376 struct e1000_hw *hw =
377 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
379 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
380 E1000_WRITE_FLUSH(hw);
384 igb_intr_disable(struct e1000_hw *hw)
386 E1000_WRITE_REG(hw, E1000_IMC, ~0);
387 E1000_WRITE_FLUSH(hw);
390 static inline int32_t
391 igb_pf_reset_hw(struct e1000_hw *hw)
396 status = e1000_reset_hw(hw);
398 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
399 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
400 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
401 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
402 E1000_WRITE_FLUSH(hw);
408 igb_identify_hardware(struct rte_eth_dev *dev)
410 struct e1000_hw *hw =
411 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
413 hw->vendor_id = dev->pci_dev->id.vendor_id;
414 hw->device_id = dev->pci_dev->id.device_id;
415 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
416 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
418 e1000_set_mac_type(hw);
420 /* need to check if it is a vf device below */
424 igb_reset_swfw_lock(struct e1000_hw *hw)
429 * Do mac ops initialization manually here, since we will need
430 * some function pointers set by this call.
432 ret_val = e1000_init_mac_params(hw);
437 * SMBI lock should not fail in this early stage. If this is the case,
438 * it is due to an improper exit of the application.
439 * So force the release of the faulty lock.
441 if (e1000_get_hw_semaphore_generic(hw) < 0) {
442 PMD_DRV_LOG(DEBUG, "SMBI lock released");
444 e1000_put_hw_semaphore_generic(hw);
446 if (hw->mac.ops.acquire_swfw_sync != NULL) {
450 * Phy lock should not fail in this early stage. If this is the case,
451 * it is due to an improper exit of the application.
452 * So force the release of the faulty lock.
454 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
455 if (hw->bus.func > E1000_FUNC_1)
457 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
458 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
461 hw->mac.ops.release_swfw_sync(hw, mask);
464 * This one is more tricky since it is common to all ports; but
465 * swfw_sync retries last long enough (1s) to be almost sure that if
466 * lock can not be taken it is due to an improper lock of the
469 mask = E1000_SWFW_EEP_SM;
470 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
471 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
473 hw->mac.ops.release_swfw_sync(hw, mask);
476 return E1000_SUCCESS;
480 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
483 struct rte_pci_device *pci_dev;
484 struct e1000_hw *hw =
485 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
486 struct e1000_vfta * shadow_vfta =
487 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
488 struct e1000_filter_info *filter_info =
489 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
492 pci_dev = eth_dev->pci_dev;
493 eth_dev->dev_ops = ð_igb_ops;
494 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
495 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
497 /* for secondary processes, we don't initialise any further as primary
498 * has already done this work. Only check we don't need a different
500 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
501 if (eth_dev->data->scattered_rx)
502 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
506 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
508 igb_identify_hardware(eth_dev);
509 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
514 e1000_get_bus_info(hw);
516 /* Reset any pending lock */
517 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
522 /* Finish initialization */
523 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
529 hw->phy.autoneg_wait_to_complete = 0;
530 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
533 if (hw->phy.media_type == e1000_media_type_copper) {
534 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
535 hw->phy.disable_polarity_correction = 0;
536 hw->phy.ms_type = e1000_ms_hw_default;
540 * Start from a known state, this is important in reading the nvm
545 /* Make sure we have a good EEPROM before we read from it */
546 if (e1000_validate_nvm_checksum(hw) < 0) {
548 * Some PCI-E parts fail the first check due to
549 * the link being in sleep state, call it again,
550 * if it fails a second time its a real issue.
552 if (e1000_validate_nvm_checksum(hw) < 0) {
553 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
559 /* Read the permanent MAC address out of the EEPROM */
560 if (e1000_read_mac_addr(hw) != 0) {
561 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
566 /* Allocate memory for storing MAC addresses */
567 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
568 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
569 if (eth_dev->data->mac_addrs == NULL) {
570 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
571 "store MAC addresses",
572 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
577 /* Copy the permanent MAC address */
578 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
580 /* initialize the vfta */
581 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
583 /* Now initialize the hardware */
584 if (igb_hardware_init(hw) != 0) {
585 PMD_INIT_LOG(ERR, "Hardware initialization failed");
586 rte_free(eth_dev->data->mac_addrs);
587 eth_dev->data->mac_addrs = NULL;
591 hw->mac.get_link_status = 1;
593 /* Indicate SOL/IDER usage */
594 if (e1000_check_reset_block(hw) < 0) {
595 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
599 /* initialize PF if max_vfs not zero */
600 igb_pf_host_init(eth_dev);
602 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
603 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
604 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
605 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
606 E1000_WRITE_FLUSH(hw);
608 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
609 eth_dev->data->port_id, pci_dev->id.vendor_id,
610 pci_dev->id.device_id);
612 rte_intr_callback_register(&(pci_dev->intr_handle),
613 eth_igb_interrupt_handler, (void *)eth_dev);
615 /* enable uio intr after callback register */
616 rte_intr_enable(&(pci_dev->intr_handle));
618 /* enable support intr */
619 igb_intr_enable(eth_dev);
621 TAILQ_INIT(&filter_info->flex_list);
622 filter_info->flex_mask = 0;
623 TAILQ_INIT(&filter_info->twotuple_list);
624 filter_info->twotuple_mask = 0;
625 TAILQ_INIT(&filter_info->fivetuple_list);
626 filter_info->fivetuple_mask = 0;
631 igb_hw_control_release(hw);
637 * Virtual Function device init
640 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
642 struct rte_pci_device *pci_dev;
643 struct e1000_hw *hw =
644 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
647 PMD_INIT_FUNC_TRACE();
649 eth_dev->dev_ops = &igbvf_eth_dev_ops;
650 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
651 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
653 /* for secondary processes, we don't initialise any further as primary
654 * has already done this work. Only check we don't need a different
656 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
657 if (eth_dev->data->scattered_rx)
658 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
662 pci_dev = eth_dev->pci_dev;
664 hw->device_id = pci_dev->id.device_id;
665 hw->vendor_id = pci_dev->id.vendor_id;
666 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
668 /* Initialize the shared code (base driver) */
669 diag = e1000_setup_init_funcs(hw, TRUE);
671 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
676 /* init_mailbox_params */
677 hw->mbx.ops.init_params(hw);
679 /* Disable the interrupts for VF */
680 igbvf_intr_disable(hw);
682 diag = hw->mac.ops.reset_hw(hw);
684 /* Allocate memory for storing MAC addresses */
685 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
686 hw->mac.rar_entry_count, 0);
687 if (eth_dev->data->mac_addrs == NULL) {
689 "Failed to allocate %d bytes needed to store MAC "
691 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
695 /* Copy the permanent MAC address */
696 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
697 ð_dev->data->mac_addrs[0]);
699 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
701 eth_dev->data->port_id, pci_dev->id.vendor_id,
702 pci_dev->id.device_id, "igb_mac_82576_vf");
707 static struct eth_driver rte_igb_pmd = {
709 .name = "rte_igb_pmd",
710 .id_table = pci_id_igb_map,
711 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
713 .eth_dev_init = eth_igb_dev_init,
714 .dev_private_size = sizeof(struct e1000_adapter),
718 * virtual function driver struct
720 static struct eth_driver rte_igbvf_pmd = {
722 .name = "rte_igbvf_pmd",
723 .id_table = pci_id_igbvf_map,
724 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
726 .eth_dev_init = eth_igbvf_dev_init,
727 .dev_private_size = sizeof(struct e1000_adapter),
731 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
733 rte_eth_driver_register(&rte_igb_pmd);
738 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
740 struct e1000_hw *hw =
741 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
742 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
743 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
744 rctl |= E1000_RCTL_VFE;
745 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
749 * VF Driver initialization routine.
750 * Invoked one at EAL init time.
751 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
754 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
756 PMD_INIT_FUNC_TRACE();
758 rte_eth_driver_register(&rte_igbvf_pmd);
763 eth_igb_configure(struct rte_eth_dev *dev)
765 struct e1000_interrupt *intr =
766 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
768 PMD_INIT_FUNC_TRACE();
769 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
770 PMD_INIT_FUNC_TRACE();
776 eth_igb_start(struct rte_eth_dev *dev)
778 struct e1000_hw *hw =
779 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
783 PMD_INIT_FUNC_TRACE();
785 /* Power up the phy. Needed to make the link go Up */
786 e1000_power_up_phy(hw);
789 * Packet Buffer Allocation (PBA)
790 * Writing PBA sets the receive portion of the buffer
791 * the remainder is used for the transmit buffer.
793 if (hw->mac.type == e1000_82575) {
796 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
797 E1000_WRITE_REG(hw, E1000_PBA, pba);
800 /* Put the address into the Receive Address Array */
801 e1000_rar_set(hw, hw->mac.addr, 0);
803 /* Initialize the hardware */
804 if (igb_hardware_init(hw)) {
805 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
809 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
811 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
812 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
813 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
814 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
815 E1000_WRITE_FLUSH(hw);
817 /* configure PF module if SRIOV enabled */
818 igb_pf_host_configure(dev);
820 /* Configure for OS presence */
821 igb_init_manageability(hw);
823 eth_igb_tx_init(dev);
825 /* This can fail when allocating mbufs for descriptor rings */
826 ret = eth_igb_rx_init(dev);
828 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
829 igb_dev_clear_queues(dev);
833 e1000_clear_hw_cntrs_base_generic(hw);
836 * VLAN Offload Settings
838 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
839 ETH_VLAN_EXTEND_MASK;
840 eth_igb_vlan_offload_set(dev, mask);
842 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
843 /* Enable VLAN filter since VMDq always use VLAN filter */
844 igb_vmdq_vlan_hw_filter_enable(dev);
848 * Configure the Interrupt Moderation register (EITR) with the maximum
849 * possible value (0xFFFF) to minimize "System Partial Write" issued by
850 * spurious [DMA] memory updates of RX and TX ring descriptors.
852 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
853 * spurious memory updates per second should be expected.
854 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
856 * Because interrupts are not used at all, the MSI-X is not activated
857 * and interrupt moderation is controlled by EITR[0].
859 * Note that having [almost] disabled memory updates of RX and TX ring
860 * descriptors through the Interrupt Moderation mechanism, memory
861 * updates of ring descriptors are now moderated by the configurable
862 * value of Write-Back Threshold registers.
864 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
865 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
866 (hw->mac.type == e1000_i211)) {
869 /* Enable all RX & TX queues in the IVAR registers */
870 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
871 for (i = 0; i < 8; i++)
872 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
874 /* Configure EITR with the maximum possible value (0xFFFF) */
875 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
878 /* Setup link speed and duplex */
879 switch (dev->data->dev_conf.link_speed) {
880 case ETH_LINK_SPEED_AUTONEG:
881 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
882 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
883 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
884 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
885 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
886 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
888 goto error_invalid_config;
890 case ETH_LINK_SPEED_10:
891 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
892 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
893 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
894 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
895 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
896 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
898 goto error_invalid_config;
900 case ETH_LINK_SPEED_100:
901 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
902 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
903 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
904 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
905 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
906 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
908 goto error_invalid_config;
910 case ETH_LINK_SPEED_1000:
911 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
912 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
913 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
915 goto error_invalid_config;
917 case ETH_LINK_SPEED_10000:
919 goto error_invalid_config;
921 e1000_setup_link(hw);
923 /* check if lsc interrupt feature is enabled */
924 if (dev->data->dev_conf.intr_conf.lsc != 0)
925 ret = eth_igb_lsc_interrupt_setup(dev);
927 /* resume enabled intr since hw reset */
928 igb_intr_enable(dev);
930 PMD_INIT_LOG(DEBUG, "<<");
934 error_invalid_config:
935 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
936 dev->data->dev_conf.link_speed,
937 dev->data->dev_conf.link_duplex, dev->data->port_id);
938 igb_dev_clear_queues(dev);
942 /*********************************************************************
944 * This routine disables all traffic on the adapter by issuing a
945 * global reset on the MAC.
947 **********************************************************************/
949 eth_igb_stop(struct rte_eth_dev *dev)
951 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
952 struct e1000_filter_info *filter_info =
953 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
954 struct rte_eth_link link;
955 struct e1000_flex_filter *p_flex;
956 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
957 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
959 igb_intr_disable(hw);
961 E1000_WRITE_REG(hw, E1000_WUC, 0);
963 /* Set bit for Go Link disconnect */
964 if (hw->mac.type >= e1000_82580) {
967 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
968 phpm_reg |= E1000_82580_PM_GO_LINKD;
969 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
972 /* Power down the phy. Needed to make the link go Down */
973 if (hw->phy.media_type == e1000_media_type_copper)
974 e1000_power_down_phy(hw);
976 e1000_shutdown_fiber_serdes_link(hw);
978 igb_dev_clear_queues(dev);
980 /* clear the recorded link status */
981 memset(&link, 0, sizeof(link));
982 rte_igb_dev_atomic_write_link_status(dev, &link);
984 /* Remove all flex filters of the device */
985 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
986 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
989 filter_info->flex_mask = 0;
991 /* Remove all ntuple filters of the device */
992 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
993 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
994 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
995 TAILQ_REMOVE(&filter_info->fivetuple_list,
999 filter_info->fivetuple_mask = 0;
1000 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1001 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1002 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1003 TAILQ_REMOVE(&filter_info->twotuple_list,
1007 filter_info->twotuple_mask = 0;
1011 eth_igb_close(struct rte_eth_dev *dev)
1013 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1014 struct rte_eth_link link;
1017 e1000_phy_hw_reset(hw);
1018 igb_release_manageability(hw);
1019 igb_hw_control_release(hw);
1021 /* Clear bit for Go Link disconnect */
1022 if (hw->mac.type >= e1000_82580) {
1025 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1026 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1027 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1030 igb_dev_clear_queues(dev);
1032 memset(&link, 0, sizeof(link));
1033 rte_igb_dev_atomic_write_link_status(dev, &link);
1037 igb_get_rx_buffer_size(struct e1000_hw *hw)
1039 uint32_t rx_buf_size;
1040 if (hw->mac.type == e1000_82576) {
1041 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1042 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1043 /* PBS needs to be translated according to a lookup table */
1044 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1045 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1046 rx_buf_size = (rx_buf_size << 10);
1047 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1048 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1050 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1056 /*********************************************************************
1058 * Initialize the hardware
1060 **********************************************************************/
1062 igb_hardware_init(struct e1000_hw *hw)
1064 uint32_t rx_buf_size;
1067 /* Let the firmware know the OS is in control */
1068 igb_hw_control_acquire(hw);
1071 * These parameters control the automatic generation (Tx) and
1072 * response (Rx) to Ethernet PAUSE frames.
1073 * - High water mark should allow for at least two standard size (1518)
1074 * frames to be received after sending an XOFF.
1075 * - Low water mark works best when it is very near the high water mark.
1076 * This allows the receiver to restart by sending XON when it has
1077 * drained a bit. Here we use an arbitrary value of 1500 which will
1078 * restart after one full frame is pulled from the buffer. There
1079 * could be several smaller frames in the buffer and if so they will
1080 * not trigger the XON until their total number reduces the buffer
1082 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1084 rx_buf_size = igb_get_rx_buffer_size(hw);
1086 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1087 hw->fc.low_water = hw->fc.high_water - 1500;
1088 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1089 hw->fc.send_xon = 1;
1091 /* Set Flow control, use the tunable location if sane */
1092 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1093 hw->fc.requested_mode = igb_fc_setting;
1095 hw->fc.requested_mode = e1000_fc_none;
1097 /* Issue a global reset */
1098 igb_pf_reset_hw(hw);
1099 E1000_WRITE_REG(hw, E1000_WUC, 0);
1101 diag = e1000_init_hw(hw);
1105 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1106 e1000_get_phy_info(hw);
1107 e1000_check_for_link(hw);
1112 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1114 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1116 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1117 struct e1000_hw_stats *stats =
1118 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1121 if(hw->phy.media_type == e1000_media_type_copper ||
1122 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1124 E1000_READ_REG(hw,E1000_SYMERRS);
1125 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1128 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1129 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1130 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1131 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1133 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1134 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1135 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1136 stats->dc += E1000_READ_REG(hw, E1000_DC);
1137 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1138 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1139 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1141 ** For watchdog management we need to know if we have been
1142 ** paused during the last interval, so capture that here.
1144 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1145 stats->xoffrxc += pause_frames;
1146 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1147 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1148 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1149 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1150 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1151 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1152 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1153 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1154 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1155 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1156 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1157 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1159 /* For the 64-bit byte counters the low dword must be read first. */
1160 /* Both registers clear on the read of the high dword */
1162 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1163 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1164 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1165 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1167 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1168 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1169 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1170 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1171 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1173 stats->tor += E1000_READ_REG(hw, E1000_TORH);
1174 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1176 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1177 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1178 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1179 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1180 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1181 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1182 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1183 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1184 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1185 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1187 /* Interrupt Counts */
1189 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1190 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1191 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1192 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1193 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1194 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1195 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1196 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1197 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1199 /* Host to Card Statistics */
1201 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1202 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1203 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1204 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1205 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1206 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1207 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1208 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1209 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1210 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1211 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1212 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1213 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1214 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1216 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1217 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1218 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1219 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1220 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1221 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1223 if (rte_stats == NULL)
1227 rte_stats->ibadcrc = stats->crcerrs;
1228 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1229 rte_stats->imissed = stats->mpc;
1230 rte_stats->ierrors = rte_stats->ibadcrc +
1231 rte_stats->ibadlen +
1232 rte_stats->imissed +
1233 stats->rxerrc + stats->algnerrc + stats->cexterr;
1236 rte_stats->oerrors = stats->ecol + stats->latecol;
1238 /* XON/XOFF pause frames */
1239 rte_stats->tx_pause_xon = stats->xontxc;
1240 rte_stats->rx_pause_xon = stats->xonrxc;
1241 rte_stats->tx_pause_xoff = stats->xofftxc;
1242 rte_stats->rx_pause_xoff = stats->xoffrxc;
1244 rte_stats->ipackets = stats->gprc;
1245 rte_stats->opackets = stats->gptc;
1246 rte_stats->ibytes = stats->gorc;
1247 rte_stats->obytes = stats->gotc;
1251 eth_igb_stats_reset(struct rte_eth_dev *dev)
1253 struct e1000_hw_stats *hw_stats =
1254 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1256 /* HW registers are cleared on read */
1257 eth_igb_stats_get(dev, NULL);
1259 /* Reset software totals */
1260 memset(hw_stats, 0, sizeof(*hw_stats));
1264 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1266 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1267 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1268 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1270 /* Good Rx packets, include VF loopback */
1271 UPDATE_VF_STAT(E1000_VFGPRC,
1272 hw_stats->last_gprc, hw_stats->gprc);
1274 /* Good Rx octets, include VF loopback */
1275 UPDATE_VF_STAT(E1000_VFGORC,
1276 hw_stats->last_gorc, hw_stats->gorc);
1278 /* Good Tx packets, include VF loopback */
1279 UPDATE_VF_STAT(E1000_VFGPTC,
1280 hw_stats->last_gptc, hw_stats->gptc);
1282 /* Good Tx octets, include VF loopback */
1283 UPDATE_VF_STAT(E1000_VFGOTC,
1284 hw_stats->last_gotc, hw_stats->gotc);
1286 /* Rx Multicst packets */
1287 UPDATE_VF_STAT(E1000_VFMPRC,
1288 hw_stats->last_mprc, hw_stats->mprc);
1290 /* Good Rx loopback packets */
1291 UPDATE_VF_STAT(E1000_VFGPRLBC,
1292 hw_stats->last_gprlbc, hw_stats->gprlbc);
1294 /* Good Rx loopback octets */
1295 UPDATE_VF_STAT(E1000_VFGORLBC,
1296 hw_stats->last_gorlbc, hw_stats->gorlbc);
1298 /* Good Tx loopback packets */
1299 UPDATE_VF_STAT(E1000_VFGPTLBC,
1300 hw_stats->last_gptlbc, hw_stats->gptlbc);
1302 /* Good Tx loopback octets */
1303 UPDATE_VF_STAT(E1000_VFGOTLBC,
1304 hw_stats->last_gotlbc, hw_stats->gotlbc);
1306 if (rte_stats == NULL)
1309 rte_stats->ipackets = hw_stats->gprc;
1310 rte_stats->ibytes = hw_stats->gorc;
1311 rte_stats->opackets = hw_stats->gptc;
1312 rte_stats->obytes = hw_stats->gotc;
1313 rte_stats->imcasts = hw_stats->mprc;
1314 rte_stats->ilbpackets = hw_stats->gprlbc;
1315 rte_stats->ilbbytes = hw_stats->gorlbc;
1316 rte_stats->olbpackets = hw_stats->gptlbc;
1317 rte_stats->olbbytes = hw_stats->gotlbc;
1322 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1324 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1325 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1327 /* Sync HW register to the last stats */
1328 eth_igbvf_stats_get(dev, NULL);
1330 /* reset HW current stats*/
1331 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1332 offsetof(struct e1000_vf_stats, gprc));
1337 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1339 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1341 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1342 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1343 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1344 dev_info->rx_offload_capa =
1345 DEV_RX_OFFLOAD_VLAN_STRIP |
1346 DEV_RX_OFFLOAD_IPV4_CKSUM |
1347 DEV_RX_OFFLOAD_UDP_CKSUM |
1348 DEV_RX_OFFLOAD_TCP_CKSUM;
1349 dev_info->tx_offload_capa =
1350 DEV_TX_OFFLOAD_VLAN_INSERT |
1351 DEV_TX_OFFLOAD_IPV4_CKSUM |
1352 DEV_TX_OFFLOAD_UDP_CKSUM |
1353 DEV_TX_OFFLOAD_TCP_CKSUM |
1354 DEV_TX_OFFLOAD_SCTP_CKSUM;
1356 switch (hw->mac.type) {
1358 dev_info->max_rx_queues = 4;
1359 dev_info->max_tx_queues = 4;
1360 dev_info->max_vmdq_pools = 0;
1364 dev_info->max_rx_queues = 16;
1365 dev_info->max_tx_queues = 16;
1366 dev_info->max_vmdq_pools = ETH_8_POOLS;
1367 dev_info->vmdq_queue_num = 16;
1371 dev_info->max_rx_queues = 8;
1372 dev_info->max_tx_queues = 8;
1373 dev_info->max_vmdq_pools = ETH_8_POOLS;
1374 dev_info->vmdq_queue_num = 8;
1378 dev_info->max_rx_queues = 8;
1379 dev_info->max_tx_queues = 8;
1380 dev_info->max_vmdq_pools = ETH_8_POOLS;
1381 dev_info->vmdq_queue_num = 8;
1385 dev_info->max_rx_queues = 8;
1386 dev_info->max_tx_queues = 8;
1390 dev_info->max_rx_queues = 4;
1391 dev_info->max_tx_queues = 4;
1392 dev_info->max_vmdq_pools = 0;
1396 dev_info->max_rx_queues = 2;
1397 dev_info->max_tx_queues = 2;
1398 dev_info->max_vmdq_pools = 0;
1402 /* Should not happen */
1405 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1406 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1407 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1409 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1411 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1412 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1413 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1415 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1419 dev_info->default_txconf = (struct rte_eth_txconf) {
1421 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1422 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1423 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1430 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1432 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1434 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1435 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1436 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1437 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1438 DEV_RX_OFFLOAD_IPV4_CKSUM |
1439 DEV_RX_OFFLOAD_UDP_CKSUM |
1440 DEV_RX_OFFLOAD_TCP_CKSUM;
1441 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1442 DEV_TX_OFFLOAD_IPV4_CKSUM |
1443 DEV_TX_OFFLOAD_UDP_CKSUM |
1444 DEV_TX_OFFLOAD_TCP_CKSUM |
1445 DEV_TX_OFFLOAD_SCTP_CKSUM;
1446 switch (hw->mac.type) {
1448 dev_info->max_rx_queues = 2;
1449 dev_info->max_tx_queues = 2;
1451 case e1000_vfadapt_i350:
1452 dev_info->max_rx_queues = 1;
1453 dev_info->max_tx_queues = 1;
1456 /* Should not happen */
1460 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1462 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1463 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1464 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1466 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1470 dev_info->default_txconf = (struct rte_eth_txconf) {
1472 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1473 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1474 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1480 /* return 0 means link status changed, -1 means not changed */
1482 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1484 struct e1000_hw *hw =
1485 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486 struct rte_eth_link link, old;
1487 int link_check, count;
1490 hw->mac.get_link_status = 1;
1492 /* possible wait-to-complete in up to 9 seconds */
1493 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1494 /* Read the real link status */
1495 switch (hw->phy.media_type) {
1496 case e1000_media_type_copper:
1497 /* Do the work to read phy */
1498 e1000_check_for_link(hw);
1499 link_check = !hw->mac.get_link_status;
1502 case e1000_media_type_fiber:
1503 e1000_check_for_link(hw);
1504 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1508 case e1000_media_type_internal_serdes:
1509 e1000_check_for_link(hw);
1510 link_check = hw->mac.serdes_has_link;
1513 /* VF device is type_unknown */
1514 case e1000_media_type_unknown:
1515 eth_igbvf_link_update(hw);
1516 link_check = !hw->mac.get_link_status;
1522 if (link_check || wait_to_complete == 0)
1524 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1526 memset(&link, 0, sizeof(link));
1527 rte_igb_dev_atomic_read_link_status(dev, &link);
1530 /* Now we check if a transition has happened */
1532 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1534 link.link_status = 1;
1535 } else if (!link_check) {
1536 link.link_speed = 0;
1537 link.link_duplex = 0;
1538 link.link_status = 0;
1540 rte_igb_dev_atomic_write_link_status(dev, &link);
1543 if (old.link_status == link.link_status)
1551 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1552 * For ASF and Pass Through versions of f/w this means
1553 * that the driver is loaded.
1556 igb_hw_control_acquire(struct e1000_hw *hw)
1560 /* Let firmware know the driver has taken over */
1561 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1562 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1566 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1567 * For ASF and Pass Through versions of f/w this means that the
1568 * driver is no longer loaded.
1571 igb_hw_control_release(struct e1000_hw *hw)
1575 /* Let firmware taken over control of h/w */
1576 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1577 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1578 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1582 * Bit of a misnomer, what this really means is
1583 * to enable OS management of the system... aka
1584 * to disable special hardware management features.
1587 igb_init_manageability(struct e1000_hw *hw)
1589 if (e1000_enable_mng_pass_thru(hw)) {
1590 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1591 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1593 /* disable hardware interception of ARP */
1594 manc &= ~(E1000_MANC_ARP_EN);
1596 /* enable receiving management packets to the host */
1597 manc |= E1000_MANC_EN_MNG2HOST;
1598 manc2h |= 1 << 5; /* Mng Port 623 */
1599 manc2h |= 1 << 6; /* Mng Port 664 */
1600 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1601 E1000_WRITE_REG(hw, E1000_MANC, manc);
1606 igb_release_manageability(struct e1000_hw *hw)
1608 if (e1000_enable_mng_pass_thru(hw)) {
1609 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1611 manc |= E1000_MANC_ARP_EN;
1612 manc &= ~E1000_MANC_EN_MNG2HOST;
1614 E1000_WRITE_REG(hw, E1000_MANC, manc);
1619 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1621 struct e1000_hw *hw =
1622 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625 rctl = E1000_READ_REG(hw, E1000_RCTL);
1626 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1627 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1631 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1633 struct e1000_hw *hw =
1634 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637 rctl = E1000_READ_REG(hw, E1000_RCTL);
1638 rctl &= (~E1000_RCTL_UPE);
1639 if (dev->data->all_multicast == 1)
1640 rctl |= E1000_RCTL_MPE;
1642 rctl &= (~E1000_RCTL_MPE);
1643 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1647 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1649 struct e1000_hw *hw =
1650 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653 rctl = E1000_READ_REG(hw, E1000_RCTL);
1654 rctl |= E1000_RCTL_MPE;
1655 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1659 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1661 struct e1000_hw *hw =
1662 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665 if (dev->data->promiscuous == 1)
1666 return; /* must remain in all_multicast mode */
1667 rctl = E1000_READ_REG(hw, E1000_RCTL);
1668 rctl &= (~E1000_RCTL_MPE);
1669 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1673 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1675 struct e1000_hw *hw =
1676 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677 struct e1000_vfta * shadow_vfta =
1678 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1683 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1684 E1000_VFTA_ENTRY_MASK);
1685 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1686 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1691 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1693 /* update local VFTA copy */
1694 shadow_vfta->vfta[vid_idx] = vfta;
1700 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1702 struct e1000_hw *hw =
1703 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 uint32_t reg = ETHER_TYPE_VLAN ;
1706 reg |= (tpid << 16);
1707 E1000_WRITE_REG(hw, E1000_VET, reg);
1711 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1713 struct e1000_hw *hw =
1714 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1717 /* Filter Table Disable */
1718 reg = E1000_READ_REG(hw, E1000_RCTL);
1719 reg &= ~E1000_RCTL_CFIEN;
1720 reg &= ~E1000_RCTL_VFE;
1721 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1725 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1727 struct e1000_hw *hw =
1728 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729 struct e1000_vfta * shadow_vfta =
1730 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1734 /* Filter Table Enable, CFI not used for packet acceptance */
1735 reg = E1000_READ_REG(hw, E1000_RCTL);
1736 reg &= ~E1000_RCTL_CFIEN;
1737 reg |= E1000_RCTL_VFE;
1738 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1740 /* restore VFTA table */
1741 for (i = 0; i < IGB_VFTA_SIZE; i++)
1742 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1746 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1748 struct e1000_hw *hw =
1749 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752 /* VLAN Mode Disable */
1753 reg = E1000_READ_REG(hw, E1000_CTRL);
1754 reg &= ~E1000_CTRL_VME;
1755 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1759 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1761 struct e1000_hw *hw =
1762 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1765 /* VLAN Mode Enable */
1766 reg = E1000_READ_REG(hw, E1000_CTRL);
1767 reg |= E1000_CTRL_VME;
1768 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1772 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1774 struct e1000_hw *hw =
1775 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1778 /* CTRL_EXT: Extended VLAN */
1779 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1780 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1781 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1783 /* Update maximum packet length */
1784 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1785 E1000_WRITE_REG(hw, E1000_RLPML,
1786 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1791 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1793 struct e1000_hw *hw =
1794 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1797 /* CTRL_EXT: Extended VLAN */
1798 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1799 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1800 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1802 /* Update maximum packet length */
1803 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1804 E1000_WRITE_REG(hw, E1000_RLPML,
1805 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1810 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1812 if(mask & ETH_VLAN_STRIP_MASK){
1813 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1814 igb_vlan_hw_strip_enable(dev);
1816 igb_vlan_hw_strip_disable(dev);
1819 if(mask & ETH_VLAN_FILTER_MASK){
1820 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1821 igb_vlan_hw_filter_enable(dev);
1823 igb_vlan_hw_filter_disable(dev);
1826 if(mask & ETH_VLAN_EXTEND_MASK){
1827 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1828 igb_vlan_hw_extend_enable(dev);
1830 igb_vlan_hw_extend_disable(dev);
1836 * It enables the interrupt mask and then enable the interrupt.
1839 * Pointer to struct rte_eth_dev.
1842 * - On success, zero.
1843 * - On failure, a negative value.
1846 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1848 struct e1000_interrupt *intr =
1849 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1851 intr->mask |= E1000_ICR_LSC;
1857 * It reads ICR and gets interrupt causes, check it and set a bit flag
1858 * to update link status.
1861 * Pointer to struct rte_eth_dev.
1864 * - On success, zero.
1865 * - On failure, a negative value.
1868 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1871 struct e1000_hw *hw =
1872 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873 struct e1000_interrupt *intr =
1874 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1876 igb_intr_disable(hw);
1878 /* read-on-clear nic registers here */
1879 icr = E1000_READ_REG(hw, E1000_ICR);
1882 if (icr & E1000_ICR_LSC) {
1883 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1886 if (icr & E1000_ICR_VMMB)
1887 intr->flags |= E1000_FLAG_MAILBOX;
1893 * It executes link_update after knowing an interrupt is prsent.
1896 * Pointer to struct rte_eth_dev.
1899 * - On success, zero.
1900 * - On failure, a negative value.
1903 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1905 struct e1000_hw *hw =
1906 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1907 struct e1000_interrupt *intr =
1908 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1909 uint32_t tctl, rctl;
1910 struct rte_eth_link link;
1913 if (intr->flags & E1000_FLAG_MAILBOX) {
1914 igb_pf_mbx_process(dev);
1915 intr->flags &= ~E1000_FLAG_MAILBOX;
1918 igb_intr_enable(dev);
1919 rte_intr_enable(&(dev->pci_dev->intr_handle));
1921 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1922 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1924 /* set get_link_status to check register later */
1925 hw->mac.get_link_status = 1;
1926 ret = eth_igb_link_update(dev, 0);
1928 /* check if link has changed */
1932 memset(&link, 0, sizeof(link));
1933 rte_igb_dev_atomic_read_link_status(dev, &link);
1934 if (link.link_status) {
1936 " Port %d: Link Up - speed %u Mbps - %s",
1938 (unsigned)link.link_speed,
1939 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1940 "full-duplex" : "half-duplex");
1942 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1943 dev->data->port_id);
1945 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1946 dev->pci_dev->addr.domain,
1947 dev->pci_dev->addr.bus,
1948 dev->pci_dev->addr.devid,
1949 dev->pci_dev->addr.function);
1950 tctl = E1000_READ_REG(hw, E1000_TCTL);
1951 rctl = E1000_READ_REG(hw, E1000_RCTL);
1952 if (link.link_status) {
1954 tctl |= E1000_TCTL_EN;
1955 rctl |= E1000_RCTL_EN;
1958 tctl &= ~E1000_TCTL_EN;
1959 rctl &= ~E1000_RCTL_EN;
1961 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1962 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1963 E1000_WRITE_FLUSH(hw);
1964 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1971 * Interrupt handler which shall be registered at first.
1974 * Pointer to interrupt handle.
1976 * The address of parameter (struct rte_eth_dev *) regsitered before.
1982 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1985 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1987 eth_igb_interrupt_get_status(dev);
1988 eth_igb_interrupt_action(dev);
1992 eth_igb_led_on(struct rte_eth_dev *dev)
1994 struct e1000_hw *hw;
1996 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2001 eth_igb_led_off(struct rte_eth_dev *dev)
2003 struct e1000_hw *hw;
2005 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2010 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2012 struct e1000_hw *hw;
2017 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018 fc_conf->pause_time = hw->fc.pause_time;
2019 fc_conf->high_water = hw->fc.high_water;
2020 fc_conf->low_water = hw->fc.low_water;
2021 fc_conf->send_xon = hw->fc.send_xon;
2022 fc_conf->autoneg = hw->mac.autoneg;
2025 * Return rx_pause and tx_pause status according to actual setting of
2026 * the TFCE and RFCE bits in the CTRL register.
2028 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2029 if (ctrl & E1000_CTRL_TFCE)
2034 if (ctrl & E1000_CTRL_RFCE)
2039 if (rx_pause && tx_pause)
2040 fc_conf->mode = RTE_FC_FULL;
2042 fc_conf->mode = RTE_FC_RX_PAUSE;
2044 fc_conf->mode = RTE_FC_TX_PAUSE;
2046 fc_conf->mode = RTE_FC_NONE;
2052 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2054 struct e1000_hw *hw;
2056 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2062 uint32_t rx_buf_size;
2063 uint32_t max_high_water;
2066 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067 if (fc_conf->autoneg != hw->mac.autoneg)
2069 rx_buf_size = igb_get_rx_buffer_size(hw);
2070 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2072 /* At least reserve one Ethernet frame for watermark */
2073 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2074 if ((fc_conf->high_water > max_high_water) ||
2075 (fc_conf->high_water < fc_conf->low_water)) {
2076 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2077 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2081 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2082 hw->fc.pause_time = fc_conf->pause_time;
2083 hw->fc.high_water = fc_conf->high_water;
2084 hw->fc.low_water = fc_conf->low_water;
2085 hw->fc.send_xon = fc_conf->send_xon;
2087 err = e1000_setup_link_generic(hw);
2088 if (err == E1000_SUCCESS) {
2090 /* check if we want to forward MAC frames - driver doesn't have native
2091 * capability to do that, so we'll write the registers ourselves */
2093 rctl = E1000_READ_REG(hw, E1000_RCTL);
2095 /* set or clear MFLCN.PMCF bit depending on configuration */
2096 if (fc_conf->mac_ctrl_frame_fwd != 0)
2097 rctl |= E1000_RCTL_PMCF;
2099 rctl &= ~E1000_RCTL_PMCF;
2101 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2102 E1000_WRITE_FLUSH(hw);
2107 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2111 #define E1000_RAH_POOLSEL_SHIFT (18)
2113 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2114 uint32_t index, __rte_unused uint32_t pool)
2116 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2120 rah = E1000_READ_REG(hw, E1000_RAH(index));
2121 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2122 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2126 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2128 uint8_t addr[ETHER_ADDR_LEN];
2129 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2131 memset(addr, 0, sizeof(addr));
2133 e1000_rar_set(hw, addr, index);
2137 * Virtual Function operations
2140 igbvf_intr_disable(struct e1000_hw *hw)
2142 PMD_INIT_FUNC_TRACE();
2144 /* Clear interrupt mask to stop from interrupts being generated */
2145 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2147 E1000_WRITE_FLUSH(hw);
2151 igbvf_stop_adapter(struct rte_eth_dev *dev)
2155 struct rte_eth_dev_info dev_info;
2156 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158 memset(&dev_info, 0, sizeof(dev_info));
2159 eth_igbvf_infos_get(dev, &dev_info);
2161 /* Clear interrupt mask to stop from interrupts being generated */
2162 igbvf_intr_disable(hw);
2164 /* Clear any pending interrupts, flush previous writes */
2165 E1000_READ_REG(hw, E1000_EICR);
2167 /* Disable the transmit unit. Each queue must be disabled. */
2168 for (i = 0; i < dev_info.max_tx_queues; i++)
2169 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2171 /* Disable the receive unit by stopping each queue */
2172 for (i = 0; i < dev_info.max_rx_queues; i++) {
2173 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2174 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2175 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2176 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2180 /* flush all queues disables */
2181 E1000_WRITE_FLUSH(hw);
2185 static int eth_igbvf_link_update(struct e1000_hw *hw)
2187 struct e1000_mbx_info *mbx = &hw->mbx;
2188 struct e1000_mac_info *mac = &hw->mac;
2189 int ret_val = E1000_SUCCESS;
2191 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2194 * We only want to run this if there has been a rst asserted.
2195 * in this case that could mean a link change, device reset,
2196 * or a virtual function reset
2199 /* If we were hit with a reset or timeout drop the link */
2200 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2201 mac->get_link_status = TRUE;
2203 if (!mac->get_link_status)
2206 /* if link status is down no point in checking to see if pf is up */
2207 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2210 /* if we passed all the tests above then the link is up and we no
2211 * longer need to check for link */
2212 mac->get_link_status = FALSE;
2220 igbvf_dev_configure(struct rte_eth_dev *dev)
2222 struct rte_eth_conf* conf = &dev->data->dev_conf;
2224 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2225 dev->data->port_id);
2228 * VF has no ability to enable/disable HW CRC
2229 * Keep the persistent behavior the same as Host PF
2231 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2232 if (!conf->rxmode.hw_strip_crc) {
2233 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2234 conf->rxmode.hw_strip_crc = 1;
2237 if (conf->rxmode.hw_strip_crc) {
2238 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2239 conf->rxmode.hw_strip_crc = 0;
2247 igbvf_dev_start(struct rte_eth_dev *dev)
2249 struct e1000_hw *hw =
2250 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253 PMD_INIT_FUNC_TRACE();
2255 hw->mac.ops.reset_hw(hw);
2258 igbvf_set_vfta_all(dev,1);
2260 eth_igbvf_tx_init(dev);
2262 /* This can fail when allocating mbufs for descriptor rings */
2263 ret = eth_igbvf_rx_init(dev);
2265 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2266 igb_dev_clear_queues(dev);
2274 igbvf_dev_stop(struct rte_eth_dev *dev)
2276 PMD_INIT_FUNC_TRACE();
2278 igbvf_stop_adapter(dev);
2281 * Clear what we set, but we still keep shadow_vfta to
2282 * restore after device starts
2284 igbvf_set_vfta_all(dev,0);
2286 igb_dev_clear_queues(dev);
2290 igbvf_dev_close(struct rte_eth_dev *dev)
2292 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2294 PMD_INIT_FUNC_TRACE();
2298 igbvf_dev_stop(dev);
2301 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2303 struct e1000_mbx_info *mbx = &hw->mbx;
2306 /* After set vlan, vlan strip will also be enabled in igb driver*/
2307 msgbuf[0] = E1000_VF_SET_VLAN;
2309 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2311 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2313 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2316 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2318 struct e1000_hw *hw =
2319 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320 struct e1000_vfta * shadow_vfta =
2321 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2322 int i = 0, j = 0, vfta = 0, mask = 1;
2324 for (i = 0; i < IGB_VFTA_SIZE; i++){
2325 vfta = shadow_vfta->vfta[i];
2328 for (j = 0; j < 32; j++){
2331 (uint16_t)((i<<5)+j), on);
2340 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2342 struct e1000_hw *hw =
2343 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2344 struct e1000_vfta * shadow_vfta =
2345 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2346 uint32_t vid_idx = 0;
2347 uint32_t vid_bit = 0;
2350 PMD_INIT_FUNC_TRACE();
2352 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2353 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2355 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2358 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2359 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2361 /*Save what we set and retore it after device reset*/
2363 shadow_vfta->vfta[vid_idx] |= vid_bit;
2365 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2371 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2372 struct rte_eth_rss_reta_entry64 *reta_conf,
2377 uint16_t idx, shift;
2378 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2381 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2382 "(%d) doesn't match the number hardware can supported "
2383 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2387 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2388 idx = i / RTE_RETA_GROUP_SIZE;
2389 shift = i % RTE_RETA_GROUP_SIZE;
2390 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2394 if (mask == IGB_4_BIT_MASK)
2397 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2398 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2399 if (mask & (0x1 << j))
2400 reta |= reta_conf[idx].reta[shift + j] <<
2403 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2405 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2412 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2413 struct rte_eth_rss_reta_entry64 *reta_conf,
2418 uint16_t idx, shift;
2419 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2421 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2422 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2423 "(%d) doesn't match the number hardware can supported "
2424 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2428 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2429 idx = i / RTE_RETA_GROUP_SIZE;
2430 shift = i % RTE_RETA_GROUP_SIZE;
2431 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2435 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2436 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2437 if (mask & (0x1 << j))
2438 reta_conf[idx].reta[shift + j] =
2439 ((reta >> (CHAR_BIT * j)) &
2447 #define MAC_TYPE_FILTER_SUP(type) do {\
2448 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2449 (type) != e1000_82576)\
2454 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2455 struct rte_eth_syn_filter *filter,
2458 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459 uint32_t synqf, rfctl;
2461 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2464 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2467 if (synqf & E1000_SYN_FILTER_ENABLE)
2470 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2471 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2473 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2474 if (filter->hig_pri)
2475 rfctl |= E1000_RFCTL_SYNQFP;
2477 rfctl &= ~E1000_RFCTL_SYNQFP;
2479 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2481 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2486 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2487 E1000_WRITE_FLUSH(hw);
2492 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2493 struct rte_eth_syn_filter *filter)
2495 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496 uint32_t synqf, rfctl;
2498 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2499 if (synqf & E1000_SYN_FILTER_ENABLE) {
2500 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2501 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2502 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2503 E1000_SYN_FILTER_QUEUE_SHIFT);
2511 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2512 enum rte_filter_op filter_op,
2515 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518 MAC_TYPE_FILTER_SUP(hw->mac.type);
2520 if (filter_op == RTE_ETH_FILTER_NOP)
2524 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2529 switch (filter_op) {
2530 case RTE_ETH_FILTER_ADD:
2531 ret = eth_igb_syn_filter_set(dev,
2532 (struct rte_eth_syn_filter *)arg,
2535 case RTE_ETH_FILTER_DELETE:
2536 ret = eth_igb_syn_filter_set(dev,
2537 (struct rte_eth_syn_filter *)arg,
2540 case RTE_ETH_FILTER_GET:
2541 ret = eth_igb_syn_filter_get(dev,
2542 (struct rte_eth_syn_filter *)arg);
2545 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2553 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
2554 if ((type) != e1000_82580 && (type) != e1000_i350)\
2558 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2560 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2561 struct e1000_2tuple_filter_info *filter_info)
2563 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2565 if (filter->priority > E1000_2TUPLE_MAX_PRI)
2566 return -EINVAL; /* filter index is out of range. */
2567 if (filter->tcp_flags > TCP_FLAG_ALL)
2568 return -EINVAL; /* flags is invalid. */
2570 switch (filter->dst_port_mask) {
2572 filter_info->dst_port_mask = 0;
2573 filter_info->dst_port = filter->dst_port;
2576 filter_info->dst_port_mask = 1;
2579 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2583 switch (filter->proto_mask) {
2585 filter_info->proto_mask = 0;
2586 filter_info->proto = filter->proto;
2589 filter_info->proto_mask = 1;
2592 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2596 filter_info->priority = (uint8_t)filter->priority;
2597 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
2598 filter_info->tcp_flags = filter->tcp_flags;
2600 filter_info->tcp_flags = 0;
2605 static inline struct e1000_2tuple_filter *
2606 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
2607 struct e1000_2tuple_filter_info *key)
2609 struct e1000_2tuple_filter *it;
2611 TAILQ_FOREACH(it, filter_list, entries) {
2612 if (memcmp(key, &it->filter_info,
2613 sizeof(struct e1000_2tuple_filter_info)) == 0) {
2621 * igb_add_2tuple_filter - add a 2tuple filter
2624 * dev: Pointer to struct rte_eth_dev.
2625 * ntuple_filter: ponter to the filter that will be added.
2628 * - On success, zero.
2629 * - On failure, a negative value.
2632 igb_add_2tuple_filter(struct rte_eth_dev *dev,
2633 struct rte_eth_ntuple_filter *ntuple_filter)
2635 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636 struct e1000_filter_info *filter_info =
2637 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2638 struct e1000_2tuple_filter *filter;
2639 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
2640 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
2643 filter = rte_zmalloc("e1000_2tuple_filter",
2644 sizeof(struct e1000_2tuple_filter), 0);
2648 ret = ntuple_filter_to_2tuple(ntuple_filter,
2649 &filter->filter_info);
2654 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2655 &filter->filter_info) != NULL) {
2656 PMD_DRV_LOG(ERR, "filter exists.");
2660 filter->queue = ntuple_filter->queue;
2663 * look for an unused 2tuple filter index,
2664 * and insert the filter to list.
2666 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
2667 if (!(filter_info->twotuple_mask & (1 << i))) {
2668 filter_info->twotuple_mask |= 1 << i;
2670 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
2676 if (i >= E1000_MAX_TTQF_FILTERS) {
2677 PMD_DRV_LOG(ERR, "2tuple filters are full.");
2682 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
2683 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
2684 imir |= E1000_IMIR_PORT_BP;
2686 imir &= ~E1000_IMIR_PORT_BP;
2688 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
2690 ttqf |= E1000_TTQF_QUEUE_ENABLE;
2691 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
2692 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
2693 if (filter->filter_info.proto_mask == 0)
2694 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2696 /* tcp flags bits setting. */
2697 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
2698 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
2699 imir_ext |= E1000_IMIREXT_CTRL_URG;
2700 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
2701 imir_ext |= E1000_IMIREXT_CTRL_ACK;
2702 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
2703 imir_ext |= E1000_IMIREXT_CTRL_PSH;
2704 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
2705 imir_ext |= E1000_IMIREXT_CTRL_RST;
2706 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
2707 imir_ext |= E1000_IMIREXT_CTRL_SYN;
2708 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
2709 imir_ext |= E1000_IMIREXT_CTRL_FIN;
2711 imir_ext |= E1000_IMIREXT_CTRL_BP;
2712 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
2713 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
2714 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
2719 * igb_remove_2tuple_filter - remove a 2tuple filter
2722 * dev: Pointer to struct rte_eth_dev.
2723 * ntuple_filter: ponter to the filter that will be removed.
2726 * - On success, zero.
2727 * - On failure, a negative value.
2730 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2731 struct rte_eth_ntuple_filter *ntuple_filter)
2733 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734 struct e1000_filter_info *filter_info =
2735 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2736 struct e1000_2tuple_filter_info filter_2tuple;
2737 struct e1000_2tuple_filter *filter;
2740 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
2741 ret = ntuple_filter_to_2tuple(ntuple_filter,
2746 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2748 if (filter == NULL) {
2749 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2753 filter_info->twotuple_mask &= ~(1 << filter->index);
2754 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
2757 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
2758 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
2759 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
2763 static inline struct e1000_flex_filter *
2764 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
2765 struct e1000_flex_filter_info *key)
2767 struct e1000_flex_filter *it;
2769 TAILQ_FOREACH(it, filter_list, entries) {
2770 if (memcmp(key, &it->filter_info,
2771 sizeof(struct e1000_flex_filter_info)) == 0)
2779 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
2780 struct rte_eth_flex_filter *filter,
2783 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784 struct e1000_filter_info *filter_info =
2785 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2786 struct e1000_flex_filter *flex_filter, *it;
2787 uint32_t wufc, queueing, mask;
2789 uint8_t shift, i, j = 0;
2791 flex_filter = rte_zmalloc("e1000_flex_filter",
2792 sizeof(struct e1000_flex_filter), 0);
2793 if (flex_filter == NULL)
2796 flex_filter->filter_info.len = filter->len;
2797 flex_filter->filter_info.priority = filter->priority;
2798 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
2799 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
2801 /* reverse bits in flex filter's mask*/
2802 for (shift = 0; shift < CHAR_BIT; shift++) {
2803 if (filter->mask[i] & (0x01 << shift))
2804 mask |= (0x80 >> shift);
2806 flex_filter->filter_info.mask[i] = mask;
2809 wufc = E1000_READ_REG(hw, E1000_WUFC);
2810 if (flex_filter->index < E1000_MAX_FHFT)
2811 reg_off = E1000_FHFT(flex_filter->index);
2813 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
2816 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
2817 &flex_filter->filter_info) != NULL) {
2818 PMD_DRV_LOG(ERR, "filter exists.");
2819 rte_free(flex_filter);
2822 flex_filter->queue = filter->queue;
2824 * look for an unused flex filter index
2825 * and insert the filter into the list.
2827 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
2828 if (!(filter_info->flex_mask & (1 << i))) {
2829 filter_info->flex_mask |= 1 << i;
2830 flex_filter->index = i;
2831 TAILQ_INSERT_TAIL(&filter_info->flex_list,
2837 if (i >= E1000_MAX_FLEX_FILTERS) {
2838 PMD_DRV_LOG(ERR, "flex filters are full.");
2839 rte_free(flex_filter);
2843 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
2844 (E1000_WUFC_FLX0 << flex_filter->index));
2845 queueing = filter->len |
2846 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2847 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2848 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
2850 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
2851 E1000_WRITE_REG(hw, reg_off,
2852 flex_filter->filter_info.dwords[j]);
2853 reg_off += sizeof(uint32_t);
2854 E1000_WRITE_REG(hw, reg_off,
2855 flex_filter->filter_info.dwords[++j]);
2856 reg_off += sizeof(uint32_t);
2857 E1000_WRITE_REG(hw, reg_off,
2858 (uint32_t)flex_filter->filter_info.mask[i]);
2859 reg_off += sizeof(uint32_t) * 2;
2863 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2864 &flex_filter->filter_info);
2866 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2867 rte_free(flex_filter);
2871 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
2872 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
2873 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
2874 (~(E1000_WUFC_FLX0 << it->index)));
2876 filter_info->flex_mask &= ~(1 << it->index);
2877 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
2879 rte_free(flex_filter);
2886 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
2887 struct rte_eth_flex_filter *filter)
2889 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890 struct e1000_filter_info *filter_info =
2891 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2892 struct e1000_flex_filter flex_filter, *it;
2893 uint32_t wufc, queueing, wufc_en = 0;
2895 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
2896 flex_filter.filter_info.len = filter->len;
2897 flex_filter.filter_info.priority = filter->priority;
2898 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
2899 memcpy(flex_filter.filter_info.mask, filter->mask,
2900 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
2902 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2903 &flex_filter.filter_info);
2905 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2909 wufc = E1000_READ_REG(hw, E1000_WUFC);
2910 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
2912 if ((wufc & wufc_en) == wufc_en) {
2913 uint32_t reg_off = 0;
2914 if (it->index < E1000_MAX_FHFT)
2915 reg_off = E1000_FHFT(it->index);
2917 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
2919 queueing = E1000_READ_REG(hw,
2920 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2921 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2922 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2923 E1000_FHFT_QUEUEING_PRIO_SHIFT;
2924 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2925 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2932 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
2933 enum rte_filter_op filter_op,
2936 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2937 struct rte_eth_flex_filter *filter;
2940 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2942 if (filter_op == RTE_ETH_FILTER_NOP)
2946 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2951 filter = (struct rte_eth_flex_filter *)arg;
2952 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
2953 || filter->len % sizeof(uint64_t) != 0) {
2954 PMD_DRV_LOG(ERR, "filter's length is out of range");
2957 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
2958 PMD_DRV_LOG(ERR, "filter's priority is out of range");
2962 switch (filter_op) {
2963 case RTE_ETH_FILTER_ADD:
2964 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
2966 case RTE_ETH_FILTER_DELETE:
2967 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
2969 case RTE_ETH_FILTER_GET:
2970 ret = eth_igb_get_flex_filter(dev, filter);
2973 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
2981 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
2983 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
2984 struct e1000_5tuple_filter_info *filter_info)
2986 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2988 if (filter->priority > E1000_2TUPLE_MAX_PRI)
2989 return -EINVAL; /* filter index is out of range. */
2990 if (filter->tcp_flags > TCP_FLAG_ALL)
2991 return -EINVAL; /* flags is invalid. */
2993 switch (filter->dst_ip_mask) {
2995 filter_info->dst_ip_mask = 0;
2996 filter_info->dst_ip = filter->dst_ip;
2999 filter_info->dst_ip_mask = 1;
3002 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3006 switch (filter->src_ip_mask) {
3008 filter_info->src_ip_mask = 0;
3009 filter_info->src_ip = filter->src_ip;
3012 filter_info->src_ip_mask = 1;
3015 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3019 switch (filter->dst_port_mask) {
3021 filter_info->dst_port_mask = 0;
3022 filter_info->dst_port = filter->dst_port;
3025 filter_info->dst_port_mask = 1;
3028 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3032 switch (filter->src_port_mask) {
3034 filter_info->src_port_mask = 0;
3035 filter_info->src_port = filter->src_port;
3038 filter_info->src_port_mask = 1;
3041 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3045 switch (filter->proto_mask) {
3047 filter_info->proto_mask = 0;
3048 filter_info->proto = filter->proto;
3051 filter_info->proto_mask = 1;
3054 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3058 filter_info->priority = (uint8_t)filter->priority;
3059 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3060 filter_info->tcp_flags = filter->tcp_flags;
3062 filter_info->tcp_flags = 0;
3067 static inline struct e1000_5tuple_filter *
3068 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3069 struct e1000_5tuple_filter_info *key)
3071 struct e1000_5tuple_filter *it;
3073 TAILQ_FOREACH(it, filter_list, entries) {
3074 if (memcmp(key, &it->filter_info,
3075 sizeof(struct e1000_5tuple_filter_info)) == 0) {
3083 * igb_add_5tuple_filter_82576 - add a 5tuple filter
3086 * dev: Pointer to struct rte_eth_dev.
3087 * ntuple_filter: ponter to the filter that will be added.
3090 * - On success, zero.
3091 * - On failure, a negative value.
3094 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3095 struct rte_eth_ntuple_filter *ntuple_filter)
3097 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3098 struct e1000_filter_info *filter_info =
3099 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3100 struct e1000_5tuple_filter *filter;
3101 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3102 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3106 filter = rte_zmalloc("e1000_5tuple_filter",
3107 sizeof(struct e1000_5tuple_filter), 0);
3111 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3112 &filter->filter_info);
3118 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3119 &filter->filter_info) != NULL) {
3120 PMD_DRV_LOG(ERR, "filter exists.");
3124 filter->queue = ntuple_filter->queue;
3127 * look for an unused 5tuple filter index,
3128 * and insert the filter to list.
3130 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3131 if (!(filter_info->fivetuple_mask & (1 << i))) {
3132 filter_info->fivetuple_mask |= 1 << i;
3134 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3140 if (i >= E1000_MAX_FTQF_FILTERS) {
3141 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3146 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3147 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3148 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3149 if (filter->filter_info.dst_ip_mask == 0)
3150 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3151 if (filter->filter_info.src_port_mask == 0)
3152 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3153 if (filter->filter_info.proto_mask == 0)
3154 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3155 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3156 E1000_FTQF_QUEUE_MASK;
3157 ftqf |= E1000_FTQF_QUEUE_ENABLE;
3158 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3159 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3160 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3162 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3163 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3165 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3166 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3167 imir |= E1000_IMIR_PORT_BP;
3169 imir &= ~E1000_IMIR_PORT_BP;
3170 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3172 /* tcp flags bits setting. */
3173 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3174 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3175 imir_ext |= E1000_IMIREXT_CTRL_URG;
3176 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3177 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3178 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3179 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3180 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3181 imir_ext |= E1000_IMIREXT_CTRL_RST;
3182 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3183 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3184 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3185 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3187 imir_ext |= E1000_IMIREXT_CTRL_BP;
3188 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3189 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3194 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3197 * dev: Pointer to struct rte_eth_dev.
3198 * ntuple_filter: ponter to the filter that will be removed.
3201 * - On success, zero.
3202 * - On failure, a negative value.
3205 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3206 struct rte_eth_ntuple_filter *ntuple_filter)
3208 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3209 struct e1000_filter_info *filter_info =
3210 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3211 struct e1000_5tuple_filter_info filter_5tuple;
3212 struct e1000_5tuple_filter *filter;
3215 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3216 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3221 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3223 if (filter == NULL) {
3224 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3228 filter_info->fivetuple_mask &= ~(1 << filter->index);
3229 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3232 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3233 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3234 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3235 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3236 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3237 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3238 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3243 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3246 struct e1000_hw *hw;
3247 struct rte_eth_dev_info dev_info;
3248 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3251 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3253 #ifdef RTE_LIBRTE_82571_SUPPORT
3254 /* XXX: not bigger than max_rx_pktlen */
3255 if (hw->mac.type == e1000_82571)
3258 eth_igb_infos_get(dev, &dev_info);
3260 /* check that mtu is within the allowed range */
3261 if ((mtu < ETHER_MIN_MTU) ||
3262 (frame_size > dev_info.max_rx_pktlen))
3265 /* refuse mtu that requires the support of scattered packets when this
3266 * feature has not been enabled before. */
3267 if (!dev->data->scattered_rx &&
3268 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3271 rctl = E1000_READ_REG(hw, E1000_RCTL);
3273 /* switch to jumbo mode if needed */
3274 if (frame_size > ETHER_MAX_LEN) {
3275 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3276 rctl |= E1000_RCTL_LPE;
3278 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3279 rctl &= ~E1000_RCTL_LPE;
3281 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3283 /* update max frame size */
3284 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3286 E1000_WRITE_REG(hw, E1000_RLPML,
3287 dev->data->dev_conf.rxmode.max_rx_pkt_len);
3293 * igb_add_del_ntuple_filter - add or delete a ntuple filter
3296 * dev: Pointer to struct rte_eth_dev.
3297 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3298 * add: if true, add filter, if false, remove filter
3301 * - On success, zero.
3302 * - On failure, a negative value.
3305 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3306 struct rte_eth_ntuple_filter *ntuple_filter,
3309 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312 switch (ntuple_filter->flags) {
3313 case RTE_5TUPLE_FLAGS:
3314 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3315 if (hw->mac.type != e1000_82576)
3318 ret = igb_add_5tuple_filter_82576(dev,
3321 ret = igb_remove_5tuple_filter_82576(dev,
3324 case RTE_2TUPLE_FLAGS:
3325 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3326 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3329 ret = igb_add_2tuple_filter(dev, ntuple_filter);
3331 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3342 * igb_get_ntuple_filter - get a ntuple filter
3345 * dev: Pointer to struct rte_eth_dev.
3346 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3349 * - On success, zero.
3350 * - On failure, a negative value.
3353 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3354 struct rte_eth_ntuple_filter *ntuple_filter)
3356 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3357 struct e1000_filter_info *filter_info =
3358 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3359 struct e1000_5tuple_filter_info filter_5tuple;
3360 struct e1000_2tuple_filter_info filter_2tuple;
3361 struct e1000_5tuple_filter *p_5tuple_filter;
3362 struct e1000_2tuple_filter *p_2tuple_filter;
3365 switch (ntuple_filter->flags) {
3366 case RTE_5TUPLE_FLAGS:
3367 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3368 if (hw->mac.type != e1000_82576)
3370 memset(&filter_5tuple,
3372 sizeof(struct e1000_5tuple_filter_info));
3373 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3377 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3378 &filter_info->fivetuple_list,
3380 if (p_5tuple_filter == NULL) {
3381 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3384 ntuple_filter->queue = p_5tuple_filter->queue;
3386 case RTE_2TUPLE_FLAGS:
3387 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3388 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3390 memset(&filter_2tuple,
3392 sizeof(struct e1000_2tuple_filter_info));
3393 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3396 p_2tuple_filter = igb_2tuple_filter_lookup(
3397 &filter_info->twotuple_list,
3399 if (p_2tuple_filter == NULL) {
3400 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3403 ntuple_filter->queue = p_2tuple_filter->queue;
3414 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3415 * @dev: pointer to rte_eth_dev structure
3416 * @filter_op:operation will be taken.
3417 * @arg: a pointer to specific structure corresponding to the filter_op
3420 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3421 enum rte_filter_op filter_op,
3424 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3427 MAC_TYPE_FILTER_SUP(hw->mac.type);
3429 if (filter_op == RTE_ETH_FILTER_NOP)
3433 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3438 switch (filter_op) {
3439 case RTE_ETH_FILTER_ADD:
3440 ret = igb_add_del_ntuple_filter(dev,
3441 (struct rte_eth_ntuple_filter *)arg,
3444 case RTE_ETH_FILTER_DELETE:
3445 ret = igb_add_del_ntuple_filter(dev,
3446 (struct rte_eth_ntuple_filter *)arg,
3449 case RTE_ETH_FILTER_GET:
3450 ret = igb_get_ntuple_filter(dev,
3451 (struct rte_eth_ntuple_filter *)arg);
3454 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3462 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3467 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3468 if (filter_info->ethertype_filters[i] == ethertype &&
3469 (filter_info->ethertype_mask & (1 << i)))
3476 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3481 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3482 if (!(filter_info->ethertype_mask & (1 << i))) {
3483 filter_info->ethertype_mask |= 1 << i;
3484 filter_info->ethertype_filters[i] = ethertype;
3492 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3495 if (idx >= E1000_MAX_ETQF_FILTERS)
3497 filter_info->ethertype_mask &= ~(1 << idx);
3498 filter_info->ethertype_filters[idx] = 0;
3504 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3505 struct rte_eth_ethertype_filter *filter,
3508 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3509 struct e1000_filter_info *filter_info =
3510 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3514 if (filter->ether_type == ETHER_TYPE_IPv4 ||
3515 filter->ether_type == ETHER_TYPE_IPv6) {
3516 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3517 " ethertype filter.", filter->ether_type);
3521 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3522 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3525 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3526 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3530 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3531 if (ret >= 0 && add) {
3532 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3533 filter->ether_type);
3536 if (ret < 0 && !add) {
3537 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3538 filter->ether_type);
3543 ret = igb_ethertype_filter_insert(filter_info,
3544 filter->ether_type);
3546 PMD_DRV_LOG(ERR, "ethertype filters are full.");
3550 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3551 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3552 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3554 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3558 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3559 E1000_WRITE_FLUSH(hw);
3565 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3566 struct rte_eth_ethertype_filter *filter)
3568 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3569 struct e1000_filter_info *filter_info =
3570 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3574 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3576 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3577 filter->ether_type);
3581 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3582 if (etqf & E1000_ETQF_FILTER_ENABLE) {
3583 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3585 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3586 E1000_ETQF_QUEUE_SHIFT;
3594 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3595 * @dev: pointer to rte_eth_dev structure
3596 * @filter_op:operation will be taken.
3597 * @arg: a pointer to specific structure corresponding to the filter_op
3600 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3601 enum rte_filter_op filter_op,
3604 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3607 MAC_TYPE_FILTER_SUP(hw->mac.type);
3609 if (filter_op == RTE_ETH_FILTER_NOP)
3613 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3618 switch (filter_op) {
3619 case RTE_ETH_FILTER_ADD:
3620 ret = igb_add_del_ethertype_filter(dev,
3621 (struct rte_eth_ethertype_filter *)arg,
3624 case RTE_ETH_FILTER_DELETE:
3625 ret = igb_add_del_ethertype_filter(dev,
3626 (struct rte_eth_ethertype_filter *)arg,
3629 case RTE_ETH_FILTER_GET:
3630 ret = igb_get_ethertype_filter(dev,
3631 (struct rte_eth_ethertype_filter *)arg);
3634 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3642 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3643 enum rte_filter_type filter_type,
3644 enum rte_filter_op filter_op,
3649 switch (filter_type) {
3650 case RTE_ETH_FILTER_NTUPLE:
3651 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
3653 case RTE_ETH_FILTER_ETHERTYPE:
3654 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3656 case RTE_ETH_FILTER_SYN:
3657 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3659 case RTE_ETH_FILTER_FLEXIBLE:
3660 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3663 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3672 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
3673 struct ether_addr *mc_addr_set,
3674 uint32_t nb_mc_addr)
3676 struct e1000_hw *hw;
3678 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
3684 igb_timesync_enable(struct rte_eth_dev *dev)
3686 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3689 /* Start incrementing the register used to timestamp PTP packets. */
3690 E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
3692 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3693 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
3695 E1000_ETQF_FILTER_ENABLE |
3698 /* Enable timestamping of received PTP packets. */
3699 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3700 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
3701 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
3703 /* Enable Timestamping of transmitted PTP packets. */
3704 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3705 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
3706 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
3712 igb_timesync_disable(struct rte_eth_dev *dev)
3714 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3717 /* Disable timestamping of transmitted PTP packets. */
3718 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3719 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
3720 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
3722 /* Disable timestamping of received PTP packets. */
3723 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3724 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
3725 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
3727 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3728 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
3730 /* Stop incrementating the System Time registers. */
3731 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
3737 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3738 struct timespec *timestamp,
3739 uint32_t flags __rte_unused)
3741 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3742 uint32_t tsync_rxctl;
3746 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3747 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
3750 rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
3751 rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
3753 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
3754 timestamp->tv_nsec = 0;
3760 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3761 struct timespec *timestamp)
3763 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764 uint32_t tsync_txctl;
3768 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3769 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
3772 tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
3773 tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
3775 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
3776 timestamp->tv_nsec = 0;
3781 static struct rte_driver pmd_igb_drv = {
3783 .init = rte_igb_pmd_init,
3786 static struct rte_driver pmd_igbvf_drv = {
3788 .init = rte_igbvf_pmd_init,
3791 PMD_REGISTER_DRIVER(pmd_igb_drv);
3792 PMD_REGISTER_DRIVER(pmd_igbvf_drv);