drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static int eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter);
 218 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 219                         enum rte_filter_op filter_op,
 220                         void *arg);
 221 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 222                         struct rte_eth_ntuple_filter *ntuple_filter);
 223 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_ntuple_filter *ntuple_filter);
 225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 226                         struct rte_eth_flex_filter *filter);
 227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 228                         enum rte_filter_op filter_op,
 229                         void *arg);
 230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *ntuple_filter);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 240                                 enum rte_filter_op filter_op,
 241                                 void *arg);
 242 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter);
 244 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 245                      enum rte_filter_type filter_type,
 246                      enum rte_filter_op filter_op,
 247                      void *arg);
 248 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 249 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 250                 struct rte_dev_reg_info *regs);
 251 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 253                 struct rte_dev_eeprom_info *eeprom);
 254 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 255                 struct rte_dev_eeprom_info *eeprom);
 256 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 257                                     struct ether_addr *mc_addr_set,
 258                                     uint32_t nb_mc_addr);
 259 static int igb_timesync_enable(struct rte_eth_dev *dev);
 260 static int igb_timesync_disable(struct rte_eth_dev *dev);
 261 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 262                                           struct timespec *timestamp,
 263                                           uint32_t flags);
 264 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp);
 266 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 267 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 268                                   struct timespec *timestamp);
 269 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 270                                    const struct timespec *timestamp);
 271 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                         uint16_t queue_id);
 273 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                          uint16_t queue_id);
 275 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 276                                        uint8_t queue, uint8_t msix_vector);
 277 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 278                                uint8_t index, uint8_t offset);
 279 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 280 static void eth_igbvf_interrupt_handler(void *param);
 281 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 282 static int igb_filter_restore(struct rte_eth_dev *dev);
 283
 284 /*
 285  * Define VF Stats MACRO for Non "cleared on read" register
 286  */
 287 #define UPDATE_VF_STAT(reg, last, cur)            \
 288 {                                                 \
 289         u32 latest = E1000_READ_REG(hw, reg);     \
 290         cur += (latest - last) & UINT_MAX;        \
 291         last = latest;                            \
 292 }
 293
 294 #define IGB_FC_PAUSE_TIME 0x0680
 295 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 296 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 297
 298 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 299
 300 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 301
 302 /*
 303  * The set of PCI devices this driver supports
 304  */
 305 static const struct rte_pci_id pci_id_igb_map[] = {
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 314
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 325
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 347         { .vendor_id = 0, /* sentinel */ },
 348 };
 349
 350 /*
 351  * The set of PCI devices this driver supports (for 82576&I350 VF)
 352  */
 353 static const struct rte_pci_id pci_id_igbvf_map[] = {
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 358         { .vendor_id = 0, /* sentinel */ },
 359 };
 360
 361 static const struct rte_eth_desc_lim rx_desc_lim = {
 362         .nb_max = E1000_MAX_RING_DESC,
 363         .nb_min = E1000_MIN_RING_DESC,
 364         .nb_align = IGB_RXD_ALIGN,
 365 };
 366
 367 static const struct rte_eth_desc_lim tx_desc_lim = {
 368         .nb_max = E1000_MAX_RING_DESC,
 369         .nb_min = E1000_MIN_RING_DESC,
 370         .nb_align = IGB_RXD_ALIGN,
 371         .nb_seg_max = IGB_TX_MAX_SEG,
 372         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 373 };
 374
 375 static const struct eth_dev_ops eth_igb_ops = {
 376         .dev_configure        = eth_igb_configure,
 377         .dev_start            = eth_igb_start,
 378         .dev_stop             = eth_igb_stop,
 379         .dev_set_link_up      = eth_igb_dev_set_link_up,
 380         .dev_set_link_down    = eth_igb_dev_set_link_down,
 381         .dev_close            = eth_igb_close,
 382         .promiscuous_enable   = eth_igb_promiscuous_enable,
 383         .promiscuous_disable  = eth_igb_promiscuous_disable,
 384         .allmulticast_enable  = eth_igb_allmulticast_enable,
 385         .allmulticast_disable = eth_igb_allmulticast_disable,
 386         .link_update          = eth_igb_link_update,
 387         .stats_get            = eth_igb_stats_get,
 388         .xstats_get           = eth_igb_xstats_get,
 389         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 390         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 391         .xstats_get_names     = eth_igb_xstats_get_names,
 392         .stats_reset          = eth_igb_stats_reset,
 393         .xstats_reset         = eth_igb_xstats_reset,
 394         .fw_version_get       = eth_igb_fw_version_get,
 395         .dev_infos_get        = eth_igb_infos_get,
 396         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 397         .mtu_set              = eth_igb_mtu_set,
 398         .vlan_filter_set      = eth_igb_vlan_filter_set,
 399         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 400         .vlan_offload_set     = eth_igb_vlan_offload_set,
 401         .rx_queue_setup       = eth_igb_rx_queue_setup,
 402         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 403         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 404         .rx_queue_release     = eth_igb_rx_queue_release,
 405         .rx_queue_count       = eth_igb_rx_queue_count,
 406         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 407         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 408         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 409         .tx_queue_setup       = eth_igb_tx_queue_setup,
 410         .tx_queue_release     = eth_igb_tx_queue_release,
 411         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 412         .dev_led_on           = eth_igb_led_on,
 413         .dev_led_off          = eth_igb_led_off,
 414         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 415         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 416         .mac_addr_add         = eth_igb_rar_set,
 417         .mac_addr_remove      = eth_igb_rar_clear,
 418         .mac_addr_set         = eth_igb_default_mac_addr_set,
 419         .reta_update          = eth_igb_rss_reta_update,
 420         .reta_query           = eth_igb_rss_reta_query,
 421         .rss_hash_update      = eth_igb_rss_hash_update,
 422         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 423         .filter_ctrl          = eth_igb_filter_ctrl,
 424         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 425         .rxq_info_get         = igb_rxq_info_get,
 426         .txq_info_get         = igb_txq_info_get,
 427         .timesync_enable      = igb_timesync_enable,
 428         .timesync_disable     = igb_timesync_disable,
 429         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 430         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 431         .get_reg              = eth_igb_get_regs,
 432         .get_eeprom_length    = eth_igb_get_eeprom_length,
 433         .get_eeprom           = eth_igb_get_eeprom,
 434         .set_eeprom           = eth_igb_set_eeprom,
 435         .timesync_adjust_time = igb_timesync_adjust_time,
 436         .timesync_read_time   = igb_timesync_read_time,
 437         .timesync_write_time  = igb_timesync_write_time,
 438 };
 439
 440 /*
 441  * dev_ops for virtual function, bare necessities for basic vf
 442  * operation have been implemented
 443  */
 444 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 445         .dev_configure        = igbvf_dev_configure,
 446         .dev_start            = igbvf_dev_start,
 447         .dev_stop             = igbvf_dev_stop,
 448         .dev_close            = igbvf_dev_close,
 449         .promiscuous_enable   = igbvf_promiscuous_enable,
 450         .promiscuous_disable  = igbvf_promiscuous_disable,
 451         .allmulticast_enable  = igbvf_allmulticast_enable,
 452         .allmulticast_disable = igbvf_allmulticast_disable,
 453         .link_update          = eth_igb_link_update,
 454         .stats_get            = eth_igbvf_stats_get,
 455         .xstats_get           = eth_igbvf_xstats_get,
 456         .xstats_get_names     = eth_igbvf_xstats_get_names,
 457         .stats_reset          = eth_igbvf_stats_reset,
 458         .xstats_reset         = eth_igbvf_stats_reset,
 459         .vlan_filter_set      = igbvf_vlan_filter_set,
 460         .dev_infos_get        = eth_igbvf_infos_get,
 461         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 462         .rx_queue_setup       = eth_igb_rx_queue_setup,
 463         .rx_queue_release     = eth_igb_rx_queue_release,
 464         .tx_queue_setup       = eth_igb_tx_queue_setup,
 465         .tx_queue_release     = eth_igb_tx_queue_release,
 466         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 467         .rxq_info_get         = igb_rxq_info_get,
 468         .txq_info_get         = igb_txq_info_get,
 469         .mac_addr_set         = igbvf_default_mac_addr_set,
 470         .get_reg              = igbvf_get_regs,
 471 };
 472
 473 /* store statistics names and its offset in stats structure */
 474 struct rte_igb_xstats_name_off {
 475         char name[RTE_ETH_XSTATS_NAME_SIZE];
 476         unsigned offset;
 477 };
 478
 479 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 480         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 481         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 482         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 483         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 484         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 485         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 486         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 487                 ecol)},
 488         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 489         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 490         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 491         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 492         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 493         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 494         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 495         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 496         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 497         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 498         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 499                 fcruc)},
 500         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 501         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 502         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 503         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 504         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 505                 prc1023)},
 506         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 507                 prc1522)},
 508         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 509         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 510         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 511         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 512         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 513         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 514         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 515         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 516         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 517         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 518         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 519         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 520         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 521         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 522         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 523         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 524         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 525         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 526                 ptc1023)},
 527         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 528                 ptc1522)},
 529         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 530         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 531         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 532         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 533         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 534         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 535         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 536
 537         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 538 };
 539
 540 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 541                 sizeof(rte_igb_stats_strings[0]))
 542
 543 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 544         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 545         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 546         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 547         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 548         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 549 };
 550
 551 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 552                 sizeof(rte_igbvf_stats_strings[0]))
 553
 554 /**
 555  * Atomically reads the link status information from global
 556  * structure rte_eth_dev.
 557  *
 558  * @param dev
 559  *   - Pointer to the structure rte_eth_dev to read from.
 560  *   - Pointer to the buffer to be saved with the link status.
 561  *
 562  * @return
 563  *   - On success, zero.
 564  *   - On failure, negative value.
 565  */
 566 static inline int
 567 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 568                                 struct rte_eth_link *link)
 569 {
 570         struct rte_eth_link *dst = link;
 571         struct rte_eth_link *src = &(dev->data->dev_link);
 572
 573         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 574                                         *(uint64_t *)src) == 0)
 575                 return -1;
 576
 577         return 0;
 578 }
 579
 580 /**
 581  * Atomically writes the link status information into global
 582  * structure rte_eth_dev.
 583  *
 584  * @param dev
 585  *   - Pointer to the structure rte_eth_dev to read from.
 586  *   - Pointer to the buffer to be saved with the link status.
 587  *
 588  * @return
 589  *   - On success, zero.
 590  *   - On failure, negative value.
 591  */
 592 static inline int
 593 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 594                                 struct rte_eth_link *link)
 595 {
 596         struct rte_eth_link *dst = &(dev->data->dev_link);
 597         struct rte_eth_link *src = link;
 598
 599         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 600                                         *(uint64_t *)src) == 0)
 601                 return -1;
 602
 603         return 0;
 604 }
 605
 606 static inline void
 607 igb_intr_enable(struct rte_eth_dev *dev)
 608 {
 609         struct e1000_interrupt *intr =
 610                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 611         struct e1000_hw *hw =
 612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 613
 614         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 615         E1000_WRITE_FLUSH(hw);
 616 }
 617
 618 static void
 619 igb_intr_disable(struct e1000_hw *hw)
 620 {
 621         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 622         E1000_WRITE_FLUSH(hw);
 623 }
 624
 625 static inline void
 626 igbvf_intr_enable(struct rte_eth_dev *dev)
 627 {
 628         struct e1000_hw *hw =
 629                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 630
 631         /* only for mailbox */
 632         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 633         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 634         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 635         E1000_WRITE_FLUSH(hw);
 636 }
 637
 638 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 639 static void
 640 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 641 {
 642         uint32_t tmp = 0;
 643
 644         /* mailbox */
 645         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 646         tmp |= E1000_VTIVAR_VALID;
 647         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 648 }
 649
 650 static void
 651 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 652 {
 653         struct e1000_hw *hw =
 654                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655
 656         /* Configure VF other cause ivar */
 657         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 658 }
 659
 660 static inline int32_t
 661 igb_pf_reset_hw(struct e1000_hw *hw)
 662 {
 663         uint32_t ctrl_ext;
 664         int32_t status;
 665
 666         status = e1000_reset_hw(hw);
 667
 668         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 669         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 670         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 671         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 672         E1000_WRITE_FLUSH(hw);
 673
 674         return status;
 675 }
 676
 677 static void
 678 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 679 {
 680         struct e1000_hw *hw =
 681                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 682
 683
 684         hw->vendor_id = pci_dev->id.vendor_id;
 685         hw->device_id = pci_dev->id.device_id;
 686         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 687         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 688
 689         e1000_set_mac_type(hw);
 690
 691         /* need to check if it is a vf device below */
 692 }
 693
 694 static int
 695 igb_reset_swfw_lock(struct e1000_hw *hw)
 696 {
 697         int ret_val;
 698
 699         /*
 700          * Do mac ops initialization manually here, since we will need
 701          * some function pointers set by this call.
 702          */
 703         ret_val = e1000_init_mac_params(hw);
 704         if (ret_val)
 705                 return ret_val;
 706
 707         /*
 708          * SMBI lock should not fail in this early stage. If this is the case,
 709          * it is due to an improper exit of the application.
 710          * So force the release of the faulty lock.
 711          */
 712         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 713                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 714         }
 715         e1000_put_hw_semaphore_generic(hw);
 716
 717         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 718                 uint16_t mask;
 719
 720                 /*
 721                  * Phy lock should not fail in this early stage. If this is the case,
 722                  * it is due to an improper exit of the application.
 723                  * So force the release of the faulty lock.
 724                  */
 725                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 726                 if (hw->bus.func > E1000_FUNC_1)
 727                         mask <<= 2;
 728                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 729                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 730                                     hw->bus.func);
 731                 }
 732                 hw->mac.ops.release_swfw_sync(hw, mask);
 733
 734                 /*
 735                  * This one is more tricky since it is common to all ports; but
 736                  * swfw_sync retries last long enough (1s) to be almost sure that if
 737                  * lock can not be taken it is due to an improper lock of the
 738                  * semaphore.
 739                  */
 740                 mask = E1000_SWFW_EEP_SM;
 741                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 742                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 743                 }
 744                 hw->mac.ops.release_swfw_sync(hw, mask);
 745         }
 746
 747         return E1000_SUCCESS;
 748 }
 749
 750 /* Remove all ntuple filters of the device */
 751 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 752 {
 753         struct e1000_filter_info *filter_info =
 754                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 755         struct e1000_5tuple_filter *p_5tuple;
 756         struct e1000_2tuple_filter *p_2tuple;
 757
 758         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 759                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 760                         p_5tuple, entries);
 761                         rte_free(p_5tuple);
 762         }
 763         filter_info->fivetuple_mask = 0;
 764         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 765                 TAILQ_REMOVE(&filter_info->twotuple_list,
 766                         p_2tuple, entries);
 767                         rte_free(p_2tuple);
 768         }
 769         filter_info->twotuple_mask = 0;
 770
 771         return 0;
 772 }
 773
 774 /* Remove all flex filters of the device */
 775 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 776 {
 777         struct e1000_filter_info *filter_info =
 778                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 779         struct e1000_flex_filter *p_flex;
 780
 781         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 782                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 783                 rte_free(p_flex);
 784         }
 785         filter_info->flex_mask = 0;
 786
 787         return 0;
 788 }
 789
 790 static int
 791 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 792 {
 793         int error = 0;
 794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 795         struct e1000_hw *hw =
 796                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 797         struct e1000_vfta * shadow_vfta =
 798                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 799         struct e1000_filter_info *filter_info =
 800                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 801         struct e1000_adapter *adapter =
 802                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 803
 804         uint32_t ctrl_ext;
 805
 806         eth_dev->dev_ops = &eth_igb_ops;
 807         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 808         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 809         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 810
 811         /* for secondary processes, we don't initialise any further as primary
 812          * has already done this work. Only check we don't need a different
 813          * RX function */
 814         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 815                 if (eth_dev->data->scattered_rx)
 816                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 817                 return 0;
 818         }
 819
 820         rte_eth_copy_pci_info(eth_dev, pci_dev);
 821         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 822
 823         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 824
 825         igb_identify_hardware(eth_dev, pci_dev);
 826         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 827                 error = -EIO;
 828                 goto err_late;
 829         }
 830
 831         e1000_get_bus_info(hw);
 832
 833         /* Reset any pending lock */
 834         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 835                 error = -EIO;
 836                 goto err_late;
 837         }
 838
 839         /* Finish initialization */
 840         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 841                 error = -EIO;
 842                 goto err_late;
 843         }
 844
 845         hw->mac.autoneg = 1;
 846         hw->phy.autoneg_wait_to_complete = 0;
 847         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 848
 849         /* Copper options */
 850         if (hw->phy.media_type == e1000_media_type_copper) {
 851                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 852                 hw->phy.disable_polarity_correction = 0;
 853                 hw->phy.ms_type = e1000_ms_hw_default;
 854         }
 855
 856         /*
 857          * Start from a known state, this is important in reading the nvm
 858          * and mac from that.
 859          */
 860         igb_pf_reset_hw(hw);
 861
 862         /* Make sure we have a good EEPROM before we read from it */
 863         if (e1000_validate_nvm_checksum(hw) < 0) {
 864                 /*
 865                  * Some PCI-E parts fail the first check due to
 866                  * the link being in sleep state, call it again,
 867                  * if it fails a second time its a real issue.
 868                  */
 869                 if (e1000_validate_nvm_checksum(hw) < 0) {
 870                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 871                         error = -EIO;
 872                         goto err_late;
 873                 }
 874         }
 875
 876         /* Read the permanent MAC address out of the EEPROM */
 877         if (e1000_read_mac_addr(hw) != 0) {
 878                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 879                 error = -EIO;
 880                 goto err_late;
 881         }
 882
 883         /* Allocate memory for storing MAC addresses */
 884         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 885                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 886         if (eth_dev->data->mac_addrs == NULL) {
 887                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 888                                                 "store MAC addresses",
 889                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 890                 error = -ENOMEM;
 891                 goto err_late;
 892         }
 893
 894         /* Copy the permanent MAC address */
 895         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 896
 897         /* initialize the vfta */
 898         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 899
 900         /* Now initialize the hardware */
 901         if (igb_hardware_init(hw) != 0) {
 902                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 903                 rte_free(eth_dev->data->mac_addrs);
 904                 eth_dev->data->mac_addrs = NULL;
 905                 error = -ENODEV;
 906                 goto err_late;
 907         }
 908         hw->mac.get_link_status = 1;
 909         adapter->stopped = 0;
 910
 911         /* Indicate SOL/IDER usage */
 912         if (e1000_check_reset_block(hw) < 0) {
 913                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 914                                         "SOL/IDER session");
 915         }
 916
 917         /* initialize PF if max_vfs not zero */
 918         igb_pf_host_init(eth_dev);
 919
 920         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 921         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 922         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 923         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 924         E1000_WRITE_FLUSH(hw);
 925
 926         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 927                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 928                      pci_dev->id.device_id);
 929
 930         rte_intr_callback_register(&pci_dev->intr_handle,
 931                                    eth_igb_interrupt_handler,
 932                                    (void *)eth_dev);
 933
 934         /* enable uio/vfio intr/eventfd mapping */
 935         rte_intr_enable(&pci_dev->intr_handle);
 936
 937         /* enable support intr */
 938         igb_intr_enable(eth_dev);
 939
 940         /* initialize filter info */
 941         memset(filter_info, 0,
 942                sizeof(struct e1000_filter_info));
 943
 944         TAILQ_INIT(&filter_info->flex_list);
 945         TAILQ_INIT(&filter_info->twotuple_list);
 946         TAILQ_INIT(&filter_info->fivetuple_list);
 947
 948         TAILQ_INIT(&igb_filter_ntuple_list);
 949         TAILQ_INIT(&igb_filter_ethertype_list);
 950         TAILQ_INIT(&igb_filter_syn_list);
 951         TAILQ_INIT(&igb_filter_flex_list);
 952         TAILQ_INIT(&igb_flow_list);
 953
 954         return 0;
 955
 956 err_late:
 957         igb_hw_control_release(hw);
 958
 959         return error;
 960 }
 961
 962 static int
 963 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 964 {
 965         struct rte_pci_device *pci_dev;
 966         struct rte_intr_handle *intr_handle;
 967         struct e1000_hw *hw;
 968         struct e1000_adapter *adapter =
 969                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 970         struct e1000_filter_info *filter_info =
 971                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 972
 973         PMD_INIT_FUNC_TRACE();
 974
 975         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 976                 return -EPERM;
 977
 978         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 979         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 980         intr_handle = &pci_dev->intr_handle;
 981
 982         if (adapter->stopped == 0)
 983                 eth_igb_close(eth_dev);
 984
 985         eth_dev->dev_ops = NULL;
 986         eth_dev->rx_pkt_burst = NULL;
 987         eth_dev->tx_pkt_burst = NULL;
 988
 989         /* Reset any pending lock */
 990         igb_reset_swfw_lock(hw);
 991
 992         rte_free(eth_dev->data->mac_addrs);
 993         eth_dev->data->mac_addrs = NULL;
 994
 995         /* uninitialize PF if max_vfs not zero */
 996         igb_pf_host_uninit(eth_dev);
 997
 998         /* disable uio intr before callback unregister */
 999         rte_intr_disable(intr_handle);
1000         rte_intr_callback_unregister(intr_handle,
1001                                      eth_igb_interrupt_handler, eth_dev);
1002
1003         /* clear the SYN filter info */
1004         filter_info->syn_info = 0;
1005
1006         /* clear the ethertype filters info */
1007         filter_info->ethertype_mask = 0;
1008         memset(filter_info->ethertype_filters, 0,
1009                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1010
1011         /* remove all ntuple filters of the device */
1012         igb_ntuple_filter_uninit(eth_dev);
1013
1014         /* remove all flex filters of the device */
1015         igb_flex_filter_uninit(eth_dev);
1016
1017         /* clear all the filters list */
1018         igb_filterlist_flush(eth_dev);
1019
1020         return 0;
1021 }
1022
1023 /*
1024  * Virtual Function device init
1025  */
1026 static int
1027 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1028 {
1029         struct rte_pci_device *pci_dev;
1030         struct rte_intr_handle *intr_handle;
1031         struct e1000_adapter *adapter =
1032                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1033         struct e1000_hw *hw =
1034                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1035         int diag;
1036         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1037
1038         PMD_INIT_FUNC_TRACE();
1039
1040         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1041         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1042         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1043         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1044
1045         /* for secondary processes, we don't initialise any further as primary
1046          * has already done this work. Only check we don't need a different
1047          * RX function */
1048         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1049                 if (eth_dev->data->scattered_rx)
1050                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1051                 return 0;
1052         }
1053
1054         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1055         rte_eth_copy_pci_info(eth_dev, pci_dev);
1056         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1057
1058         hw->device_id = pci_dev->id.device_id;
1059         hw->vendor_id = pci_dev->id.vendor_id;
1060         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1061         adapter->stopped = 0;
1062
1063         /* Initialize the shared code (base driver) */
1064         diag = e1000_setup_init_funcs(hw, TRUE);
1065         if (diag != 0) {
1066                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1067                         diag);
1068                 return -EIO;
1069         }
1070
1071         /* init_mailbox_params */
1072         hw->mbx.ops.init_params(hw);
1073
1074         /* Disable the interrupts for VF */
1075         igbvf_intr_disable(hw);
1076
1077         diag = hw->mac.ops.reset_hw(hw);
1078
1079         /* Allocate memory for storing MAC addresses */
1080         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1081                 hw->mac.rar_entry_count, 0);
1082         if (eth_dev->data->mac_addrs == NULL) {
1083                 PMD_INIT_LOG(ERR,
1084                         "Failed to allocate %d bytes needed to store MAC "
1085                         "addresses",
1086                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1087                 return -ENOMEM;
1088         }
1089
1090         /* Generate a random MAC address, if none was assigned by PF. */
1091         if (is_zero_ether_addr(perm_addr)) {
1092                 eth_random_addr(perm_addr->addr_bytes);
1093                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1094                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1095                              "%02x:%02x:%02x:%02x:%02x:%02x",
1096                              perm_addr->addr_bytes[0],
1097                              perm_addr->addr_bytes[1],
1098                              perm_addr->addr_bytes[2],
1099                              perm_addr->addr_bytes[3],
1100                              perm_addr->addr_bytes[4],
1101                              perm_addr->addr_bytes[5]);
1102         }
1103
1104         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1105         if (diag) {
1106                 rte_free(eth_dev->data->mac_addrs);
1107                 eth_dev->data->mac_addrs = NULL;
1108                 return diag;
1109         }
1110         /* Copy the permanent MAC address */
1111         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1112                         &eth_dev->data->mac_addrs[0]);
1113
1114         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1115                      "mac.type=%s",
1116                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1117                      pci_dev->id.device_id, "igb_mac_82576_vf");
1118
1119         intr_handle = &pci_dev->intr_handle;
1120         rte_intr_callback_register(intr_handle,
1121                                    eth_igbvf_interrupt_handler, eth_dev);
1122
1123         return 0;
1124 }
1125
1126 static int
1127 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1128 {
1129         struct e1000_adapter *adapter =
1130                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1131         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1132
1133         PMD_INIT_FUNC_TRACE();
1134
1135         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1136                 return -EPERM;
1137
1138         if (adapter->stopped == 0)
1139                 igbvf_dev_close(eth_dev);
1140
1141         eth_dev->dev_ops = NULL;
1142         eth_dev->rx_pkt_burst = NULL;
1143         eth_dev->tx_pkt_burst = NULL;
1144
1145         rte_free(eth_dev->data->mac_addrs);
1146         eth_dev->data->mac_addrs = NULL;
1147
1148         /* disable uio intr before callback unregister */
1149         rte_intr_disable(&pci_dev->intr_handle);
1150         rte_intr_callback_unregister(&pci_dev->intr_handle,
1151                                      eth_igbvf_interrupt_handler,
1152                                      (void *)eth_dev);
1153
1154         return 0;
1155 }
1156
1157 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1158         struct rte_pci_device *pci_dev)
1159 {
1160         return rte_eth_dev_pci_generic_probe(pci_dev,
1161                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1162 }
1163
1164 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1165 {
1166         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1167 }
1168
1169 static struct rte_pci_driver rte_igb_pmd = {
1170         .id_table = pci_id_igb_map,
1171         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1172         .probe = eth_igb_pci_probe,
1173         .remove = eth_igb_pci_remove,
1174 };
1175
1176
1177 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1178         struct rte_pci_device *pci_dev)
1179 {
1180         return rte_eth_dev_pci_generic_probe(pci_dev,
1181                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1182 }
1183
1184 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1185 {
1186         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1187 }
1188
1189 /*
1190  * virtual function driver struct
1191  */
1192 static struct rte_pci_driver rte_igbvf_pmd = {
1193         .id_table = pci_id_igbvf_map,
1194         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1195         .probe = eth_igbvf_pci_probe,
1196         .remove = eth_igbvf_pci_remove,
1197 };
1198
1199 static void
1200 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1201 {
1202         struct e1000_hw *hw =
1203                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1205         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1206         rctl |= E1000_RCTL_VFE;
1207         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1208 }
1209
1210 static int
1211 igb_check_mq_mode(struct rte_eth_dev *dev)
1212 {
1213         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1214         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1215         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1216         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1217
1218         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1219             tx_mq_mode == ETH_MQ_TX_DCB ||
1220             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1221                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1222                 return -EINVAL;
1223         }
1224         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1225                 /* Check multi-queue mode.
1226                  * To no break software we accept ETH_MQ_RX_NONE as this might
1227                  * be used to turn off VLAN filter.
1228                  */
1229
1230                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1231                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1232                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1233                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1234                 } else {
1235                         /* Only support one queue on VFs.
1236                          * RSS together with SRIOV is not supported.
1237                          */
1238                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1239                                         " wrong mq_mode rx %d.",
1240                                         rx_mq_mode);
1241                         return -EINVAL;
1242                 }
1243                 /* TX mode is not used here, so mode might be ignored.*/
1244                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1245                         /* SRIOV only works in VMDq enable mode */
1246                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1247                                         " TX mode %d is not supported. "
1248                                         " Driver will behave as %d mode.",
1249                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1250                 }
1251
1252                 /* check valid queue number */
1253                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1254                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1255                                         " only support one queue on VFs.");
1256                         return -EINVAL;
1257                 }
1258         } else {
1259                 /* To no break software that set invalid mode, only display
1260                  * warning if invalid mode is used.
1261                  */
1262                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1263                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1264                     rx_mq_mode != ETH_MQ_RX_RSS) {
1265                         /* RSS together with VMDq not supported*/
1266                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1267                                      rx_mq_mode);
1268                         return -EINVAL;
1269                 }
1270
1271                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1272                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1273                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1274                                         " Due to txmode is meaningless in this"
1275                                         " driver, just ignore.",
1276                                         tx_mq_mode);
1277                 }
1278         }
1279         return 0;
1280 }
1281
1282 static int
1283 eth_igb_configure(struct rte_eth_dev *dev)
1284 {
1285         struct e1000_interrupt *intr =
1286                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1287         int ret;
1288
1289         PMD_INIT_FUNC_TRACE();
1290
1291         /* multipe queue mode checking */
1292         ret  = igb_check_mq_mode(dev);
1293         if (ret != 0) {
1294                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1295                             ret);
1296                 return ret;
1297         }
1298
1299         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1300         PMD_INIT_FUNC_TRACE();
1301
1302         return 0;
1303 }
1304
1305 static int
1306 eth_igb_start(struct rte_eth_dev *dev)
1307 {
1308         struct e1000_hw *hw =
1309                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310         struct e1000_adapter *adapter =
1311                 E1000_DEV_PRIVATE(dev->data->dev_private);
1312         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1313         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1314         int ret, mask;
1315         uint32_t intr_vector = 0;
1316         uint32_t ctrl_ext;
1317         uint32_t *speeds;
1318         int num_speeds;
1319         bool autoneg;
1320
1321         PMD_INIT_FUNC_TRACE();
1322
1323         /* disable uio/vfio intr/eventfd mapping */
1324         rte_intr_disable(intr_handle);
1325
1326         /* Power up the phy. Needed to make the link go Up */
1327         eth_igb_dev_set_link_up(dev);
1328
1329         /*
1330          * Packet Buffer Allocation (PBA)
1331          * Writing PBA sets the receive portion of the buffer
1332          * the remainder is used for the transmit buffer.
1333          */
1334         if (hw->mac.type == e1000_82575) {
1335                 uint32_t pba;
1336
1337                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1338                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1339         }
1340
1341         /* Put the address into the Receive Address Array */
1342         e1000_rar_set(hw, hw->mac.addr, 0);
1343
1344         /* Initialize the hardware */
1345         if (igb_hardware_init(hw)) {
1346                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1347                 return -EIO;
1348         }
1349         adapter->stopped = 0;
1350
1351         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1352
1353         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1354         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1355         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1356         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1357         E1000_WRITE_FLUSH(hw);
1358
1359         /* configure PF module if SRIOV enabled */
1360         igb_pf_host_configure(dev);
1361
1362         /* check and configure queue intr-vector mapping */
1363         if ((rte_intr_cap_multiple(intr_handle) ||
1364              !RTE_ETH_DEV_SRIOV(dev).active) &&
1365             dev->data->dev_conf.intr_conf.rxq != 0) {
1366                 intr_vector = dev->data->nb_rx_queues;
1367                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1368                         return -1;
1369         }
1370
1371         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1372                 intr_handle->intr_vec =
1373                         rte_zmalloc("intr_vec",
1374                                     dev->data->nb_rx_queues * sizeof(int), 0);
1375                 if (intr_handle->intr_vec == NULL) {
1376                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1377                                      " intr_vec", dev->data->nb_rx_queues);
1378                         return -ENOMEM;
1379                 }
1380         }
1381
1382         /* confiugre msix for rx interrupt */
1383         eth_igb_configure_msix_intr(dev);
1384
1385         /* Configure for OS presence */
1386         igb_init_manageability(hw);
1387
1388         eth_igb_tx_init(dev);
1389
1390         /* This can fail when allocating mbufs for descriptor rings */
1391         ret = eth_igb_rx_init(dev);
1392         if (ret) {
1393                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1394                 igb_dev_clear_queues(dev);
1395                 return ret;
1396         }
1397
1398         e1000_clear_hw_cntrs_base_generic(hw);
1399
1400         /*
1401          * VLAN Offload Settings
1402          */
1403         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1404                         ETH_VLAN_EXTEND_MASK;
1405         eth_igb_vlan_offload_set(dev, mask);
1406
1407         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1408                 /* Enable VLAN filter since VMDq always use VLAN filter */
1409                 igb_vmdq_vlan_hw_filter_enable(dev);
1410         }
1411
1412         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1413                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1414                 (hw->mac.type == e1000_i211)) {
1415                 /* Configure EITR with the maximum possible value (0xFFFF) */
1416                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1417         }
1418
1419         /* Setup link speed and duplex */
1420         speeds = &dev->data->dev_conf.link_speeds;
1421         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1422                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1423                 hw->mac.autoneg = 1;
1424         } else {
1425                 num_speeds = 0;
1426                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1427
1428                 /* Reset */
1429                 hw->phy.autoneg_advertised = 0;
1430
1431                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1432                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1433                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1434                         num_speeds = -1;
1435                         goto error_invalid_config;
1436                 }
1437                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1438                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1439                         num_speeds++;
1440                 }
1441                 if (*speeds & ETH_LINK_SPEED_10M) {
1442                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1443                         num_speeds++;
1444                 }
1445                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1446                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1447                         num_speeds++;
1448                 }
1449                 if (*speeds & ETH_LINK_SPEED_100M) {
1450                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1451                         num_speeds++;
1452                 }
1453                 if (*speeds & ETH_LINK_SPEED_1G) {
1454                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1455                         num_speeds++;
1456                 }
1457                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1458                         goto error_invalid_config;
1459
1460                 /* Set/reset the mac.autoneg based on the link speed,
1461                  * fixed or not
1462                  */
1463                 if (!autoneg) {
1464                         hw->mac.autoneg = 0;
1465                         hw->mac.forced_speed_duplex =
1466                                         hw->phy.autoneg_advertised;
1467                 } else {
1468                         hw->mac.autoneg = 1;
1469                 }
1470         }
1471
1472         e1000_setup_link(hw);
1473
1474         if (rte_intr_allow_others(intr_handle)) {
1475                 /* check if lsc interrupt is enabled */
1476                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1477                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1478                 else
1479                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1480         } else {
1481                 rte_intr_callback_unregister(intr_handle,
1482                                              eth_igb_interrupt_handler,
1483                                              (void *)dev);
1484                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1485                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1486                                      " no intr multiplex");
1487         }
1488
1489         /* check if rxq interrupt is enabled */
1490         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1491             rte_intr_dp_is_en(intr_handle))
1492                 eth_igb_rxq_interrupt_setup(dev);
1493
1494         /* enable uio/vfio intr/eventfd mapping */
1495         rte_intr_enable(intr_handle);
1496
1497         /* resume enabled intr since hw reset */
1498         igb_intr_enable(dev);
1499
1500         /* restore all types filter */
1501         igb_filter_restore(dev);
1502
1503         PMD_INIT_LOG(DEBUG, "<<");
1504
1505         return 0;
1506
1507 error_invalid_config:
1508         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1509                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1510         igb_dev_clear_queues(dev);
1511         return -EINVAL;
1512 }
1513
1514 /*********************************************************************
1515  *
1516  *  This routine disables all traffic on the adapter by issuing a
1517  *  global reset on the MAC.
1518  *
1519  **********************************************************************/
1520 static void
1521 eth_igb_stop(struct rte_eth_dev *dev)
1522 {
1523         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1525         struct rte_eth_link link;
1526         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1527
1528         igb_intr_disable(hw);
1529
1530         /* disable intr eventfd mapping */
1531         rte_intr_disable(intr_handle);
1532
1533         igb_pf_reset_hw(hw);
1534         E1000_WRITE_REG(hw, E1000_WUC, 0);
1535
1536         /* Set bit for Go Link disconnect */
1537         if (hw->mac.type >= e1000_82580) {
1538                 uint32_t phpm_reg;
1539
1540                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1541                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1542                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1543         }
1544
1545         /* Power down the phy. Needed to make the link go Down */
1546         eth_igb_dev_set_link_down(dev);
1547
1548         igb_dev_clear_queues(dev);
1549
1550         /* clear the recorded link status */
1551         memset(&link, 0, sizeof(link));
1552         rte_igb_dev_atomic_write_link_status(dev, &link);
1553
1554         if (!rte_intr_allow_others(intr_handle))
1555                 /* resume to the default handler */
1556                 rte_intr_callback_register(intr_handle,
1557                                            eth_igb_interrupt_handler,
1558                                            (void *)dev);
1559
1560         /* Clean datapath event and queue/vec mapping */
1561         rte_intr_efd_disable(intr_handle);
1562         if (intr_handle->intr_vec != NULL) {
1563                 rte_free(intr_handle->intr_vec);
1564                 intr_handle->intr_vec = NULL;
1565         }
1566 }
1567
1568 static int
1569 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1570 {
1571         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1572
1573         if (hw->phy.media_type == e1000_media_type_copper)
1574                 e1000_power_up_phy(hw);
1575         else
1576                 e1000_power_up_fiber_serdes_link(hw);
1577
1578         return 0;
1579 }
1580
1581 static int
1582 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1583 {
1584         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585
1586         if (hw->phy.media_type == e1000_media_type_copper)
1587                 e1000_power_down_phy(hw);
1588         else
1589                 e1000_shutdown_fiber_serdes_link(hw);
1590
1591         return 0;
1592 }
1593
1594 static void
1595 eth_igb_close(struct rte_eth_dev *dev)
1596 {
1597         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         struct e1000_adapter *adapter =
1599                 E1000_DEV_PRIVATE(dev->data->dev_private);
1600         struct rte_eth_link link;
1601         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1602         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1603
1604         eth_igb_stop(dev);
1605         adapter->stopped = 1;
1606
1607         e1000_phy_hw_reset(hw);
1608         igb_release_manageability(hw);
1609         igb_hw_control_release(hw);
1610
1611         /* Clear bit for Go Link disconnect */
1612         if (hw->mac.type >= e1000_82580) {
1613                 uint32_t phpm_reg;
1614
1615                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1616                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1617                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1618         }
1619
1620         igb_dev_free_queues(dev);
1621
1622         if (intr_handle->intr_vec) {
1623                 rte_free(intr_handle->intr_vec);
1624                 intr_handle->intr_vec = NULL;
1625         }
1626
1627         memset(&link, 0, sizeof(link));
1628         rte_igb_dev_atomic_write_link_status(dev, &link);
1629 }
1630
1631 static int
1632 igb_get_rx_buffer_size(struct e1000_hw *hw)
1633 {
1634         uint32_t rx_buf_size;
1635         if (hw->mac.type == e1000_82576) {
1636                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1637         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1638                 /* PBS needs to be translated according to a lookup table */
1639                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1640                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1641                 rx_buf_size = (rx_buf_size << 10);
1642         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1643                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1644         } else {
1645                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1646         }
1647
1648         return rx_buf_size;
1649 }
1650
1651 /*********************************************************************
1652  *
1653  *  Initialize the hardware
1654  *
1655  **********************************************************************/
1656 static int
1657 igb_hardware_init(struct e1000_hw *hw)
1658 {
1659         uint32_t rx_buf_size;
1660         int diag;
1661
1662         /* Let the firmware know the OS is in control */
1663         igb_hw_control_acquire(hw);
1664
1665         /*
1666          * These parameters control the automatic generation (Tx) and
1667          * response (Rx) to Ethernet PAUSE frames.
1668          * - High water mark should allow for at least two standard size (1518)
1669          *   frames to be received after sending an XOFF.
1670          * - Low water mark works best when it is very near the high water mark.
1671          *   This allows the receiver to restart by sending XON when it has
1672          *   drained a bit. Here we use an arbitrary value of 1500 which will
1673          *   restart after one full frame is pulled from the buffer. There
1674          *   could be several smaller frames in the buffer and if so they will
1675          *   not trigger the XON until their total number reduces the buffer
1676          *   by 1500.
1677          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1678          */
1679         rx_buf_size = igb_get_rx_buffer_size(hw);
1680
1681         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1682         hw->fc.low_water = hw->fc.high_water - 1500;
1683         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1684         hw->fc.send_xon = 1;
1685
1686         /* Set Flow control, use the tunable location if sane */
1687         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1688                 hw->fc.requested_mode = igb_fc_setting;
1689         else
1690                 hw->fc.requested_mode = e1000_fc_none;
1691
1692         /* Issue a global reset */
1693         igb_pf_reset_hw(hw);
1694         E1000_WRITE_REG(hw, E1000_WUC, 0);
1695
1696         diag = e1000_init_hw(hw);
1697         if (diag < 0)
1698                 return diag;
1699
1700         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1701         e1000_get_phy_info(hw);
1702         e1000_check_for_link(hw);
1703
1704         return 0;
1705 }
1706
1707 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1708 static void
1709 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1710 {
1711         int pause_frames;
1712
1713         uint64_t old_gprc  = stats->gprc;
1714         uint64_t old_gptc  = stats->gptc;
1715         uint64_t old_tpr   = stats->tpr;
1716         uint64_t old_tpt   = stats->tpt;
1717         uint64_t old_rpthc = stats->rpthc;
1718         uint64_t old_hgptc = stats->hgptc;
1719
1720         if(hw->phy.media_type == e1000_media_type_copper ||
1721             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1722                 stats->symerrs +=
1723                     E1000_READ_REG(hw,E1000_SYMERRS);
1724                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1725         }
1726
1727         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1728         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1729         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1730         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1731
1732         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1733         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1734         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1735         stats->dc += E1000_READ_REG(hw, E1000_DC);
1736         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1737         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1738         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1739         /*
1740         ** For watchdog management we need to know if we have been
1741         ** paused during the last interval, so capture that here.
1742         */
1743         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1744         stats->xoffrxc += pause_frames;
1745         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1746         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1747         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1748         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1749         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1750         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1751         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1752         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1753         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1754         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1755         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1756         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1757
1758         /* For the 64-bit byte counters the low dword must be read first. */
1759         /* Both registers clear on the read of the high dword */
1760
1761         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1762         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1763         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1764         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1765         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1766         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1767         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1768
1769         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1770         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1771         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1772         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1773         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1774
1775         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1776         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1777
1778         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1779         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1780         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1781         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1782         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1783         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1784
1785         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1786         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1787         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1788         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1789         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1790         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1791         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1792         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1793
1794         /* Interrupt Counts */
1795
1796         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1797         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1798         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1799         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1800         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1801         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1802         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1803         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1804         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1805
1806         /* Host to Card Statistics */
1807
1808         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1809         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1810         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1811         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1812         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1813         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1814         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1815         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1816         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1817         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1818         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1819         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1820         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1821         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1822         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1823         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1824
1825         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1826         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1827         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1828         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1829         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1830         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1831 }
1832
1833 static int
1834 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1835 {
1836         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837         struct e1000_hw_stats *stats =
1838                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1839
1840         igb_read_stats_registers(hw, stats);
1841
1842         if (rte_stats == NULL)
1843                 return -EINVAL;
1844
1845         /* Rx Errors */
1846         rte_stats->imissed = stats->mpc;
1847         rte_stats->ierrors = stats->crcerrs +
1848                              stats->rlec + stats->ruc + stats->roc +
1849                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1850
1851         /* Tx Errors */
1852         rte_stats->oerrors = stats->ecol + stats->latecol;
1853
1854         rte_stats->ipackets = stats->gprc;
1855         rte_stats->opackets = stats->gptc;
1856         rte_stats->ibytes   = stats->gorc;
1857         rte_stats->obytes   = stats->gotc;
1858         return 0;
1859 }
1860
1861 static void
1862 eth_igb_stats_reset(struct rte_eth_dev *dev)
1863 {
1864         struct e1000_hw_stats *hw_stats =
1865                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1866
1867         /* HW registers are cleared on read */
1868         eth_igb_stats_get(dev, NULL);
1869
1870         /* Reset software totals */
1871         memset(hw_stats, 0, sizeof(*hw_stats));
1872 }
1873
1874 static void
1875 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1876 {
1877         struct e1000_hw_stats *stats =
1878                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1879
1880         /* HW registers are cleared on read */
1881         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1882
1883         /* Reset software totals */
1884         memset(stats, 0, sizeof(*stats));
1885 }
1886
1887 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1888         struct rte_eth_xstat_name *xstats_names,
1889         __rte_unused unsigned int size)
1890 {
1891         unsigned i;
1892
1893         if (xstats_names == NULL)
1894                 return IGB_NB_XSTATS;
1895
1896         /* Note: limit checked in rte_eth_xstats_names() */
1897
1898         for (i = 0; i < IGB_NB_XSTATS; i++) {
1899                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1900                          "%s", rte_igb_stats_strings[i].name);
1901         }
1902
1903         return IGB_NB_XSTATS;
1904 }
1905
1906 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1907                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1908                 unsigned int limit)
1909 {
1910         unsigned int i;
1911
1912         if (!ids) {
1913                 if (xstats_names == NULL)
1914                         return IGB_NB_XSTATS;
1915
1916                 for (i = 0; i < IGB_NB_XSTATS; i++)
1917                         snprintf(xstats_names[i].name,
1918                                         sizeof(xstats_names[i].name),
1919                                         "%s", rte_igb_stats_strings[i].name);
1920
1921                 return IGB_NB_XSTATS;
1922
1923         } else {
1924                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1925
1926                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1927                                 IGB_NB_XSTATS);
1928
1929                 for (i = 0; i < limit; i++) {
1930                         if (ids[i] >= IGB_NB_XSTATS) {
1931                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1932                                 return -1;
1933                         }
1934                         strcpy(xstats_names[i].name,
1935                                         xstats_names_copy[ids[i]].name);
1936                 }
1937                 return limit;
1938         }
1939 }
1940
1941 static int
1942 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1943                    unsigned n)
1944 {
1945         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         struct e1000_hw_stats *hw_stats =
1947                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1948         unsigned i;
1949
1950         if (n < IGB_NB_XSTATS)
1951                 return IGB_NB_XSTATS;
1952
1953         igb_read_stats_registers(hw, hw_stats);
1954
1955         /* If this is a reset xstats is NULL, and we have cleared the
1956          * registers by reading them.
1957          */
1958         if (!xstats)
1959                 return 0;
1960
1961         /* Extended stats */
1962         for (i = 0; i < IGB_NB_XSTATS; i++) {
1963                 xstats[i].id = i;
1964                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1965                         rte_igb_stats_strings[i].offset);
1966         }
1967
1968         return IGB_NB_XSTATS;
1969 }
1970
1971 static int
1972 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1973                 uint64_t *values, unsigned int n)
1974 {
1975         unsigned int i;
1976
1977         if (!ids) {
1978                 struct e1000_hw *hw =
1979                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1980                 struct e1000_hw_stats *hw_stats =
1981                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1982
1983                 if (n < IGB_NB_XSTATS)
1984                         return IGB_NB_XSTATS;
1985
1986                 igb_read_stats_registers(hw, hw_stats);
1987
1988                 /* If this is a reset xstats is NULL, and we have cleared the
1989                  * registers by reading them.
1990                  */
1991                 if (!values)
1992                         return 0;
1993
1994                 /* Extended stats */
1995                 for (i = 0; i < IGB_NB_XSTATS; i++)
1996                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1997                                         rte_igb_stats_strings[i].offset);
1998
1999                 return IGB_NB_XSTATS;
2000
2001         } else {
2002                 uint64_t values_copy[IGB_NB_XSTATS];
2003
2004                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2005                                 IGB_NB_XSTATS);
2006
2007                 for (i = 0; i < n; i++) {
2008                         if (ids[i] >= IGB_NB_XSTATS) {
2009                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2010                                 return -1;
2011                         }
2012                         values[i] = values_copy[ids[i]];
2013                 }
2014                 return n;
2015         }
2016 }
2017
2018 static void
2019 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2020 {
2021         /* Good Rx packets, include VF loopback */
2022         UPDATE_VF_STAT(E1000_VFGPRC,
2023             hw_stats->last_gprc, hw_stats->gprc);
2024
2025         /* Good Rx octets, include VF loopback */
2026         UPDATE_VF_STAT(E1000_VFGORC,
2027             hw_stats->last_gorc, hw_stats->gorc);
2028
2029         /* Good Tx packets, include VF loopback */
2030         UPDATE_VF_STAT(E1000_VFGPTC,
2031             hw_stats->last_gptc, hw_stats->gptc);
2032
2033         /* Good Tx octets, include VF loopback */
2034         UPDATE_VF_STAT(E1000_VFGOTC,
2035             hw_stats->last_gotc, hw_stats->gotc);
2036
2037         /* Rx Multicst packets */
2038         UPDATE_VF_STAT(E1000_VFMPRC,
2039             hw_stats->last_mprc, hw_stats->mprc);
2040
2041         /* Good Rx loopback packets */
2042         UPDATE_VF_STAT(E1000_VFGPRLBC,
2043             hw_stats->last_gprlbc, hw_stats->gprlbc);
2044
2045         /* Good Rx loopback octets */
2046         UPDATE_VF_STAT(E1000_VFGORLBC,
2047             hw_stats->last_gorlbc, hw_stats->gorlbc);
2048
2049         /* Good Tx loopback packets */
2050         UPDATE_VF_STAT(E1000_VFGPTLBC,
2051             hw_stats->last_gptlbc, hw_stats->gptlbc);
2052
2053         /* Good Tx loopback octets */
2054         UPDATE_VF_STAT(E1000_VFGOTLBC,
2055             hw_stats->last_gotlbc, hw_stats->gotlbc);
2056 }
2057
2058 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2059                                      struct rte_eth_xstat_name *xstats_names,
2060                                      __rte_unused unsigned limit)
2061 {
2062         unsigned i;
2063
2064         if (xstats_names != NULL)
2065                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2066                         snprintf(xstats_names[i].name,
2067                                 sizeof(xstats_names[i].name), "%s",
2068                                 rte_igbvf_stats_strings[i].name);
2069                 }
2070         return IGBVF_NB_XSTATS;
2071 }
2072
2073 static int
2074 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2075                      unsigned n)
2076 {
2077         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2079                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2080         unsigned i;
2081
2082         if (n < IGBVF_NB_XSTATS)
2083                 return IGBVF_NB_XSTATS;
2084
2085         igbvf_read_stats_registers(hw, hw_stats);
2086
2087         if (!xstats)
2088                 return 0;
2089
2090         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2091                 xstats[i].id = i;
2092                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2093                         rte_igbvf_stats_strings[i].offset);
2094         }
2095
2096         return IGBVF_NB_XSTATS;
2097 }
2098
2099 static int
2100 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2101 {
2102         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2104                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2105
2106         igbvf_read_stats_registers(hw, hw_stats);
2107
2108         if (rte_stats == NULL)
2109                 return -EINVAL;
2110
2111         rte_stats->ipackets = hw_stats->gprc;
2112         rte_stats->ibytes = hw_stats->gorc;
2113         rte_stats->opackets = hw_stats->gptc;
2114         rte_stats->obytes = hw_stats->gotc;
2115         return 0;
2116 }
2117
2118 static void
2119 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2120 {
2121         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2122                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2123
2124         /* Sync HW register to the last stats */
2125         eth_igbvf_stats_get(dev, NULL);
2126
2127         /* reset HW current stats*/
2128         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2129                offsetof(struct e1000_vf_stats, gprc));
2130 }
2131
2132 static int
2133 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2134                        size_t fw_size)
2135 {
2136         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2137         struct e1000_fw_version fw;
2138         int ret;
2139
2140         e1000_get_fw_version(hw, &fw);
2141
2142         switch (hw->mac.type) {
2143         case e1000_i210:
2144         case e1000_i211:
2145                 if (!(e1000_get_flash_presence_i210(hw))) {
2146                         ret = snprintf(fw_version, fw_size,
2147                                  "%2d.%2d-%d",
2148                                  fw.invm_major, fw.invm_minor,
2149                                  fw.invm_img_type);
2150                         break;
2151                 }
2152                 /* fall through */
2153         default:
2154                 /* if option rom is valid, display its version too */
2155                 if (fw.or_valid) {
2156                         ret = snprintf(fw_version, fw_size,
2157                                  "%d.%d, 0x%08x, %d.%d.%d",
2158                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2159                                  fw.or_major, fw.or_build, fw.or_patch);
2160                 /* no option rom */
2161                 } else {
2162                         if (fw.etrack_id != 0X0000) {
2163                                 ret = snprintf(fw_version, fw_size,
2164                                          "%d.%d, 0x%08x",
2165                                          fw.eep_major, fw.eep_minor,
2166                                          fw.etrack_id);
2167                         } else {
2168                                 ret = snprintf(fw_version, fw_size,
2169                                          "%d.%d.%d",
2170                                          fw.eep_major, fw.eep_minor,
2171                                          fw.eep_build);
2172                         }
2173                 }
2174                 break;
2175         }
2176
2177         ret += 1; /* add the size of '\0' */
2178         if (fw_size < (u32)ret)
2179                 return ret;
2180         else
2181                 return 0;
2182 }
2183
2184 static void
2185 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2186 {
2187         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188
2189         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2190         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2191         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2192         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2193         dev_info->rx_offload_capa =
2194                 DEV_RX_OFFLOAD_VLAN_STRIP |
2195                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2196                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2197                 DEV_RX_OFFLOAD_TCP_CKSUM;
2198         dev_info->tx_offload_capa =
2199                 DEV_TX_OFFLOAD_VLAN_INSERT |
2200                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2201                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2202                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2203                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2204                 DEV_TX_OFFLOAD_TCP_TSO;
2205
2206         switch (hw->mac.type) {
2207         case e1000_82575:
2208                 dev_info->max_rx_queues = 4;
2209                 dev_info->max_tx_queues = 4;
2210                 dev_info->max_vmdq_pools = 0;
2211                 break;
2212
2213         case e1000_82576:
2214                 dev_info->max_rx_queues = 16;
2215                 dev_info->max_tx_queues = 16;
2216                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2217                 dev_info->vmdq_queue_num = 16;
2218                 break;
2219
2220         case e1000_82580:
2221                 dev_info->max_rx_queues = 8;
2222                 dev_info->max_tx_queues = 8;
2223                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2224                 dev_info->vmdq_queue_num = 8;
2225                 break;
2226
2227         case e1000_i350:
2228                 dev_info->max_rx_queues = 8;
2229                 dev_info->max_tx_queues = 8;
2230                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2231                 dev_info->vmdq_queue_num = 8;
2232                 break;
2233
2234         case e1000_i354:
2235                 dev_info->max_rx_queues = 8;
2236                 dev_info->max_tx_queues = 8;
2237                 break;
2238
2239         case e1000_i210:
2240                 dev_info->max_rx_queues = 4;
2241                 dev_info->max_tx_queues = 4;
2242                 dev_info->max_vmdq_pools = 0;
2243                 break;
2244
2245         case e1000_i211:
2246                 dev_info->max_rx_queues = 2;
2247                 dev_info->max_tx_queues = 2;
2248                 dev_info->max_vmdq_pools = 0;
2249                 break;
2250
2251         default:
2252                 /* Should not happen */
2253                 break;
2254         }
2255         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2256         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2257         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2258
2259         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2260                 .rx_thresh = {
2261                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2262                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2263                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2264                 },
2265                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2266                 .rx_drop_en = 0,
2267         };
2268
2269         dev_info->default_txconf = (struct rte_eth_txconf) {
2270                 .tx_thresh = {
2271                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2272                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2273                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2274                 },
2275                 .txq_flags = 0,
2276         };
2277
2278         dev_info->rx_desc_lim = rx_desc_lim;
2279         dev_info->tx_desc_lim = tx_desc_lim;
2280
2281         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2282                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2283                         ETH_LINK_SPEED_1G;
2284 }
2285
2286 static const uint32_t *
2287 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2288 {
2289         static const uint32_t ptypes[] = {
2290                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2291                 RTE_PTYPE_L2_ETHER,
2292                 RTE_PTYPE_L3_IPV4,
2293                 RTE_PTYPE_L3_IPV4_EXT,
2294                 RTE_PTYPE_L3_IPV6,
2295                 RTE_PTYPE_L3_IPV6_EXT,
2296                 RTE_PTYPE_L4_TCP,
2297                 RTE_PTYPE_L4_UDP,
2298                 RTE_PTYPE_L4_SCTP,
2299                 RTE_PTYPE_TUNNEL_IP,
2300                 RTE_PTYPE_INNER_L3_IPV6,
2301                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2302                 RTE_PTYPE_INNER_L4_TCP,
2303                 RTE_PTYPE_INNER_L4_UDP,
2304                 RTE_PTYPE_UNKNOWN
2305         };
2306
2307         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2308             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2309                 return ptypes;
2310         return NULL;
2311 }
2312
2313 static void
2314 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2315 {
2316         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317
2318         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2319         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2320         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2321         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2322         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2323                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2324                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2325                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2326         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2327                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2328                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2329                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2330                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2331                                 DEV_TX_OFFLOAD_TCP_TSO;
2332         switch (hw->mac.type) {
2333         case e1000_vfadapt:
2334                 dev_info->max_rx_queues = 2;
2335                 dev_info->max_tx_queues = 2;
2336                 break;
2337         case e1000_vfadapt_i350:
2338                 dev_info->max_rx_queues = 1;
2339                 dev_info->max_tx_queues = 1;
2340                 break;
2341         default:
2342                 /* Should not happen */
2343                 break;
2344         }
2345
2346         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2347                 .rx_thresh = {
2348                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2349                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2350                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2351                 },
2352                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2353                 .rx_drop_en = 0,
2354         };
2355
2356         dev_info->default_txconf = (struct rte_eth_txconf) {
2357                 .tx_thresh = {
2358                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2359                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2360                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2361                 },
2362                 .txq_flags = 0,
2363         };
2364
2365         dev_info->rx_desc_lim = rx_desc_lim;
2366         dev_info->tx_desc_lim = tx_desc_lim;
2367 }
2368
2369 /* return 0 means link status changed, -1 means not changed */
2370 static int
2371 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2372 {
2373         struct e1000_hw *hw =
2374                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375         struct rte_eth_link link, old;
2376         int link_check, count;
2377
2378         link_check = 0;
2379         hw->mac.get_link_status = 1;
2380
2381         /* possible wait-to-complete in up to 9 seconds */
2382         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2383                 /* Read the real link status */
2384                 switch (hw->phy.media_type) {
2385                 case e1000_media_type_copper:
2386                         /* Do the work to read phy */
2387                         e1000_check_for_link(hw);
2388                         link_check = !hw->mac.get_link_status;
2389                         break;
2390
2391                 case e1000_media_type_fiber:
2392                         e1000_check_for_link(hw);
2393                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2394                                       E1000_STATUS_LU);
2395                         break;
2396
2397                 case e1000_media_type_internal_serdes:
2398                         e1000_check_for_link(hw);
2399                         link_check = hw->mac.serdes_has_link;
2400                         break;
2401
2402                 /* VF device is type_unknown */
2403                 case e1000_media_type_unknown:
2404                         eth_igbvf_link_update(hw);
2405                         link_check = !hw->mac.get_link_status;
2406                         break;
2407
2408                 default:
2409                         break;
2410                 }
2411                 if (link_check || wait_to_complete == 0)
2412                         break;
2413                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2414         }
2415         memset(&link, 0, sizeof(link));
2416         rte_igb_dev_atomic_read_link_status(dev, &link);
2417         old = link;
2418
2419         /* Now we check if a transition has happened */
2420         if (link_check) {
2421                 uint16_t duplex, speed;
2422                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2423                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2424                                 ETH_LINK_FULL_DUPLEX :
2425                                 ETH_LINK_HALF_DUPLEX;
2426                 link.link_speed = speed;
2427                 link.link_status = ETH_LINK_UP;
2428                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2429                                 ETH_LINK_SPEED_FIXED);
2430         } else if (!link_check) {
2431                 link.link_speed = 0;
2432                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2433                 link.link_status = ETH_LINK_DOWN;
2434                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2435         }
2436         rte_igb_dev_atomic_write_link_status(dev, &link);
2437
2438         /* not changed */
2439         if (old.link_status == link.link_status)
2440                 return -1;
2441
2442         /* changed */
2443         return 0;
2444 }
2445
2446 /*
2447  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2448  * For ASF and Pass Through versions of f/w this means
2449  * that the driver is loaded.
2450  */
2451 static void
2452 igb_hw_control_acquire(struct e1000_hw *hw)
2453 {
2454         uint32_t ctrl_ext;
2455
2456         /* Let firmware know the driver has taken over */
2457         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2458         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2459 }
2460
2461 /*
2462  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2463  * For ASF and Pass Through versions of f/w this means that the
2464  * driver is no longer loaded.
2465  */
2466 static void
2467 igb_hw_control_release(struct e1000_hw *hw)
2468 {
2469         uint32_t ctrl_ext;
2470
2471         /* Let firmware taken over control of h/w */
2472         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2473         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2474                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2475 }
2476
2477 /*
2478  * Bit of a misnomer, what this really means is
2479  * to enable OS management of the system... aka
2480  * to disable special hardware management features.
2481  */
2482 static void
2483 igb_init_manageability(struct e1000_hw *hw)
2484 {
2485         if (e1000_enable_mng_pass_thru(hw)) {
2486                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2487                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2488
2489                 /* disable hardware interception of ARP */
2490                 manc &= ~(E1000_MANC_ARP_EN);
2491
2492                 /* enable receiving management packets to the host */
2493                 manc |= E1000_MANC_EN_MNG2HOST;
2494                 manc2h |= 1 << 5;  /* Mng Port 623 */
2495                 manc2h |= 1 << 6;  /* Mng Port 664 */
2496                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2497                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2498         }
2499 }
2500
2501 static void
2502 igb_release_manageability(struct e1000_hw *hw)
2503 {
2504         if (e1000_enable_mng_pass_thru(hw)) {
2505                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2506
2507                 manc |= E1000_MANC_ARP_EN;
2508                 manc &= ~E1000_MANC_EN_MNG2HOST;
2509
2510                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2511         }
2512 }
2513
2514 static void
2515 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2516 {
2517         struct e1000_hw *hw =
2518                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519         uint32_t rctl;
2520
2521         rctl = E1000_READ_REG(hw, E1000_RCTL);
2522         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2523         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2524 }
2525
2526 static void
2527 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2528 {
2529         struct e1000_hw *hw =
2530                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531         uint32_t rctl;
2532
2533         rctl = E1000_READ_REG(hw, E1000_RCTL);
2534         rctl &= (~E1000_RCTL_UPE);
2535         if (dev->data->all_multicast == 1)
2536                 rctl |= E1000_RCTL_MPE;
2537         else
2538                 rctl &= (~E1000_RCTL_MPE);
2539         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2540 }
2541
2542 static void
2543 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2544 {
2545         struct e1000_hw *hw =
2546                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547         uint32_t rctl;
2548
2549         rctl = E1000_READ_REG(hw, E1000_RCTL);
2550         rctl |= E1000_RCTL_MPE;
2551         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2552 }
2553
2554 static void
2555 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2556 {
2557         struct e1000_hw *hw =
2558                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2559         uint32_t rctl;
2560
2561         if (dev->data->promiscuous == 1)
2562                 return; /* must remain in all_multicast mode */
2563         rctl = E1000_READ_REG(hw, E1000_RCTL);
2564         rctl &= (~E1000_RCTL_MPE);
2565         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2566 }
2567
2568 static int
2569 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2570 {
2571         struct e1000_hw *hw =
2572                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573         struct e1000_vfta * shadow_vfta =
2574                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2575         uint32_t vfta;
2576         uint32_t vid_idx;
2577         uint32_t vid_bit;
2578
2579         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2580                               E1000_VFTA_ENTRY_MASK);
2581         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2582         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2583         if (on)
2584                 vfta |= vid_bit;
2585         else
2586                 vfta &= ~vid_bit;
2587         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2588
2589         /* update local VFTA copy */
2590         shadow_vfta->vfta[vid_idx] = vfta;
2591
2592         return 0;
2593 }
2594
2595 static int
2596 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2597                       enum rte_vlan_type vlan_type,
2598                       uint16_t tpid)
2599 {
2600         struct e1000_hw *hw =
2601                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2602         uint32_t reg, qinq;
2603
2604         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2605         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2606
2607         /* only outer TPID of double VLAN can be configured*/
2608         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2609                 reg = E1000_READ_REG(hw, E1000_VET);
2610                 reg = (reg & (~E1000_VET_VET_EXT)) |
2611                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2612                 E1000_WRITE_REG(hw, E1000_VET, reg);
2613
2614                 return 0;
2615         }
2616
2617         /* all other TPID values are read-only*/
2618         PMD_DRV_LOG(ERR, "Not supported");
2619
2620         return -ENOTSUP;
2621 }
2622
2623 static void
2624 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2625 {
2626         struct e1000_hw *hw =
2627                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628         uint32_t reg;
2629
2630         /* Filter Table Disable */
2631         reg = E1000_READ_REG(hw, E1000_RCTL);
2632         reg &= ~E1000_RCTL_CFIEN;
2633         reg &= ~E1000_RCTL_VFE;
2634         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2635 }
2636
2637 static void
2638 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2639 {
2640         struct e1000_hw *hw =
2641                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642         struct e1000_vfta * shadow_vfta =
2643                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2644         uint32_t reg;
2645         int i;
2646
2647         /* Filter Table Enable, CFI not used for packet acceptance */
2648         reg = E1000_READ_REG(hw, E1000_RCTL);
2649         reg &= ~E1000_RCTL_CFIEN;
2650         reg |= E1000_RCTL_VFE;
2651         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2652
2653         /* restore VFTA table */
2654         for (i = 0; i < IGB_VFTA_SIZE; i++)
2655                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2656 }
2657
2658 static void
2659 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2660 {
2661         struct e1000_hw *hw =
2662                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2663         uint32_t reg;
2664
2665         /* VLAN Mode Disable */
2666         reg = E1000_READ_REG(hw, E1000_CTRL);
2667         reg &= ~E1000_CTRL_VME;
2668         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2669 }
2670
2671 static void
2672 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2673 {
2674         struct e1000_hw *hw =
2675                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2676         uint32_t reg;
2677
2678         /* VLAN Mode Enable */
2679         reg = E1000_READ_REG(hw, E1000_CTRL);
2680         reg |= E1000_CTRL_VME;
2681         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2682 }
2683
2684 static void
2685 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2686 {
2687         struct e1000_hw *hw =
2688                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689         uint32_t reg;
2690
2691         /* CTRL_EXT: Extended VLAN */
2692         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2693         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2694         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2695
2696         /* Update maximum packet length */
2697         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2698                 E1000_WRITE_REG(hw, E1000_RLPML,
2699                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2700                                                 VLAN_TAG_SIZE);
2701 }
2702
2703 static void
2704 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2705 {
2706         struct e1000_hw *hw =
2707                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708         uint32_t reg;
2709
2710         /* CTRL_EXT: Extended VLAN */
2711         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2712         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2713         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2714
2715         /* Update maximum packet length */
2716         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2717                 E1000_WRITE_REG(hw, E1000_RLPML,
2718                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2719                                                 2 * VLAN_TAG_SIZE);
2720 }
2721
2722 static void
2723 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2724 {
2725         if(mask & ETH_VLAN_STRIP_MASK){
2726                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2727                         igb_vlan_hw_strip_enable(dev);
2728                 else
2729                         igb_vlan_hw_strip_disable(dev);
2730         }
2731
2732         if(mask & ETH_VLAN_FILTER_MASK){
2733                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2734                         igb_vlan_hw_filter_enable(dev);
2735                 else
2736                         igb_vlan_hw_filter_disable(dev);
2737         }
2738
2739         if(mask & ETH_VLAN_EXTEND_MASK){
2740                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2741                         igb_vlan_hw_extend_enable(dev);
2742                 else
2743                         igb_vlan_hw_extend_disable(dev);
2744         }
2745 }
2746
2747
2748 /**
2749  * It enables the interrupt mask and then enable the interrupt.
2750  *
2751  * @param dev
2752  *  Pointer to struct rte_eth_dev.
2753  * @param on
2754  *  Enable or Disable
2755  *
2756  * @return
2757  *  - On success, zero.
2758  *  - On failure, a negative value.
2759  */
2760 static int
2761 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2762 {
2763         struct e1000_interrupt *intr =
2764                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2765
2766         if (on)
2767                 intr->mask |= E1000_ICR_LSC;
2768         else
2769                 intr->mask &= ~E1000_ICR_LSC;
2770
2771         return 0;
2772 }
2773
2774 /* It clears the interrupt causes and enables the interrupt.
2775  * It will be called once only during nic initialized.
2776  *
2777  * @param dev
2778  *  Pointer to struct rte_eth_dev.
2779  *
2780  * @return
2781  *  - On success, zero.
2782  *  - On failure, a negative value.
2783  */
2784 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2785 {
2786         uint32_t mask, regval;
2787         struct e1000_hw *hw =
2788                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789         struct rte_eth_dev_info dev_info;
2790
2791         memset(&dev_info, 0, sizeof(dev_info));
2792         eth_igb_infos_get(dev, &dev_info);
2793
2794         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2795         regval = E1000_READ_REG(hw, E1000_EIMS);
2796         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2797
2798         return 0;
2799 }
2800
2801 /*
2802  * It reads ICR and gets interrupt causes, check it and set a bit flag
2803  * to update link status.
2804  *
2805  * @param dev
2806  *  Pointer to struct rte_eth_dev.
2807  *
2808  * @return
2809  *  - On success, zero.
2810  *  - On failure, a negative value.
2811  */
2812 static int
2813 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2814 {
2815         uint32_t icr;
2816         struct e1000_hw *hw =
2817                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818         struct e1000_interrupt *intr =
2819                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2820
2821         igb_intr_disable(hw);
2822
2823         /* read-on-clear nic registers here */
2824         icr = E1000_READ_REG(hw, E1000_ICR);
2825
2826         intr->flags = 0;
2827         if (icr & E1000_ICR_LSC) {
2828                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2829         }
2830
2831         if (icr & E1000_ICR_VMMB)
2832                 intr->flags |= E1000_FLAG_MAILBOX;
2833
2834         return 0;
2835 }
2836
2837 /*
2838  * It executes link_update after knowing an interrupt is prsent.
2839  *
2840  * @param dev
2841  *  Pointer to struct rte_eth_dev.
2842  *
2843  * @return
2844  *  - On success, zero.
2845  *  - On failure, a negative value.
2846  */
2847 static int
2848 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2849                          struct rte_intr_handle *intr_handle)
2850 {
2851         struct e1000_hw *hw =
2852                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2853         struct e1000_interrupt *intr =
2854                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2855         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2856         uint32_t tctl, rctl;
2857         struct rte_eth_link link;
2858         int ret;
2859
2860         if (intr->flags & E1000_FLAG_MAILBOX) {
2861                 igb_pf_mbx_process(dev);
2862                 intr->flags &= ~E1000_FLAG_MAILBOX;
2863         }
2864
2865         igb_intr_enable(dev);
2866         rte_intr_enable(intr_handle);
2867
2868         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2869                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2870
2871                 /* set get_link_status to check register later */
2872                 hw->mac.get_link_status = 1;
2873                 ret = eth_igb_link_update(dev, 0);
2874
2875                 /* check if link has changed */
2876                 if (ret < 0)
2877                         return 0;
2878
2879                 memset(&link, 0, sizeof(link));
2880                 rte_igb_dev_atomic_read_link_status(dev, &link);
2881                 if (link.link_status) {
2882                         PMD_INIT_LOG(INFO,
2883                                      " Port %d: Link Up - speed %u Mbps - %s",
2884                                      dev->data->port_id,
2885                                      (unsigned)link.link_speed,
2886                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2887                                      "full-duplex" : "half-duplex");
2888                 } else {
2889                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2890                                      dev->data->port_id);
2891                 }
2892
2893                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2894                              pci_dev->addr.domain,
2895                              pci_dev->addr.bus,
2896                              pci_dev->addr.devid,
2897                              pci_dev->addr.function);
2898                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2899                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2900                 if (link.link_status) {
2901                         /* enable Tx/Rx */
2902                         tctl |= E1000_TCTL_EN;
2903                         rctl |= E1000_RCTL_EN;
2904                 } else {
2905                         /* disable Tx/Rx */
2906                         tctl &= ~E1000_TCTL_EN;
2907                         rctl &= ~E1000_RCTL_EN;
2908                 }
2909                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2910                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2911                 E1000_WRITE_FLUSH(hw);
2912                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2913                                               NULL, NULL);
2914         }
2915
2916         return 0;
2917 }
2918
2919 /**
2920  * Interrupt handler which shall be registered at first.
2921  *
2922  * @param handle
2923  *  Pointer to interrupt handle.
2924  * @param param
2925  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2926  *
2927  * @return
2928  *  void
2929  */
2930 static void
2931 eth_igb_interrupt_handler(void *param)
2932 {
2933         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2934
2935         eth_igb_interrupt_get_status(dev);
2936         eth_igb_interrupt_action(dev, dev->intr_handle);
2937 }
2938
2939 static int
2940 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2941 {
2942         uint32_t eicr;
2943         struct e1000_hw *hw =
2944                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2945         struct e1000_interrupt *intr =
2946                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2947
2948         igbvf_intr_disable(hw);
2949
2950         /* read-on-clear nic registers here */
2951         eicr = E1000_READ_REG(hw, E1000_EICR);
2952         intr->flags = 0;
2953
2954         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2955                 intr->flags |= E1000_FLAG_MAILBOX;
2956
2957         return 0;
2958 }
2959
2960 void igbvf_mbx_process(struct rte_eth_dev *dev)
2961 {
2962         struct e1000_hw *hw =
2963                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964         struct e1000_mbx_info *mbx = &hw->mbx;
2965         u32 in_msg = 0;
2966
2967         if (mbx->ops.read(hw, &in_msg, 1, 0))
2968                 return;
2969
2970         /* PF reset VF event */
2971         if (in_msg == E1000_PF_CONTROL_MSG)
2972                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2973                                               NULL, NULL);
2974 }
2975
2976 static int
2977 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2978 {
2979         struct e1000_interrupt *intr =
2980                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2981
2982         if (intr->flags & E1000_FLAG_MAILBOX) {
2983                 igbvf_mbx_process(dev);
2984                 intr->flags &= ~E1000_FLAG_MAILBOX;
2985         }
2986
2987         igbvf_intr_enable(dev);
2988         rte_intr_enable(intr_handle);
2989
2990         return 0;
2991 }
2992
2993 static void
2994 eth_igbvf_interrupt_handler(void *param)
2995 {
2996         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2997
2998         eth_igbvf_interrupt_get_status(dev);
2999         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3000 }
3001
3002 static int
3003 eth_igb_led_on(struct rte_eth_dev *dev)
3004 {
3005         struct e1000_hw *hw;
3006
3007         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3008         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3009 }
3010
3011 static int
3012 eth_igb_led_off(struct rte_eth_dev *dev)
3013 {
3014         struct e1000_hw *hw;
3015
3016         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3018 }
3019
3020 static int
3021 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3022 {
3023         struct e1000_hw *hw;
3024         uint32_t ctrl;
3025         int tx_pause;
3026         int rx_pause;
3027
3028         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3029         fc_conf->pause_time = hw->fc.pause_time;
3030         fc_conf->high_water = hw->fc.high_water;
3031         fc_conf->low_water = hw->fc.low_water;
3032         fc_conf->send_xon = hw->fc.send_xon;
3033         fc_conf->autoneg = hw->mac.autoneg;
3034
3035         /*
3036          * Return rx_pause and tx_pause status according to actual setting of
3037          * the TFCE and RFCE bits in the CTRL register.
3038          */
3039         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3040         if (ctrl & E1000_CTRL_TFCE)
3041                 tx_pause = 1;
3042         else
3043                 tx_pause = 0;
3044
3045         if (ctrl & E1000_CTRL_RFCE)
3046                 rx_pause = 1;
3047         else
3048                 rx_pause = 0;
3049
3050         if (rx_pause && tx_pause)
3051                 fc_conf->mode = RTE_FC_FULL;
3052         else if (rx_pause)
3053                 fc_conf->mode = RTE_FC_RX_PAUSE;
3054         else if (tx_pause)
3055                 fc_conf->mode = RTE_FC_TX_PAUSE;
3056         else
3057                 fc_conf->mode = RTE_FC_NONE;
3058
3059         return 0;
3060 }
3061
3062 static int
3063 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3064 {
3065         struct e1000_hw *hw;
3066         int err;
3067         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3068                 e1000_fc_none,
3069                 e1000_fc_rx_pause,
3070                 e1000_fc_tx_pause,
3071                 e1000_fc_full
3072         };
3073         uint32_t rx_buf_size;
3074         uint32_t max_high_water;
3075         uint32_t rctl;
3076
3077         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078         if (fc_conf->autoneg != hw->mac.autoneg)
3079                 return -ENOTSUP;
3080         rx_buf_size = igb_get_rx_buffer_size(hw);
3081         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3082
3083         /* At least reserve one Ethernet frame for watermark */
3084         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3085         if ((fc_conf->high_water > max_high_water) ||
3086             (fc_conf->high_water < fc_conf->low_water)) {
3087                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3088                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3089                 return -EINVAL;
3090         }
3091
3092         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3093         hw->fc.pause_time     = fc_conf->pause_time;
3094         hw->fc.high_water     = fc_conf->high_water;
3095         hw->fc.low_water      = fc_conf->low_water;
3096         hw->fc.send_xon       = fc_conf->send_xon;
3097
3098         err = e1000_setup_link_generic(hw);
3099         if (err == E1000_SUCCESS) {
3100
3101                 /* check if we want to forward MAC frames - driver doesn't have native
3102                  * capability to do that, so we'll write the registers ourselves */
3103
3104                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3105
3106                 /* set or clear MFLCN.PMCF bit depending on configuration */
3107                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3108                         rctl |= E1000_RCTL_PMCF;
3109                 else
3110                         rctl &= ~E1000_RCTL_PMCF;
3111
3112                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3113                 E1000_WRITE_FLUSH(hw);
3114
3115                 return 0;
3116         }
3117
3118         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3119         return -EIO;
3120 }
3121
3122 #define E1000_RAH_POOLSEL_SHIFT      (18)
3123 static int
3124 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3125                 uint32_t index, uint32_t pool)
3126 {
3127         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3128         uint32_t rah;
3129
3130         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3131         rah = E1000_READ_REG(hw, E1000_RAH(index));
3132         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3133         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3134         return 0;
3135 }
3136
3137 static void
3138 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3139 {
3140         uint8_t addr[ETHER_ADDR_LEN];
3141         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142
3143         memset(addr, 0, sizeof(addr));
3144
3145         e1000_rar_set(hw, addr, index);
3146 }
3147
3148 static void
3149 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3150                                 struct ether_addr *addr)
3151 {
3152         eth_igb_rar_clear(dev, 0);
3153
3154         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3155 }
3156 /*
3157  * Virtual Function operations
3158  */
3159 static void
3160 igbvf_intr_disable(struct e1000_hw *hw)
3161 {
3162         PMD_INIT_FUNC_TRACE();
3163
3164         /* Clear interrupt mask to stop from interrupts being generated */
3165         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3166
3167         E1000_WRITE_FLUSH(hw);
3168 }
3169
3170 static void
3171 igbvf_stop_adapter(struct rte_eth_dev *dev)
3172 {
3173         u32 reg_val;
3174         u16 i;
3175         struct rte_eth_dev_info dev_info;
3176         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3177
3178         memset(&dev_info, 0, sizeof(dev_info));
3179         eth_igbvf_infos_get(dev, &dev_info);
3180
3181         /* Clear interrupt mask to stop from interrupts being generated */
3182         igbvf_intr_disable(hw);
3183
3184         /* Clear any pending interrupts, flush previous writes */
3185         E1000_READ_REG(hw, E1000_EICR);
3186
3187         /* Disable the transmit unit.  Each queue must be disabled. */
3188         for (i = 0; i < dev_info.max_tx_queues; i++)
3189                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3190
3191         /* Disable the receive unit by stopping each queue */
3192         for (i = 0; i < dev_info.max_rx_queues; i++) {
3193                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3194                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3195                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3196                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3197                         ;
3198         }
3199
3200         /* flush all queues disables */
3201         E1000_WRITE_FLUSH(hw);
3202         msec_delay(2);
3203 }
3204
3205 static int eth_igbvf_link_update(struct e1000_hw *hw)
3206 {
3207         struct e1000_mbx_info *mbx = &hw->mbx;
3208         struct e1000_mac_info *mac = &hw->mac;
3209         int ret_val = E1000_SUCCESS;
3210
3211         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3212
3213         /*
3214          * We only want to run this if there has been a rst asserted.
3215          * in this case that could mean a link change, device reset,
3216          * or a virtual function reset
3217          */
3218
3219         /* If we were hit with a reset or timeout drop the link */
3220         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3221                 mac->get_link_status = TRUE;
3222
3223         if (!mac->get_link_status)
3224                 goto out;
3225
3226         /* if link status is down no point in checking to see if pf is up */
3227         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3228                 goto out;
3229
3230         /* if we passed all the tests above then the link is up and we no
3231          * longer need to check for link */
3232         mac->get_link_status = FALSE;
3233
3234 out:
3235         return ret_val;
3236 }
3237
3238
3239 static int
3240 igbvf_dev_configure(struct rte_eth_dev *dev)
3241 {
3242         struct rte_eth_conf* conf = &dev->data->dev_conf;
3243
3244         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3245                      dev->data->port_id);
3246
3247         /*
3248          * VF has no ability to enable/disable HW CRC
3249          * Keep the persistent behavior the same as Host PF
3250          */
3251 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3252         if (!conf->rxmode.hw_strip_crc) {
3253                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3254                 conf->rxmode.hw_strip_crc = 1;
3255         }
3256 #else
3257         if (conf->rxmode.hw_strip_crc) {
3258                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3259                 conf->rxmode.hw_strip_crc = 0;
3260         }
3261 #endif
3262
3263         return 0;
3264 }
3265
3266 static int
3267 igbvf_dev_start(struct rte_eth_dev *dev)
3268 {
3269         struct e1000_hw *hw =
3270                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3271         struct e1000_adapter *adapter =
3272                 E1000_DEV_PRIVATE(dev->data->dev_private);
3273         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3274         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3275         int ret;
3276         uint32_t intr_vector = 0;
3277
3278         PMD_INIT_FUNC_TRACE();
3279
3280         hw->mac.ops.reset_hw(hw);
3281         adapter->stopped = 0;
3282
3283         /* Set all vfta */
3284         igbvf_set_vfta_all(dev,1);
3285
3286         eth_igbvf_tx_init(dev);
3287
3288         /* This can fail when allocating mbufs for descriptor rings */
3289         ret = eth_igbvf_rx_init(dev);
3290         if (ret) {
3291                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3292                 igb_dev_clear_queues(dev);
3293                 return ret;
3294         }
3295
3296         /* check and configure queue intr-vector mapping */
3297         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3298                 intr_vector = dev->data->nb_rx_queues;
3299                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3300                 if (ret)
3301                         return ret;
3302         }
3303
3304         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3305                 intr_handle->intr_vec =
3306                         rte_zmalloc("intr_vec",
3307                                     dev->data->nb_rx_queues * sizeof(int), 0);
3308                 if (!intr_handle->intr_vec) {
3309                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3310                                      " intr_vec", dev->data->nb_rx_queues);
3311                         return -ENOMEM;
3312                 }
3313         }
3314
3315         eth_igbvf_configure_msix_intr(dev);
3316
3317         /* enable uio/vfio intr/eventfd mapping */
3318         rte_intr_enable(intr_handle);
3319
3320         /* resume enabled intr since hw reset */
3321         igbvf_intr_enable(dev);
3322
3323         return 0;
3324 }
3325
3326 static void
3327 igbvf_dev_stop(struct rte_eth_dev *dev)
3328 {
3329         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3330         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3331
3332         PMD_INIT_FUNC_TRACE();
3333
3334         igbvf_stop_adapter(dev);
3335
3336         /*
3337           * Clear what we set, but we still keep shadow_vfta to
3338           * restore after device starts
3339           */
3340         igbvf_set_vfta_all(dev,0);
3341
3342         igb_dev_clear_queues(dev);
3343
3344         /* disable intr eventfd mapping */
3345         rte_intr_disable(intr_handle);
3346
3347         /* Clean datapath event and queue/vec mapping */
3348         rte_intr_efd_disable(intr_handle);
3349         if (intr_handle->intr_vec) {
3350                 rte_free(intr_handle->intr_vec);
3351                 intr_handle->intr_vec = NULL;
3352         }
3353 }
3354
3355 static void
3356 igbvf_dev_close(struct rte_eth_dev *dev)
3357 {
3358         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3359         struct e1000_adapter *adapter =
3360                 E1000_DEV_PRIVATE(dev->data->dev_private);
3361         struct ether_addr addr;
3362
3363         PMD_INIT_FUNC_TRACE();
3364
3365         e1000_reset_hw(hw);
3366
3367         igbvf_dev_stop(dev);
3368         adapter->stopped = 1;
3369         igb_dev_free_queues(dev);
3370
3371         /**
3372          * reprogram the RAR with a zero mac address,
3373          * to ensure that the VF traffic goes to the PF
3374          * after stop, close and detach of the VF.
3375          **/
3376
3377         memset(&addr, 0, sizeof(addr));
3378         igbvf_default_mac_addr_set(dev, &addr);
3379 }
3380
3381 static void
3382 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3383 {
3384         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3385
3386         /* Set both unicast and multicast promisc */
3387         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3388 }
3389
3390 static void
3391 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3392 {
3393         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3394
3395         /* If in allmulticast mode leave multicast promisc */
3396         if (dev->data->all_multicast == 1)
3397                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3398         else
3399                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3400 }
3401
3402 static void
3403 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3404 {
3405         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3406
3407         /* In promiscuous mode multicast promisc already set */
3408         if (dev->data->promiscuous == 0)
3409                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3410 }
3411
3412 static void
3413 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3414 {
3415         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3416
3417         /* In promiscuous mode leave multicast promisc enabled */
3418         if (dev->data->promiscuous == 0)
3419                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3420 }
3421
3422 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3423 {
3424         struct e1000_mbx_info *mbx = &hw->mbx;
3425         uint32_t msgbuf[2];
3426         s32 err;
3427
3428         /* After set vlan, vlan strip will also be enabled in igb driver*/
3429         msgbuf[0] = E1000_VF_SET_VLAN;
3430         msgbuf[1] = vid;
3431         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3432         if (on)
3433                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3434
3435         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3436         if (err)
3437                 goto mbx_err;
3438
3439         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3440         if (err)
3441                 goto mbx_err;
3442
3443         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3444         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3445                 err = -EINVAL;
3446
3447 mbx_err:
3448         return err;
3449 }
3450
3451 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3452 {
3453         struct e1000_hw *hw =
3454                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3455         struct e1000_vfta * shadow_vfta =
3456                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3457         int i = 0, j = 0, vfta = 0, mask = 1;
3458
3459         for (i = 0; i < IGB_VFTA_SIZE; i++){
3460                 vfta = shadow_vfta->vfta[i];
3461                 if(vfta){
3462                         mask = 1;
3463                         for (j = 0; j < 32; j++){
3464                                 if(vfta & mask)
3465                                         igbvf_set_vfta(hw,
3466                                                 (uint16_t)((i<<5)+j), on);
3467                                 mask<<=1;
3468                         }
3469                 }
3470         }
3471
3472 }
3473
3474 static int
3475 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3476 {
3477         struct e1000_hw *hw =
3478                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3479         struct e1000_vfta * shadow_vfta =
3480                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3481         uint32_t vid_idx = 0;
3482         uint32_t vid_bit = 0;
3483         int ret = 0;
3484
3485         PMD_INIT_FUNC_TRACE();
3486
3487         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3488         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3489         if(ret){
3490                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3491                 return ret;
3492         }
3493         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3494         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3495
3496         /*Save what we set and retore it after device reset*/
3497         if (on)
3498                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3499         else
3500                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3501
3502         return 0;
3503 }
3504
3505 static void
3506 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3507 {
3508         struct e1000_hw *hw =
3509                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510
3511         /* index is not used by rar_set() */
3512         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3513 }
3514
3515
3516 static int
3517 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3518                         struct rte_eth_rss_reta_entry64 *reta_conf,
3519                         uint16_t reta_size)
3520 {
3521         uint8_t i, j, mask;
3522         uint32_t reta, r;
3523         uint16_t idx, shift;
3524         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3525
3526         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3527                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3528                         "(%d) doesn't match the number hardware can supported "
3529                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3530                 return -EINVAL;
3531         }
3532
3533         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3534                 idx = i / RTE_RETA_GROUP_SIZE;
3535                 shift = i % RTE_RETA_GROUP_SIZE;
3536                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3537                                                 IGB_4_BIT_MASK);
3538                 if (!mask)
3539                         continue;
3540                 if (mask == IGB_4_BIT_MASK)
3541                         r = 0;
3542                 else
3543                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3544                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3545                         if (mask & (0x1 << j))
3546                                 reta |= reta_conf[idx].reta[shift + j] <<
3547                                                         (CHAR_BIT * j);
3548                         else
3549                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3550                 }
3551                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3552         }
3553
3554         return 0;
3555 }
3556
3557 static int
3558 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3559                        struct rte_eth_rss_reta_entry64 *reta_conf,
3560                        uint16_t reta_size)
3561 {
3562         uint8_t i, j, mask;
3563         uint32_t reta;
3564         uint16_t idx, shift;
3565         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3566
3567         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3568                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3569                         "(%d) doesn't match the number hardware can supported "
3570                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3571                 return -EINVAL;
3572         }
3573
3574         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3575                 idx = i / RTE_RETA_GROUP_SIZE;
3576                 shift = i % RTE_RETA_GROUP_SIZE;
3577                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3578                                                 IGB_4_BIT_MASK);
3579                 if (!mask)
3580                         continue;
3581                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3582                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3583                         if (mask & (0x1 << j))
3584                                 reta_conf[idx].reta[shift + j] =
3585                                         ((reta >> (CHAR_BIT * j)) &
3586                                                 IGB_8_BIT_MASK);
3587                 }
3588         }
3589
3590         return 0;
3591 }
3592
3593 int
3594 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3595                         struct rte_eth_syn_filter *filter,
3596                         bool add)
3597 {
3598         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599         struct e1000_filter_info *filter_info =
3600                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3601         uint32_t synqf, rfctl;
3602
3603         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3604                 return -EINVAL;
3605
3606         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3607
3608         if (add) {
3609                 if (synqf & E1000_SYN_FILTER_ENABLE)
3610                         return -EINVAL;
3611
3612                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3613                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3614
3615                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3616                 if (filter->hig_pri)
3617                         rfctl |= E1000_RFCTL_SYNQFP;
3618                 else
3619                         rfctl &= ~E1000_RFCTL_SYNQFP;
3620
3621                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3622         } else {
3623                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3624                         return -ENOENT;
3625                 synqf = 0;
3626         }
3627
3628         filter_info->syn_info = synqf;
3629         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3630         E1000_WRITE_FLUSH(hw);
3631         return 0;
3632 }
3633
3634 static int
3635 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3636                         struct rte_eth_syn_filter *filter)
3637 {
3638         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639         uint32_t synqf, rfctl;
3640
3641         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3642         if (synqf & E1000_SYN_FILTER_ENABLE) {
3643                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3644                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3645                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3646                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3647                 return 0;
3648         }
3649
3650         return -ENOENT;
3651 }
3652
3653 static int
3654 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3655                         enum rte_filter_op filter_op,
3656                         void *arg)
3657 {
3658         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3659         int ret;
3660
3661         MAC_TYPE_FILTER_SUP(hw->mac.type);
3662
3663         if (filter_op == RTE_ETH_FILTER_NOP)
3664                 return 0;
3665
3666         if (arg == NULL) {
3667                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3668                             filter_op);
3669                 return -EINVAL;
3670         }
3671
3672         switch (filter_op) {
3673         case RTE_ETH_FILTER_ADD:
3674                 ret = eth_igb_syn_filter_set(dev,
3675                                 (struct rte_eth_syn_filter *)arg,
3676                                 TRUE);
3677                 break;
3678         case RTE_ETH_FILTER_DELETE:
3679                 ret = eth_igb_syn_filter_set(dev,
3680                                 (struct rte_eth_syn_filter *)arg,
3681                                 FALSE);
3682                 break;
3683         case RTE_ETH_FILTER_GET:
3684                 ret = eth_igb_syn_filter_get(dev,
3685                                 (struct rte_eth_syn_filter *)arg);
3686                 break;
3687         default:
3688                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3689                 ret = -EINVAL;
3690                 break;
3691         }
3692
3693         return ret;
3694 }
3695
3696 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3697 static inline int
3698 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3699                         struct e1000_2tuple_filter_info *filter_info)
3700 {
3701         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3702                 return -EINVAL;
3703         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3704                 return -EINVAL;  /* filter index is out of range. */
3705         if (filter->tcp_flags > TCP_FLAG_ALL)
3706                 return -EINVAL;  /* flags is invalid. */
3707
3708         switch (filter->dst_port_mask) {
3709         case UINT16_MAX:
3710                 filter_info->dst_port_mask = 0;
3711                 filter_info->dst_port = filter->dst_port;
3712                 break;
3713         case 0:
3714                 filter_info->dst_port_mask = 1;
3715                 break;
3716         default:
3717                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3718                 return -EINVAL;
3719         }
3720
3721         switch (filter->proto_mask) {
3722         case UINT8_MAX:
3723                 filter_info->proto_mask = 0;
3724                 filter_info->proto = filter->proto;
3725                 break;
3726         case 0:
3727                 filter_info->proto_mask = 1;
3728                 break;
3729         default:
3730                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3731                 return -EINVAL;
3732         }
3733
3734         filter_info->priority = (uint8_t)filter->priority;
3735         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3736                 filter_info->tcp_flags = filter->tcp_flags;
3737         else
3738                 filter_info->tcp_flags = 0;
3739
3740         return 0;
3741 }
3742
3743 static inline struct e1000_2tuple_filter *
3744 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3745                         struct e1000_2tuple_filter_info *key)
3746 {
3747         struct e1000_2tuple_filter *it;
3748
3749         TAILQ_FOREACH(it, filter_list, entries) {
3750                 if (memcmp(key, &it->filter_info,
3751                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3752                         return it;
3753                 }
3754         }
3755         return NULL;
3756 }
3757
3758 /* inject a igb 2tuple filter to HW */
3759 static inline void
3760 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3761                            struct e1000_2tuple_filter *filter)
3762 {
3763         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3765         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3766         int i;
3767
3768         i = filter->index;
3769         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3770         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3771                 imir |= E1000_IMIR_PORT_BP;
3772         else
3773                 imir &= ~E1000_IMIR_PORT_BP;
3774
3775         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3776
3777         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3778         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3779         ttqf |= (uint32_t)(filter->filter_info.proto &
3780                                                 E1000_TTQF_PROTOCOL_MASK);
3781         if (filter->filter_info.proto_mask == 0)
3782                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3783
3784         /* tcp flags bits setting. */
3785         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3786                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3787                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3788                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3789                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3790                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3791                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3792                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3793                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3794                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3795                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3796                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3797                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3798         } else {
3799                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3800         }
3801         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3802         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3803         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3804 }
3805
3806 /*
3807  * igb_add_2tuple_filter - add a 2tuple filter
3808  *
3809  * @param
3810  * dev: Pointer to struct rte_eth_dev.
3811  * ntuple_filter: ponter to the filter that will be added.
3812  *
3813  * @return
3814  *    - On success, zero.
3815  *    - On failure, a negative value.
3816  */
3817 static int
3818 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3819                         struct rte_eth_ntuple_filter *ntuple_filter)
3820 {
3821         struct e1000_filter_info *filter_info =
3822                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3823         struct e1000_2tuple_filter *filter;
3824         int i, ret;
3825
3826         filter = rte_zmalloc("e1000_2tuple_filter",
3827                         sizeof(struct e1000_2tuple_filter), 0);
3828         if (filter == NULL)
3829                 return -ENOMEM;
3830
3831         ret = ntuple_filter_to_2tuple(ntuple_filter,
3832                                       &filter->filter_info);
3833         if (ret < 0) {
3834                 rte_free(filter);
3835                 return ret;
3836         }
3837         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3838                                          &filter->filter_info) != NULL) {
3839                 PMD_DRV_LOG(ERR, "filter exists.");
3840                 rte_free(filter);
3841                 return -EEXIST;
3842         }
3843         filter->queue = ntuple_filter->queue;
3844
3845         /*
3846          * look for an unused 2tuple filter index,
3847          * and insert the filter to list.
3848          */
3849         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3850                 if (!(filter_info->twotuple_mask & (1 << i))) {
3851                         filter_info->twotuple_mask |= 1 << i;
3852                         filter->index = i;
3853                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3854                                           filter,
3855                                           entries);
3856                         break;
3857                 }
3858         }
3859         if (i >= E1000_MAX_TTQF_FILTERS) {
3860                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3861                 rte_free(filter);
3862                 return -ENOSYS;
3863         }
3864
3865         igb_inject_2uple_filter(dev, filter);
3866         return 0;
3867 }
3868
3869 int
3870 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3871                         struct e1000_2tuple_filter *filter)
3872 {
3873         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3874         struct e1000_filter_info *filter_info =
3875                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3876
3877         filter_info->twotuple_mask &= ~(1 << filter->index);
3878         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3879         rte_free(filter);
3880
3881         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3882         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3883         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3884         return 0;
3885 }
3886
3887 /*
3888  * igb_remove_2tuple_filter - remove a 2tuple filter
3889  *
3890  * @param
3891  * dev: Pointer to struct rte_eth_dev.
3892  * ntuple_filter: ponter to the filter that will be removed.
3893  *
3894  * @return
3895  *    - On success, zero.
3896  *    - On failure, a negative value.
3897  */
3898 static int
3899 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3900                         struct rte_eth_ntuple_filter *ntuple_filter)
3901 {
3902         struct e1000_filter_info *filter_info =
3903                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3904         struct e1000_2tuple_filter_info filter_2tuple;
3905         struct e1000_2tuple_filter *filter;
3906         int ret;
3907
3908         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3909         ret = ntuple_filter_to_2tuple(ntuple_filter,
3910                                       &filter_2tuple);
3911         if (ret < 0)
3912                 return ret;
3913
3914         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3915                                          &filter_2tuple);
3916         if (filter == NULL) {
3917                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3918                 return -ENOENT;
3919         }
3920
3921         igb_delete_2tuple_filter(dev, filter);
3922
3923         return 0;
3924 }
3925
3926 /* inject a igb flex filter to HW */
3927 static inline void
3928 igb_inject_flex_filter(struct rte_eth_dev *dev,
3929                            struct e1000_flex_filter *filter)
3930 {
3931         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3932         uint32_t wufc, queueing;
3933         uint32_t reg_off;
3934         uint8_t i, j = 0;
3935
3936         wufc = E1000_READ_REG(hw, E1000_WUFC);
3937         if (filter->index < E1000_MAX_FHFT)
3938                 reg_off = E1000_FHFT(filter->index);
3939         else
3940                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3941
3942         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3943                         (E1000_WUFC_FLX0 << filter->index));
3944         queueing = filter->filter_info.len |
3945                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3946                 (filter->filter_info.priority <<
3947                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3948         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3949                         queueing);
3950
3951         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3952                 E1000_WRITE_REG(hw, reg_off,
3953                                 filter->filter_info.dwords[j]);
3954                 reg_off += sizeof(uint32_t);
3955                 E1000_WRITE_REG(hw, reg_off,
3956                                 filter->filter_info.dwords[++j]);
3957                 reg_off += sizeof(uint32_t);
3958                 E1000_WRITE_REG(hw, reg_off,
3959                         (uint32_t)filter->filter_info.mask[i]);
3960                 reg_off += sizeof(uint32_t) * 2;
3961                 ++j;
3962         }
3963 }
3964
3965 static inline struct e1000_flex_filter *
3966 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3967                         struct e1000_flex_filter_info *key)
3968 {
3969         struct e1000_flex_filter *it;
3970
3971         TAILQ_FOREACH(it, filter_list, entries) {
3972                 if (memcmp(key, &it->filter_info,
3973                         sizeof(struct e1000_flex_filter_info)) == 0)
3974                         return it;
3975         }
3976
3977         return NULL;
3978 }
3979
3980 /* remove a flex byte filter
3981  * @param
3982  * dev: Pointer to struct rte_eth_dev.
3983  * filter: the pointer of the filter will be removed.
3984  */
3985 void
3986 igb_remove_flex_filter(struct rte_eth_dev *dev,
3987                         struct e1000_flex_filter *filter)
3988 {
3989         struct e1000_filter_info *filter_info =
3990                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3991         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3992         uint32_t wufc, i;
3993         uint32_t reg_off;
3994
3995         wufc = E1000_READ_REG(hw, E1000_WUFC);
3996         if (filter->index < E1000_MAX_FHFT)
3997                 reg_off = E1000_FHFT(filter->index);
3998         else
3999                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4000
4001         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4002                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4003
4004         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4005                 (~(E1000_WUFC_FLX0 << filter->index)));
4006
4007         filter_info->flex_mask &= ~(1 << filter->index);
4008         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4009         rte_free(filter);
4010 }
4011
4012 int
4013 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4014                         struct rte_eth_flex_filter *filter,
4015                         bool add)
4016 {
4017         struct e1000_filter_info *filter_info =
4018                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4019         struct e1000_flex_filter *flex_filter, *it;
4020         uint32_t mask;
4021         uint8_t shift, i;
4022
4023         flex_filter = rte_zmalloc("e1000_flex_filter",
4024                         sizeof(struct e1000_flex_filter), 0);
4025         if (flex_filter == NULL)
4026                 return -ENOMEM;
4027
4028         flex_filter->filter_info.len = filter->len;
4029         flex_filter->filter_info.priority = filter->priority;
4030         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4031         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4032                 mask = 0;
4033                 /* reverse bits in flex filter's mask*/
4034                 for (shift = 0; shift < CHAR_BIT; shift++) {
4035                         if (filter->mask[i] & (0x01 << shift))
4036                                 mask |= (0x80 >> shift);
4037                 }
4038                 flex_filter->filter_info.mask[i] = mask;
4039         }
4040
4041         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4042                                 &flex_filter->filter_info);
4043         if (it == NULL && !add) {
4044                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4045                 rte_free(flex_filter);
4046                 return -ENOENT;
4047         }
4048         if (it != NULL && add) {
4049                 PMD_DRV_LOG(ERR, "filter exists.");
4050                 rte_free(flex_filter);
4051                 return -EEXIST;
4052         }
4053
4054         if (add) {
4055                 flex_filter->queue = filter->queue;
4056                 /*
4057                  * look for an unused flex filter index
4058                  * and insert the filter into the list.
4059                  */
4060                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4061                         if (!(filter_info->flex_mask & (1 << i))) {
4062                                 filter_info->flex_mask |= 1 << i;
4063                                 flex_filter->index = i;
4064                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4065                                         flex_filter,
4066                                         entries);
4067                                 break;
4068                         }
4069                 }
4070                 if (i >= E1000_MAX_FLEX_FILTERS) {
4071                         PMD_DRV_LOG(ERR, "flex filters are full.");
4072                         rte_free(flex_filter);
4073                         return -ENOSYS;
4074                 }
4075
4076                 igb_inject_flex_filter(dev, flex_filter);
4077
4078         } else {
4079                 igb_remove_flex_filter(dev, it);
4080                 rte_free(flex_filter);
4081         }
4082
4083         return 0;
4084 }
4085
4086 static int
4087 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4088                         struct rte_eth_flex_filter *filter)
4089 {
4090         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4091         struct e1000_filter_info *filter_info =
4092                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4093         struct e1000_flex_filter flex_filter, *it;
4094         uint32_t wufc, queueing, wufc_en = 0;
4095
4096         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4097         flex_filter.filter_info.len = filter->len;
4098         flex_filter.filter_info.priority = filter->priority;
4099         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4100         memcpy(flex_filter.filter_info.mask, filter->mask,
4101                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4102
4103         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4104                                 &flex_filter.filter_info);
4105         if (it == NULL) {
4106                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4107                 return -ENOENT;
4108         }
4109
4110         wufc = E1000_READ_REG(hw, E1000_WUFC);
4111         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4112
4113         if ((wufc & wufc_en) == wufc_en) {
4114                 uint32_t reg_off = 0;
4115                 if (it->index < E1000_MAX_FHFT)
4116                         reg_off = E1000_FHFT(it->index);
4117                 else
4118                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4119
4120                 queueing = E1000_READ_REG(hw,
4121                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4122                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4123                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4124                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4125                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4126                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4127                 return 0;
4128         }
4129         return -ENOENT;
4130 }
4131
4132 static int
4133 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4134                         enum rte_filter_op filter_op,
4135                         void *arg)
4136 {
4137         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4138         struct rte_eth_flex_filter *filter;
4139         int ret = 0;
4140
4141         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4142
4143         if (filter_op == RTE_ETH_FILTER_NOP)
4144                 return ret;
4145
4146         if (arg == NULL) {
4147                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4148                             filter_op);
4149                 return -EINVAL;
4150         }
4151
4152         filter = (struct rte_eth_flex_filter *)arg;
4153         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4154             || filter->len % sizeof(uint64_t) != 0) {
4155                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4156                 return -EINVAL;
4157         }
4158         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4159                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4160                 return -EINVAL;
4161         }
4162
4163         switch (filter_op) {
4164         case RTE_ETH_FILTER_ADD:
4165                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4166                 break;
4167         case RTE_ETH_FILTER_DELETE:
4168                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4169                 break;
4170         case RTE_ETH_FILTER_GET:
4171                 ret = eth_igb_get_flex_filter(dev, filter);
4172                 break;
4173         default:
4174                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4175                 ret = -EINVAL;
4176                 break;
4177         }
4178
4179         return ret;
4180 }
4181
4182 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4183 static inline int
4184 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4185                         struct e1000_5tuple_filter_info *filter_info)
4186 {
4187         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4188                 return -EINVAL;
4189         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4190                 return -EINVAL;  /* filter index is out of range. */
4191         if (filter->tcp_flags > TCP_FLAG_ALL)
4192                 return -EINVAL;  /* flags is invalid. */
4193
4194         switch (filter->dst_ip_mask) {
4195         case UINT32_MAX:
4196                 filter_info->dst_ip_mask = 0;
4197                 filter_info->dst_ip = filter->dst_ip;
4198                 break;
4199         case 0:
4200                 filter_info->dst_ip_mask = 1;
4201                 break;
4202         default:
4203                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4204                 return -EINVAL;
4205         }
4206
4207         switch (filter->src_ip_mask) {
4208         case UINT32_MAX:
4209                 filter_info->src_ip_mask = 0;
4210                 filter_info->src_ip = filter->src_ip;
4211                 break;
4212         case 0:
4213                 filter_info->src_ip_mask = 1;
4214                 break;
4215         default:
4216                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4217                 return -EINVAL;
4218         }
4219
4220         switch (filter->dst_port_mask) {
4221         case UINT16_MAX:
4222                 filter_info->dst_port_mask = 0;
4223                 filter_info->dst_port = filter->dst_port;
4224                 break;
4225         case 0:
4226                 filter_info->dst_port_mask = 1;
4227                 break;
4228         default:
4229                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4230                 return -EINVAL;
4231         }
4232
4233         switch (filter->src_port_mask) {
4234         case UINT16_MAX:
4235                 filter_info->src_port_mask = 0;
4236                 filter_info->src_port = filter->src_port;
4237                 break;
4238         case 0:
4239                 filter_info->src_port_mask = 1;
4240                 break;
4241         default:
4242                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4243                 return -EINVAL;
4244         }
4245
4246         switch (filter->proto_mask) {
4247         case UINT8_MAX:
4248                 filter_info->proto_mask = 0;
4249                 filter_info->proto = filter->proto;
4250                 break;
4251         case 0:
4252                 filter_info->proto_mask = 1;
4253                 break;
4254         default:
4255                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4256                 return -EINVAL;
4257         }
4258
4259         filter_info->priority = (uint8_t)filter->priority;
4260         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4261                 filter_info->tcp_flags = filter->tcp_flags;
4262         else
4263                 filter_info->tcp_flags = 0;
4264
4265         return 0;
4266 }
4267
4268 static inline struct e1000_5tuple_filter *
4269 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4270                         struct e1000_5tuple_filter_info *key)
4271 {
4272         struct e1000_5tuple_filter *it;
4273
4274         TAILQ_FOREACH(it, filter_list, entries) {
4275                 if (memcmp(key, &it->filter_info,
4276                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4277                         return it;
4278                 }
4279         }
4280         return NULL;
4281 }
4282
4283 /* inject a igb 5-tuple filter to HW */
4284 static inline void
4285 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4286                            struct e1000_5tuple_filter *filter)
4287 {
4288         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4289         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4290         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4291         uint8_t i;
4292
4293         i = filter->index;
4294         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4295         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4296                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4297         if (filter->filter_info.dst_ip_mask == 0)
4298                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4299         if (filter->filter_info.src_port_mask == 0)
4300                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4301         if (filter->filter_info.proto_mask == 0)
4302                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4303         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4304                 E1000_FTQF_QUEUE_MASK;
4305         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4306         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4307         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4308         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4309
4310         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4311         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4312
4313         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4314         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4315                 imir |= E1000_IMIR_PORT_BP;
4316         else
4317                 imir &= ~E1000_IMIR_PORT_BP;
4318         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4319
4320         /* tcp flags bits setting. */
4321         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4322                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4323                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4324                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4325                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4326                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4327                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4328                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4329                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4330                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4331                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4332                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4333                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4334         } else {
4335                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4336         }
4337         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4338         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4339 }
4340
4341 /*
4342  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4343  *
4344  * @param
4345  * dev: Pointer to struct rte_eth_dev.
4346  * ntuple_filter: ponter to the filter that will be added.
4347  *
4348  * @return
4349  *    - On success, zero.
4350  *    - On failure, a negative value.
4351  */
4352 static int
4353 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4354                         struct rte_eth_ntuple_filter *ntuple_filter)
4355 {
4356         struct e1000_filter_info *filter_info =
4357                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4358         struct e1000_5tuple_filter *filter;
4359         uint8_t i;
4360         int ret;
4361
4362         filter = rte_zmalloc("e1000_5tuple_filter",
4363                         sizeof(struct e1000_5tuple_filter), 0);
4364         if (filter == NULL)
4365                 return -ENOMEM;
4366
4367         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4368                                             &filter->filter_info);
4369         if (ret < 0) {
4370                 rte_free(filter);
4371                 return ret;
4372         }
4373
4374         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4375                                          &filter->filter_info) != NULL) {
4376                 PMD_DRV_LOG(ERR, "filter exists.");
4377                 rte_free(filter);
4378                 return -EEXIST;
4379         }
4380         filter->queue = ntuple_filter->queue;
4381
4382         /*
4383          * look for an unused 5tuple filter index,
4384          * and insert the filter to list.
4385          */
4386         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4387                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4388                         filter_info->fivetuple_mask |= 1 << i;
4389                         filter->index = i;
4390                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4391                                           filter,
4392                                           entries);
4393                         break;
4394                 }
4395         }
4396         if (i >= E1000_MAX_FTQF_FILTERS) {
4397                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4398                 rte_free(filter);
4399                 return -ENOSYS;
4400         }
4401
4402         igb_inject_5tuple_filter_82576(dev, filter);
4403         return 0;
4404 }
4405
4406 int
4407 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4408                                 struct e1000_5tuple_filter *filter)
4409 {
4410         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4411         struct e1000_filter_info *filter_info =
4412                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4413
4414         filter_info->fivetuple_mask &= ~(1 << filter->index);
4415         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4416         rte_free(filter);
4417
4418         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4419                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4420         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4421         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4422         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4423         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4424         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4425         return 0;
4426 }
4427
4428 /*
4429  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4430  *
4431  * @param
4432  * dev: Pointer to struct rte_eth_dev.
4433  * ntuple_filter: ponter to the filter that will be removed.
4434  *
4435  * @return
4436  *    - On success, zero.
4437  *    - On failure, a negative value.
4438  */
4439 static int
4440 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4441                                 struct rte_eth_ntuple_filter *ntuple_filter)
4442 {
4443         struct e1000_filter_info *filter_info =
4444                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4445         struct e1000_5tuple_filter_info filter_5tuple;
4446         struct e1000_5tuple_filter *filter;
4447         int ret;
4448
4449         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4450         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4451                                             &filter_5tuple);
4452         if (ret < 0)
4453                 return ret;
4454
4455         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4456                                          &filter_5tuple);
4457         if (filter == NULL) {
4458                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4459                 return -ENOENT;
4460         }
4461
4462         igb_delete_5tuple_filter_82576(dev, filter);
4463
4464         return 0;
4465 }
4466
4467 static int
4468 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4469 {
4470         uint32_t rctl;
4471         struct e1000_hw *hw;
4472         struct rte_eth_dev_info dev_info;
4473         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4474                                      VLAN_TAG_SIZE);
4475
4476         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4477
4478 #ifdef RTE_LIBRTE_82571_SUPPORT
4479         /* XXX: not bigger than max_rx_pktlen */
4480         if (hw->mac.type == e1000_82571)
4481                 return -ENOTSUP;
4482 #endif
4483         eth_igb_infos_get(dev, &dev_info);
4484
4485         /* check that mtu is within the allowed range */
4486         if ((mtu < ETHER_MIN_MTU) ||
4487             (frame_size > dev_info.max_rx_pktlen))
4488                 return -EINVAL;
4489
4490         /* refuse mtu that requires the support of scattered packets when this
4491          * feature has not been enabled before. */
4492         if (!dev->data->scattered_rx &&
4493             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4494                 return -EINVAL;
4495
4496         rctl = E1000_READ_REG(hw, E1000_RCTL);
4497
4498         /* switch to jumbo mode if needed */
4499         if (frame_size > ETHER_MAX_LEN) {
4500                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4501                 rctl |= E1000_RCTL_LPE;
4502         } else {
4503                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4504                 rctl &= ~E1000_RCTL_LPE;
4505         }
4506         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4507
4508         /* update max frame size */
4509         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4510
4511         E1000_WRITE_REG(hw, E1000_RLPML,
4512                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4513
4514         return 0;
4515 }
4516
4517 /*
4518  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4519  *
4520  * @param
4521  * dev: Pointer to struct rte_eth_dev.
4522  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4523  * add: if true, add filter, if false, remove filter
4524  *
4525  * @return
4526  *    - On success, zero.
4527  *    - On failure, a negative value.
4528  */
4529 int
4530 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4531                         struct rte_eth_ntuple_filter *ntuple_filter,
4532                         bool add)
4533 {
4534         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4535         int ret;
4536
4537         switch (ntuple_filter->flags) {
4538         case RTE_5TUPLE_FLAGS:
4539         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4540                 if (hw->mac.type != e1000_82576)
4541                         return -ENOTSUP;
4542                 if (add)
4543                         ret = igb_add_5tuple_filter_82576(dev,
4544                                                           ntuple_filter);
4545                 else
4546                         ret = igb_remove_5tuple_filter_82576(dev,
4547                                                              ntuple_filter);
4548                 break;
4549         case RTE_2TUPLE_FLAGS:
4550         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4551                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4552                         hw->mac.type != e1000_i210 &&
4553                         hw->mac.type != e1000_i211)
4554                         return -ENOTSUP;
4555                 if (add)
4556                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4557                 else
4558                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4559                 break;
4560         default:
4561                 ret = -EINVAL;
4562                 break;
4563         }
4564
4565         return ret;
4566 }
4567
4568 /*
4569  * igb_get_ntuple_filter - get a ntuple filter
4570  *
4571  * @param
4572  * dev: Pointer to struct rte_eth_dev.
4573  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4574  *
4575  * @return
4576  *    - On success, zero.
4577  *    - On failure, a negative value.
4578  */
4579 static int
4580 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4581                         struct rte_eth_ntuple_filter *ntuple_filter)
4582 {
4583         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4584         struct e1000_filter_info *filter_info =
4585                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4586         struct e1000_5tuple_filter_info filter_5tuple;
4587         struct e1000_2tuple_filter_info filter_2tuple;
4588         struct e1000_5tuple_filter *p_5tuple_filter;
4589         struct e1000_2tuple_filter *p_2tuple_filter;
4590         int ret;
4591
4592         switch (ntuple_filter->flags) {
4593         case RTE_5TUPLE_FLAGS:
4594         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4595                 if (hw->mac.type != e1000_82576)
4596                         return -ENOTSUP;
4597                 memset(&filter_5tuple,
4598                         0,
4599                         sizeof(struct e1000_5tuple_filter_info));
4600                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4601                                                     &filter_5tuple);
4602                 if (ret < 0)
4603                         return ret;
4604                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4605                                         &filter_info->fivetuple_list,
4606                                         &filter_5tuple);
4607                 if (p_5tuple_filter == NULL) {
4608                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4609                         return -ENOENT;
4610                 }
4611                 ntuple_filter->queue = p_5tuple_filter->queue;
4612                 break;
4613         case RTE_2TUPLE_FLAGS:
4614         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4615                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4616                         return -ENOTSUP;
4617                 memset(&filter_2tuple,
4618                         0,
4619                         sizeof(struct e1000_2tuple_filter_info));
4620                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4621                 if (ret < 0)
4622                         return ret;
4623                 p_2tuple_filter = igb_2tuple_filter_lookup(
4624                                         &filter_info->twotuple_list,
4625                                         &filter_2tuple);
4626                 if (p_2tuple_filter == NULL) {
4627                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4628                         return -ENOENT;
4629                 }
4630                 ntuple_filter->queue = p_2tuple_filter->queue;
4631                 break;
4632         default:
4633                 ret = -EINVAL;
4634                 break;
4635         }
4636
4637         return 0;
4638 }
4639
4640 /*
4641  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4642  * @dev: pointer to rte_eth_dev structure
4643  * @filter_op:operation will be taken.
4644  * @arg: a pointer to specific structure corresponding to the filter_op
4645  */
4646 static int
4647 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4648                                 enum rte_filter_op filter_op,
4649                                 void *arg)
4650 {
4651         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4652         int ret;
4653
4654         MAC_TYPE_FILTER_SUP(hw->mac.type);
4655
4656         if (filter_op == RTE_ETH_FILTER_NOP)
4657                 return 0;
4658
4659         if (arg == NULL) {
4660                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4661                             filter_op);
4662                 return -EINVAL;
4663         }
4664
4665         switch (filter_op) {
4666         case RTE_ETH_FILTER_ADD:
4667                 ret = igb_add_del_ntuple_filter(dev,
4668                         (struct rte_eth_ntuple_filter *)arg,
4669                         TRUE);
4670                 break;
4671         case RTE_ETH_FILTER_DELETE:
4672                 ret = igb_add_del_ntuple_filter(dev,
4673                         (struct rte_eth_ntuple_filter *)arg,
4674                         FALSE);
4675                 break;
4676         case RTE_ETH_FILTER_GET:
4677                 ret = igb_get_ntuple_filter(dev,
4678                         (struct rte_eth_ntuple_filter *)arg);
4679                 break;
4680         default:
4681                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4682                 ret = -EINVAL;
4683                 break;
4684         }
4685         return ret;
4686 }
4687
4688 static inline int
4689 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4690                         uint16_t ethertype)
4691 {
4692         int i;
4693
4694         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4695                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4696                     (filter_info->ethertype_mask & (1 << i)))
4697                         return i;
4698         }
4699         return -1;
4700 }
4701
4702 static inline int
4703 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4704                         uint16_t ethertype, uint32_t etqf)
4705 {
4706         int i;
4707
4708         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4709                 if (!(filter_info->ethertype_mask & (1 << i))) {
4710                         filter_info->ethertype_mask |= 1 << i;
4711                         filter_info->ethertype_filters[i].ethertype = ethertype;
4712                         filter_info->ethertype_filters[i].etqf = etqf;
4713                         return i;
4714                 }
4715         }
4716         return -1;
4717 }
4718
4719 int
4720 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4721                         uint8_t idx)
4722 {
4723         if (idx >= E1000_MAX_ETQF_FILTERS)
4724                 return -1;
4725         filter_info->ethertype_mask &= ~(1 << idx);
4726         filter_info->ethertype_filters[idx].ethertype = 0;
4727         filter_info->ethertype_filters[idx].etqf = 0;
4728         return idx;
4729 }
4730
4731
4732 int
4733 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4734                         struct rte_eth_ethertype_filter *filter,
4735                         bool add)
4736 {
4737         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4738         struct e1000_filter_info *filter_info =
4739                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4740         uint32_t etqf = 0;
4741         int ret;
4742
4743         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4744                 filter->ether_type == ETHER_TYPE_IPv6) {
4745                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4746                         " ethertype filter.", filter->ether_type);
4747                 return -EINVAL;
4748         }
4749
4750         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4751                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4752                 return -EINVAL;
4753         }
4754         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4755                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4756                 return -EINVAL;
4757         }
4758
4759         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4760         if (ret >= 0 && add) {
4761                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4762                             filter->ether_type);
4763                 return -EEXIST;
4764         }
4765         if (ret < 0 && !add) {
4766                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4767                             filter->ether_type);
4768                 return -ENOENT;
4769         }
4770
4771         if (add) {
4772                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4773                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4774                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4775                 ret = igb_ethertype_filter_insert(filter_info,
4776                                 filter->ether_type, etqf);
4777                 if (ret < 0) {
4778                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4779                         return -ENOSYS;
4780                 }
4781         } else {
4782                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4783                 if (ret < 0)
4784                         return -ENOSYS;
4785         }
4786         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4787         E1000_WRITE_FLUSH(hw);
4788
4789         return 0;
4790 }
4791
4792 static int
4793 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4794                         struct rte_eth_ethertype_filter *filter)
4795 {
4796         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4797         struct e1000_filter_info *filter_info =
4798                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4799         uint32_t etqf;
4800         int ret;
4801
4802         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4803         if (ret < 0) {
4804                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4805                             filter->ether_type);
4806                 return -ENOENT;
4807         }
4808
4809         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4810         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4811                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4812                 filter->flags = 0;
4813                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4814                                 E1000_ETQF_QUEUE_SHIFT;
4815                 return 0;
4816         }
4817
4818         return -ENOENT;
4819 }
4820
4821 /*
4822  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4823  * @dev: pointer to rte_eth_dev structure
4824  * @filter_op:operation will be taken.
4825  * @arg: a pointer to specific structure corresponding to the filter_op
4826  */
4827 static int
4828 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4829                                 enum rte_filter_op filter_op,
4830                                 void *arg)
4831 {
4832         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4833         int ret;
4834
4835         MAC_TYPE_FILTER_SUP(hw->mac.type);
4836
4837         if (filter_op == RTE_ETH_FILTER_NOP)
4838                 return 0;
4839
4840         if (arg == NULL) {
4841                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4842                             filter_op);
4843                 return -EINVAL;
4844         }
4845
4846         switch (filter_op) {
4847         case RTE_ETH_FILTER_ADD:
4848                 ret = igb_add_del_ethertype_filter(dev,
4849                         (struct rte_eth_ethertype_filter *)arg,
4850                         TRUE);
4851                 break;
4852         case RTE_ETH_FILTER_DELETE:
4853                 ret = igb_add_del_ethertype_filter(dev,
4854                         (struct rte_eth_ethertype_filter *)arg,
4855                         FALSE);
4856                 break;
4857         case RTE_ETH_FILTER_GET:
4858                 ret = igb_get_ethertype_filter(dev,
4859                         (struct rte_eth_ethertype_filter *)arg);
4860                 break;
4861         default:
4862                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4863                 ret = -EINVAL;
4864                 break;
4865         }
4866         return ret;
4867 }
4868
4869 static int
4870 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4871                      enum rte_filter_type filter_type,
4872                      enum rte_filter_op filter_op,
4873                      void *arg)
4874 {
4875         int ret = 0;
4876
4877         switch (filter_type) {
4878         case RTE_ETH_FILTER_NTUPLE:
4879                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4880                 break;
4881         case RTE_ETH_FILTER_ETHERTYPE:
4882                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4883                 break;
4884         case RTE_ETH_FILTER_SYN:
4885                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4886                 break;
4887         case RTE_ETH_FILTER_FLEXIBLE:
4888                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4889                 break;
4890         case RTE_ETH_FILTER_GENERIC:
4891                 if (filter_op != RTE_ETH_FILTER_GET)
4892                         return -EINVAL;
4893                 *(const void **)arg = &igb_flow_ops;
4894                 break;
4895         default:
4896                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4897                                                         filter_type);
4898                 break;
4899         }
4900
4901         return ret;
4902 }
4903
4904 static int
4905 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4906                          struct ether_addr *mc_addr_set,
4907                          uint32_t nb_mc_addr)
4908 {
4909         struct e1000_hw *hw;
4910
4911         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4912         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4913         return 0;
4914 }
4915
4916 static uint64_t
4917 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4918 {
4919         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4920         uint64_t systime_cycles;
4921
4922         switch (hw->mac.type) {
4923         case e1000_i210:
4924         case e1000_i211:
4925                 /*
4926                  * Need to read System Time Residue Register to be able
4927                  * to read the other two registers.
4928                  */
4929                 E1000_READ_REG(hw, E1000_SYSTIMR);
4930                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4931                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4932                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4933                                 * NSEC_PER_SEC;
4934                 break;
4935         case e1000_82580:
4936         case e1000_i350:
4937         case e1000_i354:
4938                 /*
4939                  * Need to read System Time Residue Register to be able
4940                  * to read the other two registers.
4941                  */
4942                 E1000_READ_REG(hw, E1000_SYSTIMR);
4943                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4944                 /* Only the 8 LSB are valid. */
4945                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4946                                 & 0xff) << 32;
4947                 break;
4948         default:
4949                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4950                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4951                                 << 32;
4952                 break;
4953         }
4954
4955         return systime_cycles;
4956 }
4957
4958 static uint64_t
4959 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4960 {
4961         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4962         uint64_t rx_tstamp_cycles;
4963
4964         switch (hw->mac.type) {
4965         case e1000_i210:
4966         case e1000_i211:
4967                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4968                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4969                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4970                                 * NSEC_PER_SEC;
4971                 break;
4972         case e1000_82580:
4973         case e1000_i350:
4974         case e1000_i354:
4975                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4976                 /* Only the 8 LSB are valid. */
4977                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4978                                 & 0xff) << 32;
4979                 break;
4980         default:
4981                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4982                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4983                                 << 32;
4984                 break;
4985         }
4986
4987         return rx_tstamp_cycles;
4988 }
4989
4990 static uint64_t
4991 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4992 {
4993         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4994         uint64_t tx_tstamp_cycles;
4995
4996         switch (hw->mac.type) {
4997         case e1000_i210:
4998         case e1000_i211:
4999                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5000                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5001                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5002                                 * NSEC_PER_SEC;
5003                 break;
5004         case e1000_82580:
5005         case e1000_i350:
5006         case e1000_i354:
5007                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5008                 /* Only the 8 LSB are valid. */
5009                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5010                                 & 0xff) << 32;
5011                 break;
5012         default:
5013                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5014                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5015                                 << 32;
5016                 break;
5017         }
5018
5019         return tx_tstamp_cycles;
5020 }
5021
5022 static void
5023 igb_start_timecounters(struct rte_eth_dev *dev)
5024 {
5025         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5026         struct e1000_adapter *adapter =
5027                 (struct e1000_adapter *)dev->data->dev_private;
5028         uint32_t incval = 1;
5029         uint32_t shift = 0;
5030         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5031
5032         switch (hw->mac.type) {
5033         case e1000_82580:
5034         case e1000_i350:
5035         case e1000_i354:
5036                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5037                 mask = (1ULL << 40) - 1;
5038                 /* fall-through */
5039         case e1000_i210:
5040         case e1000_i211:
5041                 /*
5042                  * Start incrementing the register
5043                  * used to timestamp PTP packets.
5044                  */
5045                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5046                 break;
5047         case e1000_82576:
5048                 incval = E1000_INCVALUE_82576;
5049                 shift = IGB_82576_TSYNC_SHIFT;
5050                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5051                                 E1000_INCPERIOD_82576 | incval);
5052                 break;
5053         default:
5054                 /* Not supported */
5055                 return;
5056         }
5057
5058         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5059         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5060         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5061
5062         adapter->systime_tc.cc_mask = mask;
5063         adapter->systime_tc.cc_shift = shift;
5064         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5065
5066         adapter->rx_tstamp_tc.cc_mask = mask;
5067         adapter->rx_tstamp_tc.cc_shift = shift;
5068         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5069
5070         adapter->tx_tstamp_tc.cc_mask = mask;
5071         adapter->tx_tstamp_tc.cc_shift = shift;
5072         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5073 }
5074
5075 static int
5076 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5077 {
5078         struct e1000_adapter *adapter =
5079                         (struct e1000_adapter *)dev->data->dev_private;
5080
5081         adapter->systime_tc.nsec += delta;
5082         adapter->rx_tstamp_tc.nsec += delta;
5083         adapter->tx_tstamp_tc.nsec += delta;
5084
5085         return 0;
5086 }
5087
5088 static int
5089 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5090 {
5091         uint64_t ns;
5092         struct e1000_adapter *adapter =
5093                         (struct e1000_adapter *)dev->data->dev_private;
5094
5095         ns = rte_timespec_to_ns(ts);
5096
5097         /* Set the timecounters to a new value. */
5098         adapter->systime_tc.nsec = ns;
5099         adapter->rx_tstamp_tc.nsec = ns;
5100         adapter->tx_tstamp_tc.nsec = ns;
5101
5102         return 0;
5103 }
5104
5105 static int
5106 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5107 {
5108         uint64_t ns, systime_cycles;
5109         struct e1000_adapter *adapter =
5110                         (struct e1000_adapter *)dev->data->dev_private;
5111
5112         systime_cycles = igb_read_systime_cyclecounter(dev);
5113         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5114         *ts = rte_ns_to_timespec(ns);
5115
5116         return 0;
5117 }
5118
5119 static int
5120 igb_timesync_enable(struct rte_eth_dev *dev)
5121 {
5122         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123         uint32_t tsync_ctl;
5124         uint32_t tsauxc;
5125
5126         /* Stop the timesync system time. */
5127         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5128         /* Reset the timesync system time value. */
5129         switch (hw->mac.type) {
5130         case e1000_82580:
5131         case e1000_i350:
5132         case e1000_i354:
5133         case e1000_i210:
5134         case e1000_i211:
5135                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5136                 /* fall-through */
5137         case e1000_82576:
5138                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5139                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5140                 break;
5141         default:
5142                 /* Not supported. */
5143                 return -ENOTSUP;
5144         }
5145
5146         /* Enable system time for it isn't on by default. */
5147         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5148         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5149         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5150
5151         igb_start_timecounters(dev);
5152
5153         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5154         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5155                         (ETHER_TYPE_1588 |
5156                          E1000_ETQF_FILTER_ENABLE |
5157                          E1000_ETQF_1588));
5158
5159         /* Enable timestamping of received PTP packets. */
5160         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5161         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5162         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5163
5164         /* Enable Timestamping of transmitted PTP packets. */
5165         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5166         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5167         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5168
5169         return 0;
5170 }
5171
5172 static int
5173 igb_timesync_disable(struct rte_eth_dev *dev)
5174 {
5175         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5176         uint32_t tsync_ctl;
5177
5178         /* Disable timestamping of transmitted PTP packets. */
5179         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5180         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5181         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5182
5183         /* Disable timestamping of received PTP packets. */
5184         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5185         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5186         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5187
5188         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5189         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5190
5191         /* Stop incrementating the System Time registers. */
5192         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5193
5194         return 0;
5195 }
5196
5197 static int
5198 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5199                                struct timespec *timestamp,
5200                                uint32_t flags __rte_unused)
5201 {
5202         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5203         struct e1000_adapter *adapter =
5204                         (struct e1000_adapter *)dev->data->dev_private;
5205         uint32_t tsync_rxctl;
5206         uint64_t rx_tstamp_cycles;
5207         uint64_t ns;
5208
5209         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5210         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5211                 return -EINVAL;
5212
5213         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5214         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5215         *timestamp = rte_ns_to_timespec(ns);
5216
5217         return  0;
5218 }
5219
5220 static int
5221 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5222                                struct timespec *timestamp)
5223 {
5224         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225         struct e1000_adapter *adapter =
5226                         (struct e1000_adapter *)dev->data->dev_private;
5227         uint32_t tsync_txctl;
5228         uint64_t tx_tstamp_cycles;
5229         uint64_t ns;
5230
5231         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5232         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5233                 return -EINVAL;
5234
5235         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5236         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5237         *timestamp = rte_ns_to_timespec(ns);
5238
5239         return  0;
5240 }
5241
5242 static int
5243 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5244 {
5245         int count = 0;
5246         int g_ind = 0;
5247         const struct reg_info *reg_group;
5248
5249         while ((reg_group = igb_regs[g_ind++]))
5250                 count += igb_reg_group_count(reg_group);
5251
5252         return count;
5253 }
5254
5255 static int
5256 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5257 {
5258         int count = 0;
5259         int g_ind = 0;
5260         const struct reg_info *reg_group;
5261
5262         while ((reg_group = igbvf_regs[g_ind++]))
5263                 count += igb_reg_group_count(reg_group);
5264
5265         return count;
5266 }
5267
5268 static int
5269 eth_igb_get_regs(struct rte_eth_dev *dev,
5270         struct rte_dev_reg_info *regs)
5271 {
5272         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5273         uint32_t *data = regs->data;
5274         int g_ind = 0;
5275         int count = 0;
5276         const struct reg_info *reg_group;
5277
5278         if (data == NULL) {
5279                 regs->length = eth_igb_get_reg_length(dev);
5280                 regs->width = sizeof(uint32_t);
5281                 return 0;
5282         }
5283
5284         /* Support only full register dump */
5285         if ((regs->length == 0) ||
5286             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5287                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5288                         hw->device_id;
5289                 while ((reg_group = igb_regs[g_ind++]))
5290                         count += igb_read_regs_group(dev, &data[count],
5291                                                         reg_group);
5292                 return 0;
5293         }
5294
5295         return -ENOTSUP;
5296 }
5297
5298 static int
5299 igbvf_get_regs(struct rte_eth_dev *dev,
5300         struct rte_dev_reg_info *regs)
5301 {
5302         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303         uint32_t *data = regs->data;
5304         int g_ind = 0;
5305         int count = 0;
5306         const struct reg_info *reg_group;
5307
5308         if (data == NULL) {
5309                 regs->length = igbvf_get_reg_length(dev);
5310                 regs->width = sizeof(uint32_t);
5311                 return 0;
5312         }
5313
5314         /* Support only full register dump */
5315         if ((regs->length == 0) ||
5316             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5317                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5318                         hw->device_id;
5319                 while ((reg_group = igbvf_regs[g_ind++]))
5320                         count += igb_read_regs_group(dev, &data[count],
5321                                                         reg_group);
5322                 return 0;
5323         }
5324
5325         return -ENOTSUP;
5326 }
5327
5328 static int
5329 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5330 {
5331         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5332
5333         /* Return unit is byte count */
5334         return hw->nvm.word_size * 2;
5335 }
5336
5337 static int
5338 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5339         struct rte_dev_eeprom_info *in_eeprom)
5340 {
5341         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5342         struct e1000_nvm_info *nvm = &hw->nvm;
5343         uint16_t *data = in_eeprom->data;
5344         int first, length;
5345
5346         first = in_eeprom->offset >> 1;
5347         length = in_eeprom->length >> 1;
5348         if ((first >= hw->nvm.word_size) ||
5349             ((first + length) >= hw->nvm.word_size))
5350                 return -EINVAL;
5351
5352         in_eeprom->magic = hw->vendor_id |
5353                 ((uint32_t)hw->device_id << 16);
5354
5355         if ((nvm->ops.read) == NULL)
5356                 return -ENOTSUP;
5357
5358         return nvm->ops.read(hw, first, length, data);
5359 }
5360
5361 static int
5362 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5363         struct rte_dev_eeprom_info *in_eeprom)
5364 {
5365         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5366         struct e1000_nvm_info *nvm = &hw->nvm;
5367         uint16_t *data = in_eeprom->data;
5368         int first, length;
5369
5370         first = in_eeprom->offset >> 1;
5371         length = in_eeprom->length >> 1;
5372         if ((first >= hw->nvm.word_size) ||
5373             ((first + length) >= hw->nvm.word_size))
5374                 return -EINVAL;
5375
5376         in_eeprom->magic = (uint32_t)hw->vendor_id |
5377                 ((uint32_t)hw->device_id << 16);
5378
5379         if ((nvm->ops.write) == NULL)
5380                 return -ENOTSUP;
5381         return nvm->ops.write(hw,  first, length, data);
5382 }
5383
5384 static int
5385 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5386 {
5387         struct e1000_hw *hw =
5388                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5389         uint32_t mask = 1 << queue_id;
5390
5391         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5392         E1000_WRITE_FLUSH(hw);
5393
5394         return 0;
5395 }
5396
5397 static int
5398 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5399 {
5400         struct e1000_hw *hw =
5401                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5402         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5403         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5404         uint32_t mask = 1 << queue_id;
5405         uint32_t regval;
5406
5407         regval = E1000_READ_REG(hw, E1000_EIMS);
5408         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5409         E1000_WRITE_FLUSH(hw);
5410
5411         rte_intr_enable(intr_handle);
5412
5413         return 0;
5414 }
5415
5416 static void
5417 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5418                    uint8_t index, uint8_t offset)
5419 {
5420         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5421
5422         /* clear bits */
5423         val &= ~((uint32_t)0xFF << offset);
5424
5425         /* write vector and valid bit */
5426         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5427
5428         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5429 }
5430
5431 static void
5432 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5433                            uint8_t queue, uint8_t msix_vector)
5434 {
5435         uint32_t tmp = 0;
5436
5437         if (hw->mac.type == e1000_82575) {
5438                 if (direction == 0)
5439                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5440                 else if (direction == 1)
5441                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5442                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5443         } else if (hw->mac.type == e1000_82576) {
5444                 if ((direction == 0) || (direction == 1))
5445                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5446                                            ((queue & 0x8) << 1) +
5447                                            8 * direction);
5448         } else if ((hw->mac.type == e1000_82580) ||
5449                         (hw->mac.type == e1000_i350) ||
5450                         (hw->mac.type == e1000_i354) ||
5451                         (hw->mac.type == e1000_i210) ||
5452                         (hw->mac.type == e1000_i211)) {
5453                 if ((direction == 0) || (direction == 1))
5454                         eth_igb_write_ivar(hw, msix_vector,
5455                                            queue >> 1,
5456                                            ((queue & 0x1) << 4) +
5457                                            8 * direction);
5458         }
5459 }
5460
5461 /* Sets up the hardware to generate MSI-X interrupts properly
5462  * @hw
5463  *  board private structure
5464  */
5465 static void
5466 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5467 {
5468         int queue_id;
5469         uint32_t tmpval, regval, intr_mask;
5470         struct e1000_hw *hw =
5471                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5472         uint32_t vec = E1000_MISC_VEC_ID;
5473         uint32_t base = E1000_MISC_VEC_ID;
5474         uint32_t misc_shift = 0;
5475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5476         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5477
5478         /* won't configure msix register if no mapping is done
5479          * between intr vector and event fd
5480          */
5481         if (!rte_intr_dp_is_en(intr_handle))
5482                 return;
5483
5484         if (rte_intr_allow_others(intr_handle)) {
5485                 vec = base = E1000_RX_VEC_START;
5486                 misc_shift = 1;
5487         }
5488
5489         /* set interrupt vector for other causes */
5490         if (hw->mac.type == e1000_82575) {
5491                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5492                 /* enable MSI-X PBA support */
5493                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5494
5495                 /* Auto-Mask interrupts upon ICR read */
5496                 tmpval |= E1000_CTRL_EXT_EIAME;
5497                 tmpval |= E1000_CTRL_EXT_IRCA;
5498
5499                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5500
5501                 /* enable msix_other interrupt */
5502                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5503                 regval = E1000_READ_REG(hw, E1000_EIAC);
5504                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5505                 regval = E1000_READ_REG(hw, E1000_EIAM);
5506                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5507         } else if ((hw->mac.type == e1000_82576) ||
5508                         (hw->mac.type == e1000_82580) ||
5509                         (hw->mac.type == e1000_i350) ||
5510                         (hw->mac.type == e1000_i354) ||
5511                         (hw->mac.type == e1000_i210) ||
5512                         (hw->mac.type == e1000_i211)) {
5513                 /* turn on MSI-X capability first */
5514                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5515                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5516                                         E1000_GPIE_NSICR);
5517                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5518                         misc_shift;
5519                 regval = E1000_READ_REG(hw, E1000_EIAC);
5520                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5521
5522                 /* enable msix_other interrupt */
5523                 regval = E1000_READ_REG(hw, E1000_EIMS);
5524                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5525                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5526                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5527         }
5528
5529         /* use EIAM to auto-mask when MSI-X interrupt
5530          * is asserted, this saves a register write for every interrupt
5531          */
5532         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5533                 misc_shift;
5534         regval = E1000_READ_REG(hw, E1000_EIAM);
5535         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5536
5537         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5538                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5539                 intr_handle->intr_vec[queue_id] = vec;
5540                 if (vec < base + intr_handle->nb_efd - 1)
5541                         vec++;
5542         }
5543
5544         E1000_WRITE_FLUSH(hw);
5545 }
5546
5547 /* restore n-tuple filter */
5548 static inline void
5549 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5550 {
5551         struct e1000_filter_info *filter_info =
5552                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5553         struct e1000_5tuple_filter *p_5tuple;
5554         struct e1000_2tuple_filter *p_2tuple;
5555
5556         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5557                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5558         }
5559
5560         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5561                 igb_inject_2uple_filter(dev, p_2tuple);
5562         }
5563 }
5564
5565 /* restore SYN filter */
5566 static inline void
5567 igb_syn_filter_restore(struct rte_eth_dev *dev)
5568 {
5569         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5570         struct e1000_filter_info *filter_info =
5571                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5572         uint32_t synqf;
5573
5574         synqf = filter_info->syn_info;
5575
5576         if (synqf & E1000_SYN_FILTER_ENABLE) {
5577                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5578                 E1000_WRITE_FLUSH(hw);
5579         }
5580 }
5581
5582 /* restore ethernet type filter */
5583 static inline void
5584 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5585 {
5586         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5587         struct e1000_filter_info *filter_info =
5588                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5589         int i;
5590
5591         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5592                 if (filter_info->ethertype_mask & (1 << i)) {
5593                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5594                                 filter_info->ethertype_filters[i].etqf);
5595                         E1000_WRITE_FLUSH(hw);
5596                 }
5597         }
5598 }
5599
5600 /* restore flex byte filter */
5601 static inline void
5602 igb_flex_filter_restore(struct rte_eth_dev *dev)
5603 {
5604         struct e1000_filter_info *filter_info =
5605                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5606         struct e1000_flex_filter *flex_filter;
5607
5608         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5609                 igb_inject_flex_filter(dev, flex_filter);
5610         }
5611 }
5612
5613 /* restore all types filter */
5614 static int
5615 igb_filter_restore(struct rte_eth_dev *dev)
5616 {
5617         igb_ntuple_filter_restore(dev);
5618         igb_ethertype_filter_restore(dev);
5619         igb_syn_filter_restore(dev);
5620         igb_flex_filter_restore(dev);
5621
5622         return 0;
5623 }
5624
5625 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5626 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5627 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5628 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5629 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5630 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");