1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static void eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static int eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
158 static int igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
190 struct rte_eth_syn_filter *filter);
191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
192 enum rte_filter_op filter_op,
194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
197 struct rte_eth_ntuple_filter *ntuple_filter);
198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
199 struct rte_eth_flex_filter *filter);
200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
201 enum rte_filter_op filter_op,
203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
204 struct rte_eth_ntuple_filter *ntuple_filter);
205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
206 struct rte_eth_ntuple_filter *ntuple_filter);
207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
208 struct rte_eth_ntuple_filter *filter);
209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
210 enum rte_filter_op filter_op,
212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ethertype_filter *filter);
217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
218 enum rte_filter_type filter_type,
219 enum rte_filter_op filter_op,
221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
223 struct rte_dev_reg_info *regs);
224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
226 struct rte_dev_eeprom_info *eeprom);
227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
228 struct rte_dev_eeprom_info *eeprom);
229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
230 struct rte_eth_dev_module_info *modinfo);
231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
232 struct rte_dev_eeprom_info *info);
233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
234 struct rte_ether_addr *mc_addr_set,
235 uint32_t nb_mc_addr);
236 static int igb_timesync_enable(struct rte_eth_dev *dev);
237 static int igb_timesync_disable(struct rte_eth_dev *dev);
238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
239 struct timespec *timestamp,
241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
242 struct timespec *timestamp);
243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
245 struct timespec *timestamp);
246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
247 const struct timespec *timestamp);
248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
253 uint8_t queue, uint8_t msix_vector);
254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
255 uint8_t index, uint8_t offset);
256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
257 static void eth_igbvf_interrupt_handler(void *param);
258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
259 static int igb_filter_restore(struct rte_eth_dev *dev);
262 * Define VF Stats MACRO for Non "cleared on read" register
264 #define UPDATE_VF_STAT(reg, last, cur) \
266 u32 latest = E1000_READ_REG(hw, reg); \
267 cur += (latest - last) & UINT_MAX; \
271 #define IGB_FC_PAUSE_TIME 0x0680
272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
275 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
280 * The set of PCI devices this driver supports
282 static const struct rte_pci_id pci_id_igb_map[] = {
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
324 { .vendor_id = 0, /* sentinel */ },
328 * The set of PCI devices this driver supports (for 82576&I350 VF)
330 static const struct rte_pci_id pci_id_igbvf_map[] = {
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
335 { .vendor_id = 0, /* sentinel */ },
338 static const struct rte_eth_desc_lim rx_desc_lim = {
339 .nb_max = E1000_MAX_RING_DESC,
340 .nb_min = E1000_MIN_RING_DESC,
341 .nb_align = IGB_RXD_ALIGN,
344 static const struct rte_eth_desc_lim tx_desc_lim = {
345 .nb_max = E1000_MAX_RING_DESC,
346 .nb_min = E1000_MIN_RING_DESC,
347 .nb_align = IGB_RXD_ALIGN,
348 .nb_seg_max = IGB_TX_MAX_SEG,
349 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
352 static const struct eth_dev_ops eth_igb_ops = {
353 .dev_configure = eth_igb_configure,
354 .dev_start = eth_igb_start,
355 .dev_stop = eth_igb_stop,
356 .dev_set_link_up = eth_igb_dev_set_link_up,
357 .dev_set_link_down = eth_igb_dev_set_link_down,
358 .dev_close = eth_igb_close,
359 .dev_reset = eth_igb_reset,
360 .promiscuous_enable = eth_igb_promiscuous_enable,
361 .promiscuous_disable = eth_igb_promiscuous_disable,
362 .allmulticast_enable = eth_igb_allmulticast_enable,
363 .allmulticast_disable = eth_igb_allmulticast_disable,
364 .link_update = eth_igb_link_update,
365 .stats_get = eth_igb_stats_get,
366 .xstats_get = eth_igb_xstats_get,
367 .xstats_get_by_id = eth_igb_xstats_get_by_id,
368 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
369 .xstats_get_names = eth_igb_xstats_get_names,
370 .stats_reset = eth_igb_stats_reset,
371 .xstats_reset = eth_igb_xstats_reset,
372 .fw_version_get = eth_igb_fw_version_get,
373 .dev_infos_get = eth_igb_infos_get,
374 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
375 .mtu_set = eth_igb_mtu_set,
376 .vlan_filter_set = eth_igb_vlan_filter_set,
377 .vlan_tpid_set = eth_igb_vlan_tpid_set,
378 .vlan_offload_set = eth_igb_vlan_offload_set,
379 .rx_queue_setup = eth_igb_rx_queue_setup,
380 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
381 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
382 .rx_queue_release = eth_igb_rx_queue_release,
383 .tx_queue_setup = eth_igb_tx_queue_setup,
384 .tx_queue_release = eth_igb_tx_queue_release,
385 .tx_done_cleanup = eth_igb_tx_done_cleanup,
386 .dev_led_on = eth_igb_led_on,
387 .dev_led_off = eth_igb_led_off,
388 .flow_ctrl_get = eth_igb_flow_ctrl_get,
389 .flow_ctrl_set = eth_igb_flow_ctrl_set,
390 .mac_addr_add = eth_igb_rar_set,
391 .mac_addr_remove = eth_igb_rar_clear,
392 .mac_addr_set = eth_igb_default_mac_addr_set,
393 .reta_update = eth_igb_rss_reta_update,
394 .reta_query = eth_igb_rss_reta_query,
395 .rss_hash_update = eth_igb_rss_hash_update,
396 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
397 .filter_ctrl = eth_igb_filter_ctrl,
398 .set_mc_addr_list = eth_igb_set_mc_addr_list,
399 .rxq_info_get = igb_rxq_info_get,
400 .txq_info_get = igb_txq_info_get,
401 .timesync_enable = igb_timesync_enable,
402 .timesync_disable = igb_timesync_disable,
403 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
404 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
405 .get_reg = eth_igb_get_regs,
406 .get_eeprom_length = eth_igb_get_eeprom_length,
407 .get_eeprom = eth_igb_get_eeprom,
408 .set_eeprom = eth_igb_set_eeprom,
409 .get_module_info = eth_igb_get_module_info,
410 .get_module_eeprom = eth_igb_get_module_eeprom,
411 .timesync_adjust_time = igb_timesync_adjust_time,
412 .timesync_read_time = igb_timesync_read_time,
413 .timesync_write_time = igb_timesync_write_time,
417 * dev_ops for virtual function, bare necessities for basic vf
418 * operation have been implemented
420 static const struct eth_dev_ops igbvf_eth_dev_ops = {
421 .dev_configure = igbvf_dev_configure,
422 .dev_start = igbvf_dev_start,
423 .dev_stop = igbvf_dev_stop,
424 .dev_close = igbvf_dev_close,
425 .promiscuous_enable = igbvf_promiscuous_enable,
426 .promiscuous_disable = igbvf_promiscuous_disable,
427 .allmulticast_enable = igbvf_allmulticast_enable,
428 .allmulticast_disable = igbvf_allmulticast_disable,
429 .link_update = eth_igb_link_update,
430 .stats_get = eth_igbvf_stats_get,
431 .xstats_get = eth_igbvf_xstats_get,
432 .xstats_get_names = eth_igbvf_xstats_get_names,
433 .stats_reset = eth_igbvf_stats_reset,
434 .xstats_reset = eth_igbvf_stats_reset,
435 .vlan_filter_set = igbvf_vlan_filter_set,
436 .dev_infos_get = eth_igbvf_infos_get,
437 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
438 .rx_queue_setup = eth_igb_rx_queue_setup,
439 .rx_queue_release = eth_igb_rx_queue_release,
440 .tx_queue_setup = eth_igb_tx_queue_setup,
441 .tx_queue_release = eth_igb_tx_queue_release,
442 .tx_done_cleanup = eth_igb_tx_done_cleanup,
443 .set_mc_addr_list = eth_igb_set_mc_addr_list,
444 .rxq_info_get = igb_rxq_info_get,
445 .txq_info_get = igb_txq_info_get,
446 .mac_addr_set = igbvf_default_mac_addr_set,
447 .get_reg = igbvf_get_regs,
450 /* store statistics names and its offset in stats structure */
451 struct rte_igb_xstats_name_off {
452 char name[RTE_ETH_XSTATS_NAME_SIZE];
456 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
457 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
458 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
459 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
460 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
461 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
462 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
463 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
465 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
466 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
467 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
468 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
469 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
470 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
471 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
472 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
473 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
474 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
475 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
477 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
478 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
479 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
480 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
481 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
483 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
485 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
486 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
487 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
488 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
489 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
490 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
491 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
492 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
493 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
494 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
495 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
496 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
497 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
498 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
499 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
500 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
501 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
502 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
504 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
506 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
507 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
508 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
509 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
510 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
511 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
512 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
514 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
517 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
518 sizeof(rte_igb_stats_strings[0]))
520 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
521 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
522 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
523 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
524 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
525 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
528 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
529 sizeof(rte_igbvf_stats_strings[0]))
533 igb_intr_enable(struct rte_eth_dev *dev)
535 struct e1000_interrupt *intr =
536 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
537 struct e1000_hw *hw =
538 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
539 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
540 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
542 if (rte_intr_allow_others(intr_handle) &&
543 dev->data->dev_conf.intr_conf.lsc != 0) {
544 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
547 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
548 E1000_WRITE_FLUSH(hw);
552 igb_intr_disable(struct rte_eth_dev *dev)
554 struct e1000_hw *hw =
555 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
556 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
557 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
559 if (rte_intr_allow_others(intr_handle) &&
560 dev->data->dev_conf.intr_conf.lsc != 0) {
561 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
564 E1000_WRITE_REG(hw, E1000_IMC, ~0);
565 E1000_WRITE_FLUSH(hw);
569 igbvf_intr_enable(struct rte_eth_dev *dev)
571 struct e1000_hw *hw =
572 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
574 /* only for mailbox */
575 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
576 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
577 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
578 E1000_WRITE_FLUSH(hw);
581 /* only for mailbox now. If RX/TX needed, should extend this function. */
583 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
588 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
589 tmp |= E1000_VTIVAR_VALID;
590 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
594 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
596 struct e1000_hw *hw =
597 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
599 /* Configure VF other cause ivar */
600 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
603 static inline int32_t
604 igb_pf_reset_hw(struct e1000_hw *hw)
609 status = e1000_reset_hw(hw);
611 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
612 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
613 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
614 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
615 E1000_WRITE_FLUSH(hw);
621 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
623 struct e1000_hw *hw =
624 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
627 hw->vendor_id = pci_dev->id.vendor_id;
628 hw->device_id = pci_dev->id.device_id;
629 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
630 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
632 e1000_set_mac_type(hw);
634 /* need to check if it is a vf device below */
638 igb_reset_swfw_lock(struct e1000_hw *hw)
643 * Do mac ops initialization manually here, since we will need
644 * some function pointers set by this call.
646 ret_val = e1000_init_mac_params(hw);
651 * SMBI lock should not fail in this early stage. If this is the case,
652 * it is due to an improper exit of the application.
653 * So force the release of the faulty lock.
655 if (e1000_get_hw_semaphore_generic(hw) < 0) {
656 PMD_DRV_LOG(DEBUG, "SMBI lock released");
658 e1000_put_hw_semaphore_generic(hw);
660 if (hw->mac.ops.acquire_swfw_sync != NULL) {
664 * Phy lock should not fail in this early stage. If this is the case,
665 * it is due to an improper exit of the application.
666 * So force the release of the faulty lock.
668 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
669 if (hw->bus.func > E1000_FUNC_1)
671 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
672 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
675 hw->mac.ops.release_swfw_sync(hw, mask);
678 * This one is more tricky since it is common to all ports; but
679 * swfw_sync retries last long enough (1s) to be almost sure that if
680 * lock can not be taken it is due to an improper lock of the
683 mask = E1000_SWFW_EEP_SM;
684 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
685 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
687 hw->mac.ops.release_swfw_sync(hw, mask);
690 return E1000_SUCCESS;
693 /* Remove all ntuple filters of the device */
694 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
696 struct e1000_filter_info *filter_info =
697 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
698 struct e1000_5tuple_filter *p_5tuple;
699 struct e1000_2tuple_filter *p_2tuple;
701 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
702 TAILQ_REMOVE(&filter_info->fivetuple_list,
706 filter_info->fivetuple_mask = 0;
707 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
708 TAILQ_REMOVE(&filter_info->twotuple_list,
712 filter_info->twotuple_mask = 0;
717 /* Remove all flex filters of the device */
718 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
720 struct e1000_filter_info *filter_info =
721 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
722 struct e1000_flex_filter *p_flex;
724 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
725 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
728 filter_info->flex_mask = 0;
734 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
737 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
738 struct e1000_hw *hw =
739 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
740 struct e1000_vfta * shadow_vfta =
741 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
742 struct e1000_filter_info *filter_info =
743 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
744 struct e1000_adapter *adapter =
745 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
749 eth_dev->dev_ops = ð_igb_ops;
750 eth_dev->rx_queue_count = eth_igb_rx_queue_count;
751 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
752 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
753 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
754 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
755 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
756 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
758 /* for secondary processes, we don't initialise any further as primary
759 * has already done this work. Only check we don't need a different
761 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
762 if (eth_dev->data->scattered_rx)
763 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
767 rte_eth_copy_pci_info(eth_dev, pci_dev);
769 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
771 igb_identify_hardware(eth_dev, pci_dev);
772 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
777 e1000_get_bus_info(hw);
779 /* Reset any pending lock */
780 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
785 /* Finish initialization */
786 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
792 hw->phy.autoneg_wait_to_complete = 0;
793 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
796 if (hw->phy.media_type == e1000_media_type_copper) {
797 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
798 hw->phy.disable_polarity_correction = 0;
799 hw->phy.ms_type = e1000_ms_hw_default;
803 * Start from a known state, this is important in reading the nvm
808 /* Make sure we have a good EEPROM before we read from it */
809 if (e1000_validate_nvm_checksum(hw) < 0) {
811 * Some PCI-E parts fail the first check due to
812 * the link being in sleep state, call it again,
813 * if it fails a second time its a real issue.
815 if (e1000_validate_nvm_checksum(hw) < 0) {
816 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
822 /* Read the permanent MAC address out of the EEPROM */
823 if (e1000_read_mac_addr(hw) != 0) {
824 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
829 /* Allocate memory for storing MAC addresses */
830 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
831 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
832 if (eth_dev->data->mac_addrs == NULL) {
833 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
834 "store MAC addresses",
835 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
840 /* Copy the permanent MAC address */
841 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
842 ð_dev->data->mac_addrs[0]);
844 /* initialize the vfta */
845 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
847 /* Now initialize the hardware */
848 if (igb_hardware_init(hw) != 0) {
849 PMD_INIT_LOG(ERR, "Hardware initialization failed");
850 rte_free(eth_dev->data->mac_addrs);
851 eth_dev->data->mac_addrs = NULL;
855 hw->mac.get_link_status = 1;
856 adapter->stopped = 0;
858 /* Indicate SOL/IDER usage */
859 if (e1000_check_reset_block(hw) < 0) {
860 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
864 /* initialize PF if max_vfs not zero */
865 igb_pf_host_init(eth_dev);
867 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
868 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
869 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
870 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
871 E1000_WRITE_FLUSH(hw);
873 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
874 eth_dev->data->port_id, pci_dev->id.vendor_id,
875 pci_dev->id.device_id);
877 rte_intr_callback_register(&pci_dev->intr_handle,
878 eth_igb_interrupt_handler,
881 /* enable uio/vfio intr/eventfd mapping */
882 rte_intr_enable(&pci_dev->intr_handle);
884 /* enable support intr */
885 igb_intr_enable(eth_dev);
887 eth_igb_dev_set_link_down(eth_dev);
889 /* initialize filter info */
890 memset(filter_info, 0,
891 sizeof(struct e1000_filter_info));
893 TAILQ_INIT(&filter_info->flex_list);
894 TAILQ_INIT(&filter_info->twotuple_list);
895 TAILQ_INIT(&filter_info->fivetuple_list);
897 TAILQ_INIT(&igb_filter_ntuple_list);
898 TAILQ_INIT(&igb_filter_ethertype_list);
899 TAILQ_INIT(&igb_filter_syn_list);
900 TAILQ_INIT(&igb_filter_flex_list);
901 TAILQ_INIT(&igb_filter_rss_list);
902 TAILQ_INIT(&igb_flow_list);
907 igb_hw_control_release(hw);
913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
915 PMD_INIT_FUNC_TRACE();
917 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
920 eth_igb_close(eth_dev);
926 * Virtual Function device init
929 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
931 struct rte_pci_device *pci_dev;
932 struct rte_intr_handle *intr_handle;
933 struct e1000_adapter *adapter =
934 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
935 struct e1000_hw *hw =
936 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
938 struct rte_ether_addr *perm_addr =
939 (struct rte_ether_addr *)hw->mac.perm_addr;
941 PMD_INIT_FUNC_TRACE();
943 eth_dev->dev_ops = &igbvf_eth_dev_ops;
944 eth_dev->rx_descriptor_done = eth_igb_rx_descriptor_done;
945 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
946 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
947 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
948 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
949 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
951 /* for secondary processes, we don't initialise any further as primary
952 * has already done this work. Only check we don't need a different
954 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
955 if (eth_dev->data->scattered_rx)
956 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
960 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
961 rte_eth_copy_pci_info(eth_dev, pci_dev);
963 hw->device_id = pci_dev->id.device_id;
964 hw->vendor_id = pci_dev->id.vendor_id;
965 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
966 adapter->stopped = 0;
968 /* Initialize the shared code (base driver) */
969 diag = e1000_setup_init_funcs(hw, TRUE);
971 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
976 /* init_mailbox_params */
977 hw->mbx.ops.init_params(hw);
979 /* Disable the interrupts for VF */
980 igbvf_intr_disable(hw);
982 diag = hw->mac.ops.reset_hw(hw);
984 /* Allocate memory for storing MAC addresses */
985 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
986 hw->mac.rar_entry_count, 0);
987 if (eth_dev->data->mac_addrs == NULL) {
989 "Failed to allocate %d bytes needed to store MAC "
991 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
995 /* Generate a random MAC address, if none was assigned by PF. */
996 if (rte_is_zero_ether_addr(perm_addr)) {
997 rte_eth_random_addr(perm_addr->addr_bytes);
998 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
999 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1000 "%02x:%02x:%02x:%02x:%02x:%02x",
1001 perm_addr->addr_bytes[0],
1002 perm_addr->addr_bytes[1],
1003 perm_addr->addr_bytes[2],
1004 perm_addr->addr_bytes[3],
1005 perm_addr->addr_bytes[4],
1006 perm_addr->addr_bytes[5]);
1009 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1011 rte_free(eth_dev->data->mac_addrs);
1012 eth_dev->data->mac_addrs = NULL;
1015 /* Copy the permanent MAC address */
1016 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1017 ð_dev->data->mac_addrs[0]);
1019 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1021 eth_dev->data->port_id, pci_dev->id.vendor_id,
1022 pci_dev->id.device_id, "igb_mac_82576_vf");
1024 intr_handle = &pci_dev->intr_handle;
1025 rte_intr_callback_register(intr_handle,
1026 eth_igbvf_interrupt_handler, eth_dev);
1032 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1034 PMD_INIT_FUNC_TRACE();
1036 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1039 igbvf_dev_close(eth_dev);
1044 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1045 struct rte_pci_device *pci_dev)
1047 return rte_eth_dev_pci_generic_probe(pci_dev,
1048 sizeof(struct e1000_adapter), eth_igb_dev_init);
1051 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1053 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1056 static struct rte_pci_driver rte_igb_pmd = {
1057 .id_table = pci_id_igb_map,
1058 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1059 .probe = eth_igb_pci_probe,
1060 .remove = eth_igb_pci_remove,
1064 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1065 struct rte_pci_device *pci_dev)
1067 return rte_eth_dev_pci_generic_probe(pci_dev,
1068 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1071 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1073 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1077 * virtual function driver struct
1079 static struct rte_pci_driver rte_igbvf_pmd = {
1080 .id_table = pci_id_igbvf_map,
1081 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1082 .probe = eth_igbvf_pci_probe,
1083 .remove = eth_igbvf_pci_remove,
1087 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1089 struct e1000_hw *hw =
1090 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1091 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1092 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1093 rctl |= E1000_RCTL_VFE;
1094 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1098 igb_check_mq_mode(struct rte_eth_dev *dev)
1100 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1101 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1102 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1103 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1105 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1106 tx_mq_mode == ETH_MQ_TX_DCB ||
1107 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1108 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1111 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1112 /* Check multi-queue mode.
1113 * To no break software we accept ETH_MQ_RX_NONE as this might
1114 * be used to turn off VLAN filter.
1117 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1118 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1119 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1120 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1122 /* Only support one queue on VFs.
1123 * RSS together with SRIOV is not supported.
1125 PMD_INIT_LOG(ERR, "SRIOV is active,"
1126 " wrong mq_mode rx %d.",
1130 /* TX mode is not used here, so mode might be ignored.*/
1131 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1132 /* SRIOV only works in VMDq enable mode */
1133 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1134 " TX mode %d is not supported. "
1135 " Driver will behave as %d mode.",
1136 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1139 /* check valid queue number */
1140 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1141 PMD_INIT_LOG(ERR, "SRIOV is active,"
1142 " only support one queue on VFs.");
1146 /* To no break software that set invalid mode, only display
1147 * warning if invalid mode is used.
1149 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1150 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1151 rx_mq_mode != ETH_MQ_RX_RSS) {
1152 /* RSS together with VMDq not supported*/
1153 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1158 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1159 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1160 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1161 " Due to txmode is meaningless in this"
1162 " driver, just ignore.",
1170 eth_igb_configure(struct rte_eth_dev *dev)
1172 struct e1000_interrupt *intr =
1173 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1176 PMD_INIT_FUNC_TRACE();
1178 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1179 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1181 /* multipe queue mode checking */
1182 ret = igb_check_mq_mode(dev);
1184 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1189 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1190 PMD_INIT_FUNC_TRACE();
1196 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1199 struct e1000_hw *hw =
1200 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1201 uint32_t tctl, rctl;
1203 tctl = E1000_READ_REG(hw, E1000_TCTL);
1204 rctl = E1000_READ_REG(hw, E1000_RCTL);
1208 tctl |= E1000_TCTL_EN;
1209 rctl |= E1000_RCTL_EN;
1212 tctl &= ~E1000_TCTL_EN;
1213 rctl &= ~E1000_RCTL_EN;
1215 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1216 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1217 E1000_WRITE_FLUSH(hw);
1221 eth_igb_start(struct rte_eth_dev *dev)
1223 struct e1000_hw *hw =
1224 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1225 struct e1000_adapter *adapter =
1226 E1000_DEV_PRIVATE(dev->data->dev_private);
1227 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1228 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1230 uint32_t intr_vector = 0;
1236 PMD_INIT_FUNC_TRACE();
1238 /* disable uio/vfio intr/eventfd mapping */
1239 rte_intr_disable(intr_handle);
1241 /* Power up the phy. Needed to make the link go Up */
1242 eth_igb_dev_set_link_up(dev);
1245 * Packet Buffer Allocation (PBA)
1246 * Writing PBA sets the receive portion of the buffer
1247 * the remainder is used for the transmit buffer.
1249 if (hw->mac.type == e1000_82575) {
1252 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1253 E1000_WRITE_REG(hw, E1000_PBA, pba);
1256 /* Put the address into the Receive Address Array */
1257 e1000_rar_set(hw, hw->mac.addr, 0);
1259 /* Initialize the hardware */
1260 if (igb_hardware_init(hw)) {
1261 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1264 adapter->stopped = 0;
1266 E1000_WRITE_REG(hw, E1000_VET,
1267 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1269 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1270 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1271 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1272 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1273 E1000_WRITE_FLUSH(hw);
1275 /* configure PF module if SRIOV enabled */
1276 igb_pf_host_configure(dev);
1278 /* check and configure queue intr-vector mapping */
1279 if ((rte_intr_cap_multiple(intr_handle) ||
1280 !RTE_ETH_DEV_SRIOV(dev).active) &&
1281 dev->data->dev_conf.intr_conf.rxq != 0) {
1282 intr_vector = dev->data->nb_rx_queues;
1283 if (rte_intr_efd_enable(intr_handle, intr_vector))
1287 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1288 intr_handle->intr_vec =
1289 rte_zmalloc("intr_vec",
1290 dev->data->nb_rx_queues * sizeof(int), 0);
1291 if (intr_handle->intr_vec == NULL) {
1292 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1293 " intr_vec", dev->data->nb_rx_queues);
1298 /* confiugre msix for rx interrupt */
1299 eth_igb_configure_msix_intr(dev);
1301 /* Configure for OS presence */
1302 igb_init_manageability(hw);
1304 eth_igb_tx_init(dev);
1306 /* This can fail when allocating mbufs for descriptor rings */
1307 ret = eth_igb_rx_init(dev);
1309 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1310 igb_dev_clear_queues(dev);
1314 e1000_clear_hw_cntrs_base_generic(hw);
1317 * VLAN Offload Settings
1319 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1320 ETH_VLAN_EXTEND_MASK;
1321 ret = eth_igb_vlan_offload_set(dev, mask);
1323 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1324 igb_dev_clear_queues(dev);
1328 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1329 /* Enable VLAN filter since VMDq always use VLAN filter */
1330 igb_vmdq_vlan_hw_filter_enable(dev);
1333 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1334 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1335 (hw->mac.type == e1000_i211)) {
1336 /* Configure EITR with the maximum possible value (0xFFFF) */
1337 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1340 /* Setup link speed and duplex */
1341 speeds = &dev->data->dev_conf.link_speeds;
1342 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1343 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1344 hw->mac.autoneg = 1;
1347 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1350 hw->phy.autoneg_advertised = 0;
1352 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1353 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1354 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1356 goto error_invalid_config;
1358 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1359 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1362 if (*speeds & ETH_LINK_SPEED_10M) {
1363 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1366 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1367 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1370 if (*speeds & ETH_LINK_SPEED_100M) {
1371 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1374 if (*speeds & ETH_LINK_SPEED_1G) {
1375 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1378 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1379 goto error_invalid_config;
1381 /* Set/reset the mac.autoneg based on the link speed,
1385 hw->mac.autoneg = 0;
1386 hw->mac.forced_speed_duplex =
1387 hw->phy.autoneg_advertised;
1389 hw->mac.autoneg = 1;
1393 e1000_setup_link(hw);
1395 if (rte_intr_allow_others(intr_handle)) {
1396 /* check if lsc interrupt is enabled */
1397 if (dev->data->dev_conf.intr_conf.lsc != 0)
1398 eth_igb_lsc_interrupt_setup(dev, TRUE);
1400 eth_igb_lsc_interrupt_setup(dev, FALSE);
1402 rte_intr_callback_unregister(intr_handle,
1403 eth_igb_interrupt_handler,
1405 if (dev->data->dev_conf.intr_conf.lsc != 0)
1406 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1407 " no intr multiplex");
1410 /* check if rxq interrupt is enabled */
1411 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1412 rte_intr_dp_is_en(intr_handle))
1413 eth_igb_rxq_interrupt_setup(dev);
1415 /* enable uio/vfio intr/eventfd mapping */
1416 rte_intr_enable(intr_handle);
1418 /* resume enabled intr since hw reset */
1419 igb_intr_enable(dev);
1421 /* restore all types filter */
1422 igb_filter_restore(dev);
1424 eth_igb_rxtx_control(dev, true);
1425 eth_igb_link_update(dev, 0);
1427 PMD_INIT_LOG(DEBUG, "<<");
1431 error_invalid_config:
1432 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1433 dev->data->dev_conf.link_speeds, dev->data->port_id);
1434 igb_dev_clear_queues(dev);
1438 /*********************************************************************
1440 * This routine disables all traffic on the adapter by issuing a
1441 * global reset on the MAC.
1443 **********************************************************************/
1445 eth_igb_stop(struct rte_eth_dev *dev)
1447 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1448 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1449 struct rte_eth_link link;
1450 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1451 struct e1000_adapter *adapter =
1452 E1000_DEV_PRIVATE(dev->data->dev_private);
1454 if (adapter->stopped)
1457 eth_igb_rxtx_control(dev, false);
1459 igb_intr_disable(dev);
1461 /* disable intr eventfd mapping */
1462 rte_intr_disable(intr_handle);
1464 igb_pf_reset_hw(hw);
1465 E1000_WRITE_REG(hw, E1000_WUC, 0);
1467 /* Set bit for Go Link disconnect if PHY reset is not blocked */
1468 if (hw->mac.type >= e1000_82580 &&
1469 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1472 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1473 phpm_reg |= E1000_82580_PM_GO_LINKD;
1474 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1477 /* Power down the phy. Needed to make the link go Down */
1478 eth_igb_dev_set_link_down(dev);
1480 igb_dev_clear_queues(dev);
1482 /* clear the recorded link status */
1483 memset(&link, 0, sizeof(link));
1484 rte_eth_linkstatus_set(dev, &link);
1486 if (!rte_intr_allow_others(intr_handle))
1487 /* resume to the default handler */
1488 rte_intr_callback_register(intr_handle,
1489 eth_igb_interrupt_handler,
1492 /* Clean datapath event and queue/vec mapping */
1493 rte_intr_efd_disable(intr_handle);
1494 if (intr_handle->intr_vec != NULL) {
1495 rte_free(intr_handle->intr_vec);
1496 intr_handle->intr_vec = NULL;
1499 adapter->stopped = true;
1500 dev->data->dev_started = 0;
1504 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1506 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1508 if (hw->phy.media_type == e1000_media_type_copper)
1509 e1000_power_up_phy(hw);
1511 e1000_power_up_fiber_serdes_link(hw);
1517 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1519 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521 if (hw->phy.media_type == e1000_media_type_copper)
1522 e1000_power_down_phy(hw);
1524 e1000_shutdown_fiber_serdes_link(hw);
1530 eth_igb_close(struct rte_eth_dev *dev)
1532 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533 struct rte_eth_link link;
1534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1535 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1536 struct e1000_filter_info *filter_info =
1537 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1539 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1544 e1000_phy_hw_reset(hw);
1545 igb_release_manageability(hw);
1546 igb_hw_control_release(hw);
1548 /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1549 if (hw->mac.type >= e1000_82580 &&
1550 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1553 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1554 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1555 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1558 igb_dev_free_queues(dev);
1560 if (intr_handle->intr_vec) {
1561 rte_free(intr_handle->intr_vec);
1562 intr_handle->intr_vec = NULL;
1565 memset(&link, 0, sizeof(link));
1566 rte_eth_linkstatus_set(dev, &link);
1568 dev->dev_ops = NULL;
1569 dev->rx_pkt_burst = NULL;
1570 dev->tx_pkt_burst = NULL;
1572 /* Reset any pending lock */
1573 igb_reset_swfw_lock(hw);
1575 /* uninitialize PF if max_vfs not zero */
1576 igb_pf_host_uninit(dev);
1578 rte_intr_callback_unregister(intr_handle,
1579 eth_igb_interrupt_handler, dev);
1581 /* clear the SYN filter info */
1582 filter_info->syn_info = 0;
1584 /* clear the ethertype filters info */
1585 filter_info->ethertype_mask = 0;
1586 memset(filter_info->ethertype_filters, 0,
1587 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1589 /* clear the rss filter info */
1590 memset(&filter_info->rss_info, 0,
1591 sizeof(struct igb_rte_flow_rss_conf));
1593 /* remove all ntuple filters of the device */
1594 igb_ntuple_filter_uninit(dev);
1596 /* remove all flex filters of the device */
1597 igb_flex_filter_uninit(dev);
1599 /* clear all the filters list */
1600 igb_filterlist_flush(dev);
1609 eth_igb_reset(struct rte_eth_dev *dev)
1613 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1614 * its VF to make them align with it. The detailed notification
1615 * mechanism is PMD specific and is currently not implemented.
1616 * To avoid unexpected behavior in VF, currently reset of PF with
1617 * SR-IOV activation is not supported. It might be supported later.
1619 if (dev->data->sriov.active)
1622 ret = eth_igb_dev_uninit(dev);
1626 ret = eth_igb_dev_init(dev);
1633 igb_get_rx_buffer_size(struct e1000_hw *hw)
1635 uint32_t rx_buf_size;
1636 if (hw->mac.type == e1000_82576) {
1637 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1638 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1639 /* PBS needs to be translated according to a lookup table */
1640 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1641 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1642 rx_buf_size = (rx_buf_size << 10);
1643 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1644 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1646 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1652 /*********************************************************************
1654 * Initialize the hardware
1656 **********************************************************************/
1658 igb_hardware_init(struct e1000_hw *hw)
1660 uint32_t rx_buf_size;
1663 /* Let the firmware know the OS is in control */
1664 igb_hw_control_acquire(hw);
1667 * These parameters control the automatic generation (Tx) and
1668 * response (Rx) to Ethernet PAUSE frames.
1669 * - High water mark should allow for at least two standard size (1518)
1670 * frames to be received after sending an XOFF.
1671 * - Low water mark works best when it is very near the high water mark.
1672 * This allows the receiver to restart by sending XON when it has
1673 * drained a bit. Here we use an arbitrary value of 1500 which will
1674 * restart after one full frame is pulled from the buffer. There
1675 * could be several smaller frames in the buffer and if so they will
1676 * not trigger the XON until their total number reduces the buffer
1678 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1680 rx_buf_size = igb_get_rx_buffer_size(hw);
1682 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1683 hw->fc.low_water = hw->fc.high_water - 1500;
1684 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1685 hw->fc.send_xon = 1;
1687 /* Set Flow control, use the tunable location if sane */
1688 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1689 hw->fc.requested_mode = igb_fc_setting;
1691 hw->fc.requested_mode = e1000_fc_none;
1693 /* Issue a global reset */
1694 igb_pf_reset_hw(hw);
1695 E1000_WRITE_REG(hw, E1000_WUC, 0);
1697 diag = e1000_init_hw(hw);
1701 E1000_WRITE_REG(hw, E1000_VET,
1702 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1703 e1000_get_phy_info(hw);
1704 e1000_check_for_link(hw);
1709 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1711 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1715 uint64_t old_gprc = stats->gprc;
1716 uint64_t old_gptc = stats->gptc;
1717 uint64_t old_tpr = stats->tpr;
1718 uint64_t old_tpt = stats->tpt;
1719 uint64_t old_rpthc = stats->rpthc;
1720 uint64_t old_hgptc = stats->hgptc;
1722 if(hw->phy.media_type == e1000_media_type_copper ||
1723 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1725 E1000_READ_REG(hw,E1000_SYMERRS);
1726 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1729 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1730 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1731 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1732 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1734 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1735 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1736 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1737 stats->dc += E1000_READ_REG(hw, E1000_DC);
1738 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1739 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1740 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1742 ** For watchdog management we need to know if we have been
1743 ** paused during the last interval, so capture that here.
1745 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1746 stats->xoffrxc += pause_frames;
1747 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1748 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1749 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1750 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1751 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1752 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1753 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1754 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1755 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1756 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1757 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1758 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1760 /* For the 64-bit byte counters the low dword must be read first. */
1761 /* Both registers clear on the read of the high dword */
1763 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1764 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1765 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1766 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1767 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1768 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1769 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1771 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1772 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1773 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1774 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1775 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1777 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1778 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1780 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1781 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1782 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1783 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1784 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1785 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1787 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1788 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1789 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1790 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1791 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1792 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1793 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1794 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1796 /* Interrupt Counts */
1798 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1799 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1800 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1801 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1802 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1803 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1804 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1805 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1806 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1808 /* Host to Card Statistics */
1810 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1811 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1812 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1813 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1814 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1815 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1816 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1817 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1818 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1819 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1820 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1821 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1822 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1823 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1824 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1825 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1827 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1828 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1829 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1830 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1831 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1832 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1836 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1838 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839 struct e1000_hw_stats *stats =
1840 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1842 igb_read_stats_registers(hw, stats);
1844 if (rte_stats == NULL)
1848 rte_stats->imissed = stats->mpc;
1849 rte_stats->ierrors = stats->crcerrs +
1850 stats->rlec + stats->ruc + stats->roc +
1851 stats->rxerrc + stats->algnerrc + stats->cexterr;
1854 rte_stats->oerrors = stats->ecol + stats->latecol;
1856 rte_stats->ipackets = stats->gprc;
1857 rte_stats->opackets = stats->gptc;
1858 rte_stats->ibytes = stats->gorc;
1859 rte_stats->obytes = stats->gotc;
1864 eth_igb_stats_reset(struct rte_eth_dev *dev)
1866 struct e1000_hw_stats *hw_stats =
1867 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1869 /* HW registers are cleared on read */
1870 eth_igb_stats_get(dev, NULL);
1872 /* Reset software totals */
1873 memset(hw_stats, 0, sizeof(*hw_stats));
1879 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1881 struct e1000_hw_stats *stats =
1882 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1884 /* HW registers are cleared on read */
1885 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1887 /* Reset software totals */
1888 memset(stats, 0, sizeof(*stats));
1893 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1894 struct rte_eth_xstat_name *xstats_names,
1895 __rte_unused unsigned int size)
1899 if (xstats_names == NULL)
1900 return IGB_NB_XSTATS;
1902 /* Note: limit checked in rte_eth_xstats_names() */
1904 for (i = 0; i < IGB_NB_XSTATS; i++) {
1905 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1906 sizeof(xstats_names[i].name));
1909 return IGB_NB_XSTATS;
1912 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1913 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1919 if (xstats_names == NULL)
1920 return IGB_NB_XSTATS;
1922 for (i = 0; i < IGB_NB_XSTATS; i++)
1923 strlcpy(xstats_names[i].name,
1924 rte_igb_stats_strings[i].name,
1925 sizeof(xstats_names[i].name));
1927 return IGB_NB_XSTATS;
1930 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1932 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1935 for (i = 0; i < limit; i++) {
1936 if (ids[i] >= IGB_NB_XSTATS) {
1937 PMD_INIT_LOG(ERR, "id value isn't valid");
1940 strcpy(xstats_names[i].name,
1941 xstats_names_copy[ids[i]].name);
1948 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1951 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952 struct e1000_hw_stats *hw_stats =
1953 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1956 if (n < IGB_NB_XSTATS)
1957 return IGB_NB_XSTATS;
1959 igb_read_stats_registers(hw, hw_stats);
1961 /* If this is a reset xstats is NULL, and we have cleared the
1962 * registers by reading them.
1967 /* Extended stats */
1968 for (i = 0; i < IGB_NB_XSTATS; i++) {
1970 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1971 rte_igb_stats_strings[i].offset);
1974 return IGB_NB_XSTATS;
1978 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1979 uint64_t *values, unsigned int n)
1984 struct e1000_hw *hw =
1985 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986 struct e1000_hw_stats *hw_stats =
1987 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1989 if (n < IGB_NB_XSTATS)
1990 return IGB_NB_XSTATS;
1992 igb_read_stats_registers(hw, hw_stats);
1994 /* If this is a reset xstats is NULL, and we have cleared the
1995 * registers by reading them.
2000 /* Extended stats */
2001 for (i = 0; i < IGB_NB_XSTATS; i++)
2002 values[i] = *(uint64_t *)(((char *)hw_stats) +
2003 rte_igb_stats_strings[i].offset);
2005 return IGB_NB_XSTATS;
2008 uint64_t values_copy[IGB_NB_XSTATS];
2010 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2013 for (i = 0; i < n; i++) {
2014 if (ids[i] >= IGB_NB_XSTATS) {
2015 PMD_INIT_LOG(ERR, "id value isn't valid");
2018 values[i] = values_copy[ids[i]];
2025 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2027 /* Good Rx packets, include VF loopback */
2028 UPDATE_VF_STAT(E1000_VFGPRC,
2029 hw_stats->last_gprc, hw_stats->gprc);
2031 /* Good Rx octets, include VF loopback */
2032 UPDATE_VF_STAT(E1000_VFGORC,
2033 hw_stats->last_gorc, hw_stats->gorc);
2035 /* Good Tx packets, include VF loopback */
2036 UPDATE_VF_STAT(E1000_VFGPTC,
2037 hw_stats->last_gptc, hw_stats->gptc);
2039 /* Good Tx octets, include VF loopback */
2040 UPDATE_VF_STAT(E1000_VFGOTC,
2041 hw_stats->last_gotc, hw_stats->gotc);
2043 /* Rx Multicst packets */
2044 UPDATE_VF_STAT(E1000_VFMPRC,
2045 hw_stats->last_mprc, hw_stats->mprc);
2047 /* Good Rx loopback packets */
2048 UPDATE_VF_STAT(E1000_VFGPRLBC,
2049 hw_stats->last_gprlbc, hw_stats->gprlbc);
2051 /* Good Rx loopback octets */
2052 UPDATE_VF_STAT(E1000_VFGORLBC,
2053 hw_stats->last_gorlbc, hw_stats->gorlbc);
2055 /* Good Tx loopback packets */
2056 UPDATE_VF_STAT(E1000_VFGPTLBC,
2057 hw_stats->last_gptlbc, hw_stats->gptlbc);
2059 /* Good Tx loopback octets */
2060 UPDATE_VF_STAT(E1000_VFGOTLBC,
2061 hw_stats->last_gotlbc, hw_stats->gotlbc);
2064 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2065 struct rte_eth_xstat_name *xstats_names,
2066 __rte_unused unsigned limit)
2070 if (xstats_names != NULL)
2071 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2072 strlcpy(xstats_names[i].name,
2073 rte_igbvf_stats_strings[i].name,
2074 sizeof(xstats_names[i].name));
2076 return IGBVF_NB_XSTATS;
2080 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2083 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2085 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2088 if (n < IGBVF_NB_XSTATS)
2089 return IGBVF_NB_XSTATS;
2091 igbvf_read_stats_registers(hw, hw_stats);
2096 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2098 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2099 rte_igbvf_stats_strings[i].offset);
2102 return IGBVF_NB_XSTATS;
2106 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2108 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2110 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2112 igbvf_read_stats_registers(hw, hw_stats);
2114 if (rte_stats == NULL)
2117 rte_stats->ipackets = hw_stats->gprc;
2118 rte_stats->ibytes = hw_stats->gorc;
2119 rte_stats->opackets = hw_stats->gptc;
2120 rte_stats->obytes = hw_stats->gotc;
2125 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2127 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2128 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2130 /* Sync HW register to the last stats */
2131 eth_igbvf_stats_get(dev, NULL);
2133 /* reset HW current stats*/
2134 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2135 offsetof(struct e1000_vf_stats, gprc));
2141 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2144 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145 struct e1000_fw_version fw;
2148 e1000_get_fw_version(hw, &fw);
2150 switch (hw->mac.type) {
2153 if (!(e1000_get_flash_presence_i210(hw))) {
2154 ret = snprintf(fw_version, fw_size,
2156 fw.invm_major, fw.invm_minor,
2162 /* if option rom is valid, display its version too */
2164 ret = snprintf(fw_version, fw_size,
2165 "%d.%d, 0x%08x, %d.%d.%d",
2166 fw.eep_major, fw.eep_minor, fw.etrack_id,
2167 fw.or_major, fw.or_build, fw.or_patch);
2170 if (fw.etrack_id != 0X0000) {
2171 ret = snprintf(fw_version, fw_size,
2173 fw.eep_major, fw.eep_minor,
2176 ret = snprintf(fw_version, fw_size,
2178 fw.eep_major, fw.eep_minor,
2185 ret += 1; /* add the size of '\0' */
2186 if (fw_size < (u32)ret)
2193 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2195 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2197 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2198 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2199 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2200 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2201 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2202 dev_info->rx_queue_offload_capa;
2203 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2204 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2205 dev_info->tx_queue_offload_capa;
2207 switch (hw->mac.type) {
2209 dev_info->max_rx_queues = 4;
2210 dev_info->max_tx_queues = 4;
2211 dev_info->max_vmdq_pools = 0;
2215 dev_info->max_rx_queues = 16;
2216 dev_info->max_tx_queues = 16;
2217 dev_info->max_vmdq_pools = ETH_8_POOLS;
2218 dev_info->vmdq_queue_num = 16;
2222 dev_info->max_rx_queues = 8;
2223 dev_info->max_tx_queues = 8;
2224 dev_info->max_vmdq_pools = ETH_8_POOLS;
2225 dev_info->vmdq_queue_num = 8;
2229 dev_info->max_rx_queues = 8;
2230 dev_info->max_tx_queues = 8;
2231 dev_info->max_vmdq_pools = ETH_8_POOLS;
2232 dev_info->vmdq_queue_num = 8;
2236 dev_info->max_rx_queues = 8;
2237 dev_info->max_tx_queues = 8;
2241 dev_info->max_rx_queues = 4;
2242 dev_info->max_tx_queues = 4;
2243 dev_info->max_vmdq_pools = 0;
2247 dev_info->max_rx_queues = 2;
2248 dev_info->max_tx_queues = 2;
2249 dev_info->max_vmdq_pools = 0;
2253 /* Should not happen */
2256 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2257 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2258 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2260 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2262 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2263 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2264 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2266 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2271 dev_info->default_txconf = (struct rte_eth_txconf) {
2273 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2274 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2275 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2280 dev_info->rx_desc_lim = rx_desc_lim;
2281 dev_info->tx_desc_lim = tx_desc_lim;
2283 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2284 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2287 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2288 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2293 static const uint32_t *
2294 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2296 static const uint32_t ptypes[] = {
2297 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2300 RTE_PTYPE_L3_IPV4_EXT,
2302 RTE_PTYPE_L3_IPV6_EXT,
2306 RTE_PTYPE_TUNNEL_IP,
2307 RTE_PTYPE_INNER_L3_IPV6,
2308 RTE_PTYPE_INNER_L3_IPV6_EXT,
2309 RTE_PTYPE_INNER_L4_TCP,
2310 RTE_PTYPE_INNER_L4_UDP,
2314 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2315 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2321 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2323 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2325 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2326 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2327 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2328 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2329 DEV_TX_OFFLOAD_IPV4_CKSUM |
2330 DEV_TX_OFFLOAD_UDP_CKSUM |
2331 DEV_TX_OFFLOAD_TCP_CKSUM |
2332 DEV_TX_OFFLOAD_SCTP_CKSUM |
2333 DEV_TX_OFFLOAD_TCP_TSO;
2334 switch (hw->mac.type) {
2336 dev_info->max_rx_queues = 2;
2337 dev_info->max_tx_queues = 2;
2339 case e1000_vfadapt_i350:
2340 dev_info->max_rx_queues = 1;
2341 dev_info->max_tx_queues = 1;
2344 /* Should not happen */
2348 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2349 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2350 dev_info->rx_queue_offload_capa;
2351 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2352 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2353 dev_info->tx_queue_offload_capa;
2355 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2357 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2358 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2359 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2361 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2366 dev_info->default_txconf = (struct rte_eth_txconf) {
2368 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2369 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2370 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2375 dev_info->rx_desc_lim = rx_desc_lim;
2376 dev_info->tx_desc_lim = tx_desc_lim;
2381 /* return 0 means link status changed, -1 means not changed */
2383 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2385 struct e1000_hw *hw =
2386 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387 struct rte_eth_link link;
2388 int link_check, count;
2391 hw->mac.get_link_status = 1;
2393 /* possible wait-to-complete in up to 9 seconds */
2394 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2395 /* Read the real link status */
2396 switch (hw->phy.media_type) {
2397 case e1000_media_type_copper:
2398 /* Do the work to read phy */
2399 e1000_check_for_link(hw);
2400 link_check = !hw->mac.get_link_status;
2403 case e1000_media_type_fiber:
2404 e1000_check_for_link(hw);
2405 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2409 case e1000_media_type_internal_serdes:
2410 e1000_check_for_link(hw);
2411 link_check = hw->mac.serdes_has_link;
2414 /* VF device is type_unknown */
2415 case e1000_media_type_unknown:
2416 eth_igbvf_link_update(hw);
2417 link_check = !hw->mac.get_link_status;
2423 if (link_check || wait_to_complete == 0)
2425 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2427 memset(&link, 0, sizeof(link));
2429 /* Now we check if a transition has happened */
2431 uint16_t duplex, speed;
2432 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2433 link.link_duplex = (duplex == FULL_DUPLEX) ?
2434 ETH_LINK_FULL_DUPLEX :
2435 ETH_LINK_HALF_DUPLEX;
2436 link.link_speed = speed;
2437 link.link_status = ETH_LINK_UP;
2438 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2439 ETH_LINK_SPEED_FIXED);
2440 } else if (!link_check) {
2441 link.link_speed = 0;
2442 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2443 link.link_status = ETH_LINK_DOWN;
2444 link.link_autoneg = ETH_LINK_FIXED;
2447 return rte_eth_linkstatus_set(dev, &link);
2451 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2452 * For ASF and Pass Through versions of f/w this means
2453 * that the driver is loaded.
2456 igb_hw_control_acquire(struct e1000_hw *hw)
2460 /* Let firmware know the driver has taken over */
2461 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2462 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2466 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2467 * For ASF and Pass Through versions of f/w this means that the
2468 * driver is no longer loaded.
2471 igb_hw_control_release(struct e1000_hw *hw)
2475 /* Let firmware taken over control of h/w */
2476 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2477 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2478 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2482 * Bit of a misnomer, what this really means is
2483 * to enable OS management of the system... aka
2484 * to disable special hardware management features.
2487 igb_init_manageability(struct e1000_hw *hw)
2489 if (e1000_enable_mng_pass_thru(hw)) {
2490 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2491 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2493 /* disable hardware interception of ARP */
2494 manc &= ~(E1000_MANC_ARP_EN);
2496 /* enable receiving management packets to the host */
2497 manc |= E1000_MANC_EN_MNG2HOST;
2498 manc2h |= 1 << 5; /* Mng Port 623 */
2499 manc2h |= 1 << 6; /* Mng Port 664 */
2500 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2501 E1000_WRITE_REG(hw, E1000_MANC, manc);
2506 igb_release_manageability(struct e1000_hw *hw)
2508 if (e1000_enable_mng_pass_thru(hw)) {
2509 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2511 manc |= E1000_MANC_ARP_EN;
2512 manc &= ~E1000_MANC_EN_MNG2HOST;
2514 E1000_WRITE_REG(hw, E1000_MANC, manc);
2519 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2521 struct e1000_hw *hw =
2522 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2525 rctl = E1000_READ_REG(hw, E1000_RCTL);
2526 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2527 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2533 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2535 struct e1000_hw *hw =
2536 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539 rctl = E1000_READ_REG(hw, E1000_RCTL);
2540 rctl &= (~E1000_RCTL_UPE);
2541 if (dev->data->all_multicast == 1)
2542 rctl |= E1000_RCTL_MPE;
2544 rctl &= (~E1000_RCTL_MPE);
2545 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2551 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2553 struct e1000_hw *hw =
2554 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2557 rctl = E1000_READ_REG(hw, E1000_RCTL);
2558 rctl |= E1000_RCTL_MPE;
2559 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2565 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2567 struct e1000_hw *hw =
2568 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2571 if (dev->data->promiscuous == 1)
2572 return 0; /* must remain in all_multicast mode */
2573 rctl = E1000_READ_REG(hw, E1000_RCTL);
2574 rctl &= (~E1000_RCTL_MPE);
2575 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2581 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2583 struct e1000_hw *hw =
2584 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585 struct e1000_vfta * shadow_vfta =
2586 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2591 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2592 E1000_VFTA_ENTRY_MASK);
2593 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2594 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2599 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2601 /* update local VFTA copy */
2602 shadow_vfta->vfta[vid_idx] = vfta;
2608 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2609 enum rte_vlan_type vlan_type,
2612 struct e1000_hw *hw =
2613 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2617 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2619 /* only outer TPID of double VLAN can be configured*/
2620 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2621 reg = E1000_READ_REG(hw, E1000_VET);
2622 reg = (reg & (~E1000_VET_VET_EXT)) |
2623 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2624 E1000_WRITE_REG(hw, E1000_VET, reg);
2629 /* all other TPID values are read-only*/
2630 PMD_DRV_LOG(ERR, "Not supported");
2636 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2638 struct e1000_hw *hw =
2639 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642 /* Filter Table Disable */
2643 reg = E1000_READ_REG(hw, E1000_RCTL);
2644 reg &= ~E1000_RCTL_CFIEN;
2645 reg &= ~E1000_RCTL_VFE;
2646 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2650 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2652 struct e1000_hw *hw =
2653 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654 struct e1000_vfta * shadow_vfta =
2655 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2659 /* Filter Table Enable, CFI not used for packet acceptance */
2660 reg = E1000_READ_REG(hw, E1000_RCTL);
2661 reg &= ~E1000_RCTL_CFIEN;
2662 reg |= E1000_RCTL_VFE;
2663 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2665 /* restore VFTA table */
2666 for (i = 0; i < IGB_VFTA_SIZE; i++)
2667 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2671 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2673 struct e1000_hw *hw =
2674 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2677 /* VLAN Mode Disable */
2678 reg = E1000_READ_REG(hw, E1000_CTRL);
2679 reg &= ~E1000_CTRL_VME;
2680 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2684 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2686 struct e1000_hw *hw =
2687 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690 /* VLAN Mode Enable */
2691 reg = E1000_READ_REG(hw, E1000_CTRL);
2692 reg |= E1000_CTRL_VME;
2693 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2697 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2699 struct e1000_hw *hw =
2700 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2703 /* CTRL_EXT: Extended VLAN */
2704 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2705 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2706 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2708 /* Update maximum packet length */
2709 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2710 E1000_WRITE_REG(hw, E1000_RLPML,
2711 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2716 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2718 struct e1000_hw *hw =
2719 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2722 /* CTRL_EXT: Extended VLAN */
2723 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2724 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2725 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2727 /* Update maximum packet length */
2728 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2729 E1000_WRITE_REG(hw, E1000_RLPML,
2730 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2735 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2737 struct rte_eth_rxmode *rxmode;
2739 rxmode = &dev->data->dev_conf.rxmode;
2740 if(mask & ETH_VLAN_STRIP_MASK){
2741 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2742 igb_vlan_hw_strip_enable(dev);
2744 igb_vlan_hw_strip_disable(dev);
2747 if(mask & ETH_VLAN_FILTER_MASK){
2748 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2749 igb_vlan_hw_filter_enable(dev);
2751 igb_vlan_hw_filter_disable(dev);
2754 if(mask & ETH_VLAN_EXTEND_MASK){
2755 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2756 igb_vlan_hw_extend_enable(dev);
2758 igb_vlan_hw_extend_disable(dev);
2766 * It enables the interrupt mask and then enable the interrupt.
2769 * Pointer to struct rte_eth_dev.
2774 * - On success, zero.
2775 * - On failure, a negative value.
2778 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2780 struct e1000_interrupt *intr =
2781 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2784 intr->mask |= E1000_ICR_LSC;
2786 intr->mask &= ~E1000_ICR_LSC;
2791 /* It clears the interrupt causes and enables the interrupt.
2792 * It will be called once only during nic initialized.
2795 * Pointer to struct rte_eth_dev.
2798 * - On success, zero.
2799 * - On failure, a negative value.
2801 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2803 uint32_t mask, regval;
2805 struct e1000_hw *hw =
2806 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2808 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2809 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2810 struct rte_eth_dev_info dev_info;
2812 memset(&dev_info, 0, sizeof(dev_info));
2813 ret = eth_igb_infos_get(dev, &dev_info);
2817 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2818 regval = E1000_READ_REG(hw, E1000_EIMS);
2819 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2825 * It reads ICR and gets interrupt causes, check it and set a bit flag
2826 * to update link status.
2829 * Pointer to struct rte_eth_dev.
2832 * - On success, zero.
2833 * - On failure, a negative value.
2836 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2839 struct e1000_hw *hw =
2840 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841 struct e1000_interrupt *intr =
2842 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2844 igb_intr_disable(dev);
2846 /* read-on-clear nic registers here */
2847 icr = E1000_READ_REG(hw, E1000_ICR);
2850 if (icr & E1000_ICR_LSC) {
2851 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2854 if (icr & E1000_ICR_VMMB)
2855 intr->flags |= E1000_FLAG_MAILBOX;
2861 * It executes link_update after knowing an interrupt is prsent.
2864 * Pointer to struct rte_eth_dev.
2867 * - On success, zero.
2868 * - On failure, a negative value.
2871 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2872 struct rte_intr_handle *intr_handle)
2874 struct e1000_hw *hw =
2875 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 struct e1000_interrupt *intr =
2877 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2878 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2879 struct rte_eth_link link;
2882 if (intr->flags & E1000_FLAG_MAILBOX) {
2883 igb_pf_mbx_process(dev);
2884 intr->flags &= ~E1000_FLAG_MAILBOX;
2887 igb_intr_enable(dev);
2888 rte_intr_ack(intr_handle);
2890 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2891 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2893 /* set get_link_status to check register later */
2894 hw->mac.get_link_status = 1;
2895 ret = eth_igb_link_update(dev, 0);
2897 /* check if link has changed */
2901 rte_eth_linkstatus_get(dev, &link);
2902 if (link.link_status) {
2904 " Port %d: Link Up - speed %u Mbps - %s",
2906 (unsigned)link.link_speed,
2907 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2908 "full-duplex" : "half-duplex");
2910 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2911 dev->data->port_id);
2914 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2915 pci_dev->addr.domain,
2917 pci_dev->addr.devid,
2918 pci_dev->addr.function);
2919 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2926 * Interrupt handler which shall be registered at first.
2929 * Pointer to interrupt handle.
2931 * The address of parameter (struct rte_eth_dev *) regsitered before.
2937 eth_igb_interrupt_handler(void *param)
2939 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2941 eth_igb_interrupt_get_status(dev);
2942 eth_igb_interrupt_action(dev, dev->intr_handle);
2946 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2949 struct e1000_hw *hw =
2950 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951 struct e1000_interrupt *intr =
2952 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2954 igbvf_intr_disable(hw);
2956 /* read-on-clear nic registers here */
2957 eicr = E1000_READ_REG(hw, E1000_EICR);
2960 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2961 intr->flags |= E1000_FLAG_MAILBOX;
2966 void igbvf_mbx_process(struct rte_eth_dev *dev)
2968 struct e1000_hw *hw =
2969 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2970 struct e1000_mbx_info *mbx = &hw->mbx;
2973 /* peek the message first */
2974 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2976 /* PF reset VF event */
2977 if (in_msg == E1000_PF_CONTROL_MSG) {
2978 /* dummy mbx read to ack pf */
2979 if (mbx->ops.read(hw, &in_msg, 1, 0))
2981 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2987 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2989 struct e1000_interrupt *intr =
2990 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2992 if (intr->flags & E1000_FLAG_MAILBOX) {
2993 igbvf_mbx_process(dev);
2994 intr->flags &= ~E1000_FLAG_MAILBOX;
2997 igbvf_intr_enable(dev);
2998 rte_intr_ack(intr_handle);
3004 eth_igbvf_interrupt_handler(void *param)
3006 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3008 eth_igbvf_interrupt_get_status(dev);
3009 eth_igbvf_interrupt_action(dev, dev->intr_handle);
3013 eth_igb_led_on(struct rte_eth_dev *dev)
3015 struct e1000_hw *hw;
3017 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3022 eth_igb_led_off(struct rte_eth_dev *dev)
3024 struct e1000_hw *hw;
3026 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3031 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3033 struct e1000_hw *hw;
3038 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039 fc_conf->pause_time = hw->fc.pause_time;
3040 fc_conf->high_water = hw->fc.high_water;
3041 fc_conf->low_water = hw->fc.low_water;
3042 fc_conf->send_xon = hw->fc.send_xon;
3043 fc_conf->autoneg = hw->mac.autoneg;
3046 * Return rx_pause and tx_pause status according to actual setting of
3047 * the TFCE and RFCE bits in the CTRL register.
3049 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3050 if (ctrl & E1000_CTRL_TFCE)
3055 if (ctrl & E1000_CTRL_RFCE)
3060 if (rx_pause && tx_pause)
3061 fc_conf->mode = RTE_FC_FULL;
3063 fc_conf->mode = RTE_FC_RX_PAUSE;
3065 fc_conf->mode = RTE_FC_TX_PAUSE;
3067 fc_conf->mode = RTE_FC_NONE;
3073 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3075 struct e1000_hw *hw;
3077 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3083 uint32_t rx_buf_size;
3084 uint32_t max_high_water;
3087 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3088 if (fc_conf->autoneg != hw->mac.autoneg)
3090 rx_buf_size = igb_get_rx_buffer_size(hw);
3091 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3093 /* At least reserve one Ethernet frame for watermark */
3094 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3095 if ((fc_conf->high_water > max_high_water) ||
3096 (fc_conf->high_water < fc_conf->low_water)) {
3097 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3098 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3102 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3103 hw->fc.pause_time = fc_conf->pause_time;
3104 hw->fc.high_water = fc_conf->high_water;
3105 hw->fc.low_water = fc_conf->low_water;
3106 hw->fc.send_xon = fc_conf->send_xon;
3108 err = e1000_setup_link_generic(hw);
3109 if (err == E1000_SUCCESS) {
3111 /* check if we want to forward MAC frames - driver doesn't have native
3112 * capability to do that, so we'll write the registers ourselves */
3114 rctl = E1000_READ_REG(hw, E1000_RCTL);
3116 /* set or clear MFLCN.PMCF bit depending on configuration */
3117 if (fc_conf->mac_ctrl_frame_fwd != 0)
3118 rctl |= E1000_RCTL_PMCF;
3120 rctl &= ~E1000_RCTL_PMCF;
3122 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3123 E1000_WRITE_FLUSH(hw);
3128 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3132 #define E1000_RAH_POOLSEL_SHIFT (18)
3134 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3135 uint32_t index, uint32_t pool)
3137 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3140 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3141 rah = E1000_READ_REG(hw, E1000_RAH(index));
3142 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3143 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3148 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3150 uint8_t addr[RTE_ETHER_ADDR_LEN];
3151 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153 memset(addr, 0, sizeof(addr));
3155 e1000_rar_set(hw, addr, index);
3159 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3160 struct rte_ether_addr *addr)
3162 eth_igb_rar_clear(dev, 0);
3163 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3168 * Virtual Function operations
3171 igbvf_intr_disable(struct e1000_hw *hw)
3173 PMD_INIT_FUNC_TRACE();
3175 /* Clear interrupt mask to stop from interrupts being generated */
3176 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3178 E1000_WRITE_FLUSH(hw);
3182 igbvf_stop_adapter(struct rte_eth_dev *dev)
3186 struct rte_eth_dev_info dev_info;
3187 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190 memset(&dev_info, 0, sizeof(dev_info));
3191 ret = eth_igbvf_infos_get(dev, &dev_info);
3195 /* Clear interrupt mask to stop from interrupts being generated */
3196 igbvf_intr_disable(hw);
3198 /* Clear any pending interrupts, flush previous writes */
3199 E1000_READ_REG(hw, E1000_EICR);
3201 /* Disable the transmit unit. Each queue must be disabled. */
3202 for (i = 0; i < dev_info.max_tx_queues; i++)
3203 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3205 /* Disable the receive unit by stopping each queue */
3206 for (i = 0; i < dev_info.max_rx_queues; i++) {
3207 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3208 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3209 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3210 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3214 /* flush all queues disables */
3215 E1000_WRITE_FLUSH(hw);
3219 static int eth_igbvf_link_update(struct e1000_hw *hw)
3221 struct e1000_mbx_info *mbx = &hw->mbx;
3222 struct e1000_mac_info *mac = &hw->mac;
3223 int ret_val = E1000_SUCCESS;
3225 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3228 * We only want to run this if there has been a rst asserted.
3229 * in this case that could mean a link change, device reset,
3230 * or a virtual function reset
3233 /* If we were hit with a reset or timeout drop the link */
3234 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3235 mac->get_link_status = TRUE;
3237 if (!mac->get_link_status)
3240 /* if link status is down no point in checking to see if pf is up */
3241 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3244 /* if we passed all the tests above then the link is up and we no
3245 * longer need to check for link */
3246 mac->get_link_status = FALSE;
3254 igbvf_dev_configure(struct rte_eth_dev *dev)
3256 struct rte_eth_conf* conf = &dev->data->dev_conf;
3258 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3259 dev->data->port_id);
3261 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3262 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3265 * VF has no ability to enable/disable HW CRC
3266 * Keep the persistent behavior the same as Host PF
3268 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3269 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3270 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3271 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3274 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3275 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3276 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3284 igbvf_dev_start(struct rte_eth_dev *dev)
3286 struct e1000_hw *hw =
3287 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288 struct e1000_adapter *adapter =
3289 E1000_DEV_PRIVATE(dev->data->dev_private);
3290 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3291 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3293 uint32_t intr_vector = 0;
3295 PMD_INIT_FUNC_TRACE();
3297 hw->mac.ops.reset_hw(hw);
3298 adapter->stopped = 0;
3301 igbvf_set_vfta_all(dev,1);
3303 eth_igbvf_tx_init(dev);
3305 /* This can fail when allocating mbufs for descriptor rings */
3306 ret = eth_igbvf_rx_init(dev);
3308 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3309 igb_dev_clear_queues(dev);
3313 /* check and configure queue intr-vector mapping */
3314 if (rte_intr_cap_multiple(intr_handle) &&
3315 dev->data->dev_conf.intr_conf.rxq) {
3316 intr_vector = dev->data->nb_rx_queues;
3317 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3322 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3323 intr_handle->intr_vec =
3324 rte_zmalloc("intr_vec",
3325 dev->data->nb_rx_queues * sizeof(int), 0);
3326 if (!intr_handle->intr_vec) {
3327 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3328 " intr_vec", dev->data->nb_rx_queues);
3333 eth_igbvf_configure_msix_intr(dev);
3335 /* enable uio/vfio intr/eventfd mapping */
3336 rte_intr_enable(intr_handle);
3338 /* resume enabled intr since hw reset */
3339 igbvf_intr_enable(dev);
3345 igbvf_dev_stop(struct rte_eth_dev *dev)
3347 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3348 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3349 struct e1000_adapter *adapter =
3350 E1000_DEV_PRIVATE(dev->data->dev_private);
3352 if (adapter->stopped)
3355 PMD_INIT_FUNC_TRACE();
3357 igbvf_stop_adapter(dev);
3360 * Clear what we set, but we still keep shadow_vfta to
3361 * restore after device starts
3363 igbvf_set_vfta_all(dev,0);
3365 igb_dev_clear_queues(dev);
3367 /* disable intr eventfd mapping */
3368 rte_intr_disable(intr_handle);
3370 /* Clean datapath event and queue/vec mapping */
3371 rte_intr_efd_disable(intr_handle);
3372 if (intr_handle->intr_vec) {
3373 rte_free(intr_handle->intr_vec);
3374 intr_handle->intr_vec = NULL;
3377 adapter->stopped = true;
3378 dev->data->dev_started = 0;
3382 igbvf_dev_close(struct rte_eth_dev *dev)
3384 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3385 struct rte_ether_addr addr;
3386 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3388 PMD_INIT_FUNC_TRACE();
3390 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3395 igbvf_dev_stop(dev);
3397 igb_dev_free_queues(dev);
3400 * reprogram the RAR with a zero mac address,
3401 * to ensure that the VF traffic goes to the PF
3402 * after stop, close and detach of the VF.
3405 memset(&addr, 0, sizeof(addr));
3406 igbvf_default_mac_addr_set(dev, &addr);
3408 dev->dev_ops = NULL;
3409 dev->rx_pkt_burst = NULL;
3410 dev->tx_pkt_burst = NULL;
3412 rte_intr_callback_unregister(&pci_dev->intr_handle,
3413 eth_igbvf_interrupt_handler,
3420 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3422 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3424 /* Set both unicast and multicast promisc */
3425 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3431 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3433 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3435 /* If in allmulticast mode leave multicast promisc */
3436 if (dev->data->all_multicast == 1)
3437 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3439 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3445 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3447 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3449 /* In promiscuous mode multicast promisc already set */
3450 if (dev->data->promiscuous == 0)
3451 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3457 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3459 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3461 /* In promiscuous mode leave multicast promisc enabled */
3462 if (dev->data->promiscuous == 0)
3463 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3468 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3470 struct e1000_mbx_info *mbx = &hw->mbx;
3474 /* After set vlan, vlan strip will also be enabled in igb driver*/
3475 msgbuf[0] = E1000_VF_SET_VLAN;
3477 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3479 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3481 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3485 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3489 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3490 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3497 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3499 struct e1000_hw *hw =
3500 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3501 struct e1000_vfta * shadow_vfta =
3502 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3503 int i = 0, j = 0, vfta = 0, mask = 1;
3505 for (i = 0; i < IGB_VFTA_SIZE; i++){
3506 vfta = shadow_vfta->vfta[i];
3509 for (j = 0; j < 32; j++){
3512 (uint16_t)((i<<5)+j), on);
3521 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3523 struct e1000_hw *hw =
3524 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3525 struct e1000_vfta * shadow_vfta =
3526 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3527 uint32_t vid_idx = 0;
3528 uint32_t vid_bit = 0;
3531 PMD_INIT_FUNC_TRACE();
3533 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3534 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3536 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3539 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3540 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3542 /*Save what we set and retore it after device reset*/
3544 shadow_vfta->vfta[vid_idx] |= vid_bit;
3546 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3552 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3554 struct e1000_hw *hw =
3555 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3557 /* index is not used by rar_set() */
3558 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3564 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3565 struct rte_eth_rss_reta_entry64 *reta_conf,
3570 uint16_t idx, shift;
3571 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3573 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3574 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3575 "(%d) doesn't match the number hardware can supported "
3576 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3580 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3581 idx = i / RTE_RETA_GROUP_SIZE;
3582 shift = i % RTE_RETA_GROUP_SIZE;
3583 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3587 if (mask == IGB_4_BIT_MASK)
3590 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3591 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3592 if (mask & (0x1 << j))
3593 reta |= reta_conf[idx].reta[shift + j] <<
3596 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3598 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3605 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3606 struct rte_eth_rss_reta_entry64 *reta_conf,
3611 uint16_t idx, shift;
3612 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3614 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3615 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3616 "(%d) doesn't match the number hardware can supported "
3617 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3621 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3622 idx = i / RTE_RETA_GROUP_SIZE;
3623 shift = i % RTE_RETA_GROUP_SIZE;
3624 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3628 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3629 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3630 if (mask & (0x1 << j))
3631 reta_conf[idx].reta[shift + j] =
3632 ((reta >> (CHAR_BIT * j)) &
3641 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3642 struct rte_eth_syn_filter *filter,
3645 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3646 struct e1000_filter_info *filter_info =
3647 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3648 uint32_t synqf, rfctl;
3650 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3653 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3656 if (synqf & E1000_SYN_FILTER_ENABLE)
3659 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3660 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3662 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3663 if (filter->hig_pri)
3664 rfctl |= E1000_RFCTL_SYNQFP;
3666 rfctl &= ~E1000_RFCTL_SYNQFP;
3668 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3670 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3675 filter_info->syn_info = synqf;
3676 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3677 E1000_WRITE_FLUSH(hw);
3682 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3683 struct rte_eth_syn_filter *filter)
3685 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3686 uint32_t synqf, rfctl;
3688 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3689 if (synqf & E1000_SYN_FILTER_ENABLE) {
3690 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3691 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3692 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3693 E1000_SYN_FILTER_QUEUE_SHIFT);
3701 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3702 enum rte_filter_op filter_op,
3705 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3708 MAC_TYPE_FILTER_SUP(hw->mac.type);
3710 if (filter_op == RTE_ETH_FILTER_NOP)
3714 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3719 switch (filter_op) {
3720 case RTE_ETH_FILTER_ADD:
3721 ret = eth_igb_syn_filter_set(dev,
3722 (struct rte_eth_syn_filter *)arg,
3725 case RTE_ETH_FILTER_DELETE:
3726 ret = eth_igb_syn_filter_set(dev,
3727 (struct rte_eth_syn_filter *)arg,
3730 case RTE_ETH_FILTER_GET:
3731 ret = eth_igb_syn_filter_get(dev,
3732 (struct rte_eth_syn_filter *)arg);
3735 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3743 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3745 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3746 struct e1000_2tuple_filter_info *filter_info)
3748 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3750 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3751 return -EINVAL; /* filter index is out of range. */
3752 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3753 return -EINVAL; /* flags is invalid. */
3755 switch (filter->dst_port_mask) {
3757 filter_info->dst_port_mask = 0;
3758 filter_info->dst_port = filter->dst_port;
3761 filter_info->dst_port_mask = 1;
3764 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3768 switch (filter->proto_mask) {
3770 filter_info->proto_mask = 0;
3771 filter_info->proto = filter->proto;
3774 filter_info->proto_mask = 1;
3777 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3781 filter_info->priority = (uint8_t)filter->priority;
3782 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3783 filter_info->tcp_flags = filter->tcp_flags;
3785 filter_info->tcp_flags = 0;
3790 static inline struct e1000_2tuple_filter *
3791 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3792 struct e1000_2tuple_filter_info *key)
3794 struct e1000_2tuple_filter *it;
3796 TAILQ_FOREACH(it, filter_list, entries) {
3797 if (memcmp(key, &it->filter_info,
3798 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3805 /* inject a igb 2tuple filter to HW */
3807 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3808 struct e1000_2tuple_filter *filter)
3810 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3812 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3816 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3817 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3818 imir |= E1000_IMIR_PORT_BP;
3820 imir &= ~E1000_IMIR_PORT_BP;
3822 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3824 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3825 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3826 ttqf |= (uint32_t)(filter->filter_info.proto &
3827 E1000_TTQF_PROTOCOL_MASK);
3828 if (filter->filter_info.proto_mask == 0)
3829 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3831 /* tcp flags bits setting. */
3832 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3833 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3834 imir_ext |= E1000_IMIREXT_CTRL_URG;
3835 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3836 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3837 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3838 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3839 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3840 imir_ext |= E1000_IMIREXT_CTRL_RST;
3841 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3842 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3843 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3844 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3846 imir_ext |= E1000_IMIREXT_CTRL_BP;
3848 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3849 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3850 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3854 * igb_add_2tuple_filter - add a 2tuple filter
3857 * dev: Pointer to struct rte_eth_dev.
3858 * ntuple_filter: ponter to the filter that will be added.
3861 * - On success, zero.
3862 * - On failure, a negative value.
3865 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3866 struct rte_eth_ntuple_filter *ntuple_filter)
3868 struct e1000_filter_info *filter_info =
3869 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3870 struct e1000_2tuple_filter *filter;
3873 filter = rte_zmalloc("e1000_2tuple_filter",
3874 sizeof(struct e1000_2tuple_filter), 0);
3878 ret = ntuple_filter_to_2tuple(ntuple_filter,
3879 &filter->filter_info);
3884 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3885 &filter->filter_info) != NULL) {
3886 PMD_DRV_LOG(ERR, "filter exists.");
3890 filter->queue = ntuple_filter->queue;
3893 * look for an unused 2tuple filter index,
3894 * and insert the filter to list.
3896 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3897 if (!(filter_info->twotuple_mask & (1 << i))) {
3898 filter_info->twotuple_mask |= 1 << i;
3900 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3906 if (i >= E1000_MAX_TTQF_FILTERS) {
3907 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3912 igb_inject_2uple_filter(dev, filter);
3917 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3918 struct e1000_2tuple_filter *filter)
3920 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921 struct e1000_filter_info *filter_info =
3922 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3924 filter_info->twotuple_mask &= ~(1 << filter->index);
3925 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3928 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3929 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3930 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3935 * igb_remove_2tuple_filter - remove a 2tuple filter
3938 * dev: Pointer to struct rte_eth_dev.
3939 * ntuple_filter: ponter to the filter that will be removed.
3942 * - On success, zero.
3943 * - On failure, a negative value.
3946 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3947 struct rte_eth_ntuple_filter *ntuple_filter)
3949 struct e1000_filter_info *filter_info =
3950 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3951 struct e1000_2tuple_filter_info filter_2tuple;
3952 struct e1000_2tuple_filter *filter;
3955 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3956 ret = ntuple_filter_to_2tuple(ntuple_filter,
3961 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3963 if (filter == NULL) {
3964 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3968 igb_delete_2tuple_filter(dev, filter);
3973 /* inject a igb flex filter to HW */
3975 igb_inject_flex_filter(struct rte_eth_dev *dev,
3976 struct e1000_flex_filter *filter)
3978 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3979 uint32_t wufc, queueing;
3983 wufc = E1000_READ_REG(hw, E1000_WUFC);
3984 if (filter->index < E1000_MAX_FHFT)
3985 reg_off = E1000_FHFT(filter->index);
3987 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3989 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3990 (E1000_WUFC_FLX0 << filter->index));
3991 queueing = filter->filter_info.len |
3992 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3993 (filter->filter_info.priority <<
3994 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3995 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3998 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3999 E1000_WRITE_REG(hw, reg_off,
4000 filter->filter_info.dwords[j]);
4001 reg_off += sizeof(uint32_t);
4002 E1000_WRITE_REG(hw, reg_off,
4003 filter->filter_info.dwords[++j]);
4004 reg_off += sizeof(uint32_t);
4005 E1000_WRITE_REG(hw, reg_off,
4006 (uint32_t)filter->filter_info.mask[i]);
4007 reg_off += sizeof(uint32_t) * 2;
4012 static inline struct e1000_flex_filter *
4013 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4014 struct e1000_flex_filter_info *key)
4016 struct e1000_flex_filter *it;
4018 TAILQ_FOREACH(it, filter_list, entries) {
4019 if (memcmp(key, &it->filter_info,
4020 sizeof(struct e1000_flex_filter_info)) == 0)
4027 /* remove a flex byte filter
4029 * dev: Pointer to struct rte_eth_dev.
4030 * filter: the pointer of the filter will be removed.
4033 igb_remove_flex_filter(struct rte_eth_dev *dev,
4034 struct e1000_flex_filter *filter)
4036 struct e1000_filter_info *filter_info =
4037 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4038 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4042 wufc = E1000_READ_REG(hw, E1000_WUFC);
4043 if (filter->index < E1000_MAX_FHFT)
4044 reg_off = E1000_FHFT(filter->index);
4046 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4048 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4049 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4051 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4052 (~(E1000_WUFC_FLX0 << filter->index)));
4054 filter_info->flex_mask &= ~(1 << filter->index);
4055 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4060 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4061 struct rte_eth_flex_filter *filter,
4064 struct e1000_filter_info *filter_info =
4065 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4066 struct e1000_flex_filter *flex_filter, *it;
4070 flex_filter = rte_zmalloc("e1000_flex_filter",
4071 sizeof(struct e1000_flex_filter), 0);
4072 if (flex_filter == NULL)
4075 flex_filter->filter_info.len = filter->len;
4076 flex_filter->filter_info.priority = filter->priority;
4077 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4078 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4080 /* reverse bits in flex filter's mask*/
4081 for (shift = 0; shift < CHAR_BIT; shift++) {
4082 if (filter->mask[i] & (0x01 << shift))
4083 mask |= (0x80 >> shift);
4085 flex_filter->filter_info.mask[i] = mask;
4088 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4089 &flex_filter->filter_info);
4090 if (it == NULL && !add) {
4091 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4092 rte_free(flex_filter);
4095 if (it != NULL && add) {
4096 PMD_DRV_LOG(ERR, "filter exists.");
4097 rte_free(flex_filter);
4102 flex_filter->queue = filter->queue;
4104 * look for an unused flex filter index
4105 * and insert the filter into the list.
4107 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4108 if (!(filter_info->flex_mask & (1 << i))) {
4109 filter_info->flex_mask |= 1 << i;
4110 flex_filter->index = i;
4111 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4117 if (i >= E1000_MAX_FLEX_FILTERS) {
4118 PMD_DRV_LOG(ERR, "flex filters are full.");
4119 rte_free(flex_filter);
4123 igb_inject_flex_filter(dev, flex_filter);
4126 igb_remove_flex_filter(dev, it);
4127 rte_free(flex_filter);
4134 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4135 struct rte_eth_flex_filter *filter)
4137 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4138 struct e1000_filter_info *filter_info =
4139 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4140 struct e1000_flex_filter flex_filter, *it;
4141 uint32_t wufc, queueing, wufc_en = 0;
4143 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4144 flex_filter.filter_info.len = filter->len;
4145 flex_filter.filter_info.priority = filter->priority;
4146 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4147 memcpy(flex_filter.filter_info.mask, filter->mask,
4148 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4150 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4151 &flex_filter.filter_info);
4153 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4157 wufc = E1000_READ_REG(hw, E1000_WUFC);
4158 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4160 if ((wufc & wufc_en) == wufc_en) {
4161 uint32_t reg_off = 0;
4162 if (it->index < E1000_MAX_FHFT)
4163 reg_off = E1000_FHFT(it->index);
4165 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4167 queueing = E1000_READ_REG(hw,
4168 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4169 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4170 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4171 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4172 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4173 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4180 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4181 enum rte_filter_op filter_op,
4184 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4185 struct rte_eth_flex_filter *filter;
4188 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4190 if (filter_op == RTE_ETH_FILTER_NOP)
4194 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4199 filter = (struct rte_eth_flex_filter *)arg;
4200 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4201 || filter->len % sizeof(uint64_t) != 0) {
4202 PMD_DRV_LOG(ERR, "filter's length is out of range");
4205 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4206 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4210 switch (filter_op) {
4211 case RTE_ETH_FILTER_ADD:
4212 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4214 case RTE_ETH_FILTER_DELETE:
4215 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4217 case RTE_ETH_FILTER_GET:
4218 ret = eth_igb_get_flex_filter(dev, filter);
4221 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4229 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4231 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4232 struct e1000_5tuple_filter_info *filter_info)
4234 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4236 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4237 return -EINVAL; /* filter index is out of range. */
4238 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4239 return -EINVAL; /* flags is invalid. */
4241 switch (filter->dst_ip_mask) {
4243 filter_info->dst_ip_mask = 0;
4244 filter_info->dst_ip = filter->dst_ip;
4247 filter_info->dst_ip_mask = 1;
4250 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4254 switch (filter->src_ip_mask) {
4256 filter_info->src_ip_mask = 0;
4257 filter_info->src_ip = filter->src_ip;
4260 filter_info->src_ip_mask = 1;
4263 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4267 switch (filter->dst_port_mask) {
4269 filter_info->dst_port_mask = 0;
4270 filter_info->dst_port = filter->dst_port;
4273 filter_info->dst_port_mask = 1;
4276 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4280 switch (filter->src_port_mask) {
4282 filter_info->src_port_mask = 0;
4283 filter_info->src_port = filter->src_port;
4286 filter_info->src_port_mask = 1;
4289 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4293 switch (filter->proto_mask) {
4295 filter_info->proto_mask = 0;
4296 filter_info->proto = filter->proto;
4299 filter_info->proto_mask = 1;
4302 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4306 filter_info->priority = (uint8_t)filter->priority;
4307 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4308 filter_info->tcp_flags = filter->tcp_flags;
4310 filter_info->tcp_flags = 0;
4315 static inline struct e1000_5tuple_filter *
4316 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4317 struct e1000_5tuple_filter_info *key)
4319 struct e1000_5tuple_filter *it;
4321 TAILQ_FOREACH(it, filter_list, entries) {
4322 if (memcmp(key, &it->filter_info,
4323 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4330 /* inject a igb 5-tuple filter to HW */
4332 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4333 struct e1000_5tuple_filter *filter)
4335 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4336 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4337 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4341 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4342 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4343 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4344 if (filter->filter_info.dst_ip_mask == 0)
4345 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4346 if (filter->filter_info.src_port_mask == 0)
4347 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4348 if (filter->filter_info.proto_mask == 0)
4349 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4350 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4351 E1000_FTQF_QUEUE_MASK;
4352 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4353 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4354 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4355 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4357 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4358 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4360 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4361 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4362 imir |= E1000_IMIR_PORT_BP;
4364 imir &= ~E1000_IMIR_PORT_BP;
4365 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4367 /* tcp flags bits setting. */
4368 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4369 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4370 imir_ext |= E1000_IMIREXT_CTRL_URG;
4371 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4372 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4373 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4374 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4375 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4376 imir_ext |= E1000_IMIREXT_CTRL_RST;
4377 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4378 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4379 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4380 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4382 imir_ext |= E1000_IMIREXT_CTRL_BP;
4384 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4385 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4389 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4392 * dev: Pointer to struct rte_eth_dev.
4393 * ntuple_filter: ponter to the filter that will be added.
4396 * - On success, zero.
4397 * - On failure, a negative value.
4400 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4401 struct rte_eth_ntuple_filter *ntuple_filter)
4403 struct e1000_filter_info *filter_info =
4404 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4405 struct e1000_5tuple_filter *filter;
4409 filter = rte_zmalloc("e1000_5tuple_filter",
4410 sizeof(struct e1000_5tuple_filter), 0);
4414 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4415 &filter->filter_info);
4421 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4422 &filter->filter_info) != NULL) {
4423 PMD_DRV_LOG(ERR, "filter exists.");
4427 filter->queue = ntuple_filter->queue;
4430 * look for an unused 5tuple filter index,
4431 * and insert the filter to list.
4433 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4434 if (!(filter_info->fivetuple_mask & (1 << i))) {
4435 filter_info->fivetuple_mask |= 1 << i;
4437 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4443 if (i >= E1000_MAX_FTQF_FILTERS) {
4444 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4449 igb_inject_5tuple_filter_82576(dev, filter);
4454 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4455 struct e1000_5tuple_filter *filter)
4457 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4458 struct e1000_filter_info *filter_info =
4459 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4461 filter_info->fivetuple_mask &= ~(1 << filter->index);
4462 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4465 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4466 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4467 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4468 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4469 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4470 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4471 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4476 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4479 * dev: Pointer to struct rte_eth_dev.
4480 * ntuple_filter: ponter to the filter that will be removed.
4483 * - On success, zero.
4484 * - On failure, a negative value.
4487 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4488 struct rte_eth_ntuple_filter *ntuple_filter)
4490 struct e1000_filter_info *filter_info =
4491 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4492 struct e1000_5tuple_filter_info filter_5tuple;
4493 struct e1000_5tuple_filter *filter;
4496 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4497 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4502 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4504 if (filter == NULL) {
4505 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4509 igb_delete_5tuple_filter_82576(dev, filter);
4515 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4518 struct e1000_hw *hw;
4519 struct rte_eth_dev_info dev_info;
4520 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4523 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4525 #ifdef RTE_LIBRTE_82571_SUPPORT
4526 /* XXX: not bigger than max_rx_pktlen */
4527 if (hw->mac.type == e1000_82571)
4530 ret = eth_igb_infos_get(dev, &dev_info);
4534 /* check that mtu is within the allowed range */
4535 if (mtu < RTE_ETHER_MIN_MTU ||
4536 frame_size > dev_info.max_rx_pktlen)
4539 /* refuse mtu that requires the support of scattered packets when this
4540 * feature has not been enabled before. */
4541 if (!dev->data->scattered_rx &&
4542 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4545 rctl = E1000_READ_REG(hw, E1000_RCTL);
4547 /* switch to jumbo mode if needed */
4548 if (frame_size > RTE_ETHER_MAX_LEN) {
4549 dev->data->dev_conf.rxmode.offloads |=
4550 DEV_RX_OFFLOAD_JUMBO_FRAME;
4551 rctl |= E1000_RCTL_LPE;
4553 dev->data->dev_conf.rxmode.offloads &=
4554 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4555 rctl &= ~E1000_RCTL_LPE;
4557 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4559 /* update max frame size */
4560 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4562 E1000_WRITE_REG(hw, E1000_RLPML,
4563 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4569 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4572 * dev: Pointer to struct rte_eth_dev.
4573 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4574 * add: if true, add filter, if false, remove filter
4577 * - On success, zero.
4578 * - On failure, a negative value.
4581 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4582 struct rte_eth_ntuple_filter *ntuple_filter,
4585 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4588 switch (ntuple_filter->flags) {
4589 case RTE_5TUPLE_FLAGS:
4590 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4591 if (hw->mac.type != e1000_82576)
4594 ret = igb_add_5tuple_filter_82576(dev,
4597 ret = igb_remove_5tuple_filter_82576(dev,
4600 case RTE_2TUPLE_FLAGS:
4601 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4602 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4603 hw->mac.type != e1000_i210 &&
4604 hw->mac.type != e1000_i211)
4607 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4609 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4620 * igb_get_ntuple_filter - get a ntuple filter
4623 * dev: Pointer to struct rte_eth_dev.
4624 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4627 * - On success, zero.
4628 * - On failure, a negative value.
4631 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4632 struct rte_eth_ntuple_filter *ntuple_filter)
4634 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635 struct e1000_filter_info *filter_info =
4636 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4637 struct e1000_5tuple_filter_info filter_5tuple;
4638 struct e1000_2tuple_filter_info filter_2tuple;
4639 struct e1000_5tuple_filter *p_5tuple_filter;
4640 struct e1000_2tuple_filter *p_2tuple_filter;
4643 switch (ntuple_filter->flags) {
4644 case RTE_5TUPLE_FLAGS:
4645 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4646 if (hw->mac.type != e1000_82576)
4648 memset(&filter_5tuple,
4650 sizeof(struct e1000_5tuple_filter_info));
4651 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4655 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4656 &filter_info->fivetuple_list,
4658 if (p_5tuple_filter == NULL) {
4659 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4662 ntuple_filter->queue = p_5tuple_filter->queue;
4664 case RTE_2TUPLE_FLAGS:
4665 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4666 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4668 memset(&filter_2tuple,
4670 sizeof(struct e1000_2tuple_filter_info));
4671 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4674 p_2tuple_filter = igb_2tuple_filter_lookup(
4675 &filter_info->twotuple_list,
4677 if (p_2tuple_filter == NULL) {
4678 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4681 ntuple_filter->queue = p_2tuple_filter->queue;
4692 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4693 * @dev: pointer to rte_eth_dev structure
4694 * @filter_op:operation will be taken.
4695 * @arg: a pointer to specific structure corresponding to the filter_op
4698 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4699 enum rte_filter_op filter_op,
4702 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4705 MAC_TYPE_FILTER_SUP(hw->mac.type);
4707 if (filter_op == RTE_ETH_FILTER_NOP)
4711 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4716 switch (filter_op) {
4717 case RTE_ETH_FILTER_ADD:
4718 ret = igb_add_del_ntuple_filter(dev,
4719 (struct rte_eth_ntuple_filter *)arg,
4722 case RTE_ETH_FILTER_DELETE:
4723 ret = igb_add_del_ntuple_filter(dev,
4724 (struct rte_eth_ntuple_filter *)arg,
4727 case RTE_ETH_FILTER_GET:
4728 ret = igb_get_ntuple_filter(dev,
4729 (struct rte_eth_ntuple_filter *)arg);
4732 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4740 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4745 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4746 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4747 (filter_info->ethertype_mask & (1 << i)))
4754 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4755 uint16_t ethertype, uint32_t etqf)
4759 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4760 if (!(filter_info->ethertype_mask & (1 << i))) {
4761 filter_info->ethertype_mask |= 1 << i;
4762 filter_info->ethertype_filters[i].ethertype = ethertype;
4763 filter_info->ethertype_filters[i].etqf = etqf;
4771 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4774 if (idx >= E1000_MAX_ETQF_FILTERS)
4776 filter_info->ethertype_mask &= ~(1 << idx);
4777 filter_info->ethertype_filters[idx].ethertype = 0;
4778 filter_info->ethertype_filters[idx].etqf = 0;
4784 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4785 struct rte_eth_ethertype_filter *filter,
4788 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789 struct e1000_filter_info *filter_info =
4790 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4794 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4795 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4796 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4797 " ethertype filter.", filter->ether_type);
4801 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4802 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4805 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4806 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4810 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4811 if (ret >= 0 && add) {
4812 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4813 filter->ether_type);
4816 if (ret < 0 && !add) {
4817 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4818 filter->ether_type);
4823 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4824 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4825 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4826 ret = igb_ethertype_filter_insert(filter_info,
4827 filter->ether_type, etqf);
4829 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4833 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4837 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4838 E1000_WRITE_FLUSH(hw);
4844 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4845 struct rte_eth_ethertype_filter *filter)
4847 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4848 struct e1000_filter_info *filter_info =
4849 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4853 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4855 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4856 filter->ether_type);
4860 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4861 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4862 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4864 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4865 E1000_ETQF_QUEUE_SHIFT;
4873 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4874 * @dev: pointer to rte_eth_dev structure
4875 * @filter_op:operation will be taken.
4876 * @arg: a pointer to specific structure corresponding to the filter_op
4879 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4880 enum rte_filter_op filter_op,
4883 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886 MAC_TYPE_FILTER_SUP(hw->mac.type);
4888 if (filter_op == RTE_ETH_FILTER_NOP)
4892 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4897 switch (filter_op) {
4898 case RTE_ETH_FILTER_ADD:
4899 ret = igb_add_del_ethertype_filter(dev,
4900 (struct rte_eth_ethertype_filter *)arg,
4903 case RTE_ETH_FILTER_DELETE:
4904 ret = igb_add_del_ethertype_filter(dev,
4905 (struct rte_eth_ethertype_filter *)arg,
4908 case RTE_ETH_FILTER_GET:
4909 ret = igb_get_ethertype_filter(dev,
4910 (struct rte_eth_ethertype_filter *)arg);
4913 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4921 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4922 enum rte_filter_type filter_type,
4923 enum rte_filter_op filter_op,
4928 switch (filter_type) {
4929 case RTE_ETH_FILTER_NTUPLE:
4930 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4932 case RTE_ETH_FILTER_ETHERTYPE:
4933 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4935 case RTE_ETH_FILTER_SYN:
4936 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4938 case RTE_ETH_FILTER_FLEXIBLE:
4939 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4941 case RTE_ETH_FILTER_GENERIC:
4942 if (filter_op != RTE_ETH_FILTER_GET)
4944 *(const void **)arg = &igb_flow_ops;
4947 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4956 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4957 struct rte_ether_addr *mc_addr_set,
4958 uint32_t nb_mc_addr)
4960 struct e1000_hw *hw;
4962 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4963 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4968 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4970 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4971 uint64_t systime_cycles;
4973 switch (hw->mac.type) {
4977 * Need to read System Time Residue Register to be able
4978 * to read the other two registers.
4980 E1000_READ_REG(hw, E1000_SYSTIMR);
4981 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4982 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4983 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4990 * Need to read System Time Residue Register to be able
4991 * to read the other two registers.
4993 E1000_READ_REG(hw, E1000_SYSTIMR);
4994 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4995 /* Only the 8 LSB are valid. */
4996 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
5000 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
5001 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
5006 return systime_cycles;
5010 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5012 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5013 uint64_t rx_tstamp_cycles;
5015 switch (hw->mac.type) {
5018 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5019 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5020 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5026 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5027 /* Only the 8 LSB are valid. */
5028 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5032 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5033 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5038 return rx_tstamp_cycles;
5042 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5044 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045 uint64_t tx_tstamp_cycles;
5047 switch (hw->mac.type) {
5050 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5051 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5052 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5058 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5059 /* Only the 8 LSB are valid. */
5060 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5064 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5065 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5070 return tx_tstamp_cycles;
5074 igb_start_timecounters(struct rte_eth_dev *dev)
5076 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5077 struct e1000_adapter *adapter = dev->data->dev_private;
5078 uint32_t incval = 1;
5080 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5082 switch (hw->mac.type) {
5086 /* 32 LSB bits + 8 MSB bits = 40 bits */
5087 mask = (1ULL << 40) - 1;
5092 * Start incrementing the register
5093 * used to timestamp PTP packets.
5095 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5098 incval = E1000_INCVALUE_82576;
5099 shift = IGB_82576_TSYNC_SHIFT;
5100 E1000_WRITE_REG(hw, E1000_TIMINCA,
5101 E1000_INCPERIOD_82576 | incval);
5108 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5109 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5110 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5112 adapter->systime_tc.cc_mask = mask;
5113 adapter->systime_tc.cc_shift = shift;
5114 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5116 adapter->rx_tstamp_tc.cc_mask = mask;
5117 adapter->rx_tstamp_tc.cc_shift = shift;
5118 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5120 adapter->tx_tstamp_tc.cc_mask = mask;
5121 adapter->tx_tstamp_tc.cc_shift = shift;
5122 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5126 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5128 struct e1000_adapter *adapter = dev->data->dev_private;
5130 adapter->systime_tc.nsec += delta;
5131 adapter->rx_tstamp_tc.nsec += delta;
5132 adapter->tx_tstamp_tc.nsec += delta;
5138 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5141 struct e1000_adapter *adapter = dev->data->dev_private;
5143 ns = rte_timespec_to_ns(ts);
5145 /* Set the timecounters to a new value. */
5146 adapter->systime_tc.nsec = ns;
5147 adapter->rx_tstamp_tc.nsec = ns;
5148 adapter->tx_tstamp_tc.nsec = ns;
5154 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5156 uint64_t ns, systime_cycles;
5157 struct e1000_adapter *adapter = dev->data->dev_private;
5159 systime_cycles = igb_read_systime_cyclecounter(dev);
5160 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5161 *ts = rte_ns_to_timespec(ns);
5167 igb_timesync_enable(struct rte_eth_dev *dev)
5169 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5173 /* Stop the timesync system time. */
5174 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5175 /* Reset the timesync system time value. */
5176 switch (hw->mac.type) {
5182 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5185 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5186 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5189 /* Not supported. */
5193 /* Enable system time for it isn't on by default. */
5194 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5195 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5196 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5198 igb_start_timecounters(dev);
5200 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5201 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5202 (RTE_ETHER_TYPE_1588 |
5203 E1000_ETQF_FILTER_ENABLE |
5206 /* Enable timestamping of received PTP packets. */
5207 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5208 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5209 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5211 /* Enable Timestamping of transmitted PTP packets. */
5212 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5213 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5214 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5220 igb_timesync_disable(struct rte_eth_dev *dev)
5222 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225 /* Disable timestamping of transmitted PTP packets. */
5226 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5227 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5228 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5230 /* Disable timestamping of received PTP packets. */
5231 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5232 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5233 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5235 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5236 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5238 /* Stop incrementating the System Time registers. */
5239 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5245 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5246 struct timespec *timestamp,
5247 uint32_t flags __rte_unused)
5249 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5250 struct e1000_adapter *adapter = dev->data->dev_private;
5251 uint32_t tsync_rxctl;
5252 uint64_t rx_tstamp_cycles;
5255 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5256 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5259 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5260 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5261 *timestamp = rte_ns_to_timespec(ns);
5267 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5268 struct timespec *timestamp)
5270 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5271 struct e1000_adapter *adapter = dev->data->dev_private;
5272 uint32_t tsync_txctl;
5273 uint64_t tx_tstamp_cycles;
5276 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5277 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5280 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5281 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5282 *timestamp = rte_ns_to_timespec(ns);
5288 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5292 const struct reg_info *reg_group;
5294 while ((reg_group = igb_regs[g_ind++]))
5295 count += igb_reg_group_count(reg_group);
5301 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5305 const struct reg_info *reg_group;
5307 while ((reg_group = igbvf_regs[g_ind++]))
5308 count += igb_reg_group_count(reg_group);
5314 eth_igb_get_regs(struct rte_eth_dev *dev,
5315 struct rte_dev_reg_info *regs)
5317 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5318 uint32_t *data = regs->data;
5321 const struct reg_info *reg_group;
5324 regs->length = eth_igb_get_reg_length(dev);
5325 regs->width = sizeof(uint32_t);
5329 /* Support only full register dump */
5330 if ((regs->length == 0) ||
5331 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5332 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5334 while ((reg_group = igb_regs[g_ind++]))
5335 count += igb_read_regs_group(dev, &data[count],
5344 igbvf_get_regs(struct rte_eth_dev *dev,
5345 struct rte_dev_reg_info *regs)
5347 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5348 uint32_t *data = regs->data;
5351 const struct reg_info *reg_group;
5354 regs->length = igbvf_get_reg_length(dev);
5355 regs->width = sizeof(uint32_t);
5359 /* Support only full register dump */
5360 if ((regs->length == 0) ||
5361 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5362 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5364 while ((reg_group = igbvf_regs[g_ind++]))
5365 count += igb_read_regs_group(dev, &data[count],
5374 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5376 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5378 /* Return unit is byte count */
5379 return hw->nvm.word_size * 2;
5383 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5384 struct rte_dev_eeprom_info *in_eeprom)
5386 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5387 struct e1000_nvm_info *nvm = &hw->nvm;
5388 uint16_t *data = in_eeprom->data;
5391 first = in_eeprom->offset >> 1;
5392 length = in_eeprom->length >> 1;
5393 if ((first >= hw->nvm.word_size) ||
5394 ((first + length) >= hw->nvm.word_size))
5397 in_eeprom->magic = hw->vendor_id |
5398 ((uint32_t)hw->device_id << 16);
5400 if ((nvm->ops.read) == NULL)
5403 return nvm->ops.read(hw, first, length, data);
5407 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5408 struct rte_dev_eeprom_info *in_eeprom)
5410 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5411 struct e1000_nvm_info *nvm = &hw->nvm;
5412 uint16_t *data = in_eeprom->data;
5415 first = in_eeprom->offset >> 1;
5416 length = in_eeprom->length >> 1;
5417 if ((first >= hw->nvm.word_size) ||
5418 ((first + length) >= hw->nvm.word_size))
5421 in_eeprom->magic = (uint32_t)hw->vendor_id |
5422 ((uint32_t)hw->device_id << 16);
5424 if ((nvm->ops.write) == NULL)
5426 return nvm->ops.write(hw, first, length, data);
5430 eth_igb_get_module_info(struct rte_eth_dev *dev,
5431 struct rte_eth_dev_module_info *modinfo)
5433 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5435 uint32_t status = 0;
5436 uint16_t sff8472_rev, addr_mode;
5437 bool page_swap = false;
5439 if (hw->phy.media_type == e1000_media_type_copper ||
5440 hw->phy.media_type == e1000_media_type_unknown)
5443 /* Check whether we support SFF-8472 or not */
5444 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5448 /* addressing mode is not supported */
5449 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5453 /* addressing mode is not supported */
5454 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5456 "Address change required to access page 0xA2, "
5457 "but not supported. Please report the module "
5458 "type to the driver maintainers.\n");
5462 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5463 /* We have an SFP, but it does not support SFF-8472 */
5464 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5465 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5467 /* We have an SFP which supports a revision of SFF-8472 */
5468 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5469 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5476 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5477 struct rte_dev_eeprom_info *info)
5479 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5481 uint32_t status = 0;
5482 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5483 u16 first_word, last_word;
5486 if (info->length == 0)
5489 first_word = info->offset >> 1;
5490 last_word = (info->offset + info->length - 1) >> 1;
5492 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5493 for (i = 0; i < last_word - first_word + 1; i++) {
5494 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5497 /* Error occurred while reading module */
5501 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5504 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5510 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5512 struct e1000_hw *hw =
5513 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5514 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5515 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5516 uint32_t vec = E1000_MISC_VEC_ID;
5518 if (rte_intr_allow_others(intr_handle))
5519 vec = E1000_RX_VEC_START;
5521 uint32_t mask = 1 << (queue_id + vec);
5523 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5524 E1000_WRITE_FLUSH(hw);
5530 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5532 struct e1000_hw *hw =
5533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5535 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5536 uint32_t vec = E1000_MISC_VEC_ID;
5538 if (rte_intr_allow_others(intr_handle))
5539 vec = E1000_RX_VEC_START;
5541 uint32_t mask = 1 << (queue_id + vec);
5544 regval = E1000_READ_REG(hw, E1000_EIMS);
5545 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5546 E1000_WRITE_FLUSH(hw);
5548 rte_intr_ack(intr_handle);
5554 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5555 uint8_t index, uint8_t offset)
5557 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5560 val &= ~((uint32_t)0xFF << offset);
5562 /* write vector and valid bit */
5563 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5565 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5569 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5570 uint8_t queue, uint8_t msix_vector)
5574 if (hw->mac.type == e1000_82575) {
5576 tmp = E1000_EICR_RX_QUEUE0 << queue;
5577 else if (direction == 1)
5578 tmp = E1000_EICR_TX_QUEUE0 << queue;
5579 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5580 } else if (hw->mac.type == e1000_82576) {
5581 if ((direction == 0) || (direction == 1))
5582 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5583 ((queue & 0x8) << 1) +
5585 } else if ((hw->mac.type == e1000_82580) ||
5586 (hw->mac.type == e1000_i350) ||
5587 (hw->mac.type == e1000_i354) ||
5588 (hw->mac.type == e1000_i210) ||
5589 (hw->mac.type == e1000_i211)) {
5590 if ((direction == 0) || (direction == 1))
5591 eth_igb_write_ivar(hw, msix_vector,
5593 ((queue & 0x1) << 4) +
5598 /* Sets up the hardware to generate MSI-X interrupts properly
5600 * board private structure
5603 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5606 uint32_t tmpval, regval, intr_mask;
5607 struct e1000_hw *hw =
5608 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5609 uint32_t vec = E1000_MISC_VEC_ID;
5610 uint32_t base = E1000_MISC_VEC_ID;
5611 uint32_t misc_shift = 0;
5612 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5613 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5615 /* won't configure msix register if no mapping is done
5616 * between intr vector and event fd
5618 if (!rte_intr_dp_is_en(intr_handle))
5621 if (rte_intr_allow_others(intr_handle)) {
5622 vec = base = E1000_RX_VEC_START;
5626 /* set interrupt vector for other causes */
5627 if (hw->mac.type == e1000_82575) {
5628 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5629 /* enable MSI-X PBA support */
5630 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5632 /* Auto-Mask interrupts upon ICR read */
5633 tmpval |= E1000_CTRL_EXT_EIAME;
5634 tmpval |= E1000_CTRL_EXT_IRCA;
5636 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5638 /* enable msix_other interrupt */
5639 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5640 regval = E1000_READ_REG(hw, E1000_EIAC);
5641 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5642 regval = E1000_READ_REG(hw, E1000_EIAM);
5643 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5644 } else if ((hw->mac.type == e1000_82576) ||
5645 (hw->mac.type == e1000_82580) ||
5646 (hw->mac.type == e1000_i350) ||
5647 (hw->mac.type == e1000_i354) ||
5648 (hw->mac.type == e1000_i210) ||
5649 (hw->mac.type == e1000_i211)) {
5650 /* turn on MSI-X capability first */
5651 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5652 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5654 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5657 if (dev->data->dev_conf.intr_conf.lsc != 0)
5658 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5660 regval = E1000_READ_REG(hw, E1000_EIAC);
5661 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5663 /* enable msix_other interrupt */
5664 regval = E1000_READ_REG(hw, E1000_EIMS);
5665 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5666 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5667 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5670 /* use EIAM to auto-mask when MSI-X interrupt
5671 * is asserted, this saves a register write for every interrupt
5673 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5676 if (dev->data->dev_conf.intr_conf.lsc != 0)
5677 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5679 regval = E1000_READ_REG(hw, E1000_EIAM);
5680 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5682 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5683 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5684 intr_handle->intr_vec[queue_id] = vec;
5685 if (vec < base + intr_handle->nb_efd - 1)
5689 E1000_WRITE_FLUSH(hw);
5692 /* restore n-tuple filter */
5694 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5696 struct e1000_filter_info *filter_info =
5697 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5698 struct e1000_5tuple_filter *p_5tuple;
5699 struct e1000_2tuple_filter *p_2tuple;
5701 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5702 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5705 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5706 igb_inject_2uple_filter(dev, p_2tuple);
5710 /* restore SYN filter */
5712 igb_syn_filter_restore(struct rte_eth_dev *dev)
5714 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5715 struct e1000_filter_info *filter_info =
5716 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5719 synqf = filter_info->syn_info;
5721 if (synqf & E1000_SYN_FILTER_ENABLE) {
5722 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5723 E1000_WRITE_FLUSH(hw);
5727 /* restore ethernet type filter */
5729 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5731 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5732 struct e1000_filter_info *filter_info =
5733 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5736 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5737 if (filter_info->ethertype_mask & (1 << i)) {
5738 E1000_WRITE_REG(hw, E1000_ETQF(i),
5739 filter_info->ethertype_filters[i].etqf);
5740 E1000_WRITE_FLUSH(hw);
5745 /* restore flex byte filter */
5747 igb_flex_filter_restore(struct rte_eth_dev *dev)
5749 struct e1000_filter_info *filter_info =
5750 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5751 struct e1000_flex_filter *flex_filter;
5753 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5754 igb_inject_flex_filter(dev, flex_filter);
5758 /* restore rss filter */
5760 igb_rss_filter_restore(struct rte_eth_dev *dev)
5762 struct e1000_filter_info *filter_info =
5763 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5765 if (filter_info->rss_info.conf.queue_num)
5766 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5769 /* restore all types filter */
5771 igb_filter_restore(struct rte_eth_dev *dev)
5773 igb_ntuple_filter_restore(dev);
5774 igb_ethertype_filter_restore(dev);
5775 igb_syn_filter_restore(dev);
5776 igb_flex_filter_restore(dev);
5777 igb_rss_filter_restore(dev);
5782 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5783 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5784 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5785 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5786 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5787 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5789 /* see e1000_logs.c */
5790 RTE_INIT(e1000_init_log)
5792 e1000_igb_init_log();