1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static void eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static void eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
158 static void igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
190 struct rte_eth_syn_filter *filter);
191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
192 enum rte_filter_op filter_op,
194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
197 struct rte_eth_ntuple_filter *ntuple_filter);
198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
199 struct rte_eth_flex_filter *filter);
200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
201 enum rte_filter_op filter_op,
203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
204 struct rte_eth_ntuple_filter *ntuple_filter);
205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
206 struct rte_eth_ntuple_filter *ntuple_filter);
207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
208 struct rte_eth_ntuple_filter *filter);
209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
210 enum rte_filter_op filter_op,
212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ethertype_filter *filter);
217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
218 enum rte_filter_type filter_type,
219 enum rte_filter_op filter_op,
221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
223 struct rte_dev_reg_info *regs);
224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
226 struct rte_dev_eeprom_info *eeprom);
227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
228 struct rte_dev_eeprom_info *eeprom);
229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
230 struct rte_eth_dev_module_info *modinfo);
231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
232 struct rte_dev_eeprom_info *info);
233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
234 struct rte_ether_addr *mc_addr_set,
235 uint32_t nb_mc_addr);
236 static int igb_timesync_enable(struct rte_eth_dev *dev);
237 static int igb_timesync_disable(struct rte_eth_dev *dev);
238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
239 struct timespec *timestamp,
241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
242 struct timespec *timestamp);
243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
245 struct timespec *timestamp);
246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
247 const struct timespec *timestamp);
248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
253 uint8_t queue, uint8_t msix_vector);
254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
255 uint8_t index, uint8_t offset);
256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
257 static void eth_igbvf_interrupt_handler(void *param);
258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
259 static int igb_filter_restore(struct rte_eth_dev *dev);
262 * Define VF Stats MACRO for Non "cleared on read" register
264 #define UPDATE_VF_STAT(reg, last, cur) \
266 u32 latest = E1000_READ_REG(hw, reg); \
267 cur += (latest - last) & UINT_MAX; \
271 #define IGB_FC_PAUSE_TIME 0x0680
272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
275 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
280 * The set of PCI devices this driver supports
282 static const struct rte_pci_id pci_id_igb_map[] = {
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
324 { .vendor_id = 0, /* sentinel */ },
328 * The set of PCI devices this driver supports (for 82576&I350 VF)
330 static const struct rte_pci_id pci_id_igbvf_map[] = {
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
335 { .vendor_id = 0, /* sentinel */ },
338 static const struct rte_eth_desc_lim rx_desc_lim = {
339 .nb_max = E1000_MAX_RING_DESC,
340 .nb_min = E1000_MIN_RING_DESC,
341 .nb_align = IGB_RXD_ALIGN,
344 static const struct rte_eth_desc_lim tx_desc_lim = {
345 .nb_max = E1000_MAX_RING_DESC,
346 .nb_min = E1000_MIN_RING_DESC,
347 .nb_align = IGB_RXD_ALIGN,
348 .nb_seg_max = IGB_TX_MAX_SEG,
349 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
352 static const struct eth_dev_ops eth_igb_ops = {
353 .dev_configure = eth_igb_configure,
354 .dev_start = eth_igb_start,
355 .dev_stop = eth_igb_stop,
356 .dev_set_link_up = eth_igb_dev_set_link_up,
357 .dev_set_link_down = eth_igb_dev_set_link_down,
358 .dev_close = eth_igb_close,
359 .dev_reset = eth_igb_reset,
360 .promiscuous_enable = eth_igb_promiscuous_enable,
361 .promiscuous_disable = eth_igb_promiscuous_disable,
362 .allmulticast_enable = eth_igb_allmulticast_enable,
363 .allmulticast_disable = eth_igb_allmulticast_disable,
364 .link_update = eth_igb_link_update,
365 .stats_get = eth_igb_stats_get,
366 .xstats_get = eth_igb_xstats_get,
367 .xstats_get_by_id = eth_igb_xstats_get_by_id,
368 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
369 .xstats_get_names = eth_igb_xstats_get_names,
370 .stats_reset = eth_igb_stats_reset,
371 .xstats_reset = eth_igb_xstats_reset,
372 .fw_version_get = eth_igb_fw_version_get,
373 .dev_infos_get = eth_igb_infos_get,
374 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
375 .mtu_set = eth_igb_mtu_set,
376 .vlan_filter_set = eth_igb_vlan_filter_set,
377 .vlan_tpid_set = eth_igb_vlan_tpid_set,
378 .vlan_offload_set = eth_igb_vlan_offload_set,
379 .rx_queue_setup = eth_igb_rx_queue_setup,
380 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
381 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
382 .rx_queue_release = eth_igb_rx_queue_release,
383 .rx_queue_count = eth_igb_rx_queue_count,
384 .rx_descriptor_done = eth_igb_rx_descriptor_done,
385 .rx_descriptor_status = eth_igb_rx_descriptor_status,
386 .tx_descriptor_status = eth_igb_tx_descriptor_status,
387 .tx_queue_setup = eth_igb_tx_queue_setup,
388 .tx_queue_release = eth_igb_tx_queue_release,
389 .tx_done_cleanup = eth_igb_tx_done_cleanup,
390 .dev_led_on = eth_igb_led_on,
391 .dev_led_off = eth_igb_led_off,
392 .flow_ctrl_get = eth_igb_flow_ctrl_get,
393 .flow_ctrl_set = eth_igb_flow_ctrl_set,
394 .mac_addr_add = eth_igb_rar_set,
395 .mac_addr_remove = eth_igb_rar_clear,
396 .mac_addr_set = eth_igb_default_mac_addr_set,
397 .reta_update = eth_igb_rss_reta_update,
398 .reta_query = eth_igb_rss_reta_query,
399 .rss_hash_update = eth_igb_rss_hash_update,
400 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
401 .filter_ctrl = eth_igb_filter_ctrl,
402 .set_mc_addr_list = eth_igb_set_mc_addr_list,
403 .rxq_info_get = igb_rxq_info_get,
404 .txq_info_get = igb_txq_info_get,
405 .timesync_enable = igb_timesync_enable,
406 .timesync_disable = igb_timesync_disable,
407 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
408 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
409 .get_reg = eth_igb_get_regs,
410 .get_eeprom_length = eth_igb_get_eeprom_length,
411 .get_eeprom = eth_igb_get_eeprom,
412 .set_eeprom = eth_igb_set_eeprom,
413 .get_module_info = eth_igb_get_module_info,
414 .get_module_eeprom = eth_igb_get_module_eeprom,
415 .timesync_adjust_time = igb_timesync_adjust_time,
416 .timesync_read_time = igb_timesync_read_time,
417 .timesync_write_time = igb_timesync_write_time,
421 * dev_ops for virtual function, bare necessities for basic vf
422 * operation have been implemented
424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
425 .dev_configure = igbvf_dev_configure,
426 .dev_start = igbvf_dev_start,
427 .dev_stop = igbvf_dev_stop,
428 .dev_close = igbvf_dev_close,
429 .promiscuous_enable = igbvf_promiscuous_enable,
430 .promiscuous_disable = igbvf_promiscuous_disable,
431 .allmulticast_enable = igbvf_allmulticast_enable,
432 .allmulticast_disable = igbvf_allmulticast_disable,
433 .link_update = eth_igb_link_update,
434 .stats_get = eth_igbvf_stats_get,
435 .xstats_get = eth_igbvf_xstats_get,
436 .xstats_get_names = eth_igbvf_xstats_get_names,
437 .stats_reset = eth_igbvf_stats_reset,
438 .xstats_reset = eth_igbvf_stats_reset,
439 .vlan_filter_set = igbvf_vlan_filter_set,
440 .dev_infos_get = eth_igbvf_infos_get,
441 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
442 .rx_queue_setup = eth_igb_rx_queue_setup,
443 .rx_queue_release = eth_igb_rx_queue_release,
444 .rx_descriptor_done = eth_igb_rx_descriptor_done,
445 .rx_descriptor_status = eth_igb_rx_descriptor_status,
446 .tx_descriptor_status = eth_igb_tx_descriptor_status,
447 .tx_queue_setup = eth_igb_tx_queue_setup,
448 .tx_queue_release = eth_igb_tx_queue_release,
449 .set_mc_addr_list = eth_igb_set_mc_addr_list,
450 .rxq_info_get = igb_rxq_info_get,
451 .txq_info_get = igb_txq_info_get,
452 .mac_addr_set = igbvf_default_mac_addr_set,
453 .get_reg = igbvf_get_regs,
456 /* store statistics names and its offset in stats structure */
457 struct rte_igb_xstats_name_off {
458 char name[RTE_ETH_XSTATS_NAME_SIZE];
462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
463 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
464 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
465 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
466 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
467 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
468 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
469 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
471 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
472 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
473 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
474 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
475 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
476 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
477 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
478 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
479 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
480 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
481 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
483 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
484 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
485 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
486 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
487 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
489 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
491 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
492 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
493 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
494 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
495 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
496 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
497 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
498 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
499 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
500 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
501 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
502 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
503 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
504 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
505 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
506 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
507 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
508 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
510 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
512 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
513 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
514 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
515 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
516 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
517 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
518 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
520 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
524 sizeof(rte_igb_stats_strings[0]))
526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
527 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
528 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
529 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
530 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
531 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
535 sizeof(rte_igbvf_stats_strings[0]))
539 igb_intr_enable(struct rte_eth_dev *dev)
541 struct e1000_interrupt *intr =
542 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
543 struct e1000_hw *hw =
544 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
545 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
546 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
548 if (rte_intr_allow_others(intr_handle) &&
549 dev->data->dev_conf.intr_conf.lsc != 0) {
550 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
553 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
554 E1000_WRITE_FLUSH(hw);
558 igb_intr_disable(struct rte_eth_dev *dev)
560 struct e1000_hw *hw =
561 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
565 if (rte_intr_allow_others(intr_handle) &&
566 dev->data->dev_conf.intr_conf.lsc != 0) {
567 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
570 E1000_WRITE_REG(hw, E1000_IMC, ~0);
571 E1000_WRITE_FLUSH(hw);
575 igbvf_intr_enable(struct rte_eth_dev *dev)
577 struct e1000_hw *hw =
578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
580 /* only for mailbox */
581 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
582 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
583 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
584 E1000_WRITE_FLUSH(hw);
587 /* only for mailbox now. If RX/TX needed, should extend this function. */
589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
594 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
595 tmp |= E1000_VTIVAR_VALID;
596 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
602 struct e1000_hw *hw =
603 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 /* Configure VF other cause ivar */
606 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
609 static inline int32_t
610 igb_pf_reset_hw(struct e1000_hw *hw)
615 status = e1000_reset_hw(hw);
617 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
618 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
619 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
620 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
621 E1000_WRITE_FLUSH(hw);
627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
629 struct e1000_hw *hw =
630 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 hw->vendor_id = pci_dev->id.vendor_id;
634 hw->device_id = pci_dev->id.device_id;
635 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
636 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
638 e1000_set_mac_type(hw);
640 /* need to check if it is a vf device below */
644 igb_reset_swfw_lock(struct e1000_hw *hw)
649 * Do mac ops initialization manually here, since we will need
650 * some function pointers set by this call.
652 ret_val = e1000_init_mac_params(hw);
657 * SMBI lock should not fail in this early stage. If this is the case,
658 * it is due to an improper exit of the application.
659 * So force the release of the faulty lock.
661 if (e1000_get_hw_semaphore_generic(hw) < 0) {
662 PMD_DRV_LOG(DEBUG, "SMBI lock released");
664 e1000_put_hw_semaphore_generic(hw);
666 if (hw->mac.ops.acquire_swfw_sync != NULL) {
670 * Phy lock should not fail in this early stage. If this is the case,
671 * it is due to an improper exit of the application.
672 * So force the release of the faulty lock.
674 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
675 if (hw->bus.func > E1000_FUNC_1)
677 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
678 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
681 hw->mac.ops.release_swfw_sync(hw, mask);
684 * This one is more tricky since it is common to all ports; but
685 * swfw_sync retries last long enough (1s) to be almost sure that if
686 * lock can not be taken it is due to an improper lock of the
689 mask = E1000_SWFW_EEP_SM;
690 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
691 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
693 hw->mac.ops.release_swfw_sync(hw, mask);
696 return E1000_SUCCESS;
699 /* Remove all ntuple filters of the device */
700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
702 struct e1000_filter_info *filter_info =
703 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
704 struct e1000_5tuple_filter *p_5tuple;
705 struct e1000_2tuple_filter *p_2tuple;
707 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
708 TAILQ_REMOVE(&filter_info->fivetuple_list,
712 filter_info->fivetuple_mask = 0;
713 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
714 TAILQ_REMOVE(&filter_info->twotuple_list,
718 filter_info->twotuple_mask = 0;
723 /* Remove all flex filters of the device */
724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
726 struct e1000_filter_info *filter_info =
727 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
728 struct e1000_flex_filter *p_flex;
730 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
731 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
734 filter_info->flex_mask = 0;
740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
743 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
744 struct e1000_hw *hw =
745 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
746 struct e1000_vfta * shadow_vfta =
747 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
748 struct e1000_filter_info *filter_info =
749 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
750 struct e1000_adapter *adapter =
751 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
755 eth_dev->dev_ops = ð_igb_ops;
756 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
757 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
758 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
760 /* for secondary processes, we don't initialise any further as primary
761 * has already done this work. Only check we don't need a different
763 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
764 if (eth_dev->data->scattered_rx)
765 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
769 rte_eth_copy_pci_info(eth_dev, pci_dev);
771 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
773 igb_identify_hardware(eth_dev, pci_dev);
774 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
779 e1000_get_bus_info(hw);
781 /* Reset any pending lock */
782 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
787 /* Finish initialization */
788 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
794 hw->phy.autoneg_wait_to_complete = 0;
795 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
798 if (hw->phy.media_type == e1000_media_type_copper) {
799 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
800 hw->phy.disable_polarity_correction = 0;
801 hw->phy.ms_type = e1000_ms_hw_default;
805 * Start from a known state, this is important in reading the nvm
810 /* Make sure we have a good EEPROM before we read from it */
811 if (e1000_validate_nvm_checksum(hw) < 0) {
813 * Some PCI-E parts fail the first check due to
814 * the link being in sleep state, call it again,
815 * if it fails a second time its a real issue.
817 if (e1000_validate_nvm_checksum(hw) < 0) {
818 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
824 /* Read the permanent MAC address out of the EEPROM */
825 if (e1000_read_mac_addr(hw) != 0) {
826 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
831 /* Allocate memory for storing MAC addresses */
832 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
833 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
834 if (eth_dev->data->mac_addrs == NULL) {
835 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
836 "store MAC addresses",
837 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
842 /* Copy the permanent MAC address */
843 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
844 ð_dev->data->mac_addrs[0]);
846 /* initialize the vfta */
847 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
849 /* Now initialize the hardware */
850 if (igb_hardware_init(hw) != 0) {
851 PMD_INIT_LOG(ERR, "Hardware initialization failed");
852 rte_free(eth_dev->data->mac_addrs);
853 eth_dev->data->mac_addrs = NULL;
857 hw->mac.get_link_status = 1;
858 adapter->stopped = 0;
860 /* Indicate SOL/IDER usage */
861 if (e1000_check_reset_block(hw) < 0) {
862 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
866 /* initialize PF if max_vfs not zero */
867 igb_pf_host_init(eth_dev);
869 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
870 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
871 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
872 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
873 E1000_WRITE_FLUSH(hw);
875 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
876 eth_dev->data->port_id, pci_dev->id.vendor_id,
877 pci_dev->id.device_id);
879 rte_intr_callback_register(&pci_dev->intr_handle,
880 eth_igb_interrupt_handler,
883 /* enable uio/vfio intr/eventfd mapping */
884 rte_intr_enable(&pci_dev->intr_handle);
886 /* enable support intr */
887 igb_intr_enable(eth_dev);
889 /* initialize filter info */
890 memset(filter_info, 0,
891 sizeof(struct e1000_filter_info));
893 TAILQ_INIT(&filter_info->flex_list);
894 TAILQ_INIT(&filter_info->twotuple_list);
895 TAILQ_INIT(&filter_info->fivetuple_list);
897 TAILQ_INIT(&igb_filter_ntuple_list);
898 TAILQ_INIT(&igb_filter_ethertype_list);
899 TAILQ_INIT(&igb_filter_syn_list);
900 TAILQ_INIT(&igb_filter_flex_list);
901 TAILQ_INIT(&igb_filter_rss_list);
902 TAILQ_INIT(&igb_flow_list);
907 igb_hw_control_release(hw);
913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
915 struct rte_pci_device *pci_dev;
916 struct rte_intr_handle *intr_handle;
918 struct e1000_adapter *adapter =
919 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
920 struct e1000_filter_info *filter_info =
921 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
923 PMD_INIT_FUNC_TRACE();
925 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
928 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
929 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
930 intr_handle = &pci_dev->intr_handle;
932 if (adapter->stopped == 0)
933 eth_igb_close(eth_dev);
935 eth_dev->dev_ops = NULL;
936 eth_dev->rx_pkt_burst = NULL;
937 eth_dev->tx_pkt_burst = NULL;
939 /* Reset any pending lock */
940 igb_reset_swfw_lock(hw);
942 /* uninitialize PF if max_vfs not zero */
943 igb_pf_host_uninit(eth_dev);
945 /* disable uio intr before callback unregister */
946 rte_intr_disable(intr_handle);
947 rte_intr_callback_unregister(intr_handle,
948 eth_igb_interrupt_handler, eth_dev);
950 /* clear the SYN filter info */
951 filter_info->syn_info = 0;
953 /* clear the ethertype filters info */
954 filter_info->ethertype_mask = 0;
955 memset(filter_info->ethertype_filters, 0,
956 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
958 /* clear the rss filter info */
959 memset(&filter_info->rss_info, 0,
960 sizeof(struct igb_rte_flow_rss_conf));
962 /* remove all ntuple filters of the device */
963 igb_ntuple_filter_uninit(eth_dev);
965 /* remove all flex filters of the device */
966 igb_flex_filter_uninit(eth_dev);
968 /* clear all the filters list */
969 igb_filterlist_flush(eth_dev);
975 * Virtual Function device init
978 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
980 struct rte_pci_device *pci_dev;
981 struct rte_intr_handle *intr_handle;
982 struct e1000_adapter *adapter =
983 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
984 struct e1000_hw *hw =
985 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
987 struct rte_ether_addr *perm_addr =
988 (struct rte_ether_addr *)hw->mac.perm_addr;
990 PMD_INIT_FUNC_TRACE();
992 eth_dev->dev_ops = &igbvf_eth_dev_ops;
993 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
994 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
995 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
997 /* for secondary processes, we don't initialise any further as primary
998 * has already done this work. Only check we don't need a different
1000 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1001 if (eth_dev->data->scattered_rx)
1002 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
1006 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1007 rte_eth_copy_pci_info(eth_dev, pci_dev);
1009 hw->device_id = pci_dev->id.device_id;
1010 hw->vendor_id = pci_dev->id.vendor_id;
1011 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1012 adapter->stopped = 0;
1014 /* Initialize the shared code (base driver) */
1015 diag = e1000_setup_init_funcs(hw, TRUE);
1017 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1022 /* init_mailbox_params */
1023 hw->mbx.ops.init_params(hw);
1025 /* Disable the interrupts for VF */
1026 igbvf_intr_disable(hw);
1028 diag = hw->mac.ops.reset_hw(hw);
1030 /* Allocate memory for storing MAC addresses */
1031 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
1032 hw->mac.rar_entry_count, 0);
1033 if (eth_dev->data->mac_addrs == NULL) {
1035 "Failed to allocate %d bytes needed to store MAC "
1037 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1041 /* Generate a random MAC address, if none was assigned by PF. */
1042 if (rte_is_zero_ether_addr(perm_addr)) {
1043 rte_eth_random_addr(perm_addr->addr_bytes);
1044 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1045 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1046 "%02x:%02x:%02x:%02x:%02x:%02x",
1047 perm_addr->addr_bytes[0],
1048 perm_addr->addr_bytes[1],
1049 perm_addr->addr_bytes[2],
1050 perm_addr->addr_bytes[3],
1051 perm_addr->addr_bytes[4],
1052 perm_addr->addr_bytes[5]);
1055 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1057 rte_free(eth_dev->data->mac_addrs);
1058 eth_dev->data->mac_addrs = NULL;
1061 /* Copy the permanent MAC address */
1062 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1063 ð_dev->data->mac_addrs[0]);
1065 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1067 eth_dev->data->port_id, pci_dev->id.vendor_id,
1068 pci_dev->id.device_id, "igb_mac_82576_vf");
1070 intr_handle = &pci_dev->intr_handle;
1071 rte_intr_callback_register(intr_handle,
1072 eth_igbvf_interrupt_handler, eth_dev);
1078 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1080 struct e1000_adapter *adapter =
1081 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1082 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1084 PMD_INIT_FUNC_TRACE();
1086 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1089 if (adapter->stopped == 0)
1090 igbvf_dev_close(eth_dev);
1092 eth_dev->dev_ops = NULL;
1093 eth_dev->rx_pkt_burst = NULL;
1094 eth_dev->tx_pkt_burst = NULL;
1096 /* disable uio intr before callback unregister */
1097 rte_intr_disable(&pci_dev->intr_handle);
1098 rte_intr_callback_unregister(&pci_dev->intr_handle,
1099 eth_igbvf_interrupt_handler,
1105 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1106 struct rte_pci_device *pci_dev)
1108 return rte_eth_dev_pci_generic_probe(pci_dev,
1109 sizeof(struct e1000_adapter), eth_igb_dev_init);
1112 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1114 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1117 static struct rte_pci_driver rte_igb_pmd = {
1118 .id_table = pci_id_igb_map,
1119 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1120 .probe = eth_igb_pci_probe,
1121 .remove = eth_igb_pci_remove,
1125 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1126 struct rte_pci_device *pci_dev)
1128 return rte_eth_dev_pci_generic_probe(pci_dev,
1129 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1132 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1134 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1138 * virtual function driver struct
1140 static struct rte_pci_driver rte_igbvf_pmd = {
1141 .id_table = pci_id_igbvf_map,
1142 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1143 .probe = eth_igbvf_pci_probe,
1144 .remove = eth_igbvf_pci_remove,
1148 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1150 struct e1000_hw *hw =
1151 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1152 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1153 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1154 rctl |= E1000_RCTL_VFE;
1155 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1159 igb_check_mq_mode(struct rte_eth_dev *dev)
1161 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1162 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1163 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1164 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1166 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1167 tx_mq_mode == ETH_MQ_TX_DCB ||
1168 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1169 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1172 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1173 /* Check multi-queue mode.
1174 * To no break software we accept ETH_MQ_RX_NONE as this might
1175 * be used to turn off VLAN filter.
1178 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1179 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1180 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1181 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1183 /* Only support one queue on VFs.
1184 * RSS together with SRIOV is not supported.
1186 PMD_INIT_LOG(ERR, "SRIOV is active,"
1187 " wrong mq_mode rx %d.",
1191 /* TX mode is not used here, so mode might be ignored.*/
1192 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1193 /* SRIOV only works in VMDq enable mode */
1194 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1195 " TX mode %d is not supported. "
1196 " Driver will behave as %d mode.",
1197 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1200 /* check valid queue number */
1201 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1202 PMD_INIT_LOG(ERR, "SRIOV is active,"
1203 " only support one queue on VFs.");
1207 /* To no break software that set invalid mode, only display
1208 * warning if invalid mode is used.
1210 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1211 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1212 rx_mq_mode != ETH_MQ_RX_RSS) {
1213 /* RSS together with VMDq not supported*/
1214 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1219 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1220 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1221 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1222 " Due to txmode is meaningless in this"
1223 " driver, just ignore.",
1231 eth_igb_configure(struct rte_eth_dev *dev)
1233 struct e1000_interrupt *intr =
1234 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1237 PMD_INIT_FUNC_TRACE();
1239 /* multipe queue mode checking */
1240 ret = igb_check_mq_mode(dev);
1242 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1247 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1248 PMD_INIT_FUNC_TRACE();
1254 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1257 struct e1000_hw *hw =
1258 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259 uint32_t tctl, rctl;
1261 tctl = E1000_READ_REG(hw, E1000_TCTL);
1262 rctl = E1000_READ_REG(hw, E1000_RCTL);
1266 tctl |= E1000_TCTL_EN;
1267 rctl |= E1000_RCTL_EN;
1270 tctl &= ~E1000_TCTL_EN;
1271 rctl &= ~E1000_RCTL_EN;
1273 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1274 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1275 E1000_WRITE_FLUSH(hw);
1279 eth_igb_start(struct rte_eth_dev *dev)
1281 struct e1000_hw *hw =
1282 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283 struct e1000_adapter *adapter =
1284 E1000_DEV_PRIVATE(dev->data->dev_private);
1285 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1286 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288 uint32_t intr_vector = 0;
1294 PMD_INIT_FUNC_TRACE();
1296 /* disable uio/vfio intr/eventfd mapping */
1297 rte_intr_disable(intr_handle);
1299 /* Power up the phy. Needed to make the link go Up */
1300 eth_igb_dev_set_link_up(dev);
1303 * Packet Buffer Allocation (PBA)
1304 * Writing PBA sets the receive portion of the buffer
1305 * the remainder is used for the transmit buffer.
1307 if (hw->mac.type == e1000_82575) {
1310 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1311 E1000_WRITE_REG(hw, E1000_PBA, pba);
1314 /* Put the address into the Receive Address Array */
1315 e1000_rar_set(hw, hw->mac.addr, 0);
1317 /* Initialize the hardware */
1318 if (igb_hardware_init(hw)) {
1319 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1322 adapter->stopped = 0;
1324 E1000_WRITE_REG(hw, E1000_VET,
1325 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1327 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1328 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1329 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1330 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1331 E1000_WRITE_FLUSH(hw);
1333 /* configure PF module if SRIOV enabled */
1334 igb_pf_host_configure(dev);
1336 /* check and configure queue intr-vector mapping */
1337 if ((rte_intr_cap_multiple(intr_handle) ||
1338 !RTE_ETH_DEV_SRIOV(dev).active) &&
1339 dev->data->dev_conf.intr_conf.rxq != 0) {
1340 intr_vector = dev->data->nb_rx_queues;
1341 if (rte_intr_efd_enable(intr_handle, intr_vector))
1345 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1346 intr_handle->intr_vec =
1347 rte_zmalloc("intr_vec",
1348 dev->data->nb_rx_queues * sizeof(int), 0);
1349 if (intr_handle->intr_vec == NULL) {
1350 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1351 " intr_vec", dev->data->nb_rx_queues);
1356 /* confiugre msix for rx interrupt */
1357 eth_igb_configure_msix_intr(dev);
1359 /* Configure for OS presence */
1360 igb_init_manageability(hw);
1362 eth_igb_tx_init(dev);
1364 /* This can fail when allocating mbufs for descriptor rings */
1365 ret = eth_igb_rx_init(dev);
1367 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1368 igb_dev_clear_queues(dev);
1372 e1000_clear_hw_cntrs_base_generic(hw);
1375 * VLAN Offload Settings
1377 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1378 ETH_VLAN_EXTEND_MASK;
1379 ret = eth_igb_vlan_offload_set(dev, mask);
1381 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1382 igb_dev_clear_queues(dev);
1386 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1387 /* Enable VLAN filter since VMDq always use VLAN filter */
1388 igb_vmdq_vlan_hw_filter_enable(dev);
1391 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1392 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1393 (hw->mac.type == e1000_i211)) {
1394 /* Configure EITR with the maximum possible value (0xFFFF) */
1395 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1398 /* Setup link speed and duplex */
1399 speeds = &dev->data->dev_conf.link_speeds;
1400 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1401 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1402 hw->mac.autoneg = 1;
1405 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1408 hw->phy.autoneg_advertised = 0;
1410 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1411 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1412 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1414 goto error_invalid_config;
1416 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1417 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1420 if (*speeds & ETH_LINK_SPEED_10M) {
1421 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1424 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1425 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1428 if (*speeds & ETH_LINK_SPEED_100M) {
1429 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1432 if (*speeds & ETH_LINK_SPEED_1G) {
1433 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1436 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1437 goto error_invalid_config;
1439 /* Set/reset the mac.autoneg based on the link speed,
1443 hw->mac.autoneg = 0;
1444 hw->mac.forced_speed_duplex =
1445 hw->phy.autoneg_advertised;
1447 hw->mac.autoneg = 1;
1451 e1000_setup_link(hw);
1453 if (rte_intr_allow_others(intr_handle)) {
1454 /* check if lsc interrupt is enabled */
1455 if (dev->data->dev_conf.intr_conf.lsc != 0)
1456 eth_igb_lsc_interrupt_setup(dev, TRUE);
1458 eth_igb_lsc_interrupt_setup(dev, FALSE);
1460 rte_intr_callback_unregister(intr_handle,
1461 eth_igb_interrupt_handler,
1463 if (dev->data->dev_conf.intr_conf.lsc != 0)
1464 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1465 " no intr multiplex");
1468 /* check if rxq interrupt is enabled */
1469 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1470 rte_intr_dp_is_en(intr_handle))
1471 eth_igb_rxq_interrupt_setup(dev);
1473 /* enable uio/vfio intr/eventfd mapping */
1474 rte_intr_enable(intr_handle);
1476 /* resume enabled intr since hw reset */
1477 igb_intr_enable(dev);
1479 /* restore all types filter */
1480 igb_filter_restore(dev);
1482 eth_igb_rxtx_control(dev, true);
1483 eth_igb_link_update(dev, 0);
1485 PMD_INIT_LOG(DEBUG, "<<");
1489 error_invalid_config:
1490 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1491 dev->data->dev_conf.link_speeds, dev->data->port_id);
1492 igb_dev_clear_queues(dev);
1496 /*********************************************************************
1498 * This routine disables all traffic on the adapter by issuing a
1499 * global reset on the MAC.
1501 **********************************************************************/
1503 eth_igb_stop(struct rte_eth_dev *dev)
1505 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1507 struct rte_eth_link link;
1508 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1510 eth_igb_rxtx_control(dev, false);
1512 igb_intr_disable(dev);
1514 /* disable intr eventfd mapping */
1515 rte_intr_disable(intr_handle);
1517 igb_pf_reset_hw(hw);
1518 E1000_WRITE_REG(hw, E1000_WUC, 0);
1520 /* Set bit for Go Link disconnect */
1521 if (hw->mac.type >= e1000_82580) {
1524 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1525 phpm_reg |= E1000_82580_PM_GO_LINKD;
1526 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1529 /* Power down the phy. Needed to make the link go Down */
1530 eth_igb_dev_set_link_down(dev);
1532 igb_dev_clear_queues(dev);
1534 /* clear the recorded link status */
1535 memset(&link, 0, sizeof(link));
1536 rte_eth_linkstatus_set(dev, &link);
1538 if (!rte_intr_allow_others(intr_handle))
1539 /* resume to the default handler */
1540 rte_intr_callback_register(intr_handle,
1541 eth_igb_interrupt_handler,
1544 /* Clean datapath event and queue/vec mapping */
1545 rte_intr_efd_disable(intr_handle);
1546 if (intr_handle->intr_vec != NULL) {
1547 rte_free(intr_handle->intr_vec);
1548 intr_handle->intr_vec = NULL;
1553 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1555 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557 if (hw->phy.media_type == e1000_media_type_copper)
1558 e1000_power_up_phy(hw);
1560 e1000_power_up_fiber_serdes_link(hw);
1566 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1568 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570 if (hw->phy.media_type == e1000_media_type_copper)
1571 e1000_power_down_phy(hw);
1573 e1000_shutdown_fiber_serdes_link(hw);
1579 eth_igb_close(struct rte_eth_dev *dev)
1581 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582 struct e1000_adapter *adapter =
1583 E1000_DEV_PRIVATE(dev->data->dev_private);
1584 struct rte_eth_link link;
1585 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1586 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1589 adapter->stopped = 1;
1591 e1000_phy_hw_reset(hw);
1592 igb_release_manageability(hw);
1593 igb_hw_control_release(hw);
1595 /* Clear bit for Go Link disconnect */
1596 if (hw->mac.type >= e1000_82580) {
1599 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1600 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1601 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1604 igb_dev_free_queues(dev);
1606 if (intr_handle->intr_vec) {
1607 rte_free(intr_handle->intr_vec);
1608 intr_handle->intr_vec = NULL;
1611 memset(&link, 0, sizeof(link));
1612 rte_eth_linkstatus_set(dev, &link);
1619 eth_igb_reset(struct rte_eth_dev *dev)
1623 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1624 * its VF to make them align with it. The detailed notification
1625 * mechanism is PMD specific and is currently not implemented.
1626 * To avoid unexpected behavior in VF, currently reset of PF with
1627 * SR-IOV activation is not supported. It might be supported later.
1629 if (dev->data->sriov.active)
1632 ret = eth_igb_dev_uninit(dev);
1636 ret = eth_igb_dev_init(dev);
1643 igb_get_rx_buffer_size(struct e1000_hw *hw)
1645 uint32_t rx_buf_size;
1646 if (hw->mac.type == e1000_82576) {
1647 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1648 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1649 /* PBS needs to be translated according to a lookup table */
1650 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1651 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1652 rx_buf_size = (rx_buf_size << 10);
1653 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1654 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1656 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1662 /*********************************************************************
1664 * Initialize the hardware
1666 **********************************************************************/
1668 igb_hardware_init(struct e1000_hw *hw)
1670 uint32_t rx_buf_size;
1673 /* Let the firmware know the OS is in control */
1674 igb_hw_control_acquire(hw);
1677 * These parameters control the automatic generation (Tx) and
1678 * response (Rx) to Ethernet PAUSE frames.
1679 * - High water mark should allow for at least two standard size (1518)
1680 * frames to be received after sending an XOFF.
1681 * - Low water mark works best when it is very near the high water mark.
1682 * This allows the receiver to restart by sending XON when it has
1683 * drained a bit. Here we use an arbitrary value of 1500 which will
1684 * restart after one full frame is pulled from the buffer. There
1685 * could be several smaller frames in the buffer and if so they will
1686 * not trigger the XON until their total number reduces the buffer
1688 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1690 rx_buf_size = igb_get_rx_buffer_size(hw);
1692 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1693 hw->fc.low_water = hw->fc.high_water - 1500;
1694 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1695 hw->fc.send_xon = 1;
1697 /* Set Flow control, use the tunable location if sane */
1698 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1699 hw->fc.requested_mode = igb_fc_setting;
1701 hw->fc.requested_mode = e1000_fc_none;
1703 /* Issue a global reset */
1704 igb_pf_reset_hw(hw);
1705 E1000_WRITE_REG(hw, E1000_WUC, 0);
1707 diag = e1000_init_hw(hw);
1711 E1000_WRITE_REG(hw, E1000_VET,
1712 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1713 e1000_get_phy_info(hw);
1714 e1000_check_for_link(hw);
1719 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1721 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1725 uint64_t old_gprc = stats->gprc;
1726 uint64_t old_gptc = stats->gptc;
1727 uint64_t old_tpr = stats->tpr;
1728 uint64_t old_tpt = stats->tpt;
1729 uint64_t old_rpthc = stats->rpthc;
1730 uint64_t old_hgptc = stats->hgptc;
1732 if(hw->phy.media_type == e1000_media_type_copper ||
1733 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1735 E1000_READ_REG(hw,E1000_SYMERRS);
1736 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1739 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1740 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1741 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1742 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1744 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1745 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1746 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1747 stats->dc += E1000_READ_REG(hw, E1000_DC);
1748 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1749 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1750 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1752 ** For watchdog management we need to know if we have been
1753 ** paused during the last interval, so capture that here.
1755 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1756 stats->xoffrxc += pause_frames;
1757 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1758 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1759 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1760 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1761 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1762 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1763 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1764 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1765 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1766 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1767 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1768 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1770 /* For the 64-bit byte counters the low dword must be read first. */
1771 /* Both registers clear on the read of the high dword */
1773 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1774 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1775 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1776 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1777 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1778 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1779 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1781 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1782 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1783 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1784 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1785 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1787 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1788 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1790 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1791 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1792 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1793 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1794 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1795 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1797 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1798 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1799 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1800 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1801 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1802 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1803 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1804 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1806 /* Interrupt Counts */
1808 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1809 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1810 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1811 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1812 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1813 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1814 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1815 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1816 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1818 /* Host to Card Statistics */
1820 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1821 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1822 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1823 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1824 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1825 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1826 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1827 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1828 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1829 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1830 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1831 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1832 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1833 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1834 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1835 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1837 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1838 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1839 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1840 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1841 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1842 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1846 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1848 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1849 struct e1000_hw_stats *stats =
1850 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1852 igb_read_stats_registers(hw, stats);
1854 if (rte_stats == NULL)
1858 rte_stats->imissed = stats->mpc;
1859 rte_stats->ierrors = stats->crcerrs +
1860 stats->rlec + stats->ruc + stats->roc +
1861 stats->rxerrc + stats->algnerrc + stats->cexterr;
1864 rte_stats->oerrors = stats->ecol + stats->latecol;
1866 rte_stats->ipackets = stats->gprc;
1867 rte_stats->opackets = stats->gptc;
1868 rte_stats->ibytes = stats->gorc;
1869 rte_stats->obytes = stats->gotc;
1874 eth_igb_stats_reset(struct rte_eth_dev *dev)
1876 struct e1000_hw_stats *hw_stats =
1877 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1879 /* HW registers are cleared on read */
1880 eth_igb_stats_get(dev, NULL);
1882 /* Reset software totals */
1883 memset(hw_stats, 0, sizeof(*hw_stats));
1889 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1891 struct e1000_hw_stats *stats =
1892 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1894 /* HW registers are cleared on read */
1895 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1897 /* Reset software totals */
1898 memset(stats, 0, sizeof(*stats));
1903 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1904 struct rte_eth_xstat_name *xstats_names,
1905 __rte_unused unsigned int size)
1909 if (xstats_names == NULL)
1910 return IGB_NB_XSTATS;
1912 /* Note: limit checked in rte_eth_xstats_names() */
1914 for (i = 0; i < IGB_NB_XSTATS; i++) {
1915 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1916 sizeof(xstats_names[i].name));
1919 return IGB_NB_XSTATS;
1922 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1923 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1929 if (xstats_names == NULL)
1930 return IGB_NB_XSTATS;
1932 for (i = 0; i < IGB_NB_XSTATS; i++)
1933 strlcpy(xstats_names[i].name,
1934 rte_igb_stats_strings[i].name,
1935 sizeof(xstats_names[i].name));
1937 return IGB_NB_XSTATS;
1940 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1942 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1945 for (i = 0; i < limit; i++) {
1946 if (ids[i] >= IGB_NB_XSTATS) {
1947 PMD_INIT_LOG(ERR, "id value isn't valid");
1950 strcpy(xstats_names[i].name,
1951 xstats_names_copy[ids[i]].name);
1958 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1961 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962 struct e1000_hw_stats *hw_stats =
1963 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1966 if (n < IGB_NB_XSTATS)
1967 return IGB_NB_XSTATS;
1969 igb_read_stats_registers(hw, hw_stats);
1971 /* If this is a reset xstats is NULL, and we have cleared the
1972 * registers by reading them.
1977 /* Extended stats */
1978 for (i = 0; i < IGB_NB_XSTATS; i++) {
1980 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1981 rte_igb_stats_strings[i].offset);
1984 return IGB_NB_XSTATS;
1988 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1989 uint64_t *values, unsigned int n)
1994 struct e1000_hw *hw =
1995 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996 struct e1000_hw_stats *hw_stats =
1997 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1999 if (n < IGB_NB_XSTATS)
2000 return IGB_NB_XSTATS;
2002 igb_read_stats_registers(hw, hw_stats);
2004 /* If this is a reset xstats is NULL, and we have cleared the
2005 * registers by reading them.
2010 /* Extended stats */
2011 for (i = 0; i < IGB_NB_XSTATS; i++)
2012 values[i] = *(uint64_t *)(((char *)hw_stats) +
2013 rte_igb_stats_strings[i].offset);
2015 return IGB_NB_XSTATS;
2018 uint64_t values_copy[IGB_NB_XSTATS];
2020 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2023 for (i = 0; i < n; i++) {
2024 if (ids[i] >= IGB_NB_XSTATS) {
2025 PMD_INIT_LOG(ERR, "id value isn't valid");
2028 values[i] = values_copy[ids[i]];
2035 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2037 /* Good Rx packets, include VF loopback */
2038 UPDATE_VF_STAT(E1000_VFGPRC,
2039 hw_stats->last_gprc, hw_stats->gprc);
2041 /* Good Rx octets, include VF loopback */
2042 UPDATE_VF_STAT(E1000_VFGORC,
2043 hw_stats->last_gorc, hw_stats->gorc);
2045 /* Good Tx packets, include VF loopback */
2046 UPDATE_VF_STAT(E1000_VFGPTC,
2047 hw_stats->last_gptc, hw_stats->gptc);
2049 /* Good Tx octets, include VF loopback */
2050 UPDATE_VF_STAT(E1000_VFGOTC,
2051 hw_stats->last_gotc, hw_stats->gotc);
2053 /* Rx Multicst packets */
2054 UPDATE_VF_STAT(E1000_VFMPRC,
2055 hw_stats->last_mprc, hw_stats->mprc);
2057 /* Good Rx loopback packets */
2058 UPDATE_VF_STAT(E1000_VFGPRLBC,
2059 hw_stats->last_gprlbc, hw_stats->gprlbc);
2061 /* Good Rx loopback octets */
2062 UPDATE_VF_STAT(E1000_VFGORLBC,
2063 hw_stats->last_gorlbc, hw_stats->gorlbc);
2065 /* Good Tx loopback packets */
2066 UPDATE_VF_STAT(E1000_VFGPTLBC,
2067 hw_stats->last_gptlbc, hw_stats->gptlbc);
2069 /* Good Tx loopback octets */
2070 UPDATE_VF_STAT(E1000_VFGOTLBC,
2071 hw_stats->last_gotlbc, hw_stats->gotlbc);
2074 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2075 struct rte_eth_xstat_name *xstats_names,
2076 __rte_unused unsigned limit)
2080 if (xstats_names != NULL)
2081 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2082 strlcpy(xstats_names[i].name,
2083 rte_igbvf_stats_strings[i].name,
2084 sizeof(xstats_names[i].name));
2086 return IGBVF_NB_XSTATS;
2090 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2093 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2095 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2098 if (n < IGBVF_NB_XSTATS)
2099 return IGBVF_NB_XSTATS;
2101 igbvf_read_stats_registers(hw, hw_stats);
2106 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2108 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2109 rte_igbvf_stats_strings[i].offset);
2112 return IGBVF_NB_XSTATS;
2116 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2118 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2120 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2122 igbvf_read_stats_registers(hw, hw_stats);
2124 if (rte_stats == NULL)
2127 rte_stats->ipackets = hw_stats->gprc;
2128 rte_stats->ibytes = hw_stats->gorc;
2129 rte_stats->opackets = hw_stats->gptc;
2130 rte_stats->obytes = hw_stats->gotc;
2135 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2137 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2138 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2140 /* Sync HW register to the last stats */
2141 eth_igbvf_stats_get(dev, NULL);
2143 /* reset HW current stats*/
2144 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2145 offsetof(struct e1000_vf_stats, gprc));
2151 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2154 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155 struct e1000_fw_version fw;
2158 e1000_get_fw_version(hw, &fw);
2160 switch (hw->mac.type) {
2163 if (!(e1000_get_flash_presence_i210(hw))) {
2164 ret = snprintf(fw_version, fw_size,
2166 fw.invm_major, fw.invm_minor,
2172 /* if option rom is valid, display its version too */
2174 ret = snprintf(fw_version, fw_size,
2175 "%d.%d, 0x%08x, %d.%d.%d",
2176 fw.eep_major, fw.eep_minor, fw.etrack_id,
2177 fw.or_major, fw.or_build, fw.or_patch);
2180 if (fw.etrack_id != 0X0000) {
2181 ret = snprintf(fw_version, fw_size,
2183 fw.eep_major, fw.eep_minor,
2186 ret = snprintf(fw_version, fw_size,
2188 fw.eep_major, fw.eep_minor,
2195 ret += 1; /* add the size of '\0' */
2196 if (fw_size < (u32)ret)
2203 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2205 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2208 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2209 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2210 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2211 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2212 dev_info->rx_queue_offload_capa;
2213 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2214 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2215 dev_info->tx_queue_offload_capa;
2217 switch (hw->mac.type) {
2219 dev_info->max_rx_queues = 4;
2220 dev_info->max_tx_queues = 4;
2221 dev_info->max_vmdq_pools = 0;
2225 dev_info->max_rx_queues = 16;
2226 dev_info->max_tx_queues = 16;
2227 dev_info->max_vmdq_pools = ETH_8_POOLS;
2228 dev_info->vmdq_queue_num = 16;
2232 dev_info->max_rx_queues = 8;
2233 dev_info->max_tx_queues = 8;
2234 dev_info->max_vmdq_pools = ETH_8_POOLS;
2235 dev_info->vmdq_queue_num = 8;
2239 dev_info->max_rx_queues = 8;
2240 dev_info->max_tx_queues = 8;
2241 dev_info->max_vmdq_pools = ETH_8_POOLS;
2242 dev_info->vmdq_queue_num = 8;
2246 dev_info->max_rx_queues = 8;
2247 dev_info->max_tx_queues = 8;
2251 dev_info->max_rx_queues = 4;
2252 dev_info->max_tx_queues = 4;
2253 dev_info->max_vmdq_pools = 0;
2257 dev_info->max_rx_queues = 2;
2258 dev_info->max_tx_queues = 2;
2259 dev_info->max_vmdq_pools = 0;
2263 /* Should not happen */
2266 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2267 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2268 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2270 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2272 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2273 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2274 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2276 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2281 dev_info->default_txconf = (struct rte_eth_txconf) {
2283 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2284 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2285 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2290 dev_info->rx_desc_lim = rx_desc_lim;
2291 dev_info->tx_desc_lim = tx_desc_lim;
2293 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2294 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2297 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2298 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2303 static const uint32_t *
2304 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2306 static const uint32_t ptypes[] = {
2307 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2310 RTE_PTYPE_L3_IPV4_EXT,
2312 RTE_PTYPE_L3_IPV6_EXT,
2316 RTE_PTYPE_TUNNEL_IP,
2317 RTE_PTYPE_INNER_L3_IPV6,
2318 RTE_PTYPE_INNER_L3_IPV6_EXT,
2319 RTE_PTYPE_INNER_L4_TCP,
2320 RTE_PTYPE_INNER_L4_UDP,
2324 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2325 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2331 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2333 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2335 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2336 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2337 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2338 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2339 DEV_TX_OFFLOAD_IPV4_CKSUM |
2340 DEV_TX_OFFLOAD_UDP_CKSUM |
2341 DEV_TX_OFFLOAD_TCP_CKSUM |
2342 DEV_TX_OFFLOAD_SCTP_CKSUM |
2343 DEV_TX_OFFLOAD_TCP_TSO;
2344 switch (hw->mac.type) {
2346 dev_info->max_rx_queues = 2;
2347 dev_info->max_tx_queues = 2;
2349 case e1000_vfadapt_i350:
2350 dev_info->max_rx_queues = 1;
2351 dev_info->max_tx_queues = 1;
2354 /* Should not happen */
2358 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2359 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2360 dev_info->rx_queue_offload_capa;
2361 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2362 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2363 dev_info->tx_queue_offload_capa;
2365 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2367 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2368 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2369 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2371 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2376 dev_info->default_txconf = (struct rte_eth_txconf) {
2378 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2379 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2380 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2385 dev_info->rx_desc_lim = rx_desc_lim;
2386 dev_info->tx_desc_lim = tx_desc_lim;
2391 /* return 0 means link status changed, -1 means not changed */
2393 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2395 struct e1000_hw *hw =
2396 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397 struct rte_eth_link link;
2398 int link_check, count;
2401 hw->mac.get_link_status = 1;
2403 /* possible wait-to-complete in up to 9 seconds */
2404 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2405 /* Read the real link status */
2406 switch (hw->phy.media_type) {
2407 case e1000_media_type_copper:
2408 /* Do the work to read phy */
2409 e1000_check_for_link(hw);
2410 link_check = !hw->mac.get_link_status;
2413 case e1000_media_type_fiber:
2414 e1000_check_for_link(hw);
2415 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2419 case e1000_media_type_internal_serdes:
2420 e1000_check_for_link(hw);
2421 link_check = hw->mac.serdes_has_link;
2424 /* VF device is type_unknown */
2425 case e1000_media_type_unknown:
2426 eth_igbvf_link_update(hw);
2427 link_check = !hw->mac.get_link_status;
2433 if (link_check || wait_to_complete == 0)
2435 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2437 memset(&link, 0, sizeof(link));
2439 /* Now we check if a transition has happened */
2441 uint16_t duplex, speed;
2442 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2443 link.link_duplex = (duplex == FULL_DUPLEX) ?
2444 ETH_LINK_FULL_DUPLEX :
2445 ETH_LINK_HALF_DUPLEX;
2446 link.link_speed = speed;
2447 link.link_status = ETH_LINK_UP;
2448 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2449 ETH_LINK_SPEED_FIXED);
2450 } else if (!link_check) {
2451 link.link_speed = 0;
2452 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2453 link.link_status = ETH_LINK_DOWN;
2454 link.link_autoneg = ETH_LINK_FIXED;
2457 return rte_eth_linkstatus_set(dev, &link);
2461 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2462 * For ASF and Pass Through versions of f/w this means
2463 * that the driver is loaded.
2466 igb_hw_control_acquire(struct e1000_hw *hw)
2470 /* Let firmware know the driver has taken over */
2471 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2472 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2476 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2477 * For ASF and Pass Through versions of f/w this means that the
2478 * driver is no longer loaded.
2481 igb_hw_control_release(struct e1000_hw *hw)
2485 /* Let firmware taken over control of h/w */
2486 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2487 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2488 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2492 * Bit of a misnomer, what this really means is
2493 * to enable OS management of the system... aka
2494 * to disable special hardware management features.
2497 igb_init_manageability(struct e1000_hw *hw)
2499 if (e1000_enable_mng_pass_thru(hw)) {
2500 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2501 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2503 /* disable hardware interception of ARP */
2504 manc &= ~(E1000_MANC_ARP_EN);
2506 /* enable receiving management packets to the host */
2507 manc |= E1000_MANC_EN_MNG2HOST;
2508 manc2h |= 1 << 5; /* Mng Port 623 */
2509 manc2h |= 1 << 6; /* Mng Port 664 */
2510 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2511 E1000_WRITE_REG(hw, E1000_MANC, manc);
2516 igb_release_manageability(struct e1000_hw *hw)
2518 if (e1000_enable_mng_pass_thru(hw)) {
2519 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2521 manc |= E1000_MANC_ARP_EN;
2522 manc &= ~E1000_MANC_EN_MNG2HOST;
2524 E1000_WRITE_REG(hw, E1000_MANC, manc);
2529 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2531 struct e1000_hw *hw =
2532 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535 rctl = E1000_READ_REG(hw, E1000_RCTL);
2536 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2537 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2543 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2545 struct e1000_hw *hw =
2546 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549 rctl = E1000_READ_REG(hw, E1000_RCTL);
2550 rctl &= (~E1000_RCTL_UPE);
2551 if (dev->data->all_multicast == 1)
2552 rctl |= E1000_RCTL_MPE;
2554 rctl &= (~E1000_RCTL_MPE);
2555 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2561 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2563 struct e1000_hw *hw =
2564 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2567 rctl = E1000_READ_REG(hw, E1000_RCTL);
2568 rctl |= E1000_RCTL_MPE;
2569 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2573 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2575 struct e1000_hw *hw =
2576 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579 if (dev->data->promiscuous == 1)
2580 return; /* must remain in all_multicast mode */
2581 rctl = E1000_READ_REG(hw, E1000_RCTL);
2582 rctl &= (~E1000_RCTL_MPE);
2583 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2587 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2589 struct e1000_hw *hw =
2590 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591 struct e1000_vfta * shadow_vfta =
2592 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2597 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2598 E1000_VFTA_ENTRY_MASK);
2599 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2600 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2605 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2607 /* update local VFTA copy */
2608 shadow_vfta->vfta[vid_idx] = vfta;
2614 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2615 enum rte_vlan_type vlan_type,
2618 struct e1000_hw *hw =
2619 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2622 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2623 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2625 /* only outer TPID of double VLAN can be configured*/
2626 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2627 reg = E1000_READ_REG(hw, E1000_VET);
2628 reg = (reg & (~E1000_VET_VET_EXT)) |
2629 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2630 E1000_WRITE_REG(hw, E1000_VET, reg);
2635 /* all other TPID values are read-only*/
2636 PMD_DRV_LOG(ERR, "Not supported");
2642 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2644 struct e1000_hw *hw =
2645 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2648 /* Filter Table Disable */
2649 reg = E1000_READ_REG(hw, E1000_RCTL);
2650 reg &= ~E1000_RCTL_CFIEN;
2651 reg &= ~E1000_RCTL_VFE;
2652 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2656 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2658 struct e1000_hw *hw =
2659 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660 struct e1000_vfta * shadow_vfta =
2661 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2665 /* Filter Table Enable, CFI not used for packet acceptance */
2666 reg = E1000_READ_REG(hw, E1000_RCTL);
2667 reg &= ~E1000_RCTL_CFIEN;
2668 reg |= E1000_RCTL_VFE;
2669 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2671 /* restore VFTA table */
2672 for (i = 0; i < IGB_VFTA_SIZE; i++)
2673 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2677 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2679 struct e1000_hw *hw =
2680 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2683 /* VLAN Mode Disable */
2684 reg = E1000_READ_REG(hw, E1000_CTRL);
2685 reg &= ~E1000_CTRL_VME;
2686 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2690 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2692 struct e1000_hw *hw =
2693 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2696 /* VLAN Mode Enable */
2697 reg = E1000_READ_REG(hw, E1000_CTRL);
2698 reg |= E1000_CTRL_VME;
2699 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2703 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2705 struct e1000_hw *hw =
2706 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2709 /* CTRL_EXT: Extended VLAN */
2710 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2711 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2712 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2714 /* Update maximum packet length */
2715 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2716 E1000_WRITE_REG(hw, E1000_RLPML,
2717 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2722 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2724 struct e1000_hw *hw =
2725 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2728 /* CTRL_EXT: Extended VLAN */
2729 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2730 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2731 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2733 /* Update maximum packet length */
2734 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2735 E1000_WRITE_REG(hw, E1000_RLPML,
2736 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2741 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2743 struct rte_eth_rxmode *rxmode;
2745 rxmode = &dev->data->dev_conf.rxmode;
2746 if(mask & ETH_VLAN_STRIP_MASK){
2747 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2748 igb_vlan_hw_strip_enable(dev);
2750 igb_vlan_hw_strip_disable(dev);
2753 if(mask & ETH_VLAN_FILTER_MASK){
2754 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2755 igb_vlan_hw_filter_enable(dev);
2757 igb_vlan_hw_filter_disable(dev);
2760 if(mask & ETH_VLAN_EXTEND_MASK){
2761 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2762 igb_vlan_hw_extend_enable(dev);
2764 igb_vlan_hw_extend_disable(dev);
2772 * It enables the interrupt mask and then enable the interrupt.
2775 * Pointer to struct rte_eth_dev.
2780 * - On success, zero.
2781 * - On failure, a negative value.
2784 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2786 struct e1000_interrupt *intr =
2787 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2790 intr->mask |= E1000_ICR_LSC;
2792 intr->mask &= ~E1000_ICR_LSC;
2797 /* It clears the interrupt causes and enables the interrupt.
2798 * It will be called once only during nic initialized.
2801 * Pointer to struct rte_eth_dev.
2804 * - On success, zero.
2805 * - On failure, a negative value.
2807 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2809 uint32_t mask, regval;
2811 struct e1000_hw *hw =
2812 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2814 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2815 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2816 struct rte_eth_dev_info dev_info;
2818 memset(&dev_info, 0, sizeof(dev_info));
2819 ret = eth_igb_infos_get(dev, &dev_info);
2823 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2824 regval = E1000_READ_REG(hw, E1000_EIMS);
2825 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2831 * It reads ICR and gets interrupt causes, check it and set a bit flag
2832 * to update link status.
2835 * Pointer to struct rte_eth_dev.
2838 * - On success, zero.
2839 * - On failure, a negative value.
2842 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2845 struct e1000_hw *hw =
2846 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847 struct e1000_interrupt *intr =
2848 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2850 igb_intr_disable(dev);
2852 /* read-on-clear nic registers here */
2853 icr = E1000_READ_REG(hw, E1000_ICR);
2856 if (icr & E1000_ICR_LSC) {
2857 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2860 if (icr & E1000_ICR_VMMB)
2861 intr->flags |= E1000_FLAG_MAILBOX;
2867 * It executes link_update after knowing an interrupt is prsent.
2870 * Pointer to struct rte_eth_dev.
2873 * - On success, zero.
2874 * - On failure, a negative value.
2877 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2878 struct rte_intr_handle *intr_handle)
2880 struct e1000_hw *hw =
2881 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2882 struct e1000_interrupt *intr =
2883 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2884 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2885 struct rte_eth_link link;
2888 if (intr->flags & E1000_FLAG_MAILBOX) {
2889 igb_pf_mbx_process(dev);
2890 intr->flags &= ~E1000_FLAG_MAILBOX;
2893 igb_intr_enable(dev);
2894 rte_intr_ack(intr_handle);
2896 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2897 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2899 /* set get_link_status to check register later */
2900 hw->mac.get_link_status = 1;
2901 ret = eth_igb_link_update(dev, 0);
2903 /* check if link has changed */
2907 rte_eth_linkstatus_get(dev, &link);
2908 if (link.link_status) {
2910 " Port %d: Link Up - speed %u Mbps - %s",
2912 (unsigned)link.link_speed,
2913 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2914 "full-duplex" : "half-duplex");
2916 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2917 dev->data->port_id);
2920 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2921 pci_dev->addr.domain,
2923 pci_dev->addr.devid,
2924 pci_dev->addr.function);
2925 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2933 * Interrupt handler which shall be registered at first.
2936 * Pointer to interrupt handle.
2938 * The address of parameter (struct rte_eth_dev *) regsitered before.
2944 eth_igb_interrupt_handler(void *param)
2946 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2948 eth_igb_interrupt_get_status(dev);
2949 eth_igb_interrupt_action(dev, dev->intr_handle);
2953 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2956 struct e1000_hw *hw =
2957 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958 struct e1000_interrupt *intr =
2959 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2961 igbvf_intr_disable(hw);
2963 /* read-on-clear nic registers here */
2964 eicr = E1000_READ_REG(hw, E1000_EICR);
2967 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2968 intr->flags |= E1000_FLAG_MAILBOX;
2973 void igbvf_mbx_process(struct rte_eth_dev *dev)
2975 struct e1000_hw *hw =
2976 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2977 struct e1000_mbx_info *mbx = &hw->mbx;
2980 /* peek the message first */
2981 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2983 /* PF reset VF event */
2984 if (in_msg == E1000_PF_CONTROL_MSG) {
2985 /* dummy mbx read to ack pf */
2986 if (mbx->ops.read(hw, &in_msg, 1, 0))
2988 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2994 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2996 struct e1000_interrupt *intr =
2997 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2999 if (intr->flags & E1000_FLAG_MAILBOX) {
3000 igbvf_mbx_process(dev);
3001 intr->flags &= ~E1000_FLAG_MAILBOX;
3004 igbvf_intr_enable(dev);
3005 rte_intr_ack(intr_handle);
3011 eth_igbvf_interrupt_handler(void *param)
3013 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3015 eth_igbvf_interrupt_get_status(dev);
3016 eth_igbvf_interrupt_action(dev, dev->intr_handle);
3020 eth_igb_led_on(struct rte_eth_dev *dev)
3022 struct e1000_hw *hw;
3024 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3025 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3029 eth_igb_led_off(struct rte_eth_dev *dev)
3031 struct e1000_hw *hw;
3033 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3034 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3038 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3040 struct e1000_hw *hw;
3045 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3046 fc_conf->pause_time = hw->fc.pause_time;
3047 fc_conf->high_water = hw->fc.high_water;
3048 fc_conf->low_water = hw->fc.low_water;
3049 fc_conf->send_xon = hw->fc.send_xon;
3050 fc_conf->autoneg = hw->mac.autoneg;
3053 * Return rx_pause and tx_pause status according to actual setting of
3054 * the TFCE and RFCE bits in the CTRL register.
3056 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3057 if (ctrl & E1000_CTRL_TFCE)
3062 if (ctrl & E1000_CTRL_RFCE)
3067 if (rx_pause && tx_pause)
3068 fc_conf->mode = RTE_FC_FULL;
3070 fc_conf->mode = RTE_FC_RX_PAUSE;
3072 fc_conf->mode = RTE_FC_TX_PAUSE;
3074 fc_conf->mode = RTE_FC_NONE;
3080 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3082 struct e1000_hw *hw;
3084 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3090 uint32_t rx_buf_size;
3091 uint32_t max_high_water;
3094 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3095 if (fc_conf->autoneg != hw->mac.autoneg)
3097 rx_buf_size = igb_get_rx_buffer_size(hw);
3098 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3100 /* At least reserve one Ethernet frame for watermark */
3101 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3102 if ((fc_conf->high_water > max_high_water) ||
3103 (fc_conf->high_water < fc_conf->low_water)) {
3104 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3105 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3109 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3110 hw->fc.pause_time = fc_conf->pause_time;
3111 hw->fc.high_water = fc_conf->high_water;
3112 hw->fc.low_water = fc_conf->low_water;
3113 hw->fc.send_xon = fc_conf->send_xon;
3115 err = e1000_setup_link_generic(hw);
3116 if (err == E1000_SUCCESS) {
3118 /* check if we want to forward MAC frames - driver doesn't have native
3119 * capability to do that, so we'll write the registers ourselves */
3121 rctl = E1000_READ_REG(hw, E1000_RCTL);
3123 /* set or clear MFLCN.PMCF bit depending on configuration */
3124 if (fc_conf->mac_ctrl_frame_fwd != 0)
3125 rctl |= E1000_RCTL_PMCF;
3127 rctl &= ~E1000_RCTL_PMCF;
3129 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3130 E1000_WRITE_FLUSH(hw);
3135 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3139 #define E1000_RAH_POOLSEL_SHIFT (18)
3141 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3142 uint32_t index, uint32_t pool)
3144 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3147 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3148 rah = E1000_READ_REG(hw, E1000_RAH(index));
3149 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3150 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3155 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3157 uint8_t addr[RTE_ETHER_ADDR_LEN];
3158 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3160 memset(addr, 0, sizeof(addr));
3162 e1000_rar_set(hw, addr, index);
3166 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3167 struct rte_ether_addr *addr)
3169 eth_igb_rar_clear(dev, 0);
3170 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3175 * Virtual Function operations
3178 igbvf_intr_disable(struct e1000_hw *hw)
3180 PMD_INIT_FUNC_TRACE();
3182 /* Clear interrupt mask to stop from interrupts being generated */
3183 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3185 E1000_WRITE_FLUSH(hw);
3189 igbvf_stop_adapter(struct rte_eth_dev *dev)
3193 struct rte_eth_dev_info dev_info;
3194 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3197 memset(&dev_info, 0, sizeof(dev_info));
3198 ret = eth_igbvf_infos_get(dev, &dev_info);
3202 /* Clear interrupt mask to stop from interrupts being generated */
3203 igbvf_intr_disable(hw);
3205 /* Clear any pending interrupts, flush previous writes */
3206 E1000_READ_REG(hw, E1000_EICR);
3208 /* Disable the transmit unit. Each queue must be disabled. */
3209 for (i = 0; i < dev_info.max_tx_queues; i++)
3210 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3212 /* Disable the receive unit by stopping each queue */
3213 for (i = 0; i < dev_info.max_rx_queues; i++) {
3214 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3215 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3216 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3217 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3221 /* flush all queues disables */
3222 E1000_WRITE_FLUSH(hw);
3226 static int eth_igbvf_link_update(struct e1000_hw *hw)
3228 struct e1000_mbx_info *mbx = &hw->mbx;
3229 struct e1000_mac_info *mac = &hw->mac;
3230 int ret_val = E1000_SUCCESS;
3232 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3235 * We only want to run this if there has been a rst asserted.
3236 * in this case that could mean a link change, device reset,
3237 * or a virtual function reset
3240 /* If we were hit with a reset or timeout drop the link */
3241 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3242 mac->get_link_status = TRUE;
3244 if (!mac->get_link_status)
3247 /* if link status is down no point in checking to see if pf is up */
3248 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3251 /* if we passed all the tests above then the link is up and we no
3252 * longer need to check for link */
3253 mac->get_link_status = FALSE;
3261 igbvf_dev_configure(struct rte_eth_dev *dev)
3263 struct rte_eth_conf* conf = &dev->data->dev_conf;
3265 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3266 dev->data->port_id);
3269 * VF has no ability to enable/disable HW CRC
3270 * Keep the persistent behavior the same as Host PF
3272 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3273 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3274 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3275 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3278 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3279 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3280 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3288 igbvf_dev_start(struct rte_eth_dev *dev)
3290 struct e1000_hw *hw =
3291 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3292 struct e1000_adapter *adapter =
3293 E1000_DEV_PRIVATE(dev->data->dev_private);
3294 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3295 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3297 uint32_t intr_vector = 0;
3299 PMD_INIT_FUNC_TRACE();
3301 hw->mac.ops.reset_hw(hw);
3302 adapter->stopped = 0;
3305 igbvf_set_vfta_all(dev,1);
3307 eth_igbvf_tx_init(dev);
3309 /* This can fail when allocating mbufs for descriptor rings */
3310 ret = eth_igbvf_rx_init(dev);
3312 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3313 igb_dev_clear_queues(dev);
3317 /* check and configure queue intr-vector mapping */
3318 if (rte_intr_cap_multiple(intr_handle) &&
3319 dev->data->dev_conf.intr_conf.rxq) {
3320 intr_vector = dev->data->nb_rx_queues;
3321 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3326 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3327 intr_handle->intr_vec =
3328 rte_zmalloc("intr_vec",
3329 dev->data->nb_rx_queues * sizeof(int), 0);
3330 if (!intr_handle->intr_vec) {
3331 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3332 " intr_vec", dev->data->nb_rx_queues);
3337 eth_igbvf_configure_msix_intr(dev);
3339 /* enable uio/vfio intr/eventfd mapping */
3340 rte_intr_enable(intr_handle);
3342 /* resume enabled intr since hw reset */
3343 igbvf_intr_enable(dev);
3349 igbvf_dev_stop(struct rte_eth_dev *dev)
3351 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3352 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3354 PMD_INIT_FUNC_TRACE();
3356 igbvf_stop_adapter(dev);
3359 * Clear what we set, but we still keep shadow_vfta to
3360 * restore after device starts
3362 igbvf_set_vfta_all(dev,0);
3364 igb_dev_clear_queues(dev);
3366 /* disable intr eventfd mapping */
3367 rte_intr_disable(intr_handle);
3369 /* Clean datapath event and queue/vec mapping */
3370 rte_intr_efd_disable(intr_handle);
3371 if (intr_handle->intr_vec) {
3372 rte_free(intr_handle->intr_vec);
3373 intr_handle->intr_vec = NULL;
3378 igbvf_dev_close(struct rte_eth_dev *dev)
3380 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3381 struct e1000_adapter *adapter =
3382 E1000_DEV_PRIVATE(dev->data->dev_private);
3383 struct rte_ether_addr addr;
3385 PMD_INIT_FUNC_TRACE();
3389 igbvf_dev_stop(dev);
3390 adapter->stopped = 1;
3391 igb_dev_free_queues(dev);
3394 * reprogram the RAR with a zero mac address,
3395 * to ensure that the VF traffic goes to the PF
3396 * after stop, close and detach of the VF.
3399 memset(&addr, 0, sizeof(addr));
3400 igbvf_default_mac_addr_set(dev, &addr);
3404 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3406 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3408 /* Set both unicast and multicast promisc */
3409 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3415 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3417 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419 /* If in allmulticast mode leave multicast promisc */
3420 if (dev->data->all_multicast == 1)
3421 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3423 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3429 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3431 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3433 /* In promiscuous mode multicast promisc already set */
3434 if (dev->data->promiscuous == 0)
3435 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3439 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3441 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3443 /* In promiscuous mode leave multicast promisc enabled */
3444 if (dev->data->promiscuous == 0)
3445 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3448 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3450 struct e1000_mbx_info *mbx = &hw->mbx;
3454 /* After set vlan, vlan strip will also be enabled in igb driver*/
3455 msgbuf[0] = E1000_VF_SET_VLAN;
3457 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3459 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3461 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3465 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3469 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3470 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3477 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3479 struct e1000_hw *hw =
3480 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481 struct e1000_vfta * shadow_vfta =
3482 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3483 int i = 0, j = 0, vfta = 0, mask = 1;
3485 for (i = 0; i < IGB_VFTA_SIZE; i++){
3486 vfta = shadow_vfta->vfta[i];
3489 for (j = 0; j < 32; j++){
3492 (uint16_t)((i<<5)+j), on);
3501 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3503 struct e1000_hw *hw =
3504 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3505 struct e1000_vfta * shadow_vfta =
3506 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3507 uint32_t vid_idx = 0;
3508 uint32_t vid_bit = 0;
3511 PMD_INIT_FUNC_TRACE();
3513 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3514 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3516 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3519 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3520 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3522 /*Save what we set and retore it after device reset*/
3524 shadow_vfta->vfta[vid_idx] |= vid_bit;
3526 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3532 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3534 struct e1000_hw *hw =
3535 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3537 /* index is not used by rar_set() */
3538 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3544 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3545 struct rte_eth_rss_reta_entry64 *reta_conf,
3550 uint16_t idx, shift;
3551 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3553 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3554 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3555 "(%d) doesn't match the number hardware can supported "
3556 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3560 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3561 idx = i / RTE_RETA_GROUP_SIZE;
3562 shift = i % RTE_RETA_GROUP_SIZE;
3563 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3567 if (mask == IGB_4_BIT_MASK)
3570 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3571 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3572 if (mask & (0x1 << j))
3573 reta |= reta_conf[idx].reta[shift + j] <<
3576 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3578 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3585 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3586 struct rte_eth_rss_reta_entry64 *reta_conf,
3591 uint16_t idx, shift;
3592 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3595 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3596 "(%d) doesn't match the number hardware can supported "
3597 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3601 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3602 idx = i / RTE_RETA_GROUP_SIZE;
3603 shift = i % RTE_RETA_GROUP_SIZE;
3604 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3608 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3609 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3610 if (mask & (0x1 << j))
3611 reta_conf[idx].reta[shift + j] =
3612 ((reta >> (CHAR_BIT * j)) &
3621 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3622 struct rte_eth_syn_filter *filter,
3625 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3626 struct e1000_filter_info *filter_info =
3627 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3628 uint32_t synqf, rfctl;
3630 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3633 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3636 if (synqf & E1000_SYN_FILTER_ENABLE)
3639 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3640 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3642 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3643 if (filter->hig_pri)
3644 rfctl |= E1000_RFCTL_SYNQFP;
3646 rfctl &= ~E1000_RFCTL_SYNQFP;
3648 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3650 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3655 filter_info->syn_info = synqf;
3656 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3657 E1000_WRITE_FLUSH(hw);
3662 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3663 struct rte_eth_syn_filter *filter)
3665 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3666 uint32_t synqf, rfctl;
3668 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3669 if (synqf & E1000_SYN_FILTER_ENABLE) {
3670 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3671 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3672 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3673 E1000_SYN_FILTER_QUEUE_SHIFT);
3681 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3682 enum rte_filter_op filter_op,
3685 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3688 MAC_TYPE_FILTER_SUP(hw->mac.type);
3690 if (filter_op == RTE_ETH_FILTER_NOP)
3694 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3699 switch (filter_op) {
3700 case RTE_ETH_FILTER_ADD:
3701 ret = eth_igb_syn_filter_set(dev,
3702 (struct rte_eth_syn_filter *)arg,
3705 case RTE_ETH_FILTER_DELETE:
3706 ret = eth_igb_syn_filter_set(dev,
3707 (struct rte_eth_syn_filter *)arg,
3710 case RTE_ETH_FILTER_GET:
3711 ret = eth_igb_syn_filter_get(dev,
3712 (struct rte_eth_syn_filter *)arg);
3715 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3723 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3725 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3726 struct e1000_2tuple_filter_info *filter_info)
3728 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3730 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3731 return -EINVAL; /* filter index is out of range. */
3732 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3733 return -EINVAL; /* flags is invalid. */
3735 switch (filter->dst_port_mask) {
3737 filter_info->dst_port_mask = 0;
3738 filter_info->dst_port = filter->dst_port;
3741 filter_info->dst_port_mask = 1;
3744 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3748 switch (filter->proto_mask) {
3750 filter_info->proto_mask = 0;
3751 filter_info->proto = filter->proto;
3754 filter_info->proto_mask = 1;
3757 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3761 filter_info->priority = (uint8_t)filter->priority;
3762 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3763 filter_info->tcp_flags = filter->tcp_flags;
3765 filter_info->tcp_flags = 0;
3770 static inline struct e1000_2tuple_filter *
3771 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3772 struct e1000_2tuple_filter_info *key)
3774 struct e1000_2tuple_filter *it;
3776 TAILQ_FOREACH(it, filter_list, entries) {
3777 if (memcmp(key, &it->filter_info,
3778 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3785 /* inject a igb 2tuple filter to HW */
3787 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3788 struct e1000_2tuple_filter *filter)
3790 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3792 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3796 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3797 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3798 imir |= E1000_IMIR_PORT_BP;
3800 imir &= ~E1000_IMIR_PORT_BP;
3802 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3804 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3805 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3806 ttqf |= (uint32_t)(filter->filter_info.proto &
3807 E1000_TTQF_PROTOCOL_MASK);
3808 if (filter->filter_info.proto_mask == 0)
3809 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3811 /* tcp flags bits setting. */
3812 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3813 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3814 imir_ext |= E1000_IMIREXT_CTRL_URG;
3815 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3816 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3817 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3818 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3819 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3820 imir_ext |= E1000_IMIREXT_CTRL_RST;
3821 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3822 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3823 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3824 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3826 imir_ext |= E1000_IMIREXT_CTRL_BP;
3828 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3829 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3830 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3834 * igb_add_2tuple_filter - add a 2tuple filter
3837 * dev: Pointer to struct rte_eth_dev.
3838 * ntuple_filter: ponter to the filter that will be added.
3841 * - On success, zero.
3842 * - On failure, a negative value.
3845 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3846 struct rte_eth_ntuple_filter *ntuple_filter)
3848 struct e1000_filter_info *filter_info =
3849 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3850 struct e1000_2tuple_filter *filter;
3853 filter = rte_zmalloc("e1000_2tuple_filter",
3854 sizeof(struct e1000_2tuple_filter), 0);
3858 ret = ntuple_filter_to_2tuple(ntuple_filter,
3859 &filter->filter_info);
3864 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3865 &filter->filter_info) != NULL) {
3866 PMD_DRV_LOG(ERR, "filter exists.");
3870 filter->queue = ntuple_filter->queue;
3873 * look for an unused 2tuple filter index,
3874 * and insert the filter to list.
3876 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3877 if (!(filter_info->twotuple_mask & (1 << i))) {
3878 filter_info->twotuple_mask |= 1 << i;
3880 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3886 if (i >= E1000_MAX_TTQF_FILTERS) {
3887 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3892 igb_inject_2uple_filter(dev, filter);
3897 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3898 struct e1000_2tuple_filter *filter)
3900 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3901 struct e1000_filter_info *filter_info =
3902 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3904 filter_info->twotuple_mask &= ~(1 << filter->index);
3905 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3908 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3909 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3910 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3915 * igb_remove_2tuple_filter - remove a 2tuple filter
3918 * dev: Pointer to struct rte_eth_dev.
3919 * ntuple_filter: ponter to the filter that will be removed.
3922 * - On success, zero.
3923 * - On failure, a negative value.
3926 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3927 struct rte_eth_ntuple_filter *ntuple_filter)
3929 struct e1000_filter_info *filter_info =
3930 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3931 struct e1000_2tuple_filter_info filter_2tuple;
3932 struct e1000_2tuple_filter *filter;
3935 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3936 ret = ntuple_filter_to_2tuple(ntuple_filter,
3941 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3943 if (filter == NULL) {
3944 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3948 igb_delete_2tuple_filter(dev, filter);
3953 /* inject a igb flex filter to HW */
3955 igb_inject_flex_filter(struct rte_eth_dev *dev,
3956 struct e1000_flex_filter *filter)
3958 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3959 uint32_t wufc, queueing;
3963 wufc = E1000_READ_REG(hw, E1000_WUFC);
3964 if (filter->index < E1000_MAX_FHFT)
3965 reg_off = E1000_FHFT(filter->index);
3967 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3969 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3970 (E1000_WUFC_FLX0 << filter->index));
3971 queueing = filter->filter_info.len |
3972 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3973 (filter->filter_info.priority <<
3974 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3975 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3978 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3979 E1000_WRITE_REG(hw, reg_off,
3980 filter->filter_info.dwords[j]);
3981 reg_off += sizeof(uint32_t);
3982 E1000_WRITE_REG(hw, reg_off,
3983 filter->filter_info.dwords[++j]);
3984 reg_off += sizeof(uint32_t);
3985 E1000_WRITE_REG(hw, reg_off,
3986 (uint32_t)filter->filter_info.mask[i]);
3987 reg_off += sizeof(uint32_t) * 2;
3992 static inline struct e1000_flex_filter *
3993 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3994 struct e1000_flex_filter_info *key)
3996 struct e1000_flex_filter *it;
3998 TAILQ_FOREACH(it, filter_list, entries) {
3999 if (memcmp(key, &it->filter_info,
4000 sizeof(struct e1000_flex_filter_info)) == 0)
4007 /* remove a flex byte filter
4009 * dev: Pointer to struct rte_eth_dev.
4010 * filter: the pointer of the filter will be removed.
4013 igb_remove_flex_filter(struct rte_eth_dev *dev,
4014 struct e1000_flex_filter *filter)
4016 struct e1000_filter_info *filter_info =
4017 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4018 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4022 wufc = E1000_READ_REG(hw, E1000_WUFC);
4023 if (filter->index < E1000_MAX_FHFT)
4024 reg_off = E1000_FHFT(filter->index);
4026 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4028 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4029 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4031 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4032 (~(E1000_WUFC_FLX0 << filter->index)));
4034 filter_info->flex_mask &= ~(1 << filter->index);
4035 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4040 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4041 struct rte_eth_flex_filter *filter,
4044 struct e1000_filter_info *filter_info =
4045 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4046 struct e1000_flex_filter *flex_filter, *it;
4050 flex_filter = rte_zmalloc("e1000_flex_filter",
4051 sizeof(struct e1000_flex_filter), 0);
4052 if (flex_filter == NULL)
4055 flex_filter->filter_info.len = filter->len;
4056 flex_filter->filter_info.priority = filter->priority;
4057 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4058 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4060 /* reverse bits in flex filter's mask*/
4061 for (shift = 0; shift < CHAR_BIT; shift++) {
4062 if (filter->mask[i] & (0x01 << shift))
4063 mask |= (0x80 >> shift);
4065 flex_filter->filter_info.mask[i] = mask;
4068 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4069 &flex_filter->filter_info);
4070 if (it == NULL && !add) {
4071 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4072 rte_free(flex_filter);
4075 if (it != NULL && add) {
4076 PMD_DRV_LOG(ERR, "filter exists.");
4077 rte_free(flex_filter);
4082 flex_filter->queue = filter->queue;
4084 * look for an unused flex filter index
4085 * and insert the filter into the list.
4087 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4088 if (!(filter_info->flex_mask & (1 << i))) {
4089 filter_info->flex_mask |= 1 << i;
4090 flex_filter->index = i;
4091 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4097 if (i >= E1000_MAX_FLEX_FILTERS) {
4098 PMD_DRV_LOG(ERR, "flex filters are full.");
4099 rte_free(flex_filter);
4103 igb_inject_flex_filter(dev, flex_filter);
4106 igb_remove_flex_filter(dev, it);
4107 rte_free(flex_filter);
4114 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4115 struct rte_eth_flex_filter *filter)
4117 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4118 struct e1000_filter_info *filter_info =
4119 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4120 struct e1000_flex_filter flex_filter, *it;
4121 uint32_t wufc, queueing, wufc_en = 0;
4123 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4124 flex_filter.filter_info.len = filter->len;
4125 flex_filter.filter_info.priority = filter->priority;
4126 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4127 memcpy(flex_filter.filter_info.mask, filter->mask,
4128 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4130 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4131 &flex_filter.filter_info);
4133 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4137 wufc = E1000_READ_REG(hw, E1000_WUFC);
4138 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4140 if ((wufc & wufc_en) == wufc_en) {
4141 uint32_t reg_off = 0;
4142 if (it->index < E1000_MAX_FHFT)
4143 reg_off = E1000_FHFT(it->index);
4145 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4147 queueing = E1000_READ_REG(hw,
4148 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4149 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4150 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4151 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4152 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4153 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4160 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4161 enum rte_filter_op filter_op,
4164 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4165 struct rte_eth_flex_filter *filter;
4168 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4170 if (filter_op == RTE_ETH_FILTER_NOP)
4174 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4179 filter = (struct rte_eth_flex_filter *)arg;
4180 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4181 || filter->len % sizeof(uint64_t) != 0) {
4182 PMD_DRV_LOG(ERR, "filter's length is out of range");
4185 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4186 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4190 switch (filter_op) {
4191 case RTE_ETH_FILTER_ADD:
4192 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4194 case RTE_ETH_FILTER_DELETE:
4195 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4197 case RTE_ETH_FILTER_GET:
4198 ret = eth_igb_get_flex_filter(dev, filter);
4201 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4209 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4211 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4212 struct e1000_5tuple_filter_info *filter_info)
4214 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4216 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4217 return -EINVAL; /* filter index is out of range. */
4218 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4219 return -EINVAL; /* flags is invalid. */
4221 switch (filter->dst_ip_mask) {
4223 filter_info->dst_ip_mask = 0;
4224 filter_info->dst_ip = filter->dst_ip;
4227 filter_info->dst_ip_mask = 1;
4230 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4234 switch (filter->src_ip_mask) {
4236 filter_info->src_ip_mask = 0;
4237 filter_info->src_ip = filter->src_ip;
4240 filter_info->src_ip_mask = 1;
4243 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4247 switch (filter->dst_port_mask) {
4249 filter_info->dst_port_mask = 0;
4250 filter_info->dst_port = filter->dst_port;
4253 filter_info->dst_port_mask = 1;
4256 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4260 switch (filter->src_port_mask) {
4262 filter_info->src_port_mask = 0;
4263 filter_info->src_port = filter->src_port;
4266 filter_info->src_port_mask = 1;
4269 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4273 switch (filter->proto_mask) {
4275 filter_info->proto_mask = 0;
4276 filter_info->proto = filter->proto;
4279 filter_info->proto_mask = 1;
4282 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4286 filter_info->priority = (uint8_t)filter->priority;
4287 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4288 filter_info->tcp_flags = filter->tcp_flags;
4290 filter_info->tcp_flags = 0;
4295 static inline struct e1000_5tuple_filter *
4296 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4297 struct e1000_5tuple_filter_info *key)
4299 struct e1000_5tuple_filter *it;
4301 TAILQ_FOREACH(it, filter_list, entries) {
4302 if (memcmp(key, &it->filter_info,
4303 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4310 /* inject a igb 5-tuple filter to HW */
4312 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4313 struct e1000_5tuple_filter *filter)
4315 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4316 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4317 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4321 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4322 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4323 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4324 if (filter->filter_info.dst_ip_mask == 0)
4325 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4326 if (filter->filter_info.src_port_mask == 0)
4327 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4328 if (filter->filter_info.proto_mask == 0)
4329 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4330 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4331 E1000_FTQF_QUEUE_MASK;
4332 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4333 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4334 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4335 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4337 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4338 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4340 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4341 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4342 imir |= E1000_IMIR_PORT_BP;
4344 imir &= ~E1000_IMIR_PORT_BP;
4345 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4347 /* tcp flags bits setting. */
4348 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4349 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4350 imir_ext |= E1000_IMIREXT_CTRL_URG;
4351 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4352 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4353 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4354 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4355 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4356 imir_ext |= E1000_IMIREXT_CTRL_RST;
4357 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4358 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4359 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4360 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4362 imir_ext |= E1000_IMIREXT_CTRL_BP;
4364 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4365 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4369 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4372 * dev: Pointer to struct rte_eth_dev.
4373 * ntuple_filter: ponter to the filter that will be added.
4376 * - On success, zero.
4377 * - On failure, a negative value.
4380 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4381 struct rte_eth_ntuple_filter *ntuple_filter)
4383 struct e1000_filter_info *filter_info =
4384 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4385 struct e1000_5tuple_filter *filter;
4389 filter = rte_zmalloc("e1000_5tuple_filter",
4390 sizeof(struct e1000_5tuple_filter), 0);
4394 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4395 &filter->filter_info);
4401 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4402 &filter->filter_info) != NULL) {
4403 PMD_DRV_LOG(ERR, "filter exists.");
4407 filter->queue = ntuple_filter->queue;
4410 * look for an unused 5tuple filter index,
4411 * and insert the filter to list.
4413 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4414 if (!(filter_info->fivetuple_mask & (1 << i))) {
4415 filter_info->fivetuple_mask |= 1 << i;
4417 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4423 if (i >= E1000_MAX_FTQF_FILTERS) {
4424 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4429 igb_inject_5tuple_filter_82576(dev, filter);
4434 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4435 struct e1000_5tuple_filter *filter)
4437 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4438 struct e1000_filter_info *filter_info =
4439 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4441 filter_info->fivetuple_mask &= ~(1 << filter->index);
4442 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4445 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4446 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4447 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4448 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4449 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4450 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4451 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4456 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4459 * dev: Pointer to struct rte_eth_dev.
4460 * ntuple_filter: ponter to the filter that will be removed.
4463 * - On success, zero.
4464 * - On failure, a negative value.
4467 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4468 struct rte_eth_ntuple_filter *ntuple_filter)
4470 struct e1000_filter_info *filter_info =
4471 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4472 struct e1000_5tuple_filter_info filter_5tuple;
4473 struct e1000_5tuple_filter *filter;
4476 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4477 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4482 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4484 if (filter == NULL) {
4485 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4489 igb_delete_5tuple_filter_82576(dev, filter);
4495 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4498 struct e1000_hw *hw;
4499 struct rte_eth_dev_info dev_info;
4500 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4503 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505 #ifdef RTE_LIBRTE_82571_SUPPORT
4506 /* XXX: not bigger than max_rx_pktlen */
4507 if (hw->mac.type == e1000_82571)
4510 ret = eth_igb_infos_get(dev, &dev_info);
4514 /* check that mtu is within the allowed range */
4515 if (mtu < RTE_ETHER_MIN_MTU ||
4516 frame_size > dev_info.max_rx_pktlen)
4519 /* refuse mtu that requires the support of scattered packets when this
4520 * feature has not been enabled before. */
4521 if (!dev->data->scattered_rx &&
4522 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4525 rctl = E1000_READ_REG(hw, E1000_RCTL);
4527 /* switch to jumbo mode if needed */
4528 if (frame_size > RTE_ETHER_MAX_LEN) {
4529 dev->data->dev_conf.rxmode.offloads |=
4530 DEV_RX_OFFLOAD_JUMBO_FRAME;
4531 rctl |= E1000_RCTL_LPE;
4533 dev->data->dev_conf.rxmode.offloads &=
4534 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4535 rctl &= ~E1000_RCTL_LPE;
4537 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4539 /* update max frame size */
4540 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4542 E1000_WRITE_REG(hw, E1000_RLPML,
4543 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4549 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4552 * dev: Pointer to struct rte_eth_dev.
4553 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4554 * add: if true, add filter, if false, remove filter
4557 * - On success, zero.
4558 * - On failure, a negative value.
4561 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4562 struct rte_eth_ntuple_filter *ntuple_filter,
4565 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4568 switch (ntuple_filter->flags) {
4569 case RTE_5TUPLE_FLAGS:
4570 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4571 if (hw->mac.type != e1000_82576)
4574 ret = igb_add_5tuple_filter_82576(dev,
4577 ret = igb_remove_5tuple_filter_82576(dev,
4580 case RTE_2TUPLE_FLAGS:
4581 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4582 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4583 hw->mac.type != e1000_i210 &&
4584 hw->mac.type != e1000_i211)
4587 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4589 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4600 * igb_get_ntuple_filter - get a ntuple filter
4603 * dev: Pointer to struct rte_eth_dev.
4604 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4607 * - On success, zero.
4608 * - On failure, a negative value.
4611 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4612 struct rte_eth_ntuple_filter *ntuple_filter)
4614 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4615 struct e1000_filter_info *filter_info =
4616 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4617 struct e1000_5tuple_filter_info filter_5tuple;
4618 struct e1000_2tuple_filter_info filter_2tuple;
4619 struct e1000_5tuple_filter *p_5tuple_filter;
4620 struct e1000_2tuple_filter *p_2tuple_filter;
4623 switch (ntuple_filter->flags) {
4624 case RTE_5TUPLE_FLAGS:
4625 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4626 if (hw->mac.type != e1000_82576)
4628 memset(&filter_5tuple,
4630 sizeof(struct e1000_5tuple_filter_info));
4631 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4635 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4636 &filter_info->fivetuple_list,
4638 if (p_5tuple_filter == NULL) {
4639 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4642 ntuple_filter->queue = p_5tuple_filter->queue;
4644 case RTE_2TUPLE_FLAGS:
4645 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4646 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4648 memset(&filter_2tuple,
4650 sizeof(struct e1000_2tuple_filter_info));
4651 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4654 p_2tuple_filter = igb_2tuple_filter_lookup(
4655 &filter_info->twotuple_list,
4657 if (p_2tuple_filter == NULL) {
4658 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4661 ntuple_filter->queue = p_2tuple_filter->queue;
4672 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4673 * @dev: pointer to rte_eth_dev structure
4674 * @filter_op:operation will be taken.
4675 * @arg: a pointer to specific structure corresponding to the filter_op
4678 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4679 enum rte_filter_op filter_op,
4682 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685 MAC_TYPE_FILTER_SUP(hw->mac.type);
4687 if (filter_op == RTE_ETH_FILTER_NOP)
4691 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4696 switch (filter_op) {
4697 case RTE_ETH_FILTER_ADD:
4698 ret = igb_add_del_ntuple_filter(dev,
4699 (struct rte_eth_ntuple_filter *)arg,
4702 case RTE_ETH_FILTER_DELETE:
4703 ret = igb_add_del_ntuple_filter(dev,
4704 (struct rte_eth_ntuple_filter *)arg,
4707 case RTE_ETH_FILTER_GET:
4708 ret = igb_get_ntuple_filter(dev,
4709 (struct rte_eth_ntuple_filter *)arg);
4712 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4720 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4725 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4726 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4727 (filter_info->ethertype_mask & (1 << i)))
4734 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4735 uint16_t ethertype, uint32_t etqf)
4739 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4740 if (!(filter_info->ethertype_mask & (1 << i))) {
4741 filter_info->ethertype_mask |= 1 << i;
4742 filter_info->ethertype_filters[i].ethertype = ethertype;
4743 filter_info->ethertype_filters[i].etqf = etqf;
4751 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4754 if (idx >= E1000_MAX_ETQF_FILTERS)
4756 filter_info->ethertype_mask &= ~(1 << idx);
4757 filter_info->ethertype_filters[idx].ethertype = 0;
4758 filter_info->ethertype_filters[idx].etqf = 0;
4764 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4765 struct rte_eth_ethertype_filter *filter,
4768 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4769 struct e1000_filter_info *filter_info =
4770 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4774 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4775 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4776 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4777 " ethertype filter.", filter->ether_type);
4781 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4782 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4785 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4786 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4790 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4791 if (ret >= 0 && add) {
4792 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4793 filter->ether_type);
4796 if (ret < 0 && !add) {
4797 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4798 filter->ether_type);
4803 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4804 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4805 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4806 ret = igb_ethertype_filter_insert(filter_info,
4807 filter->ether_type, etqf);
4809 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4813 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4817 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4818 E1000_WRITE_FLUSH(hw);
4824 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4825 struct rte_eth_ethertype_filter *filter)
4827 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828 struct e1000_filter_info *filter_info =
4829 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4833 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4835 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4836 filter->ether_type);
4840 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4841 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4842 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4844 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4845 E1000_ETQF_QUEUE_SHIFT;
4853 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4854 * @dev: pointer to rte_eth_dev structure
4855 * @filter_op:operation will be taken.
4856 * @arg: a pointer to specific structure corresponding to the filter_op
4859 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4860 enum rte_filter_op filter_op,
4863 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4866 MAC_TYPE_FILTER_SUP(hw->mac.type);
4868 if (filter_op == RTE_ETH_FILTER_NOP)
4872 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4877 switch (filter_op) {
4878 case RTE_ETH_FILTER_ADD:
4879 ret = igb_add_del_ethertype_filter(dev,
4880 (struct rte_eth_ethertype_filter *)arg,
4883 case RTE_ETH_FILTER_DELETE:
4884 ret = igb_add_del_ethertype_filter(dev,
4885 (struct rte_eth_ethertype_filter *)arg,
4888 case RTE_ETH_FILTER_GET:
4889 ret = igb_get_ethertype_filter(dev,
4890 (struct rte_eth_ethertype_filter *)arg);
4893 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4901 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4902 enum rte_filter_type filter_type,
4903 enum rte_filter_op filter_op,
4908 switch (filter_type) {
4909 case RTE_ETH_FILTER_NTUPLE:
4910 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4912 case RTE_ETH_FILTER_ETHERTYPE:
4913 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4915 case RTE_ETH_FILTER_SYN:
4916 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4918 case RTE_ETH_FILTER_FLEXIBLE:
4919 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4921 case RTE_ETH_FILTER_GENERIC:
4922 if (filter_op != RTE_ETH_FILTER_GET)
4924 *(const void **)arg = &igb_flow_ops;
4927 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4936 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4937 struct rte_ether_addr *mc_addr_set,
4938 uint32_t nb_mc_addr)
4940 struct e1000_hw *hw;
4942 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4948 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4950 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4951 uint64_t systime_cycles;
4953 switch (hw->mac.type) {
4957 * Need to read System Time Residue Register to be able
4958 * to read the other two registers.
4960 E1000_READ_REG(hw, E1000_SYSTIMR);
4961 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4962 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4963 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4970 * Need to read System Time Residue Register to be able
4971 * to read the other two registers.
4973 E1000_READ_REG(hw, E1000_SYSTIMR);
4974 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4975 /* Only the 8 LSB are valid. */
4976 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4980 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4981 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4986 return systime_cycles;
4990 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4992 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4993 uint64_t rx_tstamp_cycles;
4995 switch (hw->mac.type) {
4998 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4999 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5000 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5006 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5007 /* Only the 8 LSB are valid. */
5008 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5012 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5013 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5018 return rx_tstamp_cycles;
5022 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5024 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5025 uint64_t tx_tstamp_cycles;
5027 switch (hw->mac.type) {
5030 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5031 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5032 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5038 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5039 /* Only the 8 LSB are valid. */
5040 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5044 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5045 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5050 return tx_tstamp_cycles;
5054 igb_start_timecounters(struct rte_eth_dev *dev)
5056 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057 struct e1000_adapter *adapter = dev->data->dev_private;
5058 uint32_t incval = 1;
5060 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5062 switch (hw->mac.type) {
5066 /* 32 LSB bits + 8 MSB bits = 40 bits */
5067 mask = (1ULL << 40) - 1;
5072 * Start incrementing the register
5073 * used to timestamp PTP packets.
5075 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5078 incval = E1000_INCVALUE_82576;
5079 shift = IGB_82576_TSYNC_SHIFT;
5080 E1000_WRITE_REG(hw, E1000_TIMINCA,
5081 E1000_INCPERIOD_82576 | incval);
5088 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5089 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5090 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5092 adapter->systime_tc.cc_mask = mask;
5093 adapter->systime_tc.cc_shift = shift;
5094 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5096 adapter->rx_tstamp_tc.cc_mask = mask;
5097 adapter->rx_tstamp_tc.cc_shift = shift;
5098 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5100 adapter->tx_tstamp_tc.cc_mask = mask;
5101 adapter->tx_tstamp_tc.cc_shift = shift;
5102 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5106 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5108 struct e1000_adapter *adapter = dev->data->dev_private;
5110 adapter->systime_tc.nsec += delta;
5111 adapter->rx_tstamp_tc.nsec += delta;
5112 adapter->tx_tstamp_tc.nsec += delta;
5118 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5121 struct e1000_adapter *adapter = dev->data->dev_private;
5123 ns = rte_timespec_to_ns(ts);
5125 /* Set the timecounters to a new value. */
5126 adapter->systime_tc.nsec = ns;
5127 adapter->rx_tstamp_tc.nsec = ns;
5128 adapter->tx_tstamp_tc.nsec = ns;
5134 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5136 uint64_t ns, systime_cycles;
5137 struct e1000_adapter *adapter = dev->data->dev_private;
5139 systime_cycles = igb_read_systime_cyclecounter(dev);
5140 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5141 *ts = rte_ns_to_timespec(ns);
5147 igb_timesync_enable(struct rte_eth_dev *dev)
5149 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5153 /* Stop the timesync system time. */
5154 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5155 /* Reset the timesync system time value. */
5156 switch (hw->mac.type) {
5162 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5165 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5166 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5169 /* Not supported. */
5173 /* Enable system time for it isn't on by default. */
5174 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5175 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5176 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5178 igb_start_timecounters(dev);
5180 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5181 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5182 (RTE_ETHER_TYPE_1588 |
5183 E1000_ETQF_FILTER_ENABLE |
5186 /* Enable timestamping of received PTP packets. */
5187 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5188 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5189 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5191 /* Enable Timestamping of transmitted PTP packets. */
5192 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5193 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5194 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5200 igb_timesync_disable(struct rte_eth_dev *dev)
5202 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205 /* Disable timestamping of transmitted PTP packets. */
5206 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5207 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5208 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5210 /* Disable timestamping of received PTP packets. */
5211 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5212 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5213 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5215 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5216 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5218 /* Stop incrementating the System Time registers. */
5219 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5225 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5226 struct timespec *timestamp,
5227 uint32_t flags __rte_unused)
5229 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5230 struct e1000_adapter *adapter = dev->data->dev_private;
5231 uint32_t tsync_rxctl;
5232 uint64_t rx_tstamp_cycles;
5235 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5236 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5239 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5240 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5241 *timestamp = rte_ns_to_timespec(ns);
5247 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5248 struct timespec *timestamp)
5250 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251 struct e1000_adapter *adapter = dev->data->dev_private;
5252 uint32_t tsync_txctl;
5253 uint64_t tx_tstamp_cycles;
5256 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5257 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5260 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5261 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5262 *timestamp = rte_ns_to_timespec(ns);
5268 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5272 const struct reg_info *reg_group;
5274 while ((reg_group = igb_regs[g_ind++]))
5275 count += igb_reg_group_count(reg_group);
5281 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5285 const struct reg_info *reg_group;
5287 while ((reg_group = igbvf_regs[g_ind++]))
5288 count += igb_reg_group_count(reg_group);
5294 eth_igb_get_regs(struct rte_eth_dev *dev,
5295 struct rte_dev_reg_info *regs)
5297 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5298 uint32_t *data = regs->data;
5301 const struct reg_info *reg_group;
5304 regs->length = eth_igb_get_reg_length(dev);
5305 regs->width = sizeof(uint32_t);
5309 /* Support only full register dump */
5310 if ((regs->length == 0) ||
5311 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5312 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5314 while ((reg_group = igb_regs[g_ind++]))
5315 count += igb_read_regs_group(dev, &data[count],
5324 igbvf_get_regs(struct rte_eth_dev *dev,
5325 struct rte_dev_reg_info *regs)
5327 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5328 uint32_t *data = regs->data;
5331 const struct reg_info *reg_group;
5334 regs->length = igbvf_get_reg_length(dev);
5335 regs->width = sizeof(uint32_t);
5339 /* Support only full register dump */
5340 if ((regs->length == 0) ||
5341 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5342 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5344 while ((reg_group = igbvf_regs[g_ind++]))
5345 count += igb_read_regs_group(dev, &data[count],
5354 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5356 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5358 /* Return unit is byte count */
5359 return hw->nvm.word_size * 2;
5363 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5364 struct rte_dev_eeprom_info *in_eeprom)
5366 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5367 struct e1000_nvm_info *nvm = &hw->nvm;
5368 uint16_t *data = in_eeprom->data;
5371 first = in_eeprom->offset >> 1;
5372 length = in_eeprom->length >> 1;
5373 if ((first >= hw->nvm.word_size) ||
5374 ((first + length) >= hw->nvm.word_size))
5377 in_eeprom->magic = hw->vendor_id |
5378 ((uint32_t)hw->device_id << 16);
5380 if ((nvm->ops.read) == NULL)
5383 return nvm->ops.read(hw, first, length, data);
5387 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5388 struct rte_dev_eeprom_info *in_eeprom)
5390 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5391 struct e1000_nvm_info *nvm = &hw->nvm;
5392 uint16_t *data = in_eeprom->data;
5395 first = in_eeprom->offset >> 1;
5396 length = in_eeprom->length >> 1;
5397 if ((first >= hw->nvm.word_size) ||
5398 ((first + length) >= hw->nvm.word_size))
5401 in_eeprom->magic = (uint32_t)hw->vendor_id |
5402 ((uint32_t)hw->device_id << 16);
5404 if ((nvm->ops.write) == NULL)
5406 return nvm->ops.write(hw, first, length, data);
5410 eth_igb_get_module_info(struct rte_eth_dev *dev,
5411 struct rte_eth_dev_module_info *modinfo)
5413 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5415 uint32_t status = 0;
5416 uint16_t sff8472_rev, addr_mode;
5417 bool page_swap = false;
5419 if (hw->phy.media_type == e1000_media_type_copper ||
5420 hw->phy.media_type == e1000_media_type_unknown)
5423 /* Check whether we support SFF-8472 or not */
5424 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5428 /* addressing mode is not supported */
5429 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5433 /* addressing mode is not supported */
5434 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5436 "Address change required to access page 0xA2, "
5437 "but not supported. Please report the module "
5438 "type to the driver maintainers.\n");
5442 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5443 /* We have an SFP, but it does not support SFF-8472 */
5444 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5445 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5447 /* We have an SFP which supports a revision of SFF-8472 */
5448 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5449 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5456 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5457 struct rte_dev_eeprom_info *info)
5459 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5461 uint32_t status = 0;
5462 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5463 u16 first_word, last_word;
5466 if (info->length == 0)
5469 first_word = info->offset >> 1;
5470 last_word = (info->offset + info->length - 1) >> 1;
5472 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5473 for (i = 0; i < last_word - first_word + 1; i++) {
5474 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5477 /* Error occurred while reading module */
5481 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5484 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5490 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5492 struct e1000_hw *hw =
5493 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5494 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5495 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5496 uint32_t vec = E1000_MISC_VEC_ID;
5498 if (rte_intr_allow_others(intr_handle))
5499 vec = E1000_RX_VEC_START;
5501 uint32_t mask = 1 << (queue_id + vec);
5503 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5504 E1000_WRITE_FLUSH(hw);
5510 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5512 struct e1000_hw *hw =
5513 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5514 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5515 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5516 uint32_t vec = E1000_MISC_VEC_ID;
5518 if (rte_intr_allow_others(intr_handle))
5519 vec = E1000_RX_VEC_START;
5521 uint32_t mask = 1 << (queue_id + vec);
5524 regval = E1000_READ_REG(hw, E1000_EIMS);
5525 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5526 E1000_WRITE_FLUSH(hw);
5528 rte_intr_ack(intr_handle);
5534 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5535 uint8_t index, uint8_t offset)
5537 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5540 val &= ~((uint32_t)0xFF << offset);
5542 /* write vector and valid bit */
5543 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5545 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5549 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5550 uint8_t queue, uint8_t msix_vector)
5554 if (hw->mac.type == e1000_82575) {
5556 tmp = E1000_EICR_RX_QUEUE0 << queue;
5557 else if (direction == 1)
5558 tmp = E1000_EICR_TX_QUEUE0 << queue;
5559 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5560 } else if (hw->mac.type == e1000_82576) {
5561 if ((direction == 0) || (direction == 1))
5562 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5563 ((queue & 0x8) << 1) +
5565 } else if ((hw->mac.type == e1000_82580) ||
5566 (hw->mac.type == e1000_i350) ||
5567 (hw->mac.type == e1000_i354) ||
5568 (hw->mac.type == e1000_i210) ||
5569 (hw->mac.type == e1000_i211)) {
5570 if ((direction == 0) || (direction == 1))
5571 eth_igb_write_ivar(hw, msix_vector,
5573 ((queue & 0x1) << 4) +
5578 /* Sets up the hardware to generate MSI-X interrupts properly
5580 * board private structure
5583 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5586 uint32_t tmpval, regval, intr_mask;
5587 struct e1000_hw *hw =
5588 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5589 uint32_t vec = E1000_MISC_VEC_ID;
5590 uint32_t base = E1000_MISC_VEC_ID;
5591 uint32_t misc_shift = 0;
5592 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5593 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5595 /* won't configure msix register if no mapping is done
5596 * between intr vector and event fd
5598 if (!rte_intr_dp_is_en(intr_handle))
5601 if (rte_intr_allow_others(intr_handle)) {
5602 vec = base = E1000_RX_VEC_START;
5606 /* set interrupt vector for other causes */
5607 if (hw->mac.type == e1000_82575) {
5608 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5609 /* enable MSI-X PBA support */
5610 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5612 /* Auto-Mask interrupts upon ICR read */
5613 tmpval |= E1000_CTRL_EXT_EIAME;
5614 tmpval |= E1000_CTRL_EXT_IRCA;
5616 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5618 /* enable msix_other interrupt */
5619 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5620 regval = E1000_READ_REG(hw, E1000_EIAC);
5621 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5622 regval = E1000_READ_REG(hw, E1000_EIAM);
5623 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5624 } else if ((hw->mac.type == e1000_82576) ||
5625 (hw->mac.type == e1000_82580) ||
5626 (hw->mac.type == e1000_i350) ||
5627 (hw->mac.type == e1000_i354) ||
5628 (hw->mac.type == e1000_i210) ||
5629 (hw->mac.type == e1000_i211)) {
5630 /* turn on MSI-X capability first */
5631 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5632 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5634 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5637 if (dev->data->dev_conf.intr_conf.lsc != 0)
5638 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5640 regval = E1000_READ_REG(hw, E1000_EIAC);
5641 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5643 /* enable msix_other interrupt */
5644 regval = E1000_READ_REG(hw, E1000_EIMS);
5645 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5646 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5647 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5650 /* use EIAM to auto-mask when MSI-X interrupt
5651 * is asserted, this saves a register write for every interrupt
5653 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5656 if (dev->data->dev_conf.intr_conf.lsc != 0)
5657 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5659 regval = E1000_READ_REG(hw, E1000_EIAM);
5660 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5662 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5663 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5664 intr_handle->intr_vec[queue_id] = vec;
5665 if (vec < base + intr_handle->nb_efd - 1)
5669 E1000_WRITE_FLUSH(hw);
5672 /* restore n-tuple filter */
5674 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5676 struct e1000_filter_info *filter_info =
5677 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5678 struct e1000_5tuple_filter *p_5tuple;
5679 struct e1000_2tuple_filter *p_2tuple;
5681 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5682 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5685 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5686 igb_inject_2uple_filter(dev, p_2tuple);
5690 /* restore SYN filter */
5692 igb_syn_filter_restore(struct rte_eth_dev *dev)
5694 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695 struct e1000_filter_info *filter_info =
5696 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5699 synqf = filter_info->syn_info;
5701 if (synqf & E1000_SYN_FILTER_ENABLE) {
5702 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5703 E1000_WRITE_FLUSH(hw);
5707 /* restore ethernet type filter */
5709 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5711 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5712 struct e1000_filter_info *filter_info =
5713 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5716 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5717 if (filter_info->ethertype_mask & (1 << i)) {
5718 E1000_WRITE_REG(hw, E1000_ETQF(i),
5719 filter_info->ethertype_filters[i].etqf);
5720 E1000_WRITE_FLUSH(hw);
5725 /* restore flex byte filter */
5727 igb_flex_filter_restore(struct rte_eth_dev *dev)
5729 struct e1000_filter_info *filter_info =
5730 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5731 struct e1000_flex_filter *flex_filter;
5733 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5734 igb_inject_flex_filter(dev, flex_filter);
5738 /* restore rss filter */
5740 igb_rss_filter_restore(struct rte_eth_dev *dev)
5742 struct e1000_filter_info *filter_info =
5743 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5745 if (filter_info->rss_info.conf.queue_num)
5746 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5749 /* restore all types filter */
5751 igb_filter_restore(struct rte_eth_dev *dev)
5753 igb_ntuple_filter_restore(dev);
5754 igb_ethertype_filter_restore(dev);
5755 igb_syn_filter_restore(dev);
5756 igb_flex_filter_restore(dev);
5757 igb_rss_filter_restore(dev);
5762 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5763 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5764 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5765 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5766 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5767 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5769 /* see e1000_logs.c */
5770 RTE_INIT(e1000_init_log)
5772 e1000_igb_init_log();